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* GeneralLeonard Kugis2019-11-191-528/+528
| | | | Removed too many test points.
* Schematic, generalLeonard Kugis2019-11-131-0/+17
| | | | | Added test points everywhere neccessary. Added missing pull resistors to guarantee a defined state everywhere.
* Schematic, UARTLeonard Kugis2019-11-131-0/+20
| | | | Added connectors for UART access.
* Schematic, mainLeonard Kugis2019-11-131-13/+28
| | | | | | Added pull resistors to every pin of uC. Restructured main schematic. Added ISP interface.
* Schematic, main, generalLeonard Kugis2019-11-131-26/+74
| | | | | | Added pull resistors to all ports. Added capacitors for all components to prevent high switching currents. Reordered status LEDs and transistors.
* Schematic, StatusLeonard Kugis2019-11-071-0/+19
| | | | Separated logic IO from power with transistors.
* Schematic, JTAGLeonard Kugis2019-11-071-0/+35
| | | | Added JTAG interface.
* Schematic, PinoutLeonard Kugis2019-11-071-374/+374
| | | | | Moved buttons and status interface to Port D to prepare Port C as JTAG interface.
* structure, buttons, statusLeonard Kugis2019-11-041-27/+66
| | | | | | Implemented hierarchy. Added button interface. Added status interface.
* SchematicLeonard Kugis2019-11-031-0/+151
| | | | | | Added Power wirings and connectors. Added 7-segment display output components and wiring to schematic. Added shift registers for button inputs.
* Initial commitLeonard Kugis2019-11-011-0/+184
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-28 17:05:11 +0000