summaryrefslogtreecommitdiffstats
path: root/PinLock.sch
Commit message (Collapse)AuthorAgeFilesLines
* Begin renamingLeonard Kugis2019-11-211-38/+49
|
* UARTLeonard Kugis2019-11-201-1864/+1885
| | | | | Changed UART from 2 to 4 pin connector, connecting GND and VCC additionally.
* GeneralLeonard Kugis2019-11-191-1864/+1864
| | | | Removed too many test points.
* Schematic, mainLeonard Kugis2019-11-131-1/+55
| | | | Added capacitors for subschematics.
* Schematic, generalLeonard Kugis2019-11-131-203/+715
| | | | | Added test points everywhere neccessary. Added missing pull resistors to guarantee a defined state everywhere.
* Schematic, UARTLeonard Kugis2019-11-131-24/+41
| | | | Added connectors for UART access.
* Schematic, mainLeonard Kugis2019-11-131-454/+937
| | | | | | Added pull resistors to every pin of uC. Restructured main schematic. Added ISP interface.
* Schematic, mainLeonard Kugis2019-11-131-30/+59
| | | | | Added capacitor in parallel to reset switch to reduce sensitivity and oscillations.
* Schematic, main, generalLeonard Kugis2019-11-131-72/+458
| | | | | | Added pull resistors to all ports. Added capacitors for all components to prevent high switching currents. Reordered status LEDs and transistors.
* Schematic, JTAGLeonard Kugis2019-11-071-64/+106
| | | | Added JTAG interface.
* Schematic, PinoutLeonard Kugis2019-11-071-341/+341
| | | | | Moved buttons and status interface to Port D to prepare Port C as JTAG interface.
* structure, buttons, statusLeonard Kugis2019-11-041-462/+147
| | | | | | Implemented hierarchy. Added button interface. Added status interface.
* SchematicLeonard Kugis2019-11-031-90/+595
| | | | | | Added Power wirings and connectors. Added 7-segment display output components and wiring to schematic. Added shift registers for button inputs.
* Initial commitLeonard Kugis2019-11-011-0/+151
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-29 17:57:24 +0000