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* Begin associationsLeonard Kugis2019-11-241-3/+3
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* GeneralLeonard Kugis2019-11-241-13/+13
| | | | Added references to all elements.
* UARTLeonard Kugis2019-11-201-200/+200
| | | | | Changed UART from 2 to 4 pin connector, connecting GND and VCC additionally.
* GeneralLeonard Kugis2019-11-191-328/+200
| | | | Removed too many test points.
* Schematic, generalLeonard Kugis2019-11-131-104/+232
| | | | | Added test points everywhere neccessary. Added missing pull resistors to guarantee a defined state everywhere.
* Schematic, main, generalLeonard Kugis2019-11-131-109/+126
| | | | | | Added pull resistors to all ports. Added capacitors for all components to prevent high switching currents. Reordered status LEDs and transistors.
* Schematic, StatusLeonard Kugis2019-11-071-1/+1
| | | | Separated logic IO from power with transistors.
* Schematic, PinoutLeonard Kugis2019-11-071-183/+183
| | | | | Moved buttons and status interface to Port D to prepare Port C as JTAG interface.
* structure, buttons, statusLeonard Kugis2019-11-041-0/+183
Implemented hierarchy. Added button interface. Added status interface.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-29 19:23:37 +0000