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@@ -2,6 +2,13 @@ DRAM Bender is an experimental FPGA-based memory controller design that can be used to develop tests for DDR4 [SO/R/U]DIMMs. DRAM Bender currently supports the *Bittware XUSP3S, XUPP3R, XUPVVH and Xilinx Alveo U200* boards. +<p align="center"> +<img src="images/overview.png" width="512"><br> + <em>An example DRAM Bender prototype.</em> +</p> + + + DRAM Bender is the next version of the [SoftMC memory testing infrastructure](https://github.com/CMU-SAFARI/SoftMC). DRAM Bender introduces general purpose registers and a brand new DRAM Bender ISA to provide a programmable memory controller. We provide a) prebuilt binaries for quick installation and b) the source code (both in Verilog and C++) that you can modify as you wish. @@ -10,21 +17,26 @@ We provide a) prebuilt binaries for quick installation and b) the source code (b Please cite the following paper if you find DRAM Bender useful: -A. Olgun, H. Hassan, A. G. Yaglikci, Y. C. Tugrul, L. Orosa, H. Luo, M. Patel, O. Ergin, O. Mutlu, "DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips," arXiv:2211.05838, Mar 2022 +[A. Olgun, H. Hassan, A. G. Yaglikci, Y. C. Tugrul, L. Orosa, H. Luo, M. Patel, O. Ergin, O. Mutlu, "DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips", IEEE TCAD, June 2023.](https://ieeexplore.ieee.org/document/10141996) Link to the PDF: https://arxiv.org/pdf/2211.05838.pdf -Link to the abstract: https://arxiv.org/abs/2211.05838 Below is bibtex format for citation. ``` -@misc{olgun2022drambender, +@article{olgun2023drambender, title={{DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips}}, author={Olgun, Ataberk and Hassan, Hasan and Yaglikci, A. Giray and Tugrul, Yahya Can and Orosa, Lois and Luo, Haocong and Patel, Minesh and Ergin, Oguz and Mutlu, Onur}, - year={2022}, - howpublished={arXiv:2211.05838} + year={2023}, + journal={IEEE TCAD} } ``` +## More DRAM Bender Resources + +[DRAM Bender Tutorial Video](https://www.youtube.com/watch?v=FklVEsfdZCI): 43-minute tutorial on how to set up and use DRAM Bender. + +[ETH Projects & Seminars Course on DRAM Bender](https://safari.ethz.ch/projects_and_seminars/spring2023/doku.php?id=softmc) + ## Prior Works that Use DRAM Bender We provide the sources to reproduce the results of two prior work: U-TRR ([PDF](https://people.inf.ethz.ch/omutlu/pub/U-TRR-uncovering-RowHammer-protection-mechanisms_micro21.pdf)) and QUAC-TRNG ([PDF](https://people.inf.ethz.ch/omutlu/pub/QUAC-TRNG-DRAM_isca21.pdf)). @@ -70,7 +82,8 @@ We plan to open source the following prior research works that used DRAM Bender - A Linux Host Machine, (We tested on Ubuntu 16.04, 18.04, 20.04) - DRAM Bender uses an 8-lane PCIe interface to communicate with the Host Machine. So, you would also need to attach the board to the 8x/16x PCIe slot on the motherboard of the Host Machine - One of the four FPGA boards: Bittware XUSP3S, XUPP3R, XUPVVH, Xilinx Alveo U200 - - These boards should be connected to the host machine via a programming cable. Please refer to manufacturer data sheets for more information on how to use the programming cable. + - These boards should be connected to the host machine via a programming cable. Please refer to manufacturer data sheets or user guides (e.g., [this document](https://docs.xilinx.com/r/en-US/ug1289-u200-u250-reconfig-accel) for Alveo U200) for more information on how to use the programming cable. + - Make sure to install the Xilinx Cable Drivers. These drivers are not installed by default in some cases. Follow [this guide](https://docs.xilinx.com/r/2020.2-English/ug973-vivado-release-notes-install-license/Install-Cable-Drivers) to learn how to install cable drivers. - A proper form factor memory attached to your FPGA board - If you want to build your own bitfile from the source: - Xilinx Vivado 2018.2 for the XUSP3S and XUPP3R boards @@ -78,6 +91,7 @@ We plan to open source the following prior research works that used DRAM Bender - Xilinx Vivado 2020.2 for the Alveo U200 board + ### Overview of the Prebuilt Bitstreams We provide a set of bitstreams in the `prebuilt` directory under four directories that contain the bitstreams for a specific FPGA board. @@ -95,8 +109,17 @@ We provide a set of bitstreams in the `prebuilt` directory under four directorie </p> * XUPP3R: We provide three bitstreams for: (1) single rank x4 RDIMMs, (2) dual rank x8 RDIMMs, (3) single rank x8 UDIMMs. + +<p align="center"> +<img src="images/xupp3r.png" width="512"> +</p> + * XUPVVH: We provide a single bitstream for x4 RDIMMs. +<p align="center"> +<img src="images/xupvvh.png" width="512"> +</p> + We provide a script (```prebuild/programFPGA.sh```) that programs the FPGA according to user-specified board, DIMM slot, DIMM type, the number of ranks and the DQ width. Run the script as ```./programFPGA.sh <board> <slot> <dimm_type> <num_rank> <dq_width>``` ### 1) Installing the Xilinx XDMA driver: @@ -170,6 +193,15 @@ You first need to modify the `project.vh` header file according to your DIMMs co From here on you may refer to the installation guide for XUSP3S. +### Testing SODIMMs with the Alveo U200 board (this subsection is work in progress) + +We recommend users who would like to test DDR4 SODIMMs obtain a SODIMM to DIMM adapter and use it on the widely available Alveo U200 board. We have tested the [JET-5608AA](https://www.eztest.com.tw/service_2_detail/46.htm) DDR4 SODIMM to DIMM adapter for this purpose. We suggest you contact the manufacturer directly to purchase the adapter. The Alveo U200 DRAM Bender prototype can test all major DDR4 module form factors/types (UDIMMs, RDIMMs, and SODIMMs) with a SODIMM to DIMM adapter. + +<p align="center"> +<img src="images/sodimm_dimm_adapter.jpg" width="512"><br> + <em>An Alveo U200 board using the SODIMM to DIMM adapter.</em> +</p> + ## Simulating a DRAM Bender Design This section describes how to run a Vivado simulation of the DRAM Bender hardware. diff --git a/images/overview.png b/images/overview.png Binary files differnew file mode 100644 index 0000000..54109a5 --- /dev/null +++ b/images/overview.png diff --git a/images/sodimm_dimm_adapter.jpg b/images/sodimm_dimm_adapter.jpg Binary files differnew file mode 100644 index 0000000..85cb5af --- /dev/null +++ b/images/sodimm_dimm_adapter.jpg diff --git a/images/xupp3r.png b/images/xupp3r.png Binary files differnew file mode 100644 index 0000000..7f94848 --- /dev/null +++ b/images/xupp3r.png diff --git a/images/xupvvh.png b/images/xupvvh.png Binary files differnew file mode 100644 index 0000000..1584347 --- /dev/null +++ b/images/xupvvh.png |
