From 7721980589f4c7fa811689e815a77d63f2556497 Mon Sep 17 00:00:00 2001 From: Ataberk Date: Thu, 2 May 2024 17:22:05 +0200 Subject: Add sources for U50 HBM2 --- prebuilt/XCU50/XCU50_NA_HBM_NA_NA.bit | Bin 0 -> 18157963 bytes projects/U50-HBM/U50-HBM.hw/U50-HBM.lpr | 8 + projects/U50-HBM/U50-HBM.hw/hw_1/hw.xml | 5594 + projects/U50-HBM/U50-HBM.ip_user_files/README.txt | 1 + .../axis_clock_converter/axis_clock_converter.veo | 78 + .../axis_clock_converter/axis_clock_converter.vho | 101 + .../axis_clock_converter_stub.v | 35 + .../axis_clock_converter_stub.vhdl | 43 + .../ip/c_counter_binary_0/c_counter_binary_0.veo | 66 + .../ip/c_counter_binary_0/c_counter_binary_0.vho | 77 + .../U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.veo | 76 + .../U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.vho | 97 + .../ip/cdc_fifo/cdc_fifo_stub.v | 32 + .../ip/cdc_fifo/cdc_fifo_stub.vhdl | 41 + .../ip/clk_wiz_0/clk_wiz_0.veo | 80 + .../ip/clk_wiz_0/clk_wiz_0_stub.v | 21 + .../ip/clk_wiz_0/clk_wiz_0_stub.vhdl | 30 + .../U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.veo | 75 + .../U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.vho | 95 + .../ip/cmd_fifo/cmd_fifo_stub.v | 31 + .../ip/cmd_fifo/cmd_fifo_stub.vhdl | 40 + .../U50-HBM.ip_user_files/ip/hbm_0/hbm_0.veo | 892 + .../U50-HBM.ip_user_files/ip/hbm_0/hbm_0.vho | 1729 + .../U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.v | 1070 + .../U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.vhdl | 857 + .../ip/instr_blk_mem/instr_blk_mem.veo | 70 + .../ip/instr_blk_mem/instr_blk_mem.vho | 85 + .../ip/instr_blk_mem/instr_blk_mem_stub.v | 25 + .../ip/instr_blk_mem/instr_blk_mem_stub.vhdl | 35 + .../ip/instr_blk_mem_sim/instr_blk_mem_sim.veo | 70 + .../ip/instr_blk_mem_sim/instr_blk_mem_sim.vho | 85 + .../ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v | 25 + .../instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl | 35 + .../ip/pr_read_mem/pr_read_mem.veo | 70 + .../ip/pr_read_mem/pr_read_mem.vho | 85 + .../ip/pr_read_mem/pr_read_mem_stub.v | 25 + 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.../ip/zq_calib_mem/zq_calib_mem.veo | 70 + .../ip/zq_calib_mem/zq_calib_mem.vho | 85 + .../ip/zq_calib_mem/zq_calib_mem_stub.v | 25 + .../ip/zq_calib_mem/zq_calib_mem_stub.vhdl | 35 + .../mem_init_files/program.coe | 549 + .../U50-HBM.ip_user_files/mem_init_files/read.coe | 25 + .../U50-HBM.ip_user_files/mem_init_files/ref.coe | 96 + .../U50-HBM.ip_user_files/mem_init_files/zq.coe | 80 + .../U50-HBM.sim/sim_1/behav/questa/compile.log | 79 + .../U50-HBM.sim/sim_1/behav/questa/compile.sh | 20 + .../U50-HBM.sim/sim_1/behav/questa/elaborate.log | 113 + .../U50-HBM.sim/sim_1/behav/questa/elaborate.sh | 20 + .../U50-HBM/U50-HBM.sim/sim_1/behav/questa/glbl.v | 84 + .../sim_1/behav/questa/instr_blk_mem_sim.mif | 547 + .../U50-HBM.sim/sim_1/behav/questa/modelsim.ini | 2705 + .../U50-HBM.sim/sim_1/behav/questa/pr_read.coe | 15 + .../U50-HBM.sim/sim_1/behav/questa/pr_read_mem.mif | 23 + .../U50-HBM.sim/sim_1/behav/questa/pr_ref.coe | 51 + .../U50-HBM.sim/sim_1/behav/questa/pr_ref_mem.mif | 94 + .../U50-HBM.sim/sim_1/behav/questa/pr_zq.coe | 42 + .../U50-HBM.sim/sim_1/behav/questa/program.coe | 549 + .../U50-HBM.sim/sim_1/behav/questa/read.coe | 25 + .../U50-HBM/U50-HBM.sim/sim_1/behav/questa/ref.coe | 96 + .../U50-HBM.sim/sim_1/behav/questa/sim_tb_top.udo | 8 + .../sim_1/behav/questa/sim_tb_top_compile.do | 56 + .../sim_1/behav/questa/sim_tb_top_elaborate.do | 9 + .../sim_1/behav/questa/sim_tb_top_simulate.do | 24 + .../sim_1/behav/questa/sim_tb_top_wave.do | 10 + .../U50-HBM.sim/sim_1/behav/questa/simmem.coe | 398 + .../U50-HBM.sim/sim_1/behav/questa/simulate.log | 534 + .../U50-HBM.sim/sim_1/behav/questa/simulate.sh | 20 + .../U50-HBM.sim/sim_1/behav/questa/vsim.wlf | Bin 0 -> 6643712 bytes .../behav/questa/xpm_internal_config_file_0.mem | 84 + .../behav/questa/xpm_internal_config_file_1.mem | 64 + .../questa/xpm_internal_config_file_sim_0.mem | 84 + .../questa/xpm_internal_config_file_sim_1.mem | 62 + .../U50-HBM/U50-HBM.sim/sim_1/behav/questa/zq.coe | 80 + .../sim_1/behav/questa/zq_calib_mem.mif | 78 + .../U50-HBM/U50-HBM.srcs/sim_1/new/sim_tb_top.v | 43 + .../axis_clock_converter/axis_clock_converter.xci | 133 + .../axis_clock_converter/axis_clock_converter.xml | 1478 + .../ip/c_counter_binary_0/c_counter_binary_0.xci | 109 + .../ip/c_counter_binary_0/c_counter_binary_0.xml | 927 + .../sources_1/ip/cdc_fifo/cdc_fifo.xci | 583 + .../sources_1/ip/cdc_fifo/cdc_fifo.xml | 10810 ++ .../sources_1/ip/clk_wiz_0/clk_wiz_0.xci | 747 + .../sources_1/ip/clk_wiz_0/clk_wiz_0.xml | 4695 + .../sources_1/ip/cmd_fifo/cmd_fifo.xci | 583 + .../sources_1/ip/cmd_fifo/cmd_fifo.xml | 10807 ++ .../U50-HBM.srcs/sources_1/ip/hbm_0/hbm_0.xci | 7676 + .../U50-HBM.srcs/sources_1/ip/hbm_0/hbm_0.xml | 159882 ++++++++++++++++++ .../sources_1/ip/instr_blk_mem/instr_blk_mem.xci | 317 + .../sources_1/ip/instr_blk_mem/instr_blk_mem.xml | 4180 + .../ip/instr_blk_mem_sim/instr_blk_mem_sim.xci | 318 + .../ip/instr_blk_mem_sim/instr_blk_mem_sim.xml | 4181 + .../sources_1/ip/pr_read_mem/pr_read_mem.xci | 318 + .../sources_1/ip/pr_read_mem/pr_read_mem.xml | 4180 + .../sources_1/ip/pr_ref_mem/pr_ref_mem.xci | 318 + .../sources_1/ip/pr_ref_mem/pr_ref_mem.xml | 4181 + .../sources_1/ip/rdback_fifo/rdback_fifo.xci | 580 + .../sources_1/ip/rdback_fifo/rdback_fifo.xml | 10791 ++ .../sources_1/ip/scratchpad/scratchpad.xci | 316 + .../sources_1/ip/scratchpad/scratchpad.xml | 4179 + .../sources_1/ip/wrdata_fifo/wrdata_fifo.xci | 583 + .../sources_1/ip/wrdata_fifo/wrdata_fifo.xml | 10807 ++ .../ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xci | 1433 + .../ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xml | 22837 +++ .../sources_1/ip/xdma/ip_0/xdma_pcie4c_ip.xci | 1642 + .../sources_1/ip/xdma/ip_0/xdma_pcie4c_ip.xml | 31789 ++++ .../ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci | 328 + .../ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xml | 4188 + .../xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci | 328 + .../xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xml | 4188 + .../U50-HBM.srcs/sources_1/ip/xdma/xdma.xci | 2286 + .../U50-HBM.srcs/sources_1/ip/xdma/xdma.xml | 60393 +++++++ .../sources_1/ip/zq_calib_mem/zq_calib_mem.xci | 318 + .../sources_1/ip/zq_calib_mem/zq_calib_mem.xml | 4181 + projects/U50-HBM/U50-HBM.xpr | 1185 + projects/U50-HBM/coe/program.coe | 549 + projects/U50-HBM/coe/read.coe | 25 + projects/U50-HBM/coe/ref.coe | 96 + projects/U50-HBM/coe/zq.coe | 80 + projects/U50-HBM/constraints/HBM.xdc | 1352 + projects/U50-HBM/verilog/HBM_adapter.v | 215 + projects/U50-HBM/verilog/HBM_interface.v | 628 + projects/U50-HBM/verilog/cdc_HBM_to_rbe.v | 88 + projects/U50-HBM/verilog/channel_selector.v | 497 + projects/U50-HBM/verilog/cmd_gen.v | 189 + projects/U50-HBM/verilog/controller_top.v | 2820 + projects/U50-HBM/verilog/project.vh | 27 + projects/U50-HBM/verilog/softmc_top.v | 398 + sources/api/board.cpp | 20 +- sources/api/board.h | 3 +- sources/api/instruction.cpp | 76 +- sources/api/instruction.h | 41 +- sources/api/platform.cpp | 64 +- sources/api/platform.h | 5 + sources/apps/Smalltest_HBM/.gitignore | 1 + sources/apps/Smalltest_HBM/Makefile | 32 + sources/apps/Smalltest_HBM/read_write.cpp | 304 + sources/hdl/header_verilog/encoding.vh | 10 +- sources/hdl/header_verilog/parameters.vh | 3 +- sources/hdl/verilog/ddr_pipeline.v | 83 +- sources/hdl/verilog/decode_stage.v | 18 + sources/hdl/verilog/dll_toggler.v | 34 +- sources/hdl/verilog/execute_stage.v | 38 +- sources/hdl/verilog/frontend.v | 24 + sources/hdl/verilog/maintenance_controller.v | 12 +- sources/hdl/verilog/readback_engine.v | 31 +- sources/hdl/verilog/softmc_pipeline.v | 38 +- 167 files changed, 406485 insertions(+), 155 deletions(-) create mode 100644 prebuilt/XCU50/XCU50_NA_HBM_NA_NA.bit create mode 100644 projects/U50-HBM/U50-HBM.hw/U50-HBM.lpr create mode 100644 projects/U50-HBM/U50-HBM.hw/hw_1/hw.xml create mode 100644 projects/U50-HBM/U50-HBM.ip_user_files/README.txt create mode 100755 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/README.txt b/projects/U50-HBM/U50-HBM.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo new file mode 100755 index 0000000..84a68ee --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo @@ -0,0 +1,78 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axis_clock_converter:1.1 +// IP Revision: 23 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axis_clock_converter your_instance_name ( + .s_axis_aresetn(s_axis_aresetn), // input wire s_axis_aresetn + .m_axis_aresetn(m_axis_aresetn), // input wire m_axis_aresetn + .s_axis_aclk(s_axis_aclk), // input wire s_axis_aclk + .s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid + .s_axis_tready(s_axis_tready), // output wire s_axis_tready + .s_axis_tdata(s_axis_tdata), // input wire [255 : 0] s_axis_tdata + .s_axis_tkeep(s_axis_tkeep), // input wire [31 : 0] s_axis_tkeep + .s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast + .m_axis_aclk(m_axis_aclk), // input wire m_axis_aclk + .m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid + .m_axis_tready(m_axis_tready), // input wire m_axis_tready + .m_axis_tdata(m_axis_tdata), // output wire [255 : 0] m_axis_tdata + .m_axis_tkeep(m_axis_tkeep), // output wire [31 : 0] m_axis_tkeep + .m_axis_tlast(m_axis_tlast) // output wire m_axis_tlast +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axis_clock_converter.v when simulating +// the core, axis_clock_converter. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho new file mode 100755 index 0000000..62fdd7b --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho @@ -0,0 +1,101 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axis_clock_converter:1.1 +-- IP Revision: 23 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axis_clock_converter + PORT ( + s_axis_aresetn : IN STD_LOGIC; + m_axis_aresetn : IN STD_LOGIC; + s_axis_aclk : IN STD_LOGIC; + s_axis_tvalid : IN STD_LOGIC; + s_axis_tready : OUT STD_LOGIC; + s_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + s_axis_tkeep : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_tlast : IN STD_LOGIC; + m_axis_aclk : IN STD_LOGIC; + m_axis_tvalid : OUT STD_LOGIC; + m_axis_tready : IN STD_LOGIC; + m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + m_axis_tkeep : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_tlast : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axis_clock_converter + PORT MAP ( + s_axis_aresetn => s_axis_aresetn, + m_axis_aresetn => m_axis_aresetn, + s_axis_aclk => s_axis_aclk, + s_axis_tvalid => s_axis_tvalid, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata, + s_axis_tkeep => s_axis_tkeep, + s_axis_tlast => s_axis_tlast, + m_axis_aclk => m_axis_aclk, + m_axis_tvalid => m_axis_tvalid, + m_axis_tready => m_axis_tready, + m_axis_tdata => m_axis_tdata, + m_axis_tkeep => m_axis_tkeep, + m_axis_tlast => m_axis_tlast + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axis_clock_converter.vhd when simulating +-- the core, axis_clock_converter. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v new file mode 100644 index 0000000..b09eff7 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v @@ -0,0 +1,35 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:06 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter_stub.v +// Design : axis_clock_converter +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "axis_clock_converter_v1_1_23_axis_clock_converter,Vivado 2020.2" *) +module axis_clock_converter(s_axis_aresetn, m_axis_aresetn, s_axis_aclk, + s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tkeep, s_axis_tlast, m_axis_aclk, + m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tlast) +/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,m_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[255:0],s_axis_tkeep[31:0],s_axis_tlast,m_axis_aclk,m_axis_tvalid,m_axis_tready,m_axis_tdata[255:0],m_axis_tkeep[31:0],m_axis_tlast" */; + input s_axis_aresetn; + input m_axis_aresetn; + input s_axis_aclk; + input s_axis_tvalid; + output s_axis_tready; + input [255:0]s_axis_tdata; + input [31:0]s_axis_tkeep; + input s_axis_tlast; + input m_axis_aclk; + output m_axis_tvalid; + input m_axis_tready; + output [255:0]m_axis_tdata; + output [31:0]m_axis_tkeep; + output m_axis_tlast; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl new file mode 100644 index 0000000..7b85852 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl @@ -0,0 +1,43 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:06 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter_stub.vhdl +-- Design : axis_clock_converter +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity axis_clock_converter is + Port ( + s_axis_aresetn : in STD_LOGIC; + m_axis_aresetn : in STD_LOGIC; + s_axis_aclk : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + s_axis_tkeep : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axis_tlast : in STD_LOGIC; + m_axis_aclk : in STD_LOGIC; + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); + m_axis_tkeep : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axis_tlast : out STD_LOGIC + ); + +end axis_clock_converter; + +architecture stub of axis_clock_converter is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,m_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[255:0],s_axis_tkeep[31:0],s_axis_tlast,m_axis_aclk,m_axis_tvalid,m_axis_tready,m_axis_tdata[255:0],m_axis_tkeep[31:0],m_axis_tlast"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "axis_clock_converter_v1_1_23_axis_clock_converter,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.veo new file mode 100755 index 0000000..3624678 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.veo @@ -0,0 +1,66 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:c_counter_binary:12.0 +// IP Revision: 14 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +c_counter_binary_0 your_instance_name ( + .CLK(CLK), // input wire CLK + .Q(Q) // output wire [15 : 0] Q +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file c_counter_binary_0.v when simulating +// the core, c_counter_binary_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.vho new file mode 100755 index 0000000..1bb607b --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.vho @@ -0,0 +1,77 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:c_counter_binary:12.0 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT c_counter_binary_0 + PORT ( + CLK : IN STD_LOGIC; + Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : c_counter_binary_0 + PORT MAP ( + CLK => CLK, + Q => Q + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file c_counter_binary_0.vhd when simulating +-- the core, c_counter_binary_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.veo new file mode 100755 index 0000000..eacc00d --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.veo @@ -0,0 +1,76 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +cdc_fifo your_instance_name ( + .srst(srst), // input wire srst + .wr_clk(wr_clk), // input wire wr_clk + .rd_clk(rd_clk), // input wire rd_clk + .din(din), // input wire [511 : 0] din + .wr_en(wr_en), // input wire wr_en + .rd_en(rd_en), // input wire rd_en + .dout(dout), // output wire [511 : 0] dout + .full(full), // output wire full + .empty(empty), // output wire empty + .valid(valid), // output wire valid + .wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy + .rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file cdc_fifo.v when simulating +// the core, cdc_fifo. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.vho new file mode 100755 index 0000000..1f0fb6a --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.vho @@ -0,0 +1,97 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fifo_generator:13.2 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT cdc_fifo + PORT ( + srst : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + valid : OUT STD_LOGIC; + wr_rst_busy : OUT STD_LOGIC; + rd_rst_busy : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : cdc_fifo + PORT MAP ( + srst => srst, + wr_clk => wr_clk, + rd_clk => rd_clk, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty, + valid => valid, + wr_rst_busy => wr_rst_busy, + rd_rst_busy => rd_rst_busy + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file cdc_fifo.vhd when simulating +-- the core, cdc_fifo. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.v new file mode 100644 index 0000000..5c3839f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.v @@ -0,0 +1,32 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:09 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cdc_fifo/cdc_fifo_stub.v +// Design : cdc_fifo +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *) +module cdc_fifo(srst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, + empty, valid, wr_rst_busy, rd_rst_busy) +/* synthesis syn_black_box black_box_pad_pin="srst,wr_clk,rd_clk,din[511:0],wr_en,rd_en,dout[511:0],full,empty,valid,wr_rst_busy,rd_rst_busy" */; + input srst; + input wr_clk; + input rd_clk; + input [511:0]din; + input wr_en; + input rd_en; + output [511:0]dout; + output full; + output empty; + output valid; + output wr_rst_busy; + output rd_rst_busy; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.vhdl new file mode 100644 index 0000000..a6cd581 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.vhdl @@ -0,0 +1,41 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:09 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cdc_fifo/cdc_fifo_stub.vhdl +-- Design : cdc_fifo +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity cdc_fifo is + Port ( + srst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 511 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 511 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + valid : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC + ); + +end cdc_fifo; + +architecture stub of cdc_fifo is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "srst,wr_clk,rd_clk,din[511:0],wr_en,rd_en,dout[511:0],full,empty,valid,wr_rst_busy,rd_rst_busy"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo new file mode 100755 index 0000000..e02f568 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo @@ -0,0 +1,80 @@ + +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_150MHz__150.00000______0.000______50.0______127.220____105.461 +// clk_300MHz__300.00000______0.000______50.0______111.879____105.461 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clk_wiz_0 instance_name + ( + // Clock out ports + .clk_150MHz(clk_150MHz), // output clk_150MHz + .clk_300MHz(clk_300MHz), // output clk_300MHz + // Clock in ports + .clk_in1(clk_in1)); // input clk_in1 + +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100644 index 0000000..4a2e0b1 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,21 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:07 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module clk_wiz_0(clk_150MHz, clk_300MHz, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="clk_150MHz,clk_300MHz,clk_in1" */; + output clk_150MHz; + output clk_300MHz; + input clk_in1; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..0cc7f9e --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,30 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:07 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + clk_150MHz : out STD_LOGIC; + clk_300MHz : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + +end clk_wiz_0; + +architecture stub of clk_wiz_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_150MHz,clk_300MHz,clk_in1"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.veo new file mode 100755 index 0000000..4a0a893 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.veo @@ -0,0 +1,75 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +cmd_fifo your_instance_name ( + .srst(srst), // input wire srst + .wr_clk(wr_clk), // input wire wr_clk + .rd_clk(rd_clk), // input wire rd_clk + .din(din), // input wire [127 : 0] din + .wr_en(wr_en), // input wire wr_en + .rd_en(rd_en), // input wire rd_en + .dout(dout), // output wire [63 : 0] dout + .full(full), // output wire full + .empty(empty), // output wire empty + .wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy + .rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file cmd_fifo.v when simulating +// the core, cmd_fifo. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.vho new file mode 100755 index 0000000..3dedecb --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.vho @@ -0,0 +1,95 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fifo_generator:13.2 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT cmd_fifo + PORT ( + srst : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + wr_rst_busy : OUT STD_LOGIC; + rd_rst_busy : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : cmd_fifo + PORT MAP ( + srst => srst, + wr_clk => wr_clk, + rd_clk => rd_clk, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty, + wr_rst_busy => wr_rst_busy, + rd_rst_busy => rd_rst_busy + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file cmd_fifo.vhd when simulating +-- the core, cmd_fifo. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.v new file mode 100644 index 0000000..05d0459 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:22 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cmd_fifo/cmd_fifo_stub.v +// Design : cmd_fifo +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *) +module cmd_fifo(srst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, + empty, wr_rst_busy, rd_rst_busy) +/* synthesis syn_black_box black_box_pad_pin="srst,wr_clk,rd_clk,din[127:0],wr_en,rd_en,dout[63:0],full,empty,wr_rst_busy,rd_rst_busy" */; + input srst; + input wr_clk; + input rd_clk; + input [127:0]din; + input wr_en; + input rd_en; + output [63:0]dout; + output full; + output empty; + output wr_rst_busy; + output rd_rst_busy; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.vhdl new file mode 100644 index 0000000..478af91 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:22 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cmd_fifo/cmd_fifo_stub.vhdl +-- Design : cmd_fifo +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity cmd_fifo is + Port ( + srst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 127 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 63 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC + ); + +end cmd_fifo; + +architecture stub of cmd_fifo is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "srst,wr_clk,rd_clk,din[127:0],wr_en,rd_en,dout[63:0],full,empty,wr_rst_busy,rd_rst_busy"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.veo new file mode 100755 index 0000000..aa6f294 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.veo @@ -0,0 +1,892 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:hbm:1.0 +// IP Revision: 9 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +hbm_0 your_instance_name ( + .HBM_REF_CLK_0(HBM_REF_CLK_0), // input wire HBM_REF_CLK_0 + .HBM_REF_CLK_1(HBM_REF_CLK_1), // input wire HBM_REF_CLK_1 + .dfi_0_clk(dfi_0_clk), // input wire dfi_0_clk + .dfi_0_rst_n(dfi_0_rst_n), // input wire dfi_0_rst_n + .dfi_0_init_start(dfi_0_init_start), // input wire dfi_0_init_start + .dfi_0_aw_ck_p0(dfi_0_aw_ck_p0), // input wire [1 : 0] dfi_0_aw_ck_p0 + .dfi_0_aw_cke_p0(dfi_0_aw_cke_p0), // input wire [1 : 0] dfi_0_aw_cke_p0 + .dfi_0_aw_row_p0(dfi_0_aw_row_p0), // input wire [11 : 0] dfi_0_aw_row_p0 + .dfi_0_aw_col_p0(dfi_0_aw_col_p0), // input wire [15 : 0] dfi_0_aw_col_p0 + .dfi_0_dw_wrdata_p0(dfi_0_dw_wrdata_p0), // input wire [255 : 0] dfi_0_dw_wrdata_p0 + .dfi_0_dw_wrdata_mask_p0(dfi_0_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_0_dw_wrdata_mask_p0 + .dfi_0_dw_wrdata_dbi_p0(dfi_0_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_0_dw_wrdata_dbi_p0 + .dfi_0_dw_wrdata_par_p0(dfi_0_dw_wrdata_par_p0), // input wire [7 : 0] dfi_0_dw_wrdata_par_p0 + .dfi_0_dw_wrdata_dq_en_p0(dfi_0_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_0_dw_wrdata_dq_en_p0 + .dfi_0_dw_wrdata_par_en_p0(dfi_0_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_0_dw_wrdata_par_en_p0 + .dfi_0_aw_ck_p1(dfi_0_aw_ck_p1), // input wire [1 : 0] dfi_0_aw_ck_p1 + .dfi_0_aw_cke_p1(dfi_0_aw_cke_p1), // input wire [1 : 0] dfi_0_aw_cke_p1 + .dfi_0_aw_row_p1(dfi_0_aw_row_p1), // input wire [11 : 0] dfi_0_aw_row_p1 + .dfi_0_aw_col_p1(dfi_0_aw_col_p1), // input wire [15 : 0] dfi_0_aw_col_p1 + .dfi_0_dw_wrdata_p1(dfi_0_dw_wrdata_p1), // input wire [255 : 0] dfi_0_dw_wrdata_p1 + .dfi_0_dw_wrdata_mask_p1(dfi_0_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_0_dw_wrdata_mask_p1 + .dfi_0_dw_wrdata_dbi_p1(dfi_0_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_0_dw_wrdata_dbi_p1 + .dfi_0_dw_wrdata_par_p1(dfi_0_dw_wrdata_par_p1), // input wire [7 : 0] dfi_0_dw_wrdata_par_p1 + .dfi_0_dw_wrdata_dq_en_p1(dfi_0_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_0_dw_wrdata_dq_en_p1 + .dfi_0_dw_wrdata_par_en_p1(dfi_0_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_0_dw_wrdata_par_en_p1 + .dfi_0_aw_ck_dis(dfi_0_aw_ck_dis), // input wire dfi_0_aw_ck_dis + .dfi_0_lp_pwr_e_req(dfi_0_lp_pwr_e_req), // input wire dfi_0_lp_pwr_e_req + .dfi_0_lp_sr_e_req(dfi_0_lp_sr_e_req), // input wire dfi_0_lp_sr_e_req + .dfi_0_lp_pwr_x_req(dfi_0_lp_pwr_x_req), // input wire dfi_0_lp_pwr_x_req + .dfi_0_aw_tx_indx_ld(dfi_0_aw_tx_indx_ld), // input wire dfi_0_aw_tx_indx_ld + .dfi_0_dw_tx_indx_ld(dfi_0_dw_tx_indx_ld), // input wire dfi_0_dw_tx_indx_ld + .dfi_0_dw_rx_indx_ld(dfi_0_dw_rx_indx_ld), // input wire dfi_0_dw_rx_indx_ld + .dfi_0_ctrlupd_ack(dfi_0_ctrlupd_ack), // input wire dfi_0_ctrlupd_ack + .dfi_0_phyupd_req(dfi_0_phyupd_req), // input wire dfi_0_phyupd_req + .dfi_0_dw_wrdata_dqs_p0(dfi_0_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_0_dw_wrdata_dqs_p0 + .dfi_0_dw_wrdata_dqs_p1(dfi_0_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_0_dw_wrdata_dqs_p1 + .dfi_1_clk(dfi_1_clk), // input wire dfi_1_clk + .dfi_1_rst_n(dfi_1_rst_n), // input wire dfi_1_rst_n + .dfi_1_init_start(dfi_1_init_start), // input wire dfi_1_init_start + .dfi_1_aw_ck_p0(dfi_1_aw_ck_p0), // input wire [1 : 0] dfi_1_aw_ck_p0 + .dfi_1_aw_cke_p0(dfi_1_aw_cke_p0), // input wire [1 : 0] dfi_1_aw_cke_p0 + .dfi_1_aw_row_p0(dfi_1_aw_row_p0), // input wire [11 : 0] dfi_1_aw_row_p0 + .dfi_1_aw_col_p0(dfi_1_aw_col_p0), // input wire [15 : 0] dfi_1_aw_col_p0 + .dfi_1_dw_wrdata_p0(dfi_1_dw_wrdata_p0), // input wire [255 : 0] dfi_1_dw_wrdata_p0 + .dfi_1_dw_wrdata_mask_p0(dfi_1_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_1_dw_wrdata_mask_p0 + .dfi_1_dw_wrdata_dbi_p0(dfi_1_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_1_dw_wrdata_dbi_p0 + .dfi_1_dw_wrdata_par_p0(dfi_1_dw_wrdata_par_p0), // input wire [7 : 0] dfi_1_dw_wrdata_par_p0 + .dfi_1_dw_wrdata_dq_en_p0(dfi_1_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_1_dw_wrdata_dq_en_p0 + .dfi_1_dw_wrdata_par_en_p0(dfi_1_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_1_dw_wrdata_par_en_p0 + .dfi_1_aw_ck_p1(dfi_1_aw_ck_p1), // input wire [1 : 0] dfi_1_aw_ck_p1 + .dfi_1_aw_cke_p1(dfi_1_aw_cke_p1), // input wire [1 : 0] dfi_1_aw_cke_p1 + .dfi_1_aw_row_p1(dfi_1_aw_row_p1), // input wire [11 : 0] dfi_1_aw_row_p1 + .dfi_1_aw_col_p1(dfi_1_aw_col_p1), // input wire [15 : 0] dfi_1_aw_col_p1 + .dfi_1_dw_wrdata_p1(dfi_1_dw_wrdata_p1), // input wire [255 : 0] dfi_1_dw_wrdata_p1 + .dfi_1_dw_wrdata_mask_p1(dfi_1_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_1_dw_wrdata_mask_p1 + .dfi_1_dw_wrdata_dbi_p1(dfi_1_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_1_dw_wrdata_dbi_p1 + .dfi_1_dw_wrdata_par_p1(dfi_1_dw_wrdata_par_p1), // input wire [7 : 0] dfi_1_dw_wrdata_par_p1 + .dfi_1_dw_wrdata_dq_en_p1(dfi_1_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_1_dw_wrdata_dq_en_p1 + .dfi_1_dw_wrdata_par_en_p1(dfi_1_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_1_dw_wrdata_par_en_p1 + .dfi_1_aw_ck_dis(dfi_1_aw_ck_dis), // input wire dfi_1_aw_ck_dis + .dfi_1_lp_pwr_e_req(dfi_1_lp_pwr_e_req), // input wire dfi_1_lp_pwr_e_req + .dfi_1_lp_sr_e_req(dfi_1_lp_sr_e_req), // input wire dfi_1_lp_sr_e_req + .dfi_1_lp_pwr_x_req(dfi_1_lp_pwr_x_req), // input wire dfi_1_lp_pwr_x_req + .dfi_1_aw_tx_indx_ld(dfi_1_aw_tx_indx_ld), // input wire dfi_1_aw_tx_indx_ld + .dfi_1_dw_tx_indx_ld(dfi_1_dw_tx_indx_ld), // input wire dfi_1_dw_tx_indx_ld + .dfi_1_dw_rx_indx_ld(dfi_1_dw_rx_indx_ld), // input wire dfi_1_dw_rx_indx_ld + .dfi_1_ctrlupd_ack(dfi_1_ctrlupd_ack), // input wire dfi_1_ctrlupd_ack + .dfi_1_phyupd_req(dfi_1_phyupd_req), // input wire dfi_1_phyupd_req + .dfi_1_dw_wrdata_dqs_p0(dfi_1_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_1_dw_wrdata_dqs_p0 + .dfi_1_dw_wrdata_dqs_p1(dfi_1_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_1_dw_wrdata_dqs_p1 + .dfi_2_clk(dfi_2_clk), // input wire dfi_2_clk + .dfi_2_rst_n(dfi_2_rst_n), // input wire dfi_2_rst_n + .dfi_2_init_start(dfi_2_init_start), // input wire dfi_2_init_start + .dfi_2_aw_ck_p0(dfi_2_aw_ck_p0), // input wire [1 : 0] dfi_2_aw_ck_p0 + .dfi_2_aw_cke_p0(dfi_2_aw_cke_p0), // input wire [1 : 0] dfi_2_aw_cke_p0 + .dfi_2_aw_row_p0(dfi_2_aw_row_p0), // input wire [11 : 0] dfi_2_aw_row_p0 + .dfi_2_aw_col_p0(dfi_2_aw_col_p0), // input wire [15 : 0] dfi_2_aw_col_p0 + .dfi_2_dw_wrdata_p0(dfi_2_dw_wrdata_p0), // input wire [255 : 0] dfi_2_dw_wrdata_p0 + .dfi_2_dw_wrdata_mask_p0(dfi_2_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_2_dw_wrdata_mask_p0 + .dfi_2_dw_wrdata_dbi_p0(dfi_2_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_2_dw_wrdata_dbi_p0 + .dfi_2_dw_wrdata_par_p0(dfi_2_dw_wrdata_par_p0), // input wire [7 : 0] dfi_2_dw_wrdata_par_p0 + .dfi_2_dw_wrdata_dq_en_p0(dfi_2_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_2_dw_wrdata_dq_en_p0 + .dfi_2_dw_wrdata_par_en_p0(dfi_2_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_2_dw_wrdata_par_en_p0 + .dfi_2_aw_ck_p1(dfi_2_aw_ck_p1), // input wire [1 : 0] dfi_2_aw_ck_p1 + .dfi_2_aw_cke_p1(dfi_2_aw_cke_p1), // input wire [1 : 0] dfi_2_aw_cke_p1 + .dfi_2_aw_row_p1(dfi_2_aw_row_p1), // input wire [11 : 0] dfi_2_aw_row_p1 + .dfi_2_aw_col_p1(dfi_2_aw_col_p1), // input wire [15 : 0] dfi_2_aw_col_p1 + .dfi_2_dw_wrdata_p1(dfi_2_dw_wrdata_p1), // input wire [255 : 0] dfi_2_dw_wrdata_p1 + .dfi_2_dw_wrdata_mask_p1(dfi_2_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_2_dw_wrdata_mask_p1 + .dfi_2_dw_wrdata_dbi_p1(dfi_2_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_2_dw_wrdata_dbi_p1 + .dfi_2_dw_wrdata_par_p1(dfi_2_dw_wrdata_par_p1), // input wire [7 : 0] dfi_2_dw_wrdata_par_p1 + .dfi_2_dw_wrdata_dq_en_p1(dfi_2_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_2_dw_wrdata_dq_en_p1 + .dfi_2_dw_wrdata_par_en_p1(dfi_2_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_2_dw_wrdata_par_en_p1 + .dfi_2_aw_ck_dis(dfi_2_aw_ck_dis), // input wire dfi_2_aw_ck_dis + .dfi_2_lp_pwr_e_req(dfi_2_lp_pwr_e_req), // input wire dfi_2_lp_pwr_e_req + .dfi_2_lp_sr_e_req(dfi_2_lp_sr_e_req), // input wire dfi_2_lp_sr_e_req + .dfi_2_lp_pwr_x_req(dfi_2_lp_pwr_x_req), // input wire dfi_2_lp_pwr_x_req + .dfi_2_aw_tx_indx_ld(dfi_2_aw_tx_indx_ld), // input wire dfi_2_aw_tx_indx_ld + .dfi_2_dw_tx_indx_ld(dfi_2_dw_tx_indx_ld), // input wire dfi_2_dw_tx_indx_ld + .dfi_2_dw_rx_indx_ld(dfi_2_dw_rx_indx_ld), // input wire dfi_2_dw_rx_indx_ld + .dfi_2_ctrlupd_ack(dfi_2_ctrlupd_ack), // input wire dfi_2_ctrlupd_ack + .dfi_2_phyupd_req(dfi_2_phyupd_req), // input wire dfi_2_phyupd_req + .dfi_2_dw_wrdata_dqs_p0(dfi_2_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_2_dw_wrdata_dqs_p0 + .dfi_2_dw_wrdata_dqs_p1(dfi_2_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_2_dw_wrdata_dqs_p1 + .dfi_3_clk(dfi_3_clk), // input wire dfi_3_clk + .dfi_3_rst_n(dfi_3_rst_n), // input wire dfi_3_rst_n + .dfi_3_init_start(dfi_3_init_start), // input wire dfi_3_init_start + .dfi_3_aw_ck_p0(dfi_3_aw_ck_p0), // input wire [1 : 0] dfi_3_aw_ck_p0 + .dfi_3_aw_cke_p0(dfi_3_aw_cke_p0), // input wire [1 : 0] dfi_3_aw_cke_p0 + .dfi_3_aw_row_p0(dfi_3_aw_row_p0), // input wire [11 : 0] dfi_3_aw_row_p0 + .dfi_3_aw_col_p0(dfi_3_aw_col_p0), // input wire [15 : 0] dfi_3_aw_col_p0 + .dfi_3_dw_wrdata_p0(dfi_3_dw_wrdata_p0), // input wire [255 : 0] dfi_3_dw_wrdata_p0 + .dfi_3_dw_wrdata_mask_p0(dfi_3_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_3_dw_wrdata_mask_p0 + .dfi_3_dw_wrdata_dbi_p0(dfi_3_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_3_dw_wrdata_dbi_p0 + .dfi_3_dw_wrdata_par_p0(dfi_3_dw_wrdata_par_p0), // input wire [7 : 0] dfi_3_dw_wrdata_par_p0 + .dfi_3_dw_wrdata_dq_en_p0(dfi_3_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_3_dw_wrdata_dq_en_p0 + .dfi_3_dw_wrdata_par_en_p0(dfi_3_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_3_dw_wrdata_par_en_p0 + .dfi_3_aw_ck_p1(dfi_3_aw_ck_p1), // input wire [1 : 0] dfi_3_aw_ck_p1 + .dfi_3_aw_cke_p1(dfi_3_aw_cke_p1), // input wire [1 : 0] dfi_3_aw_cke_p1 + .dfi_3_aw_row_p1(dfi_3_aw_row_p1), // input wire [11 : 0] dfi_3_aw_row_p1 + .dfi_3_aw_col_p1(dfi_3_aw_col_p1), // input wire [15 : 0] dfi_3_aw_col_p1 + .dfi_3_dw_wrdata_p1(dfi_3_dw_wrdata_p1), // input wire [255 : 0] dfi_3_dw_wrdata_p1 + .dfi_3_dw_wrdata_mask_p1(dfi_3_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_3_dw_wrdata_mask_p1 + .dfi_3_dw_wrdata_dbi_p1(dfi_3_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_3_dw_wrdata_dbi_p1 + .dfi_3_dw_wrdata_par_p1(dfi_3_dw_wrdata_par_p1), // input wire [7 : 0] dfi_3_dw_wrdata_par_p1 + .dfi_3_dw_wrdata_dq_en_p1(dfi_3_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_3_dw_wrdata_dq_en_p1 + .dfi_3_dw_wrdata_par_en_p1(dfi_3_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_3_dw_wrdata_par_en_p1 + .dfi_3_aw_ck_dis(dfi_3_aw_ck_dis), // input wire dfi_3_aw_ck_dis + .dfi_3_lp_pwr_e_req(dfi_3_lp_pwr_e_req), // input wire dfi_3_lp_pwr_e_req + .dfi_3_lp_sr_e_req(dfi_3_lp_sr_e_req), // input wire dfi_3_lp_sr_e_req + .dfi_3_lp_pwr_x_req(dfi_3_lp_pwr_x_req), // input wire dfi_3_lp_pwr_x_req + .dfi_3_aw_tx_indx_ld(dfi_3_aw_tx_indx_ld), // input wire dfi_3_aw_tx_indx_ld + .dfi_3_dw_tx_indx_ld(dfi_3_dw_tx_indx_ld), // input wire dfi_3_dw_tx_indx_ld + .dfi_3_dw_rx_indx_ld(dfi_3_dw_rx_indx_ld), // input wire dfi_3_dw_rx_indx_ld + .dfi_3_ctrlupd_ack(dfi_3_ctrlupd_ack), // input wire dfi_3_ctrlupd_ack + .dfi_3_phyupd_req(dfi_3_phyupd_req), // input wire dfi_3_phyupd_req + .dfi_3_dw_wrdata_dqs_p0(dfi_3_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_3_dw_wrdata_dqs_p0 + .dfi_3_dw_wrdata_dqs_p1(dfi_3_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_3_dw_wrdata_dqs_p1 + .dfi_4_clk(dfi_4_clk), // input wire dfi_4_clk + .dfi_4_rst_n(dfi_4_rst_n), // input wire dfi_4_rst_n + .dfi_4_init_start(dfi_4_init_start), // input wire dfi_4_init_start + .dfi_4_aw_ck_p0(dfi_4_aw_ck_p0), // input wire [1 : 0] dfi_4_aw_ck_p0 + .dfi_4_aw_cke_p0(dfi_4_aw_cke_p0), // input wire [1 : 0] dfi_4_aw_cke_p0 + .dfi_4_aw_row_p0(dfi_4_aw_row_p0), // input wire [11 : 0] dfi_4_aw_row_p0 + .dfi_4_aw_col_p0(dfi_4_aw_col_p0), // input wire [15 : 0] dfi_4_aw_col_p0 + .dfi_4_dw_wrdata_p0(dfi_4_dw_wrdata_p0), // input wire [255 : 0] dfi_4_dw_wrdata_p0 + .dfi_4_dw_wrdata_mask_p0(dfi_4_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_4_dw_wrdata_mask_p0 + .dfi_4_dw_wrdata_dbi_p0(dfi_4_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_4_dw_wrdata_dbi_p0 + .dfi_4_dw_wrdata_par_p0(dfi_4_dw_wrdata_par_p0), // input wire [7 : 0] dfi_4_dw_wrdata_par_p0 + .dfi_4_dw_wrdata_dq_en_p0(dfi_4_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_4_dw_wrdata_dq_en_p0 + .dfi_4_dw_wrdata_par_en_p0(dfi_4_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_4_dw_wrdata_par_en_p0 + .dfi_4_aw_ck_p1(dfi_4_aw_ck_p1), // input wire [1 : 0] dfi_4_aw_ck_p1 + .dfi_4_aw_cke_p1(dfi_4_aw_cke_p1), // input wire [1 : 0] dfi_4_aw_cke_p1 + .dfi_4_aw_row_p1(dfi_4_aw_row_p1), // input wire [11 : 0] dfi_4_aw_row_p1 + .dfi_4_aw_col_p1(dfi_4_aw_col_p1), // input wire [15 : 0] dfi_4_aw_col_p1 + .dfi_4_dw_wrdata_p1(dfi_4_dw_wrdata_p1), // input wire [255 : 0] dfi_4_dw_wrdata_p1 + .dfi_4_dw_wrdata_mask_p1(dfi_4_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_4_dw_wrdata_mask_p1 + .dfi_4_dw_wrdata_dbi_p1(dfi_4_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_4_dw_wrdata_dbi_p1 + .dfi_4_dw_wrdata_par_p1(dfi_4_dw_wrdata_par_p1), // input wire [7 : 0] dfi_4_dw_wrdata_par_p1 + .dfi_4_dw_wrdata_dq_en_p1(dfi_4_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_4_dw_wrdata_dq_en_p1 + .dfi_4_dw_wrdata_par_en_p1(dfi_4_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_4_dw_wrdata_par_en_p1 + .dfi_4_aw_ck_dis(dfi_4_aw_ck_dis), // input wire dfi_4_aw_ck_dis + .dfi_4_lp_pwr_e_req(dfi_4_lp_pwr_e_req), // input wire dfi_4_lp_pwr_e_req + .dfi_4_lp_sr_e_req(dfi_4_lp_sr_e_req), // input wire dfi_4_lp_sr_e_req + .dfi_4_lp_pwr_x_req(dfi_4_lp_pwr_x_req), // input wire dfi_4_lp_pwr_x_req + .dfi_4_aw_tx_indx_ld(dfi_4_aw_tx_indx_ld), // input wire dfi_4_aw_tx_indx_ld + .dfi_4_dw_tx_indx_ld(dfi_4_dw_tx_indx_ld), // input wire dfi_4_dw_tx_indx_ld + .dfi_4_dw_rx_indx_ld(dfi_4_dw_rx_indx_ld), // input wire dfi_4_dw_rx_indx_ld + .dfi_4_ctrlupd_ack(dfi_4_ctrlupd_ack), // input wire dfi_4_ctrlupd_ack + .dfi_4_phyupd_req(dfi_4_phyupd_req), // input wire dfi_4_phyupd_req + .dfi_4_dw_wrdata_dqs_p0(dfi_4_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_4_dw_wrdata_dqs_p0 + .dfi_4_dw_wrdata_dqs_p1(dfi_4_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_4_dw_wrdata_dqs_p1 + .dfi_5_clk(dfi_5_clk), // input wire dfi_5_clk + .dfi_5_rst_n(dfi_5_rst_n), // input wire dfi_5_rst_n + .dfi_5_init_start(dfi_5_init_start), // input wire dfi_5_init_start + .dfi_5_aw_ck_p0(dfi_5_aw_ck_p0), // input wire [1 : 0] dfi_5_aw_ck_p0 + .dfi_5_aw_cke_p0(dfi_5_aw_cke_p0), // input wire [1 : 0] dfi_5_aw_cke_p0 + .dfi_5_aw_row_p0(dfi_5_aw_row_p0), // input wire [11 : 0] dfi_5_aw_row_p0 + .dfi_5_aw_col_p0(dfi_5_aw_col_p0), // input wire [15 : 0] dfi_5_aw_col_p0 + .dfi_5_dw_wrdata_p0(dfi_5_dw_wrdata_p0), // input wire [255 : 0] dfi_5_dw_wrdata_p0 + .dfi_5_dw_wrdata_mask_p0(dfi_5_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_5_dw_wrdata_mask_p0 + .dfi_5_dw_wrdata_dbi_p0(dfi_5_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_5_dw_wrdata_dbi_p0 + .dfi_5_dw_wrdata_par_p0(dfi_5_dw_wrdata_par_p0), // input wire [7 : 0] dfi_5_dw_wrdata_par_p0 + .dfi_5_dw_wrdata_dq_en_p0(dfi_5_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_5_dw_wrdata_dq_en_p0 + .dfi_5_dw_wrdata_par_en_p0(dfi_5_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_5_dw_wrdata_par_en_p0 + .dfi_5_aw_ck_p1(dfi_5_aw_ck_p1), // input wire [1 : 0] dfi_5_aw_ck_p1 + .dfi_5_aw_cke_p1(dfi_5_aw_cke_p1), // input wire [1 : 0] dfi_5_aw_cke_p1 + .dfi_5_aw_row_p1(dfi_5_aw_row_p1), // input wire [11 : 0] dfi_5_aw_row_p1 + .dfi_5_aw_col_p1(dfi_5_aw_col_p1), // input wire [15 : 0] dfi_5_aw_col_p1 + .dfi_5_dw_wrdata_p1(dfi_5_dw_wrdata_p1), // input wire [255 : 0] dfi_5_dw_wrdata_p1 + .dfi_5_dw_wrdata_mask_p1(dfi_5_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_5_dw_wrdata_mask_p1 + .dfi_5_dw_wrdata_dbi_p1(dfi_5_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_5_dw_wrdata_dbi_p1 + .dfi_5_dw_wrdata_par_p1(dfi_5_dw_wrdata_par_p1), // input wire [7 : 0] dfi_5_dw_wrdata_par_p1 + .dfi_5_dw_wrdata_dq_en_p1(dfi_5_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_5_dw_wrdata_dq_en_p1 + .dfi_5_dw_wrdata_par_en_p1(dfi_5_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_5_dw_wrdata_par_en_p1 + .dfi_5_aw_ck_dis(dfi_5_aw_ck_dis), // input wire dfi_5_aw_ck_dis + .dfi_5_lp_pwr_e_req(dfi_5_lp_pwr_e_req), // input wire dfi_5_lp_pwr_e_req + .dfi_5_lp_sr_e_req(dfi_5_lp_sr_e_req), // input wire dfi_5_lp_sr_e_req + .dfi_5_lp_pwr_x_req(dfi_5_lp_pwr_x_req), // input wire dfi_5_lp_pwr_x_req + .dfi_5_aw_tx_indx_ld(dfi_5_aw_tx_indx_ld), // input wire dfi_5_aw_tx_indx_ld + .dfi_5_dw_tx_indx_ld(dfi_5_dw_tx_indx_ld), // input wire dfi_5_dw_tx_indx_ld + .dfi_5_dw_rx_indx_ld(dfi_5_dw_rx_indx_ld), // input wire dfi_5_dw_rx_indx_ld + .dfi_5_ctrlupd_ack(dfi_5_ctrlupd_ack), // input wire dfi_5_ctrlupd_ack + .dfi_5_phyupd_req(dfi_5_phyupd_req), // input wire dfi_5_phyupd_req + .dfi_5_dw_wrdata_dqs_p0(dfi_5_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_5_dw_wrdata_dqs_p0 + .dfi_5_dw_wrdata_dqs_p1(dfi_5_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_5_dw_wrdata_dqs_p1 + .dfi_6_clk(dfi_6_clk), // input wire dfi_6_clk + .dfi_6_rst_n(dfi_6_rst_n), // input wire dfi_6_rst_n + .dfi_6_init_start(dfi_6_init_start), // input wire dfi_6_init_start + .dfi_6_aw_ck_p0(dfi_6_aw_ck_p0), // input wire [1 : 0] dfi_6_aw_ck_p0 + .dfi_6_aw_cke_p0(dfi_6_aw_cke_p0), // input wire [1 : 0] dfi_6_aw_cke_p0 + .dfi_6_aw_row_p0(dfi_6_aw_row_p0), // input wire [11 : 0] dfi_6_aw_row_p0 + .dfi_6_aw_col_p0(dfi_6_aw_col_p0), // input wire [15 : 0] dfi_6_aw_col_p0 + .dfi_6_dw_wrdata_p0(dfi_6_dw_wrdata_p0), // input wire [255 : 0] dfi_6_dw_wrdata_p0 + .dfi_6_dw_wrdata_mask_p0(dfi_6_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_6_dw_wrdata_mask_p0 + .dfi_6_dw_wrdata_dbi_p0(dfi_6_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_6_dw_wrdata_dbi_p0 + .dfi_6_dw_wrdata_par_p0(dfi_6_dw_wrdata_par_p0), // input wire [7 : 0] dfi_6_dw_wrdata_par_p0 + .dfi_6_dw_wrdata_dq_en_p0(dfi_6_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_6_dw_wrdata_dq_en_p0 + .dfi_6_dw_wrdata_par_en_p0(dfi_6_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_6_dw_wrdata_par_en_p0 + .dfi_6_aw_ck_p1(dfi_6_aw_ck_p1), // input wire [1 : 0] dfi_6_aw_ck_p1 + .dfi_6_aw_cke_p1(dfi_6_aw_cke_p1), // input wire [1 : 0] dfi_6_aw_cke_p1 + .dfi_6_aw_row_p1(dfi_6_aw_row_p1), // input wire [11 : 0] dfi_6_aw_row_p1 + .dfi_6_aw_col_p1(dfi_6_aw_col_p1), // input wire [15 : 0] dfi_6_aw_col_p1 + .dfi_6_dw_wrdata_p1(dfi_6_dw_wrdata_p1), // input wire [255 : 0] dfi_6_dw_wrdata_p1 + .dfi_6_dw_wrdata_mask_p1(dfi_6_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_6_dw_wrdata_mask_p1 + .dfi_6_dw_wrdata_dbi_p1(dfi_6_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_6_dw_wrdata_dbi_p1 + .dfi_6_dw_wrdata_par_p1(dfi_6_dw_wrdata_par_p1), // input wire [7 : 0] dfi_6_dw_wrdata_par_p1 + .dfi_6_dw_wrdata_dq_en_p1(dfi_6_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_6_dw_wrdata_dq_en_p1 + .dfi_6_dw_wrdata_par_en_p1(dfi_6_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_6_dw_wrdata_par_en_p1 + .dfi_6_aw_ck_dis(dfi_6_aw_ck_dis), // input wire dfi_6_aw_ck_dis + .dfi_6_lp_pwr_e_req(dfi_6_lp_pwr_e_req), // input wire dfi_6_lp_pwr_e_req + .dfi_6_lp_sr_e_req(dfi_6_lp_sr_e_req), // input wire dfi_6_lp_sr_e_req + .dfi_6_lp_pwr_x_req(dfi_6_lp_pwr_x_req), // input wire dfi_6_lp_pwr_x_req + .dfi_6_aw_tx_indx_ld(dfi_6_aw_tx_indx_ld), // input wire dfi_6_aw_tx_indx_ld + .dfi_6_dw_tx_indx_ld(dfi_6_dw_tx_indx_ld), // input wire dfi_6_dw_tx_indx_ld + .dfi_6_dw_rx_indx_ld(dfi_6_dw_rx_indx_ld), // input wire dfi_6_dw_rx_indx_ld + .dfi_6_ctrlupd_ack(dfi_6_ctrlupd_ack), // input wire dfi_6_ctrlupd_ack + .dfi_6_phyupd_req(dfi_6_phyupd_req), // input wire dfi_6_phyupd_req + .dfi_6_dw_wrdata_dqs_p0(dfi_6_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_6_dw_wrdata_dqs_p0 + .dfi_6_dw_wrdata_dqs_p1(dfi_6_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_6_dw_wrdata_dqs_p1 + .dfi_7_clk(dfi_7_clk), // input wire dfi_7_clk + .dfi_7_rst_n(dfi_7_rst_n), // input wire dfi_7_rst_n + .dfi_7_init_start(dfi_7_init_start), // input wire dfi_7_init_start + .dfi_7_aw_ck_p0(dfi_7_aw_ck_p0), // input wire [1 : 0] dfi_7_aw_ck_p0 + .dfi_7_aw_cke_p0(dfi_7_aw_cke_p0), // input wire [1 : 0] dfi_7_aw_cke_p0 + .dfi_7_aw_row_p0(dfi_7_aw_row_p0), // input wire [11 : 0] dfi_7_aw_row_p0 + .dfi_7_aw_col_p0(dfi_7_aw_col_p0), // input wire [15 : 0] dfi_7_aw_col_p0 + .dfi_7_dw_wrdata_p0(dfi_7_dw_wrdata_p0), // input wire [255 : 0] dfi_7_dw_wrdata_p0 + .dfi_7_dw_wrdata_mask_p0(dfi_7_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_7_dw_wrdata_mask_p0 + .dfi_7_dw_wrdata_dbi_p0(dfi_7_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_7_dw_wrdata_dbi_p0 + .dfi_7_dw_wrdata_par_p0(dfi_7_dw_wrdata_par_p0), // input wire [7 : 0] dfi_7_dw_wrdata_par_p0 + .dfi_7_dw_wrdata_dq_en_p0(dfi_7_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_7_dw_wrdata_dq_en_p0 + .dfi_7_dw_wrdata_par_en_p0(dfi_7_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_7_dw_wrdata_par_en_p0 + .dfi_7_aw_ck_p1(dfi_7_aw_ck_p1), // input wire [1 : 0] dfi_7_aw_ck_p1 + .dfi_7_aw_cke_p1(dfi_7_aw_cke_p1), // input wire [1 : 0] dfi_7_aw_cke_p1 + .dfi_7_aw_row_p1(dfi_7_aw_row_p1), // input wire [11 : 0] dfi_7_aw_row_p1 + .dfi_7_aw_col_p1(dfi_7_aw_col_p1), // input wire [15 : 0] dfi_7_aw_col_p1 + .dfi_7_dw_wrdata_p1(dfi_7_dw_wrdata_p1), // input wire [255 : 0] dfi_7_dw_wrdata_p1 + .dfi_7_dw_wrdata_mask_p1(dfi_7_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_7_dw_wrdata_mask_p1 + .dfi_7_dw_wrdata_dbi_p1(dfi_7_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_7_dw_wrdata_dbi_p1 + .dfi_7_dw_wrdata_par_p1(dfi_7_dw_wrdata_par_p1), // input wire [7 : 0] dfi_7_dw_wrdata_par_p1 + .dfi_7_dw_wrdata_dq_en_p1(dfi_7_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_7_dw_wrdata_dq_en_p1 + .dfi_7_dw_wrdata_par_en_p1(dfi_7_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_7_dw_wrdata_par_en_p1 + .dfi_7_aw_ck_dis(dfi_7_aw_ck_dis), // input wire dfi_7_aw_ck_dis + .dfi_7_lp_pwr_e_req(dfi_7_lp_pwr_e_req), // input wire dfi_7_lp_pwr_e_req + .dfi_7_lp_sr_e_req(dfi_7_lp_sr_e_req), // input wire dfi_7_lp_sr_e_req + .dfi_7_lp_pwr_x_req(dfi_7_lp_pwr_x_req), // input wire dfi_7_lp_pwr_x_req + .dfi_7_aw_tx_indx_ld(dfi_7_aw_tx_indx_ld), // input wire dfi_7_aw_tx_indx_ld + .dfi_7_dw_tx_indx_ld(dfi_7_dw_tx_indx_ld), // input wire dfi_7_dw_tx_indx_ld + .dfi_7_dw_rx_indx_ld(dfi_7_dw_rx_indx_ld), // input wire dfi_7_dw_rx_indx_ld + .dfi_7_ctrlupd_ack(dfi_7_ctrlupd_ack), // input wire dfi_7_ctrlupd_ack + .dfi_7_phyupd_req(dfi_7_phyupd_req), // input wire dfi_7_phyupd_req + .dfi_7_dw_wrdata_dqs_p0(dfi_7_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_7_dw_wrdata_dqs_p0 + .dfi_7_dw_wrdata_dqs_p1(dfi_7_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_7_dw_wrdata_dqs_p1 + .dfi_8_clk(dfi_8_clk), // input wire dfi_8_clk + .dfi_8_rst_n(dfi_8_rst_n), // input wire dfi_8_rst_n + .dfi_8_init_start(dfi_8_init_start), // input wire dfi_8_init_start + .dfi_8_aw_ck_p0(dfi_8_aw_ck_p0), // input wire [1 : 0] dfi_8_aw_ck_p0 + .dfi_8_aw_cke_p0(dfi_8_aw_cke_p0), // input wire [1 : 0] dfi_8_aw_cke_p0 + .dfi_8_aw_row_p0(dfi_8_aw_row_p0), // input wire [11 : 0] dfi_8_aw_row_p0 + .dfi_8_aw_col_p0(dfi_8_aw_col_p0), // input wire [15 : 0] dfi_8_aw_col_p0 + .dfi_8_dw_wrdata_p0(dfi_8_dw_wrdata_p0), // input wire [255 : 0] dfi_8_dw_wrdata_p0 + .dfi_8_dw_wrdata_mask_p0(dfi_8_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_8_dw_wrdata_mask_p0 + .dfi_8_dw_wrdata_dbi_p0(dfi_8_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_8_dw_wrdata_dbi_p0 + .dfi_8_dw_wrdata_par_p0(dfi_8_dw_wrdata_par_p0), // input wire [7 : 0] dfi_8_dw_wrdata_par_p0 + .dfi_8_dw_wrdata_dq_en_p0(dfi_8_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_8_dw_wrdata_dq_en_p0 + .dfi_8_dw_wrdata_par_en_p0(dfi_8_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_8_dw_wrdata_par_en_p0 + .dfi_8_aw_ck_p1(dfi_8_aw_ck_p1), // input wire [1 : 0] dfi_8_aw_ck_p1 + .dfi_8_aw_cke_p1(dfi_8_aw_cke_p1), // input wire [1 : 0] dfi_8_aw_cke_p1 + .dfi_8_aw_row_p1(dfi_8_aw_row_p1), // input wire [11 : 0] dfi_8_aw_row_p1 + .dfi_8_aw_col_p1(dfi_8_aw_col_p1), // input wire [15 : 0] dfi_8_aw_col_p1 + .dfi_8_dw_wrdata_p1(dfi_8_dw_wrdata_p1), // input wire [255 : 0] dfi_8_dw_wrdata_p1 + .dfi_8_dw_wrdata_mask_p1(dfi_8_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_8_dw_wrdata_mask_p1 + .dfi_8_dw_wrdata_dbi_p1(dfi_8_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_8_dw_wrdata_dbi_p1 + .dfi_8_dw_wrdata_par_p1(dfi_8_dw_wrdata_par_p1), // input wire [7 : 0] dfi_8_dw_wrdata_par_p1 + .dfi_8_dw_wrdata_dq_en_p1(dfi_8_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_8_dw_wrdata_dq_en_p1 + .dfi_8_dw_wrdata_par_en_p1(dfi_8_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_8_dw_wrdata_par_en_p1 + .dfi_8_aw_ck_dis(dfi_8_aw_ck_dis), // input wire dfi_8_aw_ck_dis + .dfi_8_lp_pwr_e_req(dfi_8_lp_pwr_e_req), // input wire dfi_8_lp_pwr_e_req + .dfi_8_lp_sr_e_req(dfi_8_lp_sr_e_req), // input wire dfi_8_lp_sr_e_req + .dfi_8_lp_pwr_x_req(dfi_8_lp_pwr_x_req), // input wire dfi_8_lp_pwr_x_req + .dfi_8_aw_tx_indx_ld(dfi_8_aw_tx_indx_ld), // input wire dfi_8_aw_tx_indx_ld + .dfi_8_dw_tx_indx_ld(dfi_8_dw_tx_indx_ld), // input wire dfi_8_dw_tx_indx_ld + .dfi_8_dw_rx_indx_ld(dfi_8_dw_rx_indx_ld), // input wire dfi_8_dw_rx_indx_ld + .dfi_8_ctrlupd_ack(dfi_8_ctrlupd_ack), // input wire dfi_8_ctrlupd_ack + .dfi_8_phyupd_req(dfi_8_phyupd_req), // input wire dfi_8_phyupd_req + .dfi_8_dw_wrdata_dqs_p0(dfi_8_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_8_dw_wrdata_dqs_p0 + .dfi_8_dw_wrdata_dqs_p1(dfi_8_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_8_dw_wrdata_dqs_p1 + .dfi_9_clk(dfi_9_clk), // input wire dfi_9_clk + .dfi_9_rst_n(dfi_9_rst_n), // input wire dfi_9_rst_n + .dfi_9_init_start(dfi_9_init_start), // input wire dfi_9_init_start + .dfi_9_aw_ck_p0(dfi_9_aw_ck_p0), // input wire [1 : 0] dfi_9_aw_ck_p0 + .dfi_9_aw_cke_p0(dfi_9_aw_cke_p0), // input wire [1 : 0] dfi_9_aw_cke_p0 + .dfi_9_aw_row_p0(dfi_9_aw_row_p0), // input wire [11 : 0] dfi_9_aw_row_p0 + .dfi_9_aw_col_p0(dfi_9_aw_col_p0), // input wire [15 : 0] dfi_9_aw_col_p0 + .dfi_9_dw_wrdata_p0(dfi_9_dw_wrdata_p0), // input wire [255 : 0] dfi_9_dw_wrdata_p0 + .dfi_9_dw_wrdata_mask_p0(dfi_9_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_9_dw_wrdata_mask_p0 + .dfi_9_dw_wrdata_dbi_p0(dfi_9_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_9_dw_wrdata_dbi_p0 + .dfi_9_dw_wrdata_par_p0(dfi_9_dw_wrdata_par_p0), // input wire [7 : 0] dfi_9_dw_wrdata_par_p0 + .dfi_9_dw_wrdata_dq_en_p0(dfi_9_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_9_dw_wrdata_dq_en_p0 + .dfi_9_dw_wrdata_par_en_p0(dfi_9_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_9_dw_wrdata_par_en_p0 + .dfi_9_aw_ck_p1(dfi_9_aw_ck_p1), // input wire [1 : 0] dfi_9_aw_ck_p1 + .dfi_9_aw_cke_p1(dfi_9_aw_cke_p1), // input wire [1 : 0] dfi_9_aw_cke_p1 + .dfi_9_aw_row_p1(dfi_9_aw_row_p1), // input wire [11 : 0] dfi_9_aw_row_p1 + .dfi_9_aw_col_p1(dfi_9_aw_col_p1), // input wire [15 : 0] dfi_9_aw_col_p1 + .dfi_9_dw_wrdata_p1(dfi_9_dw_wrdata_p1), // input wire [255 : 0] dfi_9_dw_wrdata_p1 + .dfi_9_dw_wrdata_mask_p1(dfi_9_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_9_dw_wrdata_mask_p1 + .dfi_9_dw_wrdata_dbi_p1(dfi_9_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_9_dw_wrdata_dbi_p1 + .dfi_9_dw_wrdata_par_p1(dfi_9_dw_wrdata_par_p1), // input wire [7 : 0] dfi_9_dw_wrdata_par_p1 + .dfi_9_dw_wrdata_dq_en_p1(dfi_9_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_9_dw_wrdata_dq_en_p1 + .dfi_9_dw_wrdata_par_en_p1(dfi_9_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_9_dw_wrdata_par_en_p1 + .dfi_9_aw_ck_dis(dfi_9_aw_ck_dis), // input wire dfi_9_aw_ck_dis + .dfi_9_lp_pwr_e_req(dfi_9_lp_pwr_e_req), // input wire dfi_9_lp_pwr_e_req + .dfi_9_lp_sr_e_req(dfi_9_lp_sr_e_req), // input wire dfi_9_lp_sr_e_req + .dfi_9_lp_pwr_x_req(dfi_9_lp_pwr_x_req), // input wire dfi_9_lp_pwr_x_req + .dfi_9_aw_tx_indx_ld(dfi_9_aw_tx_indx_ld), // input wire dfi_9_aw_tx_indx_ld + .dfi_9_dw_tx_indx_ld(dfi_9_dw_tx_indx_ld), // input wire dfi_9_dw_tx_indx_ld + .dfi_9_dw_rx_indx_ld(dfi_9_dw_rx_indx_ld), // input wire dfi_9_dw_rx_indx_ld + .dfi_9_ctrlupd_ack(dfi_9_ctrlupd_ack), // input wire dfi_9_ctrlupd_ack + .dfi_9_phyupd_req(dfi_9_phyupd_req), // input wire dfi_9_phyupd_req + .dfi_9_dw_wrdata_dqs_p0(dfi_9_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_9_dw_wrdata_dqs_p0 + .dfi_9_dw_wrdata_dqs_p1(dfi_9_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_9_dw_wrdata_dqs_p1 + .dfi_10_clk(dfi_10_clk), // input wire dfi_10_clk + .dfi_10_rst_n(dfi_10_rst_n), // input wire dfi_10_rst_n + .dfi_10_init_start(dfi_10_init_start), // input wire dfi_10_init_start + .dfi_10_aw_ck_p0(dfi_10_aw_ck_p0), // input wire [1 : 0] dfi_10_aw_ck_p0 + .dfi_10_aw_cke_p0(dfi_10_aw_cke_p0), // input wire [1 : 0] dfi_10_aw_cke_p0 + .dfi_10_aw_row_p0(dfi_10_aw_row_p0), // input wire [11 : 0] dfi_10_aw_row_p0 + .dfi_10_aw_col_p0(dfi_10_aw_col_p0), // input wire [15 : 0] dfi_10_aw_col_p0 + .dfi_10_dw_wrdata_p0(dfi_10_dw_wrdata_p0), // input wire [255 : 0] dfi_10_dw_wrdata_p0 + .dfi_10_dw_wrdata_mask_p0(dfi_10_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_10_dw_wrdata_mask_p0 + .dfi_10_dw_wrdata_dbi_p0(dfi_10_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_10_dw_wrdata_dbi_p0 + .dfi_10_dw_wrdata_par_p0(dfi_10_dw_wrdata_par_p0), // input wire [7 : 0] dfi_10_dw_wrdata_par_p0 + .dfi_10_dw_wrdata_dq_en_p0(dfi_10_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_10_dw_wrdata_dq_en_p0 + .dfi_10_dw_wrdata_par_en_p0(dfi_10_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_10_dw_wrdata_par_en_p0 + .dfi_10_aw_ck_p1(dfi_10_aw_ck_p1), // input wire [1 : 0] dfi_10_aw_ck_p1 + .dfi_10_aw_cke_p1(dfi_10_aw_cke_p1), // input wire [1 : 0] dfi_10_aw_cke_p1 + .dfi_10_aw_row_p1(dfi_10_aw_row_p1), // input wire [11 : 0] dfi_10_aw_row_p1 + .dfi_10_aw_col_p1(dfi_10_aw_col_p1), // input wire [15 : 0] dfi_10_aw_col_p1 + .dfi_10_dw_wrdata_p1(dfi_10_dw_wrdata_p1), // input wire [255 : 0] dfi_10_dw_wrdata_p1 + .dfi_10_dw_wrdata_mask_p1(dfi_10_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_10_dw_wrdata_mask_p1 + .dfi_10_dw_wrdata_dbi_p1(dfi_10_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_10_dw_wrdata_dbi_p1 + .dfi_10_dw_wrdata_par_p1(dfi_10_dw_wrdata_par_p1), // input wire [7 : 0] dfi_10_dw_wrdata_par_p1 + .dfi_10_dw_wrdata_dq_en_p1(dfi_10_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_10_dw_wrdata_dq_en_p1 + .dfi_10_dw_wrdata_par_en_p1(dfi_10_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_10_dw_wrdata_par_en_p1 + .dfi_10_aw_ck_dis(dfi_10_aw_ck_dis), // input wire dfi_10_aw_ck_dis + .dfi_10_lp_pwr_e_req(dfi_10_lp_pwr_e_req), // input wire dfi_10_lp_pwr_e_req + .dfi_10_lp_sr_e_req(dfi_10_lp_sr_e_req), // input wire dfi_10_lp_sr_e_req + .dfi_10_lp_pwr_x_req(dfi_10_lp_pwr_x_req), // input wire dfi_10_lp_pwr_x_req + .dfi_10_aw_tx_indx_ld(dfi_10_aw_tx_indx_ld), // input wire dfi_10_aw_tx_indx_ld + .dfi_10_dw_tx_indx_ld(dfi_10_dw_tx_indx_ld), // input wire dfi_10_dw_tx_indx_ld + .dfi_10_dw_rx_indx_ld(dfi_10_dw_rx_indx_ld), // input wire dfi_10_dw_rx_indx_ld + .dfi_10_ctrlupd_ack(dfi_10_ctrlupd_ack), // input wire dfi_10_ctrlupd_ack + .dfi_10_phyupd_req(dfi_10_phyupd_req), // input wire dfi_10_phyupd_req + .dfi_10_dw_wrdata_dqs_p0(dfi_10_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_10_dw_wrdata_dqs_p0 + .dfi_10_dw_wrdata_dqs_p1(dfi_10_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_10_dw_wrdata_dqs_p1 + .dfi_11_clk(dfi_11_clk), // input wire dfi_11_clk + .dfi_11_rst_n(dfi_11_rst_n), // input wire dfi_11_rst_n + .dfi_11_init_start(dfi_11_init_start), // input wire dfi_11_init_start + .dfi_11_aw_ck_p0(dfi_11_aw_ck_p0), // input wire [1 : 0] dfi_11_aw_ck_p0 + .dfi_11_aw_cke_p0(dfi_11_aw_cke_p0), // input wire [1 : 0] dfi_11_aw_cke_p0 + .dfi_11_aw_row_p0(dfi_11_aw_row_p0), // input wire [11 : 0] dfi_11_aw_row_p0 + .dfi_11_aw_col_p0(dfi_11_aw_col_p0), // input wire [15 : 0] dfi_11_aw_col_p0 + .dfi_11_dw_wrdata_p0(dfi_11_dw_wrdata_p0), // input wire [255 : 0] dfi_11_dw_wrdata_p0 + .dfi_11_dw_wrdata_mask_p0(dfi_11_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_11_dw_wrdata_mask_p0 + .dfi_11_dw_wrdata_dbi_p0(dfi_11_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_11_dw_wrdata_dbi_p0 + .dfi_11_dw_wrdata_par_p0(dfi_11_dw_wrdata_par_p0), // input wire [7 : 0] dfi_11_dw_wrdata_par_p0 + .dfi_11_dw_wrdata_dq_en_p0(dfi_11_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_11_dw_wrdata_dq_en_p0 + .dfi_11_dw_wrdata_par_en_p0(dfi_11_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_11_dw_wrdata_par_en_p0 + .dfi_11_aw_ck_p1(dfi_11_aw_ck_p1), // input wire [1 : 0] dfi_11_aw_ck_p1 + .dfi_11_aw_cke_p1(dfi_11_aw_cke_p1), // input wire [1 : 0] dfi_11_aw_cke_p1 + .dfi_11_aw_row_p1(dfi_11_aw_row_p1), // input wire [11 : 0] dfi_11_aw_row_p1 + .dfi_11_aw_col_p1(dfi_11_aw_col_p1), // input wire [15 : 0] dfi_11_aw_col_p1 + .dfi_11_dw_wrdata_p1(dfi_11_dw_wrdata_p1), // input wire [255 : 0] dfi_11_dw_wrdata_p1 + .dfi_11_dw_wrdata_mask_p1(dfi_11_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_11_dw_wrdata_mask_p1 + .dfi_11_dw_wrdata_dbi_p1(dfi_11_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_11_dw_wrdata_dbi_p1 + .dfi_11_dw_wrdata_par_p1(dfi_11_dw_wrdata_par_p1), // input wire [7 : 0] dfi_11_dw_wrdata_par_p1 + .dfi_11_dw_wrdata_dq_en_p1(dfi_11_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_11_dw_wrdata_dq_en_p1 + .dfi_11_dw_wrdata_par_en_p1(dfi_11_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_11_dw_wrdata_par_en_p1 + .dfi_11_aw_ck_dis(dfi_11_aw_ck_dis), // input wire dfi_11_aw_ck_dis + .dfi_11_lp_pwr_e_req(dfi_11_lp_pwr_e_req), // input wire dfi_11_lp_pwr_e_req + .dfi_11_lp_sr_e_req(dfi_11_lp_sr_e_req), // input wire dfi_11_lp_sr_e_req + .dfi_11_lp_pwr_x_req(dfi_11_lp_pwr_x_req), // input wire dfi_11_lp_pwr_x_req + .dfi_11_aw_tx_indx_ld(dfi_11_aw_tx_indx_ld), // input wire dfi_11_aw_tx_indx_ld + .dfi_11_dw_tx_indx_ld(dfi_11_dw_tx_indx_ld), // input wire dfi_11_dw_tx_indx_ld + .dfi_11_dw_rx_indx_ld(dfi_11_dw_rx_indx_ld), // input wire dfi_11_dw_rx_indx_ld + .dfi_11_ctrlupd_ack(dfi_11_ctrlupd_ack), // input wire dfi_11_ctrlupd_ack + .dfi_11_phyupd_req(dfi_11_phyupd_req), // input wire dfi_11_phyupd_req + .dfi_11_dw_wrdata_dqs_p0(dfi_11_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_11_dw_wrdata_dqs_p0 + .dfi_11_dw_wrdata_dqs_p1(dfi_11_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_11_dw_wrdata_dqs_p1 + .dfi_12_clk(dfi_12_clk), // input wire dfi_12_clk + .dfi_12_rst_n(dfi_12_rst_n), // input wire dfi_12_rst_n + .dfi_12_init_start(dfi_12_init_start), // input wire dfi_12_init_start + .dfi_12_aw_ck_p0(dfi_12_aw_ck_p0), // input wire [1 : 0] dfi_12_aw_ck_p0 + .dfi_12_aw_cke_p0(dfi_12_aw_cke_p0), // input wire [1 : 0] dfi_12_aw_cke_p0 + .dfi_12_aw_row_p0(dfi_12_aw_row_p0), // input wire [11 : 0] dfi_12_aw_row_p0 + .dfi_12_aw_col_p0(dfi_12_aw_col_p0), // input wire [15 : 0] dfi_12_aw_col_p0 + .dfi_12_dw_wrdata_p0(dfi_12_dw_wrdata_p0), // input wire [255 : 0] dfi_12_dw_wrdata_p0 + .dfi_12_dw_wrdata_mask_p0(dfi_12_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_12_dw_wrdata_mask_p0 + .dfi_12_dw_wrdata_dbi_p0(dfi_12_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_12_dw_wrdata_dbi_p0 + .dfi_12_dw_wrdata_par_p0(dfi_12_dw_wrdata_par_p0), // input wire [7 : 0] dfi_12_dw_wrdata_par_p0 + .dfi_12_dw_wrdata_dq_en_p0(dfi_12_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_12_dw_wrdata_dq_en_p0 + .dfi_12_dw_wrdata_par_en_p0(dfi_12_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_12_dw_wrdata_par_en_p0 + .dfi_12_aw_ck_p1(dfi_12_aw_ck_p1), // input wire [1 : 0] dfi_12_aw_ck_p1 + .dfi_12_aw_cke_p1(dfi_12_aw_cke_p1), // input wire [1 : 0] dfi_12_aw_cke_p1 + .dfi_12_aw_row_p1(dfi_12_aw_row_p1), // input wire [11 : 0] dfi_12_aw_row_p1 + .dfi_12_aw_col_p1(dfi_12_aw_col_p1), // input wire [15 : 0] dfi_12_aw_col_p1 + .dfi_12_dw_wrdata_p1(dfi_12_dw_wrdata_p1), // input wire [255 : 0] dfi_12_dw_wrdata_p1 + .dfi_12_dw_wrdata_mask_p1(dfi_12_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_12_dw_wrdata_mask_p1 + .dfi_12_dw_wrdata_dbi_p1(dfi_12_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_12_dw_wrdata_dbi_p1 + .dfi_12_dw_wrdata_par_p1(dfi_12_dw_wrdata_par_p1), // input wire [7 : 0] dfi_12_dw_wrdata_par_p1 + .dfi_12_dw_wrdata_dq_en_p1(dfi_12_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_12_dw_wrdata_dq_en_p1 + .dfi_12_dw_wrdata_par_en_p1(dfi_12_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_12_dw_wrdata_par_en_p1 + .dfi_12_aw_ck_dis(dfi_12_aw_ck_dis), // input wire dfi_12_aw_ck_dis + .dfi_12_lp_pwr_e_req(dfi_12_lp_pwr_e_req), // input wire dfi_12_lp_pwr_e_req + .dfi_12_lp_sr_e_req(dfi_12_lp_sr_e_req), // input wire dfi_12_lp_sr_e_req + .dfi_12_lp_pwr_x_req(dfi_12_lp_pwr_x_req), // input wire dfi_12_lp_pwr_x_req + .dfi_12_aw_tx_indx_ld(dfi_12_aw_tx_indx_ld), // input wire dfi_12_aw_tx_indx_ld + .dfi_12_dw_tx_indx_ld(dfi_12_dw_tx_indx_ld), // input wire dfi_12_dw_tx_indx_ld + .dfi_12_dw_rx_indx_ld(dfi_12_dw_rx_indx_ld), // input wire dfi_12_dw_rx_indx_ld + .dfi_12_ctrlupd_ack(dfi_12_ctrlupd_ack), // input wire dfi_12_ctrlupd_ack + .dfi_12_phyupd_req(dfi_12_phyupd_req), // input wire dfi_12_phyupd_req + .dfi_12_dw_wrdata_dqs_p0(dfi_12_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_12_dw_wrdata_dqs_p0 + .dfi_12_dw_wrdata_dqs_p1(dfi_12_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_12_dw_wrdata_dqs_p1 + .dfi_13_clk(dfi_13_clk), // input wire dfi_13_clk + .dfi_13_rst_n(dfi_13_rst_n), // input wire dfi_13_rst_n + .dfi_13_init_start(dfi_13_init_start), // input wire dfi_13_init_start + .dfi_13_aw_ck_p0(dfi_13_aw_ck_p0), // input wire [1 : 0] dfi_13_aw_ck_p0 + .dfi_13_aw_cke_p0(dfi_13_aw_cke_p0), // input wire [1 : 0] dfi_13_aw_cke_p0 + .dfi_13_aw_row_p0(dfi_13_aw_row_p0), // input wire [11 : 0] dfi_13_aw_row_p0 + .dfi_13_aw_col_p0(dfi_13_aw_col_p0), // input wire [15 : 0] dfi_13_aw_col_p0 + .dfi_13_dw_wrdata_p0(dfi_13_dw_wrdata_p0), // input wire [255 : 0] dfi_13_dw_wrdata_p0 + .dfi_13_dw_wrdata_mask_p0(dfi_13_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_13_dw_wrdata_mask_p0 + .dfi_13_dw_wrdata_dbi_p0(dfi_13_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_13_dw_wrdata_dbi_p0 + .dfi_13_dw_wrdata_par_p0(dfi_13_dw_wrdata_par_p0), // input wire [7 : 0] dfi_13_dw_wrdata_par_p0 + .dfi_13_dw_wrdata_dq_en_p0(dfi_13_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_13_dw_wrdata_dq_en_p0 + .dfi_13_dw_wrdata_par_en_p0(dfi_13_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_13_dw_wrdata_par_en_p0 + .dfi_13_aw_ck_p1(dfi_13_aw_ck_p1), // input wire [1 : 0] dfi_13_aw_ck_p1 + .dfi_13_aw_cke_p1(dfi_13_aw_cke_p1), // input wire [1 : 0] dfi_13_aw_cke_p1 + .dfi_13_aw_row_p1(dfi_13_aw_row_p1), // input wire [11 : 0] dfi_13_aw_row_p1 + .dfi_13_aw_col_p1(dfi_13_aw_col_p1), // input wire [15 : 0] dfi_13_aw_col_p1 + .dfi_13_dw_wrdata_p1(dfi_13_dw_wrdata_p1), // input wire [255 : 0] dfi_13_dw_wrdata_p1 + .dfi_13_dw_wrdata_mask_p1(dfi_13_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_13_dw_wrdata_mask_p1 + .dfi_13_dw_wrdata_dbi_p1(dfi_13_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_13_dw_wrdata_dbi_p1 + .dfi_13_dw_wrdata_par_p1(dfi_13_dw_wrdata_par_p1), // input wire [7 : 0] dfi_13_dw_wrdata_par_p1 + .dfi_13_dw_wrdata_dq_en_p1(dfi_13_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_13_dw_wrdata_dq_en_p1 + .dfi_13_dw_wrdata_par_en_p1(dfi_13_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_13_dw_wrdata_par_en_p1 + .dfi_13_aw_ck_dis(dfi_13_aw_ck_dis), // input wire dfi_13_aw_ck_dis + .dfi_13_lp_pwr_e_req(dfi_13_lp_pwr_e_req), // input wire dfi_13_lp_pwr_e_req + .dfi_13_lp_sr_e_req(dfi_13_lp_sr_e_req), // input wire dfi_13_lp_sr_e_req + .dfi_13_lp_pwr_x_req(dfi_13_lp_pwr_x_req), // input wire dfi_13_lp_pwr_x_req + .dfi_13_aw_tx_indx_ld(dfi_13_aw_tx_indx_ld), // input wire dfi_13_aw_tx_indx_ld + .dfi_13_dw_tx_indx_ld(dfi_13_dw_tx_indx_ld), // input wire dfi_13_dw_tx_indx_ld + .dfi_13_dw_rx_indx_ld(dfi_13_dw_rx_indx_ld), // input wire dfi_13_dw_rx_indx_ld + .dfi_13_ctrlupd_ack(dfi_13_ctrlupd_ack), // input wire dfi_13_ctrlupd_ack + .dfi_13_phyupd_req(dfi_13_phyupd_req), // input wire dfi_13_phyupd_req + .dfi_13_dw_wrdata_dqs_p0(dfi_13_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_13_dw_wrdata_dqs_p0 + .dfi_13_dw_wrdata_dqs_p1(dfi_13_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_13_dw_wrdata_dqs_p1 + .dfi_14_clk(dfi_14_clk), // input wire dfi_14_clk + .dfi_14_rst_n(dfi_14_rst_n), // input wire dfi_14_rst_n + .dfi_14_init_start(dfi_14_init_start), // input wire dfi_14_init_start + .dfi_14_aw_ck_p0(dfi_14_aw_ck_p0), // input wire [1 : 0] dfi_14_aw_ck_p0 + .dfi_14_aw_cke_p0(dfi_14_aw_cke_p0), // input wire [1 : 0] dfi_14_aw_cke_p0 + .dfi_14_aw_row_p0(dfi_14_aw_row_p0), // input wire [11 : 0] dfi_14_aw_row_p0 + .dfi_14_aw_col_p0(dfi_14_aw_col_p0), // input wire [15 : 0] dfi_14_aw_col_p0 + .dfi_14_dw_wrdata_p0(dfi_14_dw_wrdata_p0), // input wire [255 : 0] dfi_14_dw_wrdata_p0 + .dfi_14_dw_wrdata_mask_p0(dfi_14_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_14_dw_wrdata_mask_p0 + .dfi_14_dw_wrdata_dbi_p0(dfi_14_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_14_dw_wrdata_dbi_p0 + .dfi_14_dw_wrdata_par_p0(dfi_14_dw_wrdata_par_p0), // input wire [7 : 0] dfi_14_dw_wrdata_par_p0 + .dfi_14_dw_wrdata_dq_en_p0(dfi_14_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_14_dw_wrdata_dq_en_p0 + .dfi_14_dw_wrdata_par_en_p0(dfi_14_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_14_dw_wrdata_par_en_p0 + .dfi_14_aw_ck_p1(dfi_14_aw_ck_p1), // input wire [1 : 0] dfi_14_aw_ck_p1 + .dfi_14_aw_cke_p1(dfi_14_aw_cke_p1), // input wire [1 : 0] dfi_14_aw_cke_p1 + .dfi_14_aw_row_p1(dfi_14_aw_row_p1), // input wire [11 : 0] dfi_14_aw_row_p1 + .dfi_14_aw_col_p1(dfi_14_aw_col_p1), // input wire [15 : 0] dfi_14_aw_col_p1 + .dfi_14_dw_wrdata_p1(dfi_14_dw_wrdata_p1), // input wire [255 : 0] dfi_14_dw_wrdata_p1 + .dfi_14_dw_wrdata_mask_p1(dfi_14_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_14_dw_wrdata_mask_p1 + .dfi_14_dw_wrdata_dbi_p1(dfi_14_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_14_dw_wrdata_dbi_p1 + .dfi_14_dw_wrdata_par_p1(dfi_14_dw_wrdata_par_p1), // input wire [7 : 0] dfi_14_dw_wrdata_par_p1 + .dfi_14_dw_wrdata_dq_en_p1(dfi_14_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_14_dw_wrdata_dq_en_p1 + .dfi_14_dw_wrdata_par_en_p1(dfi_14_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_14_dw_wrdata_par_en_p1 + .dfi_14_aw_ck_dis(dfi_14_aw_ck_dis), // input wire dfi_14_aw_ck_dis + .dfi_14_lp_pwr_e_req(dfi_14_lp_pwr_e_req), // input wire dfi_14_lp_pwr_e_req + .dfi_14_lp_sr_e_req(dfi_14_lp_sr_e_req), // input wire dfi_14_lp_sr_e_req + .dfi_14_lp_pwr_x_req(dfi_14_lp_pwr_x_req), // input wire dfi_14_lp_pwr_x_req + .dfi_14_aw_tx_indx_ld(dfi_14_aw_tx_indx_ld), // input wire dfi_14_aw_tx_indx_ld + .dfi_14_dw_tx_indx_ld(dfi_14_dw_tx_indx_ld), // input wire dfi_14_dw_tx_indx_ld + .dfi_14_dw_rx_indx_ld(dfi_14_dw_rx_indx_ld), // input wire dfi_14_dw_rx_indx_ld + .dfi_14_ctrlupd_ack(dfi_14_ctrlupd_ack), // input wire dfi_14_ctrlupd_ack + .dfi_14_phyupd_req(dfi_14_phyupd_req), // input wire dfi_14_phyupd_req + .dfi_14_dw_wrdata_dqs_p0(dfi_14_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_14_dw_wrdata_dqs_p0 + .dfi_14_dw_wrdata_dqs_p1(dfi_14_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_14_dw_wrdata_dqs_p1 + .dfi_15_clk(dfi_15_clk), // input wire dfi_15_clk + .dfi_15_rst_n(dfi_15_rst_n), // input wire dfi_15_rst_n + .dfi_15_init_start(dfi_15_init_start), // input wire dfi_15_init_start + .dfi_15_aw_ck_p0(dfi_15_aw_ck_p0), // input wire [1 : 0] dfi_15_aw_ck_p0 + .dfi_15_aw_cke_p0(dfi_15_aw_cke_p0), // input wire [1 : 0] dfi_15_aw_cke_p0 + .dfi_15_aw_row_p0(dfi_15_aw_row_p0), // input wire [11 : 0] dfi_15_aw_row_p0 + .dfi_15_aw_col_p0(dfi_15_aw_col_p0), // input wire [15 : 0] dfi_15_aw_col_p0 + .dfi_15_dw_wrdata_p0(dfi_15_dw_wrdata_p0), // input wire [255 : 0] dfi_15_dw_wrdata_p0 + .dfi_15_dw_wrdata_mask_p0(dfi_15_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_15_dw_wrdata_mask_p0 + .dfi_15_dw_wrdata_dbi_p0(dfi_15_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_15_dw_wrdata_dbi_p0 + .dfi_15_dw_wrdata_par_p0(dfi_15_dw_wrdata_par_p0), // input wire [7 : 0] dfi_15_dw_wrdata_par_p0 + .dfi_15_dw_wrdata_dq_en_p0(dfi_15_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_15_dw_wrdata_dq_en_p0 + .dfi_15_dw_wrdata_par_en_p0(dfi_15_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_15_dw_wrdata_par_en_p0 + .dfi_15_aw_ck_p1(dfi_15_aw_ck_p1), // input wire [1 : 0] dfi_15_aw_ck_p1 + .dfi_15_aw_cke_p1(dfi_15_aw_cke_p1), // input wire [1 : 0] dfi_15_aw_cke_p1 + .dfi_15_aw_row_p1(dfi_15_aw_row_p1), // input wire [11 : 0] dfi_15_aw_row_p1 + .dfi_15_aw_col_p1(dfi_15_aw_col_p1), // input wire [15 : 0] dfi_15_aw_col_p1 + .dfi_15_dw_wrdata_p1(dfi_15_dw_wrdata_p1), // input wire [255 : 0] dfi_15_dw_wrdata_p1 + .dfi_15_dw_wrdata_mask_p1(dfi_15_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_15_dw_wrdata_mask_p1 + .dfi_15_dw_wrdata_dbi_p1(dfi_15_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_15_dw_wrdata_dbi_p1 + .dfi_15_dw_wrdata_par_p1(dfi_15_dw_wrdata_par_p1), // input wire [7 : 0] dfi_15_dw_wrdata_par_p1 + .dfi_15_dw_wrdata_dq_en_p1(dfi_15_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_15_dw_wrdata_dq_en_p1 + .dfi_15_dw_wrdata_par_en_p1(dfi_15_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_15_dw_wrdata_par_en_p1 + .dfi_15_aw_ck_dis(dfi_15_aw_ck_dis), // input wire dfi_15_aw_ck_dis + .dfi_15_lp_pwr_e_req(dfi_15_lp_pwr_e_req), // input wire dfi_15_lp_pwr_e_req + .dfi_15_lp_sr_e_req(dfi_15_lp_sr_e_req), // input wire dfi_15_lp_sr_e_req + .dfi_15_lp_pwr_x_req(dfi_15_lp_pwr_x_req), // input wire dfi_15_lp_pwr_x_req + .dfi_15_aw_tx_indx_ld(dfi_15_aw_tx_indx_ld), // input wire dfi_15_aw_tx_indx_ld + .dfi_15_dw_tx_indx_ld(dfi_15_dw_tx_indx_ld), // input wire dfi_15_dw_tx_indx_ld + .dfi_15_dw_rx_indx_ld(dfi_15_dw_rx_indx_ld), // input wire dfi_15_dw_rx_indx_ld + .dfi_15_ctrlupd_ack(dfi_15_ctrlupd_ack), // input wire dfi_15_ctrlupd_ack + .dfi_15_phyupd_req(dfi_15_phyupd_req), // input wire dfi_15_phyupd_req + .dfi_15_dw_wrdata_dqs_p0(dfi_15_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_15_dw_wrdata_dqs_p0 + .dfi_15_dw_wrdata_dqs_p1(dfi_15_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_15_dw_wrdata_dqs_p1 + .APB_0_PCLK(APB_0_PCLK), // input wire APB_0_PCLK + .APB_0_PRESET_N(APB_0_PRESET_N), // input wire APB_0_PRESET_N + .APB_1_PCLK(APB_1_PCLK), // input wire APB_1_PCLK + .APB_1_PRESET_N(APB_1_PRESET_N), // input wire APB_1_PRESET_N + .dfi_0_dw_rddata_p0(dfi_0_dw_rddata_p0), // output wire [255 : 0] dfi_0_dw_rddata_p0 + .dfi_0_dw_rddata_dm_p0(dfi_0_dw_rddata_dm_p0), // output wire [31 : 0] dfi_0_dw_rddata_dm_p0 + .dfi_0_dw_rddata_dbi_p0(dfi_0_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_0_dw_rddata_dbi_p0 + .dfi_0_dw_rddata_par_p0(dfi_0_dw_rddata_par_p0), // output wire [7 : 0] dfi_0_dw_rddata_par_p0 + .dfi_0_dw_rddata_p1(dfi_0_dw_rddata_p1), // output wire [255 : 0] dfi_0_dw_rddata_p1 + .dfi_0_dw_rddata_dm_p1(dfi_0_dw_rddata_dm_p1), // output wire [31 : 0] dfi_0_dw_rddata_dm_p1 + .dfi_0_dw_rddata_dbi_p1(dfi_0_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_0_dw_rddata_dbi_p1 + .dfi_0_dw_rddata_par_p1(dfi_0_dw_rddata_par_p1), // output wire [7 : 0] dfi_0_dw_rddata_par_p1 + .dfi_0_dbi_byte_disable(dfi_0_dbi_byte_disable), // output wire [15 : 0] dfi_0_dbi_byte_disable + .dfi_0_dw_rddata_valid(dfi_0_dw_rddata_valid), // output wire [3 : 0] dfi_0_dw_rddata_valid + .dfi_0_dw_derr_n(dfi_0_dw_derr_n), // output wire [7 : 0] dfi_0_dw_derr_n + .dfi_0_aw_aerr_n(dfi_0_aw_aerr_n), // output wire [1 : 0] dfi_0_aw_aerr_n + .dfi_0_ctrlupd_req(dfi_0_ctrlupd_req), // output wire dfi_0_ctrlupd_req + .dfi_0_phyupd_ack(dfi_0_phyupd_ack), // output wire dfi_0_phyupd_ack + .dfi_0_clk_init(dfi_0_clk_init), // output wire dfi_0_clk_init + .dfi_0_init_complete(dfi_0_init_complete), // output wire dfi_0_init_complete + .dfi_0_out_rst_n(dfi_0_out_rst_n), // output wire dfi_0_out_rst_n + .dfi_1_dw_rddata_p0(dfi_1_dw_rddata_p0), // output wire [255 : 0] dfi_1_dw_rddata_p0 + .dfi_1_dw_rddata_dm_p0(dfi_1_dw_rddata_dm_p0), // output wire [31 : 0] dfi_1_dw_rddata_dm_p0 + .dfi_1_dw_rddata_dbi_p0(dfi_1_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_1_dw_rddata_dbi_p0 + .dfi_1_dw_rddata_par_p0(dfi_1_dw_rddata_par_p0), // output wire [7 : 0] dfi_1_dw_rddata_par_p0 + .dfi_1_dw_rddata_p1(dfi_1_dw_rddata_p1), // output wire [255 : 0] dfi_1_dw_rddata_p1 + .dfi_1_dw_rddata_dm_p1(dfi_1_dw_rddata_dm_p1), // output wire [31 : 0] dfi_1_dw_rddata_dm_p1 + .dfi_1_dw_rddata_dbi_p1(dfi_1_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_1_dw_rddata_dbi_p1 + .dfi_1_dw_rddata_par_p1(dfi_1_dw_rddata_par_p1), // output wire [7 : 0] dfi_1_dw_rddata_par_p1 + .dfi_1_dbi_byte_disable(dfi_1_dbi_byte_disable), // output wire [15 : 0] dfi_1_dbi_byte_disable + .dfi_1_dw_rddata_valid(dfi_1_dw_rddata_valid), // output wire [3 : 0] dfi_1_dw_rddata_valid + .dfi_1_dw_derr_n(dfi_1_dw_derr_n), // output wire [7 : 0] dfi_1_dw_derr_n + .dfi_1_aw_aerr_n(dfi_1_aw_aerr_n), // output wire [1 : 0] dfi_1_aw_aerr_n + .dfi_1_ctrlupd_req(dfi_1_ctrlupd_req), // output wire dfi_1_ctrlupd_req + .dfi_1_phyupd_ack(dfi_1_phyupd_ack), // output wire dfi_1_phyupd_ack + .dfi_1_clk_init(dfi_1_clk_init), // output wire dfi_1_clk_init + .dfi_1_init_complete(dfi_1_init_complete), // output wire dfi_1_init_complete + .dfi_1_out_rst_n(dfi_1_out_rst_n), // output wire dfi_1_out_rst_n + .dfi_2_dw_rddata_p0(dfi_2_dw_rddata_p0), // output wire [255 : 0] dfi_2_dw_rddata_p0 + .dfi_2_dw_rddata_dm_p0(dfi_2_dw_rddata_dm_p0), // output wire [31 : 0] dfi_2_dw_rddata_dm_p0 + .dfi_2_dw_rddata_dbi_p0(dfi_2_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_2_dw_rddata_dbi_p0 + .dfi_2_dw_rddata_par_p0(dfi_2_dw_rddata_par_p0), // output wire [7 : 0] dfi_2_dw_rddata_par_p0 + .dfi_2_dw_rddata_p1(dfi_2_dw_rddata_p1), // output wire [255 : 0] dfi_2_dw_rddata_p1 + .dfi_2_dw_rddata_dm_p1(dfi_2_dw_rddata_dm_p1), // output wire [31 : 0] dfi_2_dw_rddata_dm_p1 + .dfi_2_dw_rddata_dbi_p1(dfi_2_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_2_dw_rddata_dbi_p1 + .dfi_2_dw_rddata_par_p1(dfi_2_dw_rddata_par_p1), // output wire [7 : 0] dfi_2_dw_rddata_par_p1 + .dfi_2_dbi_byte_disable(dfi_2_dbi_byte_disable), // output wire [15 : 0] dfi_2_dbi_byte_disable + .dfi_2_dw_rddata_valid(dfi_2_dw_rddata_valid), // output wire [3 : 0] dfi_2_dw_rddata_valid + .dfi_2_dw_derr_n(dfi_2_dw_derr_n), // output wire [7 : 0] dfi_2_dw_derr_n + .dfi_2_aw_aerr_n(dfi_2_aw_aerr_n), // output wire [1 : 0] dfi_2_aw_aerr_n + .dfi_2_ctrlupd_req(dfi_2_ctrlupd_req), // output wire dfi_2_ctrlupd_req + .dfi_2_phyupd_ack(dfi_2_phyupd_ack), // output wire dfi_2_phyupd_ack + .dfi_2_clk_init(dfi_2_clk_init), // output wire dfi_2_clk_init + .dfi_2_init_complete(dfi_2_init_complete), // output wire dfi_2_init_complete + .dfi_2_out_rst_n(dfi_2_out_rst_n), // output wire dfi_2_out_rst_n + .dfi_3_dw_rddata_p0(dfi_3_dw_rddata_p0), // output wire [255 : 0] dfi_3_dw_rddata_p0 + .dfi_3_dw_rddata_dm_p0(dfi_3_dw_rddata_dm_p0), // output wire [31 : 0] dfi_3_dw_rddata_dm_p0 + .dfi_3_dw_rddata_dbi_p0(dfi_3_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_3_dw_rddata_dbi_p0 + .dfi_3_dw_rddata_par_p0(dfi_3_dw_rddata_par_p0), // output wire [7 : 0] dfi_3_dw_rddata_par_p0 + .dfi_3_dw_rddata_p1(dfi_3_dw_rddata_p1), // output wire [255 : 0] dfi_3_dw_rddata_p1 + .dfi_3_dw_rddata_dm_p1(dfi_3_dw_rddata_dm_p1), // output wire [31 : 0] dfi_3_dw_rddata_dm_p1 + .dfi_3_dw_rddata_dbi_p1(dfi_3_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_3_dw_rddata_dbi_p1 + .dfi_3_dw_rddata_par_p1(dfi_3_dw_rddata_par_p1), // output wire [7 : 0] dfi_3_dw_rddata_par_p1 + .dfi_3_dbi_byte_disable(dfi_3_dbi_byte_disable), // output wire [15 : 0] dfi_3_dbi_byte_disable + .dfi_3_dw_rddata_valid(dfi_3_dw_rddata_valid), // output wire [3 : 0] dfi_3_dw_rddata_valid + .dfi_3_dw_derr_n(dfi_3_dw_derr_n), // output wire [7 : 0] dfi_3_dw_derr_n + .dfi_3_aw_aerr_n(dfi_3_aw_aerr_n), // output wire [1 : 0] dfi_3_aw_aerr_n + .dfi_3_ctrlupd_req(dfi_3_ctrlupd_req), // output wire dfi_3_ctrlupd_req + .dfi_3_phyupd_ack(dfi_3_phyupd_ack), // output wire dfi_3_phyupd_ack + .dfi_3_clk_init(dfi_3_clk_init), // output wire dfi_3_clk_init + .dfi_3_init_complete(dfi_3_init_complete), // output wire dfi_3_init_complete + .dfi_3_out_rst_n(dfi_3_out_rst_n), // output wire dfi_3_out_rst_n + .dfi_4_dw_rddata_p0(dfi_4_dw_rddata_p0), // output wire [255 : 0] dfi_4_dw_rddata_p0 + .dfi_4_dw_rddata_dm_p0(dfi_4_dw_rddata_dm_p0), // output wire [31 : 0] dfi_4_dw_rddata_dm_p0 + .dfi_4_dw_rddata_dbi_p0(dfi_4_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_4_dw_rddata_dbi_p0 + .dfi_4_dw_rddata_par_p0(dfi_4_dw_rddata_par_p0), // output wire [7 : 0] dfi_4_dw_rddata_par_p0 + .dfi_4_dw_rddata_p1(dfi_4_dw_rddata_p1), // output wire [255 : 0] dfi_4_dw_rddata_p1 + .dfi_4_dw_rddata_dm_p1(dfi_4_dw_rddata_dm_p1), // output wire [31 : 0] dfi_4_dw_rddata_dm_p1 + .dfi_4_dw_rddata_dbi_p1(dfi_4_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_4_dw_rddata_dbi_p1 + .dfi_4_dw_rddata_par_p1(dfi_4_dw_rddata_par_p1), // output wire [7 : 0] dfi_4_dw_rddata_par_p1 + .dfi_4_dbi_byte_disable(dfi_4_dbi_byte_disable), // output wire [15 : 0] dfi_4_dbi_byte_disable + .dfi_4_dw_rddata_valid(dfi_4_dw_rddata_valid), // output wire [3 : 0] dfi_4_dw_rddata_valid + .dfi_4_dw_derr_n(dfi_4_dw_derr_n), // output wire [7 : 0] dfi_4_dw_derr_n + .dfi_4_aw_aerr_n(dfi_4_aw_aerr_n), // output wire [1 : 0] dfi_4_aw_aerr_n + .dfi_4_ctrlupd_req(dfi_4_ctrlupd_req), // output wire dfi_4_ctrlupd_req + .dfi_4_phyupd_ack(dfi_4_phyupd_ack), // output wire dfi_4_phyupd_ack + .dfi_4_clk_init(dfi_4_clk_init), // output wire dfi_4_clk_init + .dfi_4_init_complete(dfi_4_init_complete), // output wire dfi_4_init_complete + .dfi_4_out_rst_n(dfi_4_out_rst_n), // output wire dfi_4_out_rst_n + .dfi_5_dw_rddata_p0(dfi_5_dw_rddata_p0), // output wire [255 : 0] dfi_5_dw_rddata_p0 + .dfi_5_dw_rddata_dm_p0(dfi_5_dw_rddata_dm_p0), // output wire [31 : 0] dfi_5_dw_rddata_dm_p0 + .dfi_5_dw_rddata_dbi_p0(dfi_5_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_5_dw_rddata_dbi_p0 + .dfi_5_dw_rddata_par_p0(dfi_5_dw_rddata_par_p0), // output wire [7 : 0] dfi_5_dw_rddata_par_p0 + .dfi_5_dw_rddata_p1(dfi_5_dw_rddata_p1), // output wire [255 : 0] dfi_5_dw_rddata_p1 + .dfi_5_dw_rddata_dm_p1(dfi_5_dw_rddata_dm_p1), // output wire [31 : 0] dfi_5_dw_rddata_dm_p1 + .dfi_5_dw_rddata_dbi_p1(dfi_5_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_5_dw_rddata_dbi_p1 + .dfi_5_dw_rddata_par_p1(dfi_5_dw_rddata_par_p1), // output wire [7 : 0] dfi_5_dw_rddata_par_p1 + .dfi_5_dbi_byte_disable(dfi_5_dbi_byte_disable), // output wire [15 : 0] dfi_5_dbi_byte_disable + .dfi_5_dw_rddata_valid(dfi_5_dw_rddata_valid), // output wire [3 : 0] dfi_5_dw_rddata_valid + .dfi_5_dw_derr_n(dfi_5_dw_derr_n), // output wire [7 : 0] dfi_5_dw_derr_n + .dfi_5_aw_aerr_n(dfi_5_aw_aerr_n), // output wire [1 : 0] dfi_5_aw_aerr_n + .dfi_5_ctrlupd_req(dfi_5_ctrlupd_req), // output wire dfi_5_ctrlupd_req + .dfi_5_phyupd_ack(dfi_5_phyupd_ack), // output wire dfi_5_phyupd_ack + .dfi_5_clk_init(dfi_5_clk_init), // output wire dfi_5_clk_init + .dfi_5_init_complete(dfi_5_init_complete), // output wire dfi_5_init_complete + .dfi_5_out_rst_n(dfi_5_out_rst_n), // output wire dfi_5_out_rst_n + .dfi_6_dw_rddata_p0(dfi_6_dw_rddata_p0), // output wire [255 : 0] dfi_6_dw_rddata_p0 + .dfi_6_dw_rddata_dm_p0(dfi_6_dw_rddata_dm_p0), // output wire [31 : 0] dfi_6_dw_rddata_dm_p0 + .dfi_6_dw_rddata_dbi_p0(dfi_6_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_6_dw_rddata_dbi_p0 + .dfi_6_dw_rddata_par_p0(dfi_6_dw_rddata_par_p0), // output wire [7 : 0] dfi_6_dw_rddata_par_p0 + .dfi_6_dw_rddata_p1(dfi_6_dw_rddata_p1), // output wire [255 : 0] dfi_6_dw_rddata_p1 + .dfi_6_dw_rddata_dm_p1(dfi_6_dw_rddata_dm_p1), // output wire [31 : 0] dfi_6_dw_rddata_dm_p1 + .dfi_6_dw_rddata_dbi_p1(dfi_6_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_6_dw_rddata_dbi_p1 + .dfi_6_dw_rddata_par_p1(dfi_6_dw_rddata_par_p1), // output wire [7 : 0] dfi_6_dw_rddata_par_p1 + .dfi_6_dbi_byte_disable(dfi_6_dbi_byte_disable), // output wire [15 : 0] dfi_6_dbi_byte_disable + .dfi_6_dw_rddata_valid(dfi_6_dw_rddata_valid), // output wire [3 : 0] dfi_6_dw_rddata_valid + .dfi_6_dw_derr_n(dfi_6_dw_derr_n), // output wire [7 : 0] dfi_6_dw_derr_n + .dfi_6_aw_aerr_n(dfi_6_aw_aerr_n), // output wire [1 : 0] dfi_6_aw_aerr_n + .dfi_6_ctrlupd_req(dfi_6_ctrlupd_req), // output wire dfi_6_ctrlupd_req + .dfi_6_phyupd_ack(dfi_6_phyupd_ack), // output wire dfi_6_phyupd_ack + .dfi_6_clk_init(dfi_6_clk_init), // output wire dfi_6_clk_init + .dfi_6_init_complete(dfi_6_init_complete), // output wire dfi_6_init_complete + .dfi_6_out_rst_n(dfi_6_out_rst_n), // output wire dfi_6_out_rst_n + .dfi_7_dw_rddata_p0(dfi_7_dw_rddata_p0), // output wire [255 : 0] dfi_7_dw_rddata_p0 + .dfi_7_dw_rddata_dm_p0(dfi_7_dw_rddata_dm_p0), // output wire [31 : 0] dfi_7_dw_rddata_dm_p0 + .dfi_7_dw_rddata_dbi_p0(dfi_7_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_7_dw_rddata_dbi_p0 + .dfi_7_dw_rddata_par_p0(dfi_7_dw_rddata_par_p0), // output wire [7 : 0] dfi_7_dw_rddata_par_p0 + .dfi_7_dw_rddata_p1(dfi_7_dw_rddata_p1), // output wire [255 : 0] dfi_7_dw_rddata_p1 + .dfi_7_dw_rddata_dm_p1(dfi_7_dw_rddata_dm_p1), // output wire [31 : 0] dfi_7_dw_rddata_dm_p1 + .dfi_7_dw_rddata_dbi_p1(dfi_7_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_7_dw_rddata_dbi_p1 + .dfi_7_dw_rddata_par_p1(dfi_7_dw_rddata_par_p1), // output wire [7 : 0] dfi_7_dw_rddata_par_p1 + .dfi_7_dbi_byte_disable(dfi_7_dbi_byte_disable), // output wire [15 : 0] dfi_7_dbi_byte_disable + .dfi_7_dw_rddata_valid(dfi_7_dw_rddata_valid), // output wire [3 : 0] dfi_7_dw_rddata_valid + .dfi_7_dw_derr_n(dfi_7_dw_derr_n), // output wire [7 : 0] dfi_7_dw_derr_n + .dfi_7_aw_aerr_n(dfi_7_aw_aerr_n), // output wire [1 : 0] dfi_7_aw_aerr_n + .dfi_7_ctrlupd_req(dfi_7_ctrlupd_req), // output wire dfi_7_ctrlupd_req + .dfi_7_phyupd_ack(dfi_7_phyupd_ack), // output wire dfi_7_phyupd_ack + .dfi_7_clk_init(dfi_7_clk_init), // output wire dfi_7_clk_init + .dfi_7_init_complete(dfi_7_init_complete), // output wire dfi_7_init_complete + .dfi_7_out_rst_n(dfi_7_out_rst_n), // output wire dfi_7_out_rst_n + .dfi_8_dw_rddata_p0(dfi_8_dw_rddata_p0), // output wire [255 : 0] dfi_8_dw_rddata_p0 + .dfi_8_dw_rddata_dm_p0(dfi_8_dw_rddata_dm_p0), // output wire [31 : 0] dfi_8_dw_rddata_dm_p0 + .dfi_8_dw_rddata_dbi_p0(dfi_8_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_8_dw_rddata_dbi_p0 + .dfi_8_dw_rddata_par_p0(dfi_8_dw_rddata_par_p0), // output wire [7 : 0] dfi_8_dw_rddata_par_p0 + .dfi_8_dw_rddata_p1(dfi_8_dw_rddata_p1), // output wire [255 : 0] dfi_8_dw_rddata_p1 + .dfi_8_dw_rddata_dm_p1(dfi_8_dw_rddata_dm_p1), // output wire [31 : 0] dfi_8_dw_rddata_dm_p1 + .dfi_8_dw_rddata_dbi_p1(dfi_8_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_8_dw_rddata_dbi_p1 + .dfi_8_dw_rddata_par_p1(dfi_8_dw_rddata_par_p1), // output wire [7 : 0] dfi_8_dw_rddata_par_p1 + .dfi_8_dbi_byte_disable(dfi_8_dbi_byte_disable), // output wire [15 : 0] dfi_8_dbi_byte_disable + .dfi_8_dw_rddata_valid(dfi_8_dw_rddata_valid), // output wire [3 : 0] dfi_8_dw_rddata_valid + .dfi_8_dw_derr_n(dfi_8_dw_derr_n), // output wire [7 : 0] dfi_8_dw_derr_n + .dfi_8_aw_aerr_n(dfi_8_aw_aerr_n), // output wire [1 : 0] dfi_8_aw_aerr_n + .dfi_8_ctrlupd_req(dfi_8_ctrlupd_req), // output wire dfi_8_ctrlupd_req + .dfi_8_phyupd_ack(dfi_8_phyupd_ack), // output wire dfi_8_phyupd_ack + .dfi_8_clk_init(dfi_8_clk_init), // output wire dfi_8_clk_init + .dfi_8_init_complete(dfi_8_init_complete), // output wire dfi_8_init_complete + .dfi_8_out_rst_n(dfi_8_out_rst_n), // output wire dfi_8_out_rst_n + .dfi_9_dw_rddata_p0(dfi_9_dw_rddata_p0), // output wire [255 : 0] dfi_9_dw_rddata_p0 + .dfi_9_dw_rddata_dm_p0(dfi_9_dw_rddata_dm_p0), // output wire [31 : 0] dfi_9_dw_rddata_dm_p0 + .dfi_9_dw_rddata_dbi_p0(dfi_9_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_9_dw_rddata_dbi_p0 + .dfi_9_dw_rddata_par_p0(dfi_9_dw_rddata_par_p0), // output wire [7 : 0] dfi_9_dw_rddata_par_p0 + .dfi_9_dw_rddata_p1(dfi_9_dw_rddata_p1), // output wire [255 : 0] dfi_9_dw_rddata_p1 + .dfi_9_dw_rddata_dm_p1(dfi_9_dw_rddata_dm_p1), // output wire [31 : 0] dfi_9_dw_rddata_dm_p1 + .dfi_9_dw_rddata_dbi_p1(dfi_9_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_9_dw_rddata_dbi_p1 + .dfi_9_dw_rddata_par_p1(dfi_9_dw_rddata_par_p1), // output wire [7 : 0] dfi_9_dw_rddata_par_p1 + .dfi_9_dbi_byte_disable(dfi_9_dbi_byte_disable), // output wire [15 : 0] dfi_9_dbi_byte_disable + .dfi_9_dw_rddata_valid(dfi_9_dw_rddata_valid), // output wire [3 : 0] dfi_9_dw_rddata_valid + .dfi_9_dw_derr_n(dfi_9_dw_derr_n), // output wire [7 : 0] dfi_9_dw_derr_n + .dfi_9_aw_aerr_n(dfi_9_aw_aerr_n), // output wire [1 : 0] dfi_9_aw_aerr_n + .dfi_9_ctrlupd_req(dfi_9_ctrlupd_req), // output wire dfi_9_ctrlupd_req + .dfi_9_phyupd_ack(dfi_9_phyupd_ack), // output wire dfi_9_phyupd_ack + .dfi_9_clk_init(dfi_9_clk_init), // output wire dfi_9_clk_init + .dfi_9_init_complete(dfi_9_init_complete), // output wire dfi_9_init_complete + .dfi_9_out_rst_n(dfi_9_out_rst_n), // output wire dfi_9_out_rst_n + .dfi_10_dw_rddata_p0(dfi_10_dw_rddata_p0), // output wire [255 : 0] dfi_10_dw_rddata_p0 + .dfi_10_dw_rddata_dm_p0(dfi_10_dw_rddata_dm_p0), // output wire [31 : 0] dfi_10_dw_rddata_dm_p0 + .dfi_10_dw_rddata_dbi_p0(dfi_10_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_10_dw_rddata_dbi_p0 + .dfi_10_dw_rddata_par_p0(dfi_10_dw_rddata_par_p0), // output wire [7 : 0] dfi_10_dw_rddata_par_p0 + .dfi_10_dw_rddata_p1(dfi_10_dw_rddata_p1), // output wire [255 : 0] dfi_10_dw_rddata_p1 + .dfi_10_dw_rddata_dm_p1(dfi_10_dw_rddata_dm_p1), // output wire [31 : 0] dfi_10_dw_rddata_dm_p1 + .dfi_10_dw_rddata_dbi_p1(dfi_10_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_10_dw_rddata_dbi_p1 + .dfi_10_dw_rddata_par_p1(dfi_10_dw_rddata_par_p1), // output wire [7 : 0] dfi_10_dw_rddata_par_p1 + .dfi_10_dbi_byte_disable(dfi_10_dbi_byte_disable), // output wire [15 : 0] dfi_10_dbi_byte_disable + .dfi_10_dw_rddata_valid(dfi_10_dw_rddata_valid), // output wire [3 : 0] dfi_10_dw_rddata_valid + .dfi_10_dw_derr_n(dfi_10_dw_derr_n), // output wire [7 : 0] dfi_10_dw_derr_n + .dfi_10_aw_aerr_n(dfi_10_aw_aerr_n), // output wire [1 : 0] dfi_10_aw_aerr_n + .dfi_10_ctrlupd_req(dfi_10_ctrlupd_req), // output wire dfi_10_ctrlupd_req + .dfi_10_phyupd_ack(dfi_10_phyupd_ack), // output wire dfi_10_phyupd_ack + .dfi_10_clk_init(dfi_10_clk_init), // output wire dfi_10_clk_init + .dfi_10_init_complete(dfi_10_init_complete), // output wire dfi_10_init_complete + .dfi_10_out_rst_n(dfi_10_out_rst_n), // output wire dfi_10_out_rst_n + .dfi_11_dw_rddata_p0(dfi_11_dw_rddata_p0), // output wire [255 : 0] dfi_11_dw_rddata_p0 + .dfi_11_dw_rddata_dm_p0(dfi_11_dw_rddata_dm_p0), // output wire [31 : 0] dfi_11_dw_rddata_dm_p0 + .dfi_11_dw_rddata_dbi_p0(dfi_11_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_11_dw_rddata_dbi_p0 + .dfi_11_dw_rddata_par_p0(dfi_11_dw_rddata_par_p0), // output wire [7 : 0] dfi_11_dw_rddata_par_p0 + .dfi_11_dw_rddata_p1(dfi_11_dw_rddata_p1), // output wire [255 : 0] dfi_11_dw_rddata_p1 + .dfi_11_dw_rddata_dm_p1(dfi_11_dw_rddata_dm_p1), // output wire [31 : 0] dfi_11_dw_rddata_dm_p1 + .dfi_11_dw_rddata_dbi_p1(dfi_11_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_11_dw_rddata_dbi_p1 + .dfi_11_dw_rddata_par_p1(dfi_11_dw_rddata_par_p1), // output wire [7 : 0] dfi_11_dw_rddata_par_p1 + .dfi_11_dbi_byte_disable(dfi_11_dbi_byte_disable), // output wire [15 : 0] dfi_11_dbi_byte_disable + .dfi_11_dw_rddata_valid(dfi_11_dw_rddata_valid), // output wire [3 : 0] dfi_11_dw_rddata_valid + .dfi_11_dw_derr_n(dfi_11_dw_derr_n), // output wire [7 : 0] dfi_11_dw_derr_n + .dfi_11_aw_aerr_n(dfi_11_aw_aerr_n), // output wire [1 : 0] dfi_11_aw_aerr_n + .dfi_11_ctrlupd_req(dfi_11_ctrlupd_req), // output wire dfi_11_ctrlupd_req + .dfi_11_phyupd_ack(dfi_11_phyupd_ack), // output wire dfi_11_phyupd_ack + .dfi_11_clk_init(dfi_11_clk_init), // output wire dfi_11_clk_init + .dfi_11_init_complete(dfi_11_init_complete), // output wire dfi_11_init_complete + .dfi_11_out_rst_n(dfi_11_out_rst_n), // output wire dfi_11_out_rst_n + .dfi_12_dw_rddata_p0(dfi_12_dw_rddata_p0), // output wire [255 : 0] dfi_12_dw_rddata_p0 + .dfi_12_dw_rddata_dm_p0(dfi_12_dw_rddata_dm_p0), // output wire [31 : 0] dfi_12_dw_rddata_dm_p0 + .dfi_12_dw_rddata_dbi_p0(dfi_12_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_12_dw_rddata_dbi_p0 + .dfi_12_dw_rddata_par_p0(dfi_12_dw_rddata_par_p0), // output wire [7 : 0] dfi_12_dw_rddata_par_p0 + .dfi_12_dw_rddata_p1(dfi_12_dw_rddata_p1), // output wire [255 : 0] dfi_12_dw_rddata_p1 + .dfi_12_dw_rddata_dm_p1(dfi_12_dw_rddata_dm_p1), // output wire [31 : 0] dfi_12_dw_rddata_dm_p1 + .dfi_12_dw_rddata_dbi_p1(dfi_12_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_12_dw_rddata_dbi_p1 + .dfi_12_dw_rddata_par_p1(dfi_12_dw_rddata_par_p1), // output wire [7 : 0] dfi_12_dw_rddata_par_p1 + .dfi_12_dbi_byte_disable(dfi_12_dbi_byte_disable), // output wire [15 : 0] dfi_12_dbi_byte_disable + .dfi_12_dw_rddata_valid(dfi_12_dw_rddata_valid), // output wire [3 : 0] dfi_12_dw_rddata_valid + .dfi_12_dw_derr_n(dfi_12_dw_derr_n), // output wire [7 : 0] dfi_12_dw_derr_n + .dfi_12_aw_aerr_n(dfi_12_aw_aerr_n), // output wire [1 : 0] dfi_12_aw_aerr_n + .dfi_12_ctrlupd_req(dfi_12_ctrlupd_req), // output wire dfi_12_ctrlupd_req + .dfi_12_phyupd_ack(dfi_12_phyupd_ack), // output wire dfi_12_phyupd_ack + .dfi_12_clk_init(dfi_12_clk_init), // output wire dfi_12_clk_init + .dfi_12_init_complete(dfi_12_init_complete), // output wire dfi_12_init_complete + .dfi_12_out_rst_n(dfi_12_out_rst_n), // output wire dfi_12_out_rst_n + .dfi_13_dw_rddata_p0(dfi_13_dw_rddata_p0), // output wire [255 : 0] dfi_13_dw_rddata_p0 + .dfi_13_dw_rddata_dm_p0(dfi_13_dw_rddata_dm_p0), // output wire [31 : 0] dfi_13_dw_rddata_dm_p0 + .dfi_13_dw_rddata_dbi_p0(dfi_13_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_13_dw_rddata_dbi_p0 + .dfi_13_dw_rddata_par_p0(dfi_13_dw_rddata_par_p0), // output wire [7 : 0] dfi_13_dw_rddata_par_p0 + .dfi_13_dw_rddata_p1(dfi_13_dw_rddata_p1), // output wire [255 : 0] dfi_13_dw_rddata_p1 + .dfi_13_dw_rddata_dm_p1(dfi_13_dw_rddata_dm_p1), // output wire [31 : 0] dfi_13_dw_rddata_dm_p1 + .dfi_13_dw_rddata_dbi_p1(dfi_13_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_13_dw_rddata_dbi_p1 + .dfi_13_dw_rddata_par_p1(dfi_13_dw_rddata_par_p1), // output wire [7 : 0] dfi_13_dw_rddata_par_p1 + .dfi_13_dbi_byte_disable(dfi_13_dbi_byte_disable), // output wire [15 : 0] dfi_13_dbi_byte_disable + .dfi_13_dw_rddata_valid(dfi_13_dw_rddata_valid), // output wire [3 : 0] dfi_13_dw_rddata_valid + .dfi_13_dw_derr_n(dfi_13_dw_derr_n), // output wire [7 : 0] dfi_13_dw_derr_n + .dfi_13_aw_aerr_n(dfi_13_aw_aerr_n), // output wire [1 : 0] dfi_13_aw_aerr_n + .dfi_13_ctrlupd_req(dfi_13_ctrlupd_req), // output wire dfi_13_ctrlupd_req + .dfi_13_phyupd_ack(dfi_13_phyupd_ack), // output wire dfi_13_phyupd_ack + .dfi_13_clk_init(dfi_13_clk_init), // output wire dfi_13_clk_init + .dfi_13_init_complete(dfi_13_init_complete), // output wire dfi_13_init_complete + .dfi_13_out_rst_n(dfi_13_out_rst_n), // output wire dfi_13_out_rst_n + .dfi_14_dw_rddata_p0(dfi_14_dw_rddata_p0), // output wire [255 : 0] dfi_14_dw_rddata_p0 + .dfi_14_dw_rddata_dm_p0(dfi_14_dw_rddata_dm_p0), // output wire [31 : 0] dfi_14_dw_rddata_dm_p0 + .dfi_14_dw_rddata_dbi_p0(dfi_14_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_14_dw_rddata_dbi_p0 + .dfi_14_dw_rddata_par_p0(dfi_14_dw_rddata_par_p0), // output wire [7 : 0] dfi_14_dw_rddata_par_p0 + .dfi_14_dw_rddata_p1(dfi_14_dw_rddata_p1), // output wire [255 : 0] dfi_14_dw_rddata_p1 + .dfi_14_dw_rddata_dm_p1(dfi_14_dw_rddata_dm_p1), // output wire [31 : 0] dfi_14_dw_rddata_dm_p1 + .dfi_14_dw_rddata_dbi_p1(dfi_14_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_14_dw_rddata_dbi_p1 + .dfi_14_dw_rddata_par_p1(dfi_14_dw_rddata_par_p1), // output wire [7 : 0] dfi_14_dw_rddata_par_p1 + .dfi_14_dbi_byte_disable(dfi_14_dbi_byte_disable), // output wire [15 : 0] dfi_14_dbi_byte_disable + .dfi_14_dw_rddata_valid(dfi_14_dw_rddata_valid), // output wire [3 : 0] dfi_14_dw_rddata_valid + .dfi_14_dw_derr_n(dfi_14_dw_derr_n), // output wire [7 : 0] dfi_14_dw_derr_n + .dfi_14_aw_aerr_n(dfi_14_aw_aerr_n), // output wire [1 : 0] dfi_14_aw_aerr_n + .dfi_14_ctrlupd_req(dfi_14_ctrlupd_req), // output wire dfi_14_ctrlupd_req + .dfi_14_phyupd_ack(dfi_14_phyupd_ack), // output wire dfi_14_phyupd_ack + .dfi_14_clk_init(dfi_14_clk_init), // output wire dfi_14_clk_init + .dfi_14_init_complete(dfi_14_init_complete), // output wire dfi_14_init_complete + .dfi_14_out_rst_n(dfi_14_out_rst_n), // output wire dfi_14_out_rst_n + .dfi_15_dw_rddata_p0(dfi_15_dw_rddata_p0), // output wire [255 : 0] dfi_15_dw_rddata_p0 + .dfi_15_dw_rddata_dm_p0(dfi_15_dw_rddata_dm_p0), // output wire [31 : 0] dfi_15_dw_rddata_dm_p0 + .dfi_15_dw_rddata_dbi_p0(dfi_15_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_15_dw_rddata_dbi_p0 + .dfi_15_dw_rddata_par_p0(dfi_15_dw_rddata_par_p0), // output wire [7 : 0] dfi_15_dw_rddata_par_p0 + .dfi_15_dw_rddata_p1(dfi_15_dw_rddata_p1), // output wire [255 : 0] dfi_15_dw_rddata_p1 + .dfi_15_dw_rddata_dm_p1(dfi_15_dw_rddata_dm_p1), // output wire [31 : 0] dfi_15_dw_rddata_dm_p1 + .dfi_15_dw_rddata_dbi_p1(dfi_15_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_15_dw_rddata_dbi_p1 + .dfi_15_dw_rddata_par_p1(dfi_15_dw_rddata_par_p1), // output wire [7 : 0] dfi_15_dw_rddata_par_p1 + .dfi_15_dbi_byte_disable(dfi_15_dbi_byte_disable), // output wire [15 : 0] dfi_15_dbi_byte_disable + .dfi_15_dw_rddata_valid(dfi_15_dw_rddata_valid), // output wire [3 : 0] dfi_15_dw_rddata_valid + .dfi_15_dw_derr_n(dfi_15_dw_derr_n), // output wire [7 : 0] dfi_15_dw_derr_n + .dfi_15_aw_aerr_n(dfi_15_aw_aerr_n), // output wire [1 : 0] dfi_15_aw_aerr_n + .dfi_15_ctrlupd_req(dfi_15_ctrlupd_req), // output wire dfi_15_ctrlupd_req + .dfi_15_phyupd_ack(dfi_15_phyupd_ack), // output wire dfi_15_phyupd_ack + .dfi_15_clk_init(dfi_15_clk_init), // output wire dfi_15_clk_init + .dfi_15_init_complete(dfi_15_init_complete), // output wire dfi_15_init_complete + .dfi_15_out_rst_n(dfi_15_out_rst_n), // output wire dfi_15_out_rst_n + .apb_complete_0(apb_complete_0), // output wire apb_complete_0 + .apb_complete_1(apb_complete_1), // output wire apb_complete_1 + .DRAM_0_STAT_CATTRIP(DRAM_0_STAT_CATTRIP), // output wire DRAM_0_STAT_CATTRIP + .DRAM_0_STAT_TEMP(DRAM_0_STAT_TEMP), // output wire [6 : 0] DRAM_0_STAT_TEMP + .DRAM_1_STAT_CATTRIP(DRAM_1_STAT_CATTRIP), // output wire DRAM_1_STAT_CATTRIP + .DRAM_1_STAT_TEMP(DRAM_1_STAT_TEMP) // output wire [6 : 0] DRAM_1_STAT_TEMP +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file hbm_0.v when simulating +// the core, hbm_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.vho new file mode 100755 index 0000000..a1292d5 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.vho @@ -0,0 +1,1729 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:hbm:1.0 +-- IP Revision: 9 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT hbm_0 + PORT ( + HBM_REF_CLK_0 : IN STD_LOGIC; + HBM_REF_CLK_1 : IN STD_LOGIC; + dfi_0_clk : IN STD_LOGIC; + dfi_0_rst_n : IN STD_LOGIC; + dfi_0_init_start : IN STD_LOGIC; + dfi_0_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_0_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_0_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_0_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_0_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_0_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_0_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_0_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_0_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_0_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_0_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_aw_ck_dis : IN STD_LOGIC; + dfi_0_lp_pwr_e_req : IN STD_LOGIC; + dfi_0_lp_sr_e_req : IN STD_LOGIC; + dfi_0_lp_pwr_x_req : IN STD_LOGIC; + dfi_0_aw_tx_indx_ld : IN STD_LOGIC; + dfi_0_dw_tx_indx_ld : IN STD_LOGIC; + dfi_0_dw_rx_indx_ld : IN STD_LOGIC; + dfi_0_ctrlupd_ack : IN STD_LOGIC; + dfi_0_phyupd_req : IN STD_LOGIC; + dfi_0_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_clk : IN STD_LOGIC; + dfi_1_rst_n : IN STD_LOGIC; + dfi_1_init_start : IN STD_LOGIC; + dfi_1_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_1_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_1_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_1_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_1_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_1_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_1_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_1_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_1_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_1_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_1_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_aw_ck_dis : IN STD_LOGIC; + dfi_1_lp_pwr_e_req : IN STD_LOGIC; + dfi_1_lp_sr_e_req : IN STD_LOGIC; + dfi_1_lp_pwr_x_req : IN STD_LOGIC; + dfi_1_aw_tx_indx_ld : IN STD_LOGIC; + dfi_1_dw_tx_indx_ld : IN STD_LOGIC; + dfi_1_dw_rx_indx_ld : IN STD_LOGIC; + dfi_1_ctrlupd_ack : IN STD_LOGIC; + dfi_1_phyupd_req : IN STD_LOGIC; + dfi_1_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_clk : IN STD_LOGIC; + dfi_2_rst_n : IN STD_LOGIC; + dfi_2_init_start : IN STD_LOGIC; + dfi_2_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_2_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_2_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_2_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_2_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_2_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_2_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_2_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_2_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_2_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_2_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_aw_ck_dis : IN STD_LOGIC; + dfi_2_lp_pwr_e_req : IN STD_LOGIC; + dfi_2_lp_sr_e_req : IN STD_LOGIC; + dfi_2_lp_pwr_x_req : IN STD_LOGIC; + dfi_2_aw_tx_indx_ld : IN STD_LOGIC; + dfi_2_dw_tx_indx_ld : IN STD_LOGIC; + dfi_2_dw_rx_indx_ld : IN STD_LOGIC; + dfi_2_ctrlupd_ack : IN STD_LOGIC; + dfi_2_phyupd_req : IN STD_LOGIC; + dfi_2_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_clk : IN STD_LOGIC; + dfi_3_rst_n : IN STD_LOGIC; + dfi_3_init_start : IN STD_LOGIC; + dfi_3_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_3_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_3_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_3_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_3_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_3_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_3_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_3_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_3_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_3_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_3_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_aw_ck_dis : IN STD_LOGIC; + dfi_3_lp_pwr_e_req : IN STD_LOGIC; + dfi_3_lp_sr_e_req : IN STD_LOGIC; + dfi_3_lp_pwr_x_req : IN STD_LOGIC; + dfi_3_aw_tx_indx_ld : IN STD_LOGIC; + dfi_3_dw_tx_indx_ld : IN STD_LOGIC; + dfi_3_dw_rx_indx_ld : IN STD_LOGIC; + dfi_3_ctrlupd_ack : IN STD_LOGIC; + dfi_3_phyupd_req : IN STD_LOGIC; + dfi_3_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_clk : IN STD_LOGIC; + dfi_4_rst_n : IN STD_LOGIC; + dfi_4_init_start : IN STD_LOGIC; + dfi_4_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_4_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_4_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_4_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_4_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_4_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_4_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_4_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_4_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_4_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_4_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_aw_ck_dis : IN STD_LOGIC; + dfi_4_lp_pwr_e_req : IN STD_LOGIC; + dfi_4_lp_sr_e_req : IN STD_LOGIC; + dfi_4_lp_pwr_x_req : IN STD_LOGIC; + dfi_4_aw_tx_indx_ld : IN STD_LOGIC; + dfi_4_dw_tx_indx_ld : IN STD_LOGIC; + dfi_4_dw_rx_indx_ld : IN STD_LOGIC; + dfi_4_ctrlupd_ack : IN STD_LOGIC; + dfi_4_phyupd_req : IN STD_LOGIC; + dfi_4_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_clk : IN STD_LOGIC; + dfi_5_rst_n : IN STD_LOGIC; + dfi_5_init_start : IN STD_LOGIC; + dfi_5_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_5_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_5_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_5_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_5_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_5_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_5_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_5_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_5_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_5_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_5_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_aw_ck_dis : IN STD_LOGIC; + dfi_5_lp_pwr_e_req : IN STD_LOGIC; + dfi_5_lp_sr_e_req : IN STD_LOGIC; + dfi_5_lp_pwr_x_req : IN STD_LOGIC; + dfi_5_aw_tx_indx_ld : IN STD_LOGIC; + dfi_5_dw_tx_indx_ld : IN STD_LOGIC; + dfi_5_dw_rx_indx_ld : IN STD_LOGIC; + dfi_5_ctrlupd_ack : IN STD_LOGIC; + dfi_5_phyupd_req : IN STD_LOGIC; + dfi_5_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_clk : IN STD_LOGIC; + dfi_6_rst_n : IN STD_LOGIC; + dfi_6_init_start : IN STD_LOGIC; + dfi_6_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_6_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_6_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_6_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_6_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_6_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_6_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_6_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_6_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_6_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_6_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_aw_ck_dis : IN STD_LOGIC; + dfi_6_lp_pwr_e_req : IN STD_LOGIC; + dfi_6_lp_sr_e_req : IN STD_LOGIC; + dfi_6_lp_pwr_x_req : IN STD_LOGIC; + dfi_6_aw_tx_indx_ld : IN STD_LOGIC; + dfi_6_dw_tx_indx_ld : IN STD_LOGIC; + dfi_6_dw_rx_indx_ld : IN STD_LOGIC; + dfi_6_ctrlupd_ack : IN STD_LOGIC; + dfi_6_phyupd_req : IN STD_LOGIC; + dfi_6_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_clk : IN STD_LOGIC; + dfi_7_rst_n : IN STD_LOGIC; + dfi_7_init_start : IN STD_LOGIC; + dfi_7_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_7_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_7_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_7_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_7_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_7_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_7_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_7_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_7_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_7_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_7_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_aw_ck_dis : IN STD_LOGIC; + dfi_7_lp_pwr_e_req : IN STD_LOGIC; + dfi_7_lp_sr_e_req : IN STD_LOGIC; + dfi_7_lp_pwr_x_req : IN STD_LOGIC; + dfi_7_aw_tx_indx_ld : IN STD_LOGIC; + dfi_7_dw_tx_indx_ld : IN STD_LOGIC; + dfi_7_dw_rx_indx_ld : IN STD_LOGIC; + dfi_7_ctrlupd_ack : IN STD_LOGIC; + dfi_7_phyupd_req : IN STD_LOGIC; + dfi_7_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_clk : IN STD_LOGIC; + dfi_8_rst_n : IN STD_LOGIC; + dfi_8_init_start : IN STD_LOGIC; + dfi_8_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_8_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_8_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_8_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_8_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_8_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_8_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_8_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_8_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_8_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_8_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_aw_ck_dis : IN STD_LOGIC; + dfi_8_lp_pwr_e_req : IN STD_LOGIC; + dfi_8_lp_sr_e_req : IN STD_LOGIC; + dfi_8_lp_pwr_x_req : IN STD_LOGIC; + dfi_8_aw_tx_indx_ld : IN STD_LOGIC; + dfi_8_dw_tx_indx_ld : IN STD_LOGIC; + dfi_8_dw_rx_indx_ld : IN STD_LOGIC; + dfi_8_ctrlupd_ack : IN STD_LOGIC; + dfi_8_phyupd_req : IN STD_LOGIC; + dfi_8_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_clk : IN STD_LOGIC; + dfi_9_rst_n : IN STD_LOGIC; + dfi_9_init_start : IN STD_LOGIC; + dfi_9_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_9_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_9_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_9_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_9_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_9_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_9_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_9_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_9_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_9_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_9_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_aw_ck_dis : IN STD_LOGIC; + dfi_9_lp_pwr_e_req : IN STD_LOGIC; + dfi_9_lp_sr_e_req : IN STD_LOGIC; + dfi_9_lp_pwr_x_req : IN STD_LOGIC; + dfi_9_aw_tx_indx_ld : IN STD_LOGIC; + dfi_9_dw_tx_indx_ld : IN STD_LOGIC; + dfi_9_dw_rx_indx_ld : IN STD_LOGIC; + dfi_9_ctrlupd_ack : IN STD_LOGIC; + dfi_9_phyupd_req : IN STD_LOGIC; + dfi_9_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_clk : IN STD_LOGIC; + dfi_10_rst_n : IN STD_LOGIC; + dfi_10_init_start : IN STD_LOGIC; + dfi_10_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_10_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_10_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_10_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_10_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_10_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_10_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_10_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_10_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_10_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_10_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_aw_ck_dis : IN STD_LOGIC; + dfi_10_lp_pwr_e_req : IN STD_LOGIC; + dfi_10_lp_sr_e_req : IN STD_LOGIC; + dfi_10_lp_pwr_x_req : IN STD_LOGIC; + dfi_10_aw_tx_indx_ld : IN STD_LOGIC; + dfi_10_dw_tx_indx_ld : IN STD_LOGIC; + dfi_10_dw_rx_indx_ld : IN STD_LOGIC; + dfi_10_ctrlupd_ack : IN STD_LOGIC; + dfi_10_phyupd_req : IN STD_LOGIC; + dfi_10_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_clk : IN STD_LOGIC; + dfi_11_rst_n : IN STD_LOGIC; + dfi_11_init_start : IN STD_LOGIC; + dfi_11_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_11_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_11_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_11_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_11_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_11_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_11_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_11_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_11_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_11_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_11_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_aw_ck_dis : IN STD_LOGIC; + dfi_11_lp_pwr_e_req : IN STD_LOGIC; + dfi_11_lp_sr_e_req : IN STD_LOGIC; + dfi_11_lp_pwr_x_req : IN STD_LOGIC; + dfi_11_aw_tx_indx_ld : IN STD_LOGIC; + dfi_11_dw_tx_indx_ld : IN STD_LOGIC; + dfi_11_dw_rx_indx_ld : IN STD_LOGIC; + dfi_11_ctrlupd_ack : IN STD_LOGIC; + dfi_11_phyupd_req : IN STD_LOGIC; + dfi_11_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_clk : IN STD_LOGIC; + dfi_12_rst_n : IN STD_LOGIC; + dfi_12_init_start : IN STD_LOGIC; + dfi_12_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_12_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_12_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_12_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_12_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_12_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_12_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_12_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_12_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_12_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_12_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_aw_ck_dis : IN STD_LOGIC; + dfi_12_lp_pwr_e_req : IN STD_LOGIC; + dfi_12_lp_sr_e_req : IN STD_LOGIC; + dfi_12_lp_pwr_x_req : IN STD_LOGIC; + dfi_12_aw_tx_indx_ld : IN STD_LOGIC; + dfi_12_dw_tx_indx_ld : IN STD_LOGIC; + dfi_12_dw_rx_indx_ld : IN STD_LOGIC; + dfi_12_ctrlupd_ack : IN STD_LOGIC; + dfi_12_phyupd_req : IN STD_LOGIC; + dfi_12_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_clk : IN STD_LOGIC; + dfi_13_rst_n : IN STD_LOGIC; + dfi_13_init_start : IN STD_LOGIC; + dfi_13_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_13_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_13_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_13_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_13_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_13_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_13_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_13_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_13_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_13_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_13_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_aw_ck_dis : IN STD_LOGIC; + dfi_13_lp_pwr_e_req : IN STD_LOGIC; + dfi_13_lp_sr_e_req : IN STD_LOGIC; + dfi_13_lp_pwr_x_req : IN STD_LOGIC; + dfi_13_aw_tx_indx_ld : IN STD_LOGIC; + dfi_13_dw_tx_indx_ld : IN STD_LOGIC; + dfi_13_dw_rx_indx_ld : IN STD_LOGIC; + dfi_13_ctrlupd_ack : IN STD_LOGIC; + dfi_13_phyupd_req : IN STD_LOGIC; + dfi_13_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_clk : IN STD_LOGIC; + dfi_14_rst_n : IN STD_LOGIC; + dfi_14_init_start : IN STD_LOGIC; + dfi_14_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_14_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_14_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_14_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_14_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_14_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_14_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_14_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_14_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_14_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_14_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_aw_ck_dis : IN STD_LOGIC; + dfi_14_lp_pwr_e_req : IN STD_LOGIC; + dfi_14_lp_sr_e_req : IN STD_LOGIC; + dfi_14_lp_pwr_x_req : IN STD_LOGIC; + dfi_14_aw_tx_indx_ld : IN STD_LOGIC; + dfi_14_dw_tx_indx_ld : IN STD_LOGIC; + dfi_14_dw_rx_indx_ld : IN STD_LOGIC; + dfi_14_ctrlupd_ack : IN STD_LOGIC; + dfi_14_phyupd_req : IN STD_LOGIC; + dfi_14_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_clk : IN STD_LOGIC; + dfi_15_rst_n : IN STD_LOGIC; + dfi_15_init_start : IN STD_LOGIC; + dfi_15_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_15_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_15_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_15_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_15_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_15_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_15_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_15_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_15_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_15_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_15_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_aw_ck_dis : IN STD_LOGIC; + dfi_15_lp_pwr_e_req : IN STD_LOGIC; + dfi_15_lp_sr_e_req : IN STD_LOGIC; + dfi_15_lp_pwr_x_req : IN STD_LOGIC; + dfi_15_aw_tx_indx_ld : IN STD_LOGIC; + dfi_15_dw_tx_indx_ld : IN STD_LOGIC; + dfi_15_dw_rx_indx_ld : IN STD_LOGIC; + dfi_15_ctrlupd_ack : IN STD_LOGIC; + dfi_15_phyupd_req : IN STD_LOGIC; + dfi_15_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + APB_0_PCLK : IN STD_LOGIC; + APB_0_PRESET_N : IN STD_LOGIC; + APB_1_PCLK : IN STD_LOGIC; + APB_1_PRESET_N : IN STD_LOGIC; + dfi_0_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_0_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_0_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_0_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_0_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_0_ctrlupd_req : OUT STD_LOGIC; + dfi_0_phyupd_ack : OUT STD_LOGIC; + dfi_0_clk_init : OUT STD_LOGIC; + dfi_0_init_complete : OUT STD_LOGIC; + dfi_0_out_rst_n : OUT STD_LOGIC; + dfi_1_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_1_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_1_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_1_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_1_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_1_ctrlupd_req : OUT STD_LOGIC; + dfi_1_phyupd_ack : OUT STD_LOGIC; + dfi_1_clk_init : OUT STD_LOGIC; + dfi_1_init_complete : OUT STD_LOGIC; + dfi_1_out_rst_n : OUT STD_LOGIC; + dfi_2_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_2_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_2_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_2_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_2_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_2_ctrlupd_req : OUT STD_LOGIC; + dfi_2_phyupd_ack : OUT STD_LOGIC; + dfi_2_clk_init : OUT STD_LOGIC; + dfi_2_init_complete : OUT STD_LOGIC; + dfi_2_out_rst_n : OUT STD_LOGIC; + dfi_3_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_3_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_3_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_3_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_3_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_3_ctrlupd_req : OUT STD_LOGIC; + dfi_3_phyupd_ack : OUT STD_LOGIC; + dfi_3_clk_init : OUT STD_LOGIC; + dfi_3_init_complete : OUT STD_LOGIC; + dfi_3_out_rst_n : OUT STD_LOGIC; + dfi_4_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_4_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_4_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_4_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_4_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_4_ctrlupd_req : OUT STD_LOGIC; + dfi_4_phyupd_ack : OUT STD_LOGIC; + dfi_4_clk_init : OUT STD_LOGIC; + dfi_4_init_complete : OUT STD_LOGIC; + dfi_4_out_rst_n : OUT STD_LOGIC; + dfi_5_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_5_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_5_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_5_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_5_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_5_ctrlupd_req : OUT STD_LOGIC; + dfi_5_phyupd_ack : OUT STD_LOGIC; + dfi_5_clk_init : OUT STD_LOGIC; + dfi_5_init_complete : OUT STD_LOGIC; + dfi_5_out_rst_n : OUT STD_LOGIC; + dfi_6_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_6_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_6_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_6_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_6_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_6_ctrlupd_req : OUT STD_LOGIC; + dfi_6_phyupd_ack : OUT STD_LOGIC; + dfi_6_clk_init : OUT STD_LOGIC; + dfi_6_init_complete : OUT STD_LOGIC; + dfi_6_out_rst_n : OUT STD_LOGIC; + dfi_7_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_7_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_7_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_7_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_7_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_7_ctrlupd_req : OUT STD_LOGIC; + dfi_7_phyupd_ack : OUT STD_LOGIC; + dfi_7_clk_init : OUT STD_LOGIC; + dfi_7_init_complete : OUT STD_LOGIC; + dfi_7_out_rst_n : OUT STD_LOGIC; + dfi_8_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_8_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_8_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_8_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_8_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_8_ctrlupd_req : OUT STD_LOGIC; + dfi_8_phyupd_ack : OUT STD_LOGIC; + dfi_8_clk_init : OUT STD_LOGIC; + dfi_8_init_complete : OUT STD_LOGIC; + dfi_8_out_rst_n : OUT STD_LOGIC; + dfi_9_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_9_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_9_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_9_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_9_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_9_ctrlupd_req : OUT STD_LOGIC; + dfi_9_phyupd_ack : OUT STD_LOGIC; + dfi_9_clk_init : OUT STD_LOGIC; + dfi_9_init_complete : OUT STD_LOGIC; + dfi_9_out_rst_n : OUT STD_LOGIC; + dfi_10_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_10_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_10_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_10_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_10_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_10_ctrlupd_req : OUT STD_LOGIC; + dfi_10_phyupd_ack : OUT STD_LOGIC; + dfi_10_clk_init : OUT STD_LOGIC; + dfi_10_init_complete : OUT STD_LOGIC; + dfi_10_out_rst_n : OUT STD_LOGIC; + dfi_11_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_11_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_11_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_11_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_11_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_11_ctrlupd_req : OUT STD_LOGIC; + dfi_11_phyupd_ack : OUT STD_LOGIC; + dfi_11_clk_init : OUT STD_LOGIC; + dfi_11_init_complete : OUT STD_LOGIC; + dfi_11_out_rst_n : OUT STD_LOGIC; + dfi_12_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_12_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_12_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_12_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_12_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_12_ctrlupd_req : OUT STD_LOGIC; + dfi_12_phyupd_ack : OUT STD_LOGIC; + dfi_12_clk_init : OUT STD_LOGIC; + dfi_12_init_complete : OUT STD_LOGIC; + dfi_12_out_rst_n : OUT STD_LOGIC; + dfi_13_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_13_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_13_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_13_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_13_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_13_ctrlupd_req : OUT STD_LOGIC; + dfi_13_phyupd_ack : OUT STD_LOGIC; + dfi_13_clk_init : OUT STD_LOGIC; + dfi_13_init_complete : OUT STD_LOGIC; + dfi_13_out_rst_n : OUT STD_LOGIC; + dfi_14_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_14_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_14_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_14_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_14_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_14_ctrlupd_req : OUT STD_LOGIC; + dfi_14_phyupd_ack : OUT STD_LOGIC; + dfi_14_clk_init : OUT STD_LOGIC; + dfi_14_init_complete : OUT STD_LOGIC; + dfi_14_out_rst_n : OUT STD_LOGIC; + dfi_15_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_15_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_15_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_15_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_15_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_15_ctrlupd_req : OUT STD_LOGIC; + dfi_15_phyupd_ack : OUT STD_LOGIC; + dfi_15_clk_init : OUT STD_LOGIC; + dfi_15_init_complete : OUT STD_LOGIC; + dfi_15_out_rst_n : OUT STD_LOGIC; + apb_complete_0 : OUT STD_LOGIC; + apb_complete_1 : OUT STD_LOGIC; + DRAM_0_STAT_CATTRIP : OUT STD_LOGIC; + DRAM_0_STAT_TEMP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); + DRAM_1_STAT_CATTRIP : OUT STD_LOGIC; + DRAM_1_STAT_TEMP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : hbm_0 + PORT MAP ( + HBM_REF_CLK_0 => HBM_REF_CLK_0, + HBM_REF_CLK_1 => HBM_REF_CLK_1, + dfi_0_clk => dfi_0_clk, + dfi_0_rst_n => dfi_0_rst_n, + dfi_0_init_start => dfi_0_init_start, + dfi_0_aw_ck_p0 => dfi_0_aw_ck_p0, + dfi_0_aw_cke_p0 => dfi_0_aw_cke_p0, + dfi_0_aw_row_p0 => dfi_0_aw_row_p0, + dfi_0_aw_col_p0 => dfi_0_aw_col_p0, + dfi_0_dw_wrdata_p0 => dfi_0_dw_wrdata_p0, + dfi_0_dw_wrdata_mask_p0 => dfi_0_dw_wrdata_mask_p0, + dfi_0_dw_wrdata_dbi_p0 => dfi_0_dw_wrdata_dbi_p0, + dfi_0_dw_wrdata_par_p0 => dfi_0_dw_wrdata_par_p0, + dfi_0_dw_wrdata_dq_en_p0 => dfi_0_dw_wrdata_dq_en_p0, + dfi_0_dw_wrdata_par_en_p0 => dfi_0_dw_wrdata_par_en_p0, + dfi_0_aw_ck_p1 => dfi_0_aw_ck_p1, + dfi_0_aw_cke_p1 => dfi_0_aw_cke_p1, + dfi_0_aw_row_p1 => dfi_0_aw_row_p1, + dfi_0_aw_col_p1 => dfi_0_aw_col_p1, + dfi_0_dw_wrdata_p1 => dfi_0_dw_wrdata_p1, + dfi_0_dw_wrdata_mask_p1 => dfi_0_dw_wrdata_mask_p1, + dfi_0_dw_wrdata_dbi_p1 => dfi_0_dw_wrdata_dbi_p1, + dfi_0_dw_wrdata_par_p1 => dfi_0_dw_wrdata_par_p1, + dfi_0_dw_wrdata_dq_en_p1 => dfi_0_dw_wrdata_dq_en_p1, + dfi_0_dw_wrdata_par_en_p1 => dfi_0_dw_wrdata_par_en_p1, + dfi_0_aw_ck_dis => dfi_0_aw_ck_dis, + dfi_0_lp_pwr_e_req => dfi_0_lp_pwr_e_req, + dfi_0_lp_sr_e_req => dfi_0_lp_sr_e_req, + dfi_0_lp_pwr_x_req => dfi_0_lp_pwr_x_req, + dfi_0_aw_tx_indx_ld => dfi_0_aw_tx_indx_ld, + dfi_0_dw_tx_indx_ld => dfi_0_dw_tx_indx_ld, + dfi_0_dw_rx_indx_ld => dfi_0_dw_rx_indx_ld, + dfi_0_ctrlupd_ack => dfi_0_ctrlupd_ack, + dfi_0_phyupd_req => dfi_0_phyupd_req, + dfi_0_dw_wrdata_dqs_p0 => dfi_0_dw_wrdata_dqs_p0, + dfi_0_dw_wrdata_dqs_p1 => dfi_0_dw_wrdata_dqs_p1, + dfi_1_clk => dfi_1_clk, + dfi_1_rst_n => dfi_1_rst_n, + dfi_1_init_start => dfi_1_init_start, + dfi_1_aw_ck_p0 => dfi_1_aw_ck_p0, + dfi_1_aw_cke_p0 => dfi_1_aw_cke_p0, + dfi_1_aw_row_p0 => dfi_1_aw_row_p0, + dfi_1_aw_col_p0 => dfi_1_aw_col_p0, + dfi_1_dw_wrdata_p0 => dfi_1_dw_wrdata_p0, + dfi_1_dw_wrdata_mask_p0 => dfi_1_dw_wrdata_mask_p0, + dfi_1_dw_wrdata_dbi_p0 => dfi_1_dw_wrdata_dbi_p0, + dfi_1_dw_wrdata_par_p0 => dfi_1_dw_wrdata_par_p0, + dfi_1_dw_wrdata_dq_en_p0 => dfi_1_dw_wrdata_dq_en_p0, + dfi_1_dw_wrdata_par_en_p0 => dfi_1_dw_wrdata_par_en_p0, + dfi_1_aw_ck_p1 => dfi_1_aw_ck_p1, + dfi_1_aw_cke_p1 => dfi_1_aw_cke_p1, + dfi_1_aw_row_p1 => dfi_1_aw_row_p1, + dfi_1_aw_col_p1 => dfi_1_aw_col_p1, + dfi_1_dw_wrdata_p1 => dfi_1_dw_wrdata_p1, + dfi_1_dw_wrdata_mask_p1 => dfi_1_dw_wrdata_mask_p1, + dfi_1_dw_wrdata_dbi_p1 => dfi_1_dw_wrdata_dbi_p1, + dfi_1_dw_wrdata_par_p1 => dfi_1_dw_wrdata_par_p1, + dfi_1_dw_wrdata_dq_en_p1 => dfi_1_dw_wrdata_dq_en_p1, + dfi_1_dw_wrdata_par_en_p1 => dfi_1_dw_wrdata_par_en_p1, + dfi_1_aw_ck_dis => dfi_1_aw_ck_dis, + dfi_1_lp_pwr_e_req => dfi_1_lp_pwr_e_req, + dfi_1_lp_sr_e_req => dfi_1_lp_sr_e_req, + dfi_1_lp_pwr_x_req => dfi_1_lp_pwr_x_req, + dfi_1_aw_tx_indx_ld => dfi_1_aw_tx_indx_ld, + dfi_1_dw_tx_indx_ld => dfi_1_dw_tx_indx_ld, + dfi_1_dw_rx_indx_ld => dfi_1_dw_rx_indx_ld, + dfi_1_ctrlupd_ack => dfi_1_ctrlupd_ack, + dfi_1_phyupd_req => dfi_1_phyupd_req, + dfi_1_dw_wrdata_dqs_p0 => dfi_1_dw_wrdata_dqs_p0, + dfi_1_dw_wrdata_dqs_p1 => dfi_1_dw_wrdata_dqs_p1, + dfi_2_clk => dfi_2_clk, + dfi_2_rst_n => dfi_2_rst_n, + dfi_2_init_start => dfi_2_init_start, + dfi_2_aw_ck_p0 => dfi_2_aw_ck_p0, + dfi_2_aw_cke_p0 => dfi_2_aw_cke_p0, + dfi_2_aw_row_p0 => dfi_2_aw_row_p0, + dfi_2_aw_col_p0 => dfi_2_aw_col_p0, + dfi_2_dw_wrdata_p0 => dfi_2_dw_wrdata_p0, + dfi_2_dw_wrdata_mask_p0 => dfi_2_dw_wrdata_mask_p0, + dfi_2_dw_wrdata_dbi_p0 => dfi_2_dw_wrdata_dbi_p0, + dfi_2_dw_wrdata_par_p0 => dfi_2_dw_wrdata_par_p0, + dfi_2_dw_wrdata_dq_en_p0 => dfi_2_dw_wrdata_dq_en_p0, + dfi_2_dw_wrdata_par_en_p0 => dfi_2_dw_wrdata_par_en_p0, + dfi_2_aw_ck_p1 => dfi_2_aw_ck_p1, + dfi_2_aw_cke_p1 => dfi_2_aw_cke_p1, + dfi_2_aw_row_p1 => dfi_2_aw_row_p1, + dfi_2_aw_col_p1 => dfi_2_aw_col_p1, + dfi_2_dw_wrdata_p1 => dfi_2_dw_wrdata_p1, + dfi_2_dw_wrdata_mask_p1 => dfi_2_dw_wrdata_mask_p1, + dfi_2_dw_wrdata_dbi_p1 => dfi_2_dw_wrdata_dbi_p1, + dfi_2_dw_wrdata_par_p1 => dfi_2_dw_wrdata_par_p1, + dfi_2_dw_wrdata_dq_en_p1 => dfi_2_dw_wrdata_dq_en_p1, + dfi_2_dw_wrdata_par_en_p1 => dfi_2_dw_wrdata_par_en_p1, + dfi_2_aw_ck_dis => dfi_2_aw_ck_dis, + dfi_2_lp_pwr_e_req => dfi_2_lp_pwr_e_req, + dfi_2_lp_sr_e_req => dfi_2_lp_sr_e_req, + dfi_2_lp_pwr_x_req => dfi_2_lp_pwr_x_req, + dfi_2_aw_tx_indx_ld => dfi_2_aw_tx_indx_ld, + dfi_2_dw_tx_indx_ld => dfi_2_dw_tx_indx_ld, + dfi_2_dw_rx_indx_ld => dfi_2_dw_rx_indx_ld, + dfi_2_ctrlupd_ack => dfi_2_ctrlupd_ack, + dfi_2_phyupd_req => dfi_2_phyupd_req, + dfi_2_dw_wrdata_dqs_p0 => dfi_2_dw_wrdata_dqs_p0, + dfi_2_dw_wrdata_dqs_p1 => dfi_2_dw_wrdata_dqs_p1, + dfi_3_clk => dfi_3_clk, + dfi_3_rst_n => dfi_3_rst_n, + dfi_3_init_start => dfi_3_init_start, + dfi_3_aw_ck_p0 => dfi_3_aw_ck_p0, + dfi_3_aw_cke_p0 => dfi_3_aw_cke_p0, + dfi_3_aw_row_p0 => dfi_3_aw_row_p0, + dfi_3_aw_col_p0 => dfi_3_aw_col_p0, + dfi_3_dw_wrdata_p0 => dfi_3_dw_wrdata_p0, + dfi_3_dw_wrdata_mask_p0 => dfi_3_dw_wrdata_mask_p0, + dfi_3_dw_wrdata_dbi_p0 => dfi_3_dw_wrdata_dbi_p0, + dfi_3_dw_wrdata_par_p0 => dfi_3_dw_wrdata_par_p0, + dfi_3_dw_wrdata_dq_en_p0 => dfi_3_dw_wrdata_dq_en_p0, + dfi_3_dw_wrdata_par_en_p0 => dfi_3_dw_wrdata_par_en_p0, + dfi_3_aw_ck_p1 => dfi_3_aw_ck_p1, + dfi_3_aw_cke_p1 => dfi_3_aw_cke_p1, + dfi_3_aw_row_p1 => dfi_3_aw_row_p1, + dfi_3_aw_col_p1 => dfi_3_aw_col_p1, + dfi_3_dw_wrdata_p1 => dfi_3_dw_wrdata_p1, + dfi_3_dw_wrdata_mask_p1 => dfi_3_dw_wrdata_mask_p1, + dfi_3_dw_wrdata_dbi_p1 => dfi_3_dw_wrdata_dbi_p1, + dfi_3_dw_wrdata_par_p1 => dfi_3_dw_wrdata_par_p1, + dfi_3_dw_wrdata_dq_en_p1 => dfi_3_dw_wrdata_dq_en_p1, + dfi_3_dw_wrdata_par_en_p1 => dfi_3_dw_wrdata_par_en_p1, + dfi_3_aw_ck_dis => dfi_3_aw_ck_dis, + dfi_3_lp_pwr_e_req => dfi_3_lp_pwr_e_req, + dfi_3_lp_sr_e_req => dfi_3_lp_sr_e_req, + dfi_3_lp_pwr_x_req => dfi_3_lp_pwr_x_req, + dfi_3_aw_tx_indx_ld => dfi_3_aw_tx_indx_ld, + dfi_3_dw_tx_indx_ld => dfi_3_dw_tx_indx_ld, + dfi_3_dw_rx_indx_ld => dfi_3_dw_rx_indx_ld, + dfi_3_ctrlupd_ack => dfi_3_ctrlupd_ack, + dfi_3_phyupd_req => dfi_3_phyupd_req, + dfi_3_dw_wrdata_dqs_p0 => dfi_3_dw_wrdata_dqs_p0, + dfi_3_dw_wrdata_dqs_p1 => dfi_3_dw_wrdata_dqs_p1, + dfi_4_clk => dfi_4_clk, + dfi_4_rst_n => dfi_4_rst_n, + dfi_4_init_start => dfi_4_init_start, + dfi_4_aw_ck_p0 => dfi_4_aw_ck_p0, + dfi_4_aw_cke_p0 => dfi_4_aw_cke_p0, + dfi_4_aw_row_p0 => dfi_4_aw_row_p0, + dfi_4_aw_col_p0 => dfi_4_aw_col_p0, + dfi_4_dw_wrdata_p0 => dfi_4_dw_wrdata_p0, + dfi_4_dw_wrdata_mask_p0 => dfi_4_dw_wrdata_mask_p0, + dfi_4_dw_wrdata_dbi_p0 => dfi_4_dw_wrdata_dbi_p0, + dfi_4_dw_wrdata_par_p0 => dfi_4_dw_wrdata_par_p0, + dfi_4_dw_wrdata_dq_en_p0 => dfi_4_dw_wrdata_dq_en_p0, + dfi_4_dw_wrdata_par_en_p0 => dfi_4_dw_wrdata_par_en_p0, + dfi_4_aw_ck_p1 => dfi_4_aw_ck_p1, + dfi_4_aw_cke_p1 => dfi_4_aw_cke_p1, + dfi_4_aw_row_p1 => dfi_4_aw_row_p1, + dfi_4_aw_col_p1 => dfi_4_aw_col_p1, + dfi_4_dw_wrdata_p1 => dfi_4_dw_wrdata_p1, + dfi_4_dw_wrdata_mask_p1 => dfi_4_dw_wrdata_mask_p1, + dfi_4_dw_wrdata_dbi_p1 => dfi_4_dw_wrdata_dbi_p1, + dfi_4_dw_wrdata_par_p1 => dfi_4_dw_wrdata_par_p1, + dfi_4_dw_wrdata_dq_en_p1 => dfi_4_dw_wrdata_dq_en_p1, + dfi_4_dw_wrdata_par_en_p1 => dfi_4_dw_wrdata_par_en_p1, + dfi_4_aw_ck_dis => dfi_4_aw_ck_dis, + dfi_4_lp_pwr_e_req => dfi_4_lp_pwr_e_req, + dfi_4_lp_sr_e_req => dfi_4_lp_sr_e_req, + dfi_4_lp_pwr_x_req => dfi_4_lp_pwr_x_req, + dfi_4_aw_tx_indx_ld => dfi_4_aw_tx_indx_ld, + dfi_4_dw_tx_indx_ld => dfi_4_dw_tx_indx_ld, + dfi_4_dw_rx_indx_ld => dfi_4_dw_rx_indx_ld, + dfi_4_ctrlupd_ack => dfi_4_ctrlupd_ack, + dfi_4_phyupd_req => dfi_4_phyupd_req, + dfi_4_dw_wrdata_dqs_p0 => dfi_4_dw_wrdata_dqs_p0, + dfi_4_dw_wrdata_dqs_p1 => dfi_4_dw_wrdata_dqs_p1, + dfi_5_clk => dfi_5_clk, + dfi_5_rst_n => dfi_5_rst_n, + dfi_5_init_start => dfi_5_init_start, + dfi_5_aw_ck_p0 => dfi_5_aw_ck_p0, + dfi_5_aw_cke_p0 => dfi_5_aw_cke_p0, + dfi_5_aw_row_p0 => dfi_5_aw_row_p0, + dfi_5_aw_col_p0 => dfi_5_aw_col_p0, + dfi_5_dw_wrdata_p0 => dfi_5_dw_wrdata_p0, + dfi_5_dw_wrdata_mask_p0 => dfi_5_dw_wrdata_mask_p0, + dfi_5_dw_wrdata_dbi_p0 => dfi_5_dw_wrdata_dbi_p0, + dfi_5_dw_wrdata_par_p0 => dfi_5_dw_wrdata_par_p0, + dfi_5_dw_wrdata_dq_en_p0 => dfi_5_dw_wrdata_dq_en_p0, + dfi_5_dw_wrdata_par_en_p0 => dfi_5_dw_wrdata_par_en_p0, + dfi_5_aw_ck_p1 => dfi_5_aw_ck_p1, + dfi_5_aw_cke_p1 => dfi_5_aw_cke_p1, + dfi_5_aw_row_p1 => dfi_5_aw_row_p1, + dfi_5_aw_col_p1 => dfi_5_aw_col_p1, + dfi_5_dw_wrdata_p1 => dfi_5_dw_wrdata_p1, + dfi_5_dw_wrdata_mask_p1 => dfi_5_dw_wrdata_mask_p1, + dfi_5_dw_wrdata_dbi_p1 => dfi_5_dw_wrdata_dbi_p1, + dfi_5_dw_wrdata_par_p1 => dfi_5_dw_wrdata_par_p1, + dfi_5_dw_wrdata_dq_en_p1 => dfi_5_dw_wrdata_dq_en_p1, + dfi_5_dw_wrdata_par_en_p1 => dfi_5_dw_wrdata_par_en_p1, + dfi_5_aw_ck_dis => dfi_5_aw_ck_dis, + dfi_5_lp_pwr_e_req => dfi_5_lp_pwr_e_req, + dfi_5_lp_sr_e_req => dfi_5_lp_sr_e_req, + dfi_5_lp_pwr_x_req => dfi_5_lp_pwr_x_req, + dfi_5_aw_tx_indx_ld => dfi_5_aw_tx_indx_ld, + dfi_5_dw_tx_indx_ld => dfi_5_dw_tx_indx_ld, + dfi_5_dw_rx_indx_ld => dfi_5_dw_rx_indx_ld, + dfi_5_ctrlupd_ack => dfi_5_ctrlupd_ack, + dfi_5_phyupd_req => dfi_5_phyupd_req, + dfi_5_dw_wrdata_dqs_p0 => dfi_5_dw_wrdata_dqs_p0, + dfi_5_dw_wrdata_dqs_p1 => dfi_5_dw_wrdata_dqs_p1, + dfi_6_clk => dfi_6_clk, + dfi_6_rst_n => dfi_6_rst_n, + dfi_6_init_start => dfi_6_init_start, + dfi_6_aw_ck_p0 => dfi_6_aw_ck_p0, + dfi_6_aw_cke_p0 => dfi_6_aw_cke_p0, + dfi_6_aw_row_p0 => dfi_6_aw_row_p0, + dfi_6_aw_col_p0 => dfi_6_aw_col_p0, + dfi_6_dw_wrdata_p0 => dfi_6_dw_wrdata_p0, + dfi_6_dw_wrdata_mask_p0 => dfi_6_dw_wrdata_mask_p0, + dfi_6_dw_wrdata_dbi_p0 => dfi_6_dw_wrdata_dbi_p0, + dfi_6_dw_wrdata_par_p0 => dfi_6_dw_wrdata_par_p0, + dfi_6_dw_wrdata_dq_en_p0 => dfi_6_dw_wrdata_dq_en_p0, + dfi_6_dw_wrdata_par_en_p0 => dfi_6_dw_wrdata_par_en_p0, + dfi_6_aw_ck_p1 => dfi_6_aw_ck_p1, + dfi_6_aw_cke_p1 => dfi_6_aw_cke_p1, + dfi_6_aw_row_p1 => dfi_6_aw_row_p1, + dfi_6_aw_col_p1 => dfi_6_aw_col_p1, + dfi_6_dw_wrdata_p1 => dfi_6_dw_wrdata_p1, + dfi_6_dw_wrdata_mask_p1 => dfi_6_dw_wrdata_mask_p1, + dfi_6_dw_wrdata_dbi_p1 => dfi_6_dw_wrdata_dbi_p1, + dfi_6_dw_wrdata_par_p1 => dfi_6_dw_wrdata_par_p1, + dfi_6_dw_wrdata_dq_en_p1 => dfi_6_dw_wrdata_dq_en_p1, + dfi_6_dw_wrdata_par_en_p1 => dfi_6_dw_wrdata_par_en_p1, + dfi_6_aw_ck_dis => dfi_6_aw_ck_dis, + dfi_6_lp_pwr_e_req => dfi_6_lp_pwr_e_req, + dfi_6_lp_sr_e_req => dfi_6_lp_sr_e_req, + dfi_6_lp_pwr_x_req => dfi_6_lp_pwr_x_req, + dfi_6_aw_tx_indx_ld => dfi_6_aw_tx_indx_ld, + dfi_6_dw_tx_indx_ld => dfi_6_dw_tx_indx_ld, + dfi_6_dw_rx_indx_ld => dfi_6_dw_rx_indx_ld, + dfi_6_ctrlupd_ack => dfi_6_ctrlupd_ack, + dfi_6_phyupd_req => dfi_6_phyupd_req, + dfi_6_dw_wrdata_dqs_p0 => dfi_6_dw_wrdata_dqs_p0, + dfi_6_dw_wrdata_dqs_p1 => dfi_6_dw_wrdata_dqs_p1, + dfi_7_clk => dfi_7_clk, + dfi_7_rst_n => dfi_7_rst_n, + dfi_7_init_start => dfi_7_init_start, + dfi_7_aw_ck_p0 => dfi_7_aw_ck_p0, + dfi_7_aw_cke_p0 => dfi_7_aw_cke_p0, + dfi_7_aw_row_p0 => dfi_7_aw_row_p0, + dfi_7_aw_col_p0 => dfi_7_aw_col_p0, + dfi_7_dw_wrdata_p0 => dfi_7_dw_wrdata_p0, + dfi_7_dw_wrdata_mask_p0 => dfi_7_dw_wrdata_mask_p0, + dfi_7_dw_wrdata_dbi_p0 => dfi_7_dw_wrdata_dbi_p0, + dfi_7_dw_wrdata_par_p0 => dfi_7_dw_wrdata_par_p0, + dfi_7_dw_wrdata_dq_en_p0 => dfi_7_dw_wrdata_dq_en_p0, + dfi_7_dw_wrdata_par_en_p0 => dfi_7_dw_wrdata_par_en_p0, + dfi_7_aw_ck_p1 => dfi_7_aw_ck_p1, + dfi_7_aw_cke_p1 => dfi_7_aw_cke_p1, + dfi_7_aw_row_p1 => dfi_7_aw_row_p1, + dfi_7_aw_col_p1 => dfi_7_aw_col_p1, + dfi_7_dw_wrdata_p1 => dfi_7_dw_wrdata_p1, + dfi_7_dw_wrdata_mask_p1 => dfi_7_dw_wrdata_mask_p1, + dfi_7_dw_wrdata_dbi_p1 => dfi_7_dw_wrdata_dbi_p1, + dfi_7_dw_wrdata_par_p1 => dfi_7_dw_wrdata_par_p1, + dfi_7_dw_wrdata_dq_en_p1 => dfi_7_dw_wrdata_dq_en_p1, + dfi_7_dw_wrdata_par_en_p1 => dfi_7_dw_wrdata_par_en_p1, + dfi_7_aw_ck_dis => dfi_7_aw_ck_dis, + dfi_7_lp_pwr_e_req => dfi_7_lp_pwr_e_req, + dfi_7_lp_sr_e_req => dfi_7_lp_sr_e_req, + dfi_7_lp_pwr_x_req => dfi_7_lp_pwr_x_req, + dfi_7_aw_tx_indx_ld => dfi_7_aw_tx_indx_ld, + dfi_7_dw_tx_indx_ld => dfi_7_dw_tx_indx_ld, + dfi_7_dw_rx_indx_ld => dfi_7_dw_rx_indx_ld, + dfi_7_ctrlupd_ack => dfi_7_ctrlupd_ack, + dfi_7_phyupd_req => dfi_7_phyupd_req, + dfi_7_dw_wrdata_dqs_p0 => dfi_7_dw_wrdata_dqs_p0, + dfi_7_dw_wrdata_dqs_p1 => dfi_7_dw_wrdata_dqs_p1, + dfi_8_clk => dfi_8_clk, + dfi_8_rst_n => dfi_8_rst_n, + dfi_8_init_start => dfi_8_init_start, + dfi_8_aw_ck_p0 => dfi_8_aw_ck_p0, + dfi_8_aw_cke_p0 => dfi_8_aw_cke_p0, + dfi_8_aw_row_p0 => dfi_8_aw_row_p0, + dfi_8_aw_col_p0 => dfi_8_aw_col_p0, + dfi_8_dw_wrdata_p0 => dfi_8_dw_wrdata_p0, + dfi_8_dw_wrdata_mask_p0 => dfi_8_dw_wrdata_mask_p0, + dfi_8_dw_wrdata_dbi_p0 => dfi_8_dw_wrdata_dbi_p0, + dfi_8_dw_wrdata_par_p0 => dfi_8_dw_wrdata_par_p0, + dfi_8_dw_wrdata_dq_en_p0 => dfi_8_dw_wrdata_dq_en_p0, + dfi_8_dw_wrdata_par_en_p0 => dfi_8_dw_wrdata_par_en_p0, + dfi_8_aw_ck_p1 => dfi_8_aw_ck_p1, + dfi_8_aw_cke_p1 => dfi_8_aw_cke_p1, + dfi_8_aw_row_p1 => dfi_8_aw_row_p1, + dfi_8_aw_col_p1 => dfi_8_aw_col_p1, + dfi_8_dw_wrdata_p1 => dfi_8_dw_wrdata_p1, + dfi_8_dw_wrdata_mask_p1 => dfi_8_dw_wrdata_mask_p1, + dfi_8_dw_wrdata_dbi_p1 => dfi_8_dw_wrdata_dbi_p1, + dfi_8_dw_wrdata_par_p1 => dfi_8_dw_wrdata_par_p1, + dfi_8_dw_wrdata_dq_en_p1 => dfi_8_dw_wrdata_dq_en_p1, + dfi_8_dw_wrdata_par_en_p1 => dfi_8_dw_wrdata_par_en_p1, + dfi_8_aw_ck_dis => dfi_8_aw_ck_dis, + dfi_8_lp_pwr_e_req => dfi_8_lp_pwr_e_req, + dfi_8_lp_sr_e_req => dfi_8_lp_sr_e_req, + dfi_8_lp_pwr_x_req => dfi_8_lp_pwr_x_req, + dfi_8_aw_tx_indx_ld => dfi_8_aw_tx_indx_ld, + dfi_8_dw_tx_indx_ld => dfi_8_dw_tx_indx_ld, + dfi_8_dw_rx_indx_ld => dfi_8_dw_rx_indx_ld, + dfi_8_ctrlupd_ack => dfi_8_ctrlupd_ack, + dfi_8_phyupd_req => dfi_8_phyupd_req, + dfi_8_dw_wrdata_dqs_p0 => dfi_8_dw_wrdata_dqs_p0, + dfi_8_dw_wrdata_dqs_p1 => dfi_8_dw_wrdata_dqs_p1, + dfi_9_clk => dfi_9_clk, + dfi_9_rst_n => dfi_9_rst_n, + dfi_9_init_start => dfi_9_init_start, + dfi_9_aw_ck_p0 => dfi_9_aw_ck_p0, + dfi_9_aw_cke_p0 => dfi_9_aw_cke_p0, + dfi_9_aw_row_p0 => dfi_9_aw_row_p0, + dfi_9_aw_col_p0 => dfi_9_aw_col_p0, + dfi_9_dw_wrdata_p0 => dfi_9_dw_wrdata_p0, + dfi_9_dw_wrdata_mask_p0 => dfi_9_dw_wrdata_mask_p0, + dfi_9_dw_wrdata_dbi_p0 => dfi_9_dw_wrdata_dbi_p0, + dfi_9_dw_wrdata_par_p0 => dfi_9_dw_wrdata_par_p0, + dfi_9_dw_wrdata_dq_en_p0 => dfi_9_dw_wrdata_dq_en_p0, + dfi_9_dw_wrdata_par_en_p0 => dfi_9_dw_wrdata_par_en_p0, + dfi_9_aw_ck_p1 => dfi_9_aw_ck_p1, + dfi_9_aw_cke_p1 => dfi_9_aw_cke_p1, + dfi_9_aw_row_p1 => dfi_9_aw_row_p1, + dfi_9_aw_col_p1 => dfi_9_aw_col_p1, + dfi_9_dw_wrdata_p1 => dfi_9_dw_wrdata_p1, + dfi_9_dw_wrdata_mask_p1 => dfi_9_dw_wrdata_mask_p1, + dfi_9_dw_wrdata_dbi_p1 => dfi_9_dw_wrdata_dbi_p1, + dfi_9_dw_wrdata_par_p1 => dfi_9_dw_wrdata_par_p1, + dfi_9_dw_wrdata_dq_en_p1 => dfi_9_dw_wrdata_dq_en_p1, + dfi_9_dw_wrdata_par_en_p1 => dfi_9_dw_wrdata_par_en_p1, + dfi_9_aw_ck_dis => dfi_9_aw_ck_dis, + dfi_9_lp_pwr_e_req => dfi_9_lp_pwr_e_req, + dfi_9_lp_sr_e_req => dfi_9_lp_sr_e_req, + dfi_9_lp_pwr_x_req => dfi_9_lp_pwr_x_req, + dfi_9_aw_tx_indx_ld => dfi_9_aw_tx_indx_ld, + dfi_9_dw_tx_indx_ld => dfi_9_dw_tx_indx_ld, + dfi_9_dw_rx_indx_ld => dfi_9_dw_rx_indx_ld, + dfi_9_ctrlupd_ack => dfi_9_ctrlupd_ack, + dfi_9_phyupd_req => dfi_9_phyupd_req, + dfi_9_dw_wrdata_dqs_p0 => dfi_9_dw_wrdata_dqs_p0, + dfi_9_dw_wrdata_dqs_p1 => dfi_9_dw_wrdata_dqs_p1, + dfi_10_clk => dfi_10_clk, + dfi_10_rst_n => dfi_10_rst_n, + dfi_10_init_start => dfi_10_init_start, + dfi_10_aw_ck_p0 => dfi_10_aw_ck_p0, + dfi_10_aw_cke_p0 => dfi_10_aw_cke_p0, + dfi_10_aw_row_p0 => dfi_10_aw_row_p0, + dfi_10_aw_col_p0 => dfi_10_aw_col_p0, + dfi_10_dw_wrdata_p0 => dfi_10_dw_wrdata_p0, + dfi_10_dw_wrdata_mask_p0 => dfi_10_dw_wrdata_mask_p0, + dfi_10_dw_wrdata_dbi_p0 => dfi_10_dw_wrdata_dbi_p0, + dfi_10_dw_wrdata_par_p0 => dfi_10_dw_wrdata_par_p0, + dfi_10_dw_wrdata_dq_en_p0 => dfi_10_dw_wrdata_dq_en_p0, + dfi_10_dw_wrdata_par_en_p0 => dfi_10_dw_wrdata_par_en_p0, + dfi_10_aw_ck_p1 => dfi_10_aw_ck_p1, + dfi_10_aw_cke_p1 => dfi_10_aw_cke_p1, + dfi_10_aw_row_p1 => dfi_10_aw_row_p1, + dfi_10_aw_col_p1 => dfi_10_aw_col_p1, + dfi_10_dw_wrdata_p1 => dfi_10_dw_wrdata_p1, + dfi_10_dw_wrdata_mask_p1 => dfi_10_dw_wrdata_mask_p1, + dfi_10_dw_wrdata_dbi_p1 => dfi_10_dw_wrdata_dbi_p1, + dfi_10_dw_wrdata_par_p1 => dfi_10_dw_wrdata_par_p1, + dfi_10_dw_wrdata_dq_en_p1 => dfi_10_dw_wrdata_dq_en_p1, + dfi_10_dw_wrdata_par_en_p1 => dfi_10_dw_wrdata_par_en_p1, + dfi_10_aw_ck_dis => dfi_10_aw_ck_dis, + dfi_10_lp_pwr_e_req => dfi_10_lp_pwr_e_req, + dfi_10_lp_sr_e_req => dfi_10_lp_sr_e_req, + dfi_10_lp_pwr_x_req => dfi_10_lp_pwr_x_req, + dfi_10_aw_tx_indx_ld => dfi_10_aw_tx_indx_ld, + dfi_10_dw_tx_indx_ld => dfi_10_dw_tx_indx_ld, + dfi_10_dw_rx_indx_ld => dfi_10_dw_rx_indx_ld, + dfi_10_ctrlupd_ack => dfi_10_ctrlupd_ack, + dfi_10_phyupd_req => dfi_10_phyupd_req, + dfi_10_dw_wrdata_dqs_p0 => dfi_10_dw_wrdata_dqs_p0, + dfi_10_dw_wrdata_dqs_p1 => dfi_10_dw_wrdata_dqs_p1, + dfi_11_clk => dfi_11_clk, + dfi_11_rst_n => dfi_11_rst_n, + dfi_11_init_start => dfi_11_init_start, + dfi_11_aw_ck_p0 => dfi_11_aw_ck_p0, + dfi_11_aw_cke_p0 => dfi_11_aw_cke_p0, + dfi_11_aw_row_p0 => dfi_11_aw_row_p0, + dfi_11_aw_col_p0 => dfi_11_aw_col_p0, + dfi_11_dw_wrdata_p0 => dfi_11_dw_wrdata_p0, + dfi_11_dw_wrdata_mask_p0 => dfi_11_dw_wrdata_mask_p0, + dfi_11_dw_wrdata_dbi_p0 => dfi_11_dw_wrdata_dbi_p0, + dfi_11_dw_wrdata_par_p0 => dfi_11_dw_wrdata_par_p0, + dfi_11_dw_wrdata_dq_en_p0 => dfi_11_dw_wrdata_dq_en_p0, + dfi_11_dw_wrdata_par_en_p0 => dfi_11_dw_wrdata_par_en_p0, + dfi_11_aw_ck_p1 => dfi_11_aw_ck_p1, + dfi_11_aw_cke_p1 => dfi_11_aw_cke_p1, + dfi_11_aw_row_p1 => dfi_11_aw_row_p1, + dfi_11_aw_col_p1 => dfi_11_aw_col_p1, + dfi_11_dw_wrdata_p1 => dfi_11_dw_wrdata_p1, + dfi_11_dw_wrdata_mask_p1 => dfi_11_dw_wrdata_mask_p1, + dfi_11_dw_wrdata_dbi_p1 => dfi_11_dw_wrdata_dbi_p1, + dfi_11_dw_wrdata_par_p1 => dfi_11_dw_wrdata_par_p1, + dfi_11_dw_wrdata_dq_en_p1 => dfi_11_dw_wrdata_dq_en_p1, + dfi_11_dw_wrdata_par_en_p1 => dfi_11_dw_wrdata_par_en_p1, + dfi_11_aw_ck_dis => dfi_11_aw_ck_dis, + dfi_11_lp_pwr_e_req => dfi_11_lp_pwr_e_req, + dfi_11_lp_sr_e_req => dfi_11_lp_sr_e_req, + dfi_11_lp_pwr_x_req => dfi_11_lp_pwr_x_req, + dfi_11_aw_tx_indx_ld => dfi_11_aw_tx_indx_ld, + dfi_11_dw_tx_indx_ld => dfi_11_dw_tx_indx_ld, + dfi_11_dw_rx_indx_ld => dfi_11_dw_rx_indx_ld, + dfi_11_ctrlupd_ack => dfi_11_ctrlupd_ack, + dfi_11_phyupd_req => dfi_11_phyupd_req, + dfi_11_dw_wrdata_dqs_p0 => dfi_11_dw_wrdata_dqs_p0, + dfi_11_dw_wrdata_dqs_p1 => dfi_11_dw_wrdata_dqs_p1, + dfi_12_clk => dfi_12_clk, + dfi_12_rst_n => dfi_12_rst_n, + dfi_12_init_start => dfi_12_init_start, + dfi_12_aw_ck_p0 => dfi_12_aw_ck_p0, + dfi_12_aw_cke_p0 => dfi_12_aw_cke_p0, + dfi_12_aw_row_p0 => dfi_12_aw_row_p0, + dfi_12_aw_col_p0 => dfi_12_aw_col_p0, + dfi_12_dw_wrdata_p0 => dfi_12_dw_wrdata_p0, + dfi_12_dw_wrdata_mask_p0 => dfi_12_dw_wrdata_mask_p0, + dfi_12_dw_wrdata_dbi_p0 => dfi_12_dw_wrdata_dbi_p0, + dfi_12_dw_wrdata_par_p0 => dfi_12_dw_wrdata_par_p0, + dfi_12_dw_wrdata_dq_en_p0 => dfi_12_dw_wrdata_dq_en_p0, + dfi_12_dw_wrdata_par_en_p0 => dfi_12_dw_wrdata_par_en_p0, + dfi_12_aw_ck_p1 => dfi_12_aw_ck_p1, + dfi_12_aw_cke_p1 => dfi_12_aw_cke_p1, + dfi_12_aw_row_p1 => dfi_12_aw_row_p1, + dfi_12_aw_col_p1 => dfi_12_aw_col_p1, + dfi_12_dw_wrdata_p1 => dfi_12_dw_wrdata_p1, + dfi_12_dw_wrdata_mask_p1 => dfi_12_dw_wrdata_mask_p1, + dfi_12_dw_wrdata_dbi_p1 => dfi_12_dw_wrdata_dbi_p1, + dfi_12_dw_wrdata_par_p1 => dfi_12_dw_wrdata_par_p1, + dfi_12_dw_wrdata_dq_en_p1 => dfi_12_dw_wrdata_dq_en_p1, + dfi_12_dw_wrdata_par_en_p1 => dfi_12_dw_wrdata_par_en_p1, + dfi_12_aw_ck_dis => dfi_12_aw_ck_dis, + dfi_12_lp_pwr_e_req => dfi_12_lp_pwr_e_req, + dfi_12_lp_sr_e_req => dfi_12_lp_sr_e_req, + dfi_12_lp_pwr_x_req => dfi_12_lp_pwr_x_req, + dfi_12_aw_tx_indx_ld => dfi_12_aw_tx_indx_ld, + dfi_12_dw_tx_indx_ld => dfi_12_dw_tx_indx_ld, + dfi_12_dw_rx_indx_ld => dfi_12_dw_rx_indx_ld, + dfi_12_ctrlupd_ack => dfi_12_ctrlupd_ack, + dfi_12_phyupd_req => dfi_12_phyupd_req, + dfi_12_dw_wrdata_dqs_p0 => dfi_12_dw_wrdata_dqs_p0, + dfi_12_dw_wrdata_dqs_p1 => dfi_12_dw_wrdata_dqs_p1, + dfi_13_clk => dfi_13_clk, + dfi_13_rst_n => dfi_13_rst_n, + dfi_13_init_start => dfi_13_init_start, + dfi_13_aw_ck_p0 => dfi_13_aw_ck_p0, + dfi_13_aw_cke_p0 => dfi_13_aw_cke_p0, + dfi_13_aw_row_p0 => dfi_13_aw_row_p0, + dfi_13_aw_col_p0 => dfi_13_aw_col_p0, + dfi_13_dw_wrdata_p0 => dfi_13_dw_wrdata_p0, + dfi_13_dw_wrdata_mask_p0 => dfi_13_dw_wrdata_mask_p0, + dfi_13_dw_wrdata_dbi_p0 => dfi_13_dw_wrdata_dbi_p0, + dfi_13_dw_wrdata_par_p0 => dfi_13_dw_wrdata_par_p0, + dfi_13_dw_wrdata_dq_en_p0 => dfi_13_dw_wrdata_dq_en_p0, + dfi_13_dw_wrdata_par_en_p0 => dfi_13_dw_wrdata_par_en_p0, + dfi_13_aw_ck_p1 => dfi_13_aw_ck_p1, + dfi_13_aw_cke_p1 => dfi_13_aw_cke_p1, + dfi_13_aw_row_p1 => dfi_13_aw_row_p1, + dfi_13_aw_col_p1 => dfi_13_aw_col_p1, + dfi_13_dw_wrdata_p1 => dfi_13_dw_wrdata_p1, + dfi_13_dw_wrdata_mask_p1 => dfi_13_dw_wrdata_mask_p1, + dfi_13_dw_wrdata_dbi_p1 => dfi_13_dw_wrdata_dbi_p1, + dfi_13_dw_wrdata_par_p1 => dfi_13_dw_wrdata_par_p1, + dfi_13_dw_wrdata_dq_en_p1 => dfi_13_dw_wrdata_dq_en_p1, + dfi_13_dw_wrdata_par_en_p1 => dfi_13_dw_wrdata_par_en_p1, + dfi_13_aw_ck_dis => dfi_13_aw_ck_dis, + dfi_13_lp_pwr_e_req => dfi_13_lp_pwr_e_req, + dfi_13_lp_sr_e_req => dfi_13_lp_sr_e_req, + dfi_13_lp_pwr_x_req => dfi_13_lp_pwr_x_req, + dfi_13_aw_tx_indx_ld => dfi_13_aw_tx_indx_ld, + dfi_13_dw_tx_indx_ld => dfi_13_dw_tx_indx_ld, + dfi_13_dw_rx_indx_ld => dfi_13_dw_rx_indx_ld, + dfi_13_ctrlupd_ack => dfi_13_ctrlupd_ack, + dfi_13_phyupd_req => dfi_13_phyupd_req, + dfi_13_dw_wrdata_dqs_p0 => dfi_13_dw_wrdata_dqs_p0, + dfi_13_dw_wrdata_dqs_p1 => dfi_13_dw_wrdata_dqs_p1, + dfi_14_clk => dfi_14_clk, + dfi_14_rst_n => dfi_14_rst_n, + dfi_14_init_start => dfi_14_init_start, + dfi_14_aw_ck_p0 => dfi_14_aw_ck_p0, + dfi_14_aw_cke_p0 => dfi_14_aw_cke_p0, + dfi_14_aw_row_p0 => dfi_14_aw_row_p0, + dfi_14_aw_col_p0 => dfi_14_aw_col_p0, + dfi_14_dw_wrdata_p0 => dfi_14_dw_wrdata_p0, + dfi_14_dw_wrdata_mask_p0 => dfi_14_dw_wrdata_mask_p0, + dfi_14_dw_wrdata_dbi_p0 => dfi_14_dw_wrdata_dbi_p0, + dfi_14_dw_wrdata_par_p0 => dfi_14_dw_wrdata_par_p0, + dfi_14_dw_wrdata_dq_en_p0 => dfi_14_dw_wrdata_dq_en_p0, + dfi_14_dw_wrdata_par_en_p0 => dfi_14_dw_wrdata_par_en_p0, + dfi_14_aw_ck_p1 => dfi_14_aw_ck_p1, + dfi_14_aw_cke_p1 => dfi_14_aw_cke_p1, + dfi_14_aw_row_p1 => dfi_14_aw_row_p1, + dfi_14_aw_col_p1 => dfi_14_aw_col_p1, + dfi_14_dw_wrdata_p1 => dfi_14_dw_wrdata_p1, + dfi_14_dw_wrdata_mask_p1 => dfi_14_dw_wrdata_mask_p1, + dfi_14_dw_wrdata_dbi_p1 => dfi_14_dw_wrdata_dbi_p1, + dfi_14_dw_wrdata_par_p1 => dfi_14_dw_wrdata_par_p1, + dfi_14_dw_wrdata_dq_en_p1 => dfi_14_dw_wrdata_dq_en_p1, + dfi_14_dw_wrdata_par_en_p1 => dfi_14_dw_wrdata_par_en_p1, + dfi_14_aw_ck_dis => dfi_14_aw_ck_dis, + dfi_14_lp_pwr_e_req => dfi_14_lp_pwr_e_req, + dfi_14_lp_sr_e_req => dfi_14_lp_sr_e_req, + dfi_14_lp_pwr_x_req => dfi_14_lp_pwr_x_req, + dfi_14_aw_tx_indx_ld => dfi_14_aw_tx_indx_ld, + dfi_14_dw_tx_indx_ld => dfi_14_dw_tx_indx_ld, + dfi_14_dw_rx_indx_ld => dfi_14_dw_rx_indx_ld, + dfi_14_ctrlupd_ack => dfi_14_ctrlupd_ack, + dfi_14_phyupd_req => dfi_14_phyupd_req, + dfi_14_dw_wrdata_dqs_p0 => dfi_14_dw_wrdata_dqs_p0, + dfi_14_dw_wrdata_dqs_p1 => dfi_14_dw_wrdata_dqs_p1, + dfi_15_clk => dfi_15_clk, + dfi_15_rst_n => dfi_15_rst_n, + dfi_15_init_start => dfi_15_init_start, + dfi_15_aw_ck_p0 => dfi_15_aw_ck_p0, + dfi_15_aw_cke_p0 => dfi_15_aw_cke_p0, + dfi_15_aw_row_p0 => dfi_15_aw_row_p0, + dfi_15_aw_col_p0 => dfi_15_aw_col_p0, + dfi_15_dw_wrdata_p0 => dfi_15_dw_wrdata_p0, + dfi_15_dw_wrdata_mask_p0 => dfi_15_dw_wrdata_mask_p0, + dfi_15_dw_wrdata_dbi_p0 => dfi_15_dw_wrdata_dbi_p0, + dfi_15_dw_wrdata_par_p0 => dfi_15_dw_wrdata_par_p0, + dfi_15_dw_wrdata_dq_en_p0 => dfi_15_dw_wrdata_dq_en_p0, + dfi_15_dw_wrdata_par_en_p0 => dfi_15_dw_wrdata_par_en_p0, + dfi_15_aw_ck_p1 => dfi_15_aw_ck_p1, + dfi_15_aw_cke_p1 => dfi_15_aw_cke_p1, + dfi_15_aw_row_p1 => dfi_15_aw_row_p1, + dfi_15_aw_col_p1 => dfi_15_aw_col_p1, + dfi_15_dw_wrdata_p1 => dfi_15_dw_wrdata_p1, + dfi_15_dw_wrdata_mask_p1 => dfi_15_dw_wrdata_mask_p1, + dfi_15_dw_wrdata_dbi_p1 => dfi_15_dw_wrdata_dbi_p1, + dfi_15_dw_wrdata_par_p1 => dfi_15_dw_wrdata_par_p1, + dfi_15_dw_wrdata_dq_en_p1 => dfi_15_dw_wrdata_dq_en_p1, + dfi_15_dw_wrdata_par_en_p1 => dfi_15_dw_wrdata_par_en_p1, + dfi_15_aw_ck_dis => dfi_15_aw_ck_dis, + dfi_15_lp_pwr_e_req => dfi_15_lp_pwr_e_req, + dfi_15_lp_sr_e_req => dfi_15_lp_sr_e_req, + dfi_15_lp_pwr_x_req => dfi_15_lp_pwr_x_req, + dfi_15_aw_tx_indx_ld => dfi_15_aw_tx_indx_ld, + dfi_15_dw_tx_indx_ld => dfi_15_dw_tx_indx_ld, + dfi_15_dw_rx_indx_ld => dfi_15_dw_rx_indx_ld, + dfi_15_ctrlupd_ack => dfi_15_ctrlupd_ack, + dfi_15_phyupd_req => dfi_15_phyupd_req, + dfi_15_dw_wrdata_dqs_p0 => dfi_15_dw_wrdata_dqs_p0, + dfi_15_dw_wrdata_dqs_p1 => dfi_15_dw_wrdata_dqs_p1, + APB_0_PCLK => APB_0_PCLK, + APB_0_PRESET_N => APB_0_PRESET_N, + APB_1_PCLK => APB_1_PCLK, + APB_1_PRESET_N => APB_1_PRESET_N, + dfi_0_dw_rddata_p0 => dfi_0_dw_rddata_p0, + dfi_0_dw_rddata_dm_p0 => dfi_0_dw_rddata_dm_p0, + dfi_0_dw_rddata_dbi_p0 => dfi_0_dw_rddata_dbi_p0, + dfi_0_dw_rddata_par_p0 => dfi_0_dw_rddata_par_p0, + dfi_0_dw_rddata_p1 => dfi_0_dw_rddata_p1, + dfi_0_dw_rddata_dm_p1 => dfi_0_dw_rddata_dm_p1, + dfi_0_dw_rddata_dbi_p1 => dfi_0_dw_rddata_dbi_p1, + dfi_0_dw_rddata_par_p1 => dfi_0_dw_rddata_par_p1, + dfi_0_dbi_byte_disable => dfi_0_dbi_byte_disable, + dfi_0_dw_rddata_valid => dfi_0_dw_rddata_valid, + dfi_0_dw_derr_n => dfi_0_dw_derr_n, + dfi_0_aw_aerr_n => dfi_0_aw_aerr_n, + dfi_0_ctrlupd_req => dfi_0_ctrlupd_req, + dfi_0_phyupd_ack => dfi_0_phyupd_ack, + dfi_0_clk_init => dfi_0_clk_init, + dfi_0_init_complete => dfi_0_init_complete, + dfi_0_out_rst_n => dfi_0_out_rst_n, + dfi_1_dw_rddata_p0 => dfi_1_dw_rddata_p0, + dfi_1_dw_rddata_dm_p0 => dfi_1_dw_rddata_dm_p0, + dfi_1_dw_rddata_dbi_p0 => dfi_1_dw_rddata_dbi_p0, + dfi_1_dw_rddata_par_p0 => dfi_1_dw_rddata_par_p0, + dfi_1_dw_rddata_p1 => dfi_1_dw_rddata_p1, + dfi_1_dw_rddata_dm_p1 => dfi_1_dw_rddata_dm_p1, + dfi_1_dw_rddata_dbi_p1 => dfi_1_dw_rddata_dbi_p1, + dfi_1_dw_rddata_par_p1 => dfi_1_dw_rddata_par_p1, + dfi_1_dbi_byte_disable => dfi_1_dbi_byte_disable, + dfi_1_dw_rddata_valid => dfi_1_dw_rddata_valid, + dfi_1_dw_derr_n => dfi_1_dw_derr_n, + dfi_1_aw_aerr_n => dfi_1_aw_aerr_n, + dfi_1_ctrlupd_req => dfi_1_ctrlupd_req, + dfi_1_phyupd_ack => dfi_1_phyupd_ack, + dfi_1_clk_init => dfi_1_clk_init, + dfi_1_init_complete => dfi_1_init_complete, + dfi_1_out_rst_n => dfi_1_out_rst_n, + dfi_2_dw_rddata_p0 => dfi_2_dw_rddata_p0, + dfi_2_dw_rddata_dm_p0 => dfi_2_dw_rddata_dm_p0, + dfi_2_dw_rddata_dbi_p0 => dfi_2_dw_rddata_dbi_p0, + dfi_2_dw_rddata_par_p0 => dfi_2_dw_rddata_par_p0, + dfi_2_dw_rddata_p1 => dfi_2_dw_rddata_p1, + dfi_2_dw_rddata_dm_p1 => dfi_2_dw_rddata_dm_p1, + dfi_2_dw_rddata_dbi_p1 => dfi_2_dw_rddata_dbi_p1, + dfi_2_dw_rddata_par_p1 => dfi_2_dw_rddata_par_p1, + dfi_2_dbi_byte_disable => dfi_2_dbi_byte_disable, + dfi_2_dw_rddata_valid => dfi_2_dw_rddata_valid, + dfi_2_dw_derr_n => dfi_2_dw_derr_n, + dfi_2_aw_aerr_n => dfi_2_aw_aerr_n, + dfi_2_ctrlupd_req => dfi_2_ctrlupd_req, + dfi_2_phyupd_ack => dfi_2_phyupd_ack, + dfi_2_clk_init => dfi_2_clk_init, + dfi_2_init_complete => dfi_2_init_complete, + dfi_2_out_rst_n => dfi_2_out_rst_n, + dfi_3_dw_rddata_p0 => dfi_3_dw_rddata_p0, + dfi_3_dw_rddata_dm_p0 => dfi_3_dw_rddata_dm_p0, + dfi_3_dw_rddata_dbi_p0 => dfi_3_dw_rddata_dbi_p0, + dfi_3_dw_rddata_par_p0 => dfi_3_dw_rddata_par_p0, + dfi_3_dw_rddata_p1 => dfi_3_dw_rddata_p1, + dfi_3_dw_rddata_dm_p1 => dfi_3_dw_rddata_dm_p1, + dfi_3_dw_rddata_dbi_p1 => dfi_3_dw_rddata_dbi_p1, + dfi_3_dw_rddata_par_p1 => dfi_3_dw_rddata_par_p1, + dfi_3_dbi_byte_disable => dfi_3_dbi_byte_disable, + dfi_3_dw_rddata_valid => dfi_3_dw_rddata_valid, + dfi_3_dw_derr_n => dfi_3_dw_derr_n, + dfi_3_aw_aerr_n => dfi_3_aw_aerr_n, + dfi_3_ctrlupd_req => dfi_3_ctrlupd_req, + dfi_3_phyupd_ack => dfi_3_phyupd_ack, + dfi_3_clk_init => dfi_3_clk_init, + dfi_3_init_complete => dfi_3_init_complete, + dfi_3_out_rst_n => dfi_3_out_rst_n, + dfi_4_dw_rddata_p0 => dfi_4_dw_rddata_p0, + dfi_4_dw_rddata_dm_p0 => dfi_4_dw_rddata_dm_p0, + dfi_4_dw_rddata_dbi_p0 => dfi_4_dw_rddata_dbi_p0, + dfi_4_dw_rddata_par_p0 => dfi_4_dw_rddata_par_p0, + dfi_4_dw_rddata_p1 => dfi_4_dw_rddata_p1, + dfi_4_dw_rddata_dm_p1 => dfi_4_dw_rddata_dm_p1, + dfi_4_dw_rddata_dbi_p1 => dfi_4_dw_rddata_dbi_p1, + dfi_4_dw_rddata_par_p1 => dfi_4_dw_rddata_par_p1, + dfi_4_dbi_byte_disable => dfi_4_dbi_byte_disable, + dfi_4_dw_rddata_valid => dfi_4_dw_rddata_valid, + dfi_4_dw_derr_n => dfi_4_dw_derr_n, + dfi_4_aw_aerr_n => dfi_4_aw_aerr_n, + dfi_4_ctrlupd_req => dfi_4_ctrlupd_req, + dfi_4_phyupd_ack => dfi_4_phyupd_ack, + dfi_4_clk_init => dfi_4_clk_init, + dfi_4_init_complete => dfi_4_init_complete, + dfi_4_out_rst_n => dfi_4_out_rst_n, + dfi_5_dw_rddata_p0 => dfi_5_dw_rddata_p0, + dfi_5_dw_rddata_dm_p0 => dfi_5_dw_rddata_dm_p0, + dfi_5_dw_rddata_dbi_p0 => dfi_5_dw_rddata_dbi_p0, + dfi_5_dw_rddata_par_p0 => dfi_5_dw_rddata_par_p0, + dfi_5_dw_rddata_p1 => dfi_5_dw_rddata_p1, + dfi_5_dw_rddata_dm_p1 => dfi_5_dw_rddata_dm_p1, + dfi_5_dw_rddata_dbi_p1 => dfi_5_dw_rddata_dbi_p1, + dfi_5_dw_rddata_par_p1 => dfi_5_dw_rddata_par_p1, + dfi_5_dbi_byte_disable => dfi_5_dbi_byte_disable, + dfi_5_dw_rddata_valid => dfi_5_dw_rddata_valid, + dfi_5_dw_derr_n => dfi_5_dw_derr_n, + dfi_5_aw_aerr_n => dfi_5_aw_aerr_n, + dfi_5_ctrlupd_req => dfi_5_ctrlupd_req, + dfi_5_phyupd_ack => dfi_5_phyupd_ack, + dfi_5_clk_init => dfi_5_clk_init, + dfi_5_init_complete => dfi_5_init_complete, + dfi_5_out_rst_n => dfi_5_out_rst_n, + dfi_6_dw_rddata_p0 => dfi_6_dw_rddata_p0, + dfi_6_dw_rddata_dm_p0 => dfi_6_dw_rddata_dm_p0, + dfi_6_dw_rddata_dbi_p0 => dfi_6_dw_rddata_dbi_p0, + dfi_6_dw_rddata_par_p0 => dfi_6_dw_rddata_par_p0, + dfi_6_dw_rddata_p1 => dfi_6_dw_rddata_p1, + dfi_6_dw_rddata_dm_p1 => dfi_6_dw_rddata_dm_p1, + dfi_6_dw_rddata_dbi_p1 => dfi_6_dw_rddata_dbi_p1, + dfi_6_dw_rddata_par_p1 => dfi_6_dw_rddata_par_p1, + dfi_6_dbi_byte_disable => dfi_6_dbi_byte_disable, + dfi_6_dw_rddata_valid => dfi_6_dw_rddata_valid, + dfi_6_dw_derr_n => dfi_6_dw_derr_n, + dfi_6_aw_aerr_n => dfi_6_aw_aerr_n, + dfi_6_ctrlupd_req => dfi_6_ctrlupd_req, + dfi_6_phyupd_ack => dfi_6_phyupd_ack, + dfi_6_clk_init => dfi_6_clk_init, + dfi_6_init_complete => dfi_6_init_complete, + dfi_6_out_rst_n => dfi_6_out_rst_n, + dfi_7_dw_rddata_p0 => dfi_7_dw_rddata_p0, + dfi_7_dw_rddata_dm_p0 => dfi_7_dw_rddata_dm_p0, + dfi_7_dw_rddata_dbi_p0 => dfi_7_dw_rddata_dbi_p0, + dfi_7_dw_rddata_par_p0 => dfi_7_dw_rddata_par_p0, + dfi_7_dw_rddata_p1 => dfi_7_dw_rddata_p1, + dfi_7_dw_rddata_dm_p1 => dfi_7_dw_rddata_dm_p1, + dfi_7_dw_rddata_dbi_p1 => dfi_7_dw_rddata_dbi_p1, + dfi_7_dw_rddata_par_p1 => dfi_7_dw_rddata_par_p1, + dfi_7_dbi_byte_disable => dfi_7_dbi_byte_disable, + dfi_7_dw_rddata_valid => dfi_7_dw_rddata_valid, + dfi_7_dw_derr_n => dfi_7_dw_derr_n, + dfi_7_aw_aerr_n => dfi_7_aw_aerr_n, + dfi_7_ctrlupd_req => dfi_7_ctrlupd_req, + dfi_7_phyupd_ack => dfi_7_phyupd_ack, + dfi_7_clk_init => dfi_7_clk_init, + dfi_7_init_complete => dfi_7_init_complete, + dfi_7_out_rst_n => dfi_7_out_rst_n, + dfi_8_dw_rddata_p0 => dfi_8_dw_rddata_p0, + dfi_8_dw_rddata_dm_p0 => dfi_8_dw_rddata_dm_p0, + dfi_8_dw_rddata_dbi_p0 => dfi_8_dw_rddata_dbi_p0, + dfi_8_dw_rddata_par_p0 => dfi_8_dw_rddata_par_p0, + dfi_8_dw_rddata_p1 => dfi_8_dw_rddata_p1, + dfi_8_dw_rddata_dm_p1 => dfi_8_dw_rddata_dm_p1, + dfi_8_dw_rddata_dbi_p1 => dfi_8_dw_rddata_dbi_p1, + dfi_8_dw_rddata_par_p1 => dfi_8_dw_rddata_par_p1, + dfi_8_dbi_byte_disable => dfi_8_dbi_byte_disable, + dfi_8_dw_rddata_valid => dfi_8_dw_rddata_valid, + dfi_8_dw_derr_n => dfi_8_dw_derr_n, + dfi_8_aw_aerr_n => dfi_8_aw_aerr_n, + dfi_8_ctrlupd_req => dfi_8_ctrlupd_req, + dfi_8_phyupd_ack => dfi_8_phyupd_ack, + dfi_8_clk_init => dfi_8_clk_init, + dfi_8_init_complete => dfi_8_init_complete, + dfi_8_out_rst_n => dfi_8_out_rst_n, + dfi_9_dw_rddata_p0 => dfi_9_dw_rddata_p0, + dfi_9_dw_rddata_dm_p0 => dfi_9_dw_rddata_dm_p0, + dfi_9_dw_rddata_dbi_p0 => dfi_9_dw_rddata_dbi_p0, + dfi_9_dw_rddata_par_p0 => dfi_9_dw_rddata_par_p0, + dfi_9_dw_rddata_p1 => dfi_9_dw_rddata_p1, + dfi_9_dw_rddata_dm_p1 => dfi_9_dw_rddata_dm_p1, + dfi_9_dw_rddata_dbi_p1 => dfi_9_dw_rddata_dbi_p1, + dfi_9_dw_rddata_par_p1 => dfi_9_dw_rddata_par_p1, + dfi_9_dbi_byte_disable => dfi_9_dbi_byte_disable, + dfi_9_dw_rddata_valid => dfi_9_dw_rddata_valid, + dfi_9_dw_derr_n => dfi_9_dw_derr_n, + dfi_9_aw_aerr_n => dfi_9_aw_aerr_n, + dfi_9_ctrlupd_req => dfi_9_ctrlupd_req, + dfi_9_phyupd_ack => dfi_9_phyupd_ack, + dfi_9_clk_init => dfi_9_clk_init, + dfi_9_init_complete => dfi_9_init_complete, + dfi_9_out_rst_n => dfi_9_out_rst_n, + dfi_10_dw_rddata_p0 => dfi_10_dw_rddata_p0, + dfi_10_dw_rddata_dm_p0 => dfi_10_dw_rddata_dm_p0, + dfi_10_dw_rddata_dbi_p0 => dfi_10_dw_rddata_dbi_p0, + dfi_10_dw_rddata_par_p0 => dfi_10_dw_rddata_par_p0, + dfi_10_dw_rddata_p1 => dfi_10_dw_rddata_p1, + dfi_10_dw_rddata_dm_p1 => dfi_10_dw_rddata_dm_p1, + dfi_10_dw_rddata_dbi_p1 => dfi_10_dw_rddata_dbi_p1, + dfi_10_dw_rddata_par_p1 => dfi_10_dw_rddata_par_p1, + dfi_10_dbi_byte_disable => dfi_10_dbi_byte_disable, + dfi_10_dw_rddata_valid => dfi_10_dw_rddata_valid, + dfi_10_dw_derr_n => dfi_10_dw_derr_n, + dfi_10_aw_aerr_n => dfi_10_aw_aerr_n, + dfi_10_ctrlupd_req => dfi_10_ctrlupd_req, + dfi_10_phyupd_ack => dfi_10_phyupd_ack, + dfi_10_clk_init => dfi_10_clk_init, + dfi_10_init_complete => dfi_10_init_complete, + dfi_10_out_rst_n => dfi_10_out_rst_n, + dfi_11_dw_rddata_p0 => dfi_11_dw_rddata_p0, + dfi_11_dw_rddata_dm_p0 => dfi_11_dw_rddata_dm_p0, + dfi_11_dw_rddata_dbi_p0 => dfi_11_dw_rddata_dbi_p0, + dfi_11_dw_rddata_par_p0 => dfi_11_dw_rddata_par_p0, + dfi_11_dw_rddata_p1 => dfi_11_dw_rddata_p1, + dfi_11_dw_rddata_dm_p1 => dfi_11_dw_rddata_dm_p1, + dfi_11_dw_rddata_dbi_p1 => dfi_11_dw_rddata_dbi_p1, + dfi_11_dw_rddata_par_p1 => dfi_11_dw_rddata_par_p1, + dfi_11_dbi_byte_disable => dfi_11_dbi_byte_disable, + dfi_11_dw_rddata_valid => dfi_11_dw_rddata_valid, + dfi_11_dw_derr_n => dfi_11_dw_derr_n, + dfi_11_aw_aerr_n => dfi_11_aw_aerr_n, + dfi_11_ctrlupd_req => dfi_11_ctrlupd_req, + dfi_11_phyupd_ack => dfi_11_phyupd_ack, + dfi_11_clk_init => dfi_11_clk_init, + dfi_11_init_complete => dfi_11_init_complete, + dfi_11_out_rst_n => dfi_11_out_rst_n, + dfi_12_dw_rddata_p0 => dfi_12_dw_rddata_p0, + dfi_12_dw_rddata_dm_p0 => dfi_12_dw_rddata_dm_p0, + dfi_12_dw_rddata_dbi_p0 => dfi_12_dw_rddata_dbi_p0, + dfi_12_dw_rddata_par_p0 => dfi_12_dw_rddata_par_p0, + dfi_12_dw_rddata_p1 => dfi_12_dw_rddata_p1, + dfi_12_dw_rddata_dm_p1 => dfi_12_dw_rddata_dm_p1, + dfi_12_dw_rddata_dbi_p1 => dfi_12_dw_rddata_dbi_p1, + dfi_12_dw_rddata_par_p1 => dfi_12_dw_rddata_par_p1, + dfi_12_dbi_byte_disable => dfi_12_dbi_byte_disable, + dfi_12_dw_rddata_valid => dfi_12_dw_rddata_valid, + dfi_12_dw_derr_n => dfi_12_dw_derr_n, + dfi_12_aw_aerr_n => dfi_12_aw_aerr_n, + dfi_12_ctrlupd_req => dfi_12_ctrlupd_req, + dfi_12_phyupd_ack => dfi_12_phyupd_ack, + dfi_12_clk_init => dfi_12_clk_init, + dfi_12_init_complete => dfi_12_init_complete, + dfi_12_out_rst_n => dfi_12_out_rst_n, + dfi_13_dw_rddata_p0 => dfi_13_dw_rddata_p0, + dfi_13_dw_rddata_dm_p0 => dfi_13_dw_rddata_dm_p0, + dfi_13_dw_rddata_dbi_p0 => dfi_13_dw_rddata_dbi_p0, + dfi_13_dw_rddata_par_p0 => dfi_13_dw_rddata_par_p0, + dfi_13_dw_rddata_p1 => dfi_13_dw_rddata_p1, + dfi_13_dw_rddata_dm_p1 => dfi_13_dw_rddata_dm_p1, + dfi_13_dw_rddata_dbi_p1 => dfi_13_dw_rddata_dbi_p1, + dfi_13_dw_rddata_par_p1 => dfi_13_dw_rddata_par_p1, + dfi_13_dbi_byte_disable => dfi_13_dbi_byte_disable, + dfi_13_dw_rddata_valid => dfi_13_dw_rddata_valid, + dfi_13_dw_derr_n => dfi_13_dw_derr_n, + dfi_13_aw_aerr_n => dfi_13_aw_aerr_n, + dfi_13_ctrlupd_req => dfi_13_ctrlupd_req, + dfi_13_phyupd_ack => dfi_13_phyupd_ack, + dfi_13_clk_init => dfi_13_clk_init, + dfi_13_init_complete => dfi_13_init_complete, + dfi_13_out_rst_n => dfi_13_out_rst_n, + dfi_14_dw_rddata_p0 => dfi_14_dw_rddata_p0, + dfi_14_dw_rddata_dm_p0 => dfi_14_dw_rddata_dm_p0, + dfi_14_dw_rddata_dbi_p0 => dfi_14_dw_rddata_dbi_p0, + dfi_14_dw_rddata_par_p0 => dfi_14_dw_rddata_par_p0, + dfi_14_dw_rddata_p1 => dfi_14_dw_rddata_p1, + dfi_14_dw_rddata_dm_p1 => dfi_14_dw_rddata_dm_p1, + dfi_14_dw_rddata_dbi_p1 => dfi_14_dw_rddata_dbi_p1, + dfi_14_dw_rddata_par_p1 => dfi_14_dw_rddata_par_p1, + dfi_14_dbi_byte_disable => dfi_14_dbi_byte_disable, + dfi_14_dw_rddata_valid => dfi_14_dw_rddata_valid, + dfi_14_dw_derr_n => dfi_14_dw_derr_n, + dfi_14_aw_aerr_n => dfi_14_aw_aerr_n, + dfi_14_ctrlupd_req => dfi_14_ctrlupd_req, + dfi_14_phyupd_ack => dfi_14_phyupd_ack, + dfi_14_clk_init => dfi_14_clk_init, + dfi_14_init_complete => dfi_14_init_complete, + dfi_14_out_rst_n => dfi_14_out_rst_n, + dfi_15_dw_rddata_p0 => dfi_15_dw_rddata_p0, + dfi_15_dw_rddata_dm_p0 => dfi_15_dw_rddata_dm_p0, + dfi_15_dw_rddata_dbi_p0 => dfi_15_dw_rddata_dbi_p0, + dfi_15_dw_rddata_par_p0 => dfi_15_dw_rddata_par_p0, + dfi_15_dw_rddata_p1 => dfi_15_dw_rddata_p1, + dfi_15_dw_rddata_dm_p1 => dfi_15_dw_rddata_dm_p1, + dfi_15_dw_rddata_dbi_p1 => dfi_15_dw_rddata_dbi_p1, + dfi_15_dw_rddata_par_p1 => dfi_15_dw_rddata_par_p1, + dfi_15_dbi_byte_disable => dfi_15_dbi_byte_disable, + dfi_15_dw_rddata_valid => dfi_15_dw_rddata_valid, + dfi_15_dw_derr_n => dfi_15_dw_derr_n, + dfi_15_aw_aerr_n => dfi_15_aw_aerr_n, + dfi_15_ctrlupd_req => dfi_15_ctrlupd_req, + dfi_15_phyupd_ack => dfi_15_phyupd_ack, + dfi_15_clk_init => dfi_15_clk_init, + dfi_15_init_complete => dfi_15_init_complete, + dfi_15_out_rst_n => dfi_15_out_rst_n, + apb_complete_0 => apb_complete_0, + apb_complete_1 => apb_complete_1, + DRAM_0_STAT_CATTRIP => DRAM_0_STAT_CATTRIP, + DRAM_0_STAT_TEMP => DRAM_0_STAT_TEMP, + DRAM_1_STAT_CATTRIP => DRAM_1_STAT_CATTRIP, + DRAM_1_STAT_TEMP => DRAM_1_STAT_TEMP + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file hbm_0.vhd when simulating +-- the core, hbm_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.v new file mode 100644 index 0000000..7463743 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.v @@ -0,0 +1,1070 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:36:26 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/hbm_0/hbm_0_stub.v +// Design : hbm_0 +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "hbm_v1_0_9,Vivado 2020.2" *) +module hbm_0(HBM_REF_CLK_0, HBM_REF_CLK_1, dfi_0_clk, + dfi_0_rst_n, dfi_0_init_start, dfi_0_aw_ck_p0, dfi_0_aw_cke_p0, dfi_0_aw_row_p0, + dfi_0_aw_col_p0, dfi_0_dw_wrdata_p0, dfi_0_dw_wrdata_mask_p0, dfi_0_dw_wrdata_dbi_p0, + dfi_0_dw_wrdata_par_p0, dfi_0_dw_wrdata_dq_en_p0, dfi_0_dw_wrdata_par_en_p0, + dfi_0_aw_ck_p1, dfi_0_aw_cke_p1, dfi_0_aw_row_p1, dfi_0_aw_col_p1, dfi_0_dw_wrdata_p1, + dfi_0_dw_wrdata_mask_p1, dfi_0_dw_wrdata_dbi_p1, dfi_0_dw_wrdata_par_p1, + dfi_0_dw_wrdata_dq_en_p1, dfi_0_dw_wrdata_par_en_p1, dfi_0_aw_ck_dis, + dfi_0_lp_pwr_e_req, dfi_0_lp_sr_e_req, dfi_0_lp_pwr_x_req, dfi_0_aw_tx_indx_ld, + dfi_0_dw_tx_indx_ld, dfi_0_dw_rx_indx_ld, dfi_0_ctrlupd_ack, dfi_0_phyupd_req, + dfi_0_dw_wrdata_dqs_p0, dfi_0_dw_wrdata_dqs_p1, dfi_1_clk, dfi_1_rst_n, dfi_1_init_start, + dfi_1_aw_ck_p0, dfi_1_aw_cke_p0, dfi_1_aw_row_p0, dfi_1_aw_col_p0, dfi_1_dw_wrdata_p0, + dfi_1_dw_wrdata_mask_p0, dfi_1_dw_wrdata_dbi_p0, dfi_1_dw_wrdata_par_p0, + dfi_1_dw_wrdata_dq_en_p0, dfi_1_dw_wrdata_par_en_p0, dfi_1_aw_ck_p1, dfi_1_aw_cke_p1, + dfi_1_aw_row_p1, dfi_1_aw_col_p1, dfi_1_dw_wrdata_p1, dfi_1_dw_wrdata_mask_p1, + dfi_1_dw_wrdata_dbi_p1, dfi_1_dw_wrdata_par_p1, dfi_1_dw_wrdata_dq_en_p1, + dfi_1_dw_wrdata_par_en_p1, dfi_1_aw_ck_dis, dfi_1_lp_pwr_e_req, dfi_1_lp_sr_e_req, + dfi_1_lp_pwr_x_req, dfi_1_aw_tx_indx_ld, dfi_1_dw_tx_indx_ld, dfi_1_dw_rx_indx_ld, + dfi_1_ctrlupd_ack, dfi_1_phyupd_req, dfi_1_dw_wrdata_dqs_p0, dfi_1_dw_wrdata_dqs_p1, + dfi_2_clk, dfi_2_rst_n, dfi_2_init_start, dfi_2_aw_ck_p0, dfi_2_aw_cke_p0, dfi_2_aw_row_p0, + dfi_2_aw_col_p0, dfi_2_dw_wrdata_p0, dfi_2_dw_wrdata_mask_p0, dfi_2_dw_wrdata_dbi_p0, + dfi_2_dw_wrdata_par_p0, dfi_2_dw_wrdata_dq_en_p0, dfi_2_dw_wrdata_par_en_p0, + dfi_2_aw_ck_p1, dfi_2_aw_cke_p1, dfi_2_aw_row_p1, dfi_2_aw_col_p1, dfi_2_dw_wrdata_p1, + dfi_2_dw_wrdata_mask_p1, dfi_2_dw_wrdata_dbi_p1, dfi_2_dw_wrdata_par_p1, + dfi_2_dw_wrdata_dq_en_p1, dfi_2_dw_wrdata_par_en_p1, dfi_2_aw_ck_dis, + dfi_2_lp_pwr_e_req, dfi_2_lp_sr_e_req, dfi_2_lp_pwr_x_req, dfi_2_aw_tx_indx_ld, + dfi_2_dw_tx_indx_ld, dfi_2_dw_rx_indx_ld, dfi_2_ctrlupd_ack, dfi_2_phyupd_req, + dfi_2_dw_wrdata_dqs_p0, dfi_2_dw_wrdata_dqs_p1, dfi_3_clk, dfi_3_rst_n, dfi_3_init_start, + dfi_3_aw_ck_p0, dfi_3_aw_cke_p0, dfi_3_aw_row_p0, dfi_3_aw_col_p0, dfi_3_dw_wrdata_p0, + dfi_3_dw_wrdata_mask_p0, dfi_3_dw_wrdata_dbi_p0, dfi_3_dw_wrdata_par_p0, + dfi_3_dw_wrdata_dq_en_p0, dfi_3_dw_wrdata_par_en_p0, dfi_3_aw_ck_p1, dfi_3_aw_cke_p1, + dfi_3_aw_row_p1, dfi_3_aw_col_p1, dfi_3_dw_wrdata_p1, dfi_3_dw_wrdata_mask_p1, + dfi_3_dw_wrdata_dbi_p1, dfi_3_dw_wrdata_par_p1, dfi_3_dw_wrdata_dq_en_p1, + dfi_3_dw_wrdata_par_en_p1, dfi_3_aw_ck_dis, dfi_3_lp_pwr_e_req, dfi_3_lp_sr_e_req, + dfi_3_lp_pwr_x_req, dfi_3_aw_tx_indx_ld, dfi_3_dw_tx_indx_ld, dfi_3_dw_rx_indx_ld, + dfi_3_ctrlupd_ack, dfi_3_phyupd_req, dfi_3_dw_wrdata_dqs_p0, dfi_3_dw_wrdata_dqs_p1, + dfi_4_clk, dfi_4_rst_n, dfi_4_init_start, dfi_4_aw_ck_p0, dfi_4_aw_cke_p0, dfi_4_aw_row_p0, + dfi_4_aw_col_p0, dfi_4_dw_wrdata_p0, dfi_4_dw_wrdata_mask_p0, dfi_4_dw_wrdata_dbi_p0, + dfi_4_dw_wrdata_par_p0, dfi_4_dw_wrdata_dq_en_p0, dfi_4_dw_wrdata_par_en_p0, + dfi_4_aw_ck_p1, dfi_4_aw_cke_p1, dfi_4_aw_row_p1, dfi_4_aw_col_p1, dfi_4_dw_wrdata_p1, + dfi_4_dw_wrdata_mask_p1, dfi_4_dw_wrdata_dbi_p1, dfi_4_dw_wrdata_par_p1, + dfi_4_dw_wrdata_dq_en_p1, dfi_4_dw_wrdata_par_en_p1, dfi_4_aw_ck_dis, + dfi_4_lp_pwr_e_req, dfi_4_lp_sr_e_req, dfi_4_lp_pwr_x_req, dfi_4_aw_tx_indx_ld, + dfi_4_dw_tx_indx_ld, dfi_4_dw_rx_indx_ld, dfi_4_ctrlupd_ack, dfi_4_phyupd_req, + dfi_4_dw_wrdata_dqs_p0, dfi_4_dw_wrdata_dqs_p1, dfi_5_clk, dfi_5_rst_n, dfi_5_init_start, + dfi_5_aw_ck_p0, dfi_5_aw_cke_p0, dfi_5_aw_row_p0, dfi_5_aw_col_p0, dfi_5_dw_wrdata_p0, + dfi_5_dw_wrdata_mask_p0, dfi_5_dw_wrdata_dbi_p0, dfi_5_dw_wrdata_par_p0, + dfi_5_dw_wrdata_dq_en_p0, dfi_5_dw_wrdata_par_en_p0, dfi_5_aw_ck_p1, dfi_5_aw_cke_p1, + dfi_5_aw_row_p1, dfi_5_aw_col_p1, dfi_5_dw_wrdata_p1, dfi_5_dw_wrdata_mask_p1, + dfi_5_dw_wrdata_dbi_p1, dfi_5_dw_wrdata_par_p1, dfi_5_dw_wrdata_dq_en_p1, + dfi_5_dw_wrdata_par_en_p1, dfi_5_aw_ck_dis, dfi_5_lp_pwr_e_req, dfi_5_lp_sr_e_req, + dfi_5_lp_pwr_x_req, dfi_5_aw_tx_indx_ld, dfi_5_dw_tx_indx_ld, dfi_5_dw_rx_indx_ld, + dfi_5_ctrlupd_ack, dfi_5_phyupd_req, dfi_5_dw_wrdata_dqs_p0, dfi_5_dw_wrdata_dqs_p1, + dfi_6_clk, dfi_6_rst_n, dfi_6_init_start, dfi_6_aw_ck_p0, dfi_6_aw_cke_p0, dfi_6_aw_row_p0, + dfi_6_aw_col_p0, dfi_6_dw_wrdata_p0, dfi_6_dw_wrdata_mask_p0, dfi_6_dw_wrdata_dbi_p0, + dfi_6_dw_wrdata_par_p0, dfi_6_dw_wrdata_dq_en_p0, dfi_6_dw_wrdata_par_en_p0, + dfi_6_aw_ck_p1, dfi_6_aw_cke_p1, dfi_6_aw_row_p1, dfi_6_aw_col_p1, dfi_6_dw_wrdata_p1, + dfi_6_dw_wrdata_mask_p1, dfi_6_dw_wrdata_dbi_p1, dfi_6_dw_wrdata_par_p1, + dfi_6_dw_wrdata_dq_en_p1, dfi_6_dw_wrdata_par_en_p1, dfi_6_aw_ck_dis, + dfi_6_lp_pwr_e_req, dfi_6_lp_sr_e_req, dfi_6_lp_pwr_x_req, dfi_6_aw_tx_indx_ld, + dfi_6_dw_tx_indx_ld, dfi_6_dw_rx_indx_ld, dfi_6_ctrlupd_ack, dfi_6_phyupd_req, + dfi_6_dw_wrdata_dqs_p0, dfi_6_dw_wrdata_dqs_p1, dfi_7_clk, dfi_7_rst_n, dfi_7_init_start, + dfi_7_aw_ck_p0, dfi_7_aw_cke_p0, dfi_7_aw_row_p0, dfi_7_aw_col_p0, dfi_7_dw_wrdata_p0, + dfi_7_dw_wrdata_mask_p0, dfi_7_dw_wrdata_dbi_p0, dfi_7_dw_wrdata_par_p0, + dfi_7_dw_wrdata_dq_en_p0, dfi_7_dw_wrdata_par_en_p0, dfi_7_aw_ck_p1, dfi_7_aw_cke_p1, + dfi_7_aw_row_p1, dfi_7_aw_col_p1, dfi_7_dw_wrdata_p1, dfi_7_dw_wrdata_mask_p1, + dfi_7_dw_wrdata_dbi_p1, dfi_7_dw_wrdata_par_p1, dfi_7_dw_wrdata_dq_en_p1, + dfi_7_dw_wrdata_par_en_p1, dfi_7_aw_ck_dis, dfi_7_lp_pwr_e_req, dfi_7_lp_sr_e_req, + dfi_7_lp_pwr_x_req, dfi_7_aw_tx_indx_ld, dfi_7_dw_tx_indx_ld, dfi_7_dw_rx_indx_ld, + dfi_7_ctrlupd_ack, dfi_7_phyupd_req, dfi_7_dw_wrdata_dqs_p0, dfi_7_dw_wrdata_dqs_p1, + dfi_8_clk, dfi_8_rst_n, dfi_8_init_start, dfi_8_aw_ck_p0, dfi_8_aw_cke_p0, dfi_8_aw_row_p0, + dfi_8_aw_col_p0, dfi_8_dw_wrdata_p0, dfi_8_dw_wrdata_mask_p0, dfi_8_dw_wrdata_dbi_p0, + dfi_8_dw_wrdata_par_p0, dfi_8_dw_wrdata_dq_en_p0, dfi_8_dw_wrdata_par_en_p0, + dfi_8_aw_ck_p1, dfi_8_aw_cke_p1, dfi_8_aw_row_p1, dfi_8_aw_col_p1, dfi_8_dw_wrdata_p1, + dfi_8_dw_wrdata_mask_p1, dfi_8_dw_wrdata_dbi_p1, dfi_8_dw_wrdata_par_p1, + dfi_8_dw_wrdata_dq_en_p1, dfi_8_dw_wrdata_par_en_p1, dfi_8_aw_ck_dis, + dfi_8_lp_pwr_e_req, dfi_8_lp_sr_e_req, dfi_8_lp_pwr_x_req, dfi_8_aw_tx_indx_ld, + dfi_8_dw_tx_indx_ld, dfi_8_dw_rx_indx_ld, dfi_8_ctrlupd_ack, dfi_8_phyupd_req, + dfi_8_dw_wrdata_dqs_p0, dfi_8_dw_wrdata_dqs_p1, dfi_9_clk, dfi_9_rst_n, dfi_9_init_start, + dfi_9_aw_ck_p0, dfi_9_aw_cke_p0, dfi_9_aw_row_p0, dfi_9_aw_col_p0, dfi_9_dw_wrdata_p0, + dfi_9_dw_wrdata_mask_p0, dfi_9_dw_wrdata_dbi_p0, dfi_9_dw_wrdata_par_p0, + dfi_9_dw_wrdata_dq_en_p0, dfi_9_dw_wrdata_par_en_p0, dfi_9_aw_ck_p1, dfi_9_aw_cke_p1, + dfi_9_aw_row_p1, dfi_9_aw_col_p1, dfi_9_dw_wrdata_p1, dfi_9_dw_wrdata_mask_p1, + dfi_9_dw_wrdata_dbi_p1, dfi_9_dw_wrdata_par_p1, dfi_9_dw_wrdata_dq_en_p1, + dfi_9_dw_wrdata_par_en_p1, dfi_9_aw_ck_dis, dfi_9_lp_pwr_e_req, dfi_9_lp_sr_e_req, + dfi_9_lp_pwr_x_req, dfi_9_aw_tx_indx_ld, dfi_9_dw_tx_indx_ld, dfi_9_dw_rx_indx_ld, + dfi_9_ctrlupd_ack, dfi_9_phyupd_req, dfi_9_dw_wrdata_dqs_p0, dfi_9_dw_wrdata_dqs_p1, + dfi_10_clk, dfi_10_rst_n, dfi_10_init_start, dfi_10_aw_ck_p0, dfi_10_aw_cke_p0, + dfi_10_aw_row_p0, dfi_10_aw_col_p0, dfi_10_dw_wrdata_p0, dfi_10_dw_wrdata_mask_p0, + dfi_10_dw_wrdata_dbi_p0, dfi_10_dw_wrdata_par_p0, dfi_10_dw_wrdata_dq_en_p0, + dfi_10_dw_wrdata_par_en_p0, dfi_10_aw_ck_p1, dfi_10_aw_cke_p1, dfi_10_aw_row_p1, + dfi_10_aw_col_p1, dfi_10_dw_wrdata_p1, dfi_10_dw_wrdata_mask_p1, + dfi_10_dw_wrdata_dbi_p1, dfi_10_dw_wrdata_par_p1, dfi_10_dw_wrdata_dq_en_p1, + dfi_10_dw_wrdata_par_en_p1, dfi_10_aw_ck_dis, dfi_10_lp_pwr_e_req, dfi_10_lp_sr_e_req, + dfi_10_lp_pwr_x_req, dfi_10_aw_tx_indx_ld, dfi_10_dw_tx_indx_ld, dfi_10_dw_rx_indx_ld, + dfi_10_ctrlupd_ack, dfi_10_phyupd_req, dfi_10_dw_wrdata_dqs_p0, + dfi_10_dw_wrdata_dqs_p1, dfi_11_clk, dfi_11_rst_n, dfi_11_init_start, dfi_11_aw_ck_p0, + dfi_11_aw_cke_p0, dfi_11_aw_row_p0, dfi_11_aw_col_p0, dfi_11_dw_wrdata_p0, + dfi_11_dw_wrdata_mask_p0, dfi_11_dw_wrdata_dbi_p0, dfi_11_dw_wrdata_par_p0, + dfi_11_dw_wrdata_dq_en_p0, dfi_11_dw_wrdata_par_en_p0, dfi_11_aw_ck_p1, + dfi_11_aw_cke_p1, dfi_11_aw_row_p1, dfi_11_aw_col_p1, dfi_11_dw_wrdata_p1, + dfi_11_dw_wrdata_mask_p1, dfi_11_dw_wrdata_dbi_p1, dfi_11_dw_wrdata_par_p1, + dfi_11_dw_wrdata_dq_en_p1, dfi_11_dw_wrdata_par_en_p1, dfi_11_aw_ck_dis, + dfi_11_lp_pwr_e_req, dfi_11_lp_sr_e_req, dfi_11_lp_pwr_x_req, dfi_11_aw_tx_indx_ld, + dfi_11_dw_tx_indx_ld, dfi_11_dw_rx_indx_ld, dfi_11_ctrlupd_ack, dfi_11_phyupd_req, + dfi_11_dw_wrdata_dqs_p0, dfi_11_dw_wrdata_dqs_p1, dfi_12_clk, dfi_12_rst_n, + dfi_12_init_start, dfi_12_aw_ck_p0, dfi_12_aw_cke_p0, dfi_12_aw_row_p0, dfi_12_aw_col_p0, + dfi_12_dw_wrdata_p0, dfi_12_dw_wrdata_mask_p0, dfi_12_dw_wrdata_dbi_p0, + dfi_12_dw_wrdata_par_p0, dfi_12_dw_wrdata_dq_en_p0, dfi_12_dw_wrdata_par_en_p0, + dfi_12_aw_ck_p1, dfi_12_aw_cke_p1, dfi_12_aw_row_p1, dfi_12_aw_col_p1, + dfi_12_dw_wrdata_p1, dfi_12_dw_wrdata_mask_p1, dfi_12_dw_wrdata_dbi_p1, + dfi_12_dw_wrdata_par_p1, dfi_12_dw_wrdata_dq_en_p1, dfi_12_dw_wrdata_par_en_p1, + dfi_12_aw_ck_dis, dfi_12_lp_pwr_e_req, dfi_12_lp_sr_e_req, dfi_12_lp_pwr_x_req, + dfi_12_aw_tx_indx_ld, dfi_12_dw_tx_indx_ld, dfi_12_dw_rx_indx_ld, dfi_12_ctrlupd_ack, + dfi_12_phyupd_req, dfi_12_dw_wrdata_dqs_p0, dfi_12_dw_wrdata_dqs_p1, dfi_13_clk, + dfi_13_rst_n, dfi_13_init_start, dfi_13_aw_ck_p0, dfi_13_aw_cke_p0, dfi_13_aw_row_p0, + dfi_13_aw_col_p0, dfi_13_dw_wrdata_p0, dfi_13_dw_wrdata_mask_p0, + dfi_13_dw_wrdata_dbi_p0, dfi_13_dw_wrdata_par_p0, dfi_13_dw_wrdata_dq_en_p0, + dfi_13_dw_wrdata_par_en_p0, dfi_13_aw_ck_p1, dfi_13_aw_cke_p1, dfi_13_aw_row_p1, + dfi_13_aw_col_p1, dfi_13_dw_wrdata_p1, dfi_13_dw_wrdata_mask_p1, + dfi_13_dw_wrdata_dbi_p1, dfi_13_dw_wrdata_par_p1, dfi_13_dw_wrdata_dq_en_p1, + dfi_13_dw_wrdata_par_en_p1, dfi_13_aw_ck_dis, dfi_13_lp_pwr_e_req, dfi_13_lp_sr_e_req, + dfi_13_lp_pwr_x_req, dfi_13_aw_tx_indx_ld, dfi_13_dw_tx_indx_ld, dfi_13_dw_rx_indx_ld, + dfi_13_ctrlupd_ack, dfi_13_phyupd_req, dfi_13_dw_wrdata_dqs_p0, + dfi_13_dw_wrdata_dqs_p1, dfi_14_clk, dfi_14_rst_n, dfi_14_init_start, dfi_14_aw_ck_p0, + dfi_14_aw_cke_p0, dfi_14_aw_row_p0, dfi_14_aw_col_p0, dfi_14_dw_wrdata_p0, + dfi_14_dw_wrdata_mask_p0, dfi_14_dw_wrdata_dbi_p0, dfi_14_dw_wrdata_par_p0, + dfi_14_dw_wrdata_dq_en_p0, dfi_14_dw_wrdata_par_en_p0, dfi_14_aw_ck_p1, + dfi_14_aw_cke_p1, dfi_14_aw_row_p1, dfi_14_aw_col_p1, dfi_14_dw_wrdata_p1, + dfi_14_dw_wrdata_mask_p1, dfi_14_dw_wrdata_dbi_p1, dfi_14_dw_wrdata_par_p1, + dfi_14_dw_wrdata_dq_en_p1, dfi_14_dw_wrdata_par_en_p1, dfi_14_aw_ck_dis, + dfi_14_lp_pwr_e_req, dfi_14_lp_sr_e_req, dfi_14_lp_pwr_x_req, dfi_14_aw_tx_indx_ld, + dfi_14_dw_tx_indx_ld, dfi_14_dw_rx_indx_ld, dfi_14_ctrlupd_ack, dfi_14_phyupd_req, + dfi_14_dw_wrdata_dqs_p0, dfi_14_dw_wrdata_dqs_p1, dfi_15_clk, dfi_15_rst_n, + dfi_15_init_start, dfi_15_aw_ck_p0, dfi_15_aw_cke_p0, dfi_15_aw_row_p0, dfi_15_aw_col_p0, + dfi_15_dw_wrdata_p0, dfi_15_dw_wrdata_mask_p0, dfi_15_dw_wrdata_dbi_p0, + dfi_15_dw_wrdata_par_p0, dfi_15_dw_wrdata_dq_en_p0, dfi_15_dw_wrdata_par_en_p0, + dfi_15_aw_ck_p1, dfi_15_aw_cke_p1, dfi_15_aw_row_p1, dfi_15_aw_col_p1, + dfi_15_dw_wrdata_p1, dfi_15_dw_wrdata_mask_p1, dfi_15_dw_wrdata_dbi_p1, + dfi_15_dw_wrdata_par_p1, dfi_15_dw_wrdata_dq_en_p1, dfi_15_dw_wrdata_par_en_p1, + dfi_15_aw_ck_dis, dfi_15_lp_pwr_e_req, dfi_15_lp_sr_e_req, dfi_15_lp_pwr_x_req, + dfi_15_aw_tx_indx_ld, dfi_15_dw_tx_indx_ld, dfi_15_dw_rx_indx_ld, dfi_15_ctrlupd_ack, + dfi_15_phyupd_req, dfi_15_dw_wrdata_dqs_p0, dfi_15_dw_wrdata_dqs_p1, APB_0_PCLK, + APB_0_PRESET_N, APB_1_PCLK, APB_1_PRESET_N, dfi_0_dw_rddata_p0, dfi_0_dw_rddata_dm_p0, + dfi_0_dw_rddata_dbi_p0, dfi_0_dw_rddata_par_p0, dfi_0_dw_rddata_p1, + dfi_0_dw_rddata_dm_p1, dfi_0_dw_rddata_dbi_p1, dfi_0_dw_rddata_par_p1, + dfi_0_dbi_byte_disable, dfi_0_dw_rddata_valid, dfi_0_dw_derr_n, dfi_0_aw_aerr_n, + dfi_0_ctrlupd_req, dfi_0_phyupd_ack, dfi_0_clk_init, dfi_0_init_complete, + dfi_0_out_rst_n, dfi_1_dw_rddata_p0, dfi_1_dw_rddata_dm_p0, dfi_1_dw_rddata_dbi_p0, + dfi_1_dw_rddata_par_p0, dfi_1_dw_rddata_p1, dfi_1_dw_rddata_dm_p1, + dfi_1_dw_rddata_dbi_p1, dfi_1_dw_rddata_par_p1, dfi_1_dbi_byte_disable, + dfi_1_dw_rddata_valid, dfi_1_dw_derr_n, dfi_1_aw_aerr_n, dfi_1_ctrlupd_req, + dfi_1_phyupd_ack, dfi_1_clk_init, dfi_1_init_complete, dfi_1_out_rst_n, + dfi_2_dw_rddata_p0, dfi_2_dw_rddata_dm_p0, dfi_2_dw_rddata_dbi_p0, + dfi_2_dw_rddata_par_p0, dfi_2_dw_rddata_p1, dfi_2_dw_rddata_dm_p1, + dfi_2_dw_rddata_dbi_p1, dfi_2_dw_rddata_par_p1, dfi_2_dbi_byte_disable, + dfi_2_dw_rddata_valid, dfi_2_dw_derr_n, dfi_2_aw_aerr_n, dfi_2_ctrlupd_req, + dfi_2_phyupd_ack, dfi_2_clk_init, dfi_2_init_complete, dfi_2_out_rst_n, + dfi_3_dw_rddata_p0, dfi_3_dw_rddata_dm_p0, dfi_3_dw_rddata_dbi_p0, + dfi_3_dw_rddata_par_p0, dfi_3_dw_rddata_p1, dfi_3_dw_rddata_dm_p1, + dfi_3_dw_rddata_dbi_p1, dfi_3_dw_rddata_par_p1, dfi_3_dbi_byte_disable, + dfi_3_dw_rddata_valid, dfi_3_dw_derr_n, dfi_3_aw_aerr_n, dfi_3_ctrlupd_req, + dfi_3_phyupd_ack, dfi_3_clk_init, dfi_3_init_complete, dfi_3_out_rst_n, + dfi_4_dw_rddata_p0, dfi_4_dw_rddata_dm_p0, dfi_4_dw_rddata_dbi_p0, + dfi_4_dw_rddata_par_p0, dfi_4_dw_rddata_p1, dfi_4_dw_rddata_dm_p1, + dfi_4_dw_rddata_dbi_p1, dfi_4_dw_rddata_par_p1, dfi_4_dbi_byte_disable, + dfi_4_dw_rddata_valid, dfi_4_dw_derr_n, dfi_4_aw_aerr_n, dfi_4_ctrlupd_req, + dfi_4_phyupd_ack, dfi_4_clk_init, dfi_4_init_complete, dfi_4_out_rst_n, + dfi_5_dw_rddata_p0, dfi_5_dw_rddata_dm_p0, dfi_5_dw_rddata_dbi_p0, + dfi_5_dw_rddata_par_p0, dfi_5_dw_rddata_p1, dfi_5_dw_rddata_dm_p1, + dfi_5_dw_rddata_dbi_p1, dfi_5_dw_rddata_par_p1, dfi_5_dbi_byte_disable, + dfi_5_dw_rddata_valid, dfi_5_dw_derr_n, dfi_5_aw_aerr_n, dfi_5_ctrlupd_req, + dfi_5_phyupd_ack, dfi_5_clk_init, dfi_5_init_complete, dfi_5_out_rst_n, + dfi_6_dw_rddata_p0, dfi_6_dw_rddata_dm_p0, dfi_6_dw_rddata_dbi_p0, + dfi_6_dw_rddata_par_p0, dfi_6_dw_rddata_p1, dfi_6_dw_rddata_dm_p1, + dfi_6_dw_rddata_dbi_p1, dfi_6_dw_rddata_par_p1, dfi_6_dbi_byte_disable, + dfi_6_dw_rddata_valid, dfi_6_dw_derr_n, dfi_6_aw_aerr_n, dfi_6_ctrlupd_req, + dfi_6_phyupd_ack, dfi_6_clk_init, dfi_6_init_complete, dfi_6_out_rst_n, + dfi_7_dw_rddata_p0, dfi_7_dw_rddata_dm_p0, dfi_7_dw_rddata_dbi_p0, + dfi_7_dw_rddata_par_p0, dfi_7_dw_rddata_p1, dfi_7_dw_rddata_dm_p1, + dfi_7_dw_rddata_dbi_p1, dfi_7_dw_rddata_par_p1, dfi_7_dbi_byte_disable, + dfi_7_dw_rddata_valid, dfi_7_dw_derr_n, dfi_7_aw_aerr_n, dfi_7_ctrlupd_req, + dfi_7_phyupd_ack, dfi_7_clk_init, dfi_7_init_complete, dfi_7_out_rst_n, + dfi_8_dw_rddata_p0, dfi_8_dw_rddata_dm_p0, dfi_8_dw_rddata_dbi_p0, + dfi_8_dw_rddata_par_p0, dfi_8_dw_rddata_p1, dfi_8_dw_rddata_dm_p1, + dfi_8_dw_rddata_dbi_p1, dfi_8_dw_rddata_par_p1, dfi_8_dbi_byte_disable, + dfi_8_dw_rddata_valid, dfi_8_dw_derr_n, dfi_8_aw_aerr_n, dfi_8_ctrlupd_req, + dfi_8_phyupd_ack, dfi_8_clk_init, dfi_8_init_complete, dfi_8_out_rst_n, + dfi_9_dw_rddata_p0, dfi_9_dw_rddata_dm_p0, dfi_9_dw_rddata_dbi_p0, + dfi_9_dw_rddata_par_p0, dfi_9_dw_rddata_p1, dfi_9_dw_rddata_dm_p1, + dfi_9_dw_rddata_dbi_p1, dfi_9_dw_rddata_par_p1, dfi_9_dbi_byte_disable, + dfi_9_dw_rddata_valid, dfi_9_dw_derr_n, dfi_9_aw_aerr_n, dfi_9_ctrlupd_req, + dfi_9_phyupd_ack, dfi_9_clk_init, dfi_9_init_complete, dfi_9_out_rst_n, + dfi_10_dw_rddata_p0, dfi_10_dw_rddata_dm_p0, dfi_10_dw_rddata_dbi_p0, + dfi_10_dw_rddata_par_p0, dfi_10_dw_rddata_p1, dfi_10_dw_rddata_dm_p1, + dfi_10_dw_rddata_dbi_p1, dfi_10_dw_rddata_par_p1, dfi_10_dbi_byte_disable, + dfi_10_dw_rddata_valid, dfi_10_dw_derr_n, dfi_10_aw_aerr_n, dfi_10_ctrlupd_req, + dfi_10_phyupd_ack, dfi_10_clk_init, dfi_10_init_complete, dfi_10_out_rst_n, + dfi_11_dw_rddata_p0, dfi_11_dw_rddata_dm_p0, dfi_11_dw_rddata_dbi_p0, + dfi_11_dw_rddata_par_p0, dfi_11_dw_rddata_p1, dfi_11_dw_rddata_dm_p1, + dfi_11_dw_rddata_dbi_p1, dfi_11_dw_rddata_par_p1, dfi_11_dbi_byte_disable, + dfi_11_dw_rddata_valid, dfi_11_dw_derr_n, dfi_11_aw_aerr_n, dfi_11_ctrlupd_req, + dfi_11_phyupd_ack, dfi_11_clk_init, dfi_11_init_complete, dfi_11_out_rst_n, + dfi_12_dw_rddata_p0, dfi_12_dw_rddata_dm_p0, dfi_12_dw_rddata_dbi_p0, + dfi_12_dw_rddata_par_p0, dfi_12_dw_rddata_p1, dfi_12_dw_rddata_dm_p1, + dfi_12_dw_rddata_dbi_p1, dfi_12_dw_rddata_par_p1, dfi_12_dbi_byte_disable, + dfi_12_dw_rddata_valid, dfi_12_dw_derr_n, dfi_12_aw_aerr_n, dfi_12_ctrlupd_req, + dfi_12_phyupd_ack, dfi_12_clk_init, dfi_12_init_complete, dfi_12_out_rst_n, + dfi_13_dw_rddata_p0, dfi_13_dw_rddata_dm_p0, dfi_13_dw_rddata_dbi_p0, + dfi_13_dw_rddata_par_p0, dfi_13_dw_rddata_p1, dfi_13_dw_rddata_dm_p1, + dfi_13_dw_rddata_dbi_p1, dfi_13_dw_rddata_par_p1, dfi_13_dbi_byte_disable, + dfi_13_dw_rddata_valid, dfi_13_dw_derr_n, dfi_13_aw_aerr_n, dfi_13_ctrlupd_req, + dfi_13_phyupd_ack, dfi_13_clk_init, dfi_13_init_complete, dfi_13_out_rst_n, + dfi_14_dw_rddata_p0, dfi_14_dw_rddata_dm_p0, dfi_14_dw_rddata_dbi_p0, + dfi_14_dw_rddata_par_p0, dfi_14_dw_rddata_p1, dfi_14_dw_rddata_dm_p1, + dfi_14_dw_rddata_dbi_p1, dfi_14_dw_rddata_par_p1, dfi_14_dbi_byte_disable, + dfi_14_dw_rddata_valid, dfi_14_dw_derr_n, dfi_14_aw_aerr_n, dfi_14_ctrlupd_req, + dfi_14_phyupd_ack, dfi_14_clk_init, dfi_14_init_complete, dfi_14_out_rst_n, + dfi_15_dw_rddata_p0, dfi_15_dw_rddata_dm_p0, dfi_15_dw_rddata_dbi_p0, + dfi_15_dw_rddata_par_p0, dfi_15_dw_rddata_p1, dfi_15_dw_rddata_dm_p1, + dfi_15_dw_rddata_dbi_p1, dfi_15_dw_rddata_par_p1, dfi_15_dbi_byte_disable, + dfi_15_dw_rddata_valid, dfi_15_dw_derr_n, dfi_15_aw_aerr_n, dfi_15_ctrlupd_req, + dfi_15_phyupd_ack, dfi_15_clk_init, dfi_15_init_complete, dfi_15_out_rst_n, + apb_complete_0, apb_complete_1, DRAM_0_STAT_CATTRIP, DRAM_0_STAT_TEMP, + DRAM_1_STAT_CATTRIP, DRAM_1_STAT_TEMP) +/* synthesis syn_black_box black_box_pad_pin="HBM_REF_CLK_0,HBM_REF_CLK_1,dfi_0_clk,dfi_0_rst_n,dfi_0_init_start,dfi_0_aw_ck_p0[1:0],dfi_0_aw_cke_p0[1:0],dfi_0_aw_row_p0[11:0],dfi_0_aw_col_p0[15:0],dfi_0_dw_wrdata_p0[255:0],dfi_0_dw_wrdata_mask_p0[31:0],dfi_0_dw_wrdata_dbi_p0[31:0],dfi_0_dw_wrdata_par_p0[7:0],dfi_0_dw_wrdata_dq_en_p0[7:0],dfi_0_dw_wrdata_par_en_p0[7:0],dfi_0_aw_ck_p1[1:0],dfi_0_aw_cke_p1[1:0],dfi_0_aw_row_p1[11:0],dfi_0_aw_col_p1[15:0],dfi_0_dw_wrdata_p1[255:0],dfi_0_dw_wrdata_mask_p1[31:0],dfi_0_dw_wrdata_dbi_p1[31:0],dfi_0_dw_wrdata_par_p1[7:0],dfi_0_dw_wrdata_dq_en_p1[7:0],dfi_0_dw_wrdata_par_en_p1[7:0],dfi_0_aw_ck_dis,dfi_0_lp_pwr_e_req,dfi_0_lp_sr_e_req,dfi_0_lp_pwr_x_req,dfi_0_aw_tx_indx_ld,dfi_0_dw_tx_indx_ld,dfi_0_dw_rx_indx_ld,dfi_0_ctrlupd_ack,dfi_0_phyupd_req,dfi_0_dw_wrdata_dqs_p0[7:0],dfi_0_dw_wrdata_dqs_p1[7:0],dfi_1_clk,dfi_1_rst_n,dfi_1_init_start,dfi_1_aw_ck_p0[1:0],dfi_1_aw_cke_p0[1:0],dfi_1_aw_row_p0[11:0],dfi_1_aw_col_p0[15:0],dfi_1_dw_wrdata_p0[255:0],dfi_1_dw_wrdata_mask_p0[31:0],dfi_1_dw_wrdata_dbi_p0[31:0],dfi_1_dw_wrdata_par_p0[7:0],dfi_1_dw_wrdata_dq_en_p0[7:0],dfi_1_dw_wrdata_par_en_p0[7:0],dfi_1_aw_ck_p1[1:0],dfi_1_aw_cke_p1[1:0],dfi_1_aw_row_p1[11:0],dfi_1_aw_col_p1[15:0],dfi_1_dw_wrdata_p1[255:0],dfi_1_dw_wrdata_mask_p1[31:0],dfi_1_dw_wrdata_dbi_p1[31:0],dfi_1_dw_wrdata_par_p1[7:0],dfi_1_dw_wrdata_dq_en_p1[7:0],dfi_1_dw_wrdata_par_en_p1[7:0],dfi_1_aw_ck_dis,dfi_1_lp_pwr_e_req,dfi_1_lp_sr_e_req,dfi_1_lp_pwr_x_req,dfi_1_aw_tx_indx_ld,dfi_1_dw_tx_indx_ld,dfi_1_dw_rx_indx_ld,dfi_1_ctrlupd_ack,dfi_1_phyupd_req,dfi_1_dw_wrdata_dqs_p0[7:0],dfi_1_dw_wrdata_dqs_p1[7:0],dfi_2_clk,dfi_2_rst_n,dfi_2_init_start,dfi_2_aw_ck_p0[1:0],dfi_2_aw_cke_p0[1:0],dfi_2_aw_row_p0[11:0],dfi_2_aw_col_p0[15:0],dfi_2_dw_wrdata_p0[255:0],dfi_2_dw_wrdata_mask_p0[31:0],dfi_2_dw_wrdata_dbi_p0[31:0],dfi_2_dw_wrdata_par_p0[7:0],dfi_2_dw_wrdata_dq_en_p0[7:0],dfi_2_dw_wrdata_par_en_p0[7:0],dfi_2_aw_ck_p1[1:0],dfi_2_aw_cke_p1[1:0],dfi_2_aw_row_p1[11:0],dfi_2_aw_col_p1[15:0],dfi_2_dw_wrdata_p1[255:0],dfi_2_dw_wrdata_mask_p1[31:0],dfi_2_dw_wrdata_dbi_p1[31:0],dfi_2_dw_wrdata_par_p1[7:0],dfi_2_dw_wrdata_dq_en_p1[7:0],dfi_2_dw_wrdata_par_en_p1[7:0],dfi_2_aw_ck_dis,dfi_2_lp_pwr_e_req,dfi_2_lp_sr_e_req,dfi_2_lp_pwr_x_req,dfi_2_aw_tx_indx_ld,dfi_2_dw_tx_indx_ld,dfi_2_dw_rx_indx_ld,dfi_2_ctrlupd_ack,dfi_2_phyupd_req,dfi_2_dw_wrdata_dqs_p0[7:0],dfi_2_dw_wrdata_dqs_p1[7:0],dfi_3_clk,dfi_3_rst_n,dfi_3_init_start,dfi_3_aw_ck_p0[1:0],dfi_3_aw_cke_p0[1:0],dfi_3_aw_row_p0[11:0],dfi_3_aw_col_p0[15:0],dfi_3_dw_wrdata_p0[255:0],dfi_3_dw_wrdata_mask_p0[31:0],dfi_3_dw_wrdata_dbi_p0[31:0],dfi_3_dw_wrdata_par_p0[7:0],dfi_3_dw_wrdata_dq_en_p0[7:0],dfi_3_dw_wrdata_par_en_p0[7:0],dfi_3_aw_ck_p1[1:0],dfi_3_aw_cke_p1[1:0],dfi_3_aw_row_p1[11:0],dfi_3_aw_col_p1[15:0],dfi_3_dw_wrdata_p1[255:0],dfi_3_dw_wrdata_mask_p1[31:0],dfi_3_dw_wrdata_dbi_p1[31:0],dfi_3_dw_wrdata_par_p1[7:0],dfi_3_dw_wrdata_dq_en_p1[7:0],dfi_3_dw_wrdata_par_en_p1[7:0],dfi_3_aw_ck_dis,dfi_3_lp_pwr_e_req,dfi_3_lp_sr_e_req,dfi_3_lp_pwr_x_req,dfi_3_aw_tx_indx_ld,dfi_3_dw_tx_indx_ld,dfi_3_dw_rx_indx_ld,dfi_3_ctrlupd_ack,dfi_3_phyupd_req,dfi_3_dw_wrdata_dqs_p0[7:0],dfi_3_dw_wrdata_dqs_p1[7:0],dfi_4_clk,dfi_4_rst_n,dfi_4_init_start,dfi_4_aw_ck_p0[1:0],dfi_4_aw_cke_p0[1:0],dfi_4_aw_row_p0[11:0],dfi_4_aw_col_p0[15:0],dfi_4_dw_wrdata_p0[255:0],dfi_4_dw_wrdata_mask_p0[31:0],dfi_4_dw_wrdata_dbi_p0[31:0],dfi_4_dw_wrdata_par_p0[7:0],dfi_4_dw_wrdata_dq_en_p0[7:0],dfi_4_dw_wrdata_par_en_p0[7:0],dfi_4_aw_ck_p1[1:0],dfi_4_aw_cke_p1[1:0],dfi_4_aw_row_p1[11:0],dfi_4_aw_col_p1[15:0],dfi_4_dw_wrdata_p1[255:0],dfi_4_dw_wrdata_mask_p1[31:0],dfi_4_dw_wrdata_dbi_p1[31:0],dfi_4_dw_wrdata_par_p1[7:0],dfi_4_dw_wrdata_dq_en_p1[7:0],dfi_4_dw_wrdata_par_en_p1[7:0],dfi_4_aw_ck_dis,dfi_4_lp_pwr_e_req,dfi_4_lp_sr_e_req,dfi_4_lp_pwr_x_req,dfi_4_aw_tx_indx_ld,dfi_4_dw_tx_indx_ld,dfi_4_dw_rx_indx_ld,dfi_4_ctrlupd_ack,dfi_4_phyupd_req,dfi_4_dw_wrdata_dqs_p0[7:0],dfi_4_dw_wrdata_dqs_p1[7:0],dfi_5_clk,dfi_5_rst_n,dfi_5_init_start,dfi_5_aw_ck_p0[1:0],dfi_5_aw_cke_p0[1:0],dfi_5_aw_row_p0[11:0],dfi_5_aw_col_p0[15:0],dfi_5_dw_wrdata_p0[255:0],dfi_5_dw_wrdata_mask_p0[31:0],dfi_5_dw_wrdata_dbi_p0[31:0],dfi_5_dw_wrdata_par_p0[7:0],dfi_5_dw_wrdata_dq_en_p0[7:0],dfi_5_dw_wrdata_par_en_p0[7:0],dfi_5_aw_ck_p1[1:0],dfi_5_aw_cke_p1[1:0],dfi_5_aw_row_p1[11:0],dfi_5_aw_col_p1[15:0],dfi_5_dw_wrdata_p1[255:0],dfi_5_dw_wrdata_mask_p1[31:0],dfi_5_dw_wrdata_dbi_p1[31:0],dfi_5_dw_wrdata_par_p1[7:0],dfi_5_dw_wrdata_dq_en_p1[7:0],dfi_5_dw_wrdata_par_en_p1[7:0],dfi_5_aw_ck_dis,dfi_5_lp_pwr_e_req,dfi_5_lp_sr_e_req,dfi_5_lp_pwr_x_req,dfi_5_aw_tx_indx_ld,dfi_5_dw_tx_indx_ld,dfi_5_dw_rx_indx_ld,dfi_5_ctrlupd_ack,dfi_5_phyupd_req,dfi_5_dw_wrdata_dqs_p0[7:0],dfi_5_dw_wrdata_dqs_p1[7:0],dfi_6_clk,dfi_6_rst_n,dfi_6_init_start,dfi_6_aw_ck_p0[1:0],dfi_6_aw_cke_p0[1:0],dfi_6_aw_row_p0[11:0],dfi_6_aw_col_p0[15:0],dfi_6_dw_wrdata_p0[255:0],dfi_6_dw_wrdata_mask_p0[31:0],dfi_6_dw_wrdata_dbi_p0[31:0],dfi_6_dw_wrdata_par_p0[7:0],dfi_6_dw_wrdata_dq_en_p0[7:0],dfi_6_dw_wrdata_par_en_p0[7:0],dfi_6_aw_ck_p1[1:0],dfi_6_aw_cke_p1[1:0],dfi_6_aw_row_p1[11:0],dfi_6_aw_col_p1[15:0],dfi_6_dw_wrdata_p1[255:0],dfi_6_dw_wrdata_mask_p1[31:0],dfi_6_dw_wrdata_dbi_p1[31:0],dfi_6_dw_wrdata_par_p1[7:0],dfi_6_dw_wrdata_dq_en_p1[7:0],dfi_6_dw_wrdata_par_en_p1[7:0],dfi_6_aw_ck_dis,dfi_6_lp_pwr_e_req,dfi_6_lp_sr_e_req,dfi_6_lp_pwr_x_req,dfi_6_aw_tx_indx_ld,dfi_6_dw_tx_indx_ld,dfi_6_dw_rx_indx_ld,dfi_6_ctrlupd_ack,dfi_6_phyupd_req,dfi_6_dw_wrdata_dqs_p0[7:0],dfi_6_dw_wrdata_dqs_p1[7:0],dfi_7_clk,dfi_7_rst_n,dfi_7_init_start,dfi_7_aw_ck_p0[1:0],dfi_7_aw_cke_p0[1:0],dfi_7_aw_row_p0[11:0],dfi_7_aw_col_p0[15:0],dfi_7_dw_wrdata_p0[255:0],dfi_7_dw_wrdata_mask_p0[31:0],dfi_7_dw_wrdata_dbi_p0[31:0],dfi_7_dw_wrdata_par_p0[7:0],dfi_7_dw_wrdata_dq_en_p0[7:0],dfi_7_dw_wrdata_par_en_p0[7:0],dfi_7_aw_ck_p1[1:0],dfi_7_aw_cke_p1[1:0],dfi_7_aw_row_p1[11:0],dfi_7_aw_col_p1[15:0],dfi_7_dw_wrdata_p1[255:0],dfi_7_dw_wrdata_mask_p1[31:0],dfi_7_dw_wrdata_dbi_p1[31:0],dfi_7_dw_wrdata_par_p1[7:0],dfi_7_dw_wrdata_dq_en_p1[7:0],dfi_7_dw_wrdata_par_en_p1[7:0],dfi_7_aw_ck_dis,dfi_7_lp_pwr_e_req,dfi_7_lp_sr_e_req,dfi_7_lp_pwr_x_req,dfi_7_aw_tx_indx_ld,dfi_7_dw_tx_indx_ld,dfi_7_dw_rx_indx_ld,dfi_7_ctrlupd_ack,dfi_7_phyupd_req,dfi_7_dw_wrdata_dqs_p0[7:0],dfi_7_dw_wrdata_dqs_p1[7:0],dfi_8_clk,dfi_8_rst_n,dfi_8_init_start,dfi_8_aw_ck_p0[1:0],dfi_8_aw_cke_p0[1:0],dfi_8_aw_row_p0[11:0],dfi_8_aw_col_p0[15:0],dfi_8_dw_wrdata_p0[255:0],dfi_8_dw_wrdata_mask_p0[31:0],dfi_8_dw_wrdata_dbi_p0[31:0],dfi_8_dw_wrdata_par_p0[7:0],dfi_8_dw_wrdata_dq_en_p0[7:0],dfi_8_dw_wrdata_par_en_p0[7:0],dfi_8_aw_ck_p1[1:0],dfi_8_aw_cke_p1[1:0],dfi_8_aw_row_p1[11:0],dfi_8_aw_col_p1[15:0],dfi_8_dw_wrdata_p1[255:0],dfi_8_dw_wrdata_mask_p1[31:0],dfi_8_dw_wrdata_dbi_p1[31:0],dfi_8_dw_wrdata_par_p1[7:0],dfi_8_dw_wrdata_dq_en_p1[7:0],dfi_8_dw_wrdata_par_en_p1[7:0],dfi_8_aw_ck_dis,dfi_8_lp_pwr_e_req,dfi_8_lp_sr_e_req,dfi_8_lp_pwr_x_req,dfi_8_aw_tx_indx_ld,dfi_8_dw_tx_indx_ld,dfi_8_dw_rx_indx_ld,dfi_8_ctrlupd_ack,dfi_8_phyupd_req,dfi_8_dw_wrdata_dqs_p0[7:0],dfi_8_dw_wrdata_dqs_p1[7:0],dfi_9_clk,dfi_9_rst_n,dfi_9_init_start,dfi_9_aw_ck_p0[1:0],dfi_9_aw_cke_p0[1:0],dfi_9_aw_row_p0[11:0],dfi_9_aw_col_p0[15:0],dfi_9_dw_wrdata_p0[255:0],dfi_9_dw_wrdata_mask_p0[31:0],dfi_9_dw_wrdata_dbi_p0[31:0],dfi_9_dw_wrdata_par_p0[7:0],dfi_9_dw_wrdata_dq_en_p0[7:0],dfi_9_dw_wrdata_par_en_p0[7:0],dfi_9_aw_ck_p1[1:0],dfi_9_aw_cke_p1[1:0],dfi_9_aw_row_p1[11:0],dfi_9_aw_col_p1[15:0],dfi_9_dw_wrdata_p1[255:0],dfi_9_dw_wrdata_mask_p1[31:0],dfi_9_dw_wrdata_dbi_p1[31:0],dfi_9_dw_wrdata_par_p1[7:0],dfi_9_dw_wrdata_dq_en_p1[7:0],dfi_9_dw_wrdata_par_en_p1[7:0],dfi_9_aw_ck_dis,dfi_9_lp_pwr_e_req,dfi_9_lp_sr_e_req,dfi_9_lp_pwr_x_req,dfi_9_aw_tx_indx_ld,dfi_9_dw_tx_indx_ld,dfi_9_dw_rx_indx_ld,dfi_9_ctrlupd_ack,dfi_9_phyupd_req,dfi_9_dw_wrdata_dqs_p0[7:0],dfi_9_dw_wrdata_dqs_p1[7:0],dfi_10_clk,dfi_10_rst_n,dfi_10_init_start,dfi_10_aw_ck_p0[1:0],dfi_10_aw_cke_p0[1:0],dfi_10_aw_row_p0[11:0],dfi_10_aw_col_p0[15:0],dfi_10_dw_wrdata_p0[255:0],dfi_10_dw_wrdata_mask_p0[31:0],dfi_10_dw_wrdata_dbi_p0[31:0],dfi_10_dw_wrdata_par_p0[7:0],dfi_10_dw_wrdata_dq_en_p0[7:0],dfi_10_dw_wrdata_par_en_p0[7:0],dfi_10_aw_ck_p1[1:0],dfi_10_aw_cke_p1[1:0],dfi_10_aw_row_p1[11:0],dfi_10_aw_col_p1[15:0],dfi_10_dw_wrdata_p1[255:0],dfi_10_dw_wrdata_mask_p1[31:0],dfi_10_dw_wrdata_dbi_p1[31:0],dfi_10_dw_wrdata_par_p1[7:0],dfi_10_dw_wrdata_dq_en_p1[7:0],dfi_10_dw_wrdata_par_en_p1[7:0],dfi_10_aw_ck_dis,dfi_10_lp_pwr_e_req,dfi_10_lp_sr_e_req,dfi_10_lp_pwr_x_req,dfi_10_aw_tx_indx_ld,dfi_10_dw_tx_indx_ld,dfi_10_dw_rx_indx_ld,dfi_10_ctrlupd_ack,dfi_10_phyupd_req,dfi_10_dw_wrdata_dqs_p0[7:0],dfi_10_dw_wrdata_dqs_p1[7:0],dfi_11_clk,dfi_11_rst_n,dfi_11_init_start,dfi_11_aw_ck_p0[1:0],dfi_11_aw_cke_p0[1:0],dfi_11_aw_row_p0[11:0],dfi_11_aw_col_p0[15:0],dfi_11_dw_wrdata_p0[255:0],dfi_11_dw_wrdata_mask_p0[31:0],dfi_11_dw_wrdata_dbi_p0[31:0],dfi_11_dw_wrdata_par_p0[7:0],dfi_11_dw_wrdata_dq_en_p0[7:0],dfi_11_dw_wrdata_par_en_p0[7:0],dfi_11_aw_ck_p1[1:0],dfi_11_aw_cke_p1[1:0],dfi_11_aw_row_p1[11:0],dfi_11_aw_col_p1[15:0],dfi_11_dw_wrdata_p1[255:0],dfi_11_dw_wrdata_mask_p1[31:0],dfi_11_dw_wrdata_dbi_p1[31:0],dfi_11_dw_wrdata_par_p1[7:0],dfi_11_dw_wrdata_dq_en_p1[7:0],dfi_11_dw_wrdata_par_en_p1[7:0],dfi_11_aw_ck_dis,dfi_11_lp_pwr_e_req,dfi_11_lp_sr_e_req,dfi_11_lp_pwr_x_req,dfi_11_aw_tx_indx_ld,dfi_11_dw_tx_indx_ld,dfi_11_dw_rx_indx_ld,dfi_11_ctrlupd_ack,dfi_11_phyupd_req,dfi_11_dw_wrdata_dqs_p0[7:0],dfi_11_dw_wrdata_dqs_p1[7:0],dfi_12_clk,dfi_12_rst_n,dfi_12_init_start,dfi_12_aw_ck_p0[1:0],dfi_12_aw_cke_p0[1:0],dfi_12_aw_row_p0[11:0],dfi_12_aw_col_p0[15:0],dfi_12_dw_wrdata_p0[255:0],dfi_12_dw_wrdata_mask_p0[31:0],dfi_12_dw_wrdata_dbi_p0[31:0],dfi_12_dw_wrdata_par_p0[7:0],dfi_12_dw_wrdata_dq_en_p0[7:0],dfi_12_dw_wrdata_par_en_p0[7:0],dfi_12_aw_ck_p1[1:0],dfi_12_aw_cke_p1[1:0],dfi_12_aw_row_p1[11:0],dfi_12_aw_col_p1[15:0],dfi_12_dw_wrdata_p1[255:0],dfi_12_dw_wrdata_mask_p1[31:0],dfi_12_dw_wrdata_dbi_p1[31:0],dfi_12_dw_wrdata_par_p1[7:0],dfi_12_dw_wrdata_dq_en_p1[7:0],dfi_12_dw_wrdata_par_en_p1[7:0],dfi_12_aw_ck_dis,dfi_12_lp_pwr_e_req,dfi_12_lp_sr_e_req,dfi_12_lp_pwr_x_req,dfi_12_aw_tx_indx_ld,dfi_12_dw_tx_indx_ld,dfi_12_dw_rx_indx_ld,dfi_12_ctrlupd_ack,dfi_12_phyupd_req,dfi_12_dw_wrdata_dqs_p0[7:0],dfi_12_dw_wrdata_dqs_p1[7:0],dfi_13_clk,dfi_13_rst_n,dfi_13_init_start,dfi_13_aw_ck_p0[1:0],dfi_13_aw_cke_p0[1:0],dfi_13_aw_row_p0[11:0],dfi_13_aw_col_p0[15:0],dfi_13_dw_wrdata_p0[255:0],dfi_13_dw_wrdata_mask_p0[31:0],dfi_13_dw_wrdata_dbi_p0[31:0],dfi_13_dw_wrdata_par_p0[7:0],dfi_13_dw_wrdata_dq_en_p0[7:0],dfi_13_dw_wrdata_par_en_p0[7:0],dfi_13_aw_ck_p1[1:0],dfi_13_aw_cke_p1[1:0],dfi_13_aw_row_p1[11:0],dfi_13_aw_col_p1[15:0],dfi_13_dw_wrdata_p1[255:0],dfi_13_dw_wrdata_mask_p1[31:0],dfi_13_dw_wrdata_dbi_p1[31:0],dfi_13_dw_wrdata_par_p1[7:0],dfi_13_dw_wrdata_dq_en_p1[7:0],dfi_13_dw_wrdata_par_en_p1[7:0],dfi_13_aw_ck_dis,dfi_13_lp_pwr_e_req,dfi_13_lp_sr_e_req,dfi_13_lp_pwr_x_req,dfi_13_aw_tx_indx_ld,dfi_13_dw_tx_indx_ld,dfi_13_dw_rx_indx_ld,dfi_13_ctrlupd_ack,dfi_13_phyupd_req,dfi_13_dw_wrdata_dqs_p0[7:0],dfi_13_dw_wrdata_dqs_p1[7:0],dfi_14_clk,dfi_14_rst_n,dfi_14_init_start,dfi_14_aw_ck_p0[1:0],dfi_14_aw_cke_p0[1:0],dfi_14_aw_row_p0[11:0],dfi_14_aw_col_p0[15:0],dfi_14_dw_wrdata_p0[255:0],dfi_14_dw_wrdata_mask_p0[31:0],dfi_14_dw_wrdata_dbi_p0[31:0],dfi_14_dw_wrdata_par_p0[7:0],dfi_14_dw_wrdata_dq_en_p0[7:0],dfi_14_dw_wrdata_par_en_p0[7:0],dfi_14_aw_ck_p1[1:0],dfi_14_aw_cke_p1[1:0],dfi_14_aw_row_p1[11:0],dfi_14_aw_col_p1[15:0],dfi_14_dw_wrdata_p1[255:0],dfi_14_dw_wrdata_mask_p1[31:0],dfi_14_dw_wrdata_dbi_p1[31:0],dfi_14_dw_wrdata_par_p1[7:0],dfi_14_dw_wrdata_dq_en_p1[7:0],dfi_14_dw_wrdata_par_en_p1[7:0],dfi_14_aw_ck_dis,dfi_14_lp_pwr_e_req,dfi_14_lp_sr_e_req,dfi_14_lp_pwr_x_req,dfi_14_aw_tx_indx_ld,dfi_14_dw_tx_indx_ld,dfi_14_dw_rx_indx_ld,dfi_14_ctrlupd_ack,dfi_14_phyupd_req,dfi_14_dw_wrdata_dqs_p0[7:0],dfi_14_dw_wrdata_dqs_p1[7:0],dfi_15_clk,dfi_15_rst_n,dfi_15_init_start,dfi_15_aw_ck_p0[1:0],dfi_15_aw_cke_p0[1:0],dfi_15_aw_row_p0[11:0],dfi_15_aw_col_p0[15:0],dfi_15_dw_wrdata_p0[255:0],dfi_15_dw_wrdata_mask_p0[31:0],dfi_15_dw_wrdata_dbi_p0[31:0],dfi_15_dw_wrdata_par_p0[7:0],dfi_15_dw_wrdata_dq_en_p0[7:0],dfi_15_dw_wrdata_par_en_p0[7:0],dfi_15_aw_ck_p1[1:0],dfi_15_aw_cke_p1[1:0],dfi_15_aw_row_p1[11:0],dfi_15_aw_col_p1[15:0],dfi_15_dw_wrdata_p1[255:0],dfi_15_dw_wrdata_mask_p1[31:0],dfi_15_dw_wrdata_dbi_p1[31:0],dfi_15_dw_wrdata_par_p1[7:0],dfi_15_dw_wrdata_dq_en_p1[7:0],dfi_15_dw_wrdata_par_en_p1[7:0],dfi_15_aw_ck_dis,dfi_15_lp_pwr_e_req,dfi_15_lp_sr_e_req,dfi_15_lp_pwr_x_req,dfi_15_aw_tx_indx_ld,dfi_15_dw_tx_indx_ld,dfi_15_dw_rx_indx_ld,dfi_15_ctrlupd_ack,dfi_15_phyupd_req,dfi_15_dw_wrdata_dqs_p0[7:0],dfi_15_dw_wrdata_dqs_p1[7:0],APB_0_PCLK,APB_0_PRESET_N,APB_1_PCLK,APB_1_PRESET_N,dfi_0_dw_rddata_p0[255:0],dfi_0_dw_rddata_dm_p0[31:0],dfi_0_dw_rddata_dbi_p0[31:0],dfi_0_dw_rddata_par_p0[7:0],dfi_0_dw_rddata_p1[255:0],dfi_0_dw_rddata_dm_p1[31:0],dfi_0_dw_rddata_dbi_p1[31:0],dfi_0_dw_rddata_par_p1[7:0],dfi_0_dbi_byte_disable[15:0],dfi_0_dw_rddata_valid[3:0],dfi_0_dw_derr_n[7:0],dfi_0_aw_aerr_n[1:0],dfi_0_ctrlupd_req,dfi_0_phyupd_ack,dfi_0_clk_init,dfi_0_init_complete,dfi_0_out_rst_n,dfi_1_dw_rddata_p0[255:0],dfi_1_dw_rddata_dm_p0[31:0],dfi_1_dw_rddata_dbi_p0[31:0],dfi_1_dw_rddata_par_p0[7:0],dfi_1_dw_rddata_p1[255:0],dfi_1_dw_rddata_dm_p1[31:0],dfi_1_dw_rddata_dbi_p1[31:0],dfi_1_dw_rddata_par_p1[7:0],dfi_1_dbi_byte_disable[15:0],dfi_1_dw_rddata_valid[3:0],dfi_1_dw_derr_n[7:0],dfi_1_aw_aerr_n[1:0],dfi_1_ctrlupd_req,dfi_1_phyupd_ack,dfi_1_clk_init,dfi_1_init_complete,dfi_1_out_rst_n,dfi_2_dw_rddata_p0[255:0],dfi_2_dw_rddata_dm_p0[31:0],dfi_2_dw_rddata_dbi_p0[31:0],dfi_2_dw_rddata_par_p0[7:0],dfi_2_dw_rddata_p1[255:0],dfi_2_dw_rddata_dm_p1[31:0],dfi_2_dw_rddata_dbi_p1[31:0],dfi_2_dw_rddata_par_p1[7:0],dfi_2_dbi_byte_disable[15:0],dfi_2_dw_rddata_valid[3:0],dfi_2_dw_derr_n[7:0],dfi_2_aw_aerr_n[1:0],dfi_2_ctrlupd_req,dfi_2_phyupd_ack,dfi_2_clk_init,dfi_2_init_complete,dfi_2_out_rst_n,dfi_3_dw_rddata_p0[255:0],dfi_3_dw_rddata_dm_p0[31:0],dfi_3_dw_rddata_dbi_p0[31:0],dfi_3_dw_rddata_par_p0[7:0],dfi_3_dw_rddata_p1[255:0],dfi_3_dw_rddata_dm_p1[31:0],dfi_3_dw_rddata_dbi_p1[31:0],dfi_3_dw_rddata_par_p1[7:0],dfi_3_dbi_byte_disable[15:0],dfi_3_dw_rddata_valid[3:0],dfi_3_dw_derr_n[7:0],dfi_3_aw_aerr_n[1:0],dfi_3_ctrlupd_req,dfi_3_phyupd_ack,dfi_3_clk_init,dfi_3_init_complete,dfi_3_out_rst_n,dfi_4_dw_rddata_p0[255:0],dfi_4_dw_rddata_dm_p0[31:0],dfi_4_dw_rddata_dbi_p0[31:0],dfi_4_dw_rddata_par_p0[7:0],dfi_4_dw_rddata_p1[255:0],dfi_4_dw_rddata_dm_p1[31:0],dfi_4_dw_rddata_dbi_p1[31:0],dfi_4_dw_rddata_par_p1[7:0],dfi_4_dbi_byte_disable[15:0],dfi_4_dw_rddata_valid[3:0],dfi_4_dw_derr_n[7:0],dfi_4_aw_aerr_n[1:0],dfi_4_ctrlupd_req,dfi_4_phyupd_ack,dfi_4_clk_init,dfi_4_init_complete,dfi_4_out_rst_n,dfi_5_dw_rddata_p0[255:0],dfi_5_dw_rddata_dm_p0[31:0],dfi_5_dw_rddata_dbi_p0[31:0],dfi_5_dw_rddata_par_p0[7:0],dfi_5_dw_rddata_p1[255:0],dfi_5_dw_rddata_dm_p1[31:0],dfi_5_dw_rddata_dbi_p1[31:0],dfi_5_dw_rddata_par_p1[7:0],dfi_5_dbi_byte_disable[15:0],dfi_5_dw_rddata_valid[3:0],dfi_5_dw_derr_n[7:0],dfi_5_aw_aerr_n[1:0],dfi_5_ctrlupd_req,dfi_5_phyupd_ack,dfi_5_clk_init,dfi_5_init_complete,dfi_5_out_rst_n,dfi_6_dw_rddata_p0[255:0],dfi_6_dw_rddata_dm_p0[31:0],dfi_6_dw_rddata_dbi_p0[31:0],dfi_6_dw_rddata_par_p0[7:0],dfi_6_dw_rddata_p1[255:0],dfi_6_dw_rddata_dm_p1[31:0],dfi_6_dw_rddata_dbi_p1[31:0],dfi_6_dw_rddata_par_p1[7:0],dfi_6_dbi_byte_disable[15:0],dfi_6_dw_rddata_valid[3:0],dfi_6_dw_derr_n[7:0],dfi_6_aw_aerr_n[1:0],dfi_6_ctrlupd_req,dfi_6_phyupd_ack,dfi_6_clk_init,dfi_6_init_complete,dfi_6_out_rst_n,dfi_7_dw_rddata_p0[255:0],dfi_7_dw_rddata_dm_p0[31:0],dfi_7_dw_rddata_dbi_p0[31:0],dfi_7_dw_rddata_par_p0[7:0],dfi_7_dw_rddata_p1[255:0],dfi_7_dw_rddata_dm_p1[31:0],dfi_7_dw_rddata_dbi_p1[31:0],dfi_7_dw_rddata_par_p1[7:0],dfi_7_dbi_byte_disable[15:0],dfi_7_dw_rddata_valid[3:0],dfi_7_dw_derr_n[7:0],dfi_7_aw_aerr_n[1:0],dfi_7_ctrlupd_req,dfi_7_phyupd_ack,dfi_7_clk_init,dfi_7_init_complete,dfi_7_out_rst_n,dfi_8_dw_rddata_p0[255:0],dfi_8_dw_rddata_dm_p0[31:0],dfi_8_dw_rddata_dbi_p0[31:0],dfi_8_dw_rddata_par_p0[7:0],dfi_8_dw_rddata_p1[255:0],dfi_8_dw_rddata_dm_p1[31:0],dfi_8_dw_rddata_dbi_p1[31:0],dfi_8_dw_rddata_par_p1[7:0],dfi_8_dbi_byte_disable[15:0],dfi_8_dw_rddata_valid[3:0],dfi_8_dw_derr_n[7:0],dfi_8_aw_aerr_n[1:0],dfi_8_ctrlupd_req,dfi_8_phyupd_ack,dfi_8_clk_init,dfi_8_init_complete,dfi_8_out_rst_n,dfi_9_dw_rddata_p0[255:0],dfi_9_dw_rddata_dm_p0[31:0],dfi_9_dw_rddata_dbi_p0[31:0],dfi_9_dw_rddata_par_p0[7:0],dfi_9_dw_rddata_p1[255:0],dfi_9_dw_rddata_dm_p1[31:0],dfi_9_dw_rddata_dbi_p1[31:0],dfi_9_dw_rddata_par_p1[7:0],dfi_9_dbi_byte_disable[15:0],dfi_9_dw_rddata_valid[3:0],dfi_9_dw_derr_n[7:0],dfi_9_aw_aerr_n[1:0],dfi_9_ctrlupd_req,dfi_9_phyupd_ack,dfi_9_clk_init,dfi_9_init_complete,dfi_9_out_rst_n,dfi_10_dw_rddata_p0[255:0],dfi_10_dw_rddata_dm_p0[31:0],dfi_10_dw_rddata_dbi_p0[31:0],dfi_10_dw_rddata_par_p0[7:0],dfi_10_dw_rddata_p1[255:0],dfi_10_dw_rddata_dm_p1[31:0],dfi_10_dw_rddata_dbi_p1[31:0],dfi_10_dw_rddata_par_p1[7:0],dfi_10_dbi_byte_disable[15:0],dfi_10_dw_rddata_valid[3:0],dfi_10_dw_derr_n[7:0],dfi_10_aw_aerr_n[1:0],dfi_10_ctrlupd_req,dfi_10_phyupd_ack,dfi_10_clk_init,dfi_10_init_complete,dfi_10_out_rst_n,dfi_11_dw_rddata_p0[255:0],dfi_11_dw_rddata_dm_p0[31:0],dfi_11_dw_rddata_dbi_p0[31:0],dfi_11_dw_rddata_par_p0[7:0],dfi_11_dw_rddata_p1[255:0],dfi_11_dw_rddata_dm_p1[31:0],dfi_11_dw_rddata_dbi_p1[31:0],dfi_11_dw_rddata_par_p1[7:0],dfi_11_dbi_byte_disable[15:0],dfi_11_dw_rddata_valid[3:0],dfi_11_dw_derr_n[7:0],dfi_11_aw_aerr_n[1:0],dfi_11_ctrlupd_req,dfi_11_phyupd_ack,dfi_11_clk_init,dfi_11_init_complete,dfi_11_out_rst_n,dfi_12_dw_rddata_p0[255:0],dfi_12_dw_rddata_dm_p0[31:0],dfi_12_dw_rddata_dbi_p0[31:0],dfi_12_dw_rddata_par_p0[7:0],dfi_12_dw_rddata_p1[255:0],dfi_12_dw_rddata_dm_p1[31:0],dfi_12_dw_rddata_dbi_p1[31:0],dfi_12_dw_rddata_par_p1[7:0],dfi_12_dbi_byte_disable[15:0],dfi_12_dw_rddata_valid[3:0],dfi_12_dw_derr_n[7:0],dfi_12_aw_aerr_n[1:0],dfi_12_ctrlupd_req,dfi_12_phyupd_ack,dfi_12_clk_init,dfi_12_init_complete,dfi_12_out_rst_n,dfi_13_dw_rddata_p0[255:0],dfi_13_dw_rddata_dm_p0[31:0],dfi_13_dw_rddata_dbi_p0[31:0],dfi_13_dw_rddata_par_p0[7:0],dfi_13_dw_rddata_p1[255:0],dfi_13_dw_rddata_dm_p1[31:0],dfi_13_dw_rddata_dbi_p1[31:0],dfi_13_dw_rddata_par_p1[7:0],dfi_13_dbi_byte_disable[15:0],dfi_13_dw_rddata_valid[3:0],dfi_13_dw_derr_n[7:0],dfi_13_aw_aerr_n[1:0],dfi_13_ctrlupd_req,dfi_13_phyupd_ack,dfi_13_clk_init,dfi_13_init_complete,dfi_13_out_rst_n,dfi_14_dw_rddata_p0[255:0],dfi_14_dw_rddata_dm_p0[31:0],dfi_14_dw_rddata_dbi_p0[31:0],dfi_14_dw_rddata_par_p0[7:0],dfi_14_dw_rddata_p1[255:0],dfi_14_dw_rddata_dm_p1[31:0],dfi_14_dw_rddata_dbi_p1[31:0],dfi_14_dw_rddata_par_p1[7:0],dfi_14_dbi_byte_disable[15:0],dfi_14_dw_rddata_valid[3:0],dfi_14_dw_derr_n[7:0],dfi_14_aw_aerr_n[1:0],dfi_14_ctrlupd_req,dfi_14_phyupd_ack,dfi_14_clk_init,dfi_14_init_complete,dfi_14_out_rst_n,dfi_15_dw_rddata_p0[255:0],dfi_15_dw_rddata_dm_p0[31:0],dfi_15_dw_rddata_dbi_p0[31:0],dfi_15_dw_rddata_par_p0[7:0],dfi_15_dw_rddata_p1[255:0],dfi_15_dw_rddata_dm_p1[31:0],dfi_15_dw_rddata_dbi_p1[31:0],dfi_15_dw_rddata_par_p1[7:0],dfi_15_dbi_byte_disable[15:0],dfi_15_dw_rddata_valid[3:0],dfi_15_dw_derr_n[7:0],dfi_15_aw_aerr_n[1:0],dfi_15_ctrlupd_req,dfi_15_phyupd_ack,dfi_15_clk_init,dfi_15_init_complete,dfi_15_out_rst_n,apb_complete_0,apb_complete_1,DRAM_0_STAT_CATTRIP,DRAM_0_STAT_TEMP[6:0],DRAM_1_STAT_CATTRIP,DRAM_1_STAT_TEMP[6:0]" */; + input HBM_REF_CLK_0; + input HBM_REF_CLK_1; + input dfi_0_clk; + input dfi_0_rst_n; + input dfi_0_init_start; + input [1:0]dfi_0_aw_ck_p0; + input [1:0]dfi_0_aw_cke_p0; + input [11:0]dfi_0_aw_row_p0; + input [15:0]dfi_0_aw_col_p0; + input [255:0]dfi_0_dw_wrdata_p0; + input [31:0]dfi_0_dw_wrdata_mask_p0; + input [31:0]dfi_0_dw_wrdata_dbi_p0; + input [7:0]dfi_0_dw_wrdata_par_p0; + input [7:0]dfi_0_dw_wrdata_dq_en_p0; + input [7:0]dfi_0_dw_wrdata_par_en_p0; + input [1:0]dfi_0_aw_ck_p1; + input [1:0]dfi_0_aw_cke_p1; + input [11:0]dfi_0_aw_row_p1; + input [15:0]dfi_0_aw_col_p1; + input [255:0]dfi_0_dw_wrdata_p1; + input [31:0]dfi_0_dw_wrdata_mask_p1; + input [31:0]dfi_0_dw_wrdata_dbi_p1; + input [7:0]dfi_0_dw_wrdata_par_p1; + input [7:0]dfi_0_dw_wrdata_dq_en_p1; + input [7:0]dfi_0_dw_wrdata_par_en_p1; + input dfi_0_aw_ck_dis; + input dfi_0_lp_pwr_e_req; + input dfi_0_lp_sr_e_req; + input dfi_0_lp_pwr_x_req; + input dfi_0_aw_tx_indx_ld; + input dfi_0_dw_tx_indx_ld; + input dfi_0_dw_rx_indx_ld; + input dfi_0_ctrlupd_ack; + input dfi_0_phyupd_req; + input [7:0]dfi_0_dw_wrdata_dqs_p0; + input [7:0]dfi_0_dw_wrdata_dqs_p1; + input dfi_1_clk; + input dfi_1_rst_n; + input dfi_1_init_start; + input [1:0]dfi_1_aw_ck_p0; + input [1:0]dfi_1_aw_cke_p0; + input [11:0]dfi_1_aw_row_p0; + input [15:0]dfi_1_aw_col_p0; + input [255:0]dfi_1_dw_wrdata_p0; + input [31:0]dfi_1_dw_wrdata_mask_p0; + input [31:0]dfi_1_dw_wrdata_dbi_p0; + input [7:0]dfi_1_dw_wrdata_par_p0; + input [7:0]dfi_1_dw_wrdata_dq_en_p0; + input [7:0]dfi_1_dw_wrdata_par_en_p0; + input [1:0]dfi_1_aw_ck_p1; + input [1:0]dfi_1_aw_cke_p1; + input [11:0]dfi_1_aw_row_p1; + input [15:0]dfi_1_aw_col_p1; + input [255:0]dfi_1_dw_wrdata_p1; + input [31:0]dfi_1_dw_wrdata_mask_p1; + input [31:0]dfi_1_dw_wrdata_dbi_p1; + input [7:0]dfi_1_dw_wrdata_par_p1; + input [7:0]dfi_1_dw_wrdata_dq_en_p1; + input [7:0]dfi_1_dw_wrdata_par_en_p1; + input dfi_1_aw_ck_dis; + input dfi_1_lp_pwr_e_req; + input dfi_1_lp_sr_e_req; + input dfi_1_lp_pwr_x_req; + input dfi_1_aw_tx_indx_ld; + input dfi_1_dw_tx_indx_ld; + input dfi_1_dw_rx_indx_ld; + input dfi_1_ctrlupd_ack; + input dfi_1_phyupd_req; + input [7:0]dfi_1_dw_wrdata_dqs_p0; + input [7:0]dfi_1_dw_wrdata_dqs_p1; + input dfi_2_clk; + input dfi_2_rst_n; + input dfi_2_init_start; + input [1:0]dfi_2_aw_ck_p0; + input [1:0]dfi_2_aw_cke_p0; + input [11:0]dfi_2_aw_row_p0; + input [15:0]dfi_2_aw_col_p0; + input [255:0]dfi_2_dw_wrdata_p0; + input [31:0]dfi_2_dw_wrdata_mask_p0; + input [31:0]dfi_2_dw_wrdata_dbi_p0; + input [7:0]dfi_2_dw_wrdata_par_p0; + input [7:0]dfi_2_dw_wrdata_dq_en_p0; + input [7:0]dfi_2_dw_wrdata_par_en_p0; + input [1:0]dfi_2_aw_ck_p1; + input [1:0]dfi_2_aw_cke_p1; + input [11:0]dfi_2_aw_row_p1; + input [15:0]dfi_2_aw_col_p1; + input [255:0]dfi_2_dw_wrdata_p1; + input [31:0]dfi_2_dw_wrdata_mask_p1; + input [31:0]dfi_2_dw_wrdata_dbi_p1; + input [7:0]dfi_2_dw_wrdata_par_p1; + input [7:0]dfi_2_dw_wrdata_dq_en_p1; + input [7:0]dfi_2_dw_wrdata_par_en_p1; + input dfi_2_aw_ck_dis; + input dfi_2_lp_pwr_e_req; + input dfi_2_lp_sr_e_req; + input dfi_2_lp_pwr_x_req; + input dfi_2_aw_tx_indx_ld; + input dfi_2_dw_tx_indx_ld; + input dfi_2_dw_rx_indx_ld; + input dfi_2_ctrlupd_ack; + input dfi_2_phyupd_req; + input [7:0]dfi_2_dw_wrdata_dqs_p0; + input [7:0]dfi_2_dw_wrdata_dqs_p1; + input dfi_3_clk; + input dfi_3_rst_n; + input dfi_3_init_start; + input [1:0]dfi_3_aw_ck_p0; + input [1:0]dfi_3_aw_cke_p0; + input [11:0]dfi_3_aw_row_p0; + input [15:0]dfi_3_aw_col_p0; + input [255:0]dfi_3_dw_wrdata_p0; + input [31:0]dfi_3_dw_wrdata_mask_p0; + input [31:0]dfi_3_dw_wrdata_dbi_p0; + input [7:0]dfi_3_dw_wrdata_par_p0; + input [7:0]dfi_3_dw_wrdata_dq_en_p0; + input [7:0]dfi_3_dw_wrdata_par_en_p0; + input [1:0]dfi_3_aw_ck_p1; + input [1:0]dfi_3_aw_cke_p1; + input [11:0]dfi_3_aw_row_p1; + input [15:0]dfi_3_aw_col_p1; + input [255:0]dfi_3_dw_wrdata_p1; + input [31:0]dfi_3_dw_wrdata_mask_p1; + input [31:0]dfi_3_dw_wrdata_dbi_p1; + input [7:0]dfi_3_dw_wrdata_par_p1; + input [7:0]dfi_3_dw_wrdata_dq_en_p1; + input [7:0]dfi_3_dw_wrdata_par_en_p1; + input dfi_3_aw_ck_dis; + input dfi_3_lp_pwr_e_req; + input dfi_3_lp_sr_e_req; + input dfi_3_lp_pwr_x_req; + input dfi_3_aw_tx_indx_ld; + input dfi_3_dw_tx_indx_ld; + input dfi_3_dw_rx_indx_ld; + input dfi_3_ctrlupd_ack; + input dfi_3_phyupd_req; + input [7:0]dfi_3_dw_wrdata_dqs_p0; + input [7:0]dfi_3_dw_wrdata_dqs_p1; + input dfi_4_clk; + input dfi_4_rst_n; + input dfi_4_init_start; + input [1:0]dfi_4_aw_ck_p0; + input [1:0]dfi_4_aw_cke_p0; + input [11:0]dfi_4_aw_row_p0; + input [15:0]dfi_4_aw_col_p0; + input [255:0]dfi_4_dw_wrdata_p0; + input [31:0]dfi_4_dw_wrdata_mask_p0; + input [31:0]dfi_4_dw_wrdata_dbi_p0; + input [7:0]dfi_4_dw_wrdata_par_p0; + input [7:0]dfi_4_dw_wrdata_dq_en_p0; + input [7:0]dfi_4_dw_wrdata_par_en_p0; + input [1:0]dfi_4_aw_ck_p1; + input [1:0]dfi_4_aw_cke_p1; + input [11:0]dfi_4_aw_row_p1; + input [15:0]dfi_4_aw_col_p1; + input [255:0]dfi_4_dw_wrdata_p1; + input [31:0]dfi_4_dw_wrdata_mask_p1; + input [31:0]dfi_4_dw_wrdata_dbi_p1; + input [7:0]dfi_4_dw_wrdata_par_p1; + input [7:0]dfi_4_dw_wrdata_dq_en_p1; + input [7:0]dfi_4_dw_wrdata_par_en_p1; + input dfi_4_aw_ck_dis; + input dfi_4_lp_pwr_e_req; + input dfi_4_lp_sr_e_req; + input dfi_4_lp_pwr_x_req; + input dfi_4_aw_tx_indx_ld; + input dfi_4_dw_tx_indx_ld; + input dfi_4_dw_rx_indx_ld; + input dfi_4_ctrlupd_ack; + input dfi_4_phyupd_req; + input [7:0]dfi_4_dw_wrdata_dqs_p0; + input [7:0]dfi_4_dw_wrdata_dqs_p1; + input dfi_5_clk; + input dfi_5_rst_n; + input dfi_5_init_start; + input [1:0]dfi_5_aw_ck_p0; + input [1:0]dfi_5_aw_cke_p0; + input [11:0]dfi_5_aw_row_p0; + input [15:0]dfi_5_aw_col_p0; + input [255:0]dfi_5_dw_wrdata_p0; + input [31:0]dfi_5_dw_wrdata_mask_p0; + input [31:0]dfi_5_dw_wrdata_dbi_p0; + input [7:0]dfi_5_dw_wrdata_par_p0; + input [7:0]dfi_5_dw_wrdata_dq_en_p0; + input [7:0]dfi_5_dw_wrdata_par_en_p0; + input [1:0]dfi_5_aw_ck_p1; + input [1:0]dfi_5_aw_cke_p1; + input [11:0]dfi_5_aw_row_p1; + input [15:0]dfi_5_aw_col_p1; + input [255:0]dfi_5_dw_wrdata_p1; + input [31:0]dfi_5_dw_wrdata_mask_p1; + input [31:0]dfi_5_dw_wrdata_dbi_p1; + input [7:0]dfi_5_dw_wrdata_par_p1; + input [7:0]dfi_5_dw_wrdata_dq_en_p1; + input [7:0]dfi_5_dw_wrdata_par_en_p1; + input dfi_5_aw_ck_dis; + input dfi_5_lp_pwr_e_req; + input dfi_5_lp_sr_e_req; + input dfi_5_lp_pwr_x_req; + input dfi_5_aw_tx_indx_ld; + input dfi_5_dw_tx_indx_ld; + input dfi_5_dw_rx_indx_ld; + input dfi_5_ctrlupd_ack; + input dfi_5_phyupd_req; + input [7:0]dfi_5_dw_wrdata_dqs_p0; + input [7:0]dfi_5_dw_wrdata_dqs_p1; + input dfi_6_clk; + input dfi_6_rst_n; + input dfi_6_init_start; + input [1:0]dfi_6_aw_ck_p0; + input [1:0]dfi_6_aw_cke_p0; + input [11:0]dfi_6_aw_row_p0; + input [15:0]dfi_6_aw_col_p0; + input [255:0]dfi_6_dw_wrdata_p0; + input [31:0]dfi_6_dw_wrdata_mask_p0; + input [31:0]dfi_6_dw_wrdata_dbi_p0; + input [7:0]dfi_6_dw_wrdata_par_p0; + input [7:0]dfi_6_dw_wrdata_dq_en_p0; + input [7:0]dfi_6_dw_wrdata_par_en_p0; + input [1:0]dfi_6_aw_ck_p1; + input [1:0]dfi_6_aw_cke_p1; + input [11:0]dfi_6_aw_row_p1; + input [15:0]dfi_6_aw_col_p1; + input [255:0]dfi_6_dw_wrdata_p1; + input [31:0]dfi_6_dw_wrdata_mask_p1; + input [31:0]dfi_6_dw_wrdata_dbi_p1; + input [7:0]dfi_6_dw_wrdata_par_p1; + input [7:0]dfi_6_dw_wrdata_dq_en_p1; + input [7:0]dfi_6_dw_wrdata_par_en_p1; + input dfi_6_aw_ck_dis; + input dfi_6_lp_pwr_e_req; + input dfi_6_lp_sr_e_req; + input dfi_6_lp_pwr_x_req; + input dfi_6_aw_tx_indx_ld; + input dfi_6_dw_tx_indx_ld; + input dfi_6_dw_rx_indx_ld; + input dfi_6_ctrlupd_ack; + input dfi_6_phyupd_req; + input [7:0]dfi_6_dw_wrdata_dqs_p0; + input [7:0]dfi_6_dw_wrdata_dqs_p1; + input dfi_7_clk; + input dfi_7_rst_n; + input dfi_7_init_start; + input [1:0]dfi_7_aw_ck_p0; + input [1:0]dfi_7_aw_cke_p0; + input [11:0]dfi_7_aw_row_p0; + input [15:0]dfi_7_aw_col_p0; + input [255:0]dfi_7_dw_wrdata_p0; + input [31:0]dfi_7_dw_wrdata_mask_p0; + input [31:0]dfi_7_dw_wrdata_dbi_p0; + input [7:0]dfi_7_dw_wrdata_par_p0; + input [7:0]dfi_7_dw_wrdata_dq_en_p0; + input [7:0]dfi_7_dw_wrdata_par_en_p0; + input [1:0]dfi_7_aw_ck_p1; + input [1:0]dfi_7_aw_cke_p1; + input [11:0]dfi_7_aw_row_p1; + input [15:0]dfi_7_aw_col_p1; + input [255:0]dfi_7_dw_wrdata_p1; + input [31:0]dfi_7_dw_wrdata_mask_p1; + input [31:0]dfi_7_dw_wrdata_dbi_p1; + input [7:0]dfi_7_dw_wrdata_par_p1; + input [7:0]dfi_7_dw_wrdata_dq_en_p1; + input [7:0]dfi_7_dw_wrdata_par_en_p1; + input dfi_7_aw_ck_dis; + input dfi_7_lp_pwr_e_req; + input dfi_7_lp_sr_e_req; + input dfi_7_lp_pwr_x_req; + input dfi_7_aw_tx_indx_ld; + input dfi_7_dw_tx_indx_ld; + input dfi_7_dw_rx_indx_ld; + input dfi_7_ctrlupd_ack; + input dfi_7_phyupd_req; + input [7:0]dfi_7_dw_wrdata_dqs_p0; + input [7:0]dfi_7_dw_wrdata_dqs_p1; + input dfi_8_clk; + input dfi_8_rst_n; + input dfi_8_init_start; + input [1:0]dfi_8_aw_ck_p0; + input [1:0]dfi_8_aw_cke_p0; + input [11:0]dfi_8_aw_row_p0; + input [15:0]dfi_8_aw_col_p0; + input [255:0]dfi_8_dw_wrdata_p0; + input [31:0]dfi_8_dw_wrdata_mask_p0; + input [31:0]dfi_8_dw_wrdata_dbi_p0; + input [7:0]dfi_8_dw_wrdata_par_p0; + input [7:0]dfi_8_dw_wrdata_dq_en_p0; + input [7:0]dfi_8_dw_wrdata_par_en_p0; + input [1:0]dfi_8_aw_ck_p1; + input [1:0]dfi_8_aw_cke_p1; + input [11:0]dfi_8_aw_row_p1; + input [15:0]dfi_8_aw_col_p1; + input [255:0]dfi_8_dw_wrdata_p1; + input [31:0]dfi_8_dw_wrdata_mask_p1; + input [31:0]dfi_8_dw_wrdata_dbi_p1; + input [7:0]dfi_8_dw_wrdata_par_p1; + input [7:0]dfi_8_dw_wrdata_dq_en_p1; + input [7:0]dfi_8_dw_wrdata_par_en_p1; + input dfi_8_aw_ck_dis; + input dfi_8_lp_pwr_e_req; + input dfi_8_lp_sr_e_req; + input dfi_8_lp_pwr_x_req; + input dfi_8_aw_tx_indx_ld; + input dfi_8_dw_tx_indx_ld; + input dfi_8_dw_rx_indx_ld; + input dfi_8_ctrlupd_ack; + input dfi_8_phyupd_req; + input [7:0]dfi_8_dw_wrdata_dqs_p0; + input [7:0]dfi_8_dw_wrdata_dqs_p1; + input dfi_9_clk; + input dfi_9_rst_n; + input dfi_9_init_start; + input [1:0]dfi_9_aw_ck_p0; + input [1:0]dfi_9_aw_cke_p0; + input [11:0]dfi_9_aw_row_p0; + input [15:0]dfi_9_aw_col_p0; + input [255:0]dfi_9_dw_wrdata_p0; + input [31:0]dfi_9_dw_wrdata_mask_p0; + input [31:0]dfi_9_dw_wrdata_dbi_p0; + input [7:0]dfi_9_dw_wrdata_par_p0; + input [7:0]dfi_9_dw_wrdata_dq_en_p0; + input [7:0]dfi_9_dw_wrdata_par_en_p0; + input [1:0]dfi_9_aw_ck_p1; + input [1:0]dfi_9_aw_cke_p1; + input [11:0]dfi_9_aw_row_p1; + input [15:0]dfi_9_aw_col_p1; + input [255:0]dfi_9_dw_wrdata_p1; + input [31:0]dfi_9_dw_wrdata_mask_p1; + input [31:0]dfi_9_dw_wrdata_dbi_p1; + input [7:0]dfi_9_dw_wrdata_par_p1; + input [7:0]dfi_9_dw_wrdata_dq_en_p1; + input [7:0]dfi_9_dw_wrdata_par_en_p1; + input dfi_9_aw_ck_dis; + input dfi_9_lp_pwr_e_req; + input dfi_9_lp_sr_e_req; + input dfi_9_lp_pwr_x_req; + input dfi_9_aw_tx_indx_ld; + input dfi_9_dw_tx_indx_ld; + input dfi_9_dw_rx_indx_ld; + input dfi_9_ctrlupd_ack; + input dfi_9_phyupd_req; + input [7:0]dfi_9_dw_wrdata_dqs_p0; + input [7:0]dfi_9_dw_wrdata_dqs_p1; + input dfi_10_clk; + input dfi_10_rst_n; + input dfi_10_init_start; + input [1:0]dfi_10_aw_ck_p0; + input [1:0]dfi_10_aw_cke_p0; + input [11:0]dfi_10_aw_row_p0; + input [15:0]dfi_10_aw_col_p0; + input [255:0]dfi_10_dw_wrdata_p0; + input [31:0]dfi_10_dw_wrdata_mask_p0; + input [31:0]dfi_10_dw_wrdata_dbi_p0; + input [7:0]dfi_10_dw_wrdata_par_p0; + input [7:0]dfi_10_dw_wrdata_dq_en_p0; + input [7:0]dfi_10_dw_wrdata_par_en_p0; + input [1:0]dfi_10_aw_ck_p1; + input [1:0]dfi_10_aw_cke_p1; + input [11:0]dfi_10_aw_row_p1; + input [15:0]dfi_10_aw_col_p1; + input [255:0]dfi_10_dw_wrdata_p1; + input [31:0]dfi_10_dw_wrdata_mask_p1; + input [31:0]dfi_10_dw_wrdata_dbi_p1; + input [7:0]dfi_10_dw_wrdata_par_p1; + input [7:0]dfi_10_dw_wrdata_dq_en_p1; + input [7:0]dfi_10_dw_wrdata_par_en_p1; + input dfi_10_aw_ck_dis; + input dfi_10_lp_pwr_e_req; + input dfi_10_lp_sr_e_req; + input dfi_10_lp_pwr_x_req; + input dfi_10_aw_tx_indx_ld; + input dfi_10_dw_tx_indx_ld; + input dfi_10_dw_rx_indx_ld; + input dfi_10_ctrlupd_ack; + input dfi_10_phyupd_req; + input [7:0]dfi_10_dw_wrdata_dqs_p0; + input [7:0]dfi_10_dw_wrdata_dqs_p1; + input dfi_11_clk; + input dfi_11_rst_n; + input dfi_11_init_start; + input [1:0]dfi_11_aw_ck_p0; + input [1:0]dfi_11_aw_cke_p0; + input [11:0]dfi_11_aw_row_p0; + input [15:0]dfi_11_aw_col_p0; + input [255:0]dfi_11_dw_wrdata_p0; + input [31:0]dfi_11_dw_wrdata_mask_p0; + input [31:0]dfi_11_dw_wrdata_dbi_p0; + input [7:0]dfi_11_dw_wrdata_par_p0; + input [7:0]dfi_11_dw_wrdata_dq_en_p0; + input [7:0]dfi_11_dw_wrdata_par_en_p0; + input [1:0]dfi_11_aw_ck_p1; + input [1:0]dfi_11_aw_cke_p1; + input [11:0]dfi_11_aw_row_p1; + input [15:0]dfi_11_aw_col_p1; + input [255:0]dfi_11_dw_wrdata_p1; + input [31:0]dfi_11_dw_wrdata_mask_p1; + input [31:0]dfi_11_dw_wrdata_dbi_p1; + input [7:0]dfi_11_dw_wrdata_par_p1; + input [7:0]dfi_11_dw_wrdata_dq_en_p1; + input [7:0]dfi_11_dw_wrdata_par_en_p1; + input dfi_11_aw_ck_dis; + input dfi_11_lp_pwr_e_req; + input dfi_11_lp_sr_e_req; + input dfi_11_lp_pwr_x_req; + input dfi_11_aw_tx_indx_ld; + input dfi_11_dw_tx_indx_ld; + input dfi_11_dw_rx_indx_ld; + input dfi_11_ctrlupd_ack; + input dfi_11_phyupd_req; + input [7:0]dfi_11_dw_wrdata_dqs_p0; + input [7:0]dfi_11_dw_wrdata_dqs_p1; + input dfi_12_clk; + input dfi_12_rst_n; + input dfi_12_init_start; + input [1:0]dfi_12_aw_ck_p0; + input [1:0]dfi_12_aw_cke_p0; + input [11:0]dfi_12_aw_row_p0; + input [15:0]dfi_12_aw_col_p0; + input [255:0]dfi_12_dw_wrdata_p0; + input [31:0]dfi_12_dw_wrdata_mask_p0; + input [31:0]dfi_12_dw_wrdata_dbi_p0; + input [7:0]dfi_12_dw_wrdata_par_p0; + input [7:0]dfi_12_dw_wrdata_dq_en_p0; + input [7:0]dfi_12_dw_wrdata_par_en_p0; + input [1:0]dfi_12_aw_ck_p1; + input [1:0]dfi_12_aw_cke_p1; + input [11:0]dfi_12_aw_row_p1; + input [15:0]dfi_12_aw_col_p1; + input [255:0]dfi_12_dw_wrdata_p1; + input [31:0]dfi_12_dw_wrdata_mask_p1; + input [31:0]dfi_12_dw_wrdata_dbi_p1; + input [7:0]dfi_12_dw_wrdata_par_p1; + input [7:0]dfi_12_dw_wrdata_dq_en_p1; + input [7:0]dfi_12_dw_wrdata_par_en_p1; + input dfi_12_aw_ck_dis; + input dfi_12_lp_pwr_e_req; + input dfi_12_lp_sr_e_req; + input dfi_12_lp_pwr_x_req; + input dfi_12_aw_tx_indx_ld; + input dfi_12_dw_tx_indx_ld; + input dfi_12_dw_rx_indx_ld; + input dfi_12_ctrlupd_ack; + input dfi_12_phyupd_req; + input [7:0]dfi_12_dw_wrdata_dqs_p0; + input [7:0]dfi_12_dw_wrdata_dqs_p1; + input dfi_13_clk; + input dfi_13_rst_n; + input dfi_13_init_start; + input [1:0]dfi_13_aw_ck_p0; + input [1:0]dfi_13_aw_cke_p0; + input [11:0]dfi_13_aw_row_p0; + input [15:0]dfi_13_aw_col_p0; + input [255:0]dfi_13_dw_wrdata_p0; + input [31:0]dfi_13_dw_wrdata_mask_p0; + input [31:0]dfi_13_dw_wrdata_dbi_p0; + input [7:0]dfi_13_dw_wrdata_par_p0; + input [7:0]dfi_13_dw_wrdata_dq_en_p0; + input [7:0]dfi_13_dw_wrdata_par_en_p0; + input [1:0]dfi_13_aw_ck_p1; + input [1:0]dfi_13_aw_cke_p1; + input [11:0]dfi_13_aw_row_p1; + input [15:0]dfi_13_aw_col_p1; + input [255:0]dfi_13_dw_wrdata_p1; + input [31:0]dfi_13_dw_wrdata_mask_p1; + input [31:0]dfi_13_dw_wrdata_dbi_p1; + input [7:0]dfi_13_dw_wrdata_par_p1; + input [7:0]dfi_13_dw_wrdata_dq_en_p1; + input [7:0]dfi_13_dw_wrdata_par_en_p1; + input dfi_13_aw_ck_dis; + input dfi_13_lp_pwr_e_req; + input dfi_13_lp_sr_e_req; + input dfi_13_lp_pwr_x_req; + input dfi_13_aw_tx_indx_ld; + input dfi_13_dw_tx_indx_ld; + input dfi_13_dw_rx_indx_ld; + input dfi_13_ctrlupd_ack; + input dfi_13_phyupd_req; + input [7:0]dfi_13_dw_wrdata_dqs_p0; + input [7:0]dfi_13_dw_wrdata_dqs_p1; + input dfi_14_clk; + input dfi_14_rst_n; + input dfi_14_init_start; + input [1:0]dfi_14_aw_ck_p0; + input [1:0]dfi_14_aw_cke_p0; + input [11:0]dfi_14_aw_row_p0; + input [15:0]dfi_14_aw_col_p0; + input [255:0]dfi_14_dw_wrdata_p0; + input [31:0]dfi_14_dw_wrdata_mask_p0; + input [31:0]dfi_14_dw_wrdata_dbi_p0; + input [7:0]dfi_14_dw_wrdata_par_p0; + input [7:0]dfi_14_dw_wrdata_dq_en_p0; + input [7:0]dfi_14_dw_wrdata_par_en_p0; + input [1:0]dfi_14_aw_ck_p1; + input [1:0]dfi_14_aw_cke_p1; + input [11:0]dfi_14_aw_row_p1; + input [15:0]dfi_14_aw_col_p1; + input [255:0]dfi_14_dw_wrdata_p1; + input [31:0]dfi_14_dw_wrdata_mask_p1; + input [31:0]dfi_14_dw_wrdata_dbi_p1; + input [7:0]dfi_14_dw_wrdata_par_p1; + input [7:0]dfi_14_dw_wrdata_dq_en_p1; + input [7:0]dfi_14_dw_wrdata_par_en_p1; + input dfi_14_aw_ck_dis; + input dfi_14_lp_pwr_e_req; + input dfi_14_lp_sr_e_req; + input dfi_14_lp_pwr_x_req; + input dfi_14_aw_tx_indx_ld; + input dfi_14_dw_tx_indx_ld; + input dfi_14_dw_rx_indx_ld; + input dfi_14_ctrlupd_ack; + input dfi_14_phyupd_req; + input [7:0]dfi_14_dw_wrdata_dqs_p0; + input [7:0]dfi_14_dw_wrdata_dqs_p1; + input dfi_15_clk; + input dfi_15_rst_n; + input dfi_15_init_start; + input [1:0]dfi_15_aw_ck_p0; + input [1:0]dfi_15_aw_cke_p0; + input [11:0]dfi_15_aw_row_p0; + input [15:0]dfi_15_aw_col_p0; + input [255:0]dfi_15_dw_wrdata_p0; + input [31:0]dfi_15_dw_wrdata_mask_p0; + input [31:0]dfi_15_dw_wrdata_dbi_p0; + input [7:0]dfi_15_dw_wrdata_par_p0; + input [7:0]dfi_15_dw_wrdata_dq_en_p0; + input [7:0]dfi_15_dw_wrdata_par_en_p0; + input [1:0]dfi_15_aw_ck_p1; + input [1:0]dfi_15_aw_cke_p1; + input [11:0]dfi_15_aw_row_p1; + input [15:0]dfi_15_aw_col_p1; + input [255:0]dfi_15_dw_wrdata_p1; + input [31:0]dfi_15_dw_wrdata_mask_p1; + input [31:0]dfi_15_dw_wrdata_dbi_p1; + input [7:0]dfi_15_dw_wrdata_par_p1; + input [7:0]dfi_15_dw_wrdata_dq_en_p1; + input [7:0]dfi_15_dw_wrdata_par_en_p1; + input dfi_15_aw_ck_dis; + input dfi_15_lp_pwr_e_req; + input dfi_15_lp_sr_e_req; + input dfi_15_lp_pwr_x_req; + input dfi_15_aw_tx_indx_ld; + input dfi_15_dw_tx_indx_ld; + input dfi_15_dw_rx_indx_ld; + input dfi_15_ctrlupd_ack; + input dfi_15_phyupd_req; + input [7:0]dfi_15_dw_wrdata_dqs_p0; + input [7:0]dfi_15_dw_wrdata_dqs_p1; + input APB_0_PCLK; + input APB_0_PRESET_N; + input APB_1_PCLK; + input APB_1_PRESET_N; + output [255:0]dfi_0_dw_rddata_p0; + output [31:0]dfi_0_dw_rddata_dm_p0; + output [31:0]dfi_0_dw_rddata_dbi_p0; + output [7:0]dfi_0_dw_rddata_par_p0; + output [255:0]dfi_0_dw_rddata_p1; + output [31:0]dfi_0_dw_rddata_dm_p1; + output [31:0]dfi_0_dw_rddata_dbi_p1; + output [7:0]dfi_0_dw_rddata_par_p1; + output [15:0]dfi_0_dbi_byte_disable; + output [3:0]dfi_0_dw_rddata_valid; + output [7:0]dfi_0_dw_derr_n; + output [1:0]dfi_0_aw_aerr_n; + output dfi_0_ctrlupd_req; + output dfi_0_phyupd_ack; + output dfi_0_clk_init; + output dfi_0_init_complete; + output dfi_0_out_rst_n; + output [255:0]dfi_1_dw_rddata_p0; + output [31:0]dfi_1_dw_rddata_dm_p0; + output [31:0]dfi_1_dw_rddata_dbi_p0; + output [7:0]dfi_1_dw_rddata_par_p0; + output [255:0]dfi_1_dw_rddata_p1; + output [31:0]dfi_1_dw_rddata_dm_p1; + output [31:0]dfi_1_dw_rddata_dbi_p1; + output [7:0]dfi_1_dw_rddata_par_p1; + output [15:0]dfi_1_dbi_byte_disable; + output [3:0]dfi_1_dw_rddata_valid; + output [7:0]dfi_1_dw_derr_n; + output [1:0]dfi_1_aw_aerr_n; + output dfi_1_ctrlupd_req; + output dfi_1_phyupd_ack; + output dfi_1_clk_init; + output dfi_1_init_complete; + output dfi_1_out_rst_n; + output [255:0]dfi_2_dw_rddata_p0; + output [31:0]dfi_2_dw_rddata_dm_p0; + output [31:0]dfi_2_dw_rddata_dbi_p0; + output [7:0]dfi_2_dw_rddata_par_p0; + output [255:0]dfi_2_dw_rddata_p1; + output [31:0]dfi_2_dw_rddata_dm_p1; + output [31:0]dfi_2_dw_rddata_dbi_p1; + output [7:0]dfi_2_dw_rddata_par_p1; + output [15:0]dfi_2_dbi_byte_disable; + output [3:0]dfi_2_dw_rddata_valid; + output [7:0]dfi_2_dw_derr_n; + output [1:0]dfi_2_aw_aerr_n; + output dfi_2_ctrlupd_req; + output dfi_2_phyupd_ack; + output dfi_2_clk_init; + output dfi_2_init_complete; + output dfi_2_out_rst_n; + output [255:0]dfi_3_dw_rddata_p0; + output [31:0]dfi_3_dw_rddata_dm_p0; + output [31:0]dfi_3_dw_rddata_dbi_p0; + output [7:0]dfi_3_dw_rddata_par_p0; + output [255:0]dfi_3_dw_rddata_p1; + output [31:0]dfi_3_dw_rddata_dm_p1; + output [31:0]dfi_3_dw_rddata_dbi_p1; + output [7:0]dfi_3_dw_rddata_par_p1; + output [15:0]dfi_3_dbi_byte_disable; + output [3:0]dfi_3_dw_rddata_valid; + output [7:0]dfi_3_dw_derr_n; + output [1:0]dfi_3_aw_aerr_n; + output dfi_3_ctrlupd_req; + output dfi_3_phyupd_ack; + output dfi_3_clk_init; + output dfi_3_init_complete; + output dfi_3_out_rst_n; + output [255:0]dfi_4_dw_rddata_p0; + output [31:0]dfi_4_dw_rddata_dm_p0; + output [31:0]dfi_4_dw_rddata_dbi_p0; + output [7:0]dfi_4_dw_rddata_par_p0; + output [255:0]dfi_4_dw_rddata_p1; + output [31:0]dfi_4_dw_rddata_dm_p1; + output [31:0]dfi_4_dw_rddata_dbi_p1; + output [7:0]dfi_4_dw_rddata_par_p1; + output [15:0]dfi_4_dbi_byte_disable; + output [3:0]dfi_4_dw_rddata_valid; + output [7:0]dfi_4_dw_derr_n; + output [1:0]dfi_4_aw_aerr_n; + output dfi_4_ctrlupd_req; + output dfi_4_phyupd_ack; + output dfi_4_clk_init; + output dfi_4_init_complete; + output dfi_4_out_rst_n; + output [255:0]dfi_5_dw_rddata_p0; + output [31:0]dfi_5_dw_rddata_dm_p0; + output [31:0]dfi_5_dw_rddata_dbi_p0; + output [7:0]dfi_5_dw_rddata_par_p0; + output [255:0]dfi_5_dw_rddata_p1; + output [31:0]dfi_5_dw_rddata_dm_p1; + output [31:0]dfi_5_dw_rddata_dbi_p1; + output [7:0]dfi_5_dw_rddata_par_p1; + output [15:0]dfi_5_dbi_byte_disable; + output [3:0]dfi_5_dw_rddata_valid; + output [7:0]dfi_5_dw_derr_n; + output [1:0]dfi_5_aw_aerr_n; + output dfi_5_ctrlupd_req; + output dfi_5_phyupd_ack; + output dfi_5_clk_init; + output dfi_5_init_complete; + output dfi_5_out_rst_n; + output [255:0]dfi_6_dw_rddata_p0; + output [31:0]dfi_6_dw_rddata_dm_p0; + output [31:0]dfi_6_dw_rddata_dbi_p0; + output [7:0]dfi_6_dw_rddata_par_p0; + output [255:0]dfi_6_dw_rddata_p1; + output [31:0]dfi_6_dw_rddata_dm_p1; + output [31:0]dfi_6_dw_rddata_dbi_p1; + output [7:0]dfi_6_dw_rddata_par_p1; + output [15:0]dfi_6_dbi_byte_disable; + output [3:0]dfi_6_dw_rddata_valid; + output [7:0]dfi_6_dw_derr_n; + output [1:0]dfi_6_aw_aerr_n; + output dfi_6_ctrlupd_req; + output dfi_6_phyupd_ack; + output dfi_6_clk_init; + output dfi_6_init_complete; + output dfi_6_out_rst_n; + output [255:0]dfi_7_dw_rddata_p0; + output [31:0]dfi_7_dw_rddata_dm_p0; + output [31:0]dfi_7_dw_rddata_dbi_p0; + output [7:0]dfi_7_dw_rddata_par_p0; + output [255:0]dfi_7_dw_rddata_p1; + output [31:0]dfi_7_dw_rddata_dm_p1; + output [31:0]dfi_7_dw_rddata_dbi_p1; + output [7:0]dfi_7_dw_rddata_par_p1; + output [15:0]dfi_7_dbi_byte_disable; + output [3:0]dfi_7_dw_rddata_valid; + output [7:0]dfi_7_dw_derr_n; + output [1:0]dfi_7_aw_aerr_n; + output dfi_7_ctrlupd_req; + output dfi_7_phyupd_ack; + output dfi_7_clk_init; + output dfi_7_init_complete; + output dfi_7_out_rst_n; + output [255:0]dfi_8_dw_rddata_p0; + output [31:0]dfi_8_dw_rddata_dm_p0; + output [31:0]dfi_8_dw_rddata_dbi_p0; + output [7:0]dfi_8_dw_rddata_par_p0; + output [255:0]dfi_8_dw_rddata_p1; + output [31:0]dfi_8_dw_rddata_dm_p1; + output [31:0]dfi_8_dw_rddata_dbi_p1; + output [7:0]dfi_8_dw_rddata_par_p1; + output [15:0]dfi_8_dbi_byte_disable; + output [3:0]dfi_8_dw_rddata_valid; + output [7:0]dfi_8_dw_derr_n; + output [1:0]dfi_8_aw_aerr_n; + output dfi_8_ctrlupd_req; + output dfi_8_phyupd_ack; + output dfi_8_clk_init; + output dfi_8_init_complete; + output dfi_8_out_rst_n; + output [255:0]dfi_9_dw_rddata_p0; + output [31:0]dfi_9_dw_rddata_dm_p0; + output [31:0]dfi_9_dw_rddata_dbi_p0; + output [7:0]dfi_9_dw_rddata_par_p0; + output [255:0]dfi_9_dw_rddata_p1; + output [31:0]dfi_9_dw_rddata_dm_p1; + output [31:0]dfi_9_dw_rddata_dbi_p1; + output [7:0]dfi_9_dw_rddata_par_p1; + output [15:0]dfi_9_dbi_byte_disable; + output [3:0]dfi_9_dw_rddata_valid; + output [7:0]dfi_9_dw_derr_n; + output [1:0]dfi_9_aw_aerr_n; + output dfi_9_ctrlupd_req; + output dfi_9_phyupd_ack; + output dfi_9_clk_init; + output dfi_9_init_complete; + output dfi_9_out_rst_n; + output [255:0]dfi_10_dw_rddata_p0; + output [31:0]dfi_10_dw_rddata_dm_p0; + output [31:0]dfi_10_dw_rddata_dbi_p0; + output [7:0]dfi_10_dw_rddata_par_p0; + output [255:0]dfi_10_dw_rddata_p1; + output [31:0]dfi_10_dw_rddata_dm_p1; + output [31:0]dfi_10_dw_rddata_dbi_p1; + output [7:0]dfi_10_dw_rddata_par_p1; + output [15:0]dfi_10_dbi_byte_disable; + output [3:0]dfi_10_dw_rddata_valid; + output [7:0]dfi_10_dw_derr_n; + output [1:0]dfi_10_aw_aerr_n; + output dfi_10_ctrlupd_req; + output dfi_10_phyupd_ack; + output dfi_10_clk_init; + output dfi_10_init_complete; + output dfi_10_out_rst_n; + output [255:0]dfi_11_dw_rddata_p0; + output [31:0]dfi_11_dw_rddata_dm_p0; + output [31:0]dfi_11_dw_rddata_dbi_p0; + output [7:0]dfi_11_dw_rddata_par_p0; + output [255:0]dfi_11_dw_rddata_p1; + output [31:0]dfi_11_dw_rddata_dm_p1; + output [31:0]dfi_11_dw_rddata_dbi_p1; + output [7:0]dfi_11_dw_rddata_par_p1; + output [15:0]dfi_11_dbi_byte_disable; + output [3:0]dfi_11_dw_rddata_valid; + output [7:0]dfi_11_dw_derr_n; + output [1:0]dfi_11_aw_aerr_n; + output dfi_11_ctrlupd_req; + output dfi_11_phyupd_ack; + output dfi_11_clk_init; + output dfi_11_init_complete; + output dfi_11_out_rst_n; + output [255:0]dfi_12_dw_rddata_p0; + output [31:0]dfi_12_dw_rddata_dm_p0; + output [31:0]dfi_12_dw_rddata_dbi_p0; + output [7:0]dfi_12_dw_rddata_par_p0; + output [255:0]dfi_12_dw_rddata_p1; + output [31:0]dfi_12_dw_rddata_dm_p1; + output [31:0]dfi_12_dw_rddata_dbi_p1; + output [7:0]dfi_12_dw_rddata_par_p1; + output [15:0]dfi_12_dbi_byte_disable; + output [3:0]dfi_12_dw_rddata_valid; + output [7:0]dfi_12_dw_derr_n; + output [1:0]dfi_12_aw_aerr_n; + output dfi_12_ctrlupd_req; + output dfi_12_phyupd_ack; + output dfi_12_clk_init; + output dfi_12_init_complete; + output dfi_12_out_rst_n; + output [255:0]dfi_13_dw_rddata_p0; + output [31:0]dfi_13_dw_rddata_dm_p0; + output [31:0]dfi_13_dw_rddata_dbi_p0; + output [7:0]dfi_13_dw_rddata_par_p0; + output [255:0]dfi_13_dw_rddata_p1; + output [31:0]dfi_13_dw_rddata_dm_p1; + output [31:0]dfi_13_dw_rddata_dbi_p1; + output [7:0]dfi_13_dw_rddata_par_p1; + output [15:0]dfi_13_dbi_byte_disable; + output [3:0]dfi_13_dw_rddata_valid; + output [7:0]dfi_13_dw_derr_n; + output [1:0]dfi_13_aw_aerr_n; + output dfi_13_ctrlupd_req; + output dfi_13_phyupd_ack; + output dfi_13_clk_init; + output dfi_13_init_complete; + output dfi_13_out_rst_n; + output [255:0]dfi_14_dw_rddata_p0; + output [31:0]dfi_14_dw_rddata_dm_p0; + output [31:0]dfi_14_dw_rddata_dbi_p0; + output [7:0]dfi_14_dw_rddata_par_p0; + output [255:0]dfi_14_dw_rddata_p1; + output [31:0]dfi_14_dw_rddata_dm_p1; + output [31:0]dfi_14_dw_rddata_dbi_p1; + output [7:0]dfi_14_dw_rddata_par_p1; + output [15:0]dfi_14_dbi_byte_disable; + output [3:0]dfi_14_dw_rddata_valid; + output [7:0]dfi_14_dw_derr_n; + output [1:0]dfi_14_aw_aerr_n; + output dfi_14_ctrlupd_req; + output dfi_14_phyupd_ack; + output dfi_14_clk_init; + output dfi_14_init_complete; + output dfi_14_out_rst_n; + output [255:0]dfi_15_dw_rddata_p0; + output [31:0]dfi_15_dw_rddata_dm_p0; + output [31:0]dfi_15_dw_rddata_dbi_p0; + output [7:0]dfi_15_dw_rddata_par_p0; + output [255:0]dfi_15_dw_rddata_p1; + output [31:0]dfi_15_dw_rddata_dm_p1; + output [31:0]dfi_15_dw_rddata_dbi_p1; + output [7:0]dfi_15_dw_rddata_par_p1; + output [15:0]dfi_15_dbi_byte_disable; + output [3:0]dfi_15_dw_rddata_valid; + output [7:0]dfi_15_dw_derr_n; + output [1:0]dfi_15_aw_aerr_n; + output dfi_15_ctrlupd_req; + output dfi_15_phyupd_ack; + output dfi_15_clk_init; + output dfi_15_init_complete; + output dfi_15_out_rst_n; + output apb_complete_0; + output apb_complete_1; + output DRAM_0_STAT_CATTRIP; + output [6:0]DRAM_0_STAT_TEMP; + output DRAM_1_STAT_CATTRIP; + output [6:0]DRAM_1_STAT_TEMP; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.vhdl new file mode 100644 index 0000000..4da8c2a --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.vhdl @@ -0,0 +1,857 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:36:26 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/hbm_0/hbm_0_stub.vhdl +-- Design : hbm_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity hbm_0 is + Port ( + HBM_REF_CLK_0 : in STD_LOGIC; + HBM_REF_CLK_1 : in STD_LOGIC; + dfi_0_clk : in STD_LOGIC; + dfi_0_rst_n : in STD_LOGIC; + dfi_0_init_start : in STD_LOGIC; + dfi_0_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_0_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_0_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_0_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_0_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_0_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_0_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_0_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_0_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_0_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_0_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_aw_ck_dis : in STD_LOGIC; + dfi_0_lp_pwr_e_req : in STD_LOGIC; + dfi_0_lp_sr_e_req : in STD_LOGIC; + dfi_0_lp_pwr_x_req : in STD_LOGIC; + dfi_0_aw_tx_indx_ld : in STD_LOGIC; + dfi_0_dw_tx_indx_ld : in STD_LOGIC; + dfi_0_dw_rx_indx_ld : in STD_LOGIC; + dfi_0_ctrlupd_ack : in STD_LOGIC; + dfi_0_phyupd_req : in STD_LOGIC; + dfi_0_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_clk : in STD_LOGIC; + dfi_1_rst_n : in STD_LOGIC; + dfi_1_init_start : in STD_LOGIC; + dfi_1_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_1_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_1_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_1_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_1_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_1_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_1_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_1_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_1_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_1_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_1_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_aw_ck_dis : in STD_LOGIC; + dfi_1_lp_pwr_e_req : in STD_LOGIC; + dfi_1_lp_sr_e_req : in STD_LOGIC; + dfi_1_lp_pwr_x_req : in STD_LOGIC; + dfi_1_aw_tx_indx_ld : in STD_LOGIC; + dfi_1_dw_tx_indx_ld : in STD_LOGIC; + dfi_1_dw_rx_indx_ld : in STD_LOGIC; + dfi_1_ctrlupd_ack : in STD_LOGIC; + dfi_1_phyupd_req : in STD_LOGIC; + dfi_1_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_clk : in STD_LOGIC; + dfi_2_rst_n : in STD_LOGIC; + dfi_2_init_start : in STD_LOGIC; + dfi_2_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_2_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_2_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_2_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_2_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_2_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_2_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_2_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_2_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_2_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_2_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_aw_ck_dis : in STD_LOGIC; + dfi_2_lp_pwr_e_req : in STD_LOGIC; + dfi_2_lp_sr_e_req : in STD_LOGIC; + dfi_2_lp_pwr_x_req : in STD_LOGIC; + dfi_2_aw_tx_indx_ld : in STD_LOGIC; + dfi_2_dw_tx_indx_ld : in STD_LOGIC; + dfi_2_dw_rx_indx_ld : in STD_LOGIC; + dfi_2_ctrlupd_ack : in STD_LOGIC; + dfi_2_phyupd_req : in STD_LOGIC; + dfi_2_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_clk : in STD_LOGIC; + dfi_3_rst_n : in STD_LOGIC; + dfi_3_init_start : in STD_LOGIC; + dfi_3_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_3_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_3_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_3_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_3_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_3_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_3_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_3_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_3_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_3_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_3_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_aw_ck_dis : in STD_LOGIC; + dfi_3_lp_pwr_e_req : in STD_LOGIC; + dfi_3_lp_sr_e_req : in STD_LOGIC; + dfi_3_lp_pwr_x_req : in STD_LOGIC; + dfi_3_aw_tx_indx_ld : in STD_LOGIC; + dfi_3_dw_tx_indx_ld : in STD_LOGIC; + dfi_3_dw_rx_indx_ld : in STD_LOGIC; + dfi_3_ctrlupd_ack : in STD_LOGIC; + dfi_3_phyupd_req : in STD_LOGIC; + dfi_3_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_clk : in STD_LOGIC; + dfi_4_rst_n : in STD_LOGIC; + dfi_4_init_start : in STD_LOGIC; + dfi_4_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_4_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_4_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_4_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_4_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_4_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_4_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_4_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_4_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_4_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_4_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_aw_ck_dis : in STD_LOGIC; + dfi_4_lp_pwr_e_req : in STD_LOGIC; + dfi_4_lp_sr_e_req : in STD_LOGIC; + dfi_4_lp_pwr_x_req : in STD_LOGIC; + dfi_4_aw_tx_indx_ld : in STD_LOGIC; + dfi_4_dw_tx_indx_ld : in STD_LOGIC; + dfi_4_dw_rx_indx_ld : in STD_LOGIC; + dfi_4_ctrlupd_ack : in STD_LOGIC; + dfi_4_phyupd_req : in STD_LOGIC; + dfi_4_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_clk : in STD_LOGIC; + dfi_5_rst_n : in STD_LOGIC; + dfi_5_init_start : in STD_LOGIC; + dfi_5_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_5_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_5_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_5_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_5_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_5_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_5_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_5_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_5_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_5_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_5_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_aw_ck_dis : in STD_LOGIC; + dfi_5_lp_pwr_e_req : in STD_LOGIC; + dfi_5_lp_sr_e_req : in STD_LOGIC; + dfi_5_lp_pwr_x_req : in STD_LOGIC; + dfi_5_aw_tx_indx_ld : in STD_LOGIC; + dfi_5_dw_tx_indx_ld : in STD_LOGIC; + dfi_5_dw_rx_indx_ld : in STD_LOGIC; + dfi_5_ctrlupd_ack : in STD_LOGIC; + dfi_5_phyupd_req : in STD_LOGIC; + dfi_5_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_clk : in STD_LOGIC; + dfi_6_rst_n : in STD_LOGIC; + dfi_6_init_start : in STD_LOGIC; + dfi_6_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_6_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_6_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_6_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_6_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_6_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_6_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_6_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_6_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_6_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_6_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_aw_ck_dis : in STD_LOGIC; + dfi_6_lp_pwr_e_req : in STD_LOGIC; + dfi_6_lp_sr_e_req : in STD_LOGIC; + dfi_6_lp_pwr_x_req : in STD_LOGIC; + dfi_6_aw_tx_indx_ld : in STD_LOGIC; + dfi_6_dw_tx_indx_ld : in STD_LOGIC; + dfi_6_dw_rx_indx_ld : in STD_LOGIC; + dfi_6_ctrlupd_ack : in STD_LOGIC; + dfi_6_phyupd_req : in STD_LOGIC; + dfi_6_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_clk : in STD_LOGIC; + dfi_7_rst_n : in STD_LOGIC; + dfi_7_init_start : in STD_LOGIC; + dfi_7_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_7_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_7_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_7_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_7_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_7_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_7_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_7_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_7_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_7_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_7_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_aw_ck_dis : in STD_LOGIC; + dfi_7_lp_pwr_e_req : in STD_LOGIC; + dfi_7_lp_sr_e_req : in STD_LOGIC; + dfi_7_lp_pwr_x_req : in STD_LOGIC; + dfi_7_aw_tx_indx_ld : in STD_LOGIC; + dfi_7_dw_tx_indx_ld : in STD_LOGIC; + dfi_7_dw_rx_indx_ld : in STD_LOGIC; + dfi_7_ctrlupd_ack : in STD_LOGIC; + dfi_7_phyupd_req : in STD_LOGIC; + dfi_7_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_clk : in STD_LOGIC; + dfi_8_rst_n : in STD_LOGIC; + dfi_8_init_start : in STD_LOGIC; + dfi_8_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_8_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_8_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_8_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_8_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_8_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_8_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_8_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_8_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_8_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_8_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_aw_ck_dis : in STD_LOGIC; + dfi_8_lp_pwr_e_req : in STD_LOGIC; + dfi_8_lp_sr_e_req : in STD_LOGIC; + dfi_8_lp_pwr_x_req : in STD_LOGIC; + dfi_8_aw_tx_indx_ld : in STD_LOGIC; + dfi_8_dw_tx_indx_ld : in STD_LOGIC; + dfi_8_dw_rx_indx_ld : in STD_LOGIC; + dfi_8_ctrlupd_ack : in STD_LOGIC; + dfi_8_phyupd_req : in STD_LOGIC; + dfi_8_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_clk : in STD_LOGIC; + dfi_9_rst_n : in STD_LOGIC; + dfi_9_init_start : in STD_LOGIC; + dfi_9_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_9_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_9_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_9_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_9_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_9_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_9_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_9_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_9_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_9_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_9_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_aw_ck_dis : in STD_LOGIC; + dfi_9_lp_pwr_e_req : in STD_LOGIC; + dfi_9_lp_sr_e_req : in STD_LOGIC; + dfi_9_lp_pwr_x_req : in STD_LOGIC; + dfi_9_aw_tx_indx_ld : in STD_LOGIC; + dfi_9_dw_tx_indx_ld : in STD_LOGIC; + dfi_9_dw_rx_indx_ld : in STD_LOGIC; + dfi_9_ctrlupd_ack : in STD_LOGIC; + dfi_9_phyupd_req : in STD_LOGIC; + dfi_9_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_clk : in STD_LOGIC; + dfi_10_rst_n : in STD_LOGIC; + dfi_10_init_start : in STD_LOGIC; + dfi_10_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_10_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_10_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_10_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_10_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_10_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_10_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_10_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_10_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_10_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_10_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_aw_ck_dis : in STD_LOGIC; + dfi_10_lp_pwr_e_req : in STD_LOGIC; + dfi_10_lp_sr_e_req : in STD_LOGIC; + dfi_10_lp_pwr_x_req : in STD_LOGIC; + dfi_10_aw_tx_indx_ld : in STD_LOGIC; + dfi_10_dw_tx_indx_ld : in STD_LOGIC; + dfi_10_dw_rx_indx_ld : in STD_LOGIC; + dfi_10_ctrlupd_ack : in STD_LOGIC; + dfi_10_phyupd_req : in STD_LOGIC; + dfi_10_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_clk : in STD_LOGIC; + dfi_11_rst_n : in STD_LOGIC; + dfi_11_init_start : in STD_LOGIC; + dfi_11_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_11_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_11_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_11_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_11_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_11_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_11_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_11_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_11_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_11_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_11_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_aw_ck_dis : in STD_LOGIC; + dfi_11_lp_pwr_e_req : in STD_LOGIC; + dfi_11_lp_sr_e_req : in STD_LOGIC; + dfi_11_lp_pwr_x_req : in STD_LOGIC; + dfi_11_aw_tx_indx_ld : in STD_LOGIC; + dfi_11_dw_tx_indx_ld : in STD_LOGIC; + dfi_11_dw_rx_indx_ld : in STD_LOGIC; + dfi_11_ctrlupd_ack : in STD_LOGIC; + dfi_11_phyupd_req : in STD_LOGIC; + dfi_11_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_clk : in STD_LOGIC; + dfi_12_rst_n : in STD_LOGIC; + dfi_12_init_start : in STD_LOGIC; + dfi_12_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_12_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_12_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_12_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_12_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_12_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_12_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_12_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_12_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_12_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_12_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_aw_ck_dis : in STD_LOGIC; + dfi_12_lp_pwr_e_req : in STD_LOGIC; + dfi_12_lp_sr_e_req : in STD_LOGIC; + dfi_12_lp_pwr_x_req : in STD_LOGIC; + dfi_12_aw_tx_indx_ld : in STD_LOGIC; + dfi_12_dw_tx_indx_ld : in STD_LOGIC; + dfi_12_dw_rx_indx_ld : in STD_LOGIC; + dfi_12_ctrlupd_ack : in STD_LOGIC; + dfi_12_phyupd_req : in STD_LOGIC; + dfi_12_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_clk : in STD_LOGIC; + dfi_13_rst_n : in STD_LOGIC; + dfi_13_init_start : in STD_LOGIC; + dfi_13_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_13_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_13_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_13_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_13_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_13_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_13_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_13_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_13_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_13_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_13_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_aw_ck_dis : in STD_LOGIC; + dfi_13_lp_pwr_e_req : in STD_LOGIC; + dfi_13_lp_sr_e_req : in STD_LOGIC; + dfi_13_lp_pwr_x_req : in STD_LOGIC; + dfi_13_aw_tx_indx_ld : in STD_LOGIC; + dfi_13_dw_tx_indx_ld : in STD_LOGIC; + dfi_13_dw_rx_indx_ld : in STD_LOGIC; + dfi_13_ctrlupd_ack : in STD_LOGIC; + dfi_13_phyupd_req : in STD_LOGIC; + dfi_13_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_clk : in STD_LOGIC; + dfi_14_rst_n : in STD_LOGIC; + dfi_14_init_start : in STD_LOGIC; + dfi_14_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_14_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_14_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_14_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_14_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_14_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_14_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_14_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_14_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_14_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_14_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_aw_ck_dis : in STD_LOGIC; + dfi_14_lp_pwr_e_req : in STD_LOGIC; + dfi_14_lp_sr_e_req : in STD_LOGIC; + dfi_14_lp_pwr_x_req : in STD_LOGIC; + dfi_14_aw_tx_indx_ld : in STD_LOGIC; + dfi_14_dw_tx_indx_ld : in STD_LOGIC; + dfi_14_dw_rx_indx_ld : in STD_LOGIC; + dfi_14_ctrlupd_ack : in STD_LOGIC; + dfi_14_phyupd_req : in STD_LOGIC; + dfi_14_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_clk : in STD_LOGIC; + dfi_15_rst_n : in STD_LOGIC; + dfi_15_init_start : in STD_LOGIC; + dfi_15_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_15_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_15_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_15_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_15_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_15_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_15_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_15_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_15_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_15_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_15_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_aw_ck_dis : in STD_LOGIC; + dfi_15_lp_pwr_e_req : in STD_LOGIC; + dfi_15_lp_sr_e_req : in STD_LOGIC; + dfi_15_lp_pwr_x_req : in STD_LOGIC; + dfi_15_aw_tx_indx_ld : in STD_LOGIC; + dfi_15_dw_tx_indx_ld : in STD_LOGIC; + dfi_15_dw_rx_indx_ld : in STD_LOGIC; + dfi_15_ctrlupd_ack : in STD_LOGIC; + dfi_15_phyupd_req : in STD_LOGIC; + dfi_15_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + APB_0_PCLK : in STD_LOGIC; + APB_0_PRESET_N : in STD_LOGIC; + APB_1_PCLK : in STD_LOGIC; + APB_1_PRESET_N : in STD_LOGIC; + dfi_0_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_0_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_0_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_0_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_0_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_0_ctrlupd_req : out STD_LOGIC; + dfi_0_phyupd_ack : out STD_LOGIC; + dfi_0_clk_init : out STD_LOGIC; + dfi_0_init_complete : out STD_LOGIC; + dfi_0_out_rst_n : out STD_LOGIC; + dfi_1_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_1_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_1_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_1_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_1_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_1_ctrlupd_req : out STD_LOGIC; + dfi_1_phyupd_ack : out STD_LOGIC; + dfi_1_clk_init : out STD_LOGIC; + dfi_1_init_complete : out STD_LOGIC; + dfi_1_out_rst_n : out STD_LOGIC; + dfi_2_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_2_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_2_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_2_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_2_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_2_ctrlupd_req : out STD_LOGIC; + dfi_2_phyupd_ack : out STD_LOGIC; + dfi_2_clk_init : out STD_LOGIC; + dfi_2_init_complete : out STD_LOGIC; + dfi_2_out_rst_n : out STD_LOGIC; + dfi_3_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_3_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_3_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_3_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_3_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_3_ctrlupd_req : out STD_LOGIC; + dfi_3_phyupd_ack : out STD_LOGIC; + dfi_3_clk_init : out STD_LOGIC; + dfi_3_init_complete : out STD_LOGIC; + dfi_3_out_rst_n : out STD_LOGIC; + dfi_4_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_4_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_4_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_4_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_4_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_4_ctrlupd_req : out STD_LOGIC; + dfi_4_phyupd_ack : out STD_LOGIC; + dfi_4_clk_init : out STD_LOGIC; + dfi_4_init_complete : out STD_LOGIC; + dfi_4_out_rst_n : out STD_LOGIC; + dfi_5_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_5_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_5_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_5_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_5_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_5_ctrlupd_req : out STD_LOGIC; + dfi_5_phyupd_ack : out STD_LOGIC; + dfi_5_clk_init : out STD_LOGIC; + dfi_5_init_complete : out STD_LOGIC; + dfi_5_out_rst_n : out STD_LOGIC; + dfi_6_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_6_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_6_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_6_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_6_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_6_ctrlupd_req : out STD_LOGIC; + dfi_6_phyupd_ack : out STD_LOGIC; + dfi_6_clk_init : out STD_LOGIC; + dfi_6_init_complete : out STD_LOGIC; + dfi_6_out_rst_n : out STD_LOGIC; + dfi_7_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_7_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_7_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_7_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_7_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_7_ctrlupd_req : out STD_LOGIC; + dfi_7_phyupd_ack : out STD_LOGIC; + dfi_7_clk_init : out STD_LOGIC; + dfi_7_init_complete : out STD_LOGIC; + dfi_7_out_rst_n : out STD_LOGIC; + dfi_8_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_8_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_8_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_8_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_8_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_8_ctrlupd_req : out STD_LOGIC; + dfi_8_phyupd_ack : out STD_LOGIC; + dfi_8_clk_init : out STD_LOGIC; + dfi_8_init_complete : out STD_LOGIC; + dfi_8_out_rst_n : out STD_LOGIC; + dfi_9_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_9_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_9_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_9_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_9_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_9_ctrlupd_req : out STD_LOGIC; + dfi_9_phyupd_ack : out STD_LOGIC; + dfi_9_clk_init : out STD_LOGIC; + dfi_9_init_complete : out STD_LOGIC; + dfi_9_out_rst_n : out STD_LOGIC; + dfi_10_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_10_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_10_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_10_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_10_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_10_ctrlupd_req : out STD_LOGIC; + dfi_10_phyupd_ack : out STD_LOGIC; + dfi_10_clk_init : out STD_LOGIC; + dfi_10_init_complete : out STD_LOGIC; + dfi_10_out_rst_n : out STD_LOGIC; + dfi_11_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_11_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_11_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_11_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_11_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_11_ctrlupd_req : out STD_LOGIC; + dfi_11_phyupd_ack : out STD_LOGIC; + dfi_11_clk_init : out STD_LOGIC; + dfi_11_init_complete : out STD_LOGIC; + dfi_11_out_rst_n : out STD_LOGIC; + dfi_12_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_12_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_12_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_12_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_12_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_12_ctrlupd_req : out STD_LOGIC; + dfi_12_phyupd_ack : out STD_LOGIC; + dfi_12_clk_init : out STD_LOGIC; + dfi_12_init_complete : out STD_LOGIC; + dfi_12_out_rst_n : out STD_LOGIC; + dfi_13_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_13_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_13_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_13_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_13_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_13_ctrlupd_req : out STD_LOGIC; + dfi_13_phyupd_ack : out STD_LOGIC; + dfi_13_clk_init : out STD_LOGIC; + dfi_13_init_complete : out STD_LOGIC; + dfi_13_out_rst_n : out STD_LOGIC; + dfi_14_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_14_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_14_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_14_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_14_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_14_ctrlupd_req : out STD_LOGIC; + dfi_14_phyupd_ack : out STD_LOGIC; + dfi_14_clk_init : out STD_LOGIC; + dfi_14_init_complete : out STD_LOGIC; + dfi_14_out_rst_n : out STD_LOGIC; + dfi_15_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_15_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_15_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_15_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_15_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_15_ctrlupd_req : out STD_LOGIC; + dfi_15_phyupd_ack : out STD_LOGIC; + dfi_15_clk_init : out STD_LOGIC; + dfi_15_init_complete : out STD_LOGIC; + dfi_15_out_rst_n : out STD_LOGIC; + apb_complete_0 : out STD_LOGIC; + apb_complete_1 : out STD_LOGIC; + DRAM_0_STAT_CATTRIP : out STD_LOGIC; + DRAM_0_STAT_TEMP : out STD_LOGIC_VECTOR ( 6 downto 0 ); + DRAM_1_STAT_CATTRIP : out STD_LOGIC; + DRAM_1_STAT_TEMP : out STD_LOGIC_VECTOR ( 6 downto 0 ) + ); + +end hbm_0; + +architecture stub of hbm_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "HBM_REF_CLK_0,HBM_REF_CLK_1,dfi_0_clk,dfi_0_rst_n,dfi_0_init_start,dfi_0_aw_ck_p0[1:0],dfi_0_aw_cke_p0[1:0],dfi_0_aw_row_p0[11:0],dfi_0_aw_col_p0[15:0],dfi_0_dw_wrdata_p0[255:0],dfi_0_dw_wrdata_mask_p0[31:0],dfi_0_dw_wrdata_dbi_p0[31:0],dfi_0_dw_wrdata_par_p0[7:0],dfi_0_dw_wrdata_dq_en_p0[7:0],dfi_0_dw_wrdata_par_en_p0[7:0],dfi_0_aw_ck_p1[1:0],dfi_0_aw_cke_p1[1:0],dfi_0_aw_row_p1[11:0],dfi_0_aw_col_p1[15:0],dfi_0_dw_wrdata_p1[255:0],dfi_0_dw_wrdata_mask_p1[31:0],dfi_0_dw_wrdata_dbi_p1[31:0],dfi_0_dw_wrdata_par_p1[7:0],dfi_0_dw_wrdata_dq_en_p1[7:0],dfi_0_dw_wrdata_par_en_p1[7:0],dfi_0_aw_ck_dis,dfi_0_lp_pwr_e_req,dfi_0_lp_sr_e_req,dfi_0_lp_pwr_x_req,dfi_0_aw_tx_indx_ld,dfi_0_dw_tx_indx_ld,dfi_0_dw_rx_indx_ld,dfi_0_ctrlupd_ack,dfi_0_phyupd_req,dfi_0_dw_wrdata_dqs_p0[7:0],dfi_0_dw_wrdata_dqs_p1[7:0],dfi_1_clk,dfi_1_rst_n,dfi_1_init_start,dfi_1_aw_ck_p0[1:0],dfi_1_aw_cke_p0[1:0],dfi_1_aw_row_p0[11:0],dfi_1_aw_col_p0[15:0],dfi_1_dw_wrdata_p0[255:0],dfi_1_dw_wrdata_mask_p0[31:0],dfi_1_dw_wrdata_dbi_p0[31:0],dfi_1_dw_wrdata_par_p0[7:0],dfi_1_dw_wrdata_dq_en_p0[7:0],dfi_1_dw_wrdata_par_en_p0[7:0],dfi_1_aw_ck_p1[1:0],dfi_1_aw_cke_p1[1:0],dfi_1_aw_row_p1[11:0],dfi_1_aw_col_p1[15:0],dfi_1_dw_wrdata_p1[255:0],dfi_1_dw_wrdata_mask_p1[31:0],dfi_1_dw_wrdata_dbi_p1[31:0],dfi_1_dw_wrdata_par_p1[7:0],dfi_1_dw_wrdata_dq_en_p1[7:0],dfi_1_dw_wrdata_par_en_p1[7:0],dfi_1_aw_ck_dis,dfi_1_lp_pwr_e_req,dfi_1_lp_sr_e_req,dfi_1_lp_pwr_x_req,dfi_1_aw_tx_indx_ld,dfi_1_dw_tx_indx_ld,dfi_1_dw_rx_indx_ld,dfi_1_ctrlupd_ack,dfi_1_phyupd_req,dfi_1_dw_wrdata_dqs_p0[7:0],dfi_1_dw_wrdata_dqs_p1[7:0],dfi_2_clk,dfi_2_rst_n,dfi_2_init_start,dfi_2_aw_ck_p0[1:0],dfi_2_aw_cke_p0[1:0],dfi_2_aw_row_p0[11:0],dfi_2_aw_col_p0[15:0],dfi_2_dw_wrdata_p0[255:0],dfi_2_dw_wrdata_mask_p0[31:0],dfi_2_dw_wrdata_dbi_p0[31:0],dfi_2_dw_wrdata_par_p0[7:0],dfi_2_dw_wrdata_dq_en_p0[7:0],dfi_2_dw_wrdata_par_en_p0[7:0],dfi_2_aw_ck_p1[1:0],dfi_2_aw_cke_p1[1:0],dfi_2_aw_row_p1[11:0],dfi_2_aw_col_p1[15:0],dfi_2_dw_wrdata_p1[255:0],dfi_2_dw_wrdata_mask_p1[31:0],dfi_2_dw_wrdata_dbi_p1[31:0],dfi_2_dw_wrdata_par_p1[7:0],dfi_2_dw_wrdata_dq_en_p1[7:0],dfi_2_dw_wrdata_par_en_p1[7:0],dfi_2_aw_ck_dis,dfi_2_lp_pwr_e_req,dfi_2_lp_sr_e_req,dfi_2_lp_pwr_x_req,dfi_2_aw_tx_indx_ld,dfi_2_dw_tx_indx_ld,dfi_2_dw_rx_indx_ld,dfi_2_ctrlupd_ack,dfi_2_phyupd_req,dfi_2_dw_wrdata_dqs_p0[7:0],dfi_2_dw_wrdata_dqs_p1[7:0],dfi_3_clk,dfi_3_rst_n,dfi_3_init_start,dfi_3_aw_ck_p0[1:0],dfi_3_aw_cke_p0[1:0],dfi_3_aw_row_p0[11:0],dfi_3_aw_col_p0[15:0],dfi_3_dw_wrdata_p0[255:0],dfi_3_dw_wrdata_mask_p0[31:0],dfi_3_dw_wrdata_dbi_p0[31:0],dfi_3_dw_wrdata_par_p0[7:0],dfi_3_dw_wrdata_dq_en_p0[7:0],dfi_3_dw_wrdata_par_en_p0[7:0],dfi_3_aw_ck_p1[1:0],dfi_3_aw_cke_p1[1:0],dfi_3_aw_row_p1[11:0],dfi_3_aw_col_p1[15:0],dfi_3_dw_wrdata_p1[255:0],dfi_3_dw_wrdata_mask_p1[31:0],dfi_3_dw_wrdata_dbi_p1[31:0],dfi_3_dw_wrdata_par_p1[7:0],dfi_3_dw_wrdata_dq_en_p1[7:0],dfi_3_dw_wrdata_par_en_p1[7:0],dfi_3_aw_ck_dis,dfi_3_lp_pwr_e_req,dfi_3_lp_sr_e_req,dfi_3_lp_pwr_x_req,dfi_3_aw_tx_indx_ld,dfi_3_dw_tx_indx_ld,dfi_3_dw_rx_indx_ld,dfi_3_ctrlupd_ack,dfi_3_phyupd_req,dfi_3_dw_wrdata_dqs_p0[7:0],dfi_3_dw_wrdata_dqs_p1[7:0],dfi_4_clk,dfi_4_rst_n,dfi_4_init_start,dfi_4_aw_ck_p0[1:0],dfi_4_aw_cke_p0[1:0],dfi_4_aw_row_p0[11:0],dfi_4_aw_col_p0[15:0],dfi_4_dw_wrdata_p0[255:0],dfi_4_dw_wrdata_mask_p0[31:0],dfi_4_dw_wrdata_dbi_p0[31:0],dfi_4_dw_wrdata_par_p0[7:0],dfi_4_dw_wrdata_dq_en_p0[7:0],dfi_4_dw_wrdata_par_en_p0[7:0],dfi_4_aw_ck_p1[1:0],dfi_4_aw_cke_p1[1:0],dfi_4_aw_row_p1[11:0],dfi_4_aw_col_p1[15:0],dfi_4_dw_wrdata_p1[255:0],dfi_4_dw_wrdata_mask_p1[31:0],dfi_4_dw_wrdata_dbi_p1[31:0],dfi_4_dw_wrdata_par_p1[7:0],dfi_4_dw_wrdata_dq_en_p1[7:0],dfi_4_dw_wrdata_par_en_p1[7:0],dfi_4_aw_ck_dis,dfi_4_lp_pwr_e_req,dfi_4_lp_sr_e_req,dfi_4_lp_pwr_x_req,dfi_4_aw_tx_indx_ld,dfi_4_dw_tx_indx_ld,dfi_4_dw_rx_indx_ld,dfi_4_ctrlupd_ack,dfi_4_phyupd_req,dfi_4_dw_wrdata_dqs_p0[7:0],dfi_4_dw_wrdata_dqs_p1[7:0],dfi_5_clk,dfi_5_rst_n,dfi_5_init_start,dfi_5_aw_ck_p0[1:0],dfi_5_aw_cke_p0[1:0],dfi_5_aw_row_p0[11:0],dfi_5_aw_col_p0[15:0],dfi_5_dw_wrdata_p0[255:0],dfi_5_dw_wrdata_mask_p0[31:0],dfi_5_dw_wrdata_dbi_p0[31:0],dfi_5_dw_wrdata_par_p0[7:0],dfi_5_dw_wrdata_dq_en_p0[7:0],dfi_5_dw_wrdata_par_en_p0[7:0],dfi_5_aw_ck_p1[1:0],dfi_5_aw_cke_p1[1:0],dfi_5_aw_row_p1[11:0],dfi_5_aw_col_p1[15:0],dfi_5_dw_wrdata_p1[255:0],dfi_5_dw_wrdata_mask_p1[31:0],dfi_5_dw_wrdata_dbi_p1[31:0],dfi_5_dw_wrdata_par_p1[7:0],dfi_5_dw_wrdata_dq_en_p1[7:0],dfi_5_dw_wrdata_par_en_p1[7:0],dfi_5_aw_ck_dis,dfi_5_lp_pwr_e_req,dfi_5_lp_sr_e_req,dfi_5_lp_pwr_x_req,dfi_5_aw_tx_indx_ld,dfi_5_dw_tx_indx_ld,dfi_5_dw_rx_indx_ld,dfi_5_ctrlupd_ack,dfi_5_phyupd_req,dfi_5_dw_wrdata_dqs_p0[7:0],dfi_5_dw_wrdata_dqs_p1[7:0],dfi_6_clk,dfi_6_rst_n,dfi_6_init_start,dfi_6_aw_ck_p0[1:0],dfi_6_aw_cke_p0[1:0],dfi_6_aw_row_p0[11:0],dfi_6_aw_col_p0[15:0],dfi_6_dw_wrdata_p0[255:0],dfi_6_dw_wrdata_mask_p0[31:0],dfi_6_dw_wrdata_dbi_p0[31:0],dfi_6_dw_wrdata_par_p0[7:0],dfi_6_dw_wrdata_dq_en_p0[7:0],dfi_6_dw_wrdata_par_en_p0[7:0],dfi_6_aw_ck_p1[1:0],dfi_6_aw_cke_p1[1:0],dfi_6_aw_row_p1[11:0],dfi_6_aw_col_p1[15:0],dfi_6_dw_wrdata_p1[255:0],dfi_6_dw_wrdata_mask_p1[31:0],dfi_6_dw_wrdata_dbi_p1[31:0],dfi_6_dw_wrdata_par_p1[7:0],dfi_6_dw_wrdata_dq_en_p1[7:0],dfi_6_dw_wrdata_par_en_p1[7:0],dfi_6_aw_ck_dis,dfi_6_lp_pwr_e_req,dfi_6_lp_sr_e_req,dfi_6_lp_pwr_x_req,dfi_6_aw_tx_indx_ld,dfi_6_dw_tx_indx_ld,dfi_6_dw_rx_indx_ld,dfi_6_ctrlupd_ack,dfi_6_phyupd_req,dfi_6_dw_wrdata_dqs_p0[7:0],dfi_6_dw_wrdata_dqs_p1[7:0],dfi_7_clk,dfi_7_rst_n,dfi_7_init_start,dfi_7_aw_ck_p0[1:0],dfi_7_aw_cke_p0[1:0],dfi_7_aw_row_p0[11:0],dfi_7_aw_col_p0[15:0],dfi_7_dw_wrdata_p0[255:0],dfi_7_dw_wrdata_mask_p0[31:0],dfi_7_dw_wrdata_dbi_p0[31:0],dfi_7_dw_wrdata_par_p0[7:0],dfi_7_dw_wrdata_dq_en_p0[7:0],dfi_7_dw_wrdata_par_en_p0[7:0],dfi_7_aw_ck_p1[1:0],dfi_7_aw_cke_p1[1:0],dfi_7_aw_row_p1[11:0],dfi_7_aw_col_p1[15:0],dfi_7_dw_wrdata_p1[255:0],dfi_7_dw_wrdata_mask_p1[31:0],dfi_7_dw_wrdata_dbi_p1[31:0],dfi_7_dw_wrdata_par_p1[7:0],dfi_7_dw_wrdata_dq_en_p1[7:0],dfi_7_dw_wrdata_par_en_p1[7:0],dfi_7_aw_ck_dis,dfi_7_lp_pwr_e_req,dfi_7_lp_sr_e_req,dfi_7_lp_pwr_x_req,dfi_7_aw_tx_indx_ld,dfi_7_dw_tx_indx_ld,dfi_7_dw_rx_indx_ld,dfi_7_ctrlupd_ack,dfi_7_phyupd_req,dfi_7_dw_wrdata_dqs_p0[7:0],dfi_7_dw_wrdata_dqs_p1[7:0],dfi_8_clk,dfi_8_rst_n,dfi_8_init_start,dfi_8_aw_ck_p0[1:0],dfi_8_aw_cke_p0[1:0],dfi_8_aw_row_p0[11:0],dfi_8_aw_col_p0[15:0],dfi_8_dw_wrdata_p0[255:0],dfi_8_dw_wrdata_mask_p0[31:0],dfi_8_dw_wrdata_dbi_p0[31:0],dfi_8_dw_wrdata_par_p0[7:0],dfi_8_dw_wrdata_dq_en_p0[7:0],dfi_8_dw_wrdata_par_en_p0[7:0],dfi_8_aw_ck_p1[1:0],dfi_8_aw_cke_p1[1:0],dfi_8_aw_row_p1[11:0],dfi_8_aw_col_p1[15:0],dfi_8_dw_wrdata_p1[255:0],dfi_8_dw_wrdata_mask_p1[31:0],dfi_8_dw_wrdata_dbi_p1[31:0],dfi_8_dw_wrdata_par_p1[7:0],dfi_8_dw_wrdata_dq_en_p1[7:0],dfi_8_dw_wrdata_par_en_p1[7:0],dfi_8_aw_ck_dis,dfi_8_lp_pwr_e_req,dfi_8_lp_sr_e_req,dfi_8_lp_pwr_x_req,dfi_8_aw_tx_indx_ld,dfi_8_dw_tx_indx_ld,dfi_8_dw_rx_indx_ld,dfi_8_ctrlupd_ack,dfi_8_phyupd_req,dfi_8_dw_wrdata_dqs_p0[7:0],dfi_8_dw_wrdata_dqs_p1[7:0],dfi_9_clk,dfi_9_rst_n,dfi_9_init_start,dfi_9_aw_ck_p0[1:0],dfi_9_aw_cke_p0[1:0],dfi_9_aw_row_p0[11:0],dfi_9_aw_col_p0[15:0],dfi_9_dw_wrdata_p0[255:0],dfi_9_dw_wrdata_mask_p0[31:0],dfi_9_dw_wrdata_dbi_p0[31:0],dfi_9_dw_wrdata_par_p0[7:0],dfi_9_dw_wrdata_dq_en_p0[7:0],dfi_9_dw_wrdata_par_en_p0[7:0],dfi_9_aw_ck_p1[1:0],dfi_9_aw_cke_p1[1:0],dfi_9_aw_row_p1[11:0],dfi_9_aw_col_p1[15:0],dfi_9_dw_wrdata_p1[255:0],dfi_9_dw_wrdata_mask_p1[31:0],dfi_9_dw_wrdata_dbi_p1[31:0],dfi_9_dw_wrdata_par_p1[7:0],dfi_9_dw_wrdata_dq_en_p1[7:0],dfi_9_dw_wrdata_par_en_p1[7:0],dfi_9_aw_ck_dis,dfi_9_lp_pwr_e_req,dfi_9_lp_sr_e_req,dfi_9_lp_pwr_x_req,dfi_9_aw_tx_indx_ld,dfi_9_dw_tx_indx_ld,dfi_9_dw_rx_indx_ld,dfi_9_ctrlupd_ack,dfi_9_phyupd_req,dfi_9_dw_wrdata_dqs_p0[7:0],dfi_9_dw_wrdata_dqs_p1[7:0],dfi_10_clk,dfi_10_rst_n,dfi_10_init_start,dfi_10_aw_ck_p0[1:0],dfi_10_aw_cke_p0[1:0],dfi_10_aw_row_p0[11:0],dfi_10_aw_col_p0[15:0],dfi_10_dw_wrdata_p0[255:0],dfi_10_dw_wrdata_mask_p0[31:0],dfi_10_dw_wrdata_dbi_p0[31:0],dfi_10_dw_wrdata_par_p0[7:0],dfi_10_dw_wrdata_dq_en_p0[7:0],dfi_10_dw_wrdata_par_en_p0[7:0],dfi_10_aw_ck_p1[1:0],dfi_10_aw_cke_p1[1:0],dfi_10_aw_row_p1[11:0],dfi_10_aw_col_p1[15:0],dfi_10_dw_wrdata_p1[255:0],dfi_10_dw_wrdata_mask_p1[31:0],dfi_10_dw_wrdata_dbi_p1[31:0],dfi_10_dw_wrdata_par_p1[7:0],dfi_10_dw_wrdata_dq_en_p1[7:0],dfi_10_dw_wrdata_par_en_p1[7:0],dfi_10_aw_ck_dis,dfi_10_lp_pwr_e_req,dfi_10_lp_sr_e_req,dfi_10_lp_pwr_x_req,dfi_10_aw_tx_indx_ld,dfi_10_dw_tx_indx_ld,dfi_10_dw_rx_indx_ld,dfi_10_ctrlupd_ack,dfi_10_phyupd_req,dfi_10_dw_wrdata_dqs_p0[7:0],dfi_10_dw_wrdata_dqs_p1[7:0],dfi_11_clk,dfi_11_rst_n,dfi_11_init_start,dfi_11_aw_ck_p0[1:0],dfi_11_aw_cke_p0[1:0],dfi_11_aw_row_p0[11:0],dfi_11_aw_col_p0[15:0],dfi_11_dw_wrdata_p0[255:0],dfi_11_dw_wrdata_mask_p0[31:0],dfi_11_dw_wrdata_dbi_p0[31:0],dfi_11_dw_wrdata_par_p0[7:0],dfi_11_dw_wrdata_dq_en_p0[7:0],dfi_11_dw_wrdata_par_en_p0[7:0],dfi_11_aw_ck_p1[1:0],dfi_11_aw_cke_p1[1:0],dfi_11_aw_row_p1[11:0],dfi_11_aw_col_p1[15:0],dfi_11_dw_wrdata_p1[255:0],dfi_11_dw_wrdata_mask_p1[31:0],dfi_11_dw_wrdata_dbi_p1[31:0],dfi_11_dw_wrdata_par_p1[7:0],dfi_11_dw_wrdata_dq_en_p1[7:0],dfi_11_dw_wrdata_par_en_p1[7:0],dfi_11_aw_ck_dis,dfi_11_lp_pwr_e_req,dfi_11_lp_sr_e_req,dfi_11_lp_pwr_x_req,dfi_11_aw_tx_indx_ld,dfi_11_dw_tx_indx_ld,dfi_11_dw_rx_indx_ld,dfi_11_ctrlupd_ack,dfi_11_phyupd_req,dfi_11_dw_wrdata_dqs_p0[7:0],dfi_11_dw_wrdata_dqs_p1[7:0],dfi_12_clk,dfi_12_rst_n,dfi_12_init_start,dfi_12_aw_ck_p0[1:0],dfi_12_aw_cke_p0[1:0],dfi_12_aw_row_p0[11:0],dfi_12_aw_col_p0[15:0],dfi_12_dw_wrdata_p0[255:0],dfi_12_dw_wrdata_mask_p0[31:0],dfi_12_dw_wrdata_dbi_p0[31:0],dfi_12_dw_wrdata_par_p0[7:0],dfi_12_dw_wrdata_dq_en_p0[7:0],dfi_12_dw_wrdata_par_en_p0[7:0],dfi_12_aw_ck_p1[1:0],dfi_12_aw_cke_p1[1:0],dfi_12_aw_row_p1[11:0],dfi_12_aw_col_p1[15:0],dfi_12_dw_wrdata_p1[255:0],dfi_12_dw_wrdata_mask_p1[31:0],dfi_12_dw_wrdata_dbi_p1[31:0],dfi_12_dw_wrdata_par_p1[7:0],dfi_12_dw_wrdata_dq_en_p1[7:0],dfi_12_dw_wrdata_par_en_p1[7:0],dfi_12_aw_ck_dis,dfi_12_lp_pwr_e_req,dfi_12_lp_sr_e_req,dfi_12_lp_pwr_x_req,dfi_12_aw_tx_indx_ld,dfi_12_dw_tx_indx_ld,dfi_12_dw_rx_indx_ld,dfi_12_ctrlupd_ack,dfi_12_phyupd_req,dfi_12_dw_wrdata_dqs_p0[7:0],dfi_12_dw_wrdata_dqs_p1[7:0],dfi_13_clk,dfi_13_rst_n,dfi_13_init_start,dfi_13_aw_ck_p0[1:0],dfi_13_aw_cke_p0[1:0],dfi_13_aw_row_p0[11:0],dfi_13_aw_col_p0[15:0],dfi_13_dw_wrdata_p0[255:0],dfi_13_dw_wrdata_mask_p0[31:0],dfi_13_dw_wrdata_dbi_p0[31:0],dfi_13_dw_wrdata_par_p0[7:0],dfi_13_dw_wrdata_dq_en_p0[7:0],dfi_13_dw_wrdata_par_en_p0[7:0],dfi_13_aw_ck_p1[1:0],dfi_13_aw_cke_p1[1:0],dfi_13_aw_row_p1[11:0],dfi_13_aw_col_p1[15:0],dfi_13_dw_wrdata_p1[255:0],dfi_13_dw_wrdata_mask_p1[31:0],dfi_13_dw_wrdata_dbi_p1[31:0],dfi_13_dw_wrdata_par_p1[7:0],dfi_13_dw_wrdata_dq_en_p1[7:0],dfi_13_dw_wrdata_par_en_p1[7:0],dfi_13_aw_ck_dis,dfi_13_lp_pwr_e_req,dfi_13_lp_sr_e_req,dfi_13_lp_pwr_x_req,dfi_13_aw_tx_indx_ld,dfi_13_dw_tx_indx_ld,dfi_13_dw_rx_indx_ld,dfi_13_ctrlupd_ack,dfi_13_phyupd_req,dfi_13_dw_wrdata_dqs_p0[7:0],dfi_13_dw_wrdata_dqs_p1[7:0],dfi_14_clk,dfi_14_rst_n,dfi_14_init_start,dfi_14_aw_ck_p0[1:0],dfi_14_aw_cke_p0[1:0],dfi_14_aw_row_p0[11:0],dfi_14_aw_col_p0[15:0],dfi_14_dw_wrdata_p0[255:0],dfi_14_dw_wrdata_mask_p0[31:0],dfi_14_dw_wrdata_dbi_p0[31:0],dfi_14_dw_wrdata_par_p0[7:0],dfi_14_dw_wrdata_dq_en_p0[7:0],dfi_14_dw_wrdata_par_en_p0[7:0],dfi_14_aw_ck_p1[1:0],dfi_14_aw_cke_p1[1:0],dfi_14_aw_row_p1[11:0],dfi_14_aw_col_p1[15:0],dfi_14_dw_wrdata_p1[255:0],dfi_14_dw_wrdata_mask_p1[31:0],dfi_14_dw_wrdata_dbi_p1[31:0],dfi_14_dw_wrdata_par_p1[7:0],dfi_14_dw_wrdata_dq_en_p1[7:0],dfi_14_dw_wrdata_par_en_p1[7:0],dfi_14_aw_ck_dis,dfi_14_lp_pwr_e_req,dfi_14_lp_sr_e_req,dfi_14_lp_pwr_x_req,dfi_14_aw_tx_indx_ld,dfi_14_dw_tx_indx_ld,dfi_14_dw_rx_indx_ld,dfi_14_ctrlupd_ack,dfi_14_phyupd_req,dfi_14_dw_wrdata_dqs_p0[7:0],dfi_14_dw_wrdata_dqs_p1[7:0],dfi_15_clk,dfi_15_rst_n,dfi_15_init_start,dfi_15_aw_ck_p0[1:0],dfi_15_aw_cke_p0[1:0],dfi_15_aw_row_p0[11:0],dfi_15_aw_col_p0[15:0],dfi_15_dw_wrdata_p0[255:0],dfi_15_dw_wrdata_mask_p0[31:0],dfi_15_dw_wrdata_dbi_p0[31:0],dfi_15_dw_wrdata_par_p0[7:0],dfi_15_dw_wrdata_dq_en_p0[7:0],dfi_15_dw_wrdata_par_en_p0[7:0],dfi_15_aw_ck_p1[1:0],dfi_15_aw_cke_p1[1:0],dfi_15_aw_row_p1[11:0],dfi_15_aw_col_p1[15:0],dfi_15_dw_wrdata_p1[255:0],dfi_15_dw_wrdata_mask_p1[31:0],dfi_15_dw_wrdata_dbi_p1[31:0],dfi_15_dw_wrdata_par_p1[7:0],dfi_15_dw_wrdata_dq_en_p1[7:0],dfi_15_dw_wrdata_par_en_p1[7:0],dfi_15_aw_ck_dis,dfi_15_lp_pwr_e_req,dfi_15_lp_sr_e_req,dfi_15_lp_pwr_x_req,dfi_15_aw_tx_indx_ld,dfi_15_dw_tx_indx_ld,dfi_15_dw_rx_indx_ld,dfi_15_ctrlupd_ack,dfi_15_phyupd_req,dfi_15_dw_wrdata_dqs_p0[7:0],dfi_15_dw_wrdata_dqs_p1[7:0],APB_0_PCLK,APB_0_PRESET_N,APB_1_PCLK,APB_1_PRESET_N,dfi_0_dw_rddata_p0[255:0],dfi_0_dw_rddata_dm_p0[31:0],dfi_0_dw_rddata_dbi_p0[31:0],dfi_0_dw_rddata_par_p0[7:0],dfi_0_dw_rddata_p1[255:0],dfi_0_dw_rddata_dm_p1[31:0],dfi_0_dw_rddata_dbi_p1[31:0],dfi_0_dw_rddata_par_p1[7:0],dfi_0_dbi_byte_disable[15:0],dfi_0_dw_rddata_valid[3:0],dfi_0_dw_derr_n[7:0],dfi_0_aw_aerr_n[1:0],dfi_0_ctrlupd_req,dfi_0_phyupd_ack,dfi_0_clk_init,dfi_0_init_complete,dfi_0_out_rst_n,dfi_1_dw_rddata_p0[255:0],dfi_1_dw_rddata_dm_p0[31:0],dfi_1_dw_rddata_dbi_p0[31:0],dfi_1_dw_rddata_par_p0[7:0],dfi_1_dw_rddata_p1[255:0],dfi_1_dw_rddata_dm_p1[31:0],dfi_1_dw_rddata_dbi_p1[31:0],dfi_1_dw_rddata_par_p1[7:0],dfi_1_dbi_byte_disable[15:0],dfi_1_dw_rddata_valid[3:0],dfi_1_dw_derr_n[7:0],dfi_1_aw_aerr_n[1:0],dfi_1_ctrlupd_req,dfi_1_phyupd_ack,dfi_1_clk_init,dfi_1_init_complete,dfi_1_out_rst_n,dfi_2_dw_rddata_p0[255:0],dfi_2_dw_rddata_dm_p0[31:0],dfi_2_dw_rddata_dbi_p0[31:0],dfi_2_dw_rddata_par_p0[7:0],dfi_2_dw_rddata_p1[255:0],dfi_2_dw_rddata_dm_p1[31:0],dfi_2_dw_rddata_dbi_p1[31:0],dfi_2_dw_rddata_par_p1[7:0],dfi_2_dbi_byte_disable[15:0],dfi_2_dw_rddata_valid[3:0],dfi_2_dw_derr_n[7:0],dfi_2_aw_aerr_n[1:0],dfi_2_ctrlupd_req,dfi_2_phyupd_ack,dfi_2_clk_init,dfi_2_init_complete,dfi_2_out_rst_n,dfi_3_dw_rddata_p0[255:0],dfi_3_dw_rddata_dm_p0[31:0],dfi_3_dw_rddata_dbi_p0[31:0],dfi_3_dw_rddata_par_p0[7:0],dfi_3_dw_rddata_p1[255:0],dfi_3_dw_rddata_dm_p1[31:0],dfi_3_dw_rddata_dbi_p1[31:0],dfi_3_dw_rddata_par_p1[7:0],dfi_3_dbi_byte_disable[15:0],dfi_3_dw_rddata_valid[3:0],dfi_3_dw_derr_n[7:0],dfi_3_aw_aerr_n[1:0],dfi_3_ctrlupd_req,dfi_3_phyupd_ack,dfi_3_clk_init,dfi_3_init_complete,dfi_3_out_rst_n,dfi_4_dw_rddata_p0[255:0],dfi_4_dw_rddata_dm_p0[31:0],dfi_4_dw_rddata_dbi_p0[31:0],dfi_4_dw_rddata_par_p0[7:0],dfi_4_dw_rddata_p1[255:0],dfi_4_dw_rddata_dm_p1[31:0],dfi_4_dw_rddata_dbi_p1[31:0],dfi_4_dw_rddata_par_p1[7:0],dfi_4_dbi_byte_disable[15:0],dfi_4_dw_rddata_valid[3:0],dfi_4_dw_derr_n[7:0],dfi_4_aw_aerr_n[1:0],dfi_4_ctrlupd_req,dfi_4_phyupd_ack,dfi_4_clk_init,dfi_4_init_complete,dfi_4_out_rst_n,dfi_5_dw_rddata_p0[255:0],dfi_5_dw_rddata_dm_p0[31:0],dfi_5_dw_rddata_dbi_p0[31:0],dfi_5_dw_rddata_par_p0[7:0],dfi_5_dw_rddata_p1[255:0],dfi_5_dw_rddata_dm_p1[31:0],dfi_5_dw_rddata_dbi_p1[31:0],dfi_5_dw_rddata_par_p1[7:0],dfi_5_dbi_byte_disable[15:0],dfi_5_dw_rddata_valid[3:0],dfi_5_dw_derr_n[7:0],dfi_5_aw_aerr_n[1:0],dfi_5_ctrlupd_req,dfi_5_phyupd_ack,dfi_5_clk_init,dfi_5_init_complete,dfi_5_out_rst_n,dfi_6_dw_rddata_p0[255:0],dfi_6_dw_rddata_dm_p0[31:0],dfi_6_dw_rddata_dbi_p0[31:0],dfi_6_dw_rddata_par_p0[7:0],dfi_6_dw_rddata_p1[255:0],dfi_6_dw_rddata_dm_p1[31:0],dfi_6_dw_rddata_dbi_p1[31:0],dfi_6_dw_rddata_par_p1[7:0],dfi_6_dbi_byte_disable[15:0],dfi_6_dw_rddata_valid[3:0],dfi_6_dw_derr_n[7:0],dfi_6_aw_aerr_n[1:0],dfi_6_ctrlupd_req,dfi_6_phyupd_ack,dfi_6_clk_init,dfi_6_init_complete,dfi_6_out_rst_n,dfi_7_dw_rddata_p0[255:0],dfi_7_dw_rddata_dm_p0[31:0],dfi_7_dw_rddata_dbi_p0[31:0],dfi_7_dw_rddata_par_p0[7:0],dfi_7_dw_rddata_p1[255:0],dfi_7_dw_rddata_dm_p1[31:0],dfi_7_dw_rddata_dbi_p1[31:0],dfi_7_dw_rddata_par_p1[7:0],dfi_7_dbi_byte_disable[15:0],dfi_7_dw_rddata_valid[3:0],dfi_7_dw_derr_n[7:0],dfi_7_aw_aerr_n[1:0],dfi_7_ctrlupd_req,dfi_7_phyupd_ack,dfi_7_clk_init,dfi_7_init_complete,dfi_7_out_rst_n,dfi_8_dw_rddata_p0[255:0],dfi_8_dw_rddata_dm_p0[31:0],dfi_8_dw_rddata_dbi_p0[31:0],dfi_8_dw_rddata_par_p0[7:0],dfi_8_dw_rddata_p1[255:0],dfi_8_dw_rddata_dm_p1[31:0],dfi_8_dw_rddata_dbi_p1[31:0],dfi_8_dw_rddata_par_p1[7:0],dfi_8_dbi_byte_disable[15:0],dfi_8_dw_rddata_valid[3:0],dfi_8_dw_derr_n[7:0],dfi_8_aw_aerr_n[1:0],dfi_8_ctrlupd_req,dfi_8_phyupd_ack,dfi_8_clk_init,dfi_8_init_complete,dfi_8_out_rst_n,dfi_9_dw_rddata_p0[255:0],dfi_9_dw_rddata_dm_p0[31:0],dfi_9_dw_rddata_dbi_p0[31:0],dfi_9_dw_rddata_par_p0[7:0],dfi_9_dw_rddata_p1[255:0],dfi_9_dw_rddata_dm_p1[31:0],dfi_9_dw_rddata_dbi_p1[31:0],dfi_9_dw_rddata_par_p1[7:0],dfi_9_dbi_byte_disable[15:0],dfi_9_dw_rddata_valid[3:0],dfi_9_dw_derr_n[7:0],dfi_9_aw_aerr_n[1:0],dfi_9_ctrlupd_req,dfi_9_phyupd_ack,dfi_9_clk_init,dfi_9_init_complete,dfi_9_out_rst_n,dfi_10_dw_rddata_p0[255:0],dfi_10_dw_rddata_dm_p0[31:0],dfi_10_dw_rddata_dbi_p0[31:0],dfi_10_dw_rddata_par_p0[7:0],dfi_10_dw_rddata_p1[255:0],dfi_10_dw_rddata_dm_p1[31:0],dfi_10_dw_rddata_dbi_p1[31:0],dfi_10_dw_rddata_par_p1[7:0],dfi_10_dbi_byte_disable[15:0],dfi_10_dw_rddata_valid[3:0],dfi_10_dw_derr_n[7:0],dfi_10_aw_aerr_n[1:0],dfi_10_ctrlupd_req,dfi_10_phyupd_ack,dfi_10_clk_init,dfi_10_init_complete,dfi_10_out_rst_n,dfi_11_dw_rddata_p0[255:0],dfi_11_dw_rddata_dm_p0[31:0],dfi_11_dw_rddata_dbi_p0[31:0],dfi_11_dw_rddata_par_p0[7:0],dfi_11_dw_rddata_p1[255:0],dfi_11_dw_rddata_dm_p1[31:0],dfi_11_dw_rddata_dbi_p1[31:0],dfi_11_dw_rddata_par_p1[7:0],dfi_11_dbi_byte_disable[15:0],dfi_11_dw_rddata_valid[3:0],dfi_11_dw_derr_n[7:0],dfi_11_aw_aerr_n[1:0],dfi_11_ctrlupd_req,dfi_11_phyupd_ack,dfi_11_clk_init,dfi_11_init_complete,dfi_11_out_rst_n,dfi_12_dw_rddata_p0[255:0],dfi_12_dw_rddata_dm_p0[31:0],dfi_12_dw_rddata_dbi_p0[31:0],dfi_12_dw_rddata_par_p0[7:0],dfi_12_dw_rddata_p1[255:0],dfi_12_dw_rddata_dm_p1[31:0],dfi_12_dw_rddata_dbi_p1[31:0],dfi_12_dw_rddata_par_p1[7:0],dfi_12_dbi_byte_disable[15:0],dfi_12_dw_rddata_valid[3:0],dfi_12_dw_derr_n[7:0],dfi_12_aw_aerr_n[1:0],dfi_12_ctrlupd_req,dfi_12_phyupd_ack,dfi_12_clk_init,dfi_12_init_complete,dfi_12_out_rst_n,dfi_13_dw_rddata_p0[255:0],dfi_13_dw_rddata_dm_p0[31:0],dfi_13_dw_rddata_dbi_p0[31:0],dfi_13_dw_rddata_par_p0[7:0],dfi_13_dw_rddata_p1[255:0],dfi_13_dw_rddata_dm_p1[31:0],dfi_13_dw_rddata_dbi_p1[31:0],dfi_13_dw_rddata_par_p1[7:0],dfi_13_dbi_byte_disable[15:0],dfi_13_dw_rddata_valid[3:0],dfi_13_dw_derr_n[7:0],dfi_13_aw_aerr_n[1:0],dfi_13_ctrlupd_req,dfi_13_phyupd_ack,dfi_13_clk_init,dfi_13_init_complete,dfi_13_out_rst_n,dfi_14_dw_rddata_p0[255:0],dfi_14_dw_rddata_dm_p0[31:0],dfi_14_dw_rddata_dbi_p0[31:0],dfi_14_dw_rddata_par_p0[7:0],dfi_14_dw_rddata_p1[255:0],dfi_14_dw_rddata_dm_p1[31:0],dfi_14_dw_rddata_dbi_p1[31:0],dfi_14_dw_rddata_par_p1[7:0],dfi_14_dbi_byte_disable[15:0],dfi_14_dw_rddata_valid[3:0],dfi_14_dw_derr_n[7:0],dfi_14_aw_aerr_n[1:0],dfi_14_ctrlupd_req,dfi_14_phyupd_ack,dfi_14_clk_init,dfi_14_init_complete,dfi_14_out_rst_n,dfi_15_dw_rddata_p0[255:0],dfi_15_dw_rddata_dm_p0[31:0],dfi_15_dw_rddata_dbi_p0[31:0],dfi_15_dw_rddata_par_p0[7:0],dfi_15_dw_rddata_p1[255:0],dfi_15_dw_rddata_dm_p1[31:0],dfi_15_dw_rddata_dbi_p1[31:0],dfi_15_dw_rddata_par_p1[7:0],dfi_15_dbi_byte_disable[15:0],dfi_15_dw_rddata_valid[3:0],dfi_15_dw_derr_n[7:0],dfi_15_aw_aerr_n[1:0],dfi_15_ctrlupd_req,dfi_15_phyupd_ack,dfi_15_clk_init,dfi_15_init_complete,dfi_15_out_rst_n,apb_complete_0,apb_complete_1,DRAM_0_STAT_CATTRIP,DRAM_0_STAT_TEMP[6:0],DRAM_1_STAT_CATTRIP,DRAM_1_STAT_TEMP[6:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "hbm_v1_0_9,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo new file mode 100755 index 0000000..f6b9dee --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +instr_blk_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [10 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file instr_blk_mem.v when simulating +// the core, instr_blk_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho new file mode 100755 index 0000000..90d7f09 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT instr_blk_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : instr_blk_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file instr_blk_mem.vhd when simulating +-- the core, instr_blk_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v new file mode 100644 index 0000000..0131dc3 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:12 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem_stub.v +// Design : instr_blk_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module instr_blk_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[10:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [10:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl new file mode 100644 index 0000000..df27e48 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:12 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem_stub.vhdl +-- Design : instr_blk_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity instr_blk_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end instr_blk_mem; + +architecture stub of instr_blk_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[10:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo new file mode 100755 index 0000000..a025769 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +instr_blk_mem_sim your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [9 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file instr_blk_mem_sim.v when simulating +// the core, instr_blk_mem_sim. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho new file mode 100755 index 0000000..3eccade --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT instr_blk_mem_sim + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : instr_blk_mem_sim + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file instr_blk_mem_sim.vhd when simulating +-- the core, instr_blk_mem_sim. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v new file mode 100644 index 0000000..66874ff --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:16 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v +// Design : instr_blk_mem_sim +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module instr_blk_mem_sim(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [9:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl new file mode 100644 index 0000000..9e7993f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:16 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl +-- Design : instr_blk_mem_sim +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity instr_blk_mem_sim is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end instr_blk_mem_sim; + +architecture stub of instr_blk_mem_sim is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[9:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.veo new file mode 100755 index 0000000..4d42d6c --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +pr_read_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [4 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file pr_read_mem.v when simulating +// the core, pr_read_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.vho new file mode 100755 index 0000000..7680138 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT pr_read_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : pr_read_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file pr_read_mem.vhd when simulating +-- the core, pr_read_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v new file mode 100644 index 0000000..330eea1 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:11 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem_stub.v +// Design : pr_read_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module pr_read_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[4:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [4:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl new file mode 100644 index 0000000..1a52518 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:11 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem_stub.vhdl +-- Design : pr_read_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity pr_read_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 4 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end pr_read_mem; + +architecture stub of pr_read_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[4:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo new file mode 100755 index 0000000..ba9a615 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +pr_ref_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [6 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file pr_ref_mem.v when simulating +// the core, pr_ref_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho new file mode 100755 index 0000000..387e5f3 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT pr_ref_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : pr_ref_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file pr_ref_mem.vhd when simulating +-- the core, pr_ref_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v new file mode 100644 index 0000000..25fb46b --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:11 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem_stub.v +// Design : pr_ref_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module pr_ref_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[6:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [6:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl new file mode 100644 index 0000000..4cbf052 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:12 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem_stub.vhdl +-- Design : pr_ref_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity pr_ref_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end pr_ref_mem; + +architecture stub of pr_ref_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[6:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.veo new file mode 100755 index 0000000..14fbb52 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.veo @@ -0,0 +1,77 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +rdback_fifo your_instance_name ( + .clk(clk), // input wire clk + .srst(srst), // input wire srst + .din(din), // input wire [511 : 0] din + .wr_en(wr_en), // input wire wr_en + .rd_en(rd_en), // input wire rd_en + .dout(dout), // output wire [255 : 0] dout + .full(full), // output wire full + .empty(empty), // output wire empty + .valid(valid), // output wire valid + .prog_full(prog_full), // output wire prog_full + .prog_empty(prog_empty), // output wire prog_empty + .wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy + .rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file rdback_fifo.v when simulating +// the core, rdback_fifo. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.vho new file mode 100755 index 0000000..2d2c0ed --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.vho @@ -0,0 +1,99 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fifo_generator:13.2 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT rdback_fifo + PORT ( + clk : IN STD_LOGIC; + srst : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + valid : OUT STD_LOGIC; + prog_full : OUT STD_LOGIC; + prog_empty : OUT STD_LOGIC; + wr_rst_busy : OUT STD_LOGIC; + rd_rst_busy : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : rdback_fifo + PORT MAP ( + clk => clk, + srst => srst, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty, + valid => valid, + prog_full => prog_full, + prog_empty => prog_empty, + wr_rst_busy => wr_rst_busy, + rd_rst_busy => rd_rst_busy + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file rdback_fifo.vhd when simulating +-- the core, rdback_fifo. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v new file mode 100644 index 0000000..fe6e59e --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v @@ -0,0 +1,33 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:08 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/rdback_fifo/rdback_fifo_stub.v +// Design : rdback_fifo +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *) +module rdback_fifo(clk, srst, din, wr_en, rd_en, dout, full, empty, valid, + prog_full, prog_empty, wr_rst_busy, rd_rst_busy) +/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[511:0],wr_en,rd_en,dout[255:0],full,empty,valid,prog_full,prog_empty,wr_rst_busy,rd_rst_busy" */; + input clk; + input srst; + input [511:0]din; + input wr_en; + input rd_en; + output [255:0]dout; + output full; + output empty; + output valid; + output prog_full; + output prog_empty; + output wr_rst_busy; + output rd_rst_busy; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl new file mode 100644 index 0000000..2fba8e6 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl @@ -0,0 +1,42 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:08 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/rdback_fifo/rdback_fifo_stub.vhdl +-- Design : rdback_fifo +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity rdback_fifo is + Port ( + clk : in STD_LOGIC; + srst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 511 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 255 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + valid : out STD_LOGIC; + prog_full : out STD_LOGIC; + prog_empty : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC + ); + +end rdback_fifo; + +architecture stub of rdback_fifo is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,srst,din[511:0],wr_en,rd_en,dout[255:0],full,empty,valid,prog_full,prog_empty,wr_rst_busy,rd_rst_busy"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.veo new file mode 100755 index 0000000..2e2c1b0 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +scratchpad your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [9 : 0] addra + .dina(dina), // input wire [31 : 0] dina + .douta(douta) // output wire [31 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file scratchpad.v when simulating +// the core, scratchpad. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.vho new file mode 100755 index 0000000..8d2d151 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT scratchpad + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : scratchpad + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file scratchpad.vhd when simulating +-- the core, scratchpad. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.v new file mode 100644 index 0000000..7122b49 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:10 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad_stub.v +// Design : scratchpad +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module scratchpad(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[31:0],douta[31:0]" */; + input clka; + input ena; + input [0:0]wea; + input [9:0]addra; + input [31:0]dina; + output [31:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl new file mode 100644 index 0000000..044c890 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:10 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad_stub.vhdl +-- Design : scratchpad +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity scratchpad is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 31 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end scratchpad; + +architecture stub of scratchpad is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[9:0],dina[31:0],douta[31:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.veo new file mode 100755 index 0000000..4dcafaf --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.veo @@ -0,0 +1,75 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +wrdata_fifo your_instance_name ( + .srst(srst), // input wire srst + .wr_clk(wr_clk), // input wire wr_clk + .rd_clk(rd_clk), // input wire rd_clk + .din(din), // input wire [1023 : 0] din + .wr_en(wr_en), // input wire wr_en + .rd_en(rd_en), // input wire rd_en + .dout(dout), // output wire [511 : 0] dout + .full(full), // output wire full + .empty(empty), // output wire empty + .wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy + .rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file wrdata_fifo.v when simulating +// the core, wrdata_fifo. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.vho new file mode 100755 index 0000000..adacf54 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.vho @@ -0,0 +1,95 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fifo_generator:13.2 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT wrdata_fifo + PORT ( + srst : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(1023 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + wr_rst_busy : OUT STD_LOGIC; + rd_rst_busy : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : wrdata_fifo + PORT MAP ( + srst => srst, + wr_clk => wr_clk, + rd_clk => rd_clk, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty, + wr_rst_busy => wr_rst_busy, + rd_rst_busy => rd_rst_busy + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file wrdata_fifo.vhd when simulating +-- the core, wrdata_fifo. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.v new file mode 100644 index 0000000..7f976bf --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:18 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/wrdata_fifo/wrdata_fifo_stub.v +// Design : wrdata_fifo +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *) +module wrdata_fifo(srst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, + empty, wr_rst_busy, rd_rst_busy) +/* synthesis syn_black_box black_box_pad_pin="srst,wr_clk,rd_clk,din[1023:0],wr_en,rd_en,dout[511:0],full,empty,wr_rst_busy,rd_rst_busy" */; + input srst; + input wr_clk; + input rd_clk; + input [1023:0]din; + input wr_en; + input rd_en; + output [511:0]dout; + output full; + output empty; + output wr_rst_busy; + output rd_rst_busy; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.vhdl new file mode 100644 index 0000000..bbfea6f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:18 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/wrdata_fifo/wrdata_fifo_stub.vhdl +-- Design : wrdata_fifo +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity wrdata_fifo is + Port ( + srst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 1023 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 511 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC + ); + +end wrdata_fifo; + +architecture stub of wrdata_fifo is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "srst,wr_clk,rd_clk,din[1023:0],wr_en,rd_en,dout[511:0],full,empty,wr_rst_busy,rd_rst_busy"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.veo new file mode 100755 index 0000000..bd81a3c --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.veo @@ -0,0 +1,95 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:xdma:4.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +xdma your_instance_name ( + .sys_clk(sys_clk), // input wire sys_clk + .sys_clk_gt(sys_clk_gt), // input wire sys_clk_gt + .sys_rst_n(sys_rst_n), // input wire sys_rst_n + .user_lnk_up(user_lnk_up), // output wire user_lnk_up + .pci_exp_txp(pci_exp_txp), // output wire [7 : 0] pci_exp_txp + .pci_exp_txn(pci_exp_txn), // output wire [7 : 0] pci_exp_txn + .pci_exp_rxp(pci_exp_rxp), // input wire [7 : 0] pci_exp_rxp + .pci_exp_rxn(pci_exp_rxn), // input wire [7 : 0] pci_exp_rxn + .axi_aclk(axi_aclk), // output wire axi_aclk + .axi_aresetn(axi_aresetn), // output wire axi_aresetn + .usr_irq_req(usr_irq_req), // input wire [0 : 0] usr_irq_req + .usr_irq_ack(usr_irq_ack), // output wire [0 : 0] usr_irq_ack + .msi_enable(msi_enable), // output wire msi_enable + .msi_vector_width(msi_vector_width), // output wire [2 : 0] msi_vector_width + .cfg_mgmt_addr(cfg_mgmt_addr), // input wire [18 : 0] cfg_mgmt_addr + .cfg_mgmt_write(cfg_mgmt_write), // input wire cfg_mgmt_write + .cfg_mgmt_write_data(cfg_mgmt_write_data), // input wire [31 : 0] cfg_mgmt_write_data + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), // input wire [3 : 0] cfg_mgmt_byte_enable + .cfg_mgmt_read(cfg_mgmt_read), // input wire cfg_mgmt_read + .cfg_mgmt_read_data(cfg_mgmt_read_data), // output wire [31 : 0] cfg_mgmt_read_data + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), // output wire cfg_mgmt_read_write_done + .s_axis_c2h_tdata_0(s_axis_c2h_tdata_0), // input wire [255 : 0] s_axis_c2h_tdata_0 + .s_axis_c2h_tlast_0(s_axis_c2h_tlast_0), // input wire s_axis_c2h_tlast_0 + .s_axis_c2h_tvalid_0(s_axis_c2h_tvalid_0), // input wire s_axis_c2h_tvalid_0 + .s_axis_c2h_tready_0(s_axis_c2h_tready_0), // output wire s_axis_c2h_tready_0 + .s_axis_c2h_tkeep_0(s_axis_c2h_tkeep_0), // input wire [31 : 0] s_axis_c2h_tkeep_0 + .m_axis_h2c_tdata_0(m_axis_h2c_tdata_0), // output wire [255 : 0] m_axis_h2c_tdata_0 + .m_axis_h2c_tlast_0(m_axis_h2c_tlast_0), // output wire m_axis_h2c_tlast_0 + .m_axis_h2c_tvalid_0(m_axis_h2c_tvalid_0), // output wire m_axis_h2c_tvalid_0 + .m_axis_h2c_tready_0(m_axis_h2c_tready_0), // input wire m_axis_h2c_tready_0 + .m_axis_h2c_tkeep_0(m_axis_h2c_tkeep_0) // output wire [31 : 0] m_axis_h2c_tkeep_0 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file xdma.v when simulating +// the core, xdma. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.vho new file mode 100755 index 0000000..52e712f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.vho @@ -0,0 +1,135 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:xdma:4.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT xdma + PORT ( + sys_clk : IN STD_LOGIC; + sys_clk_gt : IN STD_LOGIC; + sys_rst_n : IN STD_LOGIC; + user_lnk_up : OUT STD_LOGIC; + pci_exp_txp : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + pci_exp_txn : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + pci_exp_rxp : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + pci_exp_rxn : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + axi_aclk : OUT STD_LOGIC; + axi_aresetn : OUT STD_LOGIC; + usr_irq_req : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + usr_irq_ack : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + msi_enable : OUT STD_LOGIC; + msi_vector_width : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + cfg_mgmt_addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0); + cfg_mgmt_write : IN STD_LOGIC; + cfg_mgmt_write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_mgmt_byte_enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + cfg_mgmt_read : IN STD_LOGIC; + cfg_mgmt_read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_mgmt_read_write_done : OUT STD_LOGIC; + s_axis_c2h_tdata_0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + s_axis_c2h_tlast_0 : IN STD_LOGIC; + s_axis_c2h_tvalid_0 : IN STD_LOGIC; + s_axis_c2h_tready_0 : OUT STD_LOGIC; + s_axis_c2h_tkeep_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_h2c_tdata_0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + m_axis_h2c_tlast_0 : OUT STD_LOGIC; + m_axis_h2c_tvalid_0 : OUT STD_LOGIC; + m_axis_h2c_tready_0 : IN STD_LOGIC; + m_axis_h2c_tkeep_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : xdma + PORT MAP ( + sys_clk => sys_clk, + sys_clk_gt => sys_clk_gt, + sys_rst_n => sys_rst_n, + user_lnk_up => user_lnk_up, + pci_exp_txp => pci_exp_txp, + pci_exp_txn => pci_exp_txn, + pci_exp_rxp => pci_exp_rxp, + pci_exp_rxn => pci_exp_rxn, + axi_aclk => axi_aclk, + axi_aresetn => axi_aresetn, + usr_irq_req => usr_irq_req, + usr_irq_ack => usr_irq_ack, + msi_enable => msi_enable, + msi_vector_width => msi_vector_width, + cfg_mgmt_addr => cfg_mgmt_addr, + cfg_mgmt_write => cfg_mgmt_write, + cfg_mgmt_write_data => cfg_mgmt_write_data, + cfg_mgmt_byte_enable => cfg_mgmt_byte_enable, + cfg_mgmt_read => cfg_mgmt_read, + cfg_mgmt_read_data => cfg_mgmt_read_data, + cfg_mgmt_read_write_done => cfg_mgmt_read_write_done, + s_axis_c2h_tdata_0 => s_axis_c2h_tdata_0, + s_axis_c2h_tlast_0 => s_axis_c2h_tlast_0, + s_axis_c2h_tvalid_0 => s_axis_c2h_tvalid_0, + s_axis_c2h_tready_0 => s_axis_c2h_tready_0, + s_axis_c2h_tkeep_0 => s_axis_c2h_tkeep_0, + m_axis_h2c_tdata_0 => m_axis_h2c_tdata_0, + m_axis_h2c_tlast_0 => m_axis_h2c_tlast_0, + m_axis_h2c_tvalid_0 => m_axis_h2c_tvalid_0, + m_axis_h2c_tready_0 => m_axis_h2c_tready_0, + m_axis_h2c_tkeep_0 => m_axis_h2c_tkeep_0 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file xdma.vhd when simulating +-- the core, xdma. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.v new file mode 100644 index 0000000..b3aa0af --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.v @@ -0,0 +1,56 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:37:02 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/xdma_stub.v +// Design : xdma +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "xdma_core_top,Vivado 2020.2" *) +module xdma(sys_clk, sys_clk_gt, sys_rst_n, user_lnk_up, + pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, axi_aclk, axi_aresetn, usr_irq_req, + usr_irq_ack, msi_enable, msi_vector_width, cfg_mgmt_addr, cfg_mgmt_write, + cfg_mgmt_write_data, cfg_mgmt_byte_enable, cfg_mgmt_read, cfg_mgmt_read_data, + cfg_mgmt_read_write_done, s_axis_c2h_tdata_0, s_axis_c2h_tlast_0, s_axis_c2h_tvalid_0, + s_axis_c2h_tready_0, s_axis_c2h_tkeep_0, m_axis_h2c_tdata_0, m_axis_h2c_tlast_0, + m_axis_h2c_tvalid_0, m_axis_h2c_tready_0, m_axis_h2c_tkeep_0) +/* synthesis syn_black_box black_box_pad_pin="sys_clk,sys_clk_gt,sys_rst_n,user_lnk_up,pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,s_axis_c2h_tdata_0[255:0],s_axis_c2h_tlast_0,s_axis_c2h_tvalid_0,s_axis_c2h_tready_0,s_axis_c2h_tkeep_0[31:0],m_axis_h2c_tdata_0[255:0],m_axis_h2c_tlast_0,m_axis_h2c_tvalid_0,m_axis_h2c_tready_0,m_axis_h2c_tkeep_0[31:0]" */; + input sys_clk; + input sys_clk_gt; + input sys_rst_n; + output user_lnk_up; + output [7:0]pci_exp_txp; + output [7:0]pci_exp_txn; + input [7:0]pci_exp_rxp; + input [7:0]pci_exp_rxn; + output axi_aclk; + output axi_aresetn; + input [0:0]usr_irq_req; + output [0:0]usr_irq_ack; + output msi_enable; + output [2:0]msi_vector_width; + input [18:0]cfg_mgmt_addr; + input cfg_mgmt_write; + input [31:0]cfg_mgmt_write_data; + input [3:0]cfg_mgmt_byte_enable; + input cfg_mgmt_read; + output [31:0]cfg_mgmt_read_data; + output cfg_mgmt_read_write_done; + input [255:0]s_axis_c2h_tdata_0; + input s_axis_c2h_tlast_0; + input s_axis_c2h_tvalid_0; + output s_axis_c2h_tready_0; + input [31:0]s_axis_c2h_tkeep_0; + output [255:0]m_axis_h2c_tdata_0; + output m_axis_h2c_tlast_0; + output m_axis_h2c_tvalid_0; + input m_axis_h2c_tready_0; + output [31:0]m_axis_h2c_tkeep_0; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.vhdl new file mode 100644 index 0000000..9e6a49f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.vhdl @@ -0,0 +1,60 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:37:02 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/xdma_stub.vhdl +-- Design : xdma +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity xdma is + Port ( + sys_clk : in STD_LOGIC; + sys_clk_gt : in STD_LOGIC; + sys_rst_n : in STD_LOGIC; + user_lnk_up : out STD_LOGIC; + pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); + pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); + pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); + axi_aclk : out STD_LOGIC; + axi_aresetn : out STD_LOGIC; + usr_irq_req : in STD_LOGIC_VECTOR ( 0 to 0 ); + usr_irq_ack : out STD_LOGIC_VECTOR ( 0 to 0 ); + msi_enable : out STD_LOGIC; + msi_vector_width : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 ); + cfg_mgmt_write : in STD_LOGIC; + cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_mgmt_read : in STD_LOGIC; + cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_read_write_done : out STD_LOGIC; + s_axis_c2h_tdata_0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + s_axis_c2h_tlast_0 : in STD_LOGIC; + s_axis_c2h_tvalid_0 : in STD_LOGIC; + s_axis_c2h_tready_0 : out STD_LOGIC; + s_axis_c2h_tkeep_0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axis_h2c_tdata_0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + m_axis_h2c_tlast_0 : out STD_LOGIC; + m_axis_h2c_tvalid_0 : out STD_LOGIC; + m_axis_h2c_tready_0 : in STD_LOGIC; + m_axis_h2c_tkeep_0 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end xdma; + +architecture stub of xdma is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "sys_clk,sys_clk_gt,sys_rst_n,user_lnk_up,pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,s_axis_c2h_tdata_0[255:0],s_axis_c2h_tlast_0,s_axis_c2h_tvalid_0,s_axis_c2h_tready_0,s_axis_c2h_tkeep_0[31:0],m_axis_h2c_tdata_0[255:0],m_axis_h2c_tlast_0,m_axis_h2c_tvalid_0,m_axis_h2c_tready_0,m_axis_h2c_tkeep_0[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "xdma_core_top,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo new file mode 100755 index 0000000..a437d51 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +zq_calib_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [6 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file zq_calib_mem.v when simulating +// the core, zq_calib_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho new file mode 100755 index 0000000..d9e1b0c --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT zq_calib_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : zq_calib_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file zq_calib_mem.vhd when simulating +-- the core, zq_calib_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v new file mode 100644 index 0000000..4515302 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:12 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem_stub.v +// Design : zq_calib_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module zq_calib_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[6:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [6:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl new file mode 100644 index 0000000..0c3fee3 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:12 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem_stub.vhdl +-- Design : zq_calib_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity zq_calib_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end zq_calib_mem; + +architecture stub of zq_calib_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[6:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/mem_init_files/program.coe b/projects/U50-HBM/U50-HBM.ip_user_files/mem_init_files/program.coe new file mode 100755 index 0000000..c59a1d2 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/mem_init_files/program.coe @@ -0,0 +1,549 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0000000000000110000000000000000000000000100010000000000000000000, +0000000000000110000000000000000000000000101100000000000100000000, +0000000000000110000000000000000000000000000000000000000010000000, +0000000000000110000000000000000000000000000100000000000000010000, +0000000000000110000000000000000000000000001000000000000000010000, +0000000000000110000000000000000000000000011100000000000000000000, +0000000000000110000000000000000000000000011000000000000000000000, +0000000000000110000000000000000000000000010000000000000000000000, +0000000000000110000000000000000000000000001100000000000000000000, +0000000000000110000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000111, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100111, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, 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+1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +0000000000000000000000000000000000000000000000000000000000000000; diff --git a/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/compile.log b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/compile.log new file mode 100644 index 0000000..54c9ddc --- /dev/null +++ b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/compile.log @@ -0,0 +1,79 @@ +** Warning: (vlib-34) Library already exists at "questa_lib/work". +** Warning: (vlib-34) Library already exists at "questa_lib/msim". +** Warning: (vlib-34) Library already exists at "questa_lib/msim/xil_defaultlib". +QuestaSim vmap 2020.1 Lib Mapping Utility 2020.01 Jan 28 2020 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +Modifying modelsim.ini +QuestaSim-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020 +Start time: 17:31:21 on Aug 31,2022 +vlog -incr "+notimingchecks" -work xil_defaultlib "+incdir+../../../../verilog" "+incdir+../../../../../../sources/hdl/header_verilog" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/hbm_0/hdl/rtl" "+incdir+../../../../XUPVVH.ip_user_files/ipstatic/verif/model" "+incdir+/usr/pack/vitis-2020.2-kgf/Vivado/2020.2/data/xilinx_vip/include" ../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v ../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v ../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v ../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v ../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v ../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v ../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v ../../../../XUPVVH.srcs/sources_1/ip/cdc_fifo/sim/cdc_fifo.v +-- Compiling module rdback_fifo +-- Compiling module instr_blk_mem +-- Compiling module instr_blk_mem_sim +-- Compiling module pr_ref_mem +-- Compiling module zq_calib_mem +-- Compiling module pr_read_mem +-- Compiling module scratchpad +-- Compiling module cdc_fifo + +Top level modules: + rdback_fifo + instr_blk_mem + instr_blk_mem_sim + pr_ref_mem + zq_calib_mem + pr_read_mem + scratchpad + cdc_fifo +End time: 17:31:21 on Aug 31,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +QuestaSim-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020 +Start time: 17:31:21 on Aug 31,2022 +vlog -incr "+notimingchecks" -sv -L hbm_v1_0_9 -work xil_defaultlib "+incdir+../../../../verilog" "+incdir+../../../../../../sources/hdl/header_verilog" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/hbm_0/hdl/rtl" "+incdir+../../../../XUPVVH.ip_user_files/ipstatic/verif/model" "+incdir+/usr/pack/vitis-2020.2-kgf/Vivado/2020.2/data/xilinx_vip/include" ../../../../XUPVVH.srcs/sources_1/ip/hbm_0/hdl/rtl/hbm_v1_0_9.sv ../../../../XUPVVH.srcs/sources_1/ip/hbm_0/verif/model/hbm_model.sv ../../../../XUPVVH.srcs/sources_1/ip/hbm_0/sim/hbm_0.sv +-- Compiling module hbm_v1_0_9 +-- Compiling module HBM +-- Compiling module hbm_0 + +Top level modules: + HBM + hbm_0 +End time: 17:31:22 on Aug 31,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +QuestaSim-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020 +Start time: 17:31:22 on Aug 31,2022 +vlog -incr "+notimingchecks" -work xil_defaultlib "+incdir+../../../../verilog" "+incdir+../../../../../../sources/hdl/header_verilog" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/hbm_0/hdl/rtl" "+incdir+../../../../XUPVVH.ip_user_files/ipstatic/verif/model" "+incdir+/usr/pack/vitis-2020.2-kgf/Vivado/2020.2/data/xilinx_vip/include" ../../../../XUPVVH.srcs/sources_1/new/HBM_adapter.v ../../../../XUPVVH.srcs/sources_1/new/HBM_interface.v ../../../../XUPVVH.srcs/sources_1/new/cdc_HBM_to_rbe.v ../../../../XUPVVH.srcs/sources_1/new/cmd_buf.v ../../../../XUPVVH.srcs/sources_1/imports/new/cmd_gen.v ../../../../XUPVVH.srcs/sources_1/imports/new/controller_top.v ../../../../../../sources/hdl/verilog/ddr_pipeline.v ../../../../../../sources/hdl/verilog/decode_stage.v ../../../../../../sources/hdl/verilog/diff_shift_reg.v ../../../../../../sources/hdl/verilog/exe_pipeline.v ../../../../../../sources/hdl/verilog/execute_stage.v ../../../../../../sources/hdl/verilog/fetch_stage.v ../../../../../../sources/hdl/verilog/frontend.v ../../../../../../sources/hdl/verilog/maintenance_controller.v ../../../../../../sources/hdl/verilog/pop_count4.v ../../../../../../sources/hdl/verilog/pre_decode.v ../../../../../../sources/hdl/verilog/readback_engine.v ../../../../../../sources/hdl/verilog/register_file.v ../../../../../../sources/hdl/verilog/softmc_pipeline.v ../../../../verilog/softmc_top.v ../../../../XUPVVH.srcs/sim_1/new/sim_tb_top.v +-- Compiling module HBM_adapter +-- Compiling module HBM_interface +-- Compiling module cdc_HBM_to_rbe +-- Compiling module cmd_buf +-- Compiling module cmd_gen +-- Compiling module controller_top +-- Compiling module ddr_pipeline +-- Compiling module decode_stage +-- Compiling module diff_shift_reg +-- Compiling module exe_pipeline +-- Compiling module execute_stage +-- Compiling module fetch_stage +-- Compiling module frontend +-- Compiling module maintenance_controller +-- Compiling module pop_count4 +-- Compiling module pre_decode +-- Compiling module readback_engine +-- Compiling module register_file +-- Compiling module softmc_pipeline +-- Compiling module softmc_top +-- Compiling module sim_tb_top + +Top level modules: + sim_tb_top +End time: 17:31:22 on Aug 31,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +QuestaSim vlog 2020.1 Compiler 2020.01 Jan 28 2020 +Start time: 17:31:22 on Aug 31,2022 +vlog -work xil_defaultlib glbl.v +-- Compiling module glbl + +Top level modules: + glbl +End time: 17:31:23 on Aug 31,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 diff --git a/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/compile.sh b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/compile.sh new file mode 100755 index 0000000..e8a2802 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/compile.sh @@ -0,0 +1,20 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2020.2.1 (64-bit) +# +# Filename : compile.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Script for compiling the simulation design source files +# +# Generated by Vivado on Wed Aug 31 17:31:20 CEST 2022 +# SW Build 3080587 on Fri Dec 11 14:53:26 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: compile.sh +# +# **************************************************************************** +bin_path="/usr/pack/questa-2020.1-kgf/questasim/bin" +set -Eeuo pipefail +source sim_tb_top_compile.do 2>&1 | tee compile.log + diff --git a/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/elaborate.log b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/elaborate.log new file mode 100644 index 0000000..46741f1 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/elaborate.log @@ -0,0 +1,113 @@ +QuestaSim-64 vopt 2020.1 Compiler 2020.01 Jan 28 2020 +Start time: 17:31:23 on Aug 31,2022 +vopt -64 "+acc=npr" -L xil_defaultlib -L fifo_generator_v13_2_5 -L blk_mem_gen_v8_4_4 -L hbm_v1_0_9 -L unisims_ver -L unimacro_ver -L secureip -L xpm -work xil_defaultlib xil_defaultlib.sim_tb_top xil_defaultlib.glbl -o sim_tb_top_opt + +Top level modules: + sim_tb_top + glbl + +Analyzing design... +-- Loading module sim_tb_top +-- Loading module glbl +-- Loading module softmc_top +-- Loading module HBM_adapter +-- Loading module cmd_gen +-- Loading module cmd_buf +-- Loading module controller_top +-- Loading module HBM_interface +-- Loading module hbm_0 +-- Loading module hbm_v1_0_9 +-- Loading module cdc_HBM_to_rbe +-- Loading module cdc_fifo +-- Loading module softmc_pipeline +-- Loading module fetch_stage +-- Loading module pre_decode +-- Loading module decode_stage +-- Loading module execute_stage +-- Loading module ddr_pipeline +-- Loading module exe_pipeline +-- Loading module scratchpad +-- Loading module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4 +-- Loading module register_file +-- Loading module frontend +-- Loading module maintenance_controller +-- Loading module pr_read_mem +-- Loading module zq_calib_mem +-- Loading module pr_ref_mem +-- Loading module unisims_ver.IBUFDS_GTE4 +-- Loading module readback_engine +-- Loading module diff_shift_reg +-- Loading module rdback_fifo +-- Loading module unisims_ver.IBUF +-- Loading module unisims_ver.BUFG +-- Loading module hbm_v1_0_9.hbm_top +-- Loading package STANDARD +-- Loading module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_mem_module +-- Loading module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_output_stage +-- Loading module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_softecc_output_reg_stage +-- Loading module instr_blk_mem_sim +-- Loading module pop_count4 +-- Loading module xpm.xpm_memory_spram +-- Loading module xpm.xpm_memory_base +-- Loading module hbm_v1_0_9.hbm_data_fetch +-- Loading module hbm_v1_0_9.hbm_apb_mst +-- Loading module hbm_v1_0_9.hbm_temp_rd +-- Loading module hbm_v1_0_9.hbm_apb_arbiter +-- Loading module unisims_ver.HBM_TWO_STACK_INTF +-- Loading module secureip.SIP_HBM_TWO_STACK_INTF +-- Loading module secureip.xil_hbm_two_stack_intf_mod786 +-- Loading module secureip.xil_hbm_two_stack_intf_mod1 +-- Loading module secureip.xil_hbm_two_stack_intf_mod6 +-- Loading module secureip.xil_hbm_two_stack_intf_mod2 +-- Loading module secureip.xil_hbm_two_stack_intf_mod4 +-- Loading module HBM +-- Loading architecture FIFO36E2_V of FIFO36E2 +-- Loading package body VPKG +Incremental compilation check found 1119 design-units (out of 1157) may be reused. +Optimizing 38 design-units (inlining 756189/763888 module instances, 0/125778 cell instances, 155200/155200 UDP instances, 0/132 architecture instances): +** Warning: ../../../../XUPVVH.ip_user_files/ipstatic/verif/model/HBM_questa.vp(257): (vopt-2250) Function "" has no return value assignment. +** Warning: ../../../../XUPVVH.ip_user_files/ipstatic/verif/model/HBM_questa.vp(257): (vopt-2250) Function "" has no return value assignment. +-- Optimizing module HBM(fast) +-- Optimizing module hbm_v1_0_9(fast) +-- Optimizing module rdback_fifo(fast) +-- Optimizing module cdc_fifo(fast) +-- Optimizing module hbm_0(fast) +-- Optimizing module readback_engine(fast) +** Warning: ../../../../../../sources/hdl/verilog/readback_engine.v(137): (vopt-2685) [TFMPC] - Too few port connections for 'rbf'. Expected 13, found 10. +** Warning: ../../../../../../sources/hdl/verilog/readback_engine.v(137): (vopt-2718) [TFMPC] - Missing connection for port 'rd_rst_busy'. +** Warning: ../../../../../../sources/hdl/verilog/readback_engine.v(137): (vopt-2718) [TFMPC] - Missing connection for port 'wr_rst_busy'. +** Warning: ../../../../../../sources/hdl/verilog/readback_engine.v(137): (vopt-2718) [TFMPC] - Missing connection for port 'prog_empty'. +-- Optimizing module HBM_interface(fast) +-- Optimizing module decode_stage(fast) +-- Optimizing module maintenance_controller(fast) +-- Optimizing module ddr_pipeline(fast) +-- Optimizing module register_file(fast) +-- Optimizing module exe_pipeline(fast) +-- Optimizing module frontend(fast) +-- Optimizing module cmd_gen(fast) +-- Optimizing module softmc_top(fast) +** Warning: ../../../../verilog/softmc_top.v(300): (vopt-2685) [TFMPC] - Too few port connections for 'pipeline'. Expected 29, found 27. +** Warning: ../../../../verilog/softmc_top.v(300): (vopt-2718) [TFMPC] - Missing connection for port 'ddr_srx'. +** Warning: ../../../../verilog/softmc_top.v(300): (vopt-2718) [TFMPC] - Missing connection for port 'ddr_sre'. +-- Optimizing module fetch_stage(fast) +-- Optimizing module execute_stage(fast) +-- Optimizing module controller_top(fast) +-- Optimizing module softmc_pipeline(fast) +-- Optimizing module scratchpad(fast) +-- Optimizing module instr_blk_mem_sim(fast) +-- Optimizing module pr_read_mem(fast) +-- Optimizing module zq_calib_mem(fast) +-- Optimizing module pr_ref_mem(fast) +-- Optimizing module HBM_adapter(fast) +-- Optimizing module cmd_buf(fast) +-- Optimizing module cdc_HBM_to_rbe(fast) +** Warning: ../../../../XUPVVH.srcs/sources_1/new/cdc_HBM_to_rbe.v(66): (vopt-2685) [TFMPC] - Too few port connections for 'cdc_fifo0'. Expected 12, found 10. +** Warning: ../../../../XUPVVH.srcs/sources_1/new/cdc_HBM_to_rbe.v(66): (vopt-2718) [TFMPC] - Missing connection for port 'rd_rst_busy'. +** Warning: ../../../../XUPVVH.srcs/sources_1/new/cdc_HBM_to_rbe.v(66): (vopt-2718) [TFMPC] - Missing connection for port 'wr_rst_busy'. +-- Optimizing module sim_tb_top(fast) +-- Optimizing module diff_shift_reg(fast) +-- Optimizing module pre_decode(fast) +-- Optimizing module pop_count4(fast) +Optimized design name is sim_tb_top_opt +End time: 17:31:36 on Aug 31,2022, Elapsed time: 0:00:13 +Errors: 0, Warnings: 12 diff --git a/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/elaborate.sh b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/elaborate.sh new file mode 100755 index 0000000..462e134 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/elaborate.sh @@ -0,0 +1,20 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2020.2.1 (64-bit) +# +# Filename : elaborate.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Script for elaborating the compiled design +# +# Generated by Vivado on Wed Aug 31 17:31:23 CEST 2022 +# SW Build 3080587 on Fri Dec 11 14:53:26 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: elaborate.sh +# +# **************************************************************************** +bin_path="/usr/pack/questa-2020.1-kgf/questasim/bin" +set -Eeuo pipefail +source sim_tb_top_elaborate.do 2>&1 | tee elaborate.log + diff --git a/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/glbl.v b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/instr_blk_mem_sim.mif b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/instr_blk_mem_sim.mif new file mode 100755 index 0000000..573723e --- /dev/null +++ b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/instr_blk_mem_sim.mif @@ -0,0 +1,547 @@ +0000000000000110000000000000000000000000100010000000000000000000 +0000000000000110000000000000000000000000101100000000000100000000 +0000000000000110000000000000000000000000000000000000000010000000 +0000000000000110000000000000000000000000000100000000000000010000 +0000000000000110000000000000000000000000001000000000000000010000 +0000000000000110000000000000000000000000011100000000000000000000 +0000000000000110000000000000000000000000011000000000000000000000 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a/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/modelsim.ini b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/modelsim.ini new file mode 100644 index 0000000..a144e16 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/modelsim.ini @@ -0,0 +1,2705 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "2021.2_1" + +; Copyright 1991-2021 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +vital2000 = $MODEL_TECH/../vital2000 +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; +verilog = $MODEL_TECH/../verilog +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std +mtiAvm = $MODEL_TECH/../avm +mtiRnm = $MODEL_TECH/../rnm +mtiOvm = $MODEL_TECH/../ovm-2.1.2 +mtiUvm = $MODEL_TECH/../uvm-1.1d +mtiUPF = $MODEL_TECH/../upf_lib +mtiPA = $MODEL_TECH/../pa_lib +floatfixlib = $MODEL_TECH/../floatfixlib +mc2_lib = $MODEL_TECH/../mc2_lib +flps_lib = $MODEL_TECH/../flps_lib +osvvm = $MODEL_TECH/../osvvm + +; added mapping for ADMS +mgc_ams = $MODEL_TECH/../mgc_ams +ieee_env = $MODEL_TECH/../ieee_env + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib +infact = $MODEL_TECH/../infact +vhdlopt_lib = $MODEL_TECH/../vhdlopt_lib +vh_ux01v_lib = $MODEL_TECH/../vh_ux01v_lib + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +secureip = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/secureip +unisim = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/unisim +unimacro = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/unimacro +unifast = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/unifast +unisims_ver = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/unisims_ver +unimacro_ver = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/unimacro_ver +unifast_ver = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/unifast_ver +simprims_ver = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/simprims_ver +xpm = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xpm +xilinx_vip = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xilinx_vip +common_cpp_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/common_cpp_v1_0 +xtlm = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xtlm +emu_perf_common_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/emu_perf_common_v1_0 +axi_tlm_ext_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_tlm_ext_v1_0 +axi_tg_sc_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_tg_sc_v1_0 +noc_sc_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/noc_sc_v1_0_0 +remote_port_c_v4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/remote_port_c_v4 +remote_port_sc_v4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/remote_port_sc_v4 +pl_fileio_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pl_fileio_v1_0_0 +xtlm_simple_interconnect_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xtlm_simple_interconnect_v1_0 +debug_tcp_server_v1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/debug_tcp_server_v1 +rwd_tlmmodel_v1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/rwd_tlmmodel_v1 +common_rpc_v1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/common_rpc_v1 +sim_xdma_cpp_v1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sim_xdma_cpp_v1 +sim_xdma_sc_v1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sim_xdma_sc_v1 +sim_qdma_cpp_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sim_qdma_cpp_v1_0 +sim_qdma_sc_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sim_qdma_sc_v1_0 +xtlm_trace_model_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xtlm_trace_model_v1_0 +aie_xtlm_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/aie_xtlm_v1_0_0 +sim_ddr_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sim_ddr_v1_0 +xtlm_ipc_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xtlm_ipc_v1_0 +xtlm_ap_ctrl_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xtlm_ap_ctrl_v1_0 +axis_switch_sc_v1_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_switch_sc_v1_1 +axis_dwidth_converter_sc_v1_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_dwidth_converter_sc_v1_1 +v_hdmi_tx_v3_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_hdmi_tx_v3_0_0 +util_vector_logic_v2_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/util_vector_logic_v2_0_1 +high_speed_selectio_wiz_v3_5_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/high_speed_selectio_wiz_v3_5_2 +ecc_v2_0_13 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ecc_v2_0_13 +v_multi_scaler_v1_2_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_multi_scaler_v1_2_0 +system_cache_v5_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/system_cache_v5_0_3 +sim_rst_gen_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sim_rst_gen_v1_0_2 +hdcp22_rng_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/hdcp22_rng_v1_0_1 +blk_mem_gen_v8_3_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/blk_mem_gen_v8_3_6 +clk_vip_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/clk_vip_v1_0_2 +av_pat_gen_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/av_pat_gen_v1_0_1 +mammoth_transcode_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mammoth_transcode_v1_0_0 +ll_compress_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ll_compress_v1_0_0 +mrmac_v1_3_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mrmac_v1_3_0 +ddr4_pl_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ddr4_pl_v1_0_3 +uhdsdi_gt_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/uhdsdi_gt_v1_0_3 +axis_cap_ctrl_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_cap_ctrl_v1_0_0 +stm_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/stm_v1_0 +pc_cfr_v6_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pc_cfr_v6_0_8 +stm_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/stm_v1_0_0 +vid_phy_controller_v2_2_7 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/vid_phy_controller_v2_2_7 +lib_pkg_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lib_pkg_v1_0_2 +mpegtsmux_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mpegtsmux_v1_1_0 +v_letterbox_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_letterbox_v1_1_0 +trace_s2mm_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/trace_s2mm_v1_1_0 +roe_framer_v3_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/roe_framer_v3_0_1 +fifo_generator_v13_1_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/fifo_generator_v13_1_4 +v_tpg_v8_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_tpg_v8_1_0 +pcie_jtag_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pcie_jtag_v1_0_0 +xhmc_v1_0_12 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xhmc_v1_0_12 +in_system_ibert_v1_0_12 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/in_system_ibert_v1_0_12 +v_mix_v5_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_mix_v5_0_1 +xlconcat_v2_1_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xlconcat_v2_1_4 +v_uhdsdi_audio_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_uhdsdi_audio_v1_0_1 +aes_v1_1_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/aes_v1_1_2 +v_csc_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_csc_v1_1_0 +smartconnect_v1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/smartconnect_v1_0 +advanced_io_wizard_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/advanced_io_wizard_v1_0_3 +gtwizard_ultrascale_v1_6_10 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/gtwizard_ultrascale_v1_6_10 +nvme_tc_v2_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/nvme_tc_v2_0_0 +util_reduced_logic_v2_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/util_reduced_logic_v2_0_4 +axi_pcie3_v3_0_14 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_pcie3_v3_0_14 +ai_noc = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ai_noc +hdcp22_cipher_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/hdcp22_cipher_v1_0_3 +microblaze_v9_5_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/microblaze_v9_5_4 +emb_fifo_gen_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/emb_fifo_gen_v1_0_2 +pcie_axi4lite_tap_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pcie_axi4lite_tap_v1_0_1 +rld3_pl_phy_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/rld3_pl_phy_v1_0_0 +processing_system7_v5_5_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/processing_system7_v5_5_6 +timer_sync_1588_v1_2_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/timer_sync_1588_v1_2_4 +lut_buffer_v2_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lut_buffer_v2_0_0 +blk_mem_gen_v8_4_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/blk_mem_gen_v8_4_4 +system_cache_v4_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/system_cache_v4_0_6 +shell_utils_msp432_bsl_crc_gen_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/shell_utils_msp432_bsl_crc_gen_v1_0_0 +v_smpte_uhdsdi_tx_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_smpte_uhdsdi_tx_v1_0_0 +an_lt_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/an_lt_v1_0_1 +v_axi4s_remap_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_axi4s_remap_v1_1_0 +axi_remapper_tx_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_remapper_tx_v1_0_0 +high_speed_selectio_wiz_v3_2_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/high_speed_selectio_wiz_v3_2_3 +v_hdmi_tx_v2_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_hdmi_tx_v2_0_0 +hdcp_keymngmt_blk_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/hdcp_keymngmt_blk_v1_0_0 +picxo = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/picxo +ibert_lib_v1_0_7 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ibert_lib_v1_0_7 +axis_mu_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_mu_v1_0_0 +lib_cdc_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lib_cdc_v1_0_2 +v_vid_in_axi4s_v4_0_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_vid_in_axi4s_v4_0_9 +v_hscaler_v1_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_hscaler_v1_0_16 +hdmi_gt_controller_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/hdmi_gt_controller_v1_0_3 +gmii_to_rgmii_v4_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/gmii_to_rgmii_v4_1_0 +high_speed_selectio_wiz_v3_6_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/high_speed_selectio_wiz_v3_6_1 +usxgmii_v1_2_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/usxgmii_v1_2_0 +vid_edid_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/vid_edid_v1_0_0 +ai_pl_trig = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ai_pl_trig +pc_cfr_v6_3_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pc_cfr_v6_3_2 +av_pat_gen_v2_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/av_pat_gen_v2_0_0 +axis_ila_pp_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_ila_pp_v1_0_0 +versal_cips_v2_1_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/versal_cips_v2_1_1 +noc_nps4_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/noc_nps4_v1_0_0 +uhdsdi_gt_v2_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/uhdsdi_gt_v2_0_3 +tcc_decoder_3gpplte_v3_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tcc_decoder_3gpplte_v3_0_6 +axi_chip2chip_v5_0_10 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_chip2chip_v5_0_10 +ieee802d3_clause74_fec_v1_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ieee802d3_clause74_fec_v1_0_8 +axi_infrastructure_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_infrastructure_v1_1_0 +xsdbm_v3_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xsdbm_v3_0_0 +axi_pmon_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_pmon_v1_0_0 +vid_phy_controller_v2_1_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/vid_phy_controller_v2_1_9 +microblaze_v11_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/microblaze_v11_0_4 +noc_nps_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/noc_nps_v1_0_0 +xlslice_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xlslice_v1_0_2 +jesd204c_v4_2_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/jesd204c_v4_2_3 +adc_dac_if_phy_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/adc_dac_if_phy_v1_0_0 +dist_mem_gen_v8_0_13 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dist_mem_gen_v8_0_13 +v_uhdsdi_audio_v2_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_uhdsdi_audio_v2_0_3 +fifo_generator_v13_2_5 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/fifo_generator_v13_2_5 +v_scenechange_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_scenechange_v1_0_4 +axi_bram_ctrl_v4_1_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_bram_ctrl_v4_1_4 +v_deinterlacer_v5_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_deinterlacer_v5_1_0 +lmb_bram_if_cntlr_v4_0_19 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lmb_bram_if_cntlr_v4_0_19 +axi_lite_ipif_v3_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_lite_ipif_v3_0_4 +tmr_inject_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tmr_inject_v1_0_4 +v_gamma_lut_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_gamma_lut_v1_1_0 +noc_ncrb_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/noc_ncrb_v1_0_0 +microblaze_v10_0_7 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/microblaze_v10_0_7 +mipi_csi2_tx_ctrl_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mipi_csi2_tx_ctrl_v1_0_4 +axis_protocol_checker_v2_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_protocol_checker_v2_0_6 +xsdbm_v2_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xsdbm_v2_0_0 +v_demosaic_v1_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_demosaic_v1_0_8 +gtwizard_ultrascale_v1_5_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/gtwizard_ultrascale_v1_5_4 +noc_na_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/noc_na_v1_0_0 +axis_ila_adv_trig_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_ila_adv_trig_v1_0_0 +pc_cfr_v6_4_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pc_cfr_v6_4_0 +axi_tg_lib = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_tg_lib +v_vscaler_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_vscaler_v1_1_0 +v_vcresampler_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_vcresampler_v1_1_0 +lut_buffer_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lut_buffer_v1_0_0 +xdma_v4_1_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xdma_v4_1_9 +zynq_ultra_ps_e_v3_3_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/zynq_ultra_ps_e_v3_3_3 +dp_videoaxi4s_bridge_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dp_videoaxi4s_bridge_v1_0_1 +multi_channel_25g_rs_fec_v1_0_11 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/multi_channel_25g_rs_fec_v1_0_11 +hdcp_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/hdcp_v1_0_3 +v_tpg_v7_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_tpg_v7_0_16 +axi_jtag_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_jtag_v1_0_0 +v_smpte_uhdsdi_v1_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_smpte_uhdsdi_v1_0_8 +tmr_voter_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tmr_voter_v1_0_3 +v_hcresampler_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_hcresampler_v1_1_0 +ai_pl = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ai_pl +pci32_v5_0_12 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pci32_v5_0_12 +sem_ultra_v3_1_17 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sem_ultra_v3_1_17 +nvmeha_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/nvmeha_v1_0_3 +v_sdi_rx_vid_bridge_v2_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_sdi_rx_vid_bridge_v2_0_0 +i2s_receiver_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/i2s_receiver_v1_0_4 +v_frmbuf_wr_v2_1_5 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_frmbuf_wr_v2_1_5 +noc_nidb_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/noc_nidb_v1_0_0 +bs_mux_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/bs_mux_v1_0_0 +video_frame_crc_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/video_frame_crc_v1_0_3 +high_speed_selectio_wiz_v3_3_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/high_speed_selectio_wiz_v3_3_1 +v_axi4s_remap_v1_0_14 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_axi4s_remap_v1_0_14 +noc_nps6_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/noc_nps6_v1_0_0 +sim_trig_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sim_trig_v1_0_4 +emb_mem_gen_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/emb_mem_gen_v1_0_3 +v_csc_v1_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_csc_v1_0_16 +util_idelay_ctrl_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/util_idelay_ctrl_v1_0_2 +ta_dma_v1_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ta_dma_v1_0_6 +lmb_v10_v3_0_11 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lmb_v10_v3_0_11 +hbm_v1_0_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/hbm_v1_0_9 +xxv_ethernet_v3_3_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xxv_ethernet_v3_3_0 +gtwizard_ultrascale_v1_7_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/gtwizard_ultrascale_v1_7_9 +cmac_usplus_v3_1_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/cmac_usplus_v3_1_2 +mpegtsmux_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mpegtsmux_v1_0_2 +v_smpte_sdi_v3_0_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_smpte_sdi_v3_0_9 +v_letterbox_v1_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_letterbox_v1_0_16 +axis_ila_ct_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_ila_ct_v1_0_0 +xpm_cdc_gen_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xpm_cdc_gen_v1_0_0 +pcie_dma_versal_v2_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pcie_dma_versal_v2_0_2 +hdcp22_cipher_dp_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/hdcp22_cipher_dp_v1_0_0 +axis_dbg_sync_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_dbg_sync_v1_0_0 +trace_s2mm_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/trace_s2mm_v1_0_0 +mem_pl_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mem_pl_v1_0_0 +v_mix_v5_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_mix_v5_1_0 +qdma_v4_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/qdma_v4_0_3 +gig_ethernet_pcs_pma_v16_1_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/gig_ethernet_pcs_pma_v16_1_9 +mutex_v2_1_11 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mutex_v2_1_11 +v_tpg_v8_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_tpg_v8_0_4 +fifo_generator_v13_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/fifo_generator_v13_0_6 +v_frmbuf_rd_v2_1_5 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_frmbuf_rd_v2_1_5 +v_uhdsdi_audio_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_uhdsdi_audio_v1_1_0 +l_ethernet_v3_2_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/l_ethernet_v3_2_0 +sim_clk_gen_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sim_clk_gen_v1_0_2 +high_speed_selectio_wiz_v3_4_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/high_speed_selectio_wiz_v3_4_1 +rst_vip_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/rst_vip_v1_0_4 +axis_dbg_stub_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_dbg_stub_v1_0_0 +mipi_csi2_rx_ctrl_v1_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mipi_csi2_rx_ctrl_v1_0_8 +cpm4_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/cpm4_v1_0_1 +ten_gig_eth_pcs_pma_v6_0_18 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ten_gig_eth_pcs_pma_v6_0_18 +axi_amm_bridge_v1_0_12 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_amm_bridge_v1_0_12 +xlconstant_v1_1_7 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xlconstant_v1_1_7 +ptp_1588_timer_syncer_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ptp_1588_timer_syncer_v1_0_1 +axis_infrastructure_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_infrastructure_v1_1_0 +pc_cfr_v6_1_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pc_cfr_v6_1_4 +ten_gig_eth_mac_v15_1_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ten_gig_eth_mac_v15_1_9 +qdriv_pl_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/qdriv_pl_v1_0_2 +clk_gen_sim_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/clk_gen_sim_v1_0_0 +v_frmbuf_wr_v2_2_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_frmbuf_wr_v2_2_0 +axi_dbg_hub = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_dbg_hub +sem_v4_1_13 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sem_v4_1_13 +v_vcresampler_v1_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_vcresampler_v1_0_16 +v_vscaler_v1_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_vscaler_v1_0_16 +jesd204_v7_2_10 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/jesd204_v7_2_10 +mipi_dsi_tx_ctrl_v1_0_7 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mipi_dsi_tx_ctrl_v1_0_7 +v_hdmi_phy1_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_hdmi_phy1_v1_0_2 +zynq_ultra_ps_e_v3_2_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/zynq_ultra_ps_e_v3_2_6 +v_hcresampler_v1_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_hcresampler_v1_0_16 +gigantic_mux = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/gigantic_mux +mipi_dphy_v4_3_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mipi_dphy_v4_3_0 +v_hdmi_rx_v3_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_hdmi_rx_v3_0_0 +interlaken_v2_4_7 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/interlaken_v2_4_7 +axis_ila_txns_cntr_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_ila_txns_cntr_v1_0_0 +v_deinterlacer_v5_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_deinterlacer_v5_0_16 +advanced_io_wizard_phy_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/advanced_io_wizard_phy_v1_0_0 +v_scenechange_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_scenechange_v1_1_0 +axis_mem_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_mem_v1_0_0 +compact_gt_v1_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/compact_gt_v1_0_8 +cpm5_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/cpm5_v1_0_1 +v_gamma_lut_v1_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_gamma_lut_v1_0_8 +emc_common_v3_0_5 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/emc_common_v3_0_5 +v_demosaic_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_demosaic_v1_1_0 +v_hdmi_tx1_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_hdmi_tx1_v1_0_0 +vfb_v1_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/vfb_v1_0_16 +bsip_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/bsip_v1_1_0 +rama_v1_1_8_lib = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/rama_v1_1_8_lib +ethernet_1_10_25g_v2_6_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ethernet_1_10_25g_v2_6_0 +axi_ahblite_bridge_v3_0_19 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_ahblite_bridge_v3_0_19 +i2s_transmitter_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/i2s_transmitter_v1_0_4 +audio_clock_recovery_unit_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/audio_clock_recovery_unit_v1_0_2 +oran_radio_if_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/oran_radio_if_v1_1_0 +cmac_v2_6_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/cmac_v2_6_2 +jtag_axi = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/jtag_axi +ddr4_pl_phy_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ddr4_pl_phy_v1_0_0 +iomodule_v3_1_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/iomodule_v3_1_6 +noc_nsu_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/noc_nsu_v1_0_0 +ltlib_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ltlib_v1_0_0 +uram_rd_back_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/uram_rd_back_v1_0_1 +v_frmbuf_rd_v2_2_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_frmbuf_rd_v2_2_0 +xbip_dsp48_wrapper_v3_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_dsp48_wrapper_v3_0_4 +tmr_manager_v1_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tmr_manager_v1_0_6 +gig_ethernet_pcs_pma_v16_2_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/gig_ethernet_pcs_pma_v16_2_1 +v_hdmi_rx_v2_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_hdmi_rx_v2_0_0 +xbip_utils_v3_0_10 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_utils_v3_0_10 +axi_remapper_rx_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_remapper_rx_v1_0_0 +v_multi_scaler_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_multi_scaler_v1_0_4 +v_hscaler_v1_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_hscaler_v1_1_0 +axis_itct_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_itct_v1_0_0 +axi_perf_mon_v5_0_24 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_perf_mon_v5_0_24 +v_smpte_uhdsdi_rx_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_smpte_uhdsdi_rx_v1_0_0 +fit_timer_v2_0_10 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/fit_timer_v2_0_10 +tsn_endpoint_ethernet_mac_block_v1_0_7 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tsn_endpoint_ethernet_mac_block_v1_0_7 +ahblite_axi_bridge_v3_0_17 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ahblite_axi_bridge_v3_0_17 +rld3_pl_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/rld3_pl_v1_0_4 +generic_baseblocks_v2_1_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/generic_baseblocks_v2_1_0 +pc_cfr_v6_2_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pc_cfr_v6_2_2 +oddr_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/oddr_v1_0_2 +v_uhdsdi_vidgen_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_uhdsdi_vidgen_v1_0_1 +pci64_v5_0_11 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pci64_v5_0_11 +audio_tpg_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/audio_tpg_v1_0_0 +lib_srl_fifo_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lib_srl_fifo_v1_0_2 +axi_emc_v3_0_22 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_emc_v3_0_22 +c_reg_fd_v12_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/c_reg_fd_v12_0_6 +c_mux_bit_v12_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/c_mux_bit_v12_0_6 +c_shift_ram_v12_0_14 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/c_shift_ram_v12_0_14 +xbip_pipe_v3_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_pipe_v3_0_6 +xbip_dsp48_addsub_v3_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_dsp48_addsub_v3_0_6 +c_gate_bit_v12_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/c_gate_bit_v12_0_6 +xbip_counter_v3_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_counter_v3_0_6 +xbip_addsub_v3_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_addsub_v3_0_6 +c_addsub_v12_0_14 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/c_addsub_v12_0_14 +c_counter_binary_v12_0_14 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/c_counter_binary_v12_0_14 +c_compare_v12_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/c_compare_v12_0_6 +g709_rs_encoder_v2_2_7 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/g709_rs_encoder_v2_2_7 +c_mux_bus_v12_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/c_mux_bus_v12_0_6 +axi_utils_v2_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_utils_v2_0_6 +rs_toolbox_v9_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/rs_toolbox_v9_0_8 +g709_rs_decoder_v2_2_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/g709_rs_decoder_v2_2_9 +ieee802d3_400g_rs_fec_v1_0_11 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ieee802d3_400g_rs_fec_v1_0_11 +lib_fifo_v1_0_14 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lib_fifo_v1_0_14 +axi_datamover_v5_1_24 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_datamover_v5_1_24 +xbip_bram18k_v3_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_bram18k_v3_0_6 +mult_gen_v12_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mult_gen_v12_0_16 +xbip_dsp48_multadd_v3_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_dsp48_multadd_v3_0_6 +floating_point_v7_1_11 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/floating_point_v7_1_11 +fec_5g_common_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/fec_5g_common_v1_0_1 +icap_arb_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/icap_arb_v1_0_0 +tcc_encoder_3gpplte_v4_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tcc_encoder_3gpplte_v4_0_16 +quadsgmii_v3_5_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/quadsgmii_v3_5_0 +axis_data_fifo_v1_1_23 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_data_fifo_v1_1_23 +floating_point_v7_0_18 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/floating_point_v7_0_18 +cmpy_v6_0_19 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/cmpy_v6_0_19 +xfft_v7_2_11 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xfft_v7_2_11 +lte_fft_v2_0_20 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lte_fft_v2_0_20 +dds_compiler_v6_0_20 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dds_compiler_v6_0_20 +fir_compiler_v7_2_15 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/fir_compiler_v7_2_15 +xbip_multadd_v3_0_15 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_multadd_v3_0_15 +xbip_dsp48_mult_v3_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_dsp48_mult_v3_0_6 +lte_rach_detector_v3_1_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lte_rach_detector_v3_1_8 +dft_v4_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dft_v4_0_16 +v_tc_v6_1_13 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_tc_v6_1_13 +v_dual_splitter_v1_0_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_dual_splitter_v1_0_9 +axi_sg_v4_1_13 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_sg_v4_1_13 +axi_cdma_v4_1_22 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_cdma_v4_1_22 +axi_firewall_v1_0_10 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_firewall_v1_0_10 +g975_efec_i4_v1_0_18 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/g975_efec_i4_v1_0_18 +axis_accelerator_adapter_v2_1_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_accelerator_adapter_v2_1_16 +lib_bmg_v1_0_13 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lib_bmg_v1_0_13 +axi_ethernetlite_v3_0_21 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_ethernetlite_v3_0_21 +ernic_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ernic_v1_0_2 +axi_register_slice_v2_1_22 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_register_slice_v2_1_22 +axi_data_fifo_v2_1_21 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_data_fifo_v2_1_21 +axi_protocol_converter_v2_1_22 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_protocol_converter_v2_1_22 +axis_register_slice_v1_1_22 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_register_slice_v1_1_22 +axis_subset_converter_v1_1_22 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_subset_converter_v1_1_22 +lte_dl_channel_encoder_v3_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lte_dl_channel_encoder_v3_0_16 +axi_msg_v1_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_msg_v1_0_6 +axi4stream_vip_v1_1_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi4stream_vip_v1_1_8 +axi_vip_v1_1_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_vip_v1_1_8 +perf_axi_tg_v1_0_11 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/perf_axi_tg_v1_0_11 +xfft_v9_1_5 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xfft_v9_1_5 +lte_fft_v2_1_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lte_fft_v2_1_3 +v_vid_gt_bridge_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_vid_gt_bridge_v1_0_1 +displayport_v8_1_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/displayport_v8_1_3 +axis_ila_intf_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_ila_intf_v1_0_0 +ieee802d3_25g_rs_fec_v1_0_18 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ieee802d3_25g_rs_fec_v1_0_18 +fec_5g_common_v1_1_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/fec_5g_common_v1_1_1 +ldpc_v2_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ldpc_v2_0_6 +amm_axi_bridge_v1_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/amm_axi_bridge_v1_0_8 +v_tc_v6_2_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_tc_v6_2_1 +v_dp_axi4s_vid_out_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_dp_axi4s_vid_out_v1_0_1 +pr_bitstream_monitor_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pr_bitstream_monitor_v1_0_2 +ieee802d3_50g_rs_fec_v2_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ieee802d3_50g_rs_fec_v2_0_6 +fir_compiler_v5_2_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/fir_compiler_v5_2_6 +lte_3gpp_channel_estimator_v2_0_17 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lte_3gpp_channel_estimator_v2_0_17 +axi_crossbar_v2_1_23 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_crossbar_v2_1_23 +processing_system7_vip_v1_0_10 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/processing_system7_vip_v1_0_10 +bs_switch_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/bs_switch_v1_0_0 +v_axi4s_vid_out_v4_0_11 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_axi4s_vid_out_v4_0_11 +axi4svideo_bridge_v1_0_11 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi4svideo_bridge_v1_0_11 +axis_dwidth_converter_v1_1_21 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_dwidth_converter_v1_1_21 +axis_interconnect_v1_1_18 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_interconnect_v1_1_18 +polar_v1_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/polar_v1_0_6 +axi_uart16550_v2_0_24 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_uart16550_v2_0_24 +ieee802d3_400g_rs_fec_v2_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ieee802d3_400g_rs_fec_v2_0_2 +axi_timebase_wdt_v3_0_14 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_timebase_wdt_v3_0_14 +axis_switch_v1_1_22 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_switch_v1_1_22 +mdm_v3_2_19 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mdm_v3_2_19 +g709_fec_v2_3_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/g709_fec_v2_3_6 +proc_sys_reset_v5_0_13 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/proc_sys_reset_v5_0_13 +versal_cips_ps_vip_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/versal_cips_ps_vip_v1_0_0 +axi_apb_bridge_v3_0_17 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_apb_bridge_v3_0_17 +axi_master_burst_v2_0_7 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_master_burst_v2_0_7 +axi_tft_v2_0_23 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_tft_v2_0_23 +displayport_v7_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/displayport_v7_0_0 +zynq_ultra_ps_e_vip_v1_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/zynq_ultra_ps_e_vip_v1_0_8 +etrnic_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/etrnic_v1_0_4 +viterbi_v9_1_12 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/viterbi_v9_1_12 +axi_dma_v7_1_23 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_dma_v7_1_23 +tcc_decoder_3gppmm_v2_0_20 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tcc_decoder_3gppmm_v2_0_20 +canfd_v2_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/canfd_v2_0_4 +tri_mode_ethernet_mac_v9_0_17 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tri_mode_ethernet_mac_v9_0_17 +ernic_v2_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ernic_v2_0_0 +shell_utils_addr_remap_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/shell_utils_addr_remap_v1_0_1 +tmr_sem_v1_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tmr_sem_v1_0_16 +xbip_dsp48_acc_v3_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_dsp48_acc_v3_0_6 +xbip_accum_v3_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_accum_v3_0_6 +c_accum_v12_0_14 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/c_accum_v12_0_14 +ernic_v3_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ernic_v3_0_0 +interrupt_control_v3_1_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/interrupt_control_v3_1_4 +axi_iic_v2_0_25 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_iic_v2_0_25 +axis_broadcaster_v1_1_21 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_broadcaster_v1_1_21 +canfd_v3_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/canfd_v3_0_1 +axi_mcdma_v1_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_mcdma_v1_0_8 +axi_hwicap_v3_0_26 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_hwicap_v3_0_26 +xbip_dsp48_multacc_v3_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_dsp48_multacc_v3_0_6 +lte_pucch_receiver_v2_0_18 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lte_pucch_receiver_v2_0_18 +dbg_intf = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dbg_intf +cpri_v8_11_5 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/cpri_v8_11_5 +ieee802d3_50g_rs_fec_v1_0_14 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ieee802d3_50g_rs_fec_v1_0_14 +spdif_v2_0_23 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/spdif_v2_0_23 +div_gen_v5_1_17 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/div_gen_v5_1_17 +tmr_comparator_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tmr_comparator_v1_0_4 +g709_fec_v2_4_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/g709_fec_v2_4_2 +axis_combiner_v1_1_20 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_combiner_v1_1_20 +rs_encoder_v9_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/rs_encoder_v9_0_16 +axi_quad_spi_v3_2_21 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_quad_spi_v3_2_21 +xfft_v9_0_19 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xfft_v9_0_19 +pr_decoupler_v1_0_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pr_decoupler_v1_0_9 +convolution_v9_0_15 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/convolution_v9_0_15 +qdriv_pl_phy_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/qdriv_pl_phy_v1_0_0 +prc_v1_3_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/prc_v1_3_4 +dfx_decoupler_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dfx_decoupler_v1_0_1 +axi_traffic_gen_v2_0_23 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_traffic_gen_v2_0_23 +xsdbs_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xsdbs_v1_0_2 +tsn_temac_v1_0_5 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tsn_temac_v1_0_5 +axi_mm2s_mapper_v1_1_21 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_mm2s_mapper_v1_1_21 +v_vid_sdi_tx_bridge_v2_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_vid_sdi_tx_bridge_v2_0_0 +axi_epc_v2_0_25 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_epc_v2_0_25 +videoaxi4s_bridge_v1_0_5 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/videoaxi4s_bridge_v1_0_5 +axi_intc_v4_1_15 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_intc_v4_1_15 +axi_mmu_v2_1_20 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_mmu_v2_1_20 +audio_formatter_v1_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/audio_formatter_v1_0_4 +switch_core_top_v1_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/switch_core_top_v1_0_8 +dfx_axi_shutdown_manager_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dfx_axi_shutdown_manager_v1_0_0 +axi_fifo_mm_s_v4_1_19 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_fifo_mm_s_v4_1_19 +axi_vfifo_ctrl_v2_0_24 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_vfifo_ctrl_v2_0_24 +lte_dl_channel_encoder_v4_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lte_dl_channel_encoder_v4_0_2 +srio_gen2_v4_1_9 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/srio_gen2_v4_1_9 +axi_uartlite_v2_0_26 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_uartlite_v2_0_26 +dft_v4_1_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dft_v4_1_1 +axis_vio_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_vio_v1_0_2 +mem_tg_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mem_tg_v1_0_3 +sid_v8_0_15 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sid_v8_0_15 +displayport_v9_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/displayport_v9_0_3 +axi_interconnect_v1_7_18 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_interconnect_v1_7_18 +axi_firewall_v1_1_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_firewall_v1_1_1 +vby1hs_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/vby1hs_v1_0_0 +rs_decoder_v9_0_17 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/rs_decoder_v9_0_17 +v_hdmi_rx1_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/v_hdmi_rx1_v1_0_0 +ieee802d3_rs_fec_v2_0_10 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ieee802d3_rs_fec_v2_0_10 +ieee802d3_200g_rs_fec_v2_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ieee802d3_200g_rs_fec_v2_0_0 +ba317 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ba317 +axi_traffic_gen_v3_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_traffic_gen_v3_0_8 +soft_ecc_proxy_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/soft_ecc_proxy_v1_0_0 +axi_gpio_v2_0_24 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_gpio_v2_0_24 +dfx_bitstream_monitor_v1_0_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dfx_bitstream_monitor_v1_0_0 +axi_hbicap_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_hbicap_v1_0_3 +duc_ddc_compiler_v3_0_15 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/duc_ddc_compiler_v3_0_15 +axi_sideband_util_v1_0_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_sideband_util_v1_0_6 +lte_ul_channel_decoder_v4_0_17 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lte_ul_channel_decoder_v4_0_17 +cic_compiler_v4_0_15 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/cic_compiler_v4_0_15 +dsp_macro_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dsp_macro_v1_0_1 +axi_protocol_checker_v2_0_8 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_protocol_checker_v2_0_8 +can_v5_0_25 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/can_v5_0_25 +axi_bram_ctrl_v4_0_14 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_bram_ctrl_v4_0_14 +flexo_100g_rs_fec_v1_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/flexo_100g_rs_fec_v1_0_16 +axi_mcdma_v1_1_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_mcdma_v1_1_3 +axi_clock_converter_v2_1_21 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_clock_converter_v2_1_21 +axi_fifo_mm_s_v4_2_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_fifo_mm_s_v4_2_4 +xbip_dsp48_macro_v3_0_18 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/xbip_dsp48_macro_v3_0_18 +axi_dwidth_converter_v2_1_22 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_dwidth_converter_v2_1_22 +lte_3gpp_mimo_encoder_v4_0_15 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lte_3gpp_mimo_encoder_v4_0_15 +lte_3gpp_mimo_decoder_v3_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lte_3gpp_mimo_decoder_v3_0_16 +iomodule_v3_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/iomodule_v3_0 +lmb_bram_if_cntlr_v4_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lmb_bram_if_cntlr_v4_0 +lmb_v10_v3_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/lmb_v10_v3_0 +axi_lite_ipif_v3_0 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_lite_ipif_v3_0 +mdm_v3_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mdm_v3_2 +microblaze_mcs_v2_3_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/microblaze_mcs_v2_3_6 +tcc_encoder_3gpp_v5_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/tcc_encoder_3gpp_v5_0_16 +axi_usb2_device_v5_0_23 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_usb2_device_v5_0_23 +axi_pcie_v2_9_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_pcie_v2_9_4 +dft_v4_2_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dft_v4_2_1 +axi_ethernet_buffer_v2_0_23 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_ethernet_buffer_v2_0_23 +axis_data_fifo_v2_0_4 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_data_fifo_v2_0_4 +etrnic_v1_1_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/etrnic_v1_1_3 +axis_clock_converter_v1_1_23 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axis_clock_converter_v1_1_23 +fc32_rs_fec_v1_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/fc32_rs_fec_v1_0_16 +cordic_v6_0_16 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/cordic_v6_0_16 +mailbox_v2_1_14 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/mailbox_v2_1_14 +dfx_controller_v1_0_1 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/dfx_controller_v1_0_1 +axi_memory_init_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_memory_init_v1_0_3 +pr_axi_shutdown_manager_v1_0_2 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/pr_axi_shutdown_manager_v1_0_2 +ieee802d3_rs_fec_v1_0_18 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ieee802d3_rs_fec_v1_0_18 +sd_fec_v1_1_6 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/sd_fec_v1_1_6 +axi_timer_v2_0_24 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_timer_v2_0_24 +ieee802d3_200g_rs_fec_v1_0_11 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ieee802d3_200g_rs_fec_v1_0_11 +axi_vdma_v6_3_10 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/axi_vdma_v6_3_10 +g975_efec_i7_v2_0_18 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/g975_efec_i7_v2_0_18 +ats_switch_v1_0_3 = /home/kanellok/majd/DRAM-Bender/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa/ats_switch_v1_0_3 +xil_defaultlib = questa_lib/msim/xil_defaultlib +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset " syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = [,]{:[,]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. +; Sc22Mode = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Override all PA VOPT and VSIM commands to run simulation in Non-PA mode. +; NonPAmode = 1 + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = fs + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = [ ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = /bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for automatically checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver. If the solver attempts to resize a dynamic array or queue +; to a size greater than the specified limit, the solver will abort with an error. +; The default value is 10000. The maximum value is 10000000. A value of 0 is +; equivalent to specifying the maximum value. +; SolveArrayResizeMax = 10000 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveBeforeErrorSeverity = 3 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveEngineErrorSeverity = 3 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate any randset exceeds the specified timeout. +; The default value is 500. A value of 0 will disable timeout failures. +; SolveTimeout = 500 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; SolveReplayOpt=[+|-][,[+|-]]*" +' Valid settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=validate + +; Switch to specify options that control the behavior of the solver profiler.. +; Valid options are: +; cputime - use CPU time instead of elapsed time (wall time) to measure performance data (default is off) +; randsets - enable detailed profiling of randsets (default is off) +; testgen - generate testcases for profiled randsets (only when randsets option is enabled) (default is off) +; SolverFProf = [+|-]