From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../ip/scratchpad/scratchpad_stub.v | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.v (limited to 'projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.v') diff --git a/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.v b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.v new file mode 100644 index 0000000..9db516d --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:28:30 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad_stub.v +// Design : scratchpad +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module scratchpad(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[31:0],douta[31:0]" */; + input clka; + input ena; + input [0:0]wea; + input [9:0]addra; + input [31:0]dina; + output [31:0]douta; +endmodule -- cgit v1.2.3