From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../sim_scripts/rdback_fifo/modelsim/README.txt | 49 ++++++ .../sim_scripts/rdback_fifo/modelsim/compile.do | 47 ++++++ .../sim_scripts/rdback_fifo/modelsim/file_info.txt | 18 +++ .../sim_scripts/rdback_fifo/modelsim/glbl.v | 84 +++++++++++ .../rdback_fifo/modelsim/rdback_fifo.sh | 167 +++++++++++++++++++++ .../rdback_fifo/modelsim/rdback_fifo.udo | 0 .../sim_scripts/rdback_fifo/modelsim/simulate.do | 16 ++ .../sim_scripts/rdback_fifo/modelsim/wave.do | 2 + 8 files changed, 383 insertions(+) create mode 100644 projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt create mode 100644 projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do create mode 100644 projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt create mode 100644 projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v create mode 100755 projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh create mode 100644 projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.udo create mode 100644 projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do create mode 100644 projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do (limited to 'projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim') diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt new file mode 100644 index 0000000..6aedcac --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do new file mode 100644 index 0000000..2a07e86 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do @@ -0,0 +1,47 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/fifo_generator_v13_2_5 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap fifo_generator_v13_2_5 modelsim_lib/msim/fifo_generator_v13_2_5 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_5 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_5 -64 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_5 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt new file mode 100644 index 0000000..b3bd811 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt @@ -0,0 +1,18 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh new file mode 100755 index 0000000..8596a31 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.udo b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.udo new file mode 100644 index 0000000..e69de29 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do new file mode 100644 index 0000000..13d9d23 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.rdback_fifo xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {rdback_fifo.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR -- cgit v1.2.3