From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../sim_scripts/scratchpad/riviera/compile.do | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/compile.do (limited to 'projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/compile.do') diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/compile.do new file mode 100644 index 0000000..ffa5c78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + -- cgit v1.2.3