From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci | 500 +++++++++++++++++++++ 1 file changed, 500 insertions(+) create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci (limited to 'projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci') diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci new file mode 100644 index 0000000..f857867 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci @@ -0,0 +1,500 @@ + + + xilinx.com + xci + unknown + 1.0 + + + phy_ddr4 + + + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 32 + 576 + 72 + X0Y11 + X0Y10 + X0Y70 + X0Y11 + 0 + 0 + DDR4_SDRAM + 18 + 0 + true + 34 + 512 + 4 + 2 + 2 + 0 + 0 + 0 + 1 + 1 + 0 + 5 + 3333 + 9 + 0 + VCO + 10 + 16Gb + 32 + 1 + 0 + 0 + 4 + 0 + 0 + 938 + 1 + 9 + 18 + 72 + false + 0 + 1.2V + true + No + 1600 + 0 + 0 + 64GB + RDIMMs + 4 + 64GB + 16 + 16384 + 72 + 34359738368 + 833 + + 0 + 0 + ROW_COLUMN_BANK + 1 + 0 + 1 + 18 + 0 + 0 + 83 + 1 + 1 + 166500000 + 1 + 0 + 0.84 + 0 + 4 + 1 + 5 + 1500 + 0 + 9 + 16 + 2 + 22 + 10 + 5200 + 234 + 74 + 10 + + 4 + 3 + 4 + 5 + 10 + + 5 + 2 + 60 + 128 + 0 + 256 + DDR4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + FALSE + 3333 + 0 + 15 + 0 + 0 + 0 + 0 + CustomPart_Address__width 18$CustomPart_Bank__group__width 2$CustomPart_Bank__width 2$CustomPart_CA__Mirror 0$CustomPart_CKE__width 1$CustomPart_CK__width 1$CustomPart_CS__width 1$CustomPart_Column__width 10$CustomPart_Component__density 16Gb$CustomPart_Data__bits__per__strobe 4$CustomPart_Data__mask 0$CustomPart_Data__widths 72$CustomPart_IO__Voltages 1.2V$CustomPart_Max__period 1600$CustomPart_Memory__component__width 4$CustomPart_Memory__density 64GB$CustomPart_Memory__device__width 72$Custom +Part_Memory__speed__grade 83$CustomPart_Min__period 833$CustomPart_ODT__width 1$CustomPart_Part__name 64GB$CustomPart_Part__type RDIMMs$CustomPart_Rank 1$CustomPart_Row__width 18$CustomPart_StackHeight 1$CustomPart_burst__length 8$CustomPart_cas__latency 24$CustomPart_cas__write__latency 22$CustomPart_tCCD_3ds 5 tck$CustomPart_tCKE 5000 ps$CustomPart_tFAW 13000 ps$CustomPart_tFAW_dlr 16 tck$CustomPart_tMRD 8 tck$CustomPart_tRAS 32000 ps$CustomPart_tRCD 14160 ps$CustomPart_tREFI 7800000 ps$Custom +Part_tRFC 350000 ps$CustomPart_tRFC_dlr 110000 ps$CustomPart_tRP 14160 ps$CustomPart_tRRD_L 4900 ps$CustomPart_tRRD_S 3300 ps$CustomPart_tRRD_dlr 4 tck$CustomPart_tRTP 7500 ps$CustomPart_tWR 15000 ps$CustomPart_tWTR_L 7500 ps$CustomPart_tWTR_S 2500 ps$CustomPart_tXPR 360 ns$CustomPart_tZQCS 128 tck$CustomPart_tZQINIT 1024 tck$ + Disable + 1 + 100 + 0 + 0.0 + 0 + 0.0 + 0 + 0.0 + 0 + 1 + BFM + Differential + 100 + None + None + None + 0 + 18 + 2 + 1 + 1 + 1 + DDR4_SDRAM + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + true + false + 34 + RD_PRI_REG + 512 + 4 + false + false + 0 + 0 + 0 + 0 + 8 + Sequential + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 5 + 9 + 0 + 0 + 0 + 0 + 512 + 16 + 14 + true + false + ../../../../custom_parts_ddr4_2016_4_and_above.csv + 1 + NONE + 72 + true + false + false + 3333 + 0 + 0 + false + ROW_COLUMN_BANK + MainMemory + 64GB + RDIMMs + 1.2V + 0 + 0 + 0 + 0 + RZQ/6 + Normal + RZQ/7 + 0 + 4:1 + false + false + false + Single + false + 0 + 0 + 0 + 0 + 1500 + false + false + true + 0 + 0 + 0 + 5 + 1 + false + 1 + 1 + Custom + Custom + false + phy_ddr4 + false + false + Disable + false + false + true + SIMPLE_TG + OFF + false + 1 + false + 1 + false + 1 + Phy_Only_Single + false + Custom + Differential + false + BFM + Differential + false + false + false + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 10 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.2.3