From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml | 8749 ++++++++++++++++++++ 1 file changed, 8749 insertions(+) create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml (limited to 'projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml') diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml new file mode 100644 index 0000000..5bcc81b --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml @@ -0,0 +1,8749 @@ + + + xilinx.com + customized_ip + phy_ddr4 + 1.0 + + + C0_SYS_CLK + + + + true + + + + CLK_N + + + c0_sys_clk_n + + + + + CLK_P + + + c0_sys_clk_p + + + + + + BOARD.ASSOCIATED_PARAM + C0_CLOCK_BOARD_INTERFACE + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + true + + 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MIRROR + 0 + + + C0.DDR4_IS_CUSTOM + IS CUSTOM + true + + + C0.DDR4_AUTO_AP_COL_A3 + AUTO AP COL A3 + true + + + C0.DDR4_MCS_ECC + MCS ECC + 0 + + + C0.DDR4_Slot + Slot Type + 1 + + + C0.APP_DATA_WIDTH + APP Data Width + 576 + + + C0.APP_MASK_WIDTH + APP Mask Width + 72 + + + C0.DDR4_StackHeight + 1 + + + CUSTOM_PART_ATTRIBUTES + custom_part_attributes + CustomPart_Address__width 18$CustomPart_Bank__group__width 2$CustomPart_Bank__width 2$CustomPart_CA__Mirror 0$CustomPart_CKE__width 1$CustomPart_CK__width 1$CustomPart_CS__width 1$CustomPart_Column__width 10$CustomPart_Component__density 16Gb$CustomPart_Data__bits__per__strobe 4$CustomPart_Data__mask 0$CustomPart_Data__widths 72$CustomPart_IO__Voltages 1.2V$CustomPart_Max__period 1600$CustomPart_Memory__component__width 4$CustomPart_Memory__density 64GB$CustomPart_Memory__device__width 72$Custom +Part_Memory__speed__grade 83$CustomPart_Min__period 833$CustomPart_ODT__width 1$CustomPart_Part__name 64GB$CustomPart_Part__type RDIMMs$CustomPart_Rank 1$CustomPart_Row__width 18$CustomPart_StackHeight 1$CustomPart_burst__length 8$CustomPart_cas__latency 24$CustomPart_cas__write__latency 22$CustomPart_tCCD_3ds 5 tck$CustomPart_tCKE 5000 ps$CustomPart_tFAW 13000 ps$CustomPart_tFAW_dlr 16 tck$CustomPart_tMRD 8 tck$CustomPart_tRAS 32000 ps$CustomPart_tRCD 14160 ps$CustomPart_tREFI 7800000 ps$Custom +Part_tRFC 350000 ps$CustomPart_tRFC_dlr 110000 ps$CustomPart_tRP 14160 ps$CustomPart_tRRD_L 4900 ps$CustomPart_tRRD_S 3300 ps$CustomPart_tRRD_dlr 4 tck$CustomPart_tRTP 7500 ps$CustomPart_tWR 15000 ps$CustomPart_tWTR_L 7500 ps$CustomPart_tWTR_S 2500 ps$CustomPart_tXPR 360 ns$CustomPart_tZQCS 128 tck$CustomPart_tZQINIT 1024 tck$ + + + M_ADDN_UI_CLKOUT1_FREQ_HZ + CLKOUT1 FREQ HZ + 100 + + + M_ADDN_UI_CLKOUT2_FREQ_HZ + CLKOUT2 FREQ HZ + 0.0 + + + M_ADDN_UI_CLKOUT3_FREQ_HZ + CLKOUT3 FREQ HZ + 0.0 + + + M_ADDN_UI_CLKOUT4_FREQ_HZ + CLKOUT4 FREQ HZ + 0.0 + + + M_ADDN_UI_CLKOUT1_PHASE + CLKOUT1 PHASE + 0 + + + M_ADDN_UI_CLKOUT2_PHASE + CLKOUT2 PHASE + 0 + + + M_ADDN_UI_CLKOUT3_PHASE + CLKOUT3 PHASE + 0 + + + M_ADDN_UI_CLKOUT4_PHASE + CLKOUT4 PHASE + 0 + + + CLKOUT0_DIVIDE + CLKOUT0 DIVIDE + 0 + + + CLKOUT1_DIVIDE + CLKOUT1 DIVIDE + 15 + + + CLKOUT2_DIVIDE + CLKOUT2 DIVIDE + 0 + + + CLKOUT3_DIVIDE + CLKOUT3 DIVIDE + 0 + + + CLKOUT4_DIVIDE + CLKOUT4 DIVIDE + 0 + + + CLKOUT6_DIVIDE + CLKOUT6 DIVIDE + 0 + + + Debug_Signal + Disable + + + Simulation_Mode + Simulation Mode + BFM + + + C0.DDR4_Ecc + false + + + simulation.tlm + + + + + + + + choice_list_09ec3310 + Single + Dual + + + choice_list_157065e4 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + 30 + 31 + 32 + + + choice_list_266493f0 + DDR4_SDRAM + + + choice_list_28391b73 + 1.2V + + + choice_list_29a21725 + Custom + default_300mhz_clk0 + default_300mhz_clk1 + default_300mhz_clk2 + default_300mhz_clk3 + + + choice_list_2b96b8de + Differential + No_Buffer + + + choice_list_301b19dd + ON + OFF + + + choice_list_30636008 + 4:1 + + + choice_list_30de7c39 + Custom + pcie_perstn + resetn + + + choice_list_34c5244e + Components + UDIMMs + SODIMMs + RDIMMs + LRDIMMs + + + choice_list_3d7b6424 + 500 + 375 + 300 + 250 + 214 + 188 + 167 + 150 + 136 + 125 + 115 + 107 + 100 + 94 + 88 + 83 + 79 + 75 + 71 + 68 + 65 + 63 + 60 + 58 + 56 + 54 + 52 + 50 + 48 + 47 + 45 + 44 + 43 + 42 + 41 + 39 + 38 + 37 + 36 + 35 + 34 + 33 + 32 + 31 + 30 + 29 + 28 + 27 + 26 + 25 + 24 + 23 + 22 + 21 + 20 + 19 + 18 + 17 + 16 + 15 + 14 + 13 + 12 + None + + + choice_list_4665eb01 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_list_4bba4966 + 22 + + + choice_list_4e3dbc0a + SIMPLE_TG + ADVANCED_TG + + + choice_list_66456a11 + Custom + ddr4_sdram_c0 + ddr4_sdram_c1 + ddr4_sdram_c2 + ddr4_sdram_c3 + + + choice_list_67b045e5 + BFM + Unisim + + + choice_list_687ca1a5 + None + 500 + 375 + 300 + 250 + 214 + 188 + 167 + 150 + 136 + 125 + 115 + 107 + 100 + 94 + 88 + 83 + 79 + 75 + 71 + 68 + 65 + 63 + 60 + 58 + 56 + 54 + 52 + 50 + 48 + 47 + 45 + 44 + 43 + 42 + 41 + 39 + 38 + 37 + 36 + 35 + 34 + 33 + 32 + 31 + 30 + 29 + 28 + 27 + 26 + 25 + 24 + 23 + 22 + 21 + 20 + 19 + 18 + 17 + 16 + 15 + 14 + 13 + 12 + + + choice_list_87b2b38f + 24 + + + choice_list_8b4f223f + Strict + Normal + + + choice_list_98f5c8fa + RZQ/6 + + + choice_list_a187d5e4 + 512 + 1024 + + + choice_list_ad101c66 + RZQ/7 + RZQ/6 + + + choice_list_c89503c8 + ROW_BANK_COLUMN + BANK_ROW_COLUMN + ROW_COLUMN_BANK + ROW_COLUMN_BANK_INTLV + + + choice_list_c8951bc1 + NONE + + + choice_list_d1ecf361 + MTA18ASF1G72PDZ-2G1 + MTA9ASF51272PZ-2G1 + MTA18ASF2G72PDZ-2G3 + MTA9ASF1G72PZ-2G3 + M393A1G43DB1-CRC + MTA9ASF51272PZ-2G3 + DDR4_CUSTOM3 + DDR4_CUSTOM4 + MTA18ADF1G72PZ-2G1 + MTA18ASF1G72PZ-2G1 + MTA36ASF2G72PZ-2G1 + MTA18ASF2G72PZ-2G9 + MTA18ASF2G72PZ-2G3 + MTA36ASF4G72PZ-2G3 + M393A2G40DB1-CRC + M393A8K40B21-CTC + M393AAK40B41-CTC + M393A2K40BB1-CRC + DDR4_CUSTOM5 + 64GB + + + choice_list_d6556846 + 32 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xilinx_elaboratesubcores_view_fileset + + ip_0/phy_ddr4_microblaze_mcs.xci + xci + + + ip_0/phy_ddr4_microblaze_mcs.xml + xml + + + ip_1/phy_ddr4_phy.xci + xci + + + ip_1/phy_ddr4_phy.xml + xml + + + + + + phy_ddr4 + + + + instance_path + inst/u_ddr_cal_riu/mcs0/inst/microblaze_I + + + bootloop_file + sw/calibration_0/Debug/calibration_ddr.elf + + + endian + little + + + processor_type + MICROBLAZE-LE + + + is_visible + false + + + + + DDR4 Interface Generator for Ultrascale Architecture + + + C0.ControllerType + DDR4_SDRAM + + + + false + + + + + + IOPowerReduction + OFF + + + Enable_SysPorts + Auto assign static ports + true + + + Phy_Only + Phy_Only_Single + + + RESET_BOARD_INTERFACE + Custom + + + + true + + + + + + C0_CLOCK_BOARD_INTERFACE + Custom + + + + true + + + + + + IS_FROM_PHY + 1 + + + RECONFIG_XSDB_SAVE_RESTORE + false + + + AL_SEL + 0 + + + Example_TG + SIMPLE_TG + + + + false + + + + + + C0.DDR4_Clamshell + false + + + + false + + + + + + C0.MIGRATION + false + + + TIMING_OP1 + false + + + TIMING_OP2 + false + + + TIMING_3DS + false + + + SET_DW_TO_40 + false + + + DIFF_TERM_SYSCLK + false + + + C0_DDR4_BOARD_INTERFACE + Custom + + + + true + + + + + + C0.DDR4_TimePeriod + 1500 + + + C0.DDR4_InputClockPeriod + 3333 + + + C0.DDR4_Specify_MandD + false + + + C0.DDR4_CLKFBOUT_MULT + 5 + + + + false + + + + + + C0.DDR4_DIVCLK_DIVIDE + 1 + + + + false + + + + + + C0.DDR4_CLKOUT0_DIVIDE + 9 + + + + false + + + + + + C0.DDR4_PhyClockRatio + 4:1 + + + C0.DDR4_MemoryType + RDIMMs + + + C0.DDR4_MemoryPart + 64GB + + + C0.DDR4_Slot + Single + + + C0.DDR4_MemoryVoltage + 1.2V + + + C0.DDR4_DataWidth + 72 + + + C0.DDR4_DataMask + NONE + + + + false + + + + + + C0.DDR4_Ecc + false + + + + false + + + + + + C0.DDR4_MCS_ECC + false + + + C0.DDR4_AxiSelection + false + + + + false + + + + + + C0.DDR4_AUTO_AP_COL_A3 + true + + + C0.DDR4_Ordering + Normal + + + C0.DDR4_BurstLength + 8 + + + + false + + + + + + C0.DDR4_BurstType + Sequential + + + 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C0.BANK_GROUP_WIDTH + BANK GROUP WIDTH + 2 + + + C0.LR_WIDTH + LR WIDTH + 1 + + + C0.CK_WIDTH + CK WIDTH + 1 + + + C0.CKE_WIDTH + CKE WIDTH + 1 + + + C0.CS_WIDTH + CS WIDTH + 1 + + + C0.ODT_WIDTH + ODT WIDTH + 1 + + + C0.StackHeight + 1 + + + PING_PONG_PHY + Ping Pong Phy + 1 + + + C0.DDR4_Enable_LVAUX + false + + + C0.DDR4_EN_PARITY + true + + + EN_PP_4R_MIR + false + + + + + DDR4 SDRAM (MIG) + + xtlm + protobuf + sim_ddr_v1_0 + + 10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + -- cgit v1.2.3