From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../axis_clock_converter/axis_clock_converter.xci | 120 + .../axis_clock_converter/axis_clock_converter.xml | 1514 + .../axis_clock_converter.xci | 133 + .../axis_clock_converter.xml | 1478 + .../sources_1/ip/instr_blk_mem/instr_blk_mem.xci | 327 + .../sources_1/ip/instr_blk_mem/instr_blk_mem.xml | 4182 ++ .../ip/instr_blk_mem_sim/instr_blk_mem_sim.xci | 330 + .../ip/instr_blk_mem_sim/instr_blk_mem_sim.xml | 4185 ++ .../sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd | 513 + .../sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml | 100 + .../ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v | 173 + .../bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci | 1032 + .../bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xml | 27445 +++++++++ .../ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xci | 96 + .../ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xml | 691 + .../bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xci | 309 + .../bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xml | 8812 +++ .../ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci | 159 + .../ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xml | 3532 ++ .../ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xci | 165 + .../ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xml | 3536 ++ .../phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci | 189 + .../phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml | 4011 ++ .../phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci | 189 + .../phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xml | 4011 ++ .../phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci | 298 + .../phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml | 4151 ++ .../bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci | 189 + .../bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xml | 4011 ++ .../bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci | 189 + .../bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xml | 4011 ++ .../bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci | 298 + .../bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xml | 4151 ++ .../ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci | 172 + .../ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml | 2235 + .../sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci | 667 + .../sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xml | 4899 ++ .../U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci | 500 + .../U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml | 8749 +++ .../phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig | 313 + .../ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej | 124 + .../ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv.rej | 31 + .../sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd | 513 + .../sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml | 100 + .../ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v | 173 + .../bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci | 1032 + .../bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xml | 27445 +++++++++ .../bd_0/ip/ip_1/bd_ba6a_rst_0_0.xci | 96 + .../bd_0/ip/ip_1/bd_ba6a_rst_0_0.xml | 691 + .../bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xci | 309 + .../bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml | 8812 +++ .../phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xci | 159 + .../phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xml | 3532 ++ .../phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xci | 165 + .../phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xml | 3536 ++ .../bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xci | 189 + .../bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xml | 4011 ++ .../bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xci | 189 + .../bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xml | 4011 ++ .../bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xci | 298 + .../bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xml | 4151 ++ .../bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci | 189 + .../bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xml | 4011 ++ .../bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xci | 189 + .../bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xml | 4011 ++ .../bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xci | 298 + .../bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xml | 4151 ++ .../ip_0/phy_ddr4_udimm_microblaze_mcs.xci | 172 + .../ip_0/phy_ddr4_udimm_microblaze_mcs.xml | 2227 + .../ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xci | 665 + .../ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xml | 4890 ++ .../sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xci | 474 + .../sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xml | 8655 +++ .../rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig | 313 + .../rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej | 124 + .../rtl/cal/ddr4_v2_2_cal_write.sv.rej | 31 + .../sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bd | 513 + .../ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bxml | 100 + .../phy_rdimm_x8_dual/bd_0/hdl/bd_afa8_wrapper.v | 173 + .../bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xci | 1032 + .../bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xml | 27445 +++++++++ .../bd_0/ip/ip_1/bd_afa8_rst_0_0.xci | 96 + .../bd_0/ip/ip_1/bd_afa8_rst_0_0.xml | 691 + .../bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xci | 309 + .../bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xml | 8812 +++ .../bd_0/ip/ip_2/bd_afa8_ilmb_0.xci | 159 + .../bd_0/ip/ip_2/bd_afa8_ilmb_0.xml | 3532 ++ .../bd_0/ip/ip_3/bd_afa8_dlmb_0.xci | 165 + .../bd_0/ip/ip_3/bd_afa8_dlmb_0.xml | 3536 ++ .../bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xci | 189 + .../bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xml | 4011 ++ .../bd_0/ip/ip_5/bd_afa8_ilmb_cntlr_0.xci | 189 + .../bd_0/ip/ip_5/bd_afa8_ilmb_cntlr_0.xml | 4011 ++ .../bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xci | 298 + .../bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xml | 4151 ++ .../bd_0/ip/ip_7/bd_afa8_second_dlmb_cntlr_0.xci | 189 + .../bd_0/ip/ip_7/bd_afa8_second_dlmb_cntlr_0.xml | 4011 ++ .../bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xci | 189 + .../bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xml | 4011 ++ .../bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xci | 298 + .../bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xml | 4151 ++ .../ip_0/phy_rdimm_x8_dual_microblaze_mcs.xci | 172 + .../ip_0/phy_rdimm_x8_dual_microblaze_mcs.xml | 2227 + .../ip_1/phy_rdimm_x8_dual_phy.xci | 665 + .../ip_1/phy_rdimm_x8_dual_phy.xml | 4897 ++ .../ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.xci | 478 + .../ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.xml | 8686 +++ .../rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig | 313 + .../rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej | 124 + .../rtl/cal/ddr4_v2_2_cal_write.sv.rej | 31 + .../sources_1/ip/pr_read_mem/pr_read_mem.xci | 329 + .../sources_1/ip/pr_read_mem/pr_read_mem.xml | 4182 ++ .../sources_1/ip/pr_ref_mem/pr_ref_mem.xci | 330 + .../sources_1/ip/pr_ref_mem/pr_ref_mem.xml | 4185 ++ .../sources_1/ip/rdback_fifo/rdback_fifo.xci | 580 + .../sources_1/ip/rdback_fifo/rdback_fifo.xml | 10791 ++++ .../sources_1/ip/scratchpad/scratchpad.xci | 327 + .../sources_1/ip/scratchpad/scratchpad.xml | 4182 ++ .../ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xci | 1433 + .../ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xml | 22837 +++++++ .../sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xci | 1508 + .../sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml | 28293 +++++++++ .../ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci | 328 + .../ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xml | 4188 ++ .../xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci | 328 + .../xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xml | 4188 ++ projects/U200/U200.srcs/sources_1/ip/xdma/xdma.xci | 2283 + projects/U200/U200.srcs/sources_1/ip/xdma/xdma.xml | 60383 +++++++++++++++++++ .../sources_1/ip/zq_calib_mem/zq_calib_mem.xci | 330 + .../sources_1/ip/zq_calib_mem/zq_calib_mem.xml | 4185 ++ 130 files changed, 437076 insertions(+) create mode 100644 projects/U200/U200.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv.rej create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xml create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xci create mode 100644 projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xml create mode 100644 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+ . + + . + 2019.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml new file mode 100644 index 0000000..f22c124 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml @@ -0,0 +1,1514 @@ + + + xilinx.com + customized_ip + axis_clock_converter + 1.0 + + + S_AXIS + S_AXIS + + + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TDATA + + + s_axis_tdata + + + + + TSTRB + + + s_axis_tstrb + + + + + TKEEP + + + s_axis_tkeep + + + + + TLAST + + + s_axis_tlast + + + + + TID + + + s_axis_tid + + + + + TDEST + + + s_axis_tdest + + + + + TUSER + + + s_axis_tuser + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + 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+ + axis_clock_converter_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The AXI4-Stream Clock Converter IP provides the infrastructure to change the clocking rate between a AXI4-Stream master and slave. + + + TDATA_NUM_BYTES + TDATA Width (bytes) + 32 + + + + true + + + + + + TID_WIDTH + TID Width (bits) + 0 + + + + true + + + + + + TDEST_WIDTH + TDEST Width (bits) + 0 + + + + true + + + + + + TUSER_WIDTH + TUSER Width (bits) + 0 + + + + true + + + + + + IS_ACLK_ASYNC + Asynchronous Clocks + 1 + + + + true + + + + + + HAS_TSTRB + Enable TSTRB + 0 + + + + true + + + + + + HAS_TKEEP + Enable TKEEP + 1 + + + + true + + + + + + HAS_TLAST + Enable TLAST + 1 + + + + true + + + + + + SYNCHRONIZATION_STAGES + Synchronization Stages across Cross Clock Domain Logic + 2 + + + + true + + + + + + ACLK_RATIO + SI to MI Clock Ratio + 1:2 + + + + false + + + + + + ACLKEN_CONV_MODE + ACLKEN Conversion Mode + 0 + + + + true + + + + + + Component_Name + axis_clock_converter + + + + + AXI4-Stream Clock Converter + + XPM_CDC + XPM_FIFO + + 21 + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xci b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xci new file mode 100644 index 0000000..76ea065 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xci @@ -0,0 +1,133 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axis_clock_converter + + + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + ACTIVE_LOW + + + + 100000000 + 0 + 0 + 0.000 + 0 + ACTIVE_LOW + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + ACTIVE_LOW + + + + 100000000 + 0 + 0 + 0.000 + 0 + ACTIVE_LOW + 0 + 0b00000000000000000000000000011011 + 256 + 1 + 1 + 1 + virtexuplus + 1 + 2 + 2 + 1 + 0 + 1:2 + axis_clock_converter + 1 + 1 + 0 + 1 + 2 + 32 + 0 + 0 + 0 + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 23 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xml b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xml new file mode 100644 index 0000000..e58898e --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xml @@ -0,0 +1,1478 @@ + + + xilinx.com + customized_ip + axis_clock_converter + 1.0 + + + S_AXIS + S_AXIS + + + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TDATA + + + s_axis_tdata + + + + + TSTRB + + + s_axis_tstrb + + + + + TKEEP + + + s_axis_tkeep + + + + + TLAST + + + s_axis_tlast + + + + + TID + + + s_axis_tid + + + + + TDEST + + + s_axis_tdest + + + + + TUSER + + + s_axis_tuser + + + + + + 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+ + + C_M_AXIS_ACLK_RATIO + 2 + + + C_ACLKEN_CONV_MODE + 0 + + + + + + choice_list_27ecedf0 + 16:1 + 15:1 + 14:1 + 13:1 + 12:1 + 11:1 + 10:1 + 9:1 + 8:1 + 7:1 + 6:1 + 5:1 + 4:1 + 3:1 + 2:1 + 1:1 + 1:2 + 1:3 + 1:4 + 1:5 + 1:6 + 1:7 + 1:8 + 1:9 + 1:10 + 1:11 + 1:12 + 1:13 + 1:14 + 1:15 + 1:16 + + + choice_pairs_37189c7b + 0 + 1 + + + choice_pairs_7e3eb5e2 + 0 + 1 + 2 + 3 + + + The AXI4-Stream Clock Converter IP provides the infrastructure to change the clocking rate between a AXI4-Stream master and slave. + + + TDATA_NUM_BYTES + TDATA Width (bytes) + 32 + + + + true + + + + + + TID_WIDTH + TID Width (bits) + 0 + + + + true + + + + + + TDEST_WIDTH + TDEST Width (bits) + 0 + + + + true + + + + + + TUSER_WIDTH + TUSER Width (bits) + 0 + + + + true + + + + + + IS_ACLK_ASYNC + Asynchronous Clocks + 1 + + + + true + + + + + + HAS_TSTRB + Enable TSTRB + 0 + + + + true + + + + + + HAS_TKEEP + Enable TKEEP + 1 + + + + true + + + + + + HAS_TLAST + Enable TLAST + 1 + + + + true + + + + + + SYNCHRONIZATION_STAGES + Synchronization Stages across Cross Clock Domain Logic + 2 + + + + true + + + + + + ACLK_RATIO + SI to MI Clock Ratio + 1:2 + + + + false + + + + + + ACLKEN_CONV_MODE + ACLKEN Conversion Mode + 0 + + + + true + + + + + + Component_Name + axis_clock_converter + + + + + AXI4-Stream Clock Converter + + XPM_CDC + XPM_FIFO + + 23 + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci b/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci new file mode 100644 index 0000000..83d955e --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci @@ -0,0 +1,327 @@ + + + xilinx.com + xci + unknown + 1.0 + + + instr_blk_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 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+ C_EST_POWER_SUMMARY + Estimated Power for IP : 7.524303 mW + + + + + + choice_list_0e6ad450 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + instr_blk_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + 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Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + instr_blk_mem_sim + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + 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false + + + + true + + + + + + Use_REGCEA_Pin + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Primitives + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Core + false + + + + false + + + + + + Use_REGCEB_Pin + false + + + + false + + + + + + register_porta_input_of_softecc + false + + + + false + + + + + + register_portb_output_of_softecc + false + + + + false + + + + + + Pipeline_Stages + 0 + + + + false + + + + + + Load_Init_File + true + + + + true + + + + + + Coe_File + ../../../../coe/simmem.coe + + + + true + + + + + + Fill_Remaining_Memory_Locations + true + + + + true + + + + + + Remaining_Memory_Locations + 0 + + + + true + + + + + + Use_RSTA_Pin + false + + + + true + + + + + + Reset_Memory_Latch_A + false + + + + false + + + + + + Reset_Priority_A + CE + + + + false + + + + + + Output_Reset_Value_A + 0 + + + + false + + + + + + Use_RSTB_Pin + false + + + + false + + + + + + Reset_Memory_Latch_B + false + + + + false + + + + + + Reset_Priority_B + CE + + + + false + + + + + + Output_Reset_Value_B + 0 + + + + false + + + + + + Reset_Type + SYNC + + + + false + + + + + + Additional_Inputs_for_Power_Estimation + false + + + + true + + + + + + Port_A_Clock + 100 + + + + true + + + + + + Port_A_Write_Rate + 50 + + + + true + + + + + + Port_B_Clock + 0 + + + + true + + + + + + Port_B_Write_Rate + 0 + + + + true + + + + + + Port_A_Enable_Rate + 100 + + + + true + + + + + + Port_B_Enable_Rate + 0 + + + + true + + + + + + Collision_Warnings + ALL + + + + true + + + + + + Disable_Collision_Warnings + false + + + + true + + + + + + Disable_Out_of_Range_Warnings + false + + + + true + + + + + + use_bram_block + Stand_Alone + + + + true + + + + + + MEM_FILE + no_mem_loaded + + + + true + + + + + + CTRL_ECC_ALGO + NONE + + + + true + + + + + + EN_SAFETY_CKT + false + + + + false + + + + + + READ_LATENCY_A + 1 + + + + false + + + + + + READ_LATENCY_B + 1 + + + + false + + + + + + + + Block Memory Generator + + XPM_MEMORY + + 4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd new file mode 100644 index 0000000..f3a1633 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd @@ -0,0 +1,513 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0xBCE55F3980178BC9", + "design_src": "SBD", + "device": "xcu200-fsgd2104-2-e", + "name": "bd_9f2c", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "scoped": "true", + "synth_flow_mode": "None", + "tool_version": "2020.2", + "validated": "true" + }, + "design_tree": { + "microblaze_I": "", + "rst_0": "", + "ilmb": "", + "dlmb": "", + "dlmb_cntlr": "", + "ilmb_cntlr": "", + "lmb_bram_I": "", + "second_dlmb_cntlr": "", + "second_ilmb_cntlr": "", + "second_lmb_bram_I": "", + "iomodule_0": "" + }, + "interface_ports": { + "IO": { + "mode": "Master", + "vlnv": "xilinx.com:interface:mcsio_bus_rtl:1.0" + }, + "TRACE": { + "mode": "Master", + "vlnv": "xilinx.com:interface:mbtrace_rtl:2.0" + } + }, + "ports": { + "Clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_ASYNC_RESET": { + "value": "Reset" + }, + "CLK_DOMAIN": { + "value": "bd_9f2c_Clk", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000", + "value_src": "default" + } + } + }, + "Reset": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_HIGH" + } + } + } + }, + "components": { + "microblaze_I": { + "vlnv": "xilinx.com:ip:microblaze:11.0", + "xci_name": "bd_9f2c_microblaze_I_0", + "parameters": { + "C_ASYNC_WAKEUP": { + "value": "3" + }, + "C_DEBUG_ENABLED": { + "value": "0" + }, + "C_FAULT_TOLERANT": { + "value": "0" + }, + "C_INSTANCE": { + "value": "mb_microblaze_0" + }, + "C_PC_WIDTH": { + "value": "17" + }, + "C_TRACE": { + "value": "1" + }, + "C_USE_BARREL": { + "value": "1" + }, + "C_USE_DIV": { + "value": "1" + }, + "C_USE_EXT_BRK": { + "value": "0" + }, + "C_USE_EXT_NM_BRK": { + "value": "0" + }, + "C_USE_HW_MUL": { + "value": "1" + }, + "C_USE_PCMP_INSTR": { + "value": "1" + }, + "C_USE_REORDER_INSTR": { + "value": "0" + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32" + }, + "Instruction": { + "range": "4G", + "width": "32" + } + } + }, + "interface_ports": { + "DLMB": { + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "ILMB": { + "mode": "Master", + "address_space_ref": "Instruction", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + } + }, + "hdl_attributes": { + "BMM_INFO_PROCESSOR": { + "value": "microblaze-le > bd_9f2c dlmb_cntlr", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "rst_0": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "bd_9f2c_rst_0_0" + }, + "ilmb": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "bd_9f2c_ilmb_0", + "parameters": { + "C_LMB_NUM_SLAVES": { + "value": "2" + } + }, + "interface_ports": { + "LMB_M": { + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0", + "LMB_Sl_1" + ] + } + } + }, + "dlmb": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "bd_9f2c_dlmb_0", + "parameters": { + "C_LMB_NUM_SLAVES": { + "value": "3" + } + }, + "interface_ports": { + "LMB_M": { + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0", + "LMB_Sl_1", + "LMB_Sl_2" + ] + } + } + }, + "dlmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_9f2c_dlmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000000000" + }, + "C_HIGHADDR": { + "value": "0x000000000000FFFF" + }, + "C_MASK": { + "value": "0x00000000C0010000" + } + }, + "hdl_attributes": { + "BMM_INFO_ADDRESS_SPACE": { + "value": "byte 0x00000000 32 > bd_9f2c lmb_bram_I bd_9f2c second_lmb_bram_I", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "ilmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_9f2c_ilmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000000000" + }, + "C_HIGHADDR": { + "value": "0x000000000000FFFF" + }, + "C_MASK": { + "value": "0x0000000080010000" + } + } + }, + "lmb_bram_I": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "bd_9f2c_lmb_bram_I_0", + "parameters": { + "Memory_Type": { + "value": "True_Dual_Port_RAM" + } + } + }, + "second_dlmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_9f2c_second_dlmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000010000" + }, + "C_HIGHADDR": { + "value": "0x0000000000017FFF" + }, + "C_MASK": { + "value": "0x00000000C0010000" + } + }, + "hdl_attributes": { + "BMM_INFO_ADDRESS_RANGE": { + "value": " ", + "value_src": "default" + } + } + }, + "second_ilmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_9f2c_second_ilmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000010000" + }, + "C_HIGHADDR": { + "value": "0x0000000000017FFF" + }, + "C_MASK": { + "value": "0x0000000080010000" + } + } + }, + "second_lmb_bram_I": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "bd_9f2c_second_lmb_bram_I_0", + "parameters": { + "Memory_Type": { + "value": "True_Dual_Port_RAM" + } + } + }, + "iomodule_0": { + "vlnv": "xilinx.com:ip:iomodule:3.1", + "xci_name": "bd_9f2c_iomodule_0_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000080000000" + }, + "C_HIGHADDR": { + "value": "0x000000008000FFFF" + }, + "C_INSTANCE": { + "value": "iomodule" + }, + "C_INTC_ADDR_WIDTH": { + "value": "17" + }, + "C_INTC_HAS_FAST": { + "value": "1" + }, + "C_INTC_USE_IRQ_OUT": { + "value": "1" + }, + "C_IO_BASEADDR": { + "value": "0x00000000C0000000" + }, + "C_IO_HIGHADDR": { + "value": "0x00000000FFFFFFFF" + }, + "C_IO_MASK": { + "value": "0x00000000C0000000" + }, + "C_MASK": { + "value": "0x00000000C0000000" + }, + "C_USE_IO_BUS": { + "value": "1" + } + } + } + }, + "interface_nets": { + "iomodule_0_IO": { + "interface_ports": [ + "IO", + "iomodule_0/IO_BUS" + ] + }, + "ilmb": { + "interface_ports": [ + "microblaze_I/ILMB", + "ilmb/LMB_M" + ] + }, + "dlmb": { + "interface_ports": [ + "microblaze_I/DLMB", + "dlmb/LMB_M" + ] + }, + "ilmb_sl_0": { + "interface_ports": [ + "ilmb/LMB_Sl_0", + "ilmb_cntlr/SLMB" + ] + }, + "dlmb_sl_0": { + "interface_ports": [ + "dlmb/LMB_Sl_0", + "dlmb_cntlr/SLMB" + ] + }, + "dlmb_sl_1": { + "interface_ports": [ + "dlmb/LMB_Sl_1", + "iomodule_0/SLMB" + ] + }, + "ilmb_port": { + "interface_ports": [ + "ilmb_cntlr/BRAM_PORT", + "lmb_bram_I/BRAM_PORTB" + ] + }, + "dlmb_port": { + "interface_ports": [ + "dlmb_cntlr/BRAM_PORT", + "lmb_bram_I/BRAM_PORTA" + ] + }, + "ilmb_sl_1": { + "interface_ports": [ + "ilmb/LMB_Sl_1", + "second_ilmb_cntlr/SLMB" + ] + }, + "dlmb_sl_2": { + "interface_ports": [ + "dlmb/LMB_Sl_2", + "second_dlmb_cntlr/SLMB" + ] + }, + "ilmb_port_2": { + "interface_ports": [ + "second_ilmb_cntlr/BRAM_PORT", + "second_lmb_bram_I/BRAM_PORTB" + ] + }, + "dlmb_port_2": { + "interface_ports": [ + "second_dlmb_cntlr/BRAM_PORT", + "second_lmb_bram_I/BRAM_PORTA" + ] + }, + "microblaze_I_Trace": { + "interface_ports": [ + "TRACE", + "microblaze_I/TRACE" + ] + } + }, + "nets": { + "Clk2": { + "ports": [ + "Clk", + "microblaze_I/Clk", + "ilmb/LMB_Clk", + "dlmb/LMB_Clk", + "dlmb_cntlr/LMB_Clk", + "ilmb_cntlr/LMB_Clk", + "second_dlmb_cntlr/LMB_Clk", + "second_ilmb_cntlr/LMB_Clk", + "iomodule_0/Clk", + "rst_0/slowest_sync_clk" + ] + }, + "Reset": { + "ports": [ + "Reset", + "rst_0/ext_reset_in" + ] + }, + "MB_Reset": { + "ports": [ + "rst_0/mb_reset", + "microblaze_I/Reset" + ] + }, + "LMB_Rst2": { + "ports": [ + "rst_0/bus_struct_reset", + "ilmb/SYS_Rst", + "dlmb/SYS_Rst", + "ilmb_cntlr/LMB_Rst", + "dlmb_cntlr/LMB_Rst", + "second_ilmb_cntlr/LMB_Rst", + "second_dlmb_cntlr/LMB_Rst" + ] + }, + "IO_Rst": { + "ports": [ + "rst_0/peripheral_reset", + "iomodule_0/Rst" + ] + } + }, + "addressing": { + "/microblaze_I": { + "address_spaces": { + "Data": { + "segments": { + "SEG_dlmb_cntlr_Mem": { + "address_block": "/dlmb_cntlr/SLMB/Mem", + "offset": "0x00000000", + "range": "64K" + }, + "SEG_iomodule_0_IO": { + "address_block": "/iomodule_0/SLMB/IO", + "offset": "0xC0000000", + "range": "1G" + }, + "SEG_iomodule_0_Reg": { + "address_block": "/iomodule_0/SLMB/Reg", + "offset": "0x80000000", + "range": "64K" + }, + "SEG_second_dlmb_cntlr_Mem": { + "address_block": "/second_dlmb_cntlr/SLMB/Mem", + "offset": "0x00010000", + "range": "32K" + } + } + }, + "Instruction": { + "segments": { + "SEG_ilmb_cntlr_Mem": { + "address_block": "/ilmb_cntlr/SLMB/Mem", + "offset": "0x00000000", + "range": "64K" + }, + "SEG_second_ilmb_cntlr_Mem": { + "address_block": "/second_ilmb_cntlr/SLMB/Mem", + "offset": "0x00010000", + "range": "32K" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml new file mode 100644 index 0000000..0462690 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml @@ -0,0 +1,100 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v new file mode 100644 index 0000000..eb836a2 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v @@ -0,0 +1,173 @@ +//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Command: generate_target bd_9f2c_wrapper.bd +//Design : bd_9f2c_wrapper +//Purpose: IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module bd_9f2c_wrapper + (Clk, + IO_addr_strobe, + IO_address, + IO_byte_enable, + IO_read_data, + IO_read_strobe, + IO_ready, + IO_write_data, + IO_write_strobe, + Reset, + TRACE_data_access, + TRACE_data_address, + TRACE_data_byte_enable, + TRACE_data_read, + TRACE_data_write, + TRACE_data_write_value, + TRACE_dcache_hit, + TRACE_dcache_rdy, + TRACE_dcache_read, + TRACE_dcache_req, + TRACE_delay_slot, + TRACE_ex_piperun, + TRACE_exception_kind, + TRACE_exception_taken, + TRACE_icache_hit, + TRACE_icache_rdy, + TRACE_icache_req, + TRACE_instruction, + TRACE_jump_hit, + TRACE_jump_taken, + TRACE_mb_halted, + TRACE_mem_piperun, + TRACE_msr_reg, + TRACE_new_reg_value, + TRACE_of_piperun, + TRACE_pc, + TRACE_pid_reg, + TRACE_reg_addr, + TRACE_reg_write, + TRACE_valid_instr); + input Clk; + output IO_addr_strobe; + output [31:0]IO_address; + output [3:0]IO_byte_enable; + input [31:0]IO_read_data; + output IO_read_strobe; + input IO_ready; + output [31:0]IO_write_data; + output IO_write_strobe; + input Reset; + output TRACE_data_access; + output [0:31]TRACE_data_address; + output [0:3]TRACE_data_byte_enable; + output TRACE_data_read; + output TRACE_data_write; + output [0:31]TRACE_data_write_value; + output TRACE_dcache_hit; + output TRACE_dcache_rdy; + output TRACE_dcache_read; + output TRACE_dcache_req; + output TRACE_delay_slot; + output TRACE_ex_piperun; + output [0:4]TRACE_exception_kind; + output TRACE_exception_taken; + output TRACE_icache_hit; + output TRACE_icache_rdy; + output TRACE_icache_req; + output [0:31]TRACE_instruction; + output TRACE_jump_hit; + output TRACE_jump_taken; + output TRACE_mb_halted; + output TRACE_mem_piperun; + output [0:14]TRACE_msr_reg; + output [0:31]TRACE_new_reg_value; + output TRACE_of_piperun; + output [0:31]TRACE_pc; + output [0:7]TRACE_pid_reg; + output [0:4]TRACE_reg_addr; + output TRACE_reg_write; + output TRACE_valid_instr; + + wire Clk; + wire IO_addr_strobe; + wire [31:0]IO_address; + wire [3:0]IO_byte_enable; + wire [31:0]IO_read_data; + wire IO_read_strobe; + wire IO_ready; + wire [31:0]IO_write_data; + wire IO_write_strobe; + wire Reset; + wire TRACE_data_access; + wire [0:31]TRACE_data_address; + wire [0:3]TRACE_data_byte_enable; + wire TRACE_data_read; + wire TRACE_data_write; + wire [0:31]TRACE_data_write_value; + wire TRACE_dcache_hit; + wire TRACE_dcache_rdy; + wire TRACE_dcache_read; + wire TRACE_dcache_req; + wire TRACE_delay_slot; + wire TRACE_ex_piperun; + wire [0:4]TRACE_exception_kind; + wire TRACE_exception_taken; + wire TRACE_icache_hit; + wire TRACE_icache_rdy; + wire TRACE_icache_req; + wire [0:31]TRACE_instruction; + wire TRACE_jump_hit; + wire TRACE_jump_taken; + wire TRACE_mb_halted; + wire TRACE_mem_piperun; + wire [0:14]TRACE_msr_reg; + wire [0:31]TRACE_new_reg_value; + wire TRACE_of_piperun; + wire [0:31]TRACE_pc; + wire [0:7]TRACE_pid_reg; + wire [0:4]TRACE_reg_addr; + wire TRACE_reg_write; + wire TRACE_valid_instr; + + bd_9f2c bd_9f2c_i + (.Clk(Clk), + .IO_addr_strobe(IO_addr_strobe), + .IO_address(IO_address), + .IO_byte_enable(IO_byte_enable), + .IO_read_data(IO_read_data), + .IO_read_strobe(IO_read_strobe), + .IO_ready(IO_ready), + .IO_write_data(IO_write_data), + .IO_write_strobe(IO_write_strobe), + .Reset(Reset), + .TRACE_data_access(TRACE_data_access), + .TRACE_data_address(TRACE_data_address), + .TRACE_data_byte_enable(TRACE_data_byte_enable), + .TRACE_data_read(TRACE_data_read), + .TRACE_data_write(TRACE_data_write), + .TRACE_data_write_value(TRACE_data_write_value), + .TRACE_dcache_hit(TRACE_dcache_hit), + .TRACE_dcache_rdy(TRACE_dcache_rdy), + .TRACE_dcache_read(TRACE_dcache_read), + .TRACE_dcache_req(TRACE_dcache_req), + .TRACE_delay_slot(TRACE_delay_slot), + .TRACE_ex_piperun(TRACE_ex_piperun), + .TRACE_exception_kind(TRACE_exception_kind), + .TRACE_exception_taken(TRACE_exception_taken), + .TRACE_icache_hit(TRACE_icache_hit), + .TRACE_icache_rdy(TRACE_icache_rdy), + .TRACE_icache_req(TRACE_icache_req), + .TRACE_instruction(TRACE_instruction), + .TRACE_jump_hit(TRACE_jump_hit), + .TRACE_jump_taken(TRACE_jump_taken), + .TRACE_mb_halted(TRACE_mb_halted), + .TRACE_mem_piperun(TRACE_mem_piperun), + .TRACE_msr_reg(TRACE_msr_reg), + .TRACE_new_reg_value(TRACE_new_reg_value), + .TRACE_of_piperun(TRACE_of_piperun), + .TRACE_pc(TRACE_pc), + .TRACE_pid_reg(TRACE_pid_reg), + .TRACE_reg_addr(TRACE_reg_addr), + .TRACE_reg_write(TRACE_reg_write), + .TRACE_valid_instr(TRACE_valid_instr)); +endmodule diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci new file mode 100644 index 0000000..97cfe2b --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci @@ -0,0 +1,1032 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_microblaze_I_0 + + + bd_9f2c_Clk + 100000000 + 0 + 0 + 0.000 + + 30000000 + 0 + 0 + 0.000 + 1 + 32 + 0 + LEVEL_HIGH + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 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Enable Fault Tolerance Support + 0 + + + C_ECC_USE_CE_EXCEPTION + Correctable Error Exception + 0 + + + C_LOCKSTEP_SLAVE + Lockstep Slave + 0 + + + C_LOCKSTEP_MASTER + Lockstep Master + 0 + + + C_ENDIANNESS + 1 + + + C_FAMILY + virtexuplus + + + C_DATA_SIZE + 32 + + + C_LMB_DATA_SIZE + 32 + + + C_INSTR_SIZE + 32 + + + C_IADDR_SIZE + 32 + + + C_PIADDR_SIZE + 32 + + + C_DADDR_SIZE + 32 + + + C_INSTANCE + bd_9f2c_microblaze_I_0 + + + C_AVOID_PRIMITIVES + 0 + + + C_AREA_OPTIMIZED + Select implementation optimization + 0 + + + C_OPTIMIZATION + 0 + + + C_INTERCONNECT + Select Bus Interface + 2 + + + C_BASE_VECTORS + Vector Base Address + 0x0000000000000000 + + + C_M_AXI_DP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_M_AXI_D_BUS_EXCEPTION + Enable Data-side AXI Exception + 0 + + + + true + + + + + + C_M_AXI_IP_THREAD_ID_WIDTH + 1 + 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Reversed Load/Store and Swap Instructions + 0 + + + C_UNALIGNED_EXCEPTIONS + Enable Unaligned Data Exception + 0 + + + C_ILL_OPCODE_EXCEPTION + Enable Illegal Instruction Exception + 0 + + + C_DIV_ZERO_EXCEPTION + Enable Integer Divide Exception + 0 + + + + true + + + + + + C_FPU_EXCEPTION + Enable Floating Point Unit Exceptions + 0 + + + + false + + + + + + C_FSL_LINKS + Number of Stream Links + 0 + + + C_USE_EXTENDED_FSL_INSTR + Enable Additional Stream Instructions + 0 + + + C_FSL_EXCEPTION + Enable Stream Exception + 0 + + + + false + + + + + + C_USE_STACK_PROTECTION + Enable stack protection + 0 + + + + true + + + + + + C_IMPRECISE_EXCEPTIONS + Allow Imprecise Exceptions + 0 + + + C_USE_INTERRUPT + 0 + + + C_USE_EXT_BRK + 0 + + + C_USE_EXT_NM_BRK + 0 + + + C_USE_NON_SECURE + 0 + + + C_USE_MMU + Memory Management + 0 + + + + true + + + + + + C_MMU_DTLB_SIZE + Data Shadow Translation Look-Aside Buffer Size + 4 + + + + false + + + + + + C_MMU_ITLB_SIZE + Instruction Shadow Translation Look-Aside Buffer Size + 2 + + + + false + + + + + + C_MMU_TLB_ACCESS + Enable Access to Memory Management Special Registers + 3 + + + + false + + + + + + C_MMU_ZONES + Number of Memory Protection Zones + 16 + + + + false + + + + + + C_MMU_PRIVILEGED_INSTR + Privileged Instructions + 0 + + + + false + + + + + + C_USE_BRANCH_TARGET_CACHE + Enable Branch Target Cache + 0 + + + + true + + + + + + C_BRANCH_TARGET_CACHE_SIZE + Branch Target Cache Size + 0 + + + + true + + + + + + C_PC_WIDTH + 17 + + + C_PVR + Specifies Processor Version Register + 0 + + + C_PVR_USER1 + Specify USER1 Bits in Processor Version Register + 0x00 + + + C_PVR_USER2 + Specify USER2 Bits in Processor Version Register + 0x00000000 + + + C_DYNAMIC_BUS_SIZING + 0 + + + C_RESET_MSR + Specify Reset Value for Select MSR Bits + 0x00000000 + + + C_OPCODE_0x0_ILLEGAL + Generate Illegal Instruction Exception for NULL Instruction + 0 + + + C_DEBUG_ENABLED + MicroBlaze Debug Module Interface + 0 + + + C_DEBUG_INTERFACE + MicroBlaze Debug Connection + 0 + + + C_NUMBER_OF_PC_BRK + Number of PC Breakpoints + 1 + + + C_NUMBER_OF_RD_ADDR_BRK + Number of Read Address Watchpoints + 0 + + + C_NUMBER_OF_WR_ADDR_BRK + Number of Write Address Watchpoints + 0 + + + C_DEBUG_EVENT_COUNTERS + Number of Performance Monitor Event Counters + 5 + + + C_DEBUG_LATENCY_COUNTERS + Number of Performance Monitor Latency Counters + 1 + + + C_DEBUG_COUNTER_WIDTH + Performance Monitor Counter Width + 32 + + + C_DEBUG_TRACE_SIZE + Trace Buffer Size + 8192 + + + C_DEBUG_EXTERNAL_TRACE + External Trace + 0 + + + C_DEBUG_TRACE_ASYNC_RESET + Use Asynchrnous Reset for External Trace + 0 + + + C_DEBUG_PROFILE_SIZE + Profile Buffer Size + 0 + + + C_INTERRUPT_IS_EDGE + Sense Interrupt on Edge vs. Level + 0 + + + C_EDGE_IS_POSITIVE + Sense Interrupt on Rising vs. Falling Edge + 1 + + + C_ASYNC_INTERRUPT + 1 + + + C_ASYNC_WAKEUP + 3 + + + C_M0_AXIS_DATA_WIDTH + 32 + + + C_S0_AXIS_DATA_WIDTH + 32 + + + C_M1_AXIS_DATA_WIDTH + 32 + + + C_S1_AXIS_DATA_WIDTH + 32 + + + C_M2_AXIS_DATA_WIDTH + 32 + + + C_S2_AXIS_DATA_WIDTH + 32 + + + C_M3_AXIS_DATA_WIDTH + 32 + + + C_S3_AXIS_DATA_WIDTH + 32 + + + C_M4_AXIS_DATA_WIDTH + 32 + + + C_S4_AXIS_DATA_WIDTH + 32 + + + C_M5_AXIS_DATA_WIDTH + 32 + + + C_S5_AXIS_DATA_WIDTH + 32 + + + C_M6_AXIS_DATA_WIDTH + 32 + + + C_S6_AXIS_DATA_WIDTH + 32 + + + C_M7_AXIS_DATA_WIDTH + 32 + + + C_S7_AXIS_DATA_WIDTH + 32 + + + C_M8_AXIS_DATA_WIDTH + 32 + + + C_S8_AXIS_DATA_WIDTH + 32 + + + C_M9_AXIS_DATA_WIDTH + 32 + + + C_S9_AXIS_DATA_WIDTH + 32 + + + C_M10_AXIS_DATA_WIDTH + 32 + + + C_S10_AXIS_DATA_WIDTH + 32 + + + C_M11_AXIS_DATA_WIDTH + 32 + + + C_S11_AXIS_DATA_WIDTH + 32 + + + C_M12_AXIS_DATA_WIDTH + 32 + + + C_S12_AXIS_DATA_WIDTH + 32 + + + C_M13_AXIS_DATA_WIDTH + 32 + + + C_S13_AXIS_DATA_WIDTH + 32 + + + C_M14_AXIS_DATA_WIDTH + 32 + + + C_S14_AXIS_DATA_WIDTH + 32 + + + C_M15_AXIS_DATA_WIDTH + 32 + + + C_S15_AXIS_DATA_WIDTH + 32 + + + C_ICACHE_BASEADDR + Base Address + 0x0000000000000000 + + + C_ICACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + C_USE_ICACHE + Enable Instruction Cache + 0 + + + C_ALLOW_ICACHE_WR + Enable Writes + 1 + + + C_ADDR_TAG_BITS + 17 + + + C_CACHE_BYTE_SIZE + Size in Bytes + 8192 + + + C_ICACHE_LINE_LEN + Line Length + 4 + + + C_ICACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 1 + + + C_ICACHE_STREAMS + Number of Streams + 0 + + + + true + + + + + + C_ICACHE_VICTIMS + Number of Victims + 0 + + + + true + + + + + + C_ICACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + + true + + + + + + C_ICACHE_DATA_WIDTH + Data Width + 0 + + + + true + + + + + + C_M_AXI_IC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_DATA_WIDTH + 32 + + + C_M_AXI_IC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IC_USER_VALUE + 31 + + + + true + + + + + + C_M_AXI_IC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_BUSER_WIDTH + 1 + + + + true + + + + + + C_DCACHE_BASEADDR + Base Address + 0x0000000000000000 + + + C_DCACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + C_USE_DCACHE + Enable Data Cache + 0 + + + C_ALLOW_DCACHE_WR + Enable Writes + 1 + + + C_DCACHE_ADDR_TAG + 17 + + + C_DCACHE_BYTE_SIZE + Size in Bytes + 8192 + + + C_DCACHE_LINE_LEN + Line Length + 4 + + + C_DCACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 1 + + + C_DCACHE_USE_WRITEBACK + Enable Write-back Storage Policy + 0 + + + + true + + + + + + C_DCACHE_VICTIMS + Number of Victims + 0 + + + + false + + + + + + C_DCACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + C_DCACHE_DATA_WIDTH + Data Width + 0 + + + + false + + + + + + C_M_AXI_DC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_DATA_WIDTH + 32 + + + C_M_AXI_DC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DC_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_M_AXI_DC_USER_VALUE + 31 + + + + true + + + + + + C_M_AXI_DC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_BUSER_WIDTH + 1 + + + + true + + + + + + + + + choice_list_29910ba8 + GENERIC + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_b1aff63c + 32 + 48 + 64 + + + choice_list_b94541ab + 0 + 2 + 4 + 8 + + + choice_list_dd2843c6 + 1 + 2 + 4 + 8 + + + choice_list_f86403bf + 4 + 8 + 16 + + + choice_pairs_0000a26c + 0 + 1 + 2 + 3 + + + choice_pairs_0873e75e + 0 + 1 + + + choice_pairs_1075faf2 + 0 + 1 + 2 + + + choice_pairs_126baff7 + 0 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_13d40c7c + 0 + 32 + 64 + 128 + 256 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_2058dc69 + 0 + 1 + + + choice_pairs_22d9f392 + 0 + 1 + 2 + 3 + + + choice_pairs_3eb333f8 + 0 + 1 + 2 + + + choice_pairs_443ae6cc + 0 + 1 + 2 + 3 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_56d5ba32 + 0 + 1 + 2 + + + choice_pairs_5ab38e91 + 0 + 1 + 2 + + + choice_pairs_5b1842a1 + 0 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_75c71b2b + 0 + 1 + 2 + 3 + + + choice_pairs_7ad6afc0 + 0 + 1 + 2 + 3 + + + choice_pairs_7bfd418d + 0 + 1 + 2 + + + choice_pairs_7dd2834f + 0 + 8 + 9 + 10 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_8b498448 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + + + choice_pairs_b1fa18d9 + 0 + 1 + 2 + + + choice_pairs_c471ed24 + 32 + 36 + 40 + 44 + 48 + 52 + 64 + + + choice_pairs_db57ca32 + 0 + 1 + 2 + + + choice_pairs_e7a1eb81 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_ff364cce + 2 + 3 + + + + + microblaze + + + + endian + little + + + elf_class + 32-bit + + + instance_path + + + + bootloop_file + data/mb_bootloop_le.elf + + + processor_type + MICROBLAZE_LE + + + is_visible + true + + + + + The MicroBlaze 32 and 64 bit soft processor core, providing an instruction set optimized for embedded applications with many user-configurable options. MicroBlaze has many advanced architecture features like Instruction and Data-side cache with AXI interfaces, Floating-Point unit (FPU), Memory Management Unit (MMU), and fault tolerance support. +It is highly recommended to create MicroBlaze systems within Vivado IP Integrator, to enable export to the Xilinx Software Development Kit (SDK) for software development. + + + + C_SCO + 0 + + + + true + + + + + + C_FREQ + 100000000 + + + + true + + + + + + C_DATA_SIZE + Select Processor Implementation + 32 + + + + true + + + + + + C_ADDR_SIZE + Select Extended Addressing + 32 + + + + true + + + + + + C_DYNAMIC_BUS_SIZING + 0 + + + + true + + + + + + C_PC_WIDTH + 17 + + + + true + + + + + + C_INSTANCE + mb_microblaze_0 + + + + true + + + + + + C_AVOID_PRIMITIVES + 0 + + + + true + + + + + + C_FAULT_TOLERANT + Enable Fault Tolerance Support + 0 + + + + true + + + + + + C_ECC_USE_CE_EXCEPTION + Correctable Error Exception + 0 + + + + true + + + + + + C_LOCKSTEP_SLAVE + Lockstep Slave + 0 + + + + true + + + + + + C_ENDIANNESS + Endianness + 1 + + + + true + + + + + + C_AREA_OPTIMIZED + Select implementation optimization + 0 + + + + true + + + + + + C_OPTIMIZATION + 0 + + + + true + + + + + + C_INTERCONNECT + Select Bus Interface + 2 + + + + true + + + + + + C_BASE_VECTORS + Vector Base Address + 0x0000000000000000 + + + + true + + + + + + C_USE_CONFIG_RESET + 0 + + + + true + + + + + + C_NUM_SYNC_FF_CLK + Synchronizing FFs to Clk region + 2 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_IRQ + Synchronizing FFs to Clk region for interrupt input + 1 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_DEBUG + Synchronizing FFs to Clk region in debug module + 2 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_CLK + Synchronizing FFs to Dbg_Clk region + 1 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_TRACE_CLK + Synchronizing FFs to Dbg_Trace_Clk region + 2 + + + + true + + + + + + C_M_AXI_DP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DP_DATA_WIDTH + 32 + + + + true + + + + + + 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TRUE + IP_Integrator + 6 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xml new file mode 100644 index 0000000..8d364bd --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xml @@ -0,0 +1,8812 @@ + + + xilinx.com + customized_ip + bd_9f2c_iomodule_0_0 + 1.0 + + + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + PROTOCOL + STANDARD + + + none + + + + + + + CLK.CLK + Clk + Clock Input + + + + + + + CLK + + + Clk + + + + + + ASSOCIATED_BUSIF + SLMB + + + ASSOCIATED_RESET + Rst:TMR_Rst + + + FREQ_HZ + Clk frequency + Clk frequency + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + bd_9f2c_Clk + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.Rst + Rst + Reset Input + + + + + + + RST + + + Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.TMR_Rst + TMR_Rst + TMR Reset Input + + + + + + + RST + + + TMR_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + IO_BUS + IO_BUS + MicroBlaze MCS IO Bus Interface + + + + + + + ADDR_STROBE + + + IO_Addr_Strobe + + + + + ADDRESS + + + IO_Address + + + + + BYTE_ENABLE + + + IO_Byte_Enable + + + + + READ_DATA + + + IO_Read_Data + + + + + READ_STROBE + + + IO_Read_Strobe + + + + + READY + + + IO_Ready + + + + + WRITE_DATA + + + IO_Write_Data + + + + + WRITE_STROBE + + + IO_Write_Strobe + + + + + + + true + + + + + + INTERRUPT.UART_Interrupt + UART_Interrupt + + + + + + + INTERRUPT + + + UART_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT1_Interrupt + FIT1_Interrupt + + + + + + + INTERRUPT + + + FIT1_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT2_Interrupt + FIT2_Interrupt + + + + + + + INTERRUPT + + + FIT2_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT3_Interrupt + FIT3_Interrupt + + + + + + + INTERRUPT + + + FIT3_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT4_Interrupt + FIT4_Interrupt + + + + + + + INTERRUPT + + + FIT4_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.PIT1_Interrupt + PIT1_Interrupt + + + + + + + INTERRUPT + + + PIT1_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.PIT2_Interrupt + PIT2_Interrupt + + + + + + + INTERRUPT + + + PIT2_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.PIT3_Interrupt + PIT3_Interrupt + + + + + + + INTERRUPT + + + PIT3_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.PIT4_Interrupt + PIT4_Interrupt + + + + + + + INTERRUPT + + + PIT4_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI1_Interrupt + GPI1_Interrupt + + + + + + + INTERRUPT + + + GPI1_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI2_Interrupt + GPI2_Interrupt + + + + + + + INTERRUPT + + + GPI2_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI3_Interrupt + GPI3_Interrupt + + + + + + + INTERRUPT + + + GPI3_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI4_Interrupt + GPI4_Interrupt + + + + + + + INTERRUPT + + + GPI4_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Interrupt + INTC_Interrupt + + + + + + + INTERRUPT + + + INTC_Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + none + + + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Irq_Single + INTC_IRQ + + + + + + + INTERRUPT + + + INTC_IRQ + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Irq + INTC_IRQ + + + + + + + ACK + + + INTC_Processor_Ack + + + + + ADDRESS + + + INTC_Interrupt_Address + + + + + INTERRUPT + + + INTC_IRQ + + + + + + SENSITIVITY + LEVEL_HIGH + + + LOW_LATENCY + 0 + + + + + + false + + + + + + INTERRUPT.INTC_Irq_Out + INTC_IRQ_OUT + + + + + + + INTERRUPT + + + INTC_IRQ_OUT + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + UART + UART + UART TX/RX + + + + + + + RxD + + + UART_Rx + + + + + TxD + + + UART_Tx + + + + + + BOARD.ASSOCIATED_PARAM + UART_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + UART_CLK.CLK + UART_Clk + Asynchronous UART Clock Input + + + + + + + CLK + + + UART_Clk + + + + + + ASSOCIATED_BUSIF + SLMB + + + ASSOCIATED_RESET + UART_Rst:TMR_Rst + + + FREQ_HZ + UART Clk frequency + UART Clk frequency + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + UART_RST.Rst + UART_Rst + Asynchronous UART Reset Input + + + + + + + RST + + + UART_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + GPIO1 + GPIO1 + General Purpose IO + + + + + + + TRI_I + + + GPI1 + + + + + TRI_O + + + GPO1 + + + + + + C_USE_GPO1 + 0 + + + + true + + + + + + C_GPO1_SIZE + 32 + + + + true + + + + + + C_GPO1_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI1 + 0 + + + + true + + + + + + C_GPI1_SIZE + 32 + + + + true + + + + + + C_GPI1_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO1_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO2 + GPIO2 + General Purpose IO + + + + + + + TRI_I + + + GPI2 + + + + + TRI_O + + + GPO2 + + + + + + C_USE_GPO2 + 0 + + + + true + + + + + + C_GPO2_SIZE + 32 + + + + true + + + + + + C_GPO2_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI2 + 0 + + + + true + + + + + + C_GPI2_SIZE + 32 + + + + true + + + + + + C_GPI2_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO2_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO3 + GPIO3 + General Purpose IO + + + + + + + TRI_I + + + GPI3 + + + + + TRI_O + + + GPO3 + + + + + + C_USE_GPO3 + 0 + + + + true + + + + + + C_GPO3_SIZE + 32 + + + + true + + + + + + C_GPO3_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI3 + 0 + + + + true + + + + + + C_GPI3_SIZE + 32 + + + + true + + + + + + C_GPI3_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO3_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO4 + GPIO4 + General Purpose IO + + + + + + + TRI_I + + + GPI4 + + + + + TRI_O + + + GPO4 + + + + + + C_USE_GPO4 + 0 + + + + true + + + + + + C_GPO4_SIZE + 32 + + + + true + + + + + + C_GPO4_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI4 + 0 + + + + true + + + + + + C_GPI4_SIZE + 32 + + + + true + + + + + + C_GPI4_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO4_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + + + SLMB + LMB memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + UART_RX + UART Receive Data Register + UART Receive Data Register + 0x0 + 8 + true + read-only + + 0x0 + + + UART_RX + Receive Data + Data received by the UART. + 0 + 8 + true + read-only + + 0 + 0 + + modify + false + + + + + false + + + + + + UART_TX + UART Transmit Data Register + UART Transmit Data Register + 0x4 + 8 + true + write-only + + 0x0 + + + UART_TX + Transmit Data + Data to be transmitted by the UART. + 0 + 8 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART_Status + UART Status Register + UART Status Register + 0x8 + 8 + true + read-only + + 0x0 + + + Rx_Valid_Data + Rx Valid Data + Indicates if the receive register has valid data: + 0 - Receive register is empty. + 1 - Receive register has valid data. + + 0 + 1 + true + read-only + + 0 + 0 + + false + + + Tx_Used + Tx Used + Indicates if the transmit register is in use: + 0 - Transmit register is not in use. + 1 - Transmit register is in use. + + 3 + 1 + true + read-only + + 0 + 0 + + false + + + Overrun_Error + Overrun Error + Indicates that an overrun error has occurred: + 0 - No overrun has occurred. + 1 - An overrun has occurred. + + 5 + 1 + true + read-only + + 0 + 0 + + false + + + Frame_Error + Frame Error + Indicates that an frame error has occurred: + 0 - No frame error has occurred. + 1 - A frame error has occurred. + + 6 + 1 + true + read-only + + 0 + 0 + + false + + + Parity_Error + Parity Error + Indicates that a parity error has occurred: + 0 - No parity error has occurred. + 1 - A parity error occurred. + + 7 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_MODE + Interrupt Mode Register + Interrupt Mode Register + 0xC + 17 + true + write-only + + 0x0 + + + IRQ_Mode + IRQ Mode + Interrupt Mode. +For each bit: + W - When written with 1 the corresponding interrupt will use fast mode. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + GPO_1 + General Purpose Output 1 Register + General Purpose Output 1 Register + 0x10 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO_2 + General Purpose Output 2 Register + General Purpose Output 2 Register + 0x14 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO_3 + General Purpose Output 3 Register + General Purpose Output 3 Register + 0x18 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO_4 + General Purpose Output 4 Register + General Purpose Output 4 Register + 0x1C + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_1 + General Purpose Input 1 Register + General Purpose Input 1 Register + 0x20 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_2 + General Purpose Input 2 Register + General Purpose Input 2 Register + 0x24 + 32 + true + read-only + + 0 + + + CPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_3 + General Purpose Input 3 Register + General Purpose Input 3 Register + 0x28 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_4 + General Purpose Input 4 Register + General Purpose Input 4 Register + 0x2C + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_STATUS + Interrupt Status Register + Interrupt Status Register + 0x30 + 17 + true + read-only + + 0x0 + + + UART_ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART_TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART_RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC_Interrupt + External interrupt input signal + Interrupt Status Register. +For each bit: + R - Reads active interrupt signal. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_PENDING + Interrupt Pending Register + Interrupt Pending Register + 0x34 + 17 + true + read-only + + 0x0 + + + UART_ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART_TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART_RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC_Interrupt + Enabled interrupt events that have occurred + Interrupt Pending. +For each bit: + R - Reads enabled interrupt event that has occurred. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_ENABLE + Interrupt Enable Register + Interrupt Enable Register + 0x38 + 17 + true + write-only + + 0x0 + + + UART_ERR + UART Error + UART Error interrupt enabled. + 0 + 1 + true + write-only + + 0 + 0 + + false + + + UART_TX + UART Transmitted Data + UART Transmitted Data interrupt enabled. + 1 + 1 + true + write-only + + 0 + 0 + + false + + + UART_RX + UART Received Data + UART Received Data interrupt enabled. + 2 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_1 + PIT 1 + PIT 1 interrupt enabled. + 3 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_2 + PIT 2 + PIT 2 interrupt enabled. + 4 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_3 + PIT 3 + PIT 3 interrupt enabled. + 5 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_4 + PIT 4 + PIT 4 interrupt enabled. + 6 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_1 + FIT 1 + FIT 1 interrupt enabled. + 7 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_2 + FIT 2 + FIT 2 interrupt enabled. + 8 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_3 + FIT 3 + FIT 3 interrupt enabled. + 9 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_4 + FIT 4 + FIT 4 interrupt enabled. + 10 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_1 + GPI 1 + GPI 1 interrupt enabled. + 11 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_2 + GPI 2 + GPI 2 interrupt enabled. + 12 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_3 + GPI 3 + GPI 3 interrupt enabled. + 13 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_4 + GPI 4 + GPI 4 interrupt enabled. + 14 + 1 + true + write-only + + 0 + 0 + + false + + + INTC_Interrupt + Enable external interrupt input signals + Interrupt Enable. +For each bit: + W - Enable external interrupt input signal. + + 16 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_ACK + Interrupt Acknowledge Register + Interrupt Acknowledge Register + 0x3C + 17 + true + write-only + + 0x0 + + + IRQ_Acknowledge + IRQ Acknowledge + Interrupt Acknowledge. +For each bit: + W - When written with 1 clear bit in IRQ_STATUS and IRQ_PENDING. + + 0 + 17 + true + write-only + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + PIT1_PRELOAD + PIT 1 Preload Register + PIT 1 Preload Register + 0x40 + 32 + true + write-only + + 0x0 + + + PIT1_Preload + PIT1 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1_COUNTER + PIT 1 Counter Register + PIT 1 Counter Register + 0x44 + 32 + true + read-only + + 0x0 + + + PIT1_Counter + PIT1 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1_CONTROL + PIT 1 Control Register + PIT 1 Control Register + 0x48 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT1_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART_BAUD + UART Programmable Baud Rate + UART Programmable Baud Rate + 0x4C + 8 + true + write-only + + 0x0 + + + UART_BAUD + Baud Rate + Programmable UART Baud Rate. + 0 + 20 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2_PRELOAD + PIT 2 Preload Register + PIT 2 Preload Register + 0x50 + 32 + true + write-only + + 0x0 + + + PIT2_Preload + PIT2 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2_COUNTER + PIT 2 Counter Register + PIT 2 Counter Register + 0x54 + 32 + true + read-only + + 0x0 + + + PIT2_Counter + PIT2 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2_CONTROL + PIT 2 Control Register + PIT 2 Control Register + 0x58 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT2_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3_PRELOAD + PIT 3 Preload Register + PIT 3 Preload Register + 0x60 + 32 + true + write-only + + 0x0 + + + PIT3_Preload + PIT3 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3_COUNTER + PIT 3 Counter Register + PIT 3 Counter Register + 0x64 + 32 + true + read-only + + 0x0 + + + PIT3_Counter + PIT3 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3_CONTROL + PIT 3 Control Register + PIT 3 Control Register + 0x68 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT3_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4_PRELOAD + PIT 4 Preload Register + PIT 4 Preload Register + 0x70 + 32 + true + write-only + + 0x0 + + + PIT4_Preload + PIT4 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4_COUNTER + PIT 4 Counter Register + PIT 4 Counter Register + 0x74 + 32 + true + read-only + + 0x0 + + + PIT4_Counter + PIT4 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4_CONTROL + PIT 4 Control Register + PIT 4 Control Register + 0x78 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT4_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_0 + Interrupt Vector Register 0 + Interrupt Vector Register 0 + 0x80 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 0 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_1 + Interrupt Vector Register 1 + Interrupt Vector Register 1 + 0x84 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 1 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_2 + Interrupt Vector Register 2 + Interrupt Vector Register 2 + 0x88 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 2 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_3 + Interrupt Vector Register 3 + Interrupt Vector Register 3 + 0x8C + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 3 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_4 + Interrupt Vector Register 4 + Interrupt Vector Register 4 + 0x90 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 4 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_5 + Interrupt Vector Register 5 + Interrupt Vector Register 5 + 0x94 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 5 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_6 + Interrupt Vector Register 6 + Interrupt Vector Register 6 + 0x98 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 6 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_7 + Interrupt Vector Register 7 + Interrupt Vector Register 7 + 0x9C + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 7 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_8 + Interrupt Vector Register 8 + Interrupt Vector Register 8 + 0xA0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 8 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_9 + Interrupt Vector Register 9 + Interrupt Vector Register 9 + 0xA4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 9 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_10 + Interrupt Vector Register 10 + Interrupt Vector Register 10 + 0xA8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 10 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_11 + Interrupt Vector Register 11 + Interrupt Vector Register 11 + 0xAC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 11 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_12 + Interrupt Vector Register 12 + Interrupt Vector Register 12 + 0xB0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 12 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_13 + Interrupt Vector Register 13 + Interrupt Vector Register 13 + 0xB4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 13 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_14 + Interrupt Vector Register 14 + Interrupt Vector Register 14 + 0xB8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 14 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_16 + Interrupt Vector Register 16 + Interrupt Vector Register 16 + 0xC0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 16 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_17 + Interrupt Vector Register 17 + Interrupt Vector Register 17 + 0xC4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 17 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_18 + Interrupt Vector Register 18 + Interrupt Vector Register 18 + 0xC8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 18 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_19 + Interrupt Vector Register 19 + Interrupt Vector Register 19 + 0xCC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 19 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_20 + Interrupt Vector Register 20 + Interrupt Vector Register 20 + 0xD0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 20 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_21 + Interrupt Vector Register 21 + Interrupt Vector Register 21 + 0xD4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 21 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_22 + Interrupt Vector Register 22 + Interrupt Vector Register 22 + 0xD8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 22 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_23 + Interrupt Vector Register 23 + Interrupt Vector Register 23 + 0xDC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 23 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_24 + Interrupt Vector Register 24 + Interrupt Vector Register 24 + 0xE0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 24 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_25 + Interrupt Vector Register 25 + Interrupt Vector Register 25 + 0xE4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 25 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_26 + Interrupt Vector Register 26 + Interrupt Vector Register 26 + 0xE8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 26 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_27 + Interrupt Vector Register 27 + Interrupt Vector Register 27 + 0xEC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 27 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_28 + Interrupt Vector Register 28 + Interrupt Vector Register 28 + 0xF0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 28 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_29 + Interrupt Vector Register 29 + Interrupt Vector Register 29 + 0xF4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 29 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_30 + Interrupt Vector Register 30 + Interrupt Vector Register 30 + 0xF8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 30 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_31 + Interrupt Vector Register 31 + Interrupt Vector Register 31 + 0xFC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 31 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_0 + Interrupt Vector Address Register 0 + Interrupt Vector Address Register 0 + 0x100 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 0 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_1 + Interrupt Vector Address Register 1 + Interrupt Vector Address Register 1 + 0x108 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 1 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_2 + Interrupt Vector Address Register 2 + Interrupt Vector Address Register 2 + 0x110 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 2 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_3 + Interrupt Vector Address Register 3 + Interrupt Vector Address Register 3 + 0x118 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 3 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_4 + Interrupt Vector Address Register 4 + Interrupt Vector Address Register 4 + 0x120 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 4 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_5 + Interrupt Vector Address Register 5 + Interrupt Vector Address Register 5 + 0x128 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 5 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_6 + Interrupt Vector Address Register 6 + Interrupt Vector Address Register 6 + 0x130 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 6 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_7 + Interrupt Vector Address Register 7 + Interrupt Vector Address Register 7 + 0x138 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 7 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_8 + Interrupt Vector Address Register 8 + Interrupt Vector Address Register 8 + 0x140 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 8 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_9 + Interrupt Vector Address Register 9 + Interrupt Vector Address Register 9 + 0x148 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 9 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_10 + Interrupt Vector Address Register 10 + Interrupt Vector Address Register 10 + 0x150 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 10 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_11 + Interrupt Vector Address Register 11 + Interrupt Vector Address Register 11 + 0x158 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 11 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_12 + Interrupt Vector Address Register 12 + Interrupt Vector Address Register 12 + 0x160 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 12 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_13 + Interrupt Vector Address Register 13 + Interrupt Vector Address Register 13 + 0x168 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 13 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_14 + Interrupt Vector Address Register 14 + Interrupt Vector Address Register 14 + 0x170 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 14 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_16 + Interrupt Vector Address Register 16 + Interrupt Vector Address Register 16 + 0x180 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 16 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_17 + Interrupt Vector Address Register 17 + Interrupt Vector Address Register 17 + 0x188 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 17 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_18 + Interrupt Vector Address Register 18 + Interrupt Vector Address Register 18 + 0x190 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 18 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_19 + Interrupt Vector Address Register 19 + Interrupt Vector Address Register 19 + 0x198 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 19 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_20 + Interrupt Vector Address Register 20 + Interrupt Vector Address Register 20 + 0x1A0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 20 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_21 + Interrupt Vector Address Register 21 + Interrupt Vector Address Register 21 + 0x1A8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 21 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_22 + Interrupt Vector Address Register 22 + Interrupt Vector Address Register 22 + 0x1B0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 22 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_23 + Interrupt Vector Address Register 23 + Interrupt Vector Address Register 23 + 0x1B8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 23 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_24 + Interrupt Vector Address Register 24 + Interrupt Vector Address Register 24 + 0x1C0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 24 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_25 + Interrupt Vector Address Register 25 + Interrupt Vector Address Register 25 + 0x1C8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 25 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_26 + Interrupt Vector Address Register 26 + Interrupt Vector Address Register 26 + 0x1D0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 26 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_27 + Interrupt Vector Address Register 27 + Interrupt Vector Address Register 27 + 0x1D8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 27 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_28 + Interrupt Vector Address Register 28 + Interrupt Vector Address Register 28 + 0x1E0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 28 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_29 + Interrupt Vector Address Register 29 + Interrupt Vector Address Register 29 + 0x1E8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 29 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_30 + Interrupt Vector Address Register 30 + Interrupt Vector Address Register 30 + 0x1F0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 30 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_31 + Interrupt Vector Address Register 31 + Interrupt Vector Address Register 31 + 0x1F8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 31 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + + IO + 0 + 65536 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_IO_BASEADDR + + + OFFSET_HIGH_PARAM + C_IO_HIGHADDR + + + + + + true + + + + + + + + + + Clk + + in + + + std_logic + dummy_view + + + + + + Rst + + in + + + std_logic + dummy_view + + + + + + Config_Reset + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + TMR_Rst + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + TMR_Disable + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + ToVote + + out + + 1023 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + FromAVote + + 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of synchronization flip-flops used to synchronize asynchronous interupt inputs + 2 + + + Component_Name + bd_9f2c_iomodule_0_0 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + GPIO1_BOARD_INTERFACE + Custom + + + GPIO2_BOARD_INTERFACE + Custom + + + GPIO3_BOARD_INTERFACE + Custom + + + GPIO4_BOARD_INTERFACE + Custom + + + UART_BOARD_INTERFACE + Custom + + + + + IOModule + 6 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci new file mode 100644 index 0000000..a41a888 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci @@ -0,0 +1,159 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_ilmb_0 + + + bd_9f2c_Clk + 100000000 + 0 + 0 + 0.000 + 32 + 32 + STANDARD + READ_ONLY + 32 + 32 + STANDARD + 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+ + + C_LMB_DWIDTH + C Lmb Dwidth + 32 + + + C_LMB_AWIDTH + C Lmb Awidth + 32 + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_EXT_RESET_HIGH + C Ext Reset High + 1 + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_0873e75e + 0 + 1 + + + choice_pairs_4873554b + 0 + 1 + + + The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM + + + C_LMB_DWIDTH + C Lmb Dwidth + 32 + + + + true + + + + + + C_LMB_AWIDTH + C Lmb Awidth + 32 + + + + true + + + + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_EXT_RESET_HIGH + C Ext Reset High + 1 + + + + true + + + + + + C_LMB_NUM_SLAVES + LMB Number of Slaves + 3 + + + + true + + + + + + Component_Name + bd_9f2c_dlmb_0 + + + + + Local Memory Bus (LMB) 1.0 + 11 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci new file mode 100644 index 0000000..c92a973 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci @@ -0,0 +1,189 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_dlmb_cntlr_0 + + + NONE + 65536 + 32 + 1 + + bd_9f2c_Clk + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000000000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000000000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_9f2c_dlmb_cntlr_0 + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 19 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml new file mode 100644 index 0000000..72e6605 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml @@ -0,0 +1,4011 @@ + + + xilinx.com + customized_ip + bd_9f2c_dlmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + PROTOCOL + STANDARD + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + PROTOCOL + STANDARD + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + PROTOCOL + STANDARD + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + PROTOCOL + STANDARD + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + READ_LATENCY + 1 + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + bd_9f2c_Clk + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC_Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE_Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + LMB_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + Sl_Ready + + out + + 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uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + LMB_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + Sl_Ready + + out + + + std_logic + dummy_view + + + + + + Sl_Wait + + out + + + std_logic + dummy_view + + + + + + Sl_UE + + out + + + std_logic + dummy_view + + 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Sl2_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + LMB3_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + Sl3_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + Sl3_Ready + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl3_Wait + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl3_UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl3_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + BRAM_Rst_A + + out + + + std_logic + dummy_view + + + + + + BRAM_Clk_A + + out + + + std_logic + dummy_view + + + + + + BRAM_Addr_A + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + BRAM_EN_A + + out + + + std_logic + dummy_view + + + + + + BRAM_WEN_A + + out + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + + + BRAM_Dout_A + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + BRAM_Din_A + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + S_AXI_CTRL_ACLK + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARESETN + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_WDATA + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RDATA + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + + + C_FAMILY + virtexuplus + + + C_HIGHADDR + LMB BRAM High Address + 0x000000000000FFFF + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000000000 + + + C_NUM_LMB + Number of LMB Ports + 1 + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_BRAM_AWIDTH + BRAM Address Bus Width + 32 + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + false + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + false + + + + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_0873e75e + 0 + 1 + + + choice_pairs_449ac0d2 + 0 + 1 + 2 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_8d6e70ff + 0 + 2 + + + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000000000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x000000000000FFFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_9f2c_ilmb_cntlr_0 + + + + + LMB BRAM Controller + 19 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci new file mode 100644 index 0000000..6a64a19 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci @@ -0,0 +1,298 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_lmb_bram_I_0 + + + 4096 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + BRAM_CTRL + NONE + 65536 + 32 + 1 + READ_WRITE + BRAM_CTRL + NONE + 65536 + 32 + 1 + READ_WRITE + + 100000000 + 0 + 0 + 0.000 + 0 + 32 + 32 + 1 + 4 + 0 + 1 + 8 + 0 + 0 + 16 + NONE + 0 + 0 + 0 + ./ + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + Estimated Power for IP : 19.660986 mW + virtexuplus + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + bd_9f2c_lmb_bram_I_0.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 16384 + 16384 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 4 + 4 + 16384 + 16384 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 8 + NONE + no_coe_file_loaded + ALL + bd_9f2c_lmb_bram_I_0 + false + false + false + false + false + true + false + false + true + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + false + Native + false + bd_9f2c_lmb_bram_I_0.mem + True_Dual_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + true + false + false + false + true + true + 16384 + 32 + 32 + No_ECC + false + false + false + BRAM_Controller + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 4 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml new file mode 100644 index 0000000..bb42e99 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml @@ -0,0 +1,4151 @@ + + + xilinx.com + customized_ip + bd_9f2c_lmb_bram_I_0 + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXI_SLAVE_S_AXI + AXI_SLAVE + AXI_SLAVE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARBURST + + + s_axi_arburst + + + + + ARID + + + s_axi_arid + + + + + ARLEN + + + s_axi_arlen + + + + + ARREADY + + + s_axi_arready + + + + + ARSIZE + + + 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choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_9f2c_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false 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4 + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci new file mode 100644 index 0000000..93d3055 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci @@ -0,0 +1,189 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_second_dlmb_cntlr_0 + + + NONE + 32768 + 32 + 1 + + bd_9f2c_Clk + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000010000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 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RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 32768 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + READ_LATENCY + 1 + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + 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+ + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC_Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE_Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + 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OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC_Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE_Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + LMB_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + Sl_Ready + + out + + + std_logic + dummy_view + + + + + + Sl_Wait + + out + + + std_logic + dummy_view + + + + + + Sl_UE + + out + + + std_logic + dummy_view + + + + + + Sl_CE + + out + + + std_logic + dummy_view + + + + + + LMB1_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + 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+ + + + + C_FAMILY + virtexuplus + + + C_HIGHADDR + LMB BRAM High Address + 0x0000000000017FFF + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000010000 + + + C_NUM_LMB + Number of LMB Ports + 1 + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_BRAM_AWIDTH + BRAM Address Bus Width + 32 + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + false + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + false + + + + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_0873e75e + 0 + 1 + + + choice_pairs_449ac0d2 + 0 + 1 + 2 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_8d6e70ff + 0 + 2 + + + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000010000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x0000000000017FFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_9f2c_second_ilmb_cntlr_0 + + + + + LMB BRAM Controller + 19 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci new file mode 100644 index 0000000..c69c392 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci @@ -0,0 +1,298 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_second_lmb_bram_I_0 + + + 4096 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + BRAM_CTRL + NONE + 32768 + 32 + 1 + READ_WRITE + BRAM_CTRL + NONE + 32768 + 32 + 1 + READ_WRITE + + 100000000 + 0 + 0 + 0.000 + 0 + 32 + 32 + 1 + 4 + 0 + 1 + 8 + 0 + 0 + 8 + NONE + 0 + 0 + 0 + ./ + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + Estimated Power for IP : 17.246228 mW + virtexuplus + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + bd_9f2c_second_lmb_bram_I_0.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 8192 + 8192 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 4 + 4 + 8192 + 8192 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 8 + NONE + no_coe_file_loaded + ALL + bd_9f2c_second_lmb_bram_I_0 + false + false + false + false + false + true + false + false + true + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + false + Native + false + bd_9f2c_second_lmb_bram_I_0.mem + True_Dual_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + true + false + false + false + true + true + 8192 + 32 + 32 + No_ECC + false + false + false + BRAM_Controller + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 4 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xml new file mode 100644 index 0000000..b398710 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xml @@ -0,0 +1,4151 @@ + + + xilinx.com + customized_ip + bd_9f2c_second_lmb_bram_I_0 + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + 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16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_6fc15197 + 32 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f9a6a28b + Native + + + choice_pairs_1f270a52 + BRAM_Controller + Stand_Alone + + + choice_pairs_246d8066 + WRITE_FIRST + READ_FIRST + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_9f2c_second_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A 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rs232_uart + + + choice_list_30de7c39 + Custom + pcie_perstn + resetn + + + choice_list_38e5a9f1 + Custom + dip_switches_4bits + led_3bits + qsfp0_lowspeed + qsfp1_lowspeed + + + choice_list_ac75ef1e + Custom + + + choice_list_f585525a + 110 + 300 + 1200 + 2400 + 4800 + 9600 + 19200 + 38400 + 57600 + 115200 + 128000 + 230400 + 460800 + 921600 + + + choice_pairs_007f01e9 + 0 + 1 + 2 + 3 + 4 + 5 + 7 + 8 + 9 + + + choice_pairs_0d2d32a8 + 0 + 1 + 2 + + + choice_pairs_366c5f3d + 0 + 1 + 2 + + + choice_pairs_4847022f + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 8 + 9 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_5502e96b + 1 + 2 + 3 + 4 + + + choice_pairs_563648c8 + 0 + 1 + + + choice_pairs_5f1e379e + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 9 + + + choice_pairs_7ba91213 + 0 + 1 + 2 + 3 + + + choice_pairs_9de6ed99 + 0 + + + choice_pairs_f0f6eb36 + 0 + 1 + 2 + 3 + 4 + 6 + 7 + 8 + 9 + + + choice_pairs_f7e0b771 + 4096 + 8192 + 12288 + 16384 + 20480 + 24576 + 32768 + 36864 + 40960 + 49152 + 65536 + 69632 + 73728 + 81920 + 98304 + 131072 + + + choice_pairs_ffa336e4 + 0 + 1 + + + + + xilinx_elaborateports_view_fileset + + ../bd_0/bd_9f2c.bd + block_diagram + + + + xilinx_elaboratebd_view_fileset + + ../bd_0/bd_9f2c.bd + block_diagram + + + + MicroBlaze Micro Controller System (MCS) is a light-weight general purpose micro controller system, based on the MicroBlaze processor. It is primarily intended for simple control applications, where a hardware solution would be less flexible and more difficult to implement. Software development with the Xilinx Software Development Kit (SDK) is supported, including a software driver for the peripherals. Debugging including UART is available either via SDK or directly with the Xilinx Microprocessor Debugger. +The MCS consists of the processor itself, local memory with sizes ranging from 4KB to 128KB, up to 4 Fixed Interval Timers, up to 4 Programmable Interval Timers, up to 4 32-bit General Purpose Output ports, up to 4 32-bit General Purpose Input ports, and an Interrupt Controller with up to 16 external interrupt inputs. + + + + JTAG_CHAIN + Debug JTAG User-defined Register + 2 + + + + false + + + + + + MICROBLAZE_INSTANCE + MicroBlaze Instance Name + microblaze_0 + + + AVOID_PRIMITIVES + 0 + + + PATH + Instance Hierarchical Design Name + mcs_0 + + + FREQ + Input Clock Frequency (MHz) + 100.0 + + + OPTIMIZATION + Select MicroBlaze Optimization + 1 + + + DEBUG_ENABLED + Enable Debug Support + 0 + + + USE_BSCAN + Select BSCAN location + 0 + + + + false + + + + + + BSCANID + Define BSCAN id + 76547328 + + + + false + + + + + + TRACE + Enable MicroBlaze Trace Bus + 1 + + + ECC + Error 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+ Custom + + + + true + + + + + + RESET_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO1_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO2_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO3_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO4_BOARD_INTERFACE + Custom + + + + true + + + + + + UART_BOARD_INTERFACE + Custom + + + + true + + + + + + + + MicroBlaze MCS + + XPM_MEMORY + + 14 + + true + subcore + + + + + + + + + + + + + + + + 2020.2 + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci new file mode 100644 index 0000000..6b0e807 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci @@ -0,0 +1,667 @@ + + + xilinx.com + xci + unknown + 1.0 + + + phy_ddr4_phy + + + 18 + 0 + 0 + 0 + 2 + HP_IO + 2 + X0Y11 + X0Y10 + X0Y70 + X0Y11 + 12 + DDR4_SDRAM + 0 + 0 + 0 + 1 + 1 + 3333 + 10 + 1 + 4 + 5 + 9 + 9 + 18 + 72 + {12{2'b00}} + { 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, + 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111011, + 15'b111111111111111, 15'b111111111111111 } + 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b +000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, + 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_000_000_000_000_000_001_000_001_001_001_001_001, 39'b001_001_001_000_000_001_001_001_00 +1_001_001_001_001, 39'b000_001_001_001_001_101_101_001_001_001_001_001_001 + true + 1 + 4 + 72 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + {{9{2'b11}}, {3{2'b00}}} + 12'b000000000000 + 1 + 3 + 1 + {13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b01111 +01111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0000001011111, 13'b1110011111111, + 13'b0111101111111 } + { 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, + 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b000000_11_01111_11, + 15'b111001_11_11111_11, 15'b011111_11_11111_11 } + {12{2'b11}} + FALSE + 1 + { 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000 +011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000001011111, 13'b1110011111111, + 13'b0111111111111 } + 1 + 0 + 4 + 1500 + 2 + 5 + 10 + 60 + 256 + DDR4_SDRAM + 5 + 9 + VCO + 16 + 14 + true + false + 1 + NONE + 72 + true + false + false + 0 + No + 3333 + 833 + 64GB + RDIMMs + 1.2V + 4:1 + false + false + Single + 1 + 1500 + 0.84 + no_file_loaded + false + 15 + 0 + 0 + 0 + CustomPart_Address__width 18$CustomPart_Bank__group__width 2$CustomPart_Bank__width 2$CustomPart_CA__Mirror 0$CustomPart_CKE__width 1$CustomPart_CK__width 1$CustomPart_CS__width 1$CustomPart_Column__width 10$CustomPart_Component__density 16Gb$CustomPart_Data__bits__per__strobe 4$CustomPart_Data__mask 0$CustomPart_Data__widths 72$CustomPart_IO__Voltages 1.2V$CustomPart_Max__period 1600$CustomPart_Memory__component__width 4$CustomPart_Memory__density 64GB$CustomPart_Memory__device__width 72$Custom +Part_Memory__speed__grade 83$CustomPart_Min__period 833$CustomPart_ODT__width 1$CustomPart_Part__name 64GB$CustomPart_Part__type RDIMMs$CustomPart_Rank 1$CustomPart_Row__width 18$CustomPart_StackHeight 1$CustomPart_burst__length 8$CustomPart_cas__latency 24$CustomPart_cas__write__latency 22$CustomPart_tCCD_3ds 5 tck$CustomPart_tCKE 5000 ps$CustomPart_tFAW 13000 ps$CustomPart_tFAW_dlr 16 tck$CustomPart_tMRD 8 tck$CustomPart_tRAS 32000 ps$CustomPart_tRCD 14160 ps$CustomPart_tREFI 7800000 ps$Custom +Part_tRFC 350000 ps$CustomPart_tRFC_dlr 110000 ps$CustomPart_tRP 14160 ps$CustomPart_tRRD_L 4900 ps$CustomPart_tRRD_S 3300 ps$CustomPart_tRRD_dlr 4 tck$CustomPart_tRTP 7500 ps$CustomPart_tWR 15000 ps$CustomPart_tWTR_L 7500 ps$CustomPart_tWTR_S 2500 ps$CustomPart_tXPR 360 ns$CustomPart_tZQCS 128 tck$CustomPart_tZQINIT 1024 tck$ + phy_ddr4_phy + false + Disable + false + 1 + 1 + false + Phy_Only_Single + false + BFM + Differential + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + 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WIDTH + 9 + + + MR0 + Mode register_0 value + 0 + + + MR2 + Mode register_0 value + 0 + + + tCK + tCK + 1500 + + + tXPR + tXPR + 60 + + + nCK_PER_CLK + nCK PER CLK + 4 + + + tMRD + tMRD + 2 + + + tZQINIT + tZQINIT + 256 + + + MEM_COMP_WIDTH + MEM COMP WIDTH + 4 + + + MEM_DEVICE_WIDTH + MEMORY DEVICE WIDTH + 72 + + + PLL_WIDTH + PLL WIDTH + 3 + + + IOBTYPE + IOBTYPE + 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b +000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, + 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_000_000_000_000_000_001_000_001_001_001_001_001, 39'b001_001_001_000_000_001_001_001_00 +1_001_001_001_001, 39'b000_001_001_001_001_101_101_001_001_001_001_001_001 + + + BYTES + BYTES + 12 + + + DBYTES + DBYTES + 9 + + + PING_PONG_CH1_BYTES_MAP + PING_PONG_CH1_BYTES_MAP + 12'b000000000000 + + + PING_PONG_PHY + PING PONG PHY + 1 + + + RX_DATA_TYPE + RX DATA TYPE + { 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, + 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b000000_11_01111_11, + 15'b111001_11_11111_11, 15'b011111_11_11111_11 } + + + INIT + INIT + { 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, + 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111011, + 15'b111111111111111, 15'b111111111111111 } + + + SELF_CALIBRATE + SELF CALIBRATE + {12{2'b11}} + + + TX_OUTPUT_PHASE_90 + TX OUTPUT PHASE 90 + { 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000 +011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000001011111, 13'b1110011111111, + 13'b0111111111111 } + + + RXTX_BITSLICE_EN + RXTX BITSLICE EN + {13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b01111 +01111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0000001011111, 13'b1110011111111, + 13'b0111101111111 } + + + EN_OTHER_PN_CLOCK_PARAM + EN OTHER PN CLOCK PARAM + {12{2'b00}} + + + PHY_BYTE_ALLOC_PARAM + PHY BYTE ALLOC PARAM + {{9{2'b11}}, {3{2'b00}}} + + + DATA_BUF_ADDR_WIDTH + DATA BUF ADDR WIDTH + 5 + + + CLKIN_PERIOD + CLKIN PERIOD + 3333 + + + MEM_TYPE + MEM TYPE + 0 + + + AXI_ID_WIDTH + AXI ID WIDTH + 0 + + + AXI_DATA_WIDTH + AXI DATA WIDTH + 0 + + + AXI_ADDR_WIDTH + AXI ADDR WIDTH + 0 + + + USE_DM_PORT + USE DM PORT + 0 + + + BUFG_LOC_1 + BUFG LOC 1 + X0Y70 + + + BUFG_LOC_2 + BUFG LOC 2 + X0Y11 + + + BUFG_DIV_LOC_1 + BUFG DIV LOC 1 + X0Y11 + + + BUFG_DIV_LOC_2 + BUFG DIV LOC 2 + X0Y10 + + + PBLOCK_SLICE_LOC + PBLOCK SLICE LOC + 0 + + + PBLOCK_RAMB36_LOC + PBLOCK RAMB36 LOC + 0 + + + PBLOCK_RAMB18_LOC + PBLOCK RAMB18 LOC + 0 + + + PBLOCK_SLICE_LOC_SC + PBLOCK SLICE LOC SC + 0 + + + PBLOCK_RAMB36_LOC_SC + PBLOCK RAMB36 LOC SC + 0 + + + PBLOCK_RAMB18_LOC_SC + PBLOCK RAMB18 LOC SC + 0 + + + MMCM_IDX_BANK + MMCM IDX BANK + 1 + + + CENTER_BANK_CLOCK_REGION + CENTER BANK CLOCK REGION + 0 + + + CENTER_BANK_MMCME3_ADV_SITE + CENTER BANK MMCME3 ADV SITE + 0 + + + SYSCLK_CENTER_INFO + SYSCLK_CENTER_INFO + FALSE + + + tWR + tWR + 10 + + + tRTP + tRTP + 5 + + + RANK_WIDTH + RANK WIDTH + 1 + + + CK_WIDTH + CK WIDTH + 1 + + + DATABITS_PER_STROBE + DATABITS PER STROBE + 4 + + + USE_CS_PORT + USE CS PORT + 1 + + + CA_MIRROR + CA MIRROR + 0 + + + IS_CUSTOM + IS CUSTOM + true + + + Slot + Slot + 1 + + + + + + phy_ddr4_phy + + + + PHY for DDR4 interfaces for Ultrascale Architecture + + + C0.ControllerType + DDR4_SDRAM + + + IS_FROM_PHY + 1 + + + Phy_Only + Phy_Only_Single + + + No_Controller + 1 + + + Default_Bank_Selections + Default Bank Selections + false + + + Debug_Signal + Disable + + + Simulation_Mode + BFM + + + PARTIAL_RECONFIG_FLOW_MIG + false + + + CLKOUT1_DIVIDE + 15 + + + CLKOUT2_DIVIDE + 0 + + + CLKOUT3_DIVIDE + 0 + + + CLKOUT4_DIVIDE + 0 + + + System_Clock + Differential + + + RECONFIG_XSDB_SAVE_RESTORE + false + + + DIFF_TERM_SYSCLK + false + + + C0.DDR4_TimePeriod + 1500 + + + C0.DDR4_InputClockPeriod + 3333 + + + C0.DDR4_CLKFBOUT_MULT + 5 + + + C0.DDR4_DIVCLK_DIVIDE + 1 + + + C0.DDR4_CLKOUT0_DIVIDE + 9 + + + C0.DDR4_PhyClockRatio + 4:1 + + + C0.DDR4_MemoryType + RDIMMs + + + C0.DDR4_MemoryPart + 64GB + + + C0.DDR4_Slot + Single + + + C0.DDR4_MemoryVoltage + 1.2V + + + C0.DDR4_DataWidth + 72 + + + C0.DDR4_DataMask + NONE + + + C0.DDR4_Ecc + false + + + C0.DDR4_CasLatency + 16 + + + C0.DDR4_CasWriteLatency + 14 + + + C0.DDR4_ChipSelect + true + + + C0.DDR4_isCKEShared + false + + + C0.DDR4_CLKOUTPHY_MODE + CLKOUTPHY MODE + VCO + + + C0.DDR4_HR_MIN_FREQ + High Range Supported frequency + 0 + + + C0.DDR4_MIN_PERIOD + Memory Min Period + 833 + + + C0.DDR4_IS_FASTER_SPEED_RAM + Indicates Faster Speed RAM Support + No + + + C0.DDR4_VrefVoltage + Vref Voltage + 0.84 + + + C0.DDR4_customPartAbsPath + no_file_loaded + + + C0.DDR4_StackHeight + 1 + + + CUSTOM_PART_ATTRIBUTES + CustomPart_Address__width 18$CustomPart_Bank__group__width 2$CustomPart_Bank__width 2$CustomPart_CA__Mirror 0$CustomPart_CKE__width 1$CustomPart_CK__width 1$CustomPart_CS__width 1$CustomPart_Column__width 10$CustomPart_Component__density 16Gb$CustomPart_Data__bits__per__strobe 4$CustomPart_Data__mask 0$CustomPart_Data__widths 72$CustomPart_IO__Voltages 1.2V$CustomPart_Max__period 1600$CustomPart_Memory__component__width 4$CustomPart_Memory__density 64GB$CustomPart_Memory__device__width 72$Custom +Part_Memory__speed__grade 83$CustomPart_Min__period 833$CustomPart_ODT__width 1$CustomPart_Part__name 64GB$CustomPart_Part__type RDIMMs$CustomPart_Rank 1$CustomPart_Row__width 18$CustomPart_StackHeight 1$CustomPart_burst__length 8$CustomPart_cas__latency 24$CustomPart_cas__write__latency 22$CustomPart_tCCD_3ds 5 tck$CustomPart_tCKE 5000 ps$CustomPart_tFAW 13000 ps$CustomPart_tFAW_dlr 16 tck$CustomPart_tMRD 8 tck$CustomPart_tRAS 32000 ps$CustomPart_tRCD 14160 ps$CustomPart_tREFI 7800000 ps$Custom +Part_tRFC 350000 ps$CustomPart_tRFC_dlr 110000 ps$CustomPart_tRP 14160 ps$CustomPart_tRRD_L 4900 ps$CustomPart_tRRD_S 3300 ps$CustomPart_tRRD_dlr 4 tck$CustomPart_tRTP 7500 ps$CustomPart_tWR 15000 ps$CustomPart_tWTR_L 7500 ps$CustomPart_tWTR_S 2500 ps$CustomPart_tXPR 360 ns$CustomPart_tZQCS 128 tck$CustomPart_tZQINIT 1024 tck$ + + + C0.DDR4_SELF_REFRESH + false + + + C0.DDR4_SAVE_RESTORE + false + + + C0.DDR4_Clamshell + false + + + C0.DDR4_Enable_LVAUX + false + + + C0.DDR4_EN_PARITY + true + + + + false + + + + + + c0_dq_0 + NONE + + + c0_dq_1 + NONE + + + c0_dq_2 + NONE + + + c0_dq_3 + NONE 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NONE + + + c0_dq_50 + NONE + + + c0_dq_51 + NONE + + + c0_dq_52 + NONE + + + c0_dq_53 + NONE + + + c0_dq_54 + NONE + + + c0_dq_55 + NONE + + + c0_dq_56 + NONE + + + c0_dq_57 + NONE + + + c0_dq_58 + NONE + + + c0_dq_59 + NONE + + + c0_dq_60 + NONE + + + c0_dq_61 + NONE + + + c0_dq_62 + NONE + + + c0_dq_63 + NONE + + + c0_dq_64 + NONE + + + c0_dq_65 + NONE + + + c0_dq_66 + NONE + + + c0_dq_67 + NONE + + + c0_dq_68 + NONE + + + c0_dq_69 + NONE + + + c0_dq_70 + NONE + + + c0_dq_71 + NONE + + + c0_dq_72 + NONE + + + c0_dq_73 + NONE + + + c0_dq_74 + NONE + + + c0_dq_75 + NONE + + + c0_dq_76 + NONE + + + c0_dq_77 + NONE + + + c0_dq_78 + NONE + + + c0_dq_79 + NONE + + + c0_dq_80 + NONE + + + c0_dq_81 + NONE + + + c0_dq_82 + NONE + + + c0_dq_83 + NONE + + + c0_dq_84 + NONE + + + c0_dq_85 + NONE + + + c0_dq_86 + NONE + + + c0_dq_87 + NONE + + + c0_dq_88 + NONE + + + c0_dq_89 + NONE + + + c0_dq_90 + NONE + + + c0_dq_91 + NONE + + + c0_dq_92 + NONE + + + c0_dq_93 + NONE + + + c0_dq_94 + NONE + + + c0_dq_95 + NONE + + + c0_dq_96 + NONE + + + c0_dq_97 + NONE + + + c0_dq_98 + NONE + + + c0_dq_99 + NONE + + + c0_dq_100 + NONE + + + c0_dq_101 + NONE + + + c0_dq_102 + NONE + + + c0_dq_103 + NONE + + + c0_dq_104 + NONE + + + c0_dq_105 + NONE + + + c0_dq_106 + NONE + + + c0_dq_107 + NONE + + + c0_dq_108 + NONE + + + c0_dq_109 + NONE + + + c0_dq_110 + NONE + + + c0_dq_111 + NONE + + + c0_dq_112 + NONE + + + c0_dq_113 + NONE + + + c0_dq_114 + NONE + + + c0_dq_115 + NONE + + + c0_dq_116 + NONE + + + c0_dq_117 + NONE + + + c0_dq_118 + NONE + + + c0_dq_119 + NONE + + + c0_dq_120 + NONE + + + c0_dq_121 + NONE + + + c0_dq_122 + NONE + + + c0_dq_123 + NONE + + + c0_dq_124 + NONE + + + c0_dq_125 + NONE + + + c0_dq_126 + NONE + + + c0_dq_127 + NONE + + + c0_dq_128 + NONE + + + c0_dq_129 + NONE + + + c0_dq_130 + NONE + + + c0_dq_131 + NONE + + + c0_dq_132 + NONE + + + c0_dq_133 + NONE + + + c0_dq_134 + NONE + + + c0_dq_135 + NONE + + + c0_dq_136 + NONE + + + c0_dq_137 + NONE + + + c0_dq_138 + NONE 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a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci new file mode 100644 index 0000000..f857867 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci @@ -0,0 +1,500 @@ + + + xilinx.com + xci + unknown + 1.0 + + + phy_ddr4 + + + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 32 + 576 + 72 + X0Y11 + X0Y10 + X0Y70 + X0Y11 + 0 + 0 + DDR4_SDRAM + 18 + 0 + true + 34 + 512 + 4 + 2 + 2 + 0 + 0 + 0 + 1 + 1 + 0 + 5 + 3333 + 9 + 0 + VCO + 10 + 16Gb + 32 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83$CustomPart_Min__period 833$CustomPart_ODT__width 1$CustomPart_Part__name 64GB$CustomPart_Part__type RDIMMs$CustomPart_Rank 1$CustomPart_Row__width 18$CustomPart_StackHeight 1$CustomPart_burst__length 8$CustomPart_cas__latency 24$CustomPart_cas__write__latency 22$CustomPart_tCCD_3ds 5 tck$CustomPart_tCKE 5000 ps$CustomPart_tFAW 13000 ps$CustomPart_tFAW_dlr 16 tck$CustomPart_tMRD 8 tck$CustomPart_tRAS 32000 ps$CustomPart_tRCD 14160 ps$CustomPart_tREFI 7800000 ps$Custom +Part_tRFC 350000 ps$CustomPart_tRFC_dlr 110000 ps$CustomPart_tRP 14160 ps$CustomPart_tRRD_L 4900 ps$CustomPart_tRRD_S 3300 ps$CustomPart_tRRD_dlr 4 tck$CustomPart_tRTP 7500 ps$CustomPart_tWR 15000 ps$CustomPart_tWTR_L 7500 ps$CustomPart_tWTR_S 2500 ps$CustomPart_tXPR 360 ns$CustomPart_tZQCS 128 tck$CustomPart_tZQINIT 1024 tck$ + Disable + 1 + 100 + 0 + 0.0 + 0 + 0.0 + 0 + 0.0 + 0 + 1 + BFM + Differential + 100 + None + None + None + 0 + 18 + 2 + 1 + 1 + 1 + DDR4_SDRAM + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 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Memory Name + 0 + + + C0.DDR4_DBAW + DBAW + 0 + + + C0.DDR4_tCK + tCK + 1500 + + + C0.DDR4_Configuration + Configuration + 0 + + + C0.DDR4_tCKE + tCKE + 0 + + + C0.DDR4_tFAW + tFAW + 9 + + + C0.DDR4_tFAW_dlr + tFAW_dlr + 16 + + + C0.DDR4_tMRD + tMRD + 2 + + + C0.DDR4_tRAS + tRAS + 22 + + + C0.DDR4_tRCD + tRCD + 10 + + + C0.DDR4_tREFI + tREFI + 5200 + + + C0.DDR4_tRFC + tRFC + 234 + + + C0.DDR4_tRFC_dlr + tRFC_dlr + 74 + + + C0.DDR4_tRP + tRP + 10 + + + C0.DDR4_tWR + tWR + 10 + + + C0.DDR4_tRRD + tRRD + + + + C0.DDR4_tRTP + tRTP + 5 + + + C0.DDR4_tRRD_S + tRRD_S + 3 + + + C0.DDR4_tRRD_L + tRRD_L + 4 + + + C0.DDR4_tRRD_dlr + tRRD_dlr + 4 + + + C0.DDR4_tWTR + tWTR + + + + C0.DDR4_tWTR_S + tWTR_S + 2 + + + C0.DDR4_tWTR_L + tWTR_L + 5 + + + C0.DDR4_tXPR + tXPR + 60 + + + C0.DDR4_tZQI + tZQI + 0 + + + C0.DDR4_tZQCS + tZQCS + 128 + + + C0.DDR4_tZQINIT + tZQINIT + 256 + + + C0.DDR4_tCCD_3ds + tCCD_3ds + 5 + + + C0.DDR4_CLKOUTPHY_MODE + CLKOUTPHY_MODE + VCO + + + C0.DDR4_CLKOUT0_DIVIDE + CLKOUT0_DIVIDE + 9 + + + C0.DDR4_CLKOUT1_DIVIDE + CLKOUT1_DIVIDE + 0 + + + C0.DDR4_CLKFBOUT_MULT + CLKFBOUT_MULT + 5 + + + C0.DDR4_DIVCLK_DIVIDE + DIVCLK DIVIDE + 1 + + + CAL_INPUT_CLK_PERIOD + Calculated Input Clock Period + 3333 + + + C0.DDR4_CLKIN_PERIOD + CLKIN_PERIOD + 3333 + + + C0.DDR4_HR_MIN_FREQ + High Range Supported frequency + 0 + + + C0.DDR4_DCI_CASCADE_CUTOFF + DCI Cascade Cutoff + 938 + + + C0.DDR4_IS_FASTER_SPEED_RAM + Is Faster Speed RAM + No + + + C0.DDR4_AXI_ID_WIDTH + AXI ID Width + 4 + + + C0.DDR4_AXI_ADDR_WIDTH + AXI Address Width + 34 + + + C0.DDR4_AXI_DATA_WIDTH + AXI Data Width + 512 + + + C0.DDR4_MEM_SIZE + Memory Size + 34359738368 + + + C0.DDR4_UI_CLOCK + DDR4 UI CLOCK + 166500000 + + + C0.DDR4_CA_MIRROR + CA MIRROR + 0 + + + C0.DDR4_IS_CUSTOM + IS CUSTOM + true + + + C0.DDR4_AUTO_AP_COL_A3 + AUTO AP COL A3 + true + + + C0.DDR4_MCS_ECC + MCS ECC + 0 + + + C0.DDR4_Slot + Slot Type + 1 + + + C0.APP_DATA_WIDTH + APP Data Width + 576 + + + C0.APP_MASK_WIDTH + APP Mask Width + 72 + + + C0.DDR4_StackHeight + 1 + + + CUSTOM_PART_ATTRIBUTES + custom_part_attributes + CustomPart_Address__width 18$CustomPart_Bank__group__width 2$CustomPart_Bank__width 2$CustomPart_CA__Mirror 0$CustomPart_CKE__width 1$CustomPart_CK__width 1$CustomPart_CS__width 1$CustomPart_Column__width 10$CustomPart_Component__density 16Gb$CustomPart_Data__bits__per__strobe 4$CustomPart_Data__mask 0$CustomPart_Data__widths 72$CustomPart_IO__Voltages 1.2V$CustomPart_Max__period 1600$CustomPart_Memory__component__width 4$CustomPart_Memory__density 64GB$CustomPart_Memory__device__width 72$Custom +Part_Memory__speed__grade 83$CustomPart_Min__period 833$CustomPart_ODT__width 1$CustomPart_Part__name 64GB$CustomPart_Part__type RDIMMs$CustomPart_Rank 1$CustomPart_Row__width 18$CustomPart_StackHeight 1$CustomPart_burst__length 8$CustomPart_cas__latency 24$CustomPart_cas__write__latency 22$CustomPart_tCCD_3ds 5 tck$CustomPart_tCKE 5000 ps$CustomPart_tFAW 13000 ps$CustomPart_tFAW_dlr 16 tck$CustomPart_tMRD 8 tck$CustomPart_tRAS 32000 ps$CustomPart_tRCD 14160 ps$CustomPart_tREFI 7800000 ps$Custom +Part_tRFC 350000 ps$CustomPart_tRFC_dlr 110000 ps$CustomPart_tRP 14160 ps$CustomPart_tRRD_L 4900 ps$CustomPart_tRRD_S 3300 ps$CustomPart_tRRD_dlr 4 tck$CustomPart_tRTP 7500 ps$CustomPart_tWR 15000 ps$CustomPart_tWTR_L 7500 ps$CustomPart_tWTR_S 2500 ps$CustomPart_tXPR 360 ns$CustomPart_tZQCS 128 tck$CustomPart_tZQINIT 1024 tck$ + + + M_ADDN_UI_CLKOUT1_FREQ_HZ + CLKOUT1 FREQ HZ + 100 + + + M_ADDN_UI_CLKOUT2_FREQ_HZ + CLKOUT2 FREQ HZ + 0.0 + + + M_ADDN_UI_CLKOUT3_FREQ_HZ + CLKOUT3 FREQ HZ + 0.0 + + + M_ADDN_UI_CLKOUT4_FREQ_HZ + CLKOUT4 FREQ HZ + 0.0 + + + M_ADDN_UI_CLKOUT1_PHASE + CLKOUT1 PHASE + 0 + + + M_ADDN_UI_CLKOUT2_PHASE + CLKOUT2 PHASE + 0 + + + M_ADDN_UI_CLKOUT3_PHASE + CLKOUT3 PHASE + 0 + + + M_ADDN_UI_CLKOUT4_PHASE + CLKOUT4 PHASE + 0 + + + CLKOUT0_DIVIDE + CLKOUT0 DIVIDE + 0 + + + CLKOUT1_DIVIDE + CLKOUT1 DIVIDE + 15 + + + CLKOUT2_DIVIDE + CLKOUT2 DIVIDE + 0 + + + CLKOUT3_DIVIDE + CLKOUT3 DIVIDE + 0 + + + CLKOUT4_DIVIDE + CLKOUT4 DIVIDE + 0 + + + CLKOUT6_DIVIDE + CLKOUT6 DIVIDE + 0 + + + Debug_Signal + Disable + + + Simulation_Mode + Simulation Mode + BFM + + + C0.DDR4_Ecc + false + + + simulation.tlm + + + + + + + + choice_list_09ec3310 + Single + Dual + + + choice_list_157065e4 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + 30 + 31 + 32 + + + choice_list_266493f0 + DDR4_SDRAM + + + choice_list_28391b73 + 1.2V + + + choice_list_29a21725 + Custom + default_300mhz_clk0 + default_300mhz_clk1 + default_300mhz_clk2 + default_300mhz_clk3 + + + choice_list_2b96b8de + Differential + No_Buffer + + + choice_list_301b19dd + ON + OFF + + + choice_list_30636008 + 4:1 + + + choice_list_30de7c39 + Custom + pcie_perstn + resetn + + + choice_list_34c5244e + Components + UDIMMs + SODIMMs + RDIMMs + LRDIMMs + + + choice_list_3d7b6424 + 500 + 375 + 300 + 250 + 214 + 188 + 167 + 150 + 136 + 125 + 115 + 107 + 100 + 94 + 88 + 83 + 79 + 75 + 71 + 68 + 65 + 63 + 60 + 58 + 56 + 54 + 52 + 50 + 48 + 47 + 45 + 44 + 43 + 42 + 41 + 39 + 38 + 37 + 36 + 35 + 34 + 33 + 32 + 31 + 30 + 29 + 28 + 27 + 26 + 25 + 24 + 23 + 22 + 21 + 20 + 19 + 18 + 17 + 16 + 15 + 14 + 13 + 12 + None + + + choice_list_4665eb01 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_list_4bba4966 + 22 + + + choice_list_4e3dbc0a + SIMPLE_TG + ADVANCED_TG + + + choice_list_66456a11 + Custom + ddr4_sdram_c0 + ddr4_sdram_c1 + ddr4_sdram_c2 + ddr4_sdram_c3 + + + choice_list_67b045e5 + BFM + Unisim + + + choice_list_687ca1a5 + None + 500 + 375 + 300 + 250 + 214 + 188 + 167 + 150 + 136 + 125 + 115 + 107 + 100 + 94 + 88 + 83 + 79 + 75 + 71 + 68 + 65 + 63 + 60 + 58 + 56 + 54 + 52 + 50 + 48 + 47 + 45 + 44 + 43 + 42 + 41 + 39 + 38 + 37 + 36 + 35 + 34 + 33 + 32 + 31 + 30 + 29 + 28 + 27 + 26 + 25 + 24 + 23 + 22 + 21 + 20 + 19 + 18 + 17 + 16 + 15 + 14 + 13 + 12 + + + choice_list_87b2b38f + 24 + + + choice_list_8b4f223f + Strict + Normal + + + choice_list_98f5c8fa + RZQ/6 + + + choice_list_a187d5e4 + 512 + 1024 + + + choice_list_ad101c66 + RZQ/7 + RZQ/6 + + + choice_list_c89503c8 + ROW_BANK_COLUMN + BANK_ROW_COLUMN + ROW_COLUMN_BANK + ROW_COLUMN_BANK_INTLV + + + choice_list_c8951bc1 + NONE + + + choice_list_d1ecf361 + MTA18ASF1G72PDZ-2G1 + MTA9ASF51272PZ-2G1 + MTA18ASF2G72PDZ-2G3 + MTA9ASF1G72PZ-2G3 + M393A1G43DB1-CRC + MTA9ASF51272PZ-2G3 + DDR4_CUSTOM3 + DDR4_CUSTOM4 + MTA18ADF1G72PZ-2G1 + MTA18ASF1G72PZ-2G1 + MTA36ASF2G72PZ-2G1 + MTA18ASF2G72PZ-2G9 + MTA18ASF2G72PZ-2G3 + MTA36ASF4G72PZ-2G3 + M393A2G40DB1-CRC + M393A8K40B21-CTC + M393AAK40B41-CTC + M393A2K40BB1-CRC + DDR4_CUSTOM5 + 64GB + + + choice_list_d6556846 + 32 + 64 + 128 + 256 + 512 + + + choice_list_d8920bdd + 8 + + + choice_list_df7e3f8b + Sequential + Interleaved + + + choice_list_e7093afb + 25 + 26 + 27 + 28 + 29 + 30 + 31 + 32 + 33 + 34 + 35 + 36 + + + choice_list_ed30197c + TDM + ROUND_ROBIN + RD_PRI_REG + RD_PRI_REG_STARVE_LIMIT + WRITE_PRIORITY_REG + WRITE_PRIORITY + + + choice_list_ef319ec8 + Differential + Single_Ended + No_Buffer + + + choice_list_f3cd92fb + Disable + Enable + + + choice_list_fe2d3253 + 72 + + + choice_list_ff0950bb + 0 + CL-1 + CL-2 + + + choice_pairs_01257c99 + Complete_Memory_Controller + Phy_Only_Single + Phy_Only_PingPong + + + choice_pairs_05415bea + 14000 + 13999 + 13200 + 13199 + 12000 + 11999 + 10801 + 10800 + 10500 + 10499 + 10000 + 9601 + 9600 + 9599 + 9000 + 8999 + 8572 + 8571 + 8400 + 8399 + 8000 + 7715 + 7714 + 7501 + 7500 + 7499 + 7201 + 7200 + 7000 + 6999 + 6858 + 6857 + 6500 + 6499 + 6000 + 5999 + 5573 + 5572 + 5571 + 5401 + 5400 + 5335 + 5334 + 5333 + 5000 + 4876 + 4875 + 4801 + 4800 + 4715 + 4714 + 4667 + 4666 + 4573 + 4572 + 4571 + 4500 + 4499 + 4446 + 4445 + 4444 + 4401 + 4400 + 4286 + 4285 + 4223 + 4222 + 4126 + 4125 + 4124 + 4000 + 3858 + 3857 + 3779 + 3778 + 3777 + 3715 + 3714 + 3601 + 3600 + 3563 + 3562 + 3557 + 3556 + 3555 + 3500 + 3499 + 3429 + 3428 + 3335 + 3334 + 3333 + 3250 + 3249 + 3188 + 3187 + 3112 + 3111 + 3000 + 2999 + 2889 + 2888 + 2801 + 2800 + 2787 + 2786 + 2785 + 2751 + 2750 + 2701 + 2700 + 2668 + 2667 + 2666 + 2641 + 2640 + 2639 + 2625 + 2624 + 2572 + 2571 + 2500 + 2445 + 2444 + 2438 + 2437 + 2401 + 2400 + 2399 + 2334 + 2333 + 2287 + 2286 + 2250 + 2249 + 2223 + 2222 + 2201 + 2200 + 2161 + 2160 + 2143 + 2142 + 2112 + 2111 + 2100 + 2099 + 2063 + 2062 + 2000 + 1960 + 1959 + 1921 + 1920 + 1919 + 1890 + 1889 + 1888 + 1886 + 1885 + 1858 + 1857 + 1801 + 1800 + 1799 + 1782 + 1781 + 1779 + 1778 + 1777 + 1750 + 1749 + 1715 + 1714 + 1680 + 1679 + 1668 + 1667 + 1666 + 1625 + 1624 + 1600 + 1594 + 1593 + 1592 + 1591 + 1556 + 1555 + 1544 + 1543 + + + + + xilinx_elaboratesubcores_view_fileset + + ip_0/phy_ddr4_microblaze_mcs.xci + xci + + + ip_0/phy_ddr4_microblaze_mcs.xml + xml + + + ip_1/phy_ddr4_phy.xci + xci + + + ip_1/phy_ddr4_phy.xml + xml + + + + + + phy_ddr4 + + + + instance_path + inst/u_ddr_cal_riu/mcs0/inst/microblaze_I + + + bootloop_file + sw/calibration_0/Debug/calibration_ddr.elf + + + endian + little + + + processor_type + MICROBLAZE-LE + + + is_visible + false + + + + + DDR4 Interface Generator for Ultrascale Architecture + + + C0.ControllerType + DDR4_SDRAM + + + + false + + + + + + IOPowerReduction + OFF + + + Enable_SysPorts + Auto assign static ports + true + + + Phy_Only + Phy_Only_Single + + + RESET_BOARD_INTERFACE + Custom + + + + true + + + + + + C0_CLOCK_BOARD_INTERFACE + Custom + + + + true + + + + + + IS_FROM_PHY + 1 + + + RECONFIG_XSDB_SAVE_RESTORE + false + + + AL_SEL + 0 + + + Example_TG + SIMPLE_TG + + + + false + + + + + + C0.DDR4_Clamshell + false + + + + false + + + + + + C0.MIGRATION + false + + + TIMING_OP1 + false + + + TIMING_OP2 + false + + + TIMING_3DS + false + + + SET_DW_TO_40 + false + + + DIFF_TERM_SYSCLK + false + + + C0_DDR4_BOARD_INTERFACE + Custom + + + + true + + + + + + C0.DDR4_TimePeriod + 1500 + + + C0.DDR4_InputClockPeriod + 3333 + + + C0.DDR4_Specify_MandD + false + + + C0.DDR4_CLKFBOUT_MULT + 5 + + + + false + + + + + + C0.DDR4_DIVCLK_DIVIDE + 1 + + + + false + + + + + + C0.DDR4_CLKOUT0_DIVIDE + 9 + + + + false + + + + + + C0.DDR4_PhyClockRatio + 4:1 + + + C0.DDR4_MemoryType + RDIMMs + + + C0.DDR4_MemoryPart + 64GB + + + C0.DDR4_Slot + Single + + + C0.DDR4_MemoryVoltage + 1.2V + + + C0.DDR4_DataWidth + 72 + + + C0.DDR4_DataMask + NONE + + + + false + + + + + + C0.DDR4_Ecc + false + + + + false + + + + + + C0.DDR4_MCS_ECC + false + + + C0.DDR4_AxiSelection + false + + + + false + + + + + + C0.DDR4_AUTO_AP_COL_A3 + true + + + C0.DDR4_Ordering + Normal + + + C0.DDR4_BurstLength + 8 + + + + false + + + + + + C0.DDR4_BurstType + Sequential + + + C0.DDR4_OutputDriverImpedenceControl + RZQ/7 + + + C0.DDR4_OnDieTermination + RZQ/6 + + + C0.DDR4_CasLatency + 16 + + + C0.DDR4_CasWriteLatency + 14 + + + C0.DDR4_ChipSelect + true + + + + false + + + + + + C0.DDR4_isCKEShared + false + + + C0.DDR4_AxiDataWidth + 512 + + + C0.DDR4_AxiArbitrationScheme + RD_PRI_REG + + + C0.DDR4_AxiNarrowBurst + false + + + C0.DDR4_AxiAddressWidth + 34 + + + C0.DDR4_AxiIDWidth + 4 + + + C0.DDR4_Capacity + 512 + + + C0.DDR4_Mem_Add_Map + ROW_COLUMN_BANK + + + C0.DDR4_MemoryName + MainMemory + + + C0.DDR4_AutoPrecharge + false + + + + false + + + + + + C0.DDR4_UserRefresh_ZQCS + false + + + + false + + + + + + C0.DDR4_CustomParts + ../../../../custom_parts_ddr4_2016_4_and_above.csv + + + file_csv + + + + + C0.DDR4_isCustom + true + + + C0.DDR4_SELF_REFRESH + false + + + + false + + + + + + C0.DDR4_SAVE_RESTORE + false + + + C0.DDR4_RESTORE_CRC + false + + + + false + + + + + + ADDN_UI_CLKOUT1_FREQ_HZ + 100 + + + ADDN_UI_CLKOUT2_FREQ_HZ + None + + + ADDN_UI_CLKOUT3_FREQ_HZ + None + + + ADDN_UI_CLKOUT4_FREQ_HZ + None + + + CLKOUT6 + false + + + Component_Name + phy_ddr4 + + + No_Controller + 1 + + + System_Clock + Differential + + + Reference_Clock + Differential + + + Debug_Signal + Disable + + + IO_Power_Reduction + IO_Power_Reduction + false + + + DCI_Cascade + DCI Cascade + false + + + Default_Bank_Selections + Default Bank Selections + false + + + Simulation_Mode + BFM + + + PARTIAL_RECONFIG_FLOW_MIG + false + + + + false + + + + + + MCS_DBG_EN + false + + + C0.DDR4_CK_SKEW_0 + 0 + + + C0.DDR4_CK_SKEW_1 + 0 + + + C0.DDR4_CK_SKEW_2 + 0 + + + C0.DDR4_CK_SKEW_3 + 0 + + + C0.DDR4_ADDR_SKEW_0 + 0 + + + C0.DDR4_ADDR_SKEW_1 + 0 + + + C0.DDR4_ADDR_SKEW_2 + 0 + + + C0.DDR4_ADDR_SKEW_3 + 0 + + + C0.DDR4_ADDR_SKEW_4 + 0 + + + C0.DDR4_ADDR_SKEW_5 + 0 + + + C0.DDR4_ADDR_SKEW_6 + 0 + + + C0.DDR4_ADDR_SKEW_7 + 0 + + + C0.DDR4_ADDR_SKEW_8 + 0 + + + C0.DDR4_ADDR_SKEW_9 + 0 + + + C0.DDR4_ADDR_SKEW_10 + 0 + + + C0.DDR4_ADDR_SKEW_11 + 0 + + + C0.DDR4_ADDR_SKEW_12 + 0 + + + C0.DDR4_ADDR_SKEW_13 + 0 + + + C0.DDR4_ADDR_SKEW_14 + 0 + + + C0.DDR4_ADDR_SKEW_15 + 0 + + + C0.DDR4_ADDR_SKEW_16 + 0 + + + C0.DDR4_ADDR_SKEW_17 + 0 + + + C0.DDR4_BA_SKEW_0 + 0 + + + C0.DDR4_BA_SKEW_1 + 0 + + + C0.DDR4_BG_SKEW_0 + 0 + + + C0.DDR4_BG_SKEW_1 + 0 + + + C0.DDR4_CS_SKEW_0 + 0 + + + C0.DDR4_CS_SKEW_1 + 0 + + + C0.DDR4_CS_SKEW_2 + 0 + + + C0.DDR4_CS_SKEW_3 + 0 + + + C0.DDR4_CKE_SKEW_0 + 0 + + + C0.DDR4_CKE_SKEW_1 + 0 + + + C0.DDR4_CKE_SKEW_2 + 0 + + + C0.DDR4_CKE_SKEW_3 + 0 + + + C0.DDR4_ACT_SKEW + 0 + + + C0.DDR4_PAR_SKEW + 0 + + + C0.DDR4_ODT_SKEW_0 + 0 + + + C0.DDR4_ODT_SKEW_1 + 0 + + + C0.DDR4_ODT_SKEW_2 + 0 + + + C0.DDR4_ODT_SKEW_3 + 0 + + + C0.DDR4_LR_SKEW_0 + 0 + + + C0.DDR4_LR_SKEW_1 + 0 + + + C0.DDR4_TREFI + 0 + + + C0.DDR4_TRFC + 0 + + + C0.DDR4_TRFC_DLR + 0 + + + C0.DDR4_TXPR + 0 + + + C0.DDR4_nCK_TREFI + 0 + + + C0.DDR4_nCK_TRFC + 0 + + + C0.DDR4_nCK_TRFC_DLR + 0 + + + C0.DDR4_nCK_TXPR + 5 + + + C0.ADDR_WIDTH + ADDR WIDTH + 18 + + + C0.BANK_GROUP_WIDTH + BANK GROUP WIDTH + 2 + + + C0.LR_WIDTH + LR WIDTH + 1 + + + C0.CK_WIDTH + CK WIDTH + 1 + + + C0.CKE_WIDTH + CKE WIDTH + 1 + + + C0.CS_WIDTH + CS WIDTH + 1 + + + C0.ODT_WIDTH + ODT WIDTH + 1 + + + C0.StackHeight + 1 + + + PING_PONG_PHY + Ping Pong Phy + 1 + + + C0.DDR4_Enable_LVAUX + false + + + C0.DDR4_EN_PARITY + true + + + EN_PP_4R_MIR + false + + + + + DDR4 SDRAM (MIG) + + xtlm + protobuf + sim_ddr_v1_0 + + 10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig new file mode 100644 index 0000000..698f7e5 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig @@ -0,0 +1,313 @@ +/****************************************************************************** +// (c) Copyright 2013 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +******************************************************************************/ +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 1.1 +// \ \ Application : MIG +// / / Filename : ddr4_v2_2_10_cal_rd_en.sv +// /___/ /\ Date Last Modified : $Date: 2015/04/23 $ +// \ \ / \ Date Created : Thu Apr 18 2013 +// \___\/\___\ +// +// Device : UltraScale +// Design Name : DDR4 SDRAM & DDR3 SDRAM +// Purpose : +// ddr4_v2_2_10_cal_rd_en module +// Reference : +// Revision History : +//***************************************************************************** + +`timescale 1ns/100ps + +module ddr4_v2_2_10_cal_rd_en #(parameter + RANKS = 1 + ,RL = 11 + ,EXTRA_CMD_DELAY = 0 + ,TCQ = 0.1 +)( + input clk + ,input rst + + ,output [3:0] mc_clb2phy_rden + ,output [3:0] mc_clb2phy_rdcs0 + ,output [3:0] mc_clb2phy_rdcs1 + + ,input [1:0] casSlot // spyglass disable W498 + ,input mccasSlot2 + ,input rdCAS + ,input calrdCAS + ,input mcrdCAS + ,input [5:0] mCL0 + ,input [5:0] mCL1 + ,input [5:0] mCL2 + ,input [5:0] mCL3 + ,input [1:0] winRank + ,input [1:0] calRank + ,input [1:0] mcwinRank + ,input calDone +); + +wire [5:0] mCL[0:3]; +assign mCL[0] = mCL0; +assign mCL[1] = mCL1; +assign mCL[2] = mCL2; +assign mCL[3] = mCL3; + +// This section generates the Gate enable mc_clb2phy_rden. +// This logic is used in calibration and during normal operation. +// Case 4'b0110 defines nominal timing where the trained mCL value equals RL. +// This logic supports mCL = RL - 3, to enable the Gate 3tCK earlier than nominal RL. +// Early gate enable is needed in Gate training, during normal operation +// if command delays are very low, and to compensate for extra Gate delay +// in the XiPhy that is allocated for VT tracking. The logic also supports Gate +// enable 4tCK later than nominal to allow for command fly-by routing. +// The Gate enable can be further delayed to allow for extra command pipeline delays. +// The Gate enable supports RL as low as 7 with no extra command delays, but other +// blocks have higher low limits, so the minimum RL without extra command delays +// is expected to be RL=8. + +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn; +(* KEEP = "true" *) reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt; +reg [18:0] rsMask[0:7]; + +function [18:0] rs2mask; + input [3:0] diff; + input slot2; +case ({diff, slot2}) + 5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111; + 5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100; + 5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110; + 5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000; + 5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100; + 5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000; + 5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000; + 5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000; + 5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000; + 5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000; + 5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000; + 5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000; + 5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000; + 5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000; + 5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000; + 5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000; + 5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000; + 5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000; + 5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000; + 5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000; + 5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000; + 5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000; + 5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000; + 5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000; + 5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000; + 5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000; + 5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000; + 5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000; + default: rs2mask = 19'b000_0000_1000_0000_1111; +endcase +endfunction + +always @(posedge clk) begin: blk1 + reg [3:0] rsNdx; + for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1) + rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]); +end + +always @(*) if (rst) begin + rdEn_nxt = 'b0; +end else begin + rdEn_nxt = (rdEn >> 4) + | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} + : 'b0); +end + +always @(posedge clk) + rdEn <= #TCQ rdEn_nxt; + +assign mc_clb2phy_rden = rdEn[3:0]; + +/////////////////////////////////////////////////////////////////// +// This logic is used during normal, multi-rank operation only. Durring cal or single +// rank operation this logic is bypassed and the output of this section is static. +// This section generates the read rank signals used by the XiPhy to select per rank +// cal values during read operations. + +integer tck_index; +localparam rdcs_msb = RL + 8 + 4*EXTRA_CMD_DELAY; + +reg [rdcs_msb :0] rdcs0; +reg [rdcs_msb :0] rdcs0_mc; +reg [rdcs_msb :0] rdcs1; +reg [rdcs_msb :0] rdcs1_mc; +reg [6:0] rdcs_rdcas_lsb_slot0; +reg calDone_dly; + +// Extend newest cs (MSB) and shift out the oldest (low 4 LSBs) +wire [rdcs_msb :0] rdcs0_shift = { { 4 { rdcs0[rdcs_msb] } }, rdcs0[ rdcs_msb : 4] }; +wire [rdcs_msb :0] rdcs1_shift = { { 4 { rdcs1[rdcs_msb] } }, rdcs1[ rdcs_msb : 4] }; + +// Create rdcs mask for the current rdcas +wire [6:0] rdcs_rdcas_lsb_slot0_nxt = { 1'b0, mCL0 } + 4*EXTRA_CMD_DELAY - 7'd7; +wire [rdcs_msb :0] rdcs_rdcas_mask_slot0 = { ( rdcs_msb + 1 ) { 1'b1 } } << rdcs_rdcas_lsb_slot0; +wire [rdcs_msb :0] rdcs_rdcas_mask = rdcs_rdcas_mask_slot0 << 2*mccasSlot2; + +// Merge the shifted rdcs and winRank based on the rdcs mask for the current rdcas +always @(*) begin + for (tck_index = 0; tck_index <= rdcs_msb; tck_index = tck_index + 1) begin + rdcs0_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[0] : rdcs0_shift[tck_index]; + rdcs1_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[1] : rdcs1_shift[tck_index]; + end +end + +// Select mc or cal rdcs +wire [rdcs_msb :0] rdcs0_nxt = calDone_dly ? rdcs0_mc : { rdcs_msb+1 { calRank[0] } }; +wire [rdcs_msb :0] rdcs1_nxt = calDone_dly ? rdcs1_mc : { rdcs_msb+1 { calRank[1] } }; + +// Final 4 bit rdcs output +assign mc_clb2phy_rdcs0 = rdcs0[3:0] & ~{ 4 { RANKS == 1 } }; +assign mc_clb2phy_rdcs1 = rdcs1[3:0] & ~{ 4 { RANKS == 1 } }; + +// Flops +always @(posedge clk) begin + rdcs_rdcas_lsb_slot0 <= #TCQ rdcs_rdcas_lsb_slot0_nxt; + calDone_dly <= #TCQ calDone; +end + +// Reset flops +always @(posedge clk) if (rst) begin + rdcs0 <= #TCQ '0; + rdcs1 <= #TCQ '0; +end else begin + rdcs0 <= #TCQ rdcs0_nxt; + rdcs1 <= #TCQ rdcs1_nxt; +end + + +//synopsys translate_off + +`ifdef MEM_INTERNAL +// Events - When asserted high in a test that passes all verification checks, these coverage +// properties indicate that a functional coverage event has been hit. +// --------------------------------------------------------------------------------------------- + +// Minimum mCL in normal operation +//wire e_mc_rd_en_000 = ( ( mCL0 + 4*EXTRA_CMD_DELAY ) == 13 ) & calDone & ~( RANKS == 1 ) & rdCAS; +//always @(posedge clk) mc_rd_en_000: if (~rst) cover property (e_mc_rd_en_000); + + +// Asserts - When asserted high, an illegal condition has been detected and the test has failed. +// --------------------------------------------------------------------------------------------- + +// Check for illegal rank switch in rdEn and rdcs. rdEn gap must be at least 2tCK wide. rdcs must be stable for 2tCK after rdEn de-assertion. +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdEn; +reg [rdcs_msb :0] a_rdcs0_dly; +reg [rdcs_msb :0] a_rdcs1_dly; +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0; +wire [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0_nxt = { rdcs0, a_rdcs0_dly[3:0] }; +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1; +wire [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1_nxt = { rdcs1, a_rdcs1_dly[3:0] }; +wire [RL+12 + 4*EXTRA_CMD_DELAY -1 :0] a_rdEn_falling_edge = ~a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY :1] & a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY -1 :0]; +reg [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold0_fail; +reg [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold1_fail; +reg [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_gap_fail; +always @(*) begin + for (tck_index = 0; tck_index < RL+12 + 4*EXTRA_CMD_DELAY -2; tck_index = tck_index + 1) begin + a_rdEn_hold0_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+1] ) | ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+2] ) ); + a_rdEn_hold1_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+1] ) | ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+2] ) ); + a_rdEn_gap_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & a_rdEn[tck_index+2]; + end +end +always @(posedge clk) if (rst) begin + a_rdEn <= #TCQ '0; + a_rdcs0_dly <= #TCQ '0; + a_rdcs1_dly <= #TCQ '0; + a_rdcs0 <= #TCQ '0; + a_rdcs1 <= #TCQ '0; +end else begin + a_rdEn <= #TCQ rdEn; + a_rdcs0_dly <= #TCQ rdcs0; + a_rdcs1_dly <= #TCQ rdcs1; + a_rdcs0 <= #TCQ a_rdcs0_nxt; + a_rdcs1 <= #TCQ a_rdcs1_nxt; +end + +// rdcs0 not held for 2tCK after end of burst +wire a_mc_rd_en_000_hld = calDone & ( | a_rdEn_hold0_fail ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_000_hld); + +// rdcs1 not held for 2tCK after end of burst +wire a_mc_rd_en_001_hld = calDone & ( | a_rdEn_hold1_fail ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_001_hld); + +// rdEn not held low for 2tCK after end of burst +wire a_mc_rd_en_002_hld = calDone & ( | a_rdEn_gap_fail ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_002_hld); + +// mCL0 is less than RL-3 +wire a_mc_rd_en_003_ovf = ( mCL0 < (RL - 3) ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_003_ovf); + +// mCL1 is less than RL-3 +wire a_mc_rd_en_004_ovf = ( mCL1 < (RL - 3) ) & ( mCL1 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_004_ovf); + +// mCL2 is less than RL-3 +wire a_mc_rd_en_005_ovf = ( mCL2 < (RL - 3) ) & ( mCL2 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_005_ovf); + +// mCL3 is less than RL-3 +wire a_mc_rd_en_006_ovf = ( mCL3 < (RL - 3) ) & ( mCL3 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_006_ovf); + + +`endif +//synopsys translate_on + +endmodule + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej new file mode 100644 index 0000000..29c4462 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej @@ -0,0 +1,124 @@ +--- U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv ++++ /dev/null +@@ -114,55 +114,86 @@ + + reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn; + (* KEEP = "true" *) reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt; +-reg [18:0] rsMask[0:7]; ++reg [19:0] rsMask[0:15]; + +-function [18:0] rs2mask; ++// RS probably stands for rank select. ++// TODO edit below in worst case. ++function [19:0] rs2mask; + input [3:0] diff; + input slot2; +-case ({diff, slot2}) +- 5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111; +- 5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110; +- 5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000; +- 5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000; ++ input slot1; ++case ({diff, slot2, slot1}) ++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111; ++ 6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000; + default: rs2mask = 19'b000_0000_1000_0000_1111; + endcase + endfunction + + always @(posedge clk) begin: blk1 +- reg [3:0] rsNdx; +- for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1) +- rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]); ++ reg [4:0] rsNdx; ++ for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1) ++ rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]); + end + + always @(*) if (rst) begin + rdEn_nxt = 'b0; + end else begin + rdEn_nxt = (rdEn >> 4) +- | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} ++ | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} + : 'b0); + end + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv.rej new file mode 100644 index 0000000..76c333f --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv.rej @@ -0,0 +1,31 @@ +--- U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv ++++ /dev/null +@@ -157,9 +157,13 @@ + // used in pushing new write CAS commands into the wrQ shift register. These values are + // calculated for both casslot0 and casslot2. + localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2; ++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2; + localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2; ++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2; + localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4; ++localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4; + localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4; ++localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4; + + integer i; + +@@ -192,10 +196,12 @@ + // Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical. + reg [3:0] oe_0_mux_cal; + wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2; +-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal; ++wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) : ++ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal); + + // tCK offset for mc. mccasSlot2 is timing critical. +-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0; ++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) : ++ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0); + + // Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical. + wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1}; diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd new file mode 100644 index 0000000..88c7541 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd @@ -0,0 +1,513 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0xBCE55F3980178BC9", + "design_src": "SBD", + "device": "xcu200-fsgd2104-2-e", + "name": "bd_ba6a", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "scoped": "true", + "synth_flow_mode": "None", + "tool_version": "2020.2", + "validated": "true" + }, + "design_tree": { + "microblaze_I": "", + "rst_0": "", + "ilmb": "", + "dlmb": "", + "dlmb_cntlr": "", + "ilmb_cntlr": "", + "lmb_bram_I": "", + "second_dlmb_cntlr": "", + "second_ilmb_cntlr": "", + "second_lmb_bram_I": "", + "iomodule_0": "" + }, + "interface_ports": { + "IO": { + "mode": "Master", + "vlnv": "xilinx.com:interface:mcsio_bus_rtl:1.0" + }, + "TRACE": { + "mode": "Master", + "vlnv": "xilinx.com:interface:mbtrace_rtl:2.0" + } + }, + "ports": { + "Clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_ASYNC_RESET": { + "value": "Reset" + }, + "CLK_DOMAIN": { + "value": "bd_ba6a_Clk", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000", + "value_src": "default" + } + } + }, + "Reset": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_HIGH" + } + } + } + }, + "components": { + "microblaze_I": { + "vlnv": "xilinx.com:ip:microblaze:11.0", + "xci_name": "bd_ba6a_microblaze_I_0", + "parameters": { + "C_ASYNC_WAKEUP": { + "value": "3" + }, + "C_DEBUG_ENABLED": { + "value": "0" + }, + "C_FAULT_TOLERANT": { + "value": "0" + }, + "C_INSTANCE": { + "value": "mb_microblaze_0" + }, + "C_PC_WIDTH": { + "value": "17" + }, + "C_TRACE": { + "value": "1" + }, + "C_USE_BARREL": { + "value": "1" + }, + "C_USE_DIV": { + "value": "1" + }, + "C_USE_EXT_BRK": { + "value": "0" + }, + "C_USE_EXT_NM_BRK": { + "value": "0" + }, + "C_USE_HW_MUL": { + "value": "1" + }, + "C_USE_PCMP_INSTR": { + "value": "1" + }, + "C_USE_REORDER_INSTR": { + "value": "0" + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32" + }, + "Instruction": { + "range": "4G", + "width": "32" + } + } + }, + "interface_ports": { + "DLMB": { + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "ILMB": { + "mode": "Master", + "address_space_ref": "Instruction", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + } + }, + "hdl_attributes": { + "BMM_INFO_PROCESSOR": { + "value": "microblaze-le > bd_ba6a dlmb_cntlr", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "rst_0": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "bd_ba6a_rst_0_0" + }, + "ilmb": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "bd_ba6a_ilmb_0", + "parameters": { + "C_LMB_NUM_SLAVES": { + "value": "2" + } + }, + "interface_ports": { + "LMB_M": { + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0", + "LMB_Sl_1" + ] + } + } + }, + "dlmb": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "bd_ba6a_dlmb_0", + "parameters": { + "C_LMB_NUM_SLAVES": { + "value": "3" + } + }, + "interface_ports": { + "LMB_M": { + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0", + "LMB_Sl_1", + "LMB_Sl_2" + ] + } + } + }, + "dlmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_ba6a_dlmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000000000" + }, + "C_HIGHADDR": { + "value": "0x000000000000FFFF" + }, + "C_MASK": { + "value": "0x00000000C0010000" + } + }, + "hdl_attributes": { + "BMM_INFO_ADDRESS_SPACE": { + "value": "byte 0x00000000 32 > bd_ba6a lmb_bram_I bd_ba6a second_lmb_bram_I", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "ilmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_ba6a_ilmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000000000" + }, + "C_HIGHADDR": { + "value": "0x000000000000FFFF" + }, + "C_MASK": { + "value": "0x0000000080010000" + } + } + }, + "lmb_bram_I": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "bd_ba6a_lmb_bram_I_0", + "parameters": { + "Memory_Type": { + "value": "True_Dual_Port_RAM" + } + } + }, + "second_dlmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_ba6a_second_dlmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000010000" + }, + "C_HIGHADDR": { + "value": "0x0000000000017FFF" + }, + "C_MASK": { + "value": "0x00000000C0010000" + } + }, + "hdl_attributes": { + "BMM_INFO_ADDRESS_RANGE": { + "value": " ", + "value_src": "default" + } + } + }, + "second_ilmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_ba6a_second_ilmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000010000" + }, + "C_HIGHADDR": { + "value": "0x0000000000017FFF" + }, + "C_MASK": { + "value": "0x0000000080010000" + } + } + }, + "second_lmb_bram_I": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "bd_ba6a_second_lmb_bram_I_0", + "parameters": { + "Memory_Type": { + "value": "True_Dual_Port_RAM" + } + } + }, + "iomodule_0": { + "vlnv": "xilinx.com:ip:iomodule:3.1", + "xci_name": "bd_ba6a_iomodule_0_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000080000000" + }, + "C_HIGHADDR": { + "value": "0x000000008000FFFF" + }, + "C_INSTANCE": { + "value": "iomodule" + }, + "C_INTC_ADDR_WIDTH": { + "value": "17" + }, + "C_INTC_HAS_FAST": { + "value": "1" + }, + "C_INTC_USE_IRQ_OUT": { + "value": "1" + }, + "C_IO_BASEADDR": { + "value": "0x00000000C0000000" + }, + "C_IO_HIGHADDR": { + "value": "0x00000000FFFFFFFF" + }, + "C_IO_MASK": { + "value": "0x00000000C0000000" + }, + "C_MASK": { + "value": "0x00000000C0000000" + }, + "C_USE_IO_BUS": { + "value": "1" + } + } + } + }, + "interface_nets": { + "dlmb_port": { + "interface_ports": [ + "dlmb_cntlr/BRAM_PORT", + "lmb_bram_I/BRAM_PORTA" + ] + }, + "dlmb_sl_0": { + "interface_ports": [ + "dlmb/LMB_Sl_0", + "dlmb_cntlr/SLMB" + ] + }, + "dlmb_sl_2": { + "interface_ports": [ + "dlmb/LMB_Sl_2", + "second_dlmb_cntlr/SLMB" + ] + }, + "ilmb_port": { + "interface_ports": [ + "ilmb_cntlr/BRAM_PORT", + "lmb_bram_I/BRAM_PORTB" + ] + }, + "dlmb_sl_1": { + "interface_ports": [ + "dlmb/LMB_Sl_1", + "iomodule_0/SLMB" + ] + }, + "microblaze_I_Trace": { + "interface_ports": [ + "TRACE", + "microblaze_I/TRACE" + ] + }, + "ilmb_port_2": { + "interface_ports": [ + "second_ilmb_cntlr/BRAM_PORT", + "second_lmb_bram_I/BRAM_PORTB" + ] + }, + "ilmb": { + "interface_ports": [ + "microblaze_I/ILMB", + "ilmb/LMB_M" + ] + }, + "ilmb_sl_0": { + "interface_ports": [ + "ilmb/LMB_Sl_0", + "ilmb_cntlr/SLMB" + ] + }, + "ilmb_sl_1": { + "interface_ports": [ + "ilmb/LMB_Sl_1", + "second_ilmb_cntlr/SLMB" + ] + }, + "dlmb_port_2": { + "interface_ports": [ + "second_dlmb_cntlr/BRAM_PORT", + "second_lmb_bram_I/BRAM_PORTA" + ] + }, + "dlmb": { + "interface_ports": [ + "microblaze_I/DLMB", + "dlmb/LMB_M" + ] + }, + "iomodule_0_IO": { + "interface_ports": [ + "IO", + "iomodule_0/IO_BUS" + ] + } + }, + "nets": { + "Clk2": { + "ports": [ + "Clk", + "microblaze_I/Clk", + "ilmb/LMB_Clk", + "dlmb/LMB_Clk", + "dlmb_cntlr/LMB_Clk", + "ilmb_cntlr/LMB_Clk", + "second_dlmb_cntlr/LMB_Clk", + "second_ilmb_cntlr/LMB_Clk", + "iomodule_0/Clk", + "rst_0/slowest_sync_clk" + ] + }, + "Reset": { + "ports": [ + "Reset", + "rst_0/ext_reset_in" + ] + }, + "MB_Reset": { + "ports": [ + "rst_0/mb_reset", + "microblaze_I/Reset" + ] + }, + "LMB_Rst2": { + "ports": [ + "rst_0/bus_struct_reset", + "ilmb/SYS_Rst", + "dlmb/SYS_Rst", + "ilmb_cntlr/LMB_Rst", + "dlmb_cntlr/LMB_Rst", + "second_ilmb_cntlr/LMB_Rst", + "second_dlmb_cntlr/LMB_Rst" + ] + }, + "IO_Rst": { + "ports": [ + "rst_0/peripheral_reset", + "iomodule_0/Rst" + ] + } + }, + "addressing": { + "/microblaze_I": { + "address_spaces": { + "Data": { + "segments": { + "SEG_dlmb_cntlr_Mem": { + "address_block": "/dlmb_cntlr/SLMB/Mem", + "offset": "0x00000000", + "range": "64K" + }, + "SEG_iomodule_0_IO": { + "address_block": "/iomodule_0/SLMB/IO", + "offset": "0xC0000000", + "range": "1G" + }, + "SEG_iomodule_0_Reg": { + "address_block": "/iomodule_0/SLMB/Reg", + "offset": "0x80000000", + "range": "64K" + }, + "SEG_second_dlmb_cntlr_Mem": { + "address_block": "/second_dlmb_cntlr/SLMB/Mem", + "offset": "0x00010000", + "range": "32K" + } + } + }, + "Instruction": { + "segments": { + "SEG_ilmb_cntlr_Mem": { + "address_block": "/ilmb_cntlr/SLMB/Mem", + "offset": "0x00000000", + "range": "64K" + }, + "SEG_second_ilmb_cntlr_Mem": { + "address_block": "/second_ilmb_cntlr/SLMB/Mem", + "offset": "0x00010000", + "range": "32K" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml new file mode 100644 index 0000000..dddba12 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml @@ -0,0 +1,100 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v new file mode 100644 index 0000000..62aef3f --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v @@ -0,0 +1,173 @@ +//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Command: generate_target bd_ba6a_wrapper.bd +//Design : bd_ba6a_wrapper +//Purpose: IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module bd_ba6a_wrapper + (Clk, + IO_addr_strobe, + IO_address, + IO_byte_enable, + IO_read_data, + IO_read_strobe, + IO_ready, + IO_write_data, + IO_write_strobe, + Reset, + TRACE_data_access, + TRACE_data_address, + TRACE_data_byte_enable, + TRACE_data_read, + TRACE_data_write, + TRACE_data_write_value, + TRACE_dcache_hit, + TRACE_dcache_rdy, + TRACE_dcache_read, + TRACE_dcache_req, + TRACE_delay_slot, + TRACE_ex_piperun, + TRACE_exception_kind, + TRACE_exception_taken, + TRACE_icache_hit, + TRACE_icache_rdy, + TRACE_icache_req, + TRACE_instruction, + TRACE_jump_hit, + TRACE_jump_taken, + TRACE_mb_halted, + TRACE_mem_piperun, + TRACE_msr_reg, + TRACE_new_reg_value, + TRACE_of_piperun, + TRACE_pc, + TRACE_pid_reg, + TRACE_reg_addr, + TRACE_reg_write, + TRACE_valid_instr); + input Clk; + output IO_addr_strobe; + output [31:0]IO_address; + output [3:0]IO_byte_enable; + input [31:0]IO_read_data; + output IO_read_strobe; + input IO_ready; + output [31:0]IO_write_data; + output IO_write_strobe; + input Reset; + output TRACE_data_access; + output [0:31]TRACE_data_address; + output [0:3]TRACE_data_byte_enable; + output TRACE_data_read; + output TRACE_data_write; + output [0:31]TRACE_data_write_value; + output TRACE_dcache_hit; + output TRACE_dcache_rdy; + output TRACE_dcache_read; + output TRACE_dcache_req; + output TRACE_delay_slot; + output TRACE_ex_piperun; + output [0:4]TRACE_exception_kind; + output TRACE_exception_taken; + output TRACE_icache_hit; + output TRACE_icache_rdy; + output TRACE_icache_req; + output [0:31]TRACE_instruction; + output TRACE_jump_hit; + output TRACE_jump_taken; + output TRACE_mb_halted; + output TRACE_mem_piperun; + output [0:14]TRACE_msr_reg; + output [0:31]TRACE_new_reg_value; + output TRACE_of_piperun; + output [0:31]TRACE_pc; + output [0:7]TRACE_pid_reg; + output [0:4]TRACE_reg_addr; + output TRACE_reg_write; + output TRACE_valid_instr; + + wire Clk; + wire IO_addr_strobe; + wire [31:0]IO_address; + wire [3:0]IO_byte_enable; + wire [31:0]IO_read_data; + wire IO_read_strobe; + wire IO_ready; + wire [31:0]IO_write_data; + wire IO_write_strobe; + wire Reset; + wire TRACE_data_access; + wire [0:31]TRACE_data_address; + wire [0:3]TRACE_data_byte_enable; + wire TRACE_data_read; + wire TRACE_data_write; + wire [0:31]TRACE_data_write_value; + wire TRACE_dcache_hit; + wire TRACE_dcache_rdy; + wire TRACE_dcache_read; + wire TRACE_dcache_req; + wire TRACE_delay_slot; + wire TRACE_ex_piperun; + wire [0:4]TRACE_exception_kind; + wire TRACE_exception_taken; + wire TRACE_icache_hit; + wire TRACE_icache_rdy; + wire TRACE_icache_req; + wire [0:31]TRACE_instruction; + wire TRACE_jump_hit; + wire TRACE_jump_taken; + wire TRACE_mb_halted; + wire TRACE_mem_piperun; + wire [0:14]TRACE_msr_reg; + wire [0:31]TRACE_new_reg_value; + wire TRACE_of_piperun; + wire [0:31]TRACE_pc; + wire [0:7]TRACE_pid_reg; + wire [0:4]TRACE_reg_addr; + wire TRACE_reg_write; + wire TRACE_valid_instr; + + bd_ba6a bd_ba6a_i + (.Clk(Clk), + .IO_addr_strobe(IO_addr_strobe), + .IO_address(IO_address), + .IO_byte_enable(IO_byte_enable), + .IO_read_data(IO_read_data), + .IO_read_strobe(IO_read_strobe), + .IO_ready(IO_ready), + .IO_write_data(IO_write_data), + .IO_write_strobe(IO_write_strobe), + .Reset(Reset), + .TRACE_data_access(TRACE_data_access), + .TRACE_data_address(TRACE_data_address), + .TRACE_data_byte_enable(TRACE_data_byte_enable), + .TRACE_data_read(TRACE_data_read), + .TRACE_data_write(TRACE_data_write), + .TRACE_data_write_value(TRACE_data_write_value), + .TRACE_dcache_hit(TRACE_dcache_hit), + .TRACE_dcache_rdy(TRACE_dcache_rdy), + .TRACE_dcache_read(TRACE_dcache_read), + .TRACE_dcache_req(TRACE_dcache_req), + .TRACE_delay_slot(TRACE_delay_slot), + .TRACE_ex_piperun(TRACE_ex_piperun), + .TRACE_exception_kind(TRACE_exception_kind), + .TRACE_exception_taken(TRACE_exception_taken), + .TRACE_icache_hit(TRACE_icache_hit), + .TRACE_icache_rdy(TRACE_icache_rdy), + .TRACE_icache_req(TRACE_icache_req), + .TRACE_instruction(TRACE_instruction), + .TRACE_jump_hit(TRACE_jump_hit), + .TRACE_jump_taken(TRACE_jump_taken), + .TRACE_mb_halted(TRACE_mb_halted), + .TRACE_mem_piperun(TRACE_mem_piperun), + .TRACE_msr_reg(TRACE_msr_reg), + .TRACE_new_reg_value(TRACE_new_reg_value), + .TRACE_of_piperun(TRACE_of_piperun), + .TRACE_pc(TRACE_pc), + .TRACE_pid_reg(TRACE_pid_reg), + .TRACE_reg_addr(TRACE_reg_addr), + .TRACE_reg_write(TRACE_reg_write), + .TRACE_valid_instr(TRACE_valid_instr)); +endmodule diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci new file mode 100644 index 0000000..7bd31b9 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci @@ -0,0 +1,1032 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_microblaze_I_0 + + + bd_ba6a_Clk + 100000000 + 0 + 0 + 0.000 + + 30000000 + 0 + 0 + 0.000 + 1 + 32 + 0 + LEVEL_HIGH + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 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Enable Fault Tolerance Support + 0 + + + C_ECC_USE_CE_EXCEPTION + Correctable Error Exception + 0 + + + C_LOCKSTEP_SLAVE + Lockstep Slave + 0 + + + C_LOCKSTEP_MASTER + Lockstep Master + 0 + + + C_ENDIANNESS + 1 + + + C_FAMILY + virtexuplus + + + C_DATA_SIZE + 32 + + + C_LMB_DATA_SIZE + 32 + + + C_INSTR_SIZE + 32 + + + C_IADDR_SIZE + 32 + + + C_PIADDR_SIZE + 32 + + + C_DADDR_SIZE + 32 + + + C_INSTANCE + bd_ba6a_microblaze_I_0 + + + C_AVOID_PRIMITIVES + 0 + + + C_AREA_OPTIMIZED + Select implementation optimization + 0 + + + C_OPTIMIZATION + 0 + + + C_INTERCONNECT + Select Bus Interface + 2 + + + C_BASE_VECTORS + Vector Base Address + 0x0000000000000000 + + + C_M_AXI_DP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_M_AXI_D_BUS_EXCEPTION + Enable Data-side AXI Exception + 0 + + + + true + + + + + + C_M_AXI_IP_THREAD_ID_WIDTH + 1 + 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Reversed Load/Store and Swap Instructions + 0 + + + C_UNALIGNED_EXCEPTIONS + Enable Unaligned Data Exception + 0 + + + C_ILL_OPCODE_EXCEPTION + Enable Illegal Instruction Exception + 0 + + + C_DIV_ZERO_EXCEPTION + Enable Integer Divide Exception + 0 + + + + true + + + + + + C_FPU_EXCEPTION + Enable Floating Point Unit Exceptions + 0 + + + + false + + + + + + C_FSL_LINKS + Number of Stream Links + 0 + + + C_USE_EXTENDED_FSL_INSTR + Enable Additional Stream Instructions + 0 + + + C_FSL_EXCEPTION + Enable Stream Exception + 0 + + + + false + + + + + + C_USE_STACK_PROTECTION + Enable stack protection + 0 + + + + true + + + + + + C_IMPRECISE_EXCEPTIONS + Allow Imprecise Exceptions + 0 + + + C_USE_INTERRUPT + 0 + + + C_USE_EXT_BRK + 0 + + + C_USE_EXT_NM_BRK + 0 + + + C_USE_NON_SECURE + 0 + + + C_USE_MMU + Memory Management + 0 + + + + true + + + + + + C_MMU_DTLB_SIZE + Data Shadow Translation Look-Aside Buffer Size + 4 + + + + false + + + + + + C_MMU_ITLB_SIZE + Instruction Shadow Translation Look-Aside Buffer Size + 2 + + + + false + + + + + + C_MMU_TLB_ACCESS + Enable Access to Memory Management Special Registers + 3 + + + + false + + + + + + C_MMU_ZONES + Number of Memory Protection Zones + 16 + + + + false + + + + + + C_MMU_PRIVILEGED_INSTR + Privileged Instructions + 0 + + + + false + + + + + + C_USE_BRANCH_TARGET_CACHE + Enable Branch Target Cache + 0 + + + + true + + + + + + C_BRANCH_TARGET_CACHE_SIZE + Branch Target Cache Size + 0 + + + + true + + + + + + C_PC_WIDTH + 17 + + + C_PVR + Specifies Processor Version Register + 0 + + + C_PVR_USER1 + Specify USER1 Bits in Processor Version Register + 0x00 + + + C_PVR_USER2 + Specify USER2 Bits in Processor Version Register + 0x00000000 + + + C_DYNAMIC_BUS_SIZING + 0 + + + C_RESET_MSR + Specify Reset Value for Select MSR Bits + 0x00000000 + + + C_OPCODE_0x0_ILLEGAL + Generate Illegal Instruction Exception for NULL Instruction + 0 + + + C_DEBUG_ENABLED + MicroBlaze Debug Module Interface + 0 + + + C_DEBUG_INTERFACE + MicroBlaze Debug Connection + 0 + + + C_NUMBER_OF_PC_BRK + Number of PC Breakpoints + 1 + + + C_NUMBER_OF_RD_ADDR_BRK + Number of Read Address Watchpoints + 0 + + + C_NUMBER_OF_WR_ADDR_BRK + Number of Write Address Watchpoints + 0 + + + C_DEBUG_EVENT_COUNTERS + Number of Performance Monitor Event Counters + 5 + + + C_DEBUG_LATENCY_COUNTERS + Number of Performance Monitor Latency Counters + 1 + + + C_DEBUG_COUNTER_WIDTH + Performance Monitor Counter Width + 32 + + + C_DEBUG_TRACE_SIZE + Trace Buffer Size + 8192 + + + C_DEBUG_EXTERNAL_TRACE + External Trace + 0 + + + C_DEBUG_TRACE_ASYNC_RESET + Use Asynchrnous Reset for External Trace + 0 + + + C_DEBUG_PROFILE_SIZE + Profile Buffer Size + 0 + + + C_INTERRUPT_IS_EDGE + Sense Interrupt on Edge vs. Level + 0 + + + C_EDGE_IS_POSITIVE + Sense Interrupt on Rising vs. Falling Edge + 1 + + + C_ASYNC_INTERRUPT + 1 + + + C_ASYNC_WAKEUP + 3 + + + C_M0_AXIS_DATA_WIDTH + 32 + + + C_S0_AXIS_DATA_WIDTH + 32 + + + C_M1_AXIS_DATA_WIDTH + 32 + + + C_S1_AXIS_DATA_WIDTH + 32 + + + C_M2_AXIS_DATA_WIDTH + 32 + + + C_S2_AXIS_DATA_WIDTH + 32 + + + C_M3_AXIS_DATA_WIDTH + 32 + + + C_S3_AXIS_DATA_WIDTH + 32 + + + C_M4_AXIS_DATA_WIDTH + 32 + + + C_S4_AXIS_DATA_WIDTH + 32 + + + C_M5_AXIS_DATA_WIDTH + 32 + + + C_S5_AXIS_DATA_WIDTH + 32 + + + C_M6_AXIS_DATA_WIDTH + 32 + + + C_S6_AXIS_DATA_WIDTH + 32 + + + C_M7_AXIS_DATA_WIDTH + 32 + + + C_S7_AXIS_DATA_WIDTH + 32 + + + C_M8_AXIS_DATA_WIDTH + 32 + + + C_S8_AXIS_DATA_WIDTH + 32 + + + C_M9_AXIS_DATA_WIDTH + 32 + + + C_S9_AXIS_DATA_WIDTH + 32 + + + C_M10_AXIS_DATA_WIDTH + 32 + + + C_S10_AXIS_DATA_WIDTH + 32 + + + C_M11_AXIS_DATA_WIDTH + 32 + + + C_S11_AXIS_DATA_WIDTH + 32 + + + C_M12_AXIS_DATA_WIDTH + 32 + + + C_S12_AXIS_DATA_WIDTH + 32 + + + C_M13_AXIS_DATA_WIDTH + 32 + + + C_S13_AXIS_DATA_WIDTH + 32 + + + C_M14_AXIS_DATA_WIDTH + 32 + + + C_S14_AXIS_DATA_WIDTH + 32 + + + C_M15_AXIS_DATA_WIDTH + 32 + + + C_S15_AXIS_DATA_WIDTH + 32 + + + C_ICACHE_BASEADDR + Base Address + 0x0000000000000000 + + + C_ICACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + C_USE_ICACHE + Enable Instruction Cache + 0 + + + C_ALLOW_ICACHE_WR + Enable Writes + 1 + + + C_ADDR_TAG_BITS + 17 + + + C_CACHE_BYTE_SIZE + Size in Bytes + 8192 + + + C_ICACHE_LINE_LEN + Line Length + 4 + + + C_ICACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 1 + + + C_ICACHE_STREAMS + Number of Streams + 0 + + + + true + + + + + + C_ICACHE_VICTIMS + Number of Victims + 0 + + + + true + + + + + + C_ICACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + + true + + + + + + C_ICACHE_DATA_WIDTH + Data Width + 0 + + + + true + + + + + + C_M_AXI_IC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_DATA_WIDTH + 32 + + + C_M_AXI_IC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IC_USER_VALUE + 31 + + + + true + + + + + + C_M_AXI_IC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_BUSER_WIDTH + 1 + + + + true + + + + + + C_DCACHE_BASEADDR + Base Address + 0x0000000000000000 + + + C_DCACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + C_USE_DCACHE + Enable Data Cache + 0 + + + C_ALLOW_DCACHE_WR + Enable Writes + 1 + + + C_DCACHE_ADDR_TAG + 17 + + + C_DCACHE_BYTE_SIZE + Size in Bytes + 8192 + + + C_DCACHE_LINE_LEN + Line Length + 4 + + + C_DCACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 1 + + + C_DCACHE_USE_WRITEBACK + Enable Write-back Storage Policy + 0 + + + + true + + + + + + C_DCACHE_VICTIMS + Number of Victims + 0 + + + + false + + + + + + C_DCACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + C_DCACHE_DATA_WIDTH + Data Width + 0 + + + + false + + + + + + C_M_AXI_DC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_DATA_WIDTH + 32 + + + C_M_AXI_DC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DC_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_M_AXI_DC_USER_VALUE + 31 + + + + true + + + + + + C_M_AXI_DC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_BUSER_WIDTH + 1 + + + + true + + + + + + + + + choice_list_29910ba8 + GENERIC + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_b1aff63c + 32 + 48 + 64 + + + choice_list_b94541ab + 0 + 2 + 4 + 8 + + + choice_list_dd2843c6 + 1 + 2 + 4 + 8 + + + choice_list_f86403bf + 4 + 8 + 16 + + + choice_pairs_0000a26c + 0 + 1 + 2 + 3 + + + choice_pairs_0873e75e + 0 + 1 + + + choice_pairs_1075faf2 + 0 + 1 + 2 + + + choice_pairs_126baff7 + 0 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_13d40c7c + 0 + 32 + 64 + 128 + 256 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_2058dc69 + 0 + 1 + + + choice_pairs_22d9f392 + 0 + 1 + 2 + 3 + + + choice_pairs_3eb333f8 + 0 + 1 + 2 + + + choice_pairs_443ae6cc + 0 + 1 + 2 + 3 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_56d5ba32 + 0 + 1 + 2 + + + choice_pairs_5ab38e91 + 0 + 1 + 2 + + + choice_pairs_5b1842a1 + 0 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_75c71b2b + 0 + 1 + 2 + 3 + + + choice_pairs_7ad6afc0 + 0 + 1 + 2 + 3 + + + choice_pairs_7bfd418d + 0 + 1 + 2 + + + choice_pairs_7dd2834f + 0 + 8 + 9 + 10 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_8b498448 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + + + choice_pairs_b1fa18d9 + 0 + 1 + 2 + + + choice_pairs_c471ed24 + 32 + 36 + 40 + 44 + 48 + 52 + 64 + + + choice_pairs_db57ca32 + 0 + 1 + 2 + + + choice_pairs_e7a1eb81 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_ff364cce + 2 + 3 + + + + + microblaze + + + + endian + little + + + elf_class + 32-bit + + + instance_path + + + + bootloop_file + data/mb_bootloop_le.elf + + + processor_type + MICROBLAZE_LE + + + is_visible + true + + + + + The MicroBlaze 32 and 64 bit soft processor core, providing an instruction set optimized for embedded applications with many user-configurable options. MicroBlaze has many advanced architecture features like Instruction and Data-side cache with AXI interfaces, Floating-Point unit (FPU), Memory Management Unit (MMU), and fault tolerance support. +It is highly recommended to create MicroBlaze systems within Vivado IP Integrator, to enable export to the Xilinx Software Development Kit (SDK) for software development. + + + + C_SCO + 0 + + + + true + + + + + + C_FREQ + 100000000 + + + + true + + + + + + C_DATA_SIZE + Select Processor Implementation + 32 + + + + true + + + + + + C_ADDR_SIZE + Select Extended Addressing + 32 + + + + true + + + + + + C_DYNAMIC_BUS_SIZING + 0 + + + + true + + + + + + C_PC_WIDTH + 17 + + + + true + + + + + + C_INSTANCE + mb_microblaze_0 + + + + true + + + + + + C_AVOID_PRIMITIVES + 0 + + + + true + + + + + + C_FAULT_TOLERANT + Enable Fault Tolerance Support + 0 + + + + true + + + + + + C_ECC_USE_CE_EXCEPTION + Correctable Error Exception + 0 + + + + true + + + + + + C_LOCKSTEP_SLAVE + Lockstep Slave + 0 + + + + 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0x00000000C0000000 + 0x00000000FFFFFFFF + 0x00000000C0000000 + 32 + 32 + 0 + 0x00000000C0000000 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 9600 + 8 + 0 + 100000000 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0x0000000080000000 + 0 + 6216 + 0 + 6216 + 0 + 6216 + 0 + 6216 + 100000000 + 0 + 32 + 0 + 32 + 0 + 32 + 0 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x000000008000FFFF + iomodule + 17 + 0xFFFF + 0x0000000000000000 + 1 + 1 + 0 + 0x0000 + 2 + 0xFFFF + 0 + 1 + 0x00000000C0000000 + 0x00000000FFFFFFFF + 0x00000000C0000000 + 32 + 32 + 0 + 0x00000000C0000000 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 9600 + 8 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + bd_ba6a_iomodule_0_0 + Custom + Custom + Custom + Custom + Custom + false + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 6 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml new file mode 100644 index 0000000..545119a --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml @@ -0,0 +1,8812 @@ + + + xilinx.com + customized_ip + bd_ba6a_iomodule_0_0 + 1.0 + + + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + 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MicroBlaze MCS IO Bus Interface + + + + + + + ADDR_STROBE + + + IO_Addr_Strobe + + + + + ADDRESS + + + IO_Address + + + + + BYTE_ENABLE + + + IO_Byte_Enable + + + + + READ_DATA + + + IO_Read_Data + + + + + READ_STROBE + + + IO_Read_Strobe + + + + + READY + + + IO_Ready + + + + + WRITE_DATA + + + IO_Write_Data + + + + + WRITE_STROBE + + + IO_Write_Strobe + + + + + + + true + + + + + + INTERRUPT.UART_Interrupt + UART_Interrupt + + + + + + + INTERRUPT + + + UART_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT1_Interrupt + FIT1_Interrupt + + + + + + + INTERRUPT + + + FIT1_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT2_Interrupt + FIT2_Interrupt + + + + + + + INTERRUPT + + + FIT2_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT3_Interrupt + FIT3_Interrupt + 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+ + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI1_Interrupt + GPI1_Interrupt + + + + + + + INTERRUPT + + + GPI1_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI2_Interrupt + GPI2_Interrupt + + + + + + + INTERRUPT + + + GPI2_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI3_Interrupt + GPI3_Interrupt + + + + + + + INTERRUPT + + + GPI3_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI4_Interrupt + GPI4_Interrupt + + + + + + + INTERRUPT + + + GPI4_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Interrupt + INTC_Interrupt + + + + + + + INTERRUPT + + + INTC_Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + none + + + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Irq_Single + INTC_IRQ + + + + + + + INTERRUPT + + + INTC_IRQ + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Irq + INTC_IRQ + + + + + + + ACK + + + INTC_Processor_Ack + + + + + ADDRESS + + + INTC_Interrupt_Address + + + + + INTERRUPT + + + INTC_IRQ + + + + + + SENSITIVITY + LEVEL_HIGH + + + LOW_LATENCY + 0 + + + + + + false + + + + + + INTERRUPT.INTC_Irq_Out + INTC_IRQ_OUT + + + + + + + INTERRUPT + + + INTC_IRQ_OUT + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + UART + UART + UART TX/RX + + + + + + + RxD + + + UART_Rx + + + + + TxD + + + UART_Tx + + + + + + BOARD.ASSOCIATED_PARAM + UART_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + UART_CLK.CLK + UART_Clk + Asynchronous UART Clock Input + + + + + + + CLK + + + UART_Clk + + + + + + ASSOCIATED_BUSIF + SLMB + + + ASSOCIATED_RESET + UART_Rst:TMR_Rst + + + FREQ_HZ + UART Clk frequency + UART Clk frequency + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + UART_RST.Rst + UART_Rst + Asynchronous UART Reset Input + + + + + + + RST + + + UART_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + GPIO1 + GPIO1 + General Purpose IO + + + + + + + TRI_I + + + GPI1 + + + + + TRI_O + + + GPO1 + + + + + + C_USE_GPO1 + 0 + + + + true + + + + + + C_GPO1_SIZE + 32 + + + + true + + + + + + C_GPO1_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI1 + 0 + + + + true + + + + + + C_GPI1_SIZE + 32 + + + + true + + + + + + C_GPI1_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO1_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO2 + GPIO2 + General Purpose IO + + + + + + + TRI_I + + + GPI2 + + + + + TRI_O + + + GPO2 + + + + + + C_USE_GPO2 + 0 + + + + true + + + + + + C_GPO2_SIZE + 32 + + + + true + + + + + + C_GPO2_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI2 + 0 + + + + true + + + + + + C_GPI2_SIZE + 32 + + + + true + + + + + + C_GPI2_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO2_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO3 + GPIO3 + General Purpose IO + + + + + + + TRI_I + + + GPI3 + + + + + TRI_O + + + GPO3 + + + + + + C_USE_GPO3 + 0 + + + + true + + + + + + C_GPO3_SIZE + 32 + + + + true + + + + + + C_GPO3_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI3 + 0 + + + + true + + + + + + C_GPI3_SIZE + 32 + + + + true + + + + + + C_GPI3_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO3_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO4 + GPIO4 + General Purpose IO + + + + + + + TRI_I + + + GPI4 + + + + + TRI_O + + + GPO4 + + + + + + C_USE_GPO4 + 0 + + + + true + + + + + + C_GPO4_SIZE + 32 + + + + true + + + + + + C_GPO4_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI4 + 0 + + + + true + + + + + + C_GPI4_SIZE + 32 + + + + true + + + + + + C_GPI4_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO4_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + + + SLMB + LMB memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + UART_RX + UART Receive Data Register + UART Receive Data Register + 0x0 + 8 + true + read-only + + 0x0 + + + UART_RX + Receive Data + Data received by the UART. + 0 + 8 + true + read-only + + 0 + 0 + + modify + false + + + + + false + + + + + + UART_TX + UART Transmit Data Register + UART Transmit Data Register + 0x4 + 8 + true + write-only + + 0x0 + + + UART_TX + Transmit Data + Data to be transmitted by the UART. + 0 + 8 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART_Status + UART Status Register + UART Status Register + 0x8 + 8 + true + read-only + + 0x0 + + + Rx_Valid_Data + Rx Valid Data + Indicates if the receive register has valid data: + 0 - Receive register is empty. + 1 - Receive register has valid data. + + 0 + 1 + true + read-only + + 0 + 0 + + false + + + Tx_Used + Tx Used + Indicates if the transmit register is in use: + 0 - Transmit register is not in use. + 1 - Transmit register is in use. + + 3 + 1 + true + read-only + + 0 + 0 + + false + + + Overrun_Error + Overrun Error + Indicates that an overrun error has occurred: + 0 - No overrun has occurred. + 1 - An overrun has occurred. + + 5 + 1 + true + read-only + + 0 + 0 + + false + + + Frame_Error + Frame Error + Indicates that an frame error has occurred: + 0 - No frame error has occurred. + 1 - A frame error has occurred. + + 6 + 1 + true + read-only + + 0 + 0 + + false + + + Parity_Error + Parity Error + Indicates that a parity error has occurred: + 0 - No parity error has occurred. + 1 - A parity error occurred. + + 7 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_MODE + Interrupt Mode Register + Interrupt Mode Register + 0xC + 17 + true + write-only + + 0x0 + + + IRQ_Mode + IRQ Mode + Interrupt Mode. +For each bit: + W - When written with 1 the corresponding interrupt will use fast mode. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + GPO_1 + General Purpose Output 1 Register + General Purpose Output 1 Register + 0x10 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO_2 + General Purpose Output 2 Register + General Purpose Output 2 Register + 0x14 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO_3 + General Purpose Output 3 Register + General Purpose Output 3 Register + 0x18 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO_4 + General Purpose Output 4 Register + General Purpose Output 4 Register + 0x1C + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_1 + General Purpose Input 1 Register + General Purpose Input 1 Register + 0x20 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_2 + General Purpose Input 2 Register + General Purpose Input 2 Register + 0x24 + 32 + true + read-only + + 0 + + + CPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_3 + General Purpose Input 3 Register + General Purpose Input 3 Register + 0x28 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_4 + General Purpose Input 4 Register + General Purpose Input 4 Register + 0x2C + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_STATUS + Interrupt Status Register + Interrupt Status Register + 0x30 + 17 + true + read-only + + 0x0 + + + UART_ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART_TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART_RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC_Interrupt + External interrupt input signal + Interrupt Status Register. +For each bit: + R - Reads active interrupt signal. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_PENDING + Interrupt Pending Register + Interrupt Pending Register + 0x34 + 17 + true + read-only + + 0x0 + + + UART_ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART_TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART_RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC_Interrupt + Enabled interrupt events that have occurred + Interrupt Pending. +For each bit: + R - Reads enabled interrupt event that has occurred. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_ENABLE + Interrupt Enable Register + Interrupt Enable Register + 0x38 + 17 + true + write-only + + 0x0 + + + UART_ERR + UART Error + UART Error interrupt enabled. + 0 + 1 + true + write-only + + 0 + 0 + + false + + + UART_TX + UART Transmitted Data + UART Transmitted Data interrupt enabled. + 1 + 1 + true + write-only + + 0 + 0 + + false + + + UART_RX + UART Received Data + UART Received Data interrupt enabled. + 2 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_1 + PIT 1 + PIT 1 interrupt enabled. + 3 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_2 + PIT 2 + PIT 2 interrupt enabled. + 4 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_3 + PIT 3 + PIT 3 interrupt enabled. + 5 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_4 + PIT 4 + PIT 4 interrupt enabled. + 6 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_1 + FIT 1 + FIT 1 interrupt enabled. + 7 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_2 + FIT 2 + FIT 2 interrupt enabled. + 8 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_3 + FIT 3 + FIT 3 interrupt enabled. + 9 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_4 + FIT 4 + FIT 4 interrupt enabled. + 10 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_1 + GPI 1 + GPI 1 interrupt enabled. + 11 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_2 + GPI 2 + GPI 2 interrupt enabled. + 12 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_3 + GPI 3 + GPI 3 interrupt enabled. + 13 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_4 + GPI 4 + GPI 4 interrupt enabled. + 14 + 1 + true + write-only + + 0 + 0 + + false + + + INTC_Interrupt + Enable external interrupt input signals + Interrupt Enable. +For each bit: + W - Enable external interrupt input signal. + + 16 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_ACK + Interrupt Acknowledge Register + Interrupt Acknowledge Register + 0x3C + 17 + true + write-only + + 0x0 + + + IRQ_Acknowledge + IRQ Acknowledge + Interrupt Acknowledge. +For each bit: + W - When written with 1 clear bit in IRQ_STATUS and IRQ_PENDING. + + 0 + 17 + true + write-only + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + PIT1_PRELOAD + PIT 1 Preload Register + PIT 1 Preload Register + 0x40 + 32 + true + write-only + + 0x0 + + + PIT1_Preload + PIT1 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1_COUNTER + PIT 1 Counter Register + PIT 1 Counter Register + 0x44 + 32 + true + read-only + + 0x0 + + + PIT1_Counter + PIT1 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1_CONTROL + PIT 1 Control Register + PIT 1 Control Register + 0x48 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT1_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART_BAUD + UART Programmable Baud Rate + UART Programmable Baud Rate + 0x4C + 8 + true + write-only + + 0x0 + + + UART_BAUD + Baud Rate + Programmable UART Baud Rate. + 0 + 20 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2_PRELOAD + PIT 2 Preload Register + PIT 2 Preload Register + 0x50 + 32 + true + write-only + + 0x0 + + + PIT2_Preload + PIT2 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2_COUNTER + PIT 2 Counter Register + PIT 2 Counter Register + 0x54 + 32 + true + read-only + + 0x0 + + + PIT2_Counter + PIT2 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2_CONTROL + PIT 2 Control Register + PIT 2 Control Register + 0x58 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT2_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3_PRELOAD + PIT 3 Preload Register + PIT 3 Preload Register + 0x60 + 32 + true + write-only + + 0x0 + + + PIT3_Preload + PIT3 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3_COUNTER + PIT 3 Counter Register + PIT 3 Counter Register + 0x64 + 32 + true + read-only + + 0x0 + + + PIT3_Counter + PIT3 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3_CONTROL + PIT 3 Control Register + PIT 3 Control Register + 0x68 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT3_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4_PRELOAD + PIT 4 Preload Register + PIT 4 Preload Register + 0x70 + 32 + true + write-only + + 0x0 + + + PIT4_Preload + PIT4 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4_COUNTER + PIT 4 Counter Register + PIT 4 Counter Register + 0x74 + 32 + true + read-only + + 0x0 + + + PIT4_Counter + PIT4 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4_CONTROL + PIT 4 Control Register + PIT 4 Control Register + 0x78 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT4_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_0 + Interrupt Vector Register 0 + Interrupt Vector Register 0 + 0x80 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 0 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_1 + Interrupt Vector Register 1 + Interrupt Vector Register 1 + 0x84 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 1 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_2 + Interrupt Vector Register 2 + Interrupt Vector Register 2 + 0x88 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 2 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_3 + Interrupt Vector Register 3 + Interrupt Vector Register 3 + 0x8C + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 3 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_4 + Interrupt Vector Register 4 + Interrupt Vector Register 4 + 0x90 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 4 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_5 + Interrupt Vector Register 5 + Interrupt Vector Register 5 + 0x94 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 5 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_6 + Interrupt Vector Register 6 + Interrupt Vector Register 6 + 0x98 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 6 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_7 + Interrupt Vector Register 7 + Interrupt Vector Register 7 + 0x9C + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 7 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_8 + Interrupt Vector Register 8 + Interrupt Vector Register 8 + 0xA0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 8 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_9 + Interrupt Vector Register 9 + Interrupt Vector Register 9 + 0xA4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 9 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_10 + Interrupt Vector Register 10 + Interrupt Vector Register 10 + 0xA8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 10 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_11 + Interrupt Vector Register 11 + Interrupt Vector Register 11 + 0xAC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 11 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_12 + Interrupt Vector Register 12 + Interrupt Vector Register 12 + 0xB0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 12 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_13 + Interrupt Vector Register 13 + Interrupt Vector Register 13 + 0xB4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 13 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_14 + Interrupt Vector Register 14 + Interrupt Vector Register 14 + 0xB8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 14 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_16 + Interrupt Vector Register 16 + Interrupt Vector Register 16 + 0xC0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 16 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_17 + Interrupt Vector Register 17 + Interrupt Vector Register 17 + 0xC4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 17 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_18 + Interrupt Vector Register 18 + Interrupt Vector Register 18 + 0xC8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 18 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_19 + Interrupt Vector Register 19 + Interrupt Vector Register 19 + 0xCC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 19 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_20 + Interrupt Vector Register 20 + Interrupt Vector Register 20 + 0xD0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 20 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_21 + Interrupt Vector Register 21 + Interrupt Vector Register 21 + 0xD4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 21 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_22 + Interrupt Vector Register 22 + Interrupt Vector Register 22 + 0xD8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 22 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_23 + Interrupt Vector Register 23 + Interrupt Vector Register 23 + 0xDC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 23 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_24 + Interrupt Vector Register 24 + Interrupt Vector Register 24 + 0xE0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 24 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_25 + Interrupt Vector Register 25 + Interrupt Vector Register 25 + 0xE4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 25 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_26 + Interrupt Vector Register 26 + Interrupt Vector Register 26 + 0xE8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 26 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_27 + Interrupt Vector Register 27 + Interrupt Vector Register 27 + 0xEC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 27 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_28 + Interrupt Vector Register 28 + Interrupt Vector Register 28 + 0xF0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 28 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_29 + Interrupt Vector Register 29 + Interrupt Vector Register 29 + 0xF4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 29 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_30 + Interrupt Vector Register 30 + Interrupt Vector Register 30 + 0xF8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 30 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_31 + Interrupt Vector Register 31 + Interrupt Vector Register 31 + 0xFC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 31 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_0 + Interrupt Vector Address Register 0 + Interrupt Vector Address Register 0 + 0x100 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 0 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_1 + Interrupt Vector Address Register 1 + Interrupt Vector Address Register 1 + 0x108 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 1 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_2 + Interrupt Vector Address Register 2 + Interrupt Vector Address Register 2 + 0x110 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 2 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_3 + Interrupt Vector Address Register 3 + Interrupt Vector Address Register 3 + 0x118 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 3 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_4 + Interrupt Vector Address Register 4 + Interrupt Vector Address Register 4 + 0x120 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 4 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_5 + Interrupt Vector Address Register 5 + Interrupt Vector Address Register 5 + 0x128 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 5 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_6 + Interrupt Vector Address Register 6 + Interrupt Vector Address Register 6 + 0x130 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 6 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_7 + Interrupt Vector Address Register 7 + Interrupt Vector Address Register 7 + 0x138 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 7 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_8 + Interrupt Vector Address Register 8 + Interrupt Vector Address Register 8 + 0x140 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 8 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_9 + Interrupt Vector Address Register 9 + Interrupt Vector Address Register 9 + 0x148 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 9 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_10 + Interrupt Vector Address Register 10 + Interrupt Vector Address Register 10 + 0x150 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 10 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_11 + Interrupt Vector Address Register 11 + Interrupt Vector Address Register 11 + 0x158 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 11 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_12 + Interrupt Vector Address Register 12 + Interrupt Vector Address Register 12 + 0x160 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 12 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_13 + Interrupt Vector Address Register 13 + Interrupt Vector Address Register 13 + 0x168 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 13 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_14 + Interrupt Vector Address Register 14 + Interrupt Vector Address Register 14 + 0x170 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 14 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_16 + Interrupt Vector Address Register 16 + Interrupt Vector Address Register 16 + 0x180 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 16 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_17 + Interrupt Vector Address Register 17 + Interrupt Vector Address Register 17 + 0x188 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 17 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_18 + Interrupt Vector Address Register 18 + Interrupt Vector Address Register 18 + 0x190 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 18 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_19 + Interrupt Vector Address Register 19 + Interrupt Vector Address Register 19 + 0x198 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 19 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_20 + Interrupt Vector Address Register 20 + Interrupt Vector Address Register 20 + 0x1A0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 20 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_21 + Interrupt Vector Address Register 21 + Interrupt Vector Address Register 21 + 0x1A8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 21 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_22 + Interrupt Vector Address Register 22 + Interrupt Vector Address Register 22 + 0x1B0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 22 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_23 + Interrupt Vector Address Register 23 + Interrupt Vector Address Register 23 + 0x1B8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 23 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_24 + Interrupt Vector Address Register 24 + Interrupt Vector Address Register 24 + 0x1C0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 24 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_25 + Interrupt Vector Address Register 25 + Interrupt Vector Address Register 25 + 0x1C8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 25 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_26 + Interrupt Vector Address Register 26 + Interrupt Vector Address Register 26 + 0x1D0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 26 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_27 + Interrupt Vector Address Register 27 + Interrupt Vector Address Register 27 + 0x1D8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 27 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_28 + Interrupt Vector Address Register 28 + Interrupt Vector Address Register 28 + 0x1E0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 28 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_29 + Interrupt Vector Address Register 29 + Interrupt Vector Address Register 29 + 0x1E8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 29 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_30 + Interrupt Vector Address Register 30 + Interrupt Vector Address Register 30 + 0x1F0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector 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is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous. + 0xFFFF + + + C_INTC_NUM_SYNC_FF + Number of synchronization flip-flops + Number of synchronization flip-flops used to synchronize asynchronous interupt inputs + 2 + + + Component_Name + bd_ba6a_iomodule_0_0 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + GPIO1_BOARD_INTERFACE + Custom + + + GPIO2_BOARD_INTERFACE + Custom + + + GPIO3_BOARD_INTERFACE + Custom + + + GPIO4_BOARD_INTERFACE + Custom + + + UART_BOARD_INTERFACE + Custom + + + + + IOModule + 6 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xci new file mode 100644 index 0000000..a5df74b --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xci @@ -0,0 +1,159 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_ilmb_0 + + + bd_ba6a_Clk + 100000000 + 0 + 0 + 0.000 + 32 + 32 + STANDARD + READ_ONLY + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 0 + 1 + 32 + 32 + 2 + 0 + 1 + 32 + 32 + 2 + 0 + bd_ba6a_ilmb_0 + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 11 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xml new file mode 100644 index 0000000..fd650dd --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xml @@ -0,0 +1,3532 @@ + + + xilinx.com + customized_ip + bd_ba6a_ilmb_0 + 1.0 + + + LMB_Sl_0 + LMB_Sl_00 + Local Memory Bus Mirrored Slave interface 0 + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + 0 + 0 + + + + + + READDBUS + + + Sl_DBus + + 0 + 31 + + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + 0 + 0 + + + + + + RST + + + LMB_Rst + + + + + UE + + + Sl_UE + + 0 + 0 + + + + + + WAIT + + + Sl_Wait + + 0 + 0 + + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + 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+ bd_ba6a_dlmb_0 + + + + + Local Memory Bus (LMB) 1.0 + 11 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xci new file mode 100644 index 0000000..3345ed9 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xci @@ -0,0 +1,189 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_dlmb_cntlr_0 + + + NONE + 65536 + 32 + 1 + + bd_ba6a_Clk + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000000000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000000000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_ba6a_dlmb_cntlr_0 + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 19 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xml new file mode 100644 index 0000000..f502ac2 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xml @@ -0,0 +1,4011 @@ + + + xilinx.com + customized_ip + bd_ba6a_dlmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + PROTOCOL + STANDARD + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + PROTOCOL + STANDARD + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + 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BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + READ_LATENCY + 1 + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + bd_ba6a_Clk + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC_Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE_Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + 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C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC_Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE_Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + LMB_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + Sl_Ready + + out + + + std_logic + dummy_view + + + + + + Sl_Wait + + out + + + std_logic + dummy_view + + + + + + Sl_UE + + out + + + std_logic + dummy_view + + + + + + Sl_CE + + out + + + std_logic + dummy_view + + + + + + LMB1_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteStrobe 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std_logic_vector + dummy_view + + + + + + BRAM_Din_A + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + S_AXI_CTRL_ACLK + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARESETN + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_WDATA + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RDATA + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + + + C_FAMILY + virtexuplus + + + C_HIGHADDR + LMB BRAM High Address + 0x000000000000FFFF + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000000000 + + + C_NUM_LMB + Number of LMB Ports + 1 + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_BRAM_AWIDTH + BRAM Address Bus Width + 32 + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + false + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + false + + + + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_0873e75e + 0 + 1 + + + choice_pairs_449ac0d2 + 0 + 1 + 2 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_8d6e70ff + 0 + 2 + + + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000000000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x000000000000FFFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_ba6a_ilmb_cntlr_0 + + + + + LMB BRAM Controller + 19 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xci new file mode 100644 index 0000000..0e3e0b9 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xci @@ -0,0 +1,298 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_lmb_bram_I_0 + + + 4096 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + BRAM_CTRL + NONE + 65536 + 32 + 1 + READ_WRITE + BRAM_CTRL + NONE + 65536 + 32 + 1 + READ_WRITE + + 100000000 + 0 + 0 + 0.000 + 0 + 32 + 32 + 1 + 4 + 0 + 1 + 8 + 0 + 0 + 16 + NONE + 0 + 0 + 0 + ./ + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + Estimated Power for IP : 19.660986 mW + virtexuplus + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + bd_ba6a_lmb_bram_I_0.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 16384 + 16384 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 4 + 4 + 16384 + 16384 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 8 + NONE + no_coe_file_loaded + ALL + bd_ba6a_lmb_bram_I_0 + false + false + false + false + false + true + false + false + true + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + false + Native + false + bd_ba6a_lmb_bram_I_0.mem + True_Dual_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + true + false + false + false + true + true + 16384 + 32 + 32 + No_ECC + false + false + false + BRAM_Controller + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 4 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xml new file mode 100644 index 0000000..bdf7b98 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xml @@ -0,0 +1,4151 @@ + + + xilinx.com + customized_ip + bd_ba6a_lmb_bram_I_0 + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + 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Estimated Power for IP : 19.660986 mW + + + + + + choice_list_0132492a + 32 + 64 + 128 + + + choice_list_302d3091 + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_6fc15197 + 32 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f9a6a28b + Native + + + choice_pairs_1f270a52 + BRAM_Controller + Stand_Alone + + + choice_pairs_246d8066 + WRITE_FIRST + READ_FIRST + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_ba6a_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false 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4 + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci new file mode 100644 index 0000000..d6fe9d7 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci @@ -0,0 +1,189 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_second_dlmb_cntlr_0 + + + NONE + 32768 + 32 + 1 + + bd_ba6a_Clk + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000010000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + 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b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xml @@ -0,0 +1,4011 @@ + + + xilinx.com + customized_ip + bd_ba6a_second_dlmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + PROTOCOL + STANDARD + + + none + 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BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 32768 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + READ_LATENCY + 1 + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING 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Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC_Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE_Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + 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C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC_Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE_Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + LMB_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + Sl_Ready + + out + + + std_logic + dummy_view + + + + + + Sl_Wait + + out + + + std_logic + dummy_view + + + + + + Sl_UE + + out + + + std_logic + dummy_view + + + + + + Sl_CE + + out + + + std_logic + dummy_view + + + + + + LMB1_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteStrobe 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LMB2_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + Sl2_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + Sl2_Ready + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_Wait + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + LMB3_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + 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std_logic_vector + dummy_view + + + + + + BRAM_Din_A + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + S_AXI_CTRL_ACLK + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARESETN + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_WDATA + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RDATA + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + + + C_FAMILY + virtexuplus + + + C_HIGHADDR + LMB BRAM High Address + 0x0000000000017FFF + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000010000 + + + C_NUM_LMB + Number of LMB Ports + 1 + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_BRAM_AWIDTH + BRAM Address Bus Width + 32 + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + false + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + false + + + + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_0873e75e + 0 + 1 + + + choice_pairs_449ac0d2 + 0 + 1 + 2 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_8d6e70ff + 0 + 2 + + + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000010000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x0000000000017FFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_ba6a_second_ilmb_cntlr_0 + + + + + LMB BRAM Controller + 19 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xci new file mode 100644 index 0000000..40c231e --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xci @@ -0,0 +1,298 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_second_lmb_bram_I_0 + + + 4096 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + BRAM_CTRL + NONE + 32768 + 32 + 1 + READ_WRITE + BRAM_CTRL + NONE + 32768 + 32 + 1 + READ_WRITE + + 100000000 + 0 + 0 + 0.000 + 0 + 32 + 32 + 1 + 4 + 0 + 1 + 8 + 0 + 0 + 8 + NONE + 0 + 0 + 0 + ./ + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + Estimated Power for IP : 17.246228 mW + virtexuplus + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + bd_ba6a_second_lmb_bram_I_0.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 8192 + 8192 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 4 + 4 + 8192 + 8192 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 8 + NONE + no_coe_file_loaded + ALL + bd_ba6a_second_lmb_bram_I_0 + false + false + false + false + false + true + false + false + true + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + false + Native + false + bd_ba6a_second_lmb_bram_I_0.mem + True_Dual_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + true + false + false + false + true + true + 8192 + 32 + 32 + No_ECC + false + false + false + BRAM_Controller + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 4 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xml new file mode 100644 index 0000000..4c0a36a --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xml @@ -0,0 +1,4151 @@ + + + xilinx.com + customized_ip + bd_ba6a_second_lmb_bram_I_0 + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + 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+ C_COUNT_36K_BRAM + 8 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 17.246228 mW + + + + + + choice_list_0132492a + 32 + 64 + 128 + + + choice_list_302d3091 + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_6fc15197 + 32 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f9a6a28b + Native + + + choice_pairs_1f270a52 + BRAM_Controller + Stand_Alone + + + choice_pairs_246d8066 + WRITE_FIRST + READ_FIRST + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_ba6a_second_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A 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rs232_uart + + + choice_list_30de7c39 + Custom + pcie_perstn + resetn + + + choice_list_38e5a9f1 + Custom + dip_switches_4bits + led_3bits + qsfp0_lowspeed + qsfp1_lowspeed + + + choice_list_ac75ef1e + Custom + + + choice_list_f585525a + 110 + 300 + 1200 + 2400 + 4800 + 9600 + 19200 + 38400 + 57600 + 115200 + 128000 + 230400 + 460800 + 921600 + + + choice_pairs_007f01e9 + 0 + 1 + 2 + 3 + 4 + 5 + 7 + 8 + 9 + + + choice_pairs_0d2d32a8 + 0 + 1 + 2 + + + choice_pairs_366c5f3d + 0 + 1 + 2 + + + choice_pairs_4847022f + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 8 + 9 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_5502e96b + 1 + 2 + 3 + 4 + + + choice_pairs_563648c8 + 0 + 1 + + + choice_pairs_5f1e379e + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 9 + + + choice_pairs_7ba91213 + 0 + 1 + 2 + 3 + + + choice_pairs_9de6ed99 + 0 + + + choice_pairs_f0f6eb36 + 0 + 1 + 2 + 3 + 4 + 6 + 7 + 8 + 9 + + + choice_pairs_f7e0b771 + 4096 + 8192 + 12288 + 16384 + 20480 + 24576 + 32768 + 36864 + 40960 + 49152 + 65536 + 69632 + 73728 + 81920 + 98304 + 131072 + + + choice_pairs_ffa336e4 + 0 + 1 + + + + + xilinx_elaborateports_view_fileset + + ../bd_0/bd_ba6a.bd + block_diagram + + + + xilinx_elaboratebd_view_fileset + + ../bd_0/bd_ba6a.bd + block_diagram + + + + MicroBlaze Micro Controller System (MCS) is a light-weight general purpose micro controller system, based on the MicroBlaze processor. It is primarily intended for simple control applications, where a hardware solution would be less flexible and more difficult to implement. Software development with the Xilinx Software Development Kit (SDK) is supported, including a software driver for the peripherals. Debugging including UART is available either via SDK or directly with the Xilinx Microprocessor Debugger. +The MCS consists of the processor itself, local memory with sizes ranging from 4KB to 128KB, up to 4 Fixed Interval Timers, up to 4 Programmable Interval Timers, up to 4 32-bit General Purpose Output ports, up to 4 32-bit General Purpose Input ports, and an Interrupt Controller with up to 16 external interrupt inputs. + + + + JTAG_CHAIN + Debug JTAG User-defined Register + 2 + + + + false + + + + + + MICROBLAZE_INSTANCE + MicroBlaze Instance Name + microblaze_0 + + + AVOID_PRIMITIVES + 0 + + + PATH + Instance Hierarchical Design Name + mcs_0 + + + FREQ + Input Clock Frequency (MHz) + 100.0 + + + OPTIMIZATION + Select MicroBlaze Optimization + 1 + + + DEBUG_ENABLED + Enable Debug Support + 0 + + + USE_BSCAN + Select BSCAN location + 0 + + + + false + + + + + + BSCANID + Define BSCAN id + 76547328 + + + + false + + + + + + TRACE + Enable MicroBlaze Trace Bus + 1 + + + ECC + Error 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GPO2_SIZE + Number of Bits + 32 + + + + false + + + + + + GPO2_INIT + Initial Value of GPO + 0x00000000 + + + + false + + + + + + USE_GPO3 + Use GPO + 0 + + + + true + + + + + + GPO3_SIZE + Number of Bits + 32 + + + + false + + + + + + GPO3_INIT + Initial Value of GPO + 0x00000000 + + + + false + + + + + + USE_GPO4 + Use GPO + 0 + + + + true + + + + + + GPO4_SIZE + Number of Bits + 32 + + + + false + + + + + + GPO4_INIT + Initial Value of GPO + 0x00000000 + + + + false + + + + + + USE_GPI1 + Use GPI + 0 + + + + true + + + + + + GPI1_SIZE + Number of Bits + 32 + + + + false + + + + + + GPI1_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_GPI2 + Use GPI + 0 + + + + true + + + + + + GPI2_SIZE + Number of Bits + 32 + + + + false + + + + + + GPI2_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_GPI3 + Use GPI + 0 + + + + true + + + + + + GPI3_SIZE + Number of Bits + 32 + + + + false + + + + + + GPI3_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + 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CLK_BOARD_INTERFACE + Custom + + + + true + + + + + + RESET_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO1_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO2_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO3_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO4_BOARD_INTERFACE + Custom + + + + true + + + + + + UART_BOARD_INTERFACE + Custom + + + + true + + + + + + + + MicroBlaze MCS + + XPM_MEMORY + + 14 + + true + subcore + + + + + + + + + + + + + + + + 2020.2 + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xci new file mode 100644 index 0000000..855a261 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xci @@ -0,0 +1,665 @@ + + + xilinx.com + xci + unknown + 1.0 + + + phy_ddr4_udimm_phy + + + 17 + 0 + 0 + 0 + 2 + HP_IO + 2 + X0Y11 + X0Y10 + X0Y70 + X0Y11 + 11 + DDR4_SDRAM + 0 + 0 + 0 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MEMORY DEVICE WIDTH + 64 + + + PLL_WIDTH + PLL WIDTH + 3 + + + IOBTYPE + IOBTYPE + 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b +000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, + 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_000_000_000_000_000_000_000_000_001_001_001_001, 39'b001_001_001_000_000_001_001_001_001_001_001_001_001, 39'b000_001_001_001_001_101_101_001_00 +1_001_001_001_001 + + + BYTES + BYTES + 11 + + + DBYTES + DBYTES + 8 + + + PING_PONG_CH1_BYTES_MAP + PING_PONG_CH1_BYTES_MAP + 11'b00000000000 + + + PING_PONG_PHY + PING PONG PHY + 1 + + + RX_DATA_TYPE + RX DATA TYPE + { 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, + 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b000000_00_00111_11, 15'b111001_11_11111_11, + 15'b011111_11_11111_11 } + + + INIT + INIT + { 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, + 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111101, 15'b111111111111111, + 15'b111111111111111 } + + + SELF_CALIBRATE + SELF CALIBRATE + {11{2'b11}} + + + TX_OUTPUT_PHASE_90 + TX OUTPUT PHASE 90 + { 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000 +011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000000001111, 13'b1110011111111, 13'b0111111111111 + } + + + RXTX_BITSLICE_EN + RXTX BITSLICE EN + {13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b01111 +01111101, 13'b0111101111101, 13'b0111101111101, 13'b0000000001111, 13'b1110011111111, 13'b0111101111111 + } + + + EN_OTHER_PN_CLOCK_PARAM + EN OTHER PN CLOCK PARAM + {{8{2'b01}}, {3{2'b00}}} + + + PHY_BYTE_ALLOC_PARAM + PHY BYTE ALLOC PARAM + {{8{2'b11}}, {3{2'b00}}} + + + DATA_BUF_ADDR_WIDTH + DATA BUF ADDR WIDTH + 5 + + + CLKIN_PERIOD + CLKIN PERIOD + 3333 + + + MEM_TYPE + MEM TYPE + 0 + + + AXI_ID_WIDTH + AXI ID WIDTH + 0 + + + AXI_DATA_WIDTH + AXI DATA WIDTH + 0 + + + AXI_ADDR_WIDTH + AXI ADDR WIDTH + 0 + + + USE_DM_PORT + USE DM PORT + 1 + + + BUFG_LOC_1 + BUFG LOC 1 + X0Y70 + + + BUFG_LOC_2 + BUFG LOC 2 + X0Y11 + + + BUFG_DIV_LOC_1 + BUFG DIV LOC 1 + X0Y11 + + + BUFG_DIV_LOC_2 + BUFG DIV LOC 2 + X0Y10 + + + PBLOCK_SLICE_LOC + PBLOCK SLICE LOC + 0 + + + PBLOCK_RAMB36_LOC + PBLOCK RAMB36 LOC + 0 + + + PBLOCK_RAMB18_LOC + PBLOCK RAMB18 LOC + 0 + + + PBLOCK_SLICE_LOC_SC + PBLOCK SLICE LOC SC + 0 + + + PBLOCK_RAMB36_LOC_SC + PBLOCK RAMB36 LOC SC + 0 + + + PBLOCK_RAMB18_LOC_SC + PBLOCK RAMB18 LOC SC + 0 + + + MMCM_IDX_BANK + MMCM IDX BANK + 1 + + + CENTER_BANK_CLOCK_REGION + CENTER BANK CLOCK REGION + 0 + + + CENTER_BANK_MMCME3_ADV_SITE + CENTER BANK MMCME3 ADV SITE + 0 + + + SYSCLK_CENTER_INFO + SYSCLK_CENTER_INFO + FALSE + + + tWR + tWR + 10 + + + tRTP + tRTP + 5 + + + RANK_WIDTH + RANK WIDTH + 1 + + + CK_WIDTH + CK WIDTH + 1 + + + DATABITS_PER_STROBE + DATABITS PER STROBE + 8 + + + USE_CS_PORT + USE CS PORT + 1 + + + CA_MIRROR + CA MIRROR + 0 + + + IS_CUSTOM + IS CUSTOM + false + + + Slot + Slot + 1 + + + + + + phy_ddr4_udimm_phy + + + + PHY for DDR4 interfaces for Ultrascale Architecture + + + C0.ControllerType + DDR4_SDRAM + + + IS_FROM_PHY + 1 + + + Phy_Only + Phy_Only_Single + + + No_Controller + 1 + + + Default_Bank_Selections + Default Bank Selections + false + + + Debug_Signal + Disable + + + Simulation_Mode + BFM + + + PARTIAL_RECONFIG_FLOW_MIG + false + + + CLKOUT1_DIVIDE + 0 + + + CLKOUT2_DIVIDE + 0 + + + CLKOUT3_DIVIDE + 0 + + + CLKOUT4_DIVIDE + 0 + + + System_Clock + Differential + + + RECONFIG_XSDB_SAVE_RESTORE + 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+ + C0.StackHeight + 1 + + + PING_PONG_PHY + Ping Pong Phy + 1 + + + C0.DDR4_Enable_LVAUX + false + + + C0.DDR4_EN_PARITY + false + + + EN_PP_4R_MIR + false + + + + + DDR4 SDRAM (MIG) + + xtlm + protobuf + sim_ddr_v1_0 + + 10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig new file mode 100644 index 0000000..698f7e5 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig @@ -0,0 +1,313 @@ +/****************************************************************************** +// (c) Copyright 2013 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +******************************************************************************/ +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 1.1 +// \ \ Application : MIG +// / / Filename : ddr4_v2_2_10_cal_rd_en.sv +// /___/ /\ Date Last Modified : $Date: 2015/04/23 $ +// \ \ / \ Date Created : Thu Apr 18 2013 +// \___\/\___\ +// +// Device : UltraScale +// Design Name : DDR4 SDRAM & DDR3 SDRAM +// Purpose : +// ddr4_v2_2_10_cal_rd_en module +// Reference : +// Revision History : +//***************************************************************************** + +`timescale 1ns/100ps + +module ddr4_v2_2_10_cal_rd_en #(parameter + RANKS = 1 + ,RL = 11 + ,EXTRA_CMD_DELAY = 0 + ,TCQ = 0.1 +)( + input clk + ,input rst + + ,output [3:0] mc_clb2phy_rden + ,output [3:0] mc_clb2phy_rdcs0 + ,output [3:0] mc_clb2phy_rdcs1 + + ,input [1:0] casSlot // spyglass disable W498 + ,input mccasSlot2 + ,input rdCAS + ,input calrdCAS + ,input mcrdCAS + ,input [5:0] mCL0 + ,input [5:0] mCL1 + ,input [5:0] mCL2 + ,input [5:0] mCL3 + ,input [1:0] winRank + ,input [1:0] calRank + ,input [1:0] mcwinRank + ,input calDone +); + +wire [5:0] mCL[0:3]; +assign mCL[0] = mCL0; +assign mCL[1] = mCL1; +assign mCL[2] = mCL2; +assign mCL[3] = mCL3; + +// This section generates the Gate enable mc_clb2phy_rden. +// This logic is used in calibration and during normal operation. +// Case 4'b0110 defines nominal timing where the trained mCL value equals RL. +// This logic supports mCL = RL - 3, to enable the Gate 3tCK earlier than nominal RL. +// Early gate enable is needed in Gate training, during normal operation +// if command delays are very low, and to compensate for extra Gate delay +// in the XiPhy that is allocated for VT tracking. The logic also supports Gate +// enable 4tCK later than nominal to allow for command fly-by routing. +// The Gate enable can be further delayed to allow for extra command pipeline delays. +// The Gate enable supports RL as low as 7 with no extra command delays, but other +// blocks have higher low limits, so the minimum RL without extra command delays +// is expected to be RL=8. + +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn; +(* KEEP = "true" *) reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt; +reg [18:0] rsMask[0:7]; + +function [18:0] rs2mask; + input [3:0] diff; + input slot2; +case ({diff, slot2}) + 5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111; + 5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100; + 5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110; + 5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000; + 5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100; + 5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000; + 5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000; + 5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000; + 5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000; + 5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000; + 5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000; + 5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000; + 5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000; + 5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000; + 5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000; + 5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000; + 5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000; + 5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000; + 5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000; + 5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000; + 5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000; + 5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000; + 5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000; + 5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000; + 5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000; + 5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000; + 5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000; + 5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000; + default: rs2mask = 19'b000_0000_1000_0000_1111; +endcase +endfunction + +always @(posedge clk) begin: blk1 + reg [3:0] rsNdx; + for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1) + rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]); +end + +always @(*) if (rst) begin + rdEn_nxt = 'b0; +end else begin + rdEn_nxt = (rdEn >> 4) + | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} + : 'b0); +end + +always @(posedge clk) + rdEn <= #TCQ rdEn_nxt; + +assign mc_clb2phy_rden = rdEn[3:0]; + +/////////////////////////////////////////////////////////////////// +// This logic is used during normal, multi-rank operation only. Durring cal or single +// rank operation this logic is bypassed and the output of this section is static. +// This section generates the read rank signals used by the XiPhy to select per rank +// cal values during read operations. + +integer tck_index; +localparam rdcs_msb = RL + 8 + 4*EXTRA_CMD_DELAY; + +reg [rdcs_msb :0] rdcs0; +reg [rdcs_msb :0] rdcs0_mc; +reg [rdcs_msb :0] rdcs1; +reg [rdcs_msb :0] rdcs1_mc; +reg [6:0] rdcs_rdcas_lsb_slot0; +reg calDone_dly; + +// Extend newest cs (MSB) and shift out the oldest (low 4 LSBs) +wire [rdcs_msb :0] rdcs0_shift = { { 4 { rdcs0[rdcs_msb] } }, rdcs0[ rdcs_msb : 4] }; +wire [rdcs_msb :0] rdcs1_shift = { { 4 { rdcs1[rdcs_msb] } }, rdcs1[ rdcs_msb : 4] }; + +// Create rdcs mask for the current rdcas +wire [6:0] rdcs_rdcas_lsb_slot0_nxt = { 1'b0, mCL0 } + 4*EXTRA_CMD_DELAY - 7'd7; +wire [rdcs_msb :0] rdcs_rdcas_mask_slot0 = { ( rdcs_msb + 1 ) { 1'b1 } } << rdcs_rdcas_lsb_slot0; +wire [rdcs_msb :0] rdcs_rdcas_mask = rdcs_rdcas_mask_slot0 << 2*mccasSlot2; + +// Merge the shifted rdcs and winRank based on the rdcs mask for the current rdcas +always @(*) begin + for (tck_index = 0; tck_index <= rdcs_msb; tck_index = tck_index + 1) begin + rdcs0_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[0] : rdcs0_shift[tck_index]; + rdcs1_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[1] : rdcs1_shift[tck_index]; + end +end + +// Select mc or cal rdcs +wire [rdcs_msb :0] rdcs0_nxt = calDone_dly ? rdcs0_mc : { rdcs_msb+1 { calRank[0] } }; +wire [rdcs_msb :0] rdcs1_nxt = calDone_dly ? rdcs1_mc : { rdcs_msb+1 { calRank[1] } }; + +// Final 4 bit rdcs output +assign mc_clb2phy_rdcs0 = rdcs0[3:0] & ~{ 4 { RANKS == 1 } }; +assign mc_clb2phy_rdcs1 = rdcs1[3:0] & ~{ 4 { RANKS == 1 } }; + +// Flops +always @(posedge clk) begin + rdcs_rdcas_lsb_slot0 <= #TCQ rdcs_rdcas_lsb_slot0_nxt; + calDone_dly <= #TCQ calDone; +end + +// Reset flops +always @(posedge clk) if (rst) begin + rdcs0 <= #TCQ '0; + rdcs1 <= #TCQ '0; +end else begin + rdcs0 <= #TCQ rdcs0_nxt; + rdcs1 <= #TCQ rdcs1_nxt; +end + + +//synopsys translate_off + +`ifdef MEM_INTERNAL +// Events - When asserted high in a test that passes all verification checks, these coverage +// properties indicate that a functional coverage event has been hit. +// --------------------------------------------------------------------------------------------- + +// Minimum mCL in normal operation +//wire e_mc_rd_en_000 = ( ( mCL0 + 4*EXTRA_CMD_DELAY ) == 13 ) & calDone & ~( RANKS == 1 ) & rdCAS; +//always @(posedge clk) mc_rd_en_000: if (~rst) cover property (e_mc_rd_en_000); + + +// Asserts - When asserted high, an illegal condition has been detected and the test has failed. +// --------------------------------------------------------------------------------------------- + +// Check for illegal rank switch in rdEn and rdcs. rdEn gap must be at least 2tCK wide. rdcs must be stable for 2tCK after rdEn de-assertion. +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdEn; +reg [rdcs_msb :0] a_rdcs0_dly; +reg [rdcs_msb :0] a_rdcs1_dly; +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0; +wire [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0_nxt = { rdcs0, a_rdcs0_dly[3:0] }; +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1; +wire [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1_nxt = { rdcs1, a_rdcs1_dly[3:0] }; +wire [RL+12 + 4*EXTRA_CMD_DELAY -1 :0] a_rdEn_falling_edge = ~a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY :1] & a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY -1 :0]; +reg [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold0_fail; +reg [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold1_fail; +reg [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_gap_fail; +always @(*) begin + for (tck_index = 0; tck_index < RL+12 + 4*EXTRA_CMD_DELAY -2; tck_index = tck_index + 1) begin + a_rdEn_hold0_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+1] ) | ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+2] ) ); + a_rdEn_hold1_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+1] ) | ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+2] ) ); + a_rdEn_gap_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & a_rdEn[tck_index+2]; + end +end +always @(posedge clk) if (rst) begin + a_rdEn <= #TCQ '0; + a_rdcs0_dly <= #TCQ '0; + a_rdcs1_dly <= #TCQ '0; + a_rdcs0 <= #TCQ '0; + a_rdcs1 <= #TCQ '0; +end else begin + a_rdEn <= #TCQ rdEn; + a_rdcs0_dly <= #TCQ rdcs0; + a_rdcs1_dly <= #TCQ rdcs1; + a_rdcs0 <= #TCQ a_rdcs0_nxt; + a_rdcs1 <= #TCQ a_rdcs1_nxt; +end + +// rdcs0 not held for 2tCK after end of burst +wire a_mc_rd_en_000_hld = calDone & ( | a_rdEn_hold0_fail ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_000_hld); + +// rdcs1 not held for 2tCK after end of burst +wire a_mc_rd_en_001_hld = calDone & ( | a_rdEn_hold1_fail ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_001_hld); + +// rdEn not held low for 2tCK after end of burst +wire a_mc_rd_en_002_hld = calDone & ( | a_rdEn_gap_fail ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_002_hld); + +// mCL0 is less than RL-3 +wire a_mc_rd_en_003_ovf = ( mCL0 < (RL - 3) ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_003_ovf); + +// mCL1 is less than RL-3 +wire a_mc_rd_en_004_ovf = ( mCL1 < (RL - 3) ) & ( mCL1 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_004_ovf); + +// mCL2 is less than RL-3 +wire a_mc_rd_en_005_ovf = ( mCL2 < (RL - 3) ) & ( mCL2 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_005_ovf); + +// mCL3 is less than RL-3 +wire a_mc_rd_en_006_ovf = ( mCL3 < (RL - 3) ) & ( mCL3 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_006_ovf); + + +`endif +//synopsys translate_on + +endmodule + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej new file mode 100644 index 0000000..abf0911 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej @@ -0,0 +1,124 @@ +--- U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv ++++ /dev/null +@@ -114,55 +114,86 @@ + + reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn; + (* KEEP = "true" *) reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt; +-reg [18:0] rsMask[0:7]; ++reg [19:0] rsMask[0:15]; + +-function [18:0] rs2mask; ++// RS probably stands for rank select. ++// TODO edit below in worst case. ++function [19:0] rs2mask; + input [3:0] diff; + input slot2; +-case ({diff, slot2}) +- 5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111; +- 5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110; +- 5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000; +- 5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000; ++ input slot1; ++case ({diff, slot2, slot1}) ++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111; ++ 6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000; + default: rs2mask = 19'b000_0000_1000_0000_1111; + endcase + endfunction + + always @(posedge clk) begin: blk1 +- reg [3:0] rsNdx; +- for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1) +- rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]); ++ reg [4:0] rsNdx; ++ for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1) ++ rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]); + end + + always @(*) if (rst) begin + rdEn_nxt = 'b0; + end else begin + rdEn_nxt = (rdEn >> 4) +- | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} ++ | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} + : 'b0); + end + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv.rej new file mode 100644 index 0000000..217d7e9 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv.rej @@ -0,0 +1,31 @@ +--- U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv ++++ /dev/null +@@ -157,9 +157,13 @@ + // used in pushing new write CAS commands into the wrQ shift register. These values are + // calculated for both casslot0 and casslot2. + localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2; ++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2; + localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2; ++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2; + localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4; ++localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4; + localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4; ++localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4; + + integer i; + +@@ -192,10 +196,12 @@ + // Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical. + reg [3:0] oe_0_mux_cal; + wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2; +-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal; ++wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) : ++ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal); + + // tCK offset for mc. mccasSlot2 is timing critical. +-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0; ++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) : ++ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0); + + // Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical. + wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1}; diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bd b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bd new file mode 100644 index 0000000..c114c72 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bd @@ -0,0 +1,513 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0xBCE55F3980178BC9", + "design_src": "SBD", + "device": "xcu200-fsgd2104-2-e", + "name": "bd_afa8", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "scoped": "true", + "synth_flow_mode": "None", + "tool_version": "2020.2", + "validated": "true" + }, + "design_tree": { + "microblaze_I": "", + "rst_0": "", + "ilmb": "", + "dlmb": "", + "dlmb_cntlr": "", + "ilmb_cntlr": "", + "lmb_bram_I": "", + "second_dlmb_cntlr": "", + "second_ilmb_cntlr": "", + "second_lmb_bram_I": "", + "iomodule_0": "" + }, + "interface_ports": { + "IO": { + "mode": "Master", + "vlnv": "xilinx.com:interface:mcsio_bus_rtl:1.0" + }, + "TRACE": { + "mode": "Master", + "vlnv": "xilinx.com:interface:mbtrace_rtl:2.0" + } + }, + "ports": { + "Clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_ASYNC_RESET": { + "value": "Reset" + }, + "CLK_DOMAIN": { + "value": "bd_afa8_Clk", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000", + "value_src": "default" + } + } + }, + "Reset": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_HIGH" + } + } + } + }, + "components": { + "microblaze_I": { + "vlnv": "xilinx.com:ip:microblaze:11.0", + "xci_name": "bd_afa8_microblaze_I_0", + "parameters": { + "C_ASYNC_WAKEUP": { + "value": "3" + }, + "C_DEBUG_ENABLED": { + "value": "0" + }, + "C_FAULT_TOLERANT": { + "value": "0" + }, + "C_INSTANCE": { + "value": "mb_microblaze_0" + }, + "C_PC_WIDTH": { + "value": "17" + }, + "C_TRACE": { + "value": "1" + }, + "C_USE_BARREL": { + "value": "1" + }, + "C_USE_DIV": { + "value": "1" + }, + "C_USE_EXT_BRK": { + "value": "0" + }, + "C_USE_EXT_NM_BRK": { + "value": "0" + }, + "C_USE_HW_MUL": { + "value": "1" + }, + "C_USE_PCMP_INSTR": { + "value": "1" + }, + "C_USE_REORDER_INSTR": { + "value": "0" + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32" + }, + "Instruction": { + "range": "4G", + "width": "32" + } + } + }, + "interface_ports": { + "DLMB": { + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "ILMB": { + "mode": "Master", + "address_space_ref": "Instruction", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + } + }, + "hdl_attributes": { + "BMM_INFO_PROCESSOR": { + "value": "microblaze-le > bd_afa8 dlmb_cntlr", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "rst_0": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "bd_afa8_rst_0_0" + }, + "ilmb": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "bd_afa8_ilmb_0", + "parameters": { + "C_LMB_NUM_SLAVES": { + "value": "2" + } + }, + "interface_ports": { + "LMB_M": { + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0", + "LMB_Sl_1" + ] + } + } + }, + "dlmb": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "bd_afa8_dlmb_0", + "parameters": { + "C_LMB_NUM_SLAVES": { + "value": "3" + } + }, + "interface_ports": { + "LMB_M": { + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0", + "LMB_Sl_1", + "LMB_Sl_2" + ] + } + } + }, + "dlmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_afa8_dlmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000000000" + }, + "C_HIGHADDR": { + "value": "0x000000000000FFFF" + }, + "C_MASK": { + "value": "0x00000000C0010000" + } + }, + "hdl_attributes": { + "BMM_INFO_ADDRESS_SPACE": { + "value": "byte 0x00000000 32 > bd_afa8 lmb_bram_I bd_afa8 second_lmb_bram_I", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "ilmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_afa8_ilmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000000000" + }, + "C_HIGHADDR": { + "value": "0x000000000000FFFF" + }, + "C_MASK": { + "value": "0x0000000080010000" + } + } + }, + "lmb_bram_I": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "bd_afa8_lmb_bram_I_0", + "parameters": { + "Memory_Type": { + "value": "True_Dual_Port_RAM" + } + } + }, + "second_dlmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_afa8_second_dlmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000010000" + }, + "C_HIGHADDR": { + "value": "0x0000000000017FFF" + }, + "C_MASK": { + "value": "0x00000000C0010000" + } + }, + "hdl_attributes": { + "BMM_INFO_ADDRESS_RANGE": { + "value": " ", + "value_src": "default" + } + } + }, + "second_ilmb_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "bd_afa8_second_ilmb_cntlr_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000000010000" + }, + "C_HIGHADDR": { + "value": "0x0000000000017FFF" + }, + "C_MASK": { + "value": "0x0000000080010000" + } + } + }, + "second_lmb_bram_I": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "bd_afa8_second_lmb_bram_I_0", + "parameters": { + "Memory_Type": { + "value": "True_Dual_Port_RAM" + } + } + }, + "iomodule_0": { + "vlnv": "xilinx.com:ip:iomodule:3.1", + "xci_name": "bd_afa8_iomodule_0_0", + "parameters": { + "C_BASEADDR": { + "value": "0x0000000080000000" + }, + "C_HIGHADDR": { + "value": "0x000000008000FFFF" + }, + "C_INSTANCE": { + "value": "iomodule" + }, + "C_INTC_ADDR_WIDTH": { + "value": "17" + }, + "C_INTC_HAS_FAST": { + "value": "1" + }, + "C_INTC_USE_IRQ_OUT": { + "value": "1" + }, + "C_IO_BASEADDR": { + "value": "0x00000000C0000000" + }, + "C_IO_HIGHADDR": { + "value": "0x00000000FFFFFFFF" + }, + "C_IO_MASK": { + "value": "0x00000000C0000000" + }, + "C_MASK": { + "value": "0x00000000C0000000" + }, + "C_USE_IO_BUS": { + "value": "1" + } + } + } + }, + "interface_nets": { + "iomodule_0_IO": { + "interface_ports": [ + "IO", + "iomodule_0/IO_BUS" + ] + }, + "dlmb_sl_0": { + "interface_ports": [ + "dlmb/LMB_Sl_0", + "dlmb_cntlr/SLMB" + ] + }, + "dlmb_port_2": { + "interface_ports": [ + "second_dlmb_cntlr/BRAM_PORT", + "second_lmb_bram_I/BRAM_PORTA" + ] + }, + "dlmb_port": { + "interface_ports": [ + "dlmb_cntlr/BRAM_PORT", + "lmb_bram_I/BRAM_PORTA" + ] + }, + "ilmb_sl_0": { + "interface_ports": [ + "ilmb/LMB_Sl_0", + "ilmb_cntlr/SLMB" + ] + }, + "ilmb_port_2": { + "interface_ports": [ + "second_ilmb_cntlr/BRAM_PORT", + "second_lmb_bram_I/BRAM_PORTB" + ] + }, + "microblaze_I_Trace": { + "interface_ports": [ + "TRACE", + "microblaze_I/TRACE" + ] + }, + "dlmb_sl_1": { + "interface_ports": [ + "dlmb/LMB_Sl_1", + "iomodule_0/SLMB" + ] + }, + "ilmb_port": { + "interface_ports": [ + "ilmb_cntlr/BRAM_PORT", + "lmb_bram_I/BRAM_PORTB" + ] + }, + "dlmb_sl_2": { + "interface_ports": [ + "dlmb/LMB_Sl_2", + "second_dlmb_cntlr/SLMB" + ] + }, + "ilmb_sl_1": { + "interface_ports": [ + "ilmb/LMB_Sl_1", + "second_ilmb_cntlr/SLMB" + ] + }, + "dlmb": { + "interface_ports": [ + "microblaze_I/DLMB", + "dlmb/LMB_M" + ] + }, + "ilmb": { + "interface_ports": [ + "microblaze_I/ILMB", + "ilmb/LMB_M" + ] + } + }, + "nets": { + "Clk2": { + "ports": [ + "Clk", + "microblaze_I/Clk", + "ilmb/LMB_Clk", + "dlmb/LMB_Clk", + "dlmb_cntlr/LMB_Clk", + "ilmb_cntlr/LMB_Clk", + "second_dlmb_cntlr/LMB_Clk", + "second_ilmb_cntlr/LMB_Clk", + "iomodule_0/Clk", + "rst_0/slowest_sync_clk" + ] + }, + "Reset": { + "ports": [ + "Reset", + "rst_0/ext_reset_in" + ] + }, + "MB_Reset": { + "ports": [ + "rst_0/mb_reset", + "microblaze_I/Reset" + ] + }, + "LMB_Rst2": { + "ports": [ + "rst_0/bus_struct_reset", + "ilmb/SYS_Rst", + "dlmb/SYS_Rst", + "ilmb_cntlr/LMB_Rst", + "dlmb_cntlr/LMB_Rst", + "second_ilmb_cntlr/LMB_Rst", + "second_dlmb_cntlr/LMB_Rst" + ] + }, + "IO_Rst": { + "ports": [ + "rst_0/peripheral_reset", + "iomodule_0/Rst" + ] + } + }, + "addressing": { + "/microblaze_I": { + "address_spaces": { + "Data": { + "segments": { + "SEG_dlmb_cntlr_Mem": { + "address_block": "/dlmb_cntlr/SLMB/Mem", + "offset": "0x00000000", + "range": "64K" + }, + "SEG_iomodule_0_IO": { + "address_block": "/iomodule_0/SLMB/IO", + "offset": "0xC0000000", + "range": "1G" + }, + "SEG_iomodule_0_Reg": { + "address_block": "/iomodule_0/SLMB/Reg", + "offset": "0x80000000", + "range": "64K" + }, + "SEG_second_dlmb_cntlr_Mem": { + "address_block": "/second_dlmb_cntlr/SLMB/Mem", + "offset": "0x00010000", + "range": "32K" + } + } + }, + "Instruction": { + "segments": { + "SEG_ilmb_cntlr_Mem": { + "address_block": "/ilmb_cntlr/SLMB/Mem", + "offset": "0x00000000", + "range": "64K" + }, + "SEG_second_ilmb_cntlr_Mem": { + "address_block": "/second_ilmb_cntlr/SLMB/Mem", + "offset": "0x00010000", + "range": "32K" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bxml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bxml new file mode 100644 index 0000000..64d4f45 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bxml @@ -0,0 +1,100 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/hdl/bd_afa8_wrapper.v b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/hdl/bd_afa8_wrapper.v new file mode 100644 index 0000000..2347719 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/hdl/bd_afa8_wrapper.v @@ -0,0 +1,173 @@ +//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Command: generate_target bd_afa8_wrapper.bd +//Design : bd_afa8_wrapper +//Purpose: IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module bd_afa8_wrapper + (Clk, + IO_addr_strobe, + IO_address, + IO_byte_enable, + IO_read_data, + IO_read_strobe, + IO_ready, + IO_write_data, + IO_write_strobe, + Reset, + TRACE_data_access, + TRACE_data_address, + TRACE_data_byte_enable, + TRACE_data_read, + TRACE_data_write, + TRACE_data_write_value, + TRACE_dcache_hit, + TRACE_dcache_rdy, + TRACE_dcache_read, + TRACE_dcache_req, + TRACE_delay_slot, + TRACE_ex_piperun, + TRACE_exception_kind, + TRACE_exception_taken, + TRACE_icache_hit, + TRACE_icache_rdy, + TRACE_icache_req, + TRACE_instruction, + TRACE_jump_hit, + TRACE_jump_taken, + TRACE_mb_halted, + TRACE_mem_piperun, + TRACE_msr_reg, + TRACE_new_reg_value, + TRACE_of_piperun, + TRACE_pc, + TRACE_pid_reg, + TRACE_reg_addr, + TRACE_reg_write, + TRACE_valid_instr); + input Clk; + output IO_addr_strobe; + output [31:0]IO_address; + output [3:0]IO_byte_enable; + input [31:0]IO_read_data; + output IO_read_strobe; + input IO_ready; + output [31:0]IO_write_data; + output IO_write_strobe; + input Reset; + output TRACE_data_access; + output [0:31]TRACE_data_address; + output [0:3]TRACE_data_byte_enable; + output TRACE_data_read; + output TRACE_data_write; + output [0:31]TRACE_data_write_value; + output TRACE_dcache_hit; + output TRACE_dcache_rdy; + output TRACE_dcache_read; + output TRACE_dcache_req; + output TRACE_delay_slot; + output TRACE_ex_piperun; + output [0:4]TRACE_exception_kind; + output TRACE_exception_taken; + output TRACE_icache_hit; + output TRACE_icache_rdy; + output TRACE_icache_req; + output [0:31]TRACE_instruction; + output TRACE_jump_hit; + output TRACE_jump_taken; + output TRACE_mb_halted; + output TRACE_mem_piperun; + output [0:14]TRACE_msr_reg; + output [0:31]TRACE_new_reg_value; + output TRACE_of_piperun; + output [0:31]TRACE_pc; + output [0:7]TRACE_pid_reg; + output [0:4]TRACE_reg_addr; + output TRACE_reg_write; + output TRACE_valid_instr; + + wire Clk; + wire IO_addr_strobe; + wire [31:0]IO_address; + wire [3:0]IO_byte_enable; + wire [31:0]IO_read_data; + wire IO_read_strobe; + wire IO_ready; + wire [31:0]IO_write_data; + wire IO_write_strobe; + wire Reset; + wire TRACE_data_access; + wire [0:31]TRACE_data_address; + wire [0:3]TRACE_data_byte_enable; + wire TRACE_data_read; + wire TRACE_data_write; + wire [0:31]TRACE_data_write_value; + wire TRACE_dcache_hit; + wire TRACE_dcache_rdy; + wire TRACE_dcache_read; + wire TRACE_dcache_req; + wire TRACE_delay_slot; + wire TRACE_ex_piperun; + wire [0:4]TRACE_exception_kind; + wire TRACE_exception_taken; + wire TRACE_icache_hit; + wire TRACE_icache_rdy; + wire TRACE_icache_req; + wire [0:31]TRACE_instruction; + wire TRACE_jump_hit; + wire TRACE_jump_taken; + wire TRACE_mb_halted; + wire TRACE_mem_piperun; + wire [0:14]TRACE_msr_reg; + wire [0:31]TRACE_new_reg_value; + wire TRACE_of_piperun; + wire [0:31]TRACE_pc; + wire [0:7]TRACE_pid_reg; + wire [0:4]TRACE_reg_addr; + wire TRACE_reg_write; + wire TRACE_valid_instr; + + bd_afa8 bd_afa8_i + (.Clk(Clk), + .IO_addr_strobe(IO_addr_strobe), + .IO_address(IO_address), + .IO_byte_enable(IO_byte_enable), + .IO_read_data(IO_read_data), + .IO_read_strobe(IO_read_strobe), + .IO_ready(IO_ready), + .IO_write_data(IO_write_data), + .IO_write_strobe(IO_write_strobe), + .Reset(Reset), + .TRACE_data_access(TRACE_data_access), + .TRACE_data_address(TRACE_data_address), + .TRACE_data_byte_enable(TRACE_data_byte_enable), + .TRACE_data_read(TRACE_data_read), + .TRACE_data_write(TRACE_data_write), + .TRACE_data_write_value(TRACE_data_write_value), + .TRACE_dcache_hit(TRACE_dcache_hit), + .TRACE_dcache_rdy(TRACE_dcache_rdy), + .TRACE_dcache_read(TRACE_dcache_read), + .TRACE_dcache_req(TRACE_dcache_req), + .TRACE_delay_slot(TRACE_delay_slot), + .TRACE_ex_piperun(TRACE_ex_piperun), + .TRACE_exception_kind(TRACE_exception_kind), + .TRACE_exception_taken(TRACE_exception_taken), + .TRACE_icache_hit(TRACE_icache_hit), + .TRACE_icache_rdy(TRACE_icache_rdy), + .TRACE_icache_req(TRACE_icache_req), + .TRACE_instruction(TRACE_instruction), + .TRACE_jump_hit(TRACE_jump_hit), + .TRACE_jump_taken(TRACE_jump_taken), + .TRACE_mb_halted(TRACE_mb_halted), + .TRACE_mem_piperun(TRACE_mem_piperun), + .TRACE_msr_reg(TRACE_msr_reg), + .TRACE_new_reg_value(TRACE_new_reg_value), + .TRACE_of_piperun(TRACE_of_piperun), + .TRACE_pc(TRACE_pc), + .TRACE_pid_reg(TRACE_pid_reg), + .TRACE_reg_addr(TRACE_reg_addr), + .TRACE_reg_write(TRACE_reg_write), + .TRACE_valid_instr(TRACE_valid_instr)); +endmodule diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xci new file mode 100644 index 0000000..1c2d623 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xci @@ -0,0 +1,1032 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_afa8_microblaze_I_0 + + + bd_afa8_Clk + 100000000 + 0 + 0 + 0.000 + + 30000000 + 0 + 0 + 0.000 + 1 + 32 + 0 + LEVEL_HIGH + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 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Enable Fault Tolerance Support + 0 + + + C_ECC_USE_CE_EXCEPTION + Correctable Error Exception + 0 + + + C_LOCKSTEP_SLAVE + Lockstep Slave + 0 + + + C_LOCKSTEP_MASTER + Lockstep Master + 0 + + + C_ENDIANNESS + 1 + + + C_FAMILY + virtexuplus + + + C_DATA_SIZE + 32 + + + C_LMB_DATA_SIZE + 32 + + + C_INSTR_SIZE + 32 + + + C_IADDR_SIZE + 32 + + + C_PIADDR_SIZE + 32 + + + C_DADDR_SIZE + 32 + + + C_INSTANCE + bd_afa8_microblaze_I_0 + + + C_AVOID_PRIMITIVES + 0 + + + C_AREA_OPTIMIZED + Select implementation optimization + 0 + + + C_OPTIMIZATION + 0 + + + C_INTERCONNECT + Select Bus Interface + 2 + + + C_BASE_VECTORS + Vector Base Address + 0x0000000000000000 + + + C_M_AXI_DP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_M_AXI_D_BUS_EXCEPTION + Enable Data-side AXI Exception + 0 + + + + true + + + + + + C_M_AXI_IP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IP_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_I_BUS_EXCEPTION + Enable Instruction-side AXI Exception + 0 + + + + true + + + + + + C_D_LMB + Enable Local Memory Bus Data Interface + 1 + + + C_D_LMB_PROTOCOL + Local Memory Bus Data Protocol + 0 + + + C_D_AXI + Enable Peripheral AXI Data Interface + 0 + + + C_I_LMB + Enable Local Memory Bus Instruction Interface + 1 + + + C_I_LMB_PROTOCOL + Local Memory Bus Instruction Protocol + 0 + + + C_I_AXI + Enable Peripheral AXI Instruction Interface + 0 + + + G_TEMPLATE_LIST + Select Configuration + 0 + + + C_USE_MSR_INSTR + Enable Additional Machine Status Register Instructions + 0 + + + C_USE_PCMP_INSTR + Enable Pattern Comparator + 1 + + + C_USE_BARREL + Enable Barrel Shifter + 1 + + + C_USE_DIV + Enable Integer Divider + 1 + + + C_USE_HW_MUL + Enable Integer Multiplier + 1 + + + C_USE_FPU + Enable Floating Point Unit + 0 + + + C_USE_REORDER_INSTR + Enable Reversed Load/Store and Swap Instructions + 0 + + + C_UNALIGNED_EXCEPTIONS + Enable Unaligned Data Exception + 0 + + + C_ILL_OPCODE_EXCEPTION + Enable Illegal Instruction Exception + 0 + + + C_DIV_ZERO_EXCEPTION + Enable Integer Divide Exception + 0 + + + + true + + + + + + C_FPU_EXCEPTION + Enable Floating Point Unit Exceptions + 0 + + + + false + + + + + + C_FSL_LINKS + Number of Stream Links + 0 + + + C_USE_EXTENDED_FSL_INSTR + Enable Additional Stream Instructions + 0 + + + C_FSL_EXCEPTION + Enable Stream Exception + 0 + + + + false + + + + + + C_USE_STACK_PROTECTION + Enable stack protection + 0 + + + + true + + + + + + C_IMPRECISE_EXCEPTIONS + Allow Imprecise Exceptions + 0 + + + C_USE_INTERRUPT + 0 + + + C_USE_EXT_BRK + 0 + + + C_USE_EXT_NM_BRK + 0 + + + C_USE_NON_SECURE + 0 + + + C_USE_MMU + Memory Management + 0 + + + + true + + + + + + C_MMU_DTLB_SIZE + Data Shadow Translation Look-Aside Buffer Size + 4 + + + + false + + + + + + C_MMU_ITLB_SIZE + Instruction Shadow Translation Look-Aside Buffer Size + 2 + + + + false + + + + + + C_MMU_TLB_ACCESS + Enable Access to Memory Management Special Registers + 3 + + + + false + + + + + + C_MMU_ZONES + Number of Memory Protection Zones + 16 + + + + false + + + + + + C_MMU_PRIVILEGED_INSTR + Privileged Instructions + 0 + + + + false + + + + + + C_USE_BRANCH_TARGET_CACHE + Enable Branch Target Cache + 0 + + + + true + + + + + + C_BRANCH_TARGET_CACHE_SIZE + Branch Target Cache Size + 0 + + + + true + + + + + + C_PC_WIDTH + 17 + + + C_PVR + Specifies Processor Version Register + 0 + + + C_PVR_USER1 + Specify USER1 Bits in Processor Version Register + 0x00 + + + C_PVR_USER2 + Specify USER2 Bits in Processor Version Register + 0x00000000 + + + C_DYNAMIC_BUS_SIZING + 0 + + + C_RESET_MSR + Specify Reset Value for Select MSR Bits + 0x00000000 + + + C_OPCODE_0x0_ILLEGAL + Generate Illegal Instruction Exception for NULL Instruction + 0 + + + C_DEBUG_ENABLED + MicroBlaze Debug Module Interface + 0 + + + C_DEBUG_INTERFACE + MicroBlaze Debug Connection + 0 + + + C_NUMBER_OF_PC_BRK + Number of PC Breakpoints + 1 + + + C_NUMBER_OF_RD_ADDR_BRK + Number of Read Address Watchpoints + 0 + + + C_NUMBER_OF_WR_ADDR_BRK + Number of Write Address Watchpoints + 0 + + + C_DEBUG_EVENT_COUNTERS + Number of Performance Monitor Event Counters + 5 + + + C_DEBUG_LATENCY_COUNTERS + Number of Performance Monitor Latency Counters + 1 + + + C_DEBUG_COUNTER_WIDTH + Performance Monitor Counter Width + 32 + + + C_DEBUG_TRACE_SIZE + Trace Buffer Size + 8192 + + + C_DEBUG_EXTERNAL_TRACE + External Trace + 0 + + + C_DEBUG_TRACE_ASYNC_RESET + Use Asynchrnous Reset for External Trace + 0 + + + C_DEBUG_PROFILE_SIZE + Profile Buffer Size + 0 + + + C_INTERRUPT_IS_EDGE + Sense Interrupt on Edge vs. Level + 0 + + + C_EDGE_IS_POSITIVE + Sense Interrupt on Rising vs. Falling Edge + 1 + + + C_ASYNC_INTERRUPT + 1 + + + C_ASYNC_WAKEUP + 3 + + + C_M0_AXIS_DATA_WIDTH + 32 + + + C_S0_AXIS_DATA_WIDTH + 32 + + + C_M1_AXIS_DATA_WIDTH + 32 + + + C_S1_AXIS_DATA_WIDTH + 32 + + + C_M2_AXIS_DATA_WIDTH + 32 + + + C_S2_AXIS_DATA_WIDTH + 32 + + + C_M3_AXIS_DATA_WIDTH + 32 + + + C_S3_AXIS_DATA_WIDTH + 32 + + + C_M4_AXIS_DATA_WIDTH + 32 + + + C_S4_AXIS_DATA_WIDTH + 32 + + + C_M5_AXIS_DATA_WIDTH + 32 + + + C_S5_AXIS_DATA_WIDTH + 32 + + + C_M6_AXIS_DATA_WIDTH + 32 + + + C_S6_AXIS_DATA_WIDTH + 32 + + + C_M7_AXIS_DATA_WIDTH + 32 + + + C_S7_AXIS_DATA_WIDTH + 32 + + + C_M8_AXIS_DATA_WIDTH + 32 + + + C_S8_AXIS_DATA_WIDTH + 32 + + + C_M9_AXIS_DATA_WIDTH + 32 + + + C_S9_AXIS_DATA_WIDTH + 32 + + + C_M10_AXIS_DATA_WIDTH + 32 + + + C_S10_AXIS_DATA_WIDTH + 32 + + + C_M11_AXIS_DATA_WIDTH + 32 + + + C_S11_AXIS_DATA_WIDTH + 32 + + + C_M12_AXIS_DATA_WIDTH + 32 + + + C_S12_AXIS_DATA_WIDTH + 32 + + + C_M13_AXIS_DATA_WIDTH + 32 + + + C_S13_AXIS_DATA_WIDTH + 32 + + + C_M14_AXIS_DATA_WIDTH + 32 + + + C_S14_AXIS_DATA_WIDTH + 32 + + + C_M15_AXIS_DATA_WIDTH + 32 + + + C_S15_AXIS_DATA_WIDTH + 32 + + + C_ICACHE_BASEADDR + Base Address + 0x0000000000000000 + + + C_ICACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + C_USE_ICACHE + Enable Instruction Cache + 0 + + + C_ALLOW_ICACHE_WR + Enable Writes + 1 + + + C_ADDR_TAG_BITS + 17 + + + C_CACHE_BYTE_SIZE + Size in Bytes + 8192 + + + C_ICACHE_LINE_LEN + Line Length + 4 + + + C_ICACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 1 + + + C_ICACHE_STREAMS + Number of Streams + 0 + + + + true + + + + + + C_ICACHE_VICTIMS + Number of Victims + 0 + + + + true + + + + + + C_ICACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + + true + + + + + + C_ICACHE_DATA_WIDTH + Data Width + 0 + + + + true + + + + + + C_M_AXI_IC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_DATA_WIDTH + 32 + + + C_M_AXI_IC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IC_USER_VALUE + 31 + + + + true + + + + + + C_M_AXI_IC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_BUSER_WIDTH + 1 + + + + true + + + + + + C_DCACHE_BASEADDR + Base Address + 0x0000000000000000 + + + C_DCACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + C_USE_DCACHE + Enable Data Cache + 0 + + + C_ALLOW_DCACHE_WR + Enable Writes + 1 + + + C_DCACHE_ADDR_TAG + 17 + + + C_DCACHE_BYTE_SIZE + Size in Bytes + 8192 + + + C_DCACHE_LINE_LEN + Line Length + 4 + + + C_DCACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 1 + + + C_DCACHE_USE_WRITEBACK + Enable Write-back Storage Policy + 0 + + + + true + + + + + + C_DCACHE_VICTIMS + Number of Victims + 0 + + + + false + + + + + + C_DCACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + C_DCACHE_DATA_WIDTH + Data Width + 0 + + + + false + + + + + + C_M_AXI_DC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_DATA_WIDTH + 32 + + + C_M_AXI_DC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DC_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_M_AXI_DC_USER_VALUE + 31 + + + + true + + + + + + C_M_AXI_DC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_BUSER_WIDTH + 1 + + + + true + + + + + + + + + choice_list_29910ba8 + GENERIC + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_b1aff63c + 32 + 48 + 64 + + + choice_list_b94541ab + 0 + 2 + 4 + 8 + + + choice_list_dd2843c6 + 1 + 2 + 4 + 8 + + + choice_list_f86403bf + 4 + 8 + 16 + + + choice_pairs_0000a26c + 0 + 1 + 2 + 3 + + + choice_pairs_0873e75e + 0 + 1 + + + choice_pairs_1075faf2 + 0 + 1 + 2 + + + choice_pairs_126baff7 + 0 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_13d40c7c + 0 + 32 + 64 + 128 + 256 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_2058dc69 + 0 + 1 + + + choice_pairs_22d9f392 + 0 + 1 + 2 + 3 + + + choice_pairs_3eb333f8 + 0 + 1 + 2 + + + choice_pairs_443ae6cc + 0 + 1 + 2 + 3 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_56d5ba32 + 0 + 1 + 2 + + + choice_pairs_5ab38e91 + 0 + 1 + 2 + + + choice_pairs_5b1842a1 + 0 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_75c71b2b + 0 + 1 + 2 + 3 + + + choice_pairs_7ad6afc0 + 0 + 1 + 2 + 3 + + + choice_pairs_7bfd418d + 0 + 1 + 2 + + + choice_pairs_7dd2834f + 0 + 8 + 9 + 10 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_8b498448 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + + + choice_pairs_b1fa18d9 + 0 + 1 + 2 + + + choice_pairs_c471ed24 + 32 + 36 + 40 + 44 + 48 + 52 + 64 + + + choice_pairs_db57ca32 + 0 + 1 + 2 + + + choice_pairs_e7a1eb81 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_ff364cce + 2 + 3 + + + + + microblaze + + + + endian + little + + + elf_class + 32-bit + + + instance_path + + + + bootloop_file + data/mb_bootloop_le.elf + + + processor_type + MICROBLAZE_LE + + + is_visible + true + + + + + The MicroBlaze 32 and 64 bit soft processor core, providing an instruction set optimized for embedded applications with many user-configurable options. MicroBlaze has many advanced architecture features like Instruction and Data-side cache with AXI interfaces, Floating-Point unit (FPU), Memory Management Unit (MMU), and fault tolerance support. +It is highly recommended to create MicroBlaze systems within Vivado IP Integrator, to enable export to the Xilinx Software Development Kit (SDK) for software development. + + + + C_SCO + 0 + + + + true + + + + + + C_FREQ + 100000000 + + + + true + + + + + + C_DATA_SIZE + Select Processor Implementation + 32 + + + + true + + + + + + C_ADDR_SIZE + Select Extended Addressing + 32 + + + + true + + + + + + C_DYNAMIC_BUS_SIZING + 0 + + + + true + + + + + + C_PC_WIDTH + 17 + + + + true + + + + + + C_INSTANCE + mb_microblaze_0 + + + + true + + + + + + C_AVOID_PRIMITIVES + 0 + + + + true + + + + + + C_FAULT_TOLERANT + Enable Fault Tolerance Support + 0 + + + + true + + + + + + C_ECC_USE_CE_EXCEPTION + Correctable Error Exception + 0 + + + + true + + + + + + C_LOCKSTEP_SLAVE + Lockstep Slave + 0 + + + + true + + + + + + C_ENDIANNESS + Endianness + 1 + + + + true + + + + + + C_AREA_OPTIMIZED + Select implementation optimization + 0 + + + + true + + + + + + C_OPTIMIZATION + 0 + + + + true + + + + + + C_INTERCONNECT + Select Bus Interface + 2 + + + + true + + + + + + C_BASE_VECTORS + Vector Base Address + 0x0000000000000000 + + + + true + + + + + + C_USE_CONFIG_RESET + 0 + + + + true + + + + + + C_NUM_SYNC_FF_CLK + Synchronizing FFs to Clk region + 2 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_IRQ + Synchronizing FFs to Clk region for interrupt input + 1 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_DEBUG + Synchronizing FFs to Clk region in debug module + 2 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_CLK + Synchronizing FFs to Dbg_Clk region + 1 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_TRACE_CLK + Synchronizing FFs to Dbg_Trace_Clk region + 2 + + + + true + + + + + + C_M_AXI_DP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_D_AXI + Enable Peripheral AXI Data Interface + 0 + + + + true + + + + + + C_DP_AXI_MON + Use Monitor Interface for Peripheral AXI Data Interface + 0 + + + + true + + + + + + C_DC_AXI_MON + Use Monitor Interface for Cache AXI Data Interface + 0 + + + + true + + + + + + C_D_LMB + Enable Local Memory Bus Data Interface + 1 + + + + true + + + + + + C_D_LMB_PROTOCOL + Local Memory Bus Data Protocol + 0 + + + + true + + + + + + C_D_LMB_MON + Use Monitor Interface for Local Memory Bus Data Interface + 0 + + + + true + + + + + + C_M_AXI_IP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IP_ADDR_WIDTH + 32 + + + + true + + + + + + C_I_AXI + Enable Peripheral AXI Instruction Interface + 0 + + + + true + + + + + + C_IP_AXI_MON + Use Monitor Interface for Peripheral AXI Instruction Interface + 0 + + + + true + + + + + + C_IC_AXI_MON + Use Monitor Interface for Cache AXI Instruction Interface + 0 + + + + true + + + + + + C_I_LMB + Enable Local Memory Bus Instruction Interface + 1 + + + + true + + + + + + C_I_LMB_PROTOCOL + Local Memory Bus Instruction Protocol + 0 + + + + true + + + + + + C_I_LMB_MON + Use Monitor Interface for Local Memory Bus Instruction Interface + 0 + + + + true + + + + + + C_TRACE + Enable Trace Bus Interface + 1 + + + + true + + + + + + C_LOCKSTEP_SELECT + Lockstep Interface + 0 + + + + true + + + + + + C_ENABLE_DISCRETE_PORTS + Enable Discrete Ports + 0 + + + + true + + + + + + C_M_AXI_DC_USER_SIGNALS + Enable M_AXI_DC User Signals + 0 + + + + true + + + + + + C_M_AXI_IC_USER_SIGNALS + Enable M_AXI_IC User Signals + 0 + + + + true + + + + + + G_TEMPLATE_LIST + Select Configuration + 0 + + + + true + + + + + + G_USE_EXCEPTIONS + Enable Exceptions + 0 + + + + true + + + + + + C_USE_MSR_INSTR + Enable Additional Machine Status Register Instructions + 0 + + + + true + + + + + + C_USE_PCMP_INSTR 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virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 6 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xml new file mode 100644 index 0000000..53d556e --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xml @@ -0,0 +1,8812 @@ + + + xilinx.com + customized_ip + bd_afa8_iomodule_0_0 + 1.0 + + + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + PROTOCOL + STANDARD + + + none + + + + + + + CLK.CLK + Clk + Clock Input + + + + + + + CLK + + + Clk + + + + + + ASSOCIATED_BUSIF + SLMB + + + ASSOCIATED_RESET + Rst:TMR_Rst + + + FREQ_HZ + Clk frequency + Clk frequency + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + bd_afa8_Clk + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.Rst + Rst + Reset Input + + + + + + + RST + + + Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.TMR_Rst + TMR_Rst + TMR Reset Input + + + + + + + RST + + + TMR_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + IO_BUS + IO_BUS + MicroBlaze MCS IO Bus Interface + + + + + + + ADDR_STROBE + + + IO_Addr_Strobe + + + + + ADDRESS + + + IO_Address + + + + + BYTE_ENABLE + + + IO_Byte_Enable + + + + + READ_DATA + + + IO_Read_Data + + + + + READ_STROBE + + + IO_Read_Strobe + + + + + READY + + + IO_Ready + + + + + WRITE_DATA + + + IO_Write_Data + + + + + WRITE_STROBE + + + IO_Write_Strobe + + + + + + + true + + + + + + INTERRUPT.UART_Interrupt + UART_Interrupt + + + + + + + INTERRUPT + + + UART_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT1_Interrupt + FIT1_Interrupt + + + + + + + INTERRUPT + + + FIT1_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT2_Interrupt + FIT2_Interrupt + + + + + + + INTERRUPT + + + FIT2_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT3_Interrupt + FIT3_Interrupt + + + + + + + INTERRUPT + + + FIT3_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT4_Interrupt + FIT4_Interrupt + + + + + + + INTERRUPT + + + FIT4_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.PIT1_Interrupt + PIT1_Interrupt + + + + + + + INTERRUPT + + + PIT1_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.PIT2_Interrupt + PIT2_Interrupt + + + + + + + INTERRUPT + + + PIT2_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.PIT3_Interrupt + PIT3_Interrupt + + + + + + + INTERRUPT + + + PIT3_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.PIT4_Interrupt + PIT4_Interrupt + + + + + + + INTERRUPT + + + PIT4_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI1_Interrupt + GPI1_Interrupt + + + + + + + INTERRUPT + + + GPI1_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI2_Interrupt + GPI2_Interrupt + + + + + + + INTERRUPT + + + GPI2_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI3_Interrupt + GPI3_Interrupt + + + + + + + INTERRUPT + + + GPI3_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI4_Interrupt + GPI4_Interrupt + + + + + + + INTERRUPT + + + GPI4_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Interrupt + INTC_Interrupt + + + + + + + INTERRUPT + + + INTC_Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + none + + + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Irq_Single + INTC_IRQ + + + + + + + INTERRUPT + + + INTC_IRQ + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Irq + INTC_IRQ + + + + + + + ACK + + + INTC_Processor_Ack + + + + + ADDRESS + + + INTC_Interrupt_Address + + + + + INTERRUPT + + + INTC_IRQ + + + + + + SENSITIVITY + LEVEL_HIGH + + + LOW_LATENCY + 0 + + + + + + false + + + + + + INTERRUPT.INTC_Irq_Out + INTC_IRQ_OUT + + + + + + + INTERRUPT + + + INTC_IRQ_OUT + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + UART + UART + UART TX/RX + + + + + + + RxD + + + UART_Rx + + + + + TxD + + + UART_Tx + + + + + + BOARD.ASSOCIATED_PARAM + UART_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + UART_CLK.CLK + UART_Clk + Asynchronous UART Clock Input + + + + + + + CLK + + + UART_Clk + + + + + + ASSOCIATED_BUSIF + SLMB + + + ASSOCIATED_RESET + UART_Rst:TMR_Rst + + + FREQ_HZ + UART Clk frequency + UART Clk frequency + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + UART_RST.Rst + UART_Rst + Asynchronous UART Reset Input + + + + + + + RST + + + UART_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + GPIO1 + GPIO1 + General Purpose IO + + + + + + + TRI_I + + + GPI1 + + + + + TRI_O + + + GPO1 + + + + + + C_USE_GPO1 + 0 + + + + true + + + + + + C_GPO1_SIZE + 32 + + + + true + + + + + + C_GPO1_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI1 + 0 + + + + true + + + + + + C_GPI1_SIZE + 32 + + + + true + + + + + + C_GPI1_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO1_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO2 + GPIO2 + General Purpose IO + + + + + + + TRI_I + + + GPI2 + + + + + TRI_O + + + GPO2 + + + + + + C_USE_GPO2 + 0 + + + + true + + + + + + C_GPO2_SIZE + 32 + + + + true + + + + + + C_GPO2_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI2 + 0 + + + + true + + + + + + C_GPI2_SIZE + 32 + + + + true + + + + + + C_GPI2_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO2_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO3 + GPIO3 + General Purpose IO + + + + + + + TRI_I + + + GPI3 + + + + + TRI_O + + + GPO3 + + + + + + C_USE_GPO3 + 0 + + + + true + + + + + + C_GPO3_SIZE + 32 + + + + true + + + + + + C_GPO3_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI3 + 0 + + + + true + + + + + + C_GPI3_SIZE + 32 + + + + true + + + + + + C_GPI3_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO3_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO4 + GPIO4 + General Purpose IO + + + + + + + TRI_I + + + GPI4 + + + + + TRI_O + + + GPO4 + + + + + + C_USE_GPO4 + 0 + + + + true + + + + + + C_GPO4_SIZE + 32 + + + + true + + + + + + C_GPO4_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI4 + 0 + + + + true + + + + + + C_GPI4_SIZE + 32 + + + + true + + + + + + C_GPI4_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO4_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + + + SLMB + LMB memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + UART_RX + UART Receive Data Register + UART Receive Data Register + 0x0 + 8 + true + read-only + + 0x0 + + + UART_RX + Receive Data + Data received by the UART. + 0 + 8 + true + read-only + + 0 + 0 + + modify + false + + + + + false + + + + + + UART_TX + UART Transmit Data Register + UART Transmit Data Register + 0x4 + 8 + true + write-only + + 0x0 + + + UART_TX + Transmit Data + Data to be transmitted by the UART. + 0 + 8 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART_Status + UART Status Register + UART Status Register + 0x8 + 8 + true + read-only + + 0x0 + + + Rx_Valid_Data + Rx Valid Data + Indicates if the receive register has valid data: + 0 - Receive register is empty. + 1 - Receive register has valid data. + + 0 + 1 + true + read-only + + 0 + 0 + + false + + + Tx_Used + Tx Used + Indicates if the transmit register is in use: + 0 - Transmit register is not in use. + 1 - Transmit register is in use. + + 3 + 1 + true + read-only + + 0 + 0 + + false + + + Overrun_Error + Overrun Error + Indicates that an overrun error has occurred: + 0 - No overrun has occurred. + 1 - An overrun has occurred. + + 5 + 1 + true + read-only + + 0 + 0 + + false + + + Frame_Error + Frame Error + Indicates that an frame error has occurred: + 0 - No frame error has occurred. + 1 - A frame error has occurred. + + 6 + 1 + true + read-only + + 0 + 0 + + false + + + Parity_Error + Parity Error + Indicates that a parity error has occurred: + 0 - No parity error has occurred. + 1 - A parity error occurred. + + 7 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_MODE + Interrupt Mode Register + Interrupt Mode Register + 0xC + 17 + true + write-only + + 0x0 + + + IRQ_Mode + IRQ Mode + Interrupt Mode. +For each bit: + W - When written with 1 the corresponding interrupt will use fast mode. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + GPO_1 + General Purpose Output 1 Register + General Purpose Output 1 Register + 0x10 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO_2 + General Purpose Output 2 Register + General Purpose Output 2 Register + 0x14 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO_3 + General Purpose Output 3 Register + General Purpose Output 3 Register + 0x18 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO_4 + General Purpose Output 4 Register + General Purpose Output 4 Register + 0x1C + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_1 + General Purpose Input 1 Register + General Purpose Input 1 Register + 0x20 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_2 + General Purpose Input 2 Register + General Purpose Input 2 Register + 0x24 + 32 + true + read-only + + 0 + + + CPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_3 + General Purpose Input 3 Register + General Purpose Input 3 Register + 0x28 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI_4 + General Purpose Input 4 Register + General Purpose Input 4 Register + 0x2C + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_STATUS + Interrupt Status Register + Interrupt Status Register + 0x30 + 17 + true + read-only + + 0x0 + + + UART_ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART_TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART_RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC_Interrupt + External interrupt input signal + Interrupt Status Register. +For each bit: + R - Reads active interrupt signal. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_PENDING + Interrupt Pending Register + Interrupt Pending Register + 0x34 + 17 + true + read-only + + 0x0 + + + UART_ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART_TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART_RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT_4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT_4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI_4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC_Interrupt + Enabled interrupt events that have occurred + Interrupt Pending. +For each bit: + R - Reads enabled interrupt event that has occurred. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_ENABLE + Interrupt Enable Register + Interrupt Enable Register + 0x38 + 17 + true + write-only + + 0x0 + + + UART_ERR + UART Error + UART Error interrupt enabled. + 0 + 1 + true + write-only + + 0 + 0 + + false + + + UART_TX + UART Transmitted Data + UART Transmitted Data interrupt enabled. + 1 + 1 + true + write-only + + 0 + 0 + + false + + + UART_RX + UART Received Data + UART Received Data interrupt enabled. + 2 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_1 + PIT 1 + PIT 1 interrupt enabled. + 3 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_2 + PIT 2 + PIT 2 interrupt enabled. + 4 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_3 + PIT 3 + PIT 3 interrupt enabled. + 5 + 1 + true + write-only + + 0 + 0 + + false + + + PIT_4 + PIT 4 + PIT 4 interrupt enabled. + 6 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_1 + FIT 1 + FIT 1 interrupt enabled. + 7 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_2 + FIT 2 + FIT 2 interrupt enabled. + 8 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_3 + FIT 3 + FIT 3 interrupt enabled. + 9 + 1 + true + write-only + + 0 + 0 + + false + + + FIT_4 + FIT 4 + FIT 4 interrupt enabled. + 10 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_1 + GPI 1 + GPI 1 interrupt enabled. + 11 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_2 + GPI 2 + GPI 2 interrupt enabled. + 12 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_3 + GPI 3 + GPI 3 interrupt enabled. + 13 + 1 + true + write-only + + 0 + 0 + + false + + + GPI_4 + GPI 4 + GPI 4 interrupt enabled. + 14 + 1 + true + write-only + + 0 + 0 + + false + + + INTC_Interrupt + Enable external interrupt input signals + Interrupt Enable. +For each bit: + W - Enable external interrupt input signal. + + 16 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_ACK + Interrupt Acknowledge Register + Interrupt Acknowledge Register + 0x3C + 17 + true + write-only + + 0x0 + + + IRQ_Acknowledge + IRQ Acknowledge + Interrupt Acknowledge. +For each bit: + W - When written with 1 clear bit in IRQ_STATUS and IRQ_PENDING. + + 0 + 17 + true + write-only + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + PIT1_PRELOAD + PIT 1 Preload Register + PIT 1 Preload Register + 0x40 + 32 + true + write-only + + 0x0 + + + PIT1_Preload + PIT1 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1_COUNTER + PIT 1 Counter Register + PIT 1 Counter Register + 0x44 + 32 + true + read-only + + 0x0 + + + PIT1_Counter + PIT1 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1_CONTROL + PIT 1 Control Register + PIT 1 Control Register + 0x48 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT1_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART_BAUD + UART Programmable Baud Rate + UART Programmable Baud Rate + 0x4C + 8 + true + write-only + + 0x0 + + + UART_BAUD + Baud Rate + Programmable UART Baud Rate. + 0 + 20 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2_PRELOAD + PIT 2 Preload Register + PIT 2 Preload Register + 0x50 + 32 + true + write-only + + 0x0 + + + PIT2_Preload + PIT2 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2_COUNTER + PIT 2 Counter Register + PIT 2 Counter Register + 0x54 + 32 + true + read-only + + 0x0 + + + PIT2_Counter + PIT2 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2_CONTROL + PIT 2 Control Register + PIT 2 Control Register + 0x58 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT2_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3_PRELOAD + PIT 3 Preload Register + PIT 3 Preload Register + 0x60 + 32 + true + write-only + + 0x0 + + + PIT3_Preload + PIT3 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3_COUNTER + PIT 3 Counter Register + PIT 3 Counter Register + 0x64 + 32 + true + read-only + + 0x0 + + + PIT3_Counter + PIT3 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3_CONTROL + PIT 3 Control Register + PIT 3 Control Register + 0x68 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT3_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4_PRELOAD + PIT 4 Preload Register + PIT 4 Preload Register + 0x70 + 32 + true + write-only + + 0x0 + + + PIT4_Preload + PIT4 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4_COUNTER + PIT 4 Counter Register + PIT 4 Counter Register + 0x74 + 32 + true + read-only + + 0x0 + + + PIT4_Counter + PIT4 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4_CONTROL + PIT 4 Control Register + PIT 4 Control Register + 0x78 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT4_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_0 + Interrupt Vector Register 0 + Interrupt Vector Register 0 + 0x80 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 0 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_1 + Interrupt Vector Register 1 + Interrupt Vector Register 1 + 0x84 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 1 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_2 + Interrupt Vector Register 2 + Interrupt Vector Register 2 + 0x88 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 2 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_3 + Interrupt Vector Register 3 + Interrupt Vector Register 3 + 0x8C + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 3 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_4 + Interrupt Vector Register 4 + Interrupt Vector Register 4 + 0x90 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 4 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_5 + Interrupt Vector Register 5 + Interrupt Vector Register 5 + 0x94 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 5 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_6 + Interrupt Vector Register 6 + Interrupt Vector Register 6 + 0x98 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 6 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_7 + Interrupt Vector Register 7 + Interrupt Vector Register 7 + 0x9C + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 7 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_8 + Interrupt Vector Register 8 + Interrupt Vector Register 8 + 0xA0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 8 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_9 + Interrupt Vector Register 9 + Interrupt Vector Register 9 + 0xA4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 9 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_10 + Interrupt Vector Register 10 + Interrupt Vector Register 10 + 0xA8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 10 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_11 + Interrupt Vector Register 11 + Interrupt Vector Register 11 + 0xAC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 11 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_12 + Interrupt Vector Register 12 + Interrupt Vector Register 12 + 0xB0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 12 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_13 + Interrupt Vector Register 13 + Interrupt Vector Register 13 + 0xB4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 13 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_14 + Interrupt Vector Register 14 + Interrupt Vector Register 14 + 0xB8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 14 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_16 + Interrupt Vector Register 16 + Interrupt Vector Register 16 + 0xC0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 16 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_17 + Interrupt Vector Register 17 + Interrupt Vector Register 17 + 0xC4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 17 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_18 + Interrupt Vector Register 18 + Interrupt Vector Register 18 + 0xC8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 18 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_19 + Interrupt Vector Register 19 + Interrupt Vector Register 19 + 0xCC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 19 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_20 + Interrupt Vector Register 20 + Interrupt Vector Register 20 + 0xD0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 20 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_21 + Interrupt Vector Register 21 + Interrupt Vector Register 21 + 0xD4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 21 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_22 + Interrupt Vector Register 22 + Interrupt Vector Register 22 + 0xD8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 22 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_23 + Interrupt Vector Register 23 + Interrupt Vector Register 23 + 0xDC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 23 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_24 + Interrupt Vector Register 24 + Interrupt Vector Register 24 + 0xE0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 24 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_25 + Interrupt Vector Register 25 + Interrupt Vector Register 25 + 0xE4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 25 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_26 + Interrupt Vector Register 26 + Interrupt Vector Register 26 + 0xE8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 26 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_27 + Interrupt Vector Register 27 + Interrupt Vector Register 27 + 0xEC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 27 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_28 + Interrupt Vector Register 28 + Interrupt Vector Register 28 + 0xF0 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 28 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_29 + Interrupt Vector Register 29 + Interrupt Vector Register 29 + 0xF4 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 29 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_30 + Interrupt Vector Register 30 + Interrupt Vector Register 30 + 0xF8 + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 30 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_VECTOR_31 + Interrupt Vector Register 31 + Interrupt Vector Register 31 + 0xFC + 17 + true + write-only + + 0x0000000010 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 31 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_0 + Interrupt Vector Address Register 0 + Interrupt Vector Address Register 0 + 0x100 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 0 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_1 + Interrupt Vector Address Register 1 + Interrupt Vector Address Register 1 + 0x108 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 1 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_2 + Interrupt Vector Address Register 2 + Interrupt Vector Address Register 2 + 0x110 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 2 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_3 + Interrupt Vector Address Register 3 + Interrupt Vector Address Register 3 + 0x118 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 3 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_4 + Interrupt Vector Address Register 4 + Interrupt Vector Address Register 4 + 0x120 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 4 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_5 + Interrupt Vector Address Register 5 + Interrupt Vector Address Register 5 + 0x128 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 5 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_6 + Interrupt Vector Address Register 6 + Interrupt Vector Address Register 6 + 0x130 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 6 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_7 + Interrupt Vector Address Register 7 + Interrupt Vector Address Register 7 + 0x138 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 7 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_8 + Interrupt Vector Address Register 8 + Interrupt Vector Address Register 8 + 0x140 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 8 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_9 + Interrupt Vector Address Register 9 + Interrupt Vector Address Register 9 + 0x148 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 9 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_10 + Interrupt Vector Address Register 10 + Interrupt Vector Address Register 10 + 0x150 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 10 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_11 + Interrupt Vector Address Register 11 + Interrupt Vector Address Register 11 + 0x158 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 11 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_12 + Interrupt Vector Address Register 12 + Interrupt Vector Address Register 12 + 0x160 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 12 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_13 + Interrupt Vector Address Register 13 + Interrupt Vector Address Register 13 + 0x168 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 13 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_14 + Interrupt Vector Address Register 14 + Interrupt Vector Address Register 14 + 0x170 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 14 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_16 + Interrupt Vector Address Register 16 + Interrupt Vector Address Register 16 + 0x180 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 16 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_17 + Interrupt Vector Address Register 17 + Interrupt Vector Address Register 17 + 0x188 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 17 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_18 + Interrupt Vector Address Register 18 + Interrupt Vector Address Register 18 + 0x190 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 18 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_19 + Interrupt Vector Address Register 19 + Interrupt Vector Address Register 19 + 0x198 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 19 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_20 + Interrupt Vector Address Register 20 + Interrupt Vector Address Register 20 + 0x1A0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 20 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_21 + Interrupt Vector Address Register 21 + Interrupt Vector Address Register 21 + 0x1A8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 21 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_22 + Interrupt Vector Address Register 22 + Interrupt Vector Address Register 22 + 0x1B0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 22 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_23 + Interrupt Vector Address Register 23 + Interrupt Vector Address Register 23 + 0x1B8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 23 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_24 + Interrupt Vector Address Register 24 + Interrupt Vector Address Register 24 + 0x1C0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 24 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_25 + Interrupt Vector Address Register 25 + Interrupt Vector Address Register 25 + 0x1C8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 25 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_26 + Interrupt Vector Address Register 26 + Interrupt Vector Address Register 26 + 0x1D0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 26 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_27 + Interrupt Vector Address Register 27 + Interrupt Vector Address Register 27 + 0x1D8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 27 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_28 + Interrupt Vector Address Register 28 + Interrupt Vector Address Register 28 + 0x1E0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 28 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_29 + Interrupt Vector Address Register 29 + Interrupt Vector Address Register 29 + 0x1E8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 29 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_30 + Interrupt Vector Address Register 30 + Interrupt Vector Address Register 30 + 0x1F0 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 30 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ_EA_VECTOR_31 + Interrupt Vector Address Register 31 + Interrupt Vector Address Register 31 + 0x1F8 + 17 + true + write-only + + 0x0000000000000000 + + + IRQ_Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 31 with highest priority. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + + IO + 0 + 65536 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_IO_BASEADDR + + + OFFSET_HIGH_PARAM + C_IO_HIGHADDR + + + + + + true + + + + + + + + + + Clk + + in + + + std_logic + dummy_view + + + + + + Rst + + in + + + std_logic + dummy_view + + + + + + Config_Reset + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + TMR_Rst + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + TMR_Disable + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + ToVote + + out + + 1023 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + FromAVote + + in + + 1023 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + FromBVote + + in + + 1023 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + IO_Addr_Strobe + + out + + + std_logic + dummy_view + + + + + + + true + + + + + + IO_Read_Strobe + + out + + + std_logic + dummy_view + + + + + + + true + + + + + + IO_Write_Strobe + + out + + + std_logic + dummy_view + + + + + + + true + + + + + + IO_Address + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + true + + + + + + IO_Byte_Enable + + out + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + + + + true + + + + + + IO_Write_Data + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + true + + + + + + IO_Read_Data + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + 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is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous. + 0xFFFF + + + C_INTC_NUM_SYNC_FF + Number of synchronization flip-flops + Number of synchronization flip-flops used to synchronize asynchronous interupt inputs + 2 + + + Component_Name + bd_afa8_iomodule_0_0 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + GPIO1_BOARD_INTERFACE + Custom + + + GPIO2_BOARD_INTERFACE + Custom + + + GPIO3_BOARD_INTERFACE + Custom + + + GPIO4_BOARD_INTERFACE + Custom + + + UART_BOARD_INTERFACE + Custom + + + + + IOModule + 6 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/bd_afa8_ilmb_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/bd_afa8_ilmb_0.xci new file mode 100644 index 0000000..7d91c47 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/bd_afa8_ilmb_0.xci @@ -0,0 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+ + + true + + + + + + Component_Name + bd_afa8_dlmb_0 + + + + + Local Memory Bus (LMB) 1.0 + 11 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xci new file mode 100644 index 0000000..8c879e1 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xci @@ -0,0 +1,189 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_afa8_dlmb_cntlr_0 + + + NONE + 65536 + 32 + 1 + + bd_afa8_Clk + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000000000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000000000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_afa8_dlmb_cntlr_0 + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 19 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xml new file mode 100644 index 0000000..08c2b4d --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xml @@ -0,0 +1,4011 @@ + + + xilinx.com + customized_ip + bd_afa8_dlmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + PROTOCOL + STANDARD + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + PROTOCOL + STANDARD + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + 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BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + READ_LATENCY + 1 + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + bd_afa8_Clk + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC_Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE_Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + 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BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + READ_LATENCY + 1 + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + bd_afa8_Clk + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC_Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE_Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + LMB_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + Sl_Ready + + out + + + std_logic + dummy_view + + + + + + Sl_Wait + + out + + + std_logic + dummy_view + + + + + + Sl_UE + + out + + + std_logic + dummy_view + + + + + + Sl_CE + + out + + + std_logic + dummy_view + + + + + + LMB1_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteStrobe 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LMB2_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + Sl2_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + Sl2_Ready + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_Wait + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + LMB3_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + Sl3_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + Sl3_Ready + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl3_Wait + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl3_UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl3_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + BRAM_Rst_A + + out + + + std_logic + dummy_view + + + + + + BRAM_Clk_A + + out + + + std_logic + dummy_view + + + + + + BRAM_Addr_A + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + BRAM_EN_A + + out + + + std_logic + dummy_view + + + + + + BRAM_WEN_A + + out + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + + + BRAM_Dout_A + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + BRAM_Din_A + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + S_AXI_CTRL_ACLK + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARESETN + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_WDATA + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RDATA + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + + + C_FAMILY + virtexuplus + + + C_HIGHADDR + LMB BRAM High Address + 0x000000000000FFFF + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000000000 + + + C_NUM_LMB + Number of LMB Ports + 1 + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_BRAM_AWIDTH + BRAM Address Bus Width + 32 + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + false + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + false + + + + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_0873e75e + 0 + 1 + + + choice_pairs_449ac0d2 + 0 + 1 + 2 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_8d6e70ff + 0 + 2 + + + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000000000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x000000000000FFFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_afa8_ilmb_cntlr_0 + + + + + LMB BRAM Controller + 19 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xci new file mode 100644 index 0000000..de3259a --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xci @@ -0,0 +1,298 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_afa8_lmb_bram_I_0 + + + 4096 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + BRAM_CTRL + NONE + 65536 + 32 + 1 + READ_WRITE + BRAM_CTRL + NONE + 65536 + 32 + 1 + READ_WRITE + + 100000000 + 0 + 0 + 0.000 + 0 + 32 + 32 + 1 + 4 + 0 + 1 + 8 + 0 + 0 + 16 + NONE + 0 + 0 + 0 + ./ + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + Estimated Power for IP : 19.660986 mW + virtexuplus + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + bd_afa8_lmb_bram_I_0.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 16384 + 16384 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 4 + 4 + 16384 + 16384 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 8 + NONE + no_coe_file_loaded + ALL + bd_afa8_lmb_bram_I_0 + false + false + false + false + false + true + false + false + true + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + false + Native + false + bd_afa8_lmb_bram_I_0.mem + True_Dual_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + true + false + false + false + true + true + 16384 + 32 + 32 + No_ECC + false + false + false + BRAM_Controller + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 4 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xml new file mode 100644 index 0000000..be458ff --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xml @@ -0,0 +1,4151 @@ + + + xilinx.com + customized_ip + bd_afa8_lmb_bram_I_0 + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + 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Estimated Power for IP : 19.660986 mW + + + + + + choice_list_0132492a + 32 + 64 + 128 + + + choice_list_302d3091 + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_6fc15197 + 32 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f9a6a28b + Native + + + choice_pairs_1f270a52 + BRAM_Controller + Stand_Alone + + + choice_pairs_246d8066 + WRITE_FIRST + READ_FIRST + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_afa8_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false 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CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 32768 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + READ_LATENCY + 1 + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA 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CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC_Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE_Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + 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bd_afa8_second_dlmb_cntlr_0 + + + + + LMB BRAM Controller + 19 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xci new file mode 100644 index 0000000..4ba85ff --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xci @@ -0,0 +1,189 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_afa8_second_ilmb_cntlr_0 + + + NONE + 32768 + 32 + 1 + + bd_afa8_Clk + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 32 + STANDARD + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + 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CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 32768 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + READ_LATENCY + 1 + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + bd_afa8_Clk + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC_Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE_Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE_Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC_EN_IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE_EN_IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE_EN_IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC_ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON_OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE_CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE_FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE_FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE_FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE_FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE_FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE_FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE_FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE_FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE_FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI_D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI_D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI_ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI_ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + LMB_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + Sl_Ready + + out + + + std_logic + dummy_view + + + + + + Sl_Wait + + out + + + std_logic + dummy_view + + + + + + Sl_UE + + out + + + std_logic + dummy_view + + + + + + Sl_CE + + out + + + std_logic + dummy_view + + + + + + LMB1_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + 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+ + + std_logic_vector + dummy_view + + + + + + BRAM_Din_A + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + S_AXI_CTRL_ACLK + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARESETN + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_WDATA + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RDATA + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + + + C_FAMILY + virtexuplus + + + C_HIGHADDR + LMB BRAM High Address + 0x0000000000017FFF + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000010000 + + + C_NUM_LMB + Number of LMB Ports + 1 + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_BRAM_AWIDTH + BRAM Address Bus Width + 32 + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + false + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + false + + + + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_0873e75e + 0 + 1 + + + choice_pairs_449ac0d2 + 0 + 1 + 2 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_8d6e70ff + 0 + 2 + + + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000010000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x0000000000017FFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_LMB_PROTOCOL + LMB Protocol + 0 + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_afa8_second_ilmb_cntlr_0 + + + + + LMB BRAM Controller + 19 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xci new file mode 100644 index 0000000..e441f33 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xci @@ -0,0 +1,298 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_afa8_second_lmb_bram_I_0 + + + 4096 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + BRAM_CTRL + NONE + 32768 + 32 + 1 + READ_WRITE + BRAM_CTRL + NONE + 32768 + 32 + 1 + READ_WRITE + + 100000000 + 0 + 0 + 0.000 + 0 + 32 + 32 + 1 + 4 + 0 + 1 + 8 + 0 + 0 + 8 + NONE + 0 + 0 + 0 + ./ + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + Estimated Power for IP : 17.246228 mW + virtexuplus + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + bd_afa8_second_lmb_bram_I_0.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 8192 + 8192 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 4 + 4 + 8192 + 8192 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 8 + NONE + no_coe_file_loaded + ALL + bd_afa8_second_lmb_bram_I_0 + false + false + false + false + false + true + false + false + true + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + false + Native + false + bd_afa8_second_lmb_bram_I_0.mem + True_Dual_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + true + false + false + false + true + true + 8192 + 32 + 32 + No_ECC + false + false + false + BRAM_Controller + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Integrator + 4 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xml new file mode 100644 index 0000000..2960628 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xml @@ -0,0 +1,4151 @@ + + + xilinx.com + customized_ip + bd_afa8_second_lmb_bram_I_0 + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + 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GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_afa8_second_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A 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choice_list_0739ee39 + Custom + rs232_uart + + + choice_list_30de7c39 + Custom + pcie_perstn + resetn + + + choice_list_38e5a9f1 + Custom + dip_switches_4bits + led_3bits + qsfp0_lowspeed + qsfp1_lowspeed + + + choice_list_ac75ef1e + Custom + + + choice_list_f585525a + 110 + 300 + 1200 + 2400 + 4800 + 9600 + 19200 + 38400 + 57600 + 115200 + 128000 + 230400 + 460800 + 921600 + + + choice_pairs_007f01e9 + 0 + 1 + 2 + 3 + 4 + 5 + 7 + 8 + 9 + + + choice_pairs_0d2d32a8 + 0 + 1 + 2 + + + choice_pairs_366c5f3d + 0 + 1 + 2 + + + choice_pairs_4847022f + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 8 + 9 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_5502e96b + 1 + 2 + 3 + 4 + + + choice_pairs_563648c8 + 0 + 1 + + + choice_pairs_5f1e379e + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 9 + + + choice_pairs_7ba91213 + 0 + 1 + 2 + 3 + + + choice_pairs_9de6ed99 + 0 + + + choice_pairs_f0f6eb36 + 0 + 1 + 2 + 3 + 4 + 6 + 7 + 8 + 9 + + + choice_pairs_f7e0b771 + 4096 + 8192 + 12288 + 16384 + 20480 + 24576 + 32768 + 36864 + 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It is primarily intended for simple control applications, where a hardware solution would be less flexible and more difficult to implement. Software development with the Xilinx Software Development Kit (SDK) is supported, including a software driver for the peripherals. Debugging including UART is available either via SDK or directly with the Xilinx Microprocessor Debugger. +The MCS consists of the processor itself, local memory with sizes ranging from 4KB to 128KB, up to 4 Fixed Interval Timers, up to 4 Programmable Interval Timers, up to 4 32-bit General Purpose Output ports, up to 4 32-bit General Purpose Input ports, and an Interrupt Controller with up to 16 external interrupt inputs. + + + + JTAG_CHAIN + Debug JTAG User-defined Register + 2 + + + + false + + + + + + MICROBLAZE_INSTANCE + MicroBlaze Instance Name + microblaze_0 + + + AVOID_PRIMITIVES + 0 + + + PATH + Instance Hierarchical Design Name + mcs_0 + + + FREQ + Input Clock Frequency (MHz) + 100.0 + + + OPTIMIZATION + Select MicroBlaze Optimization + 1 + + + DEBUG_ENABLED + Enable Debug Support + 0 + + + USE_BSCAN + Select BSCAN location + 0 + + + + false + + + + + + BSCANID + Define BSCAN id + 76547328 + + + + false + + + + + + TRACE + Enable MicroBlaze Trace Bus + 1 + + + ECC + Error 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tXPR + tXPR + 60 + + + nCK_PER_CLK + nCK PER CLK + 4 + + + tMRD + tMRD + 2 + + + tZQINIT + tZQINIT + 256 + + + MEM_COMP_WIDTH + MEM COMP WIDTH + 8 + + + MEM_DEVICE_WIDTH + MEMORY DEVICE WIDTH + 72 + + + PLL_WIDTH + PLL WIDTH + 3 + + + IOBTYPE + IOBTYPE + 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b +000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, + 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_000_000_000_000_000_000_001_000_001_001_001_001, 39'b001_001_001_000_000_001_001_001_00 +1_001_001_001_001, 39'b000_001_001_001_001_101_101_001_001_001_001_001_001 + + + BYTES + BYTES + 12 + + + DBYTES + DBYTES + 9 + + + PING_PONG_CH1_BYTES_MAP + PING_PONG_CH1_BYTES_MAP + 12'b000000000000 + + + PING_PONG_PHY + PING PONG PHY + 1 + + + RX_DATA_TYPE + RX DATA TYPE + { 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, + 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b000000_00_10111_11, + 15'b111001_11_11111_11, 15'b011111_11_11111_11 } + + + INIT + INIT + { 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, + 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111101, + 15'b111111111111111, 15'b111111111111111 } + + + SELF_CALIBRATE + SELF CALIBRATE + {12{2'b11}} + + + TX_OUTPUT_PHASE_90 + TX OUTPUT PHASE 90 + { 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000 +011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000000101111, 13'b1110011111111, + 13'b0111111111111 } + + + RXTX_BITSLICE_EN + RXTX BITSLICE EN + {13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b01111 +01111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0000000101111, 13'b1110011111111, + 13'b0111101111111 } + + + EN_OTHER_PN_CLOCK_PARAM + EN OTHER PN CLOCK PARAM + {{9{2'b01}}, {3{2'b00}}} + + + PHY_BYTE_ALLOC_PARAM + PHY BYTE ALLOC PARAM + {{9{2'b11}}, {3{2'b00}}} + + + DATA_BUF_ADDR_WIDTH + DATA BUF ADDR WIDTH + 5 + + + CLKIN_PERIOD + CLKIN PERIOD + 3333 + + + MEM_TYPE + MEM TYPE + 0 + + + AXI_ID_WIDTH + AXI ID WIDTH + 0 + + + AXI_DATA_WIDTH + AXI DATA WIDTH + 0 + + + AXI_ADDR_WIDTH + AXI ADDR WIDTH + 0 + + + USE_DM_PORT + USE DM PORT + 1 + + + BUFG_LOC_1 + BUFG LOC 1 + X0Y70 + + + BUFG_LOC_2 + BUFG LOC 2 + X0Y11 + + + BUFG_DIV_LOC_1 + BUFG DIV LOC 1 + X0Y11 + + + BUFG_DIV_LOC_2 + BUFG DIV LOC 2 + X0Y10 + + + PBLOCK_SLICE_LOC + PBLOCK SLICE LOC + 0 + + + PBLOCK_RAMB36_LOC + PBLOCK RAMB36 LOC + 0 + + + PBLOCK_RAMB18_LOC + PBLOCK RAMB18 LOC + 0 + + + PBLOCK_SLICE_LOC_SC + PBLOCK SLICE LOC SC + 0 + + + PBLOCK_RAMB36_LOC_SC + PBLOCK RAMB36 LOC SC + 0 + + + PBLOCK_RAMB18_LOC_SC + PBLOCK RAMB18 LOC SC + 0 + + + MMCM_IDX_BANK + MMCM IDX BANK + 1 + + + CENTER_BANK_CLOCK_REGION + CENTER BANK CLOCK REGION + 0 + + + CENTER_BANK_MMCME3_ADV_SITE + CENTER BANK MMCME3 ADV SITE + 0 + + + SYSCLK_CENTER_INFO + SYSCLK_CENTER_INFO + FALSE + + + tWR + tWR + 10 + + + tRTP + tRTP + 5 + + + RANK_WIDTH + RANK WIDTH + 1 + + + CK_WIDTH + CK WIDTH + 1 + + + DATABITS_PER_STROBE + DATABITS PER STROBE + 8 + + + USE_CS_PORT + USE CS PORT + 1 + + + CA_MIRROR + CA MIRROR + 0 + + + IS_CUSTOM + IS CUSTOM + false + + + Slot + Slot + 1 + + + + + + phy_rdimm_x8_dual_phy + + + + PHY for DDR4 interfaces for Ultrascale Architecture + + + C0.ControllerType + DDR4_SDRAM + + + IS_FROM_PHY + 1 + + + Phy_Only + Phy_Only_Single + + + No_Controller + 1 + + + Default_Bank_Selections + Default Bank Selections + false + + + Debug_Signal + Disable + + + Simulation_Mode + BFM + + + PARTIAL_RECONFIG_FLOW_MIG + false + + + CLKOUT1_DIVIDE + 0 + + + CLKOUT2_DIVIDE + 0 + + + CLKOUT3_DIVIDE + 0 + + + CLKOUT4_DIVIDE + 0 + + + System_Clock + Differential + + + RECONFIG_XSDB_SAVE_RESTORE + false + + + DIFF_TERM_SYSCLK + false + + + C0.DDR4_TimePeriod + 1500 + + + C0.DDR4_InputClockPeriod + 3333 + + + C0.DDR4_CLKFBOUT_MULT + 5 + + + C0.DDR4_DIVCLK_DIVIDE + 1 + + + C0.DDR4_CLKOUT0_DIVIDE + 9 + + + C0.DDR4_PhyClockRatio + 4:1 + + + C0.DDR4_MemoryType + RDIMMs + + + C0.DDR4_MemoryPart + MTA9ASF1G72PZ-2G3 + + + C0.DDR4_Slot + Single + + + C0.DDR4_MemoryVoltage + 1.2V + + + C0.DDR4_DataWidth + 72 + + + C0.DDR4_DataMask + DM_NO_DBI + + + C0.DDR4_Ecc + false + + + C0.DDR4_CasLatency + 10 + + + C0.DDR4_CasWriteLatency + 9 + + + C0.DDR4_ChipSelect + true + + + C0.DDR4_isCKEShared + false + + + C0.DDR4_CLKOUTPHY_MODE + CLKOUTPHY MODE + VCO + + + C0.DDR4_HR_MIN_FREQ + High Range Supported frequency + 0 + + + C0.DDR4_MIN_PERIOD + Memory Min Period + 833 + + + C0.DDR4_IS_FASTER_SPEED_RAM + Indicates Faster Speed RAM Support + No + + + C0.DDR4_VrefVoltage + Vref Voltage + 0.84 + + + C0.DDR4_customPartAbsPath + no_file_loaded + + + C0.DDR4_StackHeight + 1 + + + CUSTOM_PART_ATTRIBUTES + NONE + + + C0.DDR4_SELF_REFRESH + false + + + C0.DDR4_SAVE_RESTORE + false + + + C0.DDR4_Clamshell + false + + + C0.DDR4_Enable_LVAUX + false + + + C0.DDR4_EN_PARITY + true + + + + false + + + + + + c0_dq_0 + NONE + + + c0_dq_1 + NONE + + + c0_dq_2 + NONE + + + c0_dq_3 + NONE + + + c0_dq_4 + NONE + + + c0_dq_5 + NONE + + + c0_dq_6 + NONE + + + c0_dq_7 + NONE + + + c0_dq_8 + NONE + + + c0_dq_9 + NONE + + + c0_dq_10 + NONE + + + c0_dq_11 + NONE + + + c0_dq_12 + NONE + + + c0_dq_13 + NONE + + + c0_dq_14 + NONE + + + c0_dq_15 + NONE + + + c0_dq_16 + NONE + + + c0_dq_17 + NONE + + + c0_dq_18 + NONE + + + c0_dq_19 + NONE + + + c0_dq_20 + NONE + + + c0_dq_21 + NONE + + + c0_dq_22 + NONE + + + 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+ + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig new file mode 100644 index 0000000..698f7e5 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig @@ -0,0 +1,313 @@ +/****************************************************************************** +// (c) Copyright 2013 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +******************************************************************************/ +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 1.1 +// \ \ Application : MIG +// / / Filename : ddr4_v2_2_10_cal_rd_en.sv +// /___/ /\ Date Last Modified : $Date: 2015/04/23 $ +// \ \ / \ Date Created : Thu Apr 18 2013 +// \___\/\___\ +// +// Device : UltraScale +// Design Name : DDR4 SDRAM & DDR3 SDRAM +// Purpose : +// ddr4_v2_2_10_cal_rd_en module +// Reference : +// Revision History : +//***************************************************************************** + +`timescale 1ns/100ps + +module ddr4_v2_2_10_cal_rd_en #(parameter + RANKS = 1 + ,RL = 11 + ,EXTRA_CMD_DELAY = 0 + ,TCQ = 0.1 +)( + input clk + ,input rst + + ,output [3:0] mc_clb2phy_rden + ,output [3:0] mc_clb2phy_rdcs0 + ,output [3:0] mc_clb2phy_rdcs1 + + ,input [1:0] casSlot // spyglass disable W498 + ,input mccasSlot2 + ,input rdCAS + ,input calrdCAS + ,input mcrdCAS + ,input [5:0] mCL0 + ,input [5:0] mCL1 + ,input [5:0] mCL2 + ,input [5:0] mCL3 + ,input [1:0] winRank + ,input [1:0] calRank + ,input [1:0] mcwinRank + ,input calDone +); + +wire [5:0] mCL[0:3]; +assign mCL[0] = mCL0; +assign mCL[1] = mCL1; +assign mCL[2] = mCL2; +assign mCL[3] = mCL3; + +// This section generates the Gate enable mc_clb2phy_rden. +// This logic is used in calibration and during normal operation. +// Case 4'b0110 defines nominal timing where the trained mCL value equals RL. +// This logic supports mCL = RL - 3, to enable the Gate 3tCK earlier than nominal RL. +// Early gate enable is needed in Gate training, during normal operation +// if command delays are very low, and to compensate for extra Gate delay +// in the XiPhy that is allocated for VT tracking. The logic also supports Gate +// enable 4tCK later than nominal to allow for command fly-by routing. +// The Gate enable can be further delayed to allow for extra command pipeline delays. +// The Gate enable supports RL as low as 7 with no extra command delays, but other +// blocks have higher low limits, so the minimum RL without extra command delays +// is expected to be RL=8. + +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn; +(* KEEP = "true" *) reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt; +reg [18:0] rsMask[0:7]; + +function [18:0] rs2mask; + input [3:0] diff; + input slot2; +case ({diff, slot2}) + 5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111; + 5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100; + 5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110; + 5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000; + 5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100; + 5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000; + 5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000; + 5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000; + 5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000; + 5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000; + 5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000; + 5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000; + 5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000; + 5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000; + 5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000; + 5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000; + 5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000; + 5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000; + 5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000; + 5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000; + 5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000; + 5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000; + 5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000; + 5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000; + 5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000; + 5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000; + 5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000; + 5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000; + default: rs2mask = 19'b000_0000_1000_0000_1111; +endcase +endfunction + +always @(posedge clk) begin: blk1 + reg [3:0] rsNdx; + for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1) + rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]); +end + +always @(*) if (rst) begin + rdEn_nxt = 'b0; +end else begin + rdEn_nxt = (rdEn >> 4) + | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} + : 'b0); +end + +always @(posedge clk) + rdEn <= #TCQ rdEn_nxt; + +assign mc_clb2phy_rden = rdEn[3:0]; + +/////////////////////////////////////////////////////////////////// +// This logic is used during normal, multi-rank operation only. Durring cal or single +// rank operation this logic is bypassed and the output of this section is static. +// This section generates the read rank signals used by the XiPhy to select per rank +// cal values during read operations. + +integer tck_index; +localparam rdcs_msb = RL + 8 + 4*EXTRA_CMD_DELAY; + +reg [rdcs_msb :0] rdcs0; +reg [rdcs_msb :0] rdcs0_mc; +reg [rdcs_msb :0] rdcs1; +reg [rdcs_msb :0] rdcs1_mc; +reg [6:0] rdcs_rdcas_lsb_slot0; +reg calDone_dly; + +// Extend newest cs (MSB) and shift out the oldest (low 4 LSBs) +wire [rdcs_msb :0] rdcs0_shift = { { 4 { rdcs0[rdcs_msb] } }, rdcs0[ rdcs_msb : 4] }; +wire [rdcs_msb :0] rdcs1_shift = { { 4 { rdcs1[rdcs_msb] } }, rdcs1[ rdcs_msb : 4] }; + +// Create rdcs mask for the current rdcas +wire [6:0] rdcs_rdcas_lsb_slot0_nxt = { 1'b0, mCL0 } + 4*EXTRA_CMD_DELAY - 7'd7; +wire [rdcs_msb :0] rdcs_rdcas_mask_slot0 = { ( rdcs_msb + 1 ) { 1'b1 } } << rdcs_rdcas_lsb_slot0; +wire [rdcs_msb :0] rdcs_rdcas_mask = rdcs_rdcas_mask_slot0 << 2*mccasSlot2; + +// Merge the shifted rdcs and winRank based on the rdcs mask for the current rdcas +always @(*) begin + for (tck_index = 0; tck_index <= rdcs_msb; tck_index = tck_index + 1) begin + rdcs0_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[0] : rdcs0_shift[tck_index]; + rdcs1_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[1] : rdcs1_shift[tck_index]; + end +end + +// Select mc or cal rdcs +wire [rdcs_msb :0] rdcs0_nxt = calDone_dly ? rdcs0_mc : { rdcs_msb+1 { calRank[0] } }; +wire [rdcs_msb :0] rdcs1_nxt = calDone_dly ? rdcs1_mc : { rdcs_msb+1 { calRank[1] } }; + +// Final 4 bit rdcs output +assign mc_clb2phy_rdcs0 = rdcs0[3:0] & ~{ 4 { RANKS == 1 } }; +assign mc_clb2phy_rdcs1 = rdcs1[3:0] & ~{ 4 { RANKS == 1 } }; + +// Flops +always @(posedge clk) begin + rdcs_rdcas_lsb_slot0 <= #TCQ rdcs_rdcas_lsb_slot0_nxt; + calDone_dly <= #TCQ calDone; +end + +// Reset flops +always @(posedge clk) if (rst) begin + rdcs0 <= #TCQ '0; + rdcs1 <= #TCQ '0; +end else begin + rdcs0 <= #TCQ rdcs0_nxt; + rdcs1 <= #TCQ rdcs1_nxt; +end + + +//synopsys translate_off + +`ifdef MEM_INTERNAL +// Events - When asserted high in a test that passes all verification checks, these coverage +// properties indicate that a functional coverage event has been hit. +// --------------------------------------------------------------------------------------------- + +// Minimum mCL in normal operation +//wire e_mc_rd_en_000 = ( ( mCL0 + 4*EXTRA_CMD_DELAY ) == 13 ) & calDone & ~( RANKS == 1 ) & rdCAS; +//always @(posedge clk) mc_rd_en_000: if (~rst) cover property (e_mc_rd_en_000); + + +// Asserts - When asserted high, an illegal condition has been detected and the test has failed. +// --------------------------------------------------------------------------------------------- + +// Check for illegal rank switch in rdEn and rdcs. rdEn gap must be at least 2tCK wide. rdcs must be stable for 2tCK after rdEn de-assertion. +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdEn; +reg [rdcs_msb :0] a_rdcs0_dly; +reg [rdcs_msb :0] a_rdcs1_dly; +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0; +wire [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0_nxt = { rdcs0, a_rdcs0_dly[3:0] }; +reg [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1; +wire [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1_nxt = { rdcs1, a_rdcs1_dly[3:0] }; +wire [RL+12 + 4*EXTRA_CMD_DELAY -1 :0] a_rdEn_falling_edge = ~a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY :1] & a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY -1 :0]; +reg [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold0_fail; +reg [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold1_fail; +reg [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_gap_fail; +always @(*) begin + for (tck_index = 0; tck_index < RL+12 + 4*EXTRA_CMD_DELAY -2; tck_index = tck_index + 1) begin + a_rdEn_hold0_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+1] ) | ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+2] ) ); + a_rdEn_hold1_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+1] ) | ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+2] ) ); + a_rdEn_gap_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & a_rdEn[tck_index+2]; + end +end +always @(posedge clk) if (rst) begin + a_rdEn <= #TCQ '0; + a_rdcs0_dly <= #TCQ '0; + a_rdcs1_dly <= #TCQ '0; + a_rdcs0 <= #TCQ '0; + a_rdcs1 <= #TCQ '0; +end else begin + a_rdEn <= #TCQ rdEn; + a_rdcs0_dly <= #TCQ rdcs0; + a_rdcs1_dly <= #TCQ rdcs1; + a_rdcs0 <= #TCQ a_rdcs0_nxt; + a_rdcs1 <= #TCQ a_rdcs1_nxt; +end + +// rdcs0 not held for 2tCK after end of burst +wire a_mc_rd_en_000_hld = calDone & ( | a_rdEn_hold0_fail ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_000_hld); + +// rdcs1 not held for 2tCK after end of burst +wire a_mc_rd_en_001_hld = calDone & ( | a_rdEn_hold1_fail ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_001_hld); + +// rdEn not held low for 2tCK after end of burst +wire a_mc_rd_en_002_hld = calDone & ( | a_rdEn_gap_fail ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_002_hld); + +// mCL0 is less than RL-3 +wire a_mc_rd_en_003_ovf = ( mCL0 < (RL - 3) ) & ( mCL0 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_003_ovf); + +// mCL1 is less than RL-3 +wire a_mc_rd_en_004_ovf = ( mCL1 < (RL - 3) ) & ( mCL1 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_004_ovf); + +// mCL2 is less than RL-3 +wire a_mc_rd_en_005_ovf = ( mCL2 < (RL - 3) ) & ( mCL2 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_005_ovf); + +// mCL3 is less than RL-3 +wire a_mc_rd_en_006_ovf = ( mCL3 < (RL - 3) ) & ( mCL3 > 6'b0 ); +always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_006_ovf); + + +`endif +//synopsys translate_on + +endmodule + + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej new file mode 100644 index 0000000..dd5a9cf --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej @@ -0,0 +1,124 @@ +--- U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv ++++ /dev/null +@@ -114,55 +114,86 @@ + + reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn; + (* KEEP = "true" *) reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt; +-reg [18:0] rsMask[0:7]; ++reg [19:0] rsMask[0:15]; + +-function [18:0] rs2mask; ++// RS probably stands for rank select. ++// TODO edit below in worst case. ++function [19:0] rs2mask; + input [3:0] diff; + input slot2; +-case ({diff, slot2}) +- 5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111; +- 5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110; +- 5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000; +- 5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000; ++ input slot1; ++case ({diff, slot2, slot1}) ++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111; ++ 6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000; + default: rs2mask = 19'b000_0000_1000_0000_1111; + endcase + endfunction + + always @(posedge clk) begin: blk1 +- reg [3:0] rsNdx; +- for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1) +- rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]); ++ reg [4:0] rsNdx; ++ for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1) ++ rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]); + end + + always @(*) if (rst) begin + rdEn_nxt = 'b0; + end else begin + rdEn_nxt = (rdEn >> 4) +- | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} ++ | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} + : 'b0); + end + diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv.rej new file mode 100644 index 0000000..1d2fee7 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv.rej @@ -0,0 +1,31 @@ +--- U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv ++++ /dev/null +@@ -157,9 +157,13 @@ + // used in pushing new write CAS commands into the wrQ shift register. These values are + // calculated for both casslot0 and casslot2. + localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2; ++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2; + localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2; ++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2; + localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4; ++localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4; + localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4; ++localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4; + + integer i; + +@@ -192,10 +196,12 @@ + // Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical. + reg [3:0] oe_0_mux_cal; + wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2; +-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal; ++wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) : ++ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal); + + // tCK offset for mc. mccasSlot2 is timing critical. +-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0; ++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) : ++ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0); + + // Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical. + wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1}; diff --git a/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci b/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci new file mode 100644 index 0000000..73efc2c --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci @@ -0,0 +1,329 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pr_read_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 4 + 4 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 5.931282 mW + virtexuplus + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + pr_read_mem.mem + pr_read_mem.mif + 0 + 1 + 0 + 0 + 1 + 16 + 16 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 16 + 16 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../coe/pr_read.coe + ALL + pr_read_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + true + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 16 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xml b/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xml new file mode 100644 index 0000000..b374295 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xml @@ -0,0 +1,4182 @@ + + + xilinx.com + customized_ip + pr_read_mem + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + 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C_CTRL_ECC_ALGO + NONE + + + C_HAS_AXI_ID + 0 + + + C_AXI_ID_WIDTH + 4 + + + C_MEM_TYPE + 0 + + + C_BYTE_SIZE + 9 + + + C_ALGORITHM + 1 + + + C_PRIM_TYPE + 1 + + + C_LOAD_INIT_FILE + 1 + + + C_INIT_FILE_NAME + pr_read_mem.mif + + + C_INIT_FILE + pr_read_mem.mem + + + C_USE_DEFAULT_DATA + 1 + + + C_DEFAULT_DATA + 0 + + + C_HAS_RSTA + 0 + + + C_RST_PRIORITY_A + CE + + + C_RSTRAM_A + 0 + + + C_INITA_VAL + 0 + + + C_HAS_ENA + 1 + + + C_HAS_REGCEA + 0 + + + C_USE_BYTE_WEA + 0 + + + C_WEA_WIDTH + 1 + + + C_WRITE_MODE_A + WRITE_FIRST + + + C_WRITE_WIDTH_A + 64 + + + C_READ_WIDTH_A + 64 + + + C_WRITE_DEPTH_A + 16 + + + C_READ_DEPTH_A + 16 + + + C_ADDRA_WIDTH + 4 + + + C_HAS_RSTB + 0 + + + C_RST_PRIORITY_B + CE + + + C_RSTRAM_B + 0 + + + C_INITB_VAL + 0 + + + C_HAS_ENB + 0 + + + C_HAS_REGCEB + 0 + + + C_USE_BYTE_WEB + 0 + + + C_WEB_WIDTH + 1 + + + C_WRITE_MODE_B + WRITE_FIRST + + + C_WRITE_WIDTH_B + 64 + + + C_READ_WIDTH_B + 64 + + + C_WRITE_DEPTH_B + 16 + + + C_READ_DEPTH_B + 16 + + + C_ADDRB_WIDTH + 4 + + + C_HAS_MEM_OUTPUT_REGS_A + 0 + + + C_HAS_MEM_OUTPUT_REGS_B + 0 + + + C_HAS_MUX_OUTPUT_REGS_A + 0 + + + C_HAS_MUX_OUTPUT_REGS_B + 0 + + + C_MUX_PIPELINE_STAGES + 0 + + + C_HAS_SOFTECC_INPUT_REGS_A + 0 + + + C_HAS_SOFTECC_OUTPUT_REGS_B + 0 + + + C_USE_SOFTECC + 0 + + + C_USE_ECC + 0 + + + C_EN_ECC_PIPE + 0 + + + C_READ_LATENCY_A + 1 + + + C_READ_LATENCY_B + 1 + + + C_HAS_INJECTERR + 0 + + + C_SIM_COLLISION_CHECK + ALL + + + C_COMMON_CLK + 0 + + + C_DISABLE_WARN_BHV_COLL + 0 + + + C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 0 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 1 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 5.931282 mW + + + + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f5f941aa + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + pr_read_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci b/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci new file mode 100644 index 0000000..ec19729 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci @@ -0,0 +1,330 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pr_ref_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 6 + 6 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 5.931282 mW + virtexuplus + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + pr_ref_mem.mem + pr_ref_mem.mif + 0 + 1 + 0 + 0 + 1 + 64 + 64 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 64 + 64 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../coe/pr_ref.coe + ALL + pr_ref_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + true + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 64 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml b/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml new file mode 100644 index 0000000..45667dd --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml @@ -0,0 +1,4185 @@ + + + xilinx.com + customized_ip + pr_ref_mem + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn + + + + + 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8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + pr_ref_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + 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dummy_view + + + + 1 + + + + + + false + + + + + + + + C_COMMON_CLOCK + 1 + + + C_SELECT_XPM + 0 + + + C_COUNT_TYPE + 0 + + + C_DATA_COUNT_WIDTH + 10 + + + C_DEFAULT_VALUE + BlankString + + + C_DIN_WIDTH + 512 + + + C_DOUT_RST_VAL + 0 + + + C_DOUT_WIDTH + 256 + + + C_ENABLE_RLOCS + 0 + + + C_FAMILY + virtexuplus + + + C_FULL_FLAGS_RST_VAL + 0 + + + C_HAS_ALMOST_EMPTY + 0 + + + C_HAS_ALMOST_FULL + 0 + + + C_HAS_BACKUP + 0 + + + C_HAS_DATA_COUNT + 0 + + + C_HAS_INT_CLK + 0 + + + C_HAS_MEMINIT_FILE + 0 + + + C_HAS_OVERFLOW + 0 + + + C_HAS_RD_DATA_COUNT + 0 + + + C_HAS_RD_RST + 0 + + + C_HAS_RST + 0 + + + C_HAS_SRST + 1 + + + C_HAS_UNDERFLOW + 0 + + + C_HAS_VALID + 1 + + + C_HAS_WR_ACK + 0 + + + C_HAS_WR_DATA_COUNT + 0 + + + C_HAS_WR_RST + 0 + + + C_IMPLEMENTATION_TYPE + 6 + + + C_INIT_WR_PNTR_VAL + 0 + + + C_MEMORY_TYPE + 4 + + + C_MIF_FILE_NAME + BlankString + + + C_OPTIMIZATION_MODE + 0 + + + C_OVERFLOW_LOW + 0 + + + C_PRELOAD_LATENCY + 0 + + + C_PRELOAD_REGS + 1 + + + C_PRIM_FIFO_TYPE + 1kx36 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL + 4 + + + C_PROG_EMPTY_THRESH_NEGATE_VAL + 5 + + + C_PROG_EMPTY_TYPE + 1 + + + C_PROG_FULL_THRESH_ASSERT_VAL + 895 + + + C_PROG_FULL_THRESH_NEGATE_VAL + 894 + + + C_PROG_FULL_TYPE + 1 + + + C_RD_DATA_COUNT_WIDTH + 11 + + + C_RD_DEPTH + 2048 + + + C_RD_FREQ + 1 + + + C_RD_PNTR_WIDTH + 11 + + + C_UNDERFLOW_LOW + 0 + + + C_USE_DOUT_RST + 1 + + + C_USE_ECC + 0 + + + C_USE_EMBEDDED_REG + 1 + + + C_USE_PIPELINE_REG + 0 + + + C_POWER_SAVING_MODE + 0 + + + C_USE_FIFO16_FLAGS + 0 + + + C_USE_FWFT_DATA_COUNT + 0 + + + C_VALID_LOW + 0 + + + C_WR_ACK_LOW + 0 + + + C_WR_DATA_COUNT_WIDTH + 10 + + + C_WR_DEPTH + 1024 + + + C_WR_FREQ + 1 + + + C_WR_PNTR_WIDTH + 10 + + + C_WR_RESPONSE_LATENCY + 1 + + + C_MSGON_VAL + 1 + + + C_ENABLE_RST_SYNC + 1 + + + C_EN_SAFETY_CKT + 0 + + + C_ERROR_INJECTION_TYPE + 0 + + + C_SYNCHRONIZER_STAGE + 2 + + + C_INTERFACE_TYPE + 0 + + + C_AXI_TYPE + 1 + + + C_HAS_AXI_WR_CHANNEL + 1 + + + C_HAS_AXI_RD_CHANNEL + 1 + + + C_HAS_SLAVE_CE + 0 + + + C_HAS_MASTER_CE + 0 + + + C_ADD_NGC_CONSTRAINT + 0 + + + C_USE_COMMON_OVERFLOW + 0 + + + C_USE_COMMON_UNDERFLOW + 0 + + + C_USE_DEFAULT_SETTINGS + 0 + + + C_AXI_ID_WIDTH + 1 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 64 + + + C_AXI_LEN_WIDTH + 8 + + + C_AXI_LOCK_WIDTH + 1 + + + C_HAS_AXI_ID + 0 + + + C_HAS_AXI_AWUSER + 0 + + + C_HAS_AXI_WUSER + 0 + + + C_HAS_AXI_BUSER + 0 + + + C_HAS_AXI_ARUSER + 0 + + + C_HAS_AXI_RUSER + 0 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_HAS_AXIS_TDATA + 1 + + + C_HAS_AXIS_TID + 0 + + + C_HAS_AXIS_TDEST + 0 + + + C_HAS_AXIS_TUSER + 1 + + + C_HAS_AXIS_TREADY + 1 + + + C_HAS_AXIS_TLAST + 0 + + + C_HAS_AXIS_TSTRB + 0 + + + C_HAS_AXIS_TKEEP + 0 + + + C_AXIS_TDATA_WIDTH + 8 + + + C_AXIS_TID_WIDTH + 1 + + + C_AXIS_TDEST_WIDTH + 1 + + + C_AXIS_TUSER_WIDTH + 4 + + + C_AXIS_TSTRB_WIDTH + 1 + + + C_AXIS_TKEEP_WIDTH + 1 + + + C_WACH_TYPE + 0 + + + C_WDCH_TYPE + 0 + + + C_WRCH_TYPE + 0 + + + C_RACH_TYPE + 0 + + + C_RDCH_TYPE + 0 + + + C_AXIS_TYPE + 0 + + + C_IMPLEMENTATION_TYPE_WACH + 1 + + + C_IMPLEMENTATION_TYPE_WDCH + 1 + + + C_IMPLEMENTATION_TYPE_WRCH + 1 + + + C_IMPLEMENTATION_TYPE_RACH + 1 + + + C_IMPLEMENTATION_TYPE_RDCH + 1 + + + C_IMPLEMENTATION_TYPE_AXIS + 1 + + + C_APPLICATION_TYPE_WACH + 0 + + + C_APPLICATION_TYPE_WDCH + 0 + + + C_APPLICATION_TYPE_WRCH + 0 + + + C_APPLICATION_TYPE_RACH + 0 + + + C_APPLICATION_TYPE_RDCH + 0 + + + C_APPLICATION_TYPE_AXIS + 0 + + + C_PRIM_FIFO_TYPE_WACH + 512x36 + + + C_PRIM_FIFO_TYPE_WDCH + 512x72 + + + C_PRIM_FIFO_TYPE_WRCH + 512x36 + + + C_PRIM_FIFO_TYPE_RACH + 512x36 + + + C_PRIM_FIFO_TYPE_RDCH + 512x72 + + + C_PRIM_FIFO_TYPE_AXIS + 1kx18 + + + C_USE_ECC_WACH + 0 + + + C_USE_ECC_WDCH + 0 + + + C_USE_ECC_WRCH + 0 + + + C_USE_ECC_RACH + 0 + + + C_USE_ECC_RDCH + 0 + + + C_USE_ECC_AXIS + 0 + + + C_ERROR_INJECTION_TYPE_WACH + 0 + + + C_ERROR_INJECTION_TYPE_WDCH + 0 + + + C_ERROR_INJECTION_TYPE_WRCH + 0 + + + C_ERROR_INJECTION_TYPE_RACH + 0 + + + C_ERROR_INJECTION_TYPE_RDCH + 0 + + + C_ERROR_INJECTION_TYPE_AXIS + 0 + + + C_DIN_WIDTH_WACH + 1 + + + C_DIN_WIDTH_WDCH + 64 + + + C_DIN_WIDTH_WRCH + 2 + + + C_DIN_WIDTH_RACH + 32 + + + C_DIN_WIDTH_RDCH + 64 + + + C_DIN_WIDTH_AXIS + 1 + + + C_WR_DEPTH_WACH + 16 + + + C_WR_DEPTH_WDCH + 1024 + + + C_WR_DEPTH_WRCH + 16 + + + C_WR_DEPTH_RACH + 16 + + + C_WR_DEPTH_RDCH + 1024 + + + C_WR_DEPTH_AXIS + 1024 + + + C_WR_PNTR_WIDTH_WACH + 4 + + + C_WR_PNTR_WIDTH_WDCH + 10 + + + C_WR_PNTR_WIDTH_WRCH + 4 + + + C_WR_PNTR_WIDTH_RACH + 4 + + + C_WR_PNTR_WIDTH_RDCH + 10 + + + C_WR_PNTR_WIDTH_AXIS + 10 + + + C_HAS_DATA_COUNTS_WACH + 0 + + + C_HAS_DATA_COUNTS_WDCH + 0 + + + C_HAS_DATA_COUNTS_WRCH + 0 + + + C_HAS_DATA_COUNTS_RACH + 0 + + + C_HAS_DATA_COUNTS_RDCH + 0 + + + C_HAS_DATA_COUNTS_AXIS + 0 + + + C_HAS_PROG_FLAGS_WACH + 0 + + + C_HAS_PROG_FLAGS_WDCH + 0 + + + C_HAS_PROG_FLAGS_WRCH + 0 + + + C_HAS_PROG_FLAGS_RACH + 0 + + + C_HAS_PROG_FLAGS_RDCH + 0 + + + C_HAS_PROG_FLAGS_AXIS + 0 + + + C_PROG_FULL_TYPE_WACH + 0 + + + C_PROG_FULL_TYPE_WDCH + 0 + + + C_PROG_FULL_TYPE_WRCH + 0 + + + C_PROG_FULL_TYPE_RACH + 0 + + + C_PROG_FULL_TYPE_RDCH + 0 + + + C_PROG_FULL_TYPE_AXIS + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WRCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_165ed04b + 64 + + + choice_list_22f447d7 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_62eb4a48 + 512 + 1024 + 2048 + 4096 + 8192 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_19452de4 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_40558afa + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + choice_pairs_ef3e87e1 + Embedded_Reg + + + choice_pairs_f78383bc + Synchronous_Reset + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + rdback_fifo + + + + true + + + + + + Fifo_Implementation + Common_Clock_Builtin_FIFO + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + First_Word_Fall_Through + + + + true + + + + + + asymmetric_port_width + true + + + + true + + + + + + Input_Data_Width + 512 + + + + true + + + + + + Input_Depth + 1024 + + + + true + + + + + + Output_Data_Width + 256 + + + + true + + + + + + Output_Depth + 2048 + + + + false + + + + + + Enable_ECC + false + + + + false + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + false + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + false + + + + + + Full_Flags_Reset_Value + 0 + + + + false + + + + + + Use_Dout_Reset + true + + + + false + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + true + + + + + + Almost_Full_Flag + false + + + + false + + + + + + Almost_Empty_Flag + false + + + + false + + + + + + Valid_Flag + true + + + + true + + + + + + Valid_Sense + Active_High + + + + true + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + false + + + + false + + + + + + Data_Count_Width + 10 + + + + false + + + + + + Write_Data_Count + false + + + + false + + + + + + Write_Data_Count_Width + 10 + + + + false + + + + + + Read_Data_Count + false + + + + false + + + + + + Read_Data_Count_Width + 11 + + + + false + + + + + + Disable_Timing_Violations + false + + + + false + + + + + + Read_Clock_Frequency + 1 + + + + false + + + + + + Write_Clock_Frequency + 1 + + + + false + + + + + + Programmable_Full_Type + Single_Programmable_Full_Threshold_Constant + + + + true + + + + + + Full_Threshold_Assert_Value + 895 + + + + true + + + + + + Full_Threshold_Negate_Value + 894 + + + + false + + + + + + Programmable_Empty_Type + Single_Programmable_Empty_Threshold_Constant + + + + true + + + + + + Empty_Threshold_Assert_Value + 4 + + + + true + + + + + + Empty_Threshold_Negate_Value + 5 + + + + false + + + + + + PROTOCOL + AXI4 + + + + false + + + + + + Clock_Type_AXI + Common_Clock + + + + true + + + + + + HAS_ACLKEN + false + + + + false + + + + + + Clock_Enable_Type + Slave_Interface_Clock_Enable + + + + false + + + + + + READ_WRITE_MODE + READ_WRITE + + + + true + + + + + + ID_WIDTH + 0 + + + + false + + + + + + ADDRESS_WIDTH + 32 + + + + false + + + + + + DATA_WIDTH + 64 + + + + false + + + + + + AWUSER_Width + 0 + + + + false + + + + + + WUSER_Width + 0 + + + + false + + + + + + BUSER_Width + 0 + + + + false + + + + + + ARUSER_Width + 0 + + + + false + + + + + + RUSER_Width + 0 + + + + false + + + + + + TDATA_NUM_BYTES + 1 + + + + true + + + + + + TID_WIDTH + 0 + + + + false + + + + + + TDEST_WIDTH + 0 + + + + false + + + + + + TUSER_WIDTH + 4 + + + + false + + + + + + Enable_TREADY + true + + + + false + + + + + + Enable_TLAST + false + + + + true + + + + + + HAS_TSTRB + false + + + + false + + + + + + TSTRB_WIDTH + 1 + + + + false + + + + + + HAS_TKEEP + false + + + + false + + + + + + TKEEP_WIDTH + 1 + + + + false + + + + + + wach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wach + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wach + false + + + + false + + + + + + Inject_Sbit_Error_wach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wach + false + + + + false + + + + + + Input_Depth_wach + 16 + + + + true + + + + + + Enable_Data_Counts_wach + false + + + + false + + + + + + Programmable_Full_Type_wach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wdch + false + + + + false + + + + + + Inject_Sbit_Error_wdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wdch + false + + + + false + + + + + + Input_Depth_wdch + 1024 + + + + true + + + + + + Enable_Data_Counts_wdch + false + + + + false + + + + + + Programmable_Full_Type_wdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wrch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wrch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wrch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wrch + false + + + + false + + + + + + Inject_Sbit_Error_wrch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wrch + false + + + + false + + + + + + Input_Depth_wrch + 16 + + + + true + + + + + + Enable_Data_Counts_wrch + false + + + + false + + + + + + Programmable_Full_Type_wrch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wrch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wrch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wrch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rach + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rach + false + + + + false + + + + + + Inject_Sbit_Error_rach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rach + false + + + + false + + + + + + Input_Depth_rach + 16 + + + + true + + + + + + Enable_Data_Counts_rach + false + + + + false + + + + + + Programmable_Full_Type_rach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rdch + false + + + + false + + + + + + Inject_Sbit_Error_rdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rdch + false + + + + false + + + + + + Input_Depth_rdch + 1024 + + + + true + + + + + + Enable_Data_Counts_rdch + false + + + + false + + + + + + Programmable_Full_Type_rdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + axis_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_axis + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_axis + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_axis + false + 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+ use_dout_register + false + + + + false + + + + + + Master_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Slave_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Output_Register_Type + Embedded_Reg + + + + true + + + + + + Enable_Safety_Circuit + false + + + + false + + + + + + Enable_ECC_Type + Hard_ECC + + + + false + + + + + + C_SELECT_XPM + 0 + + + + + FIFO Generator + + XPM_MEMORY + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xci b/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xci new file mode 100644 index 0000000..44575ea --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xci @@ -0,0 +1,327 @@ + + + xilinx.com + xci + unknown + 1.0 + + + scratchpad + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 10 + 10 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 2.119075 mW + virtexuplus + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + scratchpad.mem + no_coe_file_loaded + 0 + 0 + 0 + 0 + 1 + 1024 + 1024 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1024 + 1024 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + no_coe_file_loaded + ALL + scratchpad + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 1024 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xml b/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xml new file mode 100644 index 0000000..b489504 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xml @@ -0,0 +1,4182 @@ + + + xilinx.com + customized_ip + scratchpad + 1.0 + + + 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C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 0 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 1 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 2.119075 mW + + + + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_784e1e2a + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + scratchpad + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + 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rxcdrreset_in rxdfelpmreset_in rxlpmen_in rxpc +sreset_in rxpd_in rxpmareset_in rxpolarity_in rxprbscntreset_in rxprbssel_in rxrate_in txdeemph_in txdetectrx_in txelecidle_in txmaincursor_in txmargin_in txpcsreset_in txpd_in txpmareset_in txpostcursor_in txprbsforceerr_in txprbssel_in txprecursor_in txrate_in txswing_in bufgtce_out bufgtcemask_out bufgtdiv_out bufgtreset_out bufgtrstmask_out drpdo_common_out drprdy_common_out gtpowergood_out pcierategen3_out pcierateidle_out pcierateqpllpd_out pcierateqpllreset_out pciesynctxsyncdone_out pcie +usergen3rdy_out pcieuserphystatusrst_out pcieuserratestart_out phystatus_out rxelecidle_out rxoutclkfabric_out rxoutclkpcs_out rxprbserr_out rxprbslocked_out rxrecclkout_out rxstatus_out rxvalid_out txoutclkfabric_out txoutclkpcs_out qpll1freqlock_in qpll0freqlock_in cpllfreqlock_in qpll0lock_out qpll1lock_out drpclk_in cpllreset_in qpll1outclk_out qpll1outrefclk_out qpll0outclk_out qpll0outrefclk_out pcierateqpll0_in pcierateqpll1_in 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+ CUSTOM + PCIE_GEN1_GEN2 + PCIE_GEN3 + QPI + + + choice_pairs_4e550952 + NONE + EXAMPLE_DESIGN + + + choice_pairs_5d4d976c + None + GTY-100GAUI_4 + GTY-100GBASE-KR4 + GTY-10GBASE-KR + GTY-10GBASE-R + GTY-12G_SDI + GTY-1G_10G_25G_switchable + GTY-3G_SDI + GTY-50GAUI_2 + GTY-Aurora_64B66B + GTY-Aurora_8B10B + GTY-Bandwidth_Engine + GTY-CAUI_10 + GTY-CAUI_10_raw + GTY-CAUI_4 + GTY-CEI_11G_SR + GTY-CPRI_10G + GTY-CPRI_10_1G + GTY-CPRI_10_1G_lowloss + GTY-CPRI_6G + GTY-DisplayPort_1_62G + GTY-DisplayPort_2_7G + GTY-DisplayPort_5_4G + GTY-DisplayPort_8_1G + GTY-Gigabit_Ethernet + GTY-HDMI + GTY-HD_SDI + GTY-HMC_12_5G + GTY-Interlaken_10G + GTY-Interlaken_12_5G + GTY-Interlaken_25G + GTY-JESD204 + GTY-JESD204B_highloss + GTY-JESD204B_lowloss + GTY-OTL4_10 + GTY-OTU2 + GTY-OTU2e + GTY-OTU4 + GTY-QSGMII + GTY-RXAUI + GTY-SATA + GTY-SRIO_Gen2 + GTY-VbyOne + GTY-XAUI + GTY-XLAUI + + + choice_pairs_7b0c3758 + RX + BOTH + TX + + + choice_pairs_85f99b7f + K28.1 + K28.5 + NONE + + + choice_pairs_8846c8f0 + RAW + 8B10B + 64B66B + 64B66B_CAUI + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_88c85933 + 8B10B + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + RAW + 64B66B + 64B66B_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_93c2d4ee + CORE + EXAMPLE_DESIGN + + + choice_pairs_9c19f015 + 1 + 2 + + + choice_pairs_a537ddda + 0 + 1 + + + choice_pairs_aa541099 + AUTO + DFE + LPM + + + choice_pairs_ae574462 + OFF + PCS + PMA + AUTO + + + choice_pairs_b0974ef0 + 1 + 2 + 0 + + + choice_pairs_d4feb97d + DISABLE + ENABLE + + + choice_pairs_f05b8192 + CHANNEL + NAME + + + The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. + + + GT_TYPE + Transceiver type + For devices which contain more than one serial transceiver type, select the type of transceiver to configure + GTY + + + INTERNAL_GT_PRIM_TYPE + gtye4 + + + + false + + + + + + GT_REV + Transceiver revision + Select the serial transceiver silicon revision + 0 + + + GT_DIRECTION + Transmit and/or Receive direction + Enable transmit and/or receive + BOTH + + + RX_ENABLE + Enabled + Enable the receiver for use + true + + + + false + + + + + + TX_ENABLE + Enabled + Enable the transmitter for use + true + + + + false + + + + + + CHANNEL_ENABLE + Enable channel + Indicate whether this transceiver channel is instantiated and enabled for use + X1Y35 X1Y34 X1Y33 X1Y32 X1Y31 X1Y30 X1Y29 X1Y28 + + + TX_MASTER_CHANNEL + Master TX channel + Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) + X1Y35 + + + RX_MASTER_CHANNEL + Master RX channel + Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) + X1Y35 + + + INTERNAL_TOTAL_NUM_CHANNELS + Total number of channels + 8 + + + + false + + + + + + INTERNAL_TOTAL_NUM_COMMONS + Total number of commons required + 2 + + + + false + + + + + + LOCATE_COMMON + Include transceiver COMMON in the + If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. + CORE + + + INTERNAL_NUM_COMMONS_CORE + Number of commons in core + 2 + + + + false + + + + + + INTERNAL_NUM_COMMONS_EXAMPLE + Number of commons in example + 0 + + + + false + + + + + + INTERNAL_TX_USRCLK_FREQUENCY + 400.0000000 + + + + false + + + + + + INTERNAL_RX_USRCLK_FREQUENCY + 400.0000000 + + + + false + + + + + + RX_PPM_OFFSET + PPM offset between receiver and transmitter + Specify the PPM offset between received data and transmitted data + 0 + + + OOB_ENABLE + Enable Out of Band signaling (OOB)/Electrical Idle + Enable or disable Out of Band signaling (OOB)/Electrical Idle + false + + + + false + + + + + + RX_SSC_PPM + Spread spectrum clocking + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Insertion loss at Nyquist (dB) + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 15 + + + PCIE_CORECLK_FREQ + 500 + + + PCIE_USERCLK_FREQ + 250 + + + TX_LINE_RATE + Line rate (Gb/s) + Enter the transmitter line rate in Gb/s + 8 + + + TX_PLL_TYPE + PLL type + Select the transmitter PLL type + QPLL1 + + + TX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type + 100 + + + TX_DATA_ENCODING + Encoding + Select the encoding format for data transmission, or choose 'Raw' for no data encoding + 8B10B + + + TX_USER_DATA_WIDTH + User data width + Select the width at which the user logic will provide parallel data to the serial transceiver for transmission + 16 + + + TX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal transmitter data path + 20 + + + TX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the transmitter buffer + 0 + + + TX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection + 0 + + + TX_OUTCLK_SOURCE + TXOUTCLK source + Select the source of TXOUTCLK + TXPROGDIVCLK + + + TX_DIFF_SWING_EMPH_MODE + Differential swing and emphasis mode + Select the transmitter differential swing and emphasis mode for your application + PCIE_GEN1_GEN2 + + + RX_LINE_RATE + Line rate (Gb/s) + Enter the receiver line rate in Gb/s + 8 + + + RX_PLL_TYPE + PLL type + Select the receiver PLL type + QPLL1 + + + RX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type + 100 + + + RX_DATA_DECODING + Decoding + Select the decoding format for data reception, or choose 'Raw' for no data decoding + 8B10B + + + RX_USER_DATA_WIDTH + User data width + Select the width at which the serial transceiver will provide received parallel data to the user logic + 16 + + + RX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal receiver data path + 20 + + + RX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the receiver elastic buffer + 1 + + + RX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection + 0 + + + RX_EQ_MODE + Equalization mode + Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. + DFE + + + RX_JTOL_FC + Mask corner frequency (MHz) + Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. + 1 + + + RX_JTOL_LF_SLOPE + Mask low frequency slope (dB/decade) + Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. + -20 + + + RX_OUTCLK_SOURCE + RXOUTCLK source + Select the source of RXOUTCLK + RXOUTCLKPMA + + + SIM_CPLL_CAL_BYPASS + 1 + + + PCIE_ENABLE + true + + + RX_TERMINATION + Termination + Select the receiver termination + PROGRAMMABLE + + + RX_TERMINATION_PROG_VALUE + Programmable termination voltage (mV) + Select the termination voltage (in mV) when in programmable mode + 800 + + + RX_COUPLING + Link coupling + Select the link coupling + AC + + + RX_BUFFER_BYPASS_MODE + Receiver elastic buffer bypass mode + Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode + MULTI + + + + false + + + + + + RX_BUFFER_RESET_ON_CB_CHANGE + Reset receiver elastic buffer on channel bonding change + Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL + ENABLE + + + + false + + + + + + RX_BUFFER_RESET_ON_COMMAALIGN + Reset receiver elastic buffer on comma alignment + Control whether the receiver elastic buffer is reset on comma alignment + DISABLE + + + RX_BUFFER_RESET_ON_RATE_CHANGE + Reset receiver elastic buffer on rate change + Control whether the receiver elastic buffer is reset on rate change + ENABLE + + + TX_BUFFER_RESET_ON_RATE_CHANGE + Reset transmitter buffer on rate change + Control whether the transmitter buffer is reset on rate change + ENABLE + + + + false + + + + + + RESET_SEQUENCE_INTERVAL + Reset sequence time interval (ns) + Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval + 0 + + + RX_COMMA_PRESET + Comma value preset + K28.5 + + + RX_COMMA_VALID_ONLY + Valid comma values for 8B/10B decoding + Select the range of comma characters decoded by the 8B/10B decoder + 0 + + + RX_COMMA_P_ENABLE + Detect plus comma + Indicate whether or not the specified bit pattern is detected as a plus comma + true + + + RX_COMMA_M_ENABLE + Detect minus comma + Indicate whether or not the specified bit pattern is detected as a minus comma + true + + + RX_COMMA_DOUBLE_ENABLE + Detect combined plus/minus (double-length) comma + Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence + false + + + RX_COMMA_P_VAL + Plus comma value + Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received + 0101111100 + + + RX_COMMA_M_VAL + Minus comma value + Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received + 1010000011 + + + RX_COMMA_MASK + Mask + Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" + 1111111111 + + + RX_COMMA_ALIGN_WORD + Alignment boundary + Select which data byte boundaries are allowed for comma alignment + 1 + + + RX_COMMA_SHOW_REALIGN_ENABLE + Show realign comma + Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency + true + + + RX_SLIDE_MODE + Manual alignment (RXSLIDE) mode + Select whether to enable manual alignment, and in what mode if enabled + PMA + + + RX_CB_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable channel bonding, and how many sequences to use if enabled + 0 + + + RX_CB_LEN_SEQ + Length of each sequence + Select the number of characters in each channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_SKEW + Sequence maximum skew + Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_LEVEL + Maximum channel bonding level to be used + Select the maximum channel bonding level that will be used in the system channel bonding topology + 4 + + + + false + + + + + + RX_CB_MASK + 00000000 + + + + false + + + + + + RX_CB_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + + + + false + + + + + + RX_CB_K + 00000000 + + + + false + + + + + + RX_CB_DISP + 00000000 + + + + false + + + + + + RX_CB_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable clock correction, and how many sequences to use if enabled + 1 + + + RX_CC_LEN_SEQ + Length of each sequence + Select the number of characters in each channel clock correction sequence + 1 + + + RX_CC_PERIODICITY + Periodicity of the sequence (in bytes) + Specify the separation between clock correction sequences, in bytes + 5000 + + + RX_CC_KEEP_IDLE + Keep idle + Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received + ENABLE + + + RX_CC_PRECEDENCE + Precedence + Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time + ENABLE + + + + false + + + + + + RX_CC_REPEAT_WAIT + Minimum repetition + Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction + 0 + + + RX_CC_MASK + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + 00000000 + + + + false + + + + + + RX_CC_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000011100 + + + RX_CC_K + 00000001 + + + + false + + + + + + RX_CC_DISP + 00000000 + + + + false + + + + + + RX_CC_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_0 + Value + Specify the value for this clock correction sequence and pattern + 00011100 + + + RX_CC_K_0_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_1 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_0 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_1 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + ENABLE_OPTIONAL_PORTS + Enable optional ports + Indicate whether a port should be included + txpdelecidlemode_in txprgdivresetdone_out rcalenb_in txpisopd_in rxratemode_in dmonfiforeset_in dmonitorclk_in dmonitorout_out txdlysresetdone_out rxdlysresetdone_out rxphaligndone_out rxsyncdone_out eyescanreset_in txdiffctrl_in rxtermination_in cpllpd_in drpaddr_common_in drpclk_common_in drpdi_common_in drpen_common_in drpwe_common_in loopback_in pcieeqrxeqadaptdone_in pcierstidle_in pciersttxsyncstart_in pcieuserratedone_in qpll0pd_in qpll1pd_in rxcdrreset_in rxdfelpmreset_in rxlpmen_in rxpc +sreset_in rxpd_in rxpmareset_in rxpolarity_in rxprbscntreset_in rxprbssel_in rxrate_in txdeemph_in txdetectrx_in txelecidle_in txmaincursor_in txmargin_in txpcsreset_in txpd_in txpmareset_in txpostcursor_in txprbsforceerr_in txprbssel_in txprecursor_in txrate_in txswing_in bufgtce_out bufgtcemask_out bufgtdiv_out bufgtreset_out bufgtrstmask_out drpdo_common_out drprdy_common_out gtpowergood_out pcierategen3_out pcierateidle_out pcierateqpllpd_out pcierateqpllreset_out pciesynctxsyncdone_out pcie +usergen3rdy_out pcieuserphystatusrst_out pcieuserratestart_out phystatus_out rxelecidle_out rxoutclkfabric_out rxoutclkpcs_out rxprbserr_out rxprbslocked_out rxrecclkout_out rxstatus_out rxvalid_out txoutclkfabric_out txoutclkpcs_out qpll1freqlock_in qpll0freqlock_in cpllfreqlock_in qpll0lock_out qpll1lock_out drpclk_in cpllreset_in qpll1outclk_out qpll1outrefclk_out qpll0outclk_out qpll0outrefclk_out pcierateqpll0_in pcierateqpll1_in gtrefclk00_in gtrefclk01_in qpll0reset_in qpll1reset_in drpwe +_in drpaddr_in drpen_in drprst_in drprdy_out drpdi_in drpdo_out rxcdrhold_in rxdfeagchold_in rxdfecfokhold_in rxdfelfhold_in rxdfekhhold_in rxdfetap2hold_in rxdfetap3hold_in rxdfetap4hold_in rxdfetap5hold_in rxdfetap6hold_in rxdfetap7hold_in rxdfetap8hold_in rxdfetap9hold_in rxdfetap10hold_in rxdfetap11hold_in rxdfetap12hold_in rxdfetap13hold_in rxdfetap14hold_in rxdfetap15hold_in rxdfeuthold_in rxdfevphold_in rxoshold_in rxlpmgchold_in rxlpmhfhold_in rxlpmlfhold_in rxlpmoshold_in rxratedone_out + rxcdrfreqreset_in resetovrd_in txoutclksel_in cplllock_out gtrefclk0_in + + + RX_REFCLK_SOURCE + Receiver reference clock source + Select a reference clock input to drive the PLL chosen for receiver operation + + + + TX_REFCLK_SOURCE + Transmitter reference clock source + Select a reference clock input to drive the PLL chosen for transmitter operation + + + + RX_RECCLK_OUTPUT + Drive recovered clock out of device + Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use + + + + LOCATE_RESET_CONTROLLER + Include reset controller in the + Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + LOCATE_TX_BUFFER_BYPASS_CONTROLLER + Include transmitter buffer bypass controller in the + If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + LOCATE_RX_BUFFER_BYPASS_CONTROLLER + Include receiver elastic buffer bypass controller in the + If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_IN_SYSTEM_IBERT_CORE + Include In-System IBERT core + Indicate whether or not the In-System IBERT core should be instantiated in the example design. + NONE + + + LOCATE_TX_USER_CLOCKING + Include simple transmitter user clocking network in the + Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_RX_USER_CLOCKING + Include simple receiver user clocking network in the + Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_USER_DATA_WIDTH_SIZING + Include user data width sizing in the + Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + ORGANIZE_PORTS_BY + In the example design, organize ports across multiple channels by + If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) + NAME + + + PRESET + Transceiver configuration preset + You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard + None + + + INTERNAL_PRESET + Transceiver configuration preset + None + + + INTERNAL_PORT_USAGE_UPDATED + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLEMENT_UPDATED + 23 + + + + false + + + + + + INTERNAL_CHANNEL_SITES_UPDATED + 5 + + + + false + + + + + + INTERNAL_CHANNEL_COLUMN_LOC_MAX + 96 + + + + false + + + + + + INTERNAL_RX_COMMA_PRESET_UPDATE + 8 + + + + false + + + + + + INTERNAL_UPDATE_IP_SYMBOL_drpclk_in + true + + + + false + + + + + + SECONDARY_QPLL_ENABLE + Enable secondary QPLL + Enable and configure the QPLL which is not used in this core configuration + false + + + SECONDARY_QPLL_LINE_RATE + Line rate of second core (Gb/s) + Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL + 10.3125 + + + + false + + + + + + SECONDARY_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection + 0 + + + + false + + + + + + SECONDARY_QPLL_REFCLK_FREQUENCY + Actual Reference clock frequency (MHz) + Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate + 257.8125 + + + + false + + + + + + TXPROGDIV_FREQ_ENABLE + Enable selectable TXOUTCLK frequency + Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency + false + + + TXPROGDIV_FREQ_SOURCE + Programmable divider clock source + Select which PLL source is used to generate the selectable TXOUTCLK frequency + QPLL1 + + + + false + + + + + + TXPROGDIV_FREQ_VAL + TXOUTCLK frequency (MHz) + Select the TXOUTCLK frequency to be generated by the TX programmable divider + 400 + + + + false + + + + + + SATA_TX_BURST_LEN + TX COM sequence burst length + Select the number of bursts that make up a SATA COM sequence + 15 + + + FREERUN_FREQUENCY + Free-running and DRP clock frequency (MHz) + Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface + 100 + + + INCLUDE_CPLL_CAL + 1 + + + USER_GTPOWERGOOD_DELAY_EN + Select 1 to enable powergood delay circuit + 1 + + + DISABLE_LOC_XDC + Select to disable generation of LOC constraints in xdc + 0 + + + ENABLE_COMMON_USRCLK + 0 + + + USB_ENABLE + false + + + PCIE_64BIT + false + + + PCIE_GEN4_EIOS + false + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGBYPASSB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGMONITORENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGPDB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK01_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0PD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0RESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN + 0 + + + + false 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml new file mode 100644 index 0000000..26fa7a1 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml @@ -0,0 +1,28293 @@ + + + xilinx.com + customized_ip + xdma_pcie4_ip + 1.0 + + + m_axis_cq + m_axis_cq + The Completer Request interface is used to transmit Completion TLP's to the Client Application + + + + + + + TDATA + + + m_axis_cq_tdata + + + + + TKEEP + + + m_axis_cq_tkeep + + + + + TLAST + + + m_axis_cq_tlast + + + + + TREADY + + + m_axis_cq_tready + + + + + TUSER + + + m_axis_cq_tuser + + + + + TVALID + + + m_axis_cq_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 88 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + s_axis_cc + s_axis_cc + The Completer Completion Interface is used to transmit Completion TLP's + + + + + + + TDATA + + + s_axis_cc_tdata + + + + + TKEEP + + + s_axis_cc_tkeep + + + + + TLAST + + + s_axis_cc_tlast + + + + + TREADY + + + s_axis_cc_tready + + + + + TUSER + + + s_axis_cc_tuser + + + + + TVALID + + + s_axis_cc_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 33 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + s_axis_rq + s_axis_rq + The Requestor Request interface received requests TLP's from the Client Application + + + + + + + TDATA + + + s_axis_rq_tdata + + + + + TKEEP + + + s_axis_rq_tkeep + + + + + TLAST + + + s_axis_rq_tlast + + + + + TREADY + + + s_axis_rq_tready + + + + + TUSER + + + s_axis_rq_tuser + + + + + TVALID + + + s_axis_rq_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 62 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + m_axis_rc + m_axis_rc + The Requestor Completer interface transmits completions to the client application + + + + + + + TDATA + + + m_axis_rc_tdata + + + + + TKEEP + + + m_axis_rc_tkeep + + + + + TLAST + + + m_axis_rc_tlast + + + + + TREADY + + + m_axis_rc_tready + + + + + TUSER + + + m_axis_rc_tuser + + + + + TVALID + + + m_axis_rc_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 75 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.sys_rst + RST.sys_rst + sys_rst interface + + + + + + + RST + + + sys_reset + + + + + + BOARD.ASSOCIATED_PARAM + SYS_RST_N_BOARD_INTERFACE + + + + required + + + + + + TYPE + PCIE_PERST + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + pcie4_mgt + pcie_7x_mgt + PCIExpress Serial Link Interface + + + + + + + rxn + + + pci_exp_rxn + + + + + rxp + + + pci_exp_rxp + + + + + txn + + + pci_exp_txn + + + + + txp + + + pci_exp_txp + + + + + + BOARD.ASSOCIATED_PARAM + PCIE_BOARD_INTERFACE + + + + required + + + + + + + + + true + + + + + + pcie4_cfg_fc + pcie_cfg_fc + Configuration Flow Control INTERFACE + + + + + + + CPLD + + + cfg_fc_cpld + + + + + CPLH + + + cfg_fc_cplh + + + + + NPD + + + cfg_fc_npd + + + + + NPH + + + cfg_fc_nph + + + + + PD + + + cfg_fc_pd + + + + + PH + + + cfg_fc_ph + + + + + SEL + + + cfg_fc_sel + + + + + + + true + + + + + + pcie4_cfg_mgmt + pcie4_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr + + + + + BYTE_EN + + + cfg_mgmt_byte_enable + + + + + DEBUG_ACCESS + + + cfg_mgmt_debug_access + + + + + FUNCTION_NUMBER + + + cfg_mgmt_function_number + + + + + READ_DATA + + + cfg_mgmt_read_data + + + + + READ_EN + + + cfg_mgmt_read + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done + + + + + WRITE_DATA + + + cfg_mgmt_write_data + + + + + WRITE_EN + + + cfg_mgmt_write + + + + + + + true + + + + + + pcie4_cfg_mgmt_if + pcie4_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr + + + + + BYTE_EN + + + cfg_mgmt_byte_enable + + + + + DEBUG_ACCESS + + + cfg_mgmt_debug_access + + + + + FUNCTION_NUMBER + + + cfg_mgmt_function_number + + + + + READ_DATA + + + cfg_mgmt_read_data + + + + + READ_EN + + + cfg_mgmt_read + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done + + + + + WRITE_DATA + + + cfg_mgmt_write_data + + + + + WRITE_EN + + + cfg_mgmt_write + + + + + + + false + + + + + + pcie4_cfg_pm + pcie4_cfg_pm + PCIE4 Power Management Interface + + + + + + + pm_aspm_l1entry_reject + + + cfg_pm_aspm_l1_entry_reject + + + + + pm_aspm_tx_l0s_entry_disable + + + cfg_pm_aspm_tx_l0s_entry_disable + + + + + + + true + + + + + + pcie4_cfg_msi + pcie4_cfg_msi + PCIE MSI interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr + + + + + data + + + cfg_interrupt_msi_data + + + + + enable + + + cfg_interrupt_msi_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msi_int + + + + + mask_update + + + cfg_interrupt_msi_mask_update + + + + + mmenable + + + cfg_interrupt_msi_mmenable + + + + + pending_status + + + cfg_interrupt_msi_pending_status + + + + + pending_status_data_enable + + + cfg_interrupt_msi_pending_status_data_enable + + + + + pending_status_function_num + + + cfg_interrupt_msi_pending_status_function_num + + + + + select + + + cfg_interrupt_msi_select + + + + + sent + + + cfg_interrupt_msi_sent + + + + + tph_present + + + cfg_interrupt_msi_tph_present + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag + + + + + tph_type + + + cfg_interrupt_msi_tph_type + + + + + + + true + + + + + + pcie4_cfg_msix_internal + pcie4_cfg_msix_internal + PCIE MSIx Int Interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr + + + + + enable + + + cfg_interrupt_msix_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + mint_vector + + + cfg_interrupt_msi_int + + + + + sent + + + cfg_interrupt_msi_sent + + + + + tph_present + + + cfg_interrupt_msi_tph_present + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag + + + + + tph_type + + + cfg_interrupt_msi_tph_type + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_msix_internal_if + pcie4_cfg_msix_internal + PCIE MSIx Int Interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr + + + + + enable + + + cfg_interrupt_msix_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + mint_vector + + + cfg_interrupt_msi_int + + + + + sent + + + cfg_interrupt_msi_sent + + + + + tph_present + + + cfg_interrupt_msi_tph_present + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag + + + + + tph_type + + + cfg_interrupt_msi_tph_type + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_external_msix + pcie4_cfg_external_msix_without_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address + + + + + data + + + cfg_interrupt_msix_data + + + + + enable + + + cfg_interrupt_msix_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + sent + + + cfg_interrupt_msi_sent + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_external_msix_without_msi_if + pcie4_cfg_external_msix_without_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address + + + + + data + + + cfg_interrupt_msix_data + + + + + enable + + + cfg_interrupt_msix_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + sent + + + cfg_interrupt_msi_sent + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_msix_external + pcie4_cfg_external_msix_with_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address + + + + + data + + + cfg_interrupt_msix_data + + + + + enable + + + cfg_interrupt_msix_enable + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_external_msix_with_msi_if + pcie4_cfg_external_msix_with_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address + + + + + data + + + cfg_interrupt_msix_data + + + + + enable + + + cfg_interrupt_msix_enable + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_interrupt + pcie4_cfg_interrupt + PCIE Legacy Interrupt + + + + + + + INTx_VECTOR + + + cfg_interrupt_int + + + + + PENDING + + + cfg_interrupt_pending + + + + + SENT + + + cfg_interrupt_sent + + + + + + pcie4_cfg_ext + pcie4_cfg_ext + Configuration Extend Interface + + + + + + + function_number + + + cfg_ext_function_number + + + + + read_data + + + cfg_ext_read_data + + + + + read_data_valid + + + cfg_ext_read_data_valid + + + + + read_received + + + cfg_ext_read_received + + + + + register_number + + + cfg_ext_register_number + + + + + write_byte_enable + + + cfg_ext_write_byte_enable + + + + + write_data + + + cfg_ext_write_data + + + + + write_received + + + cfg_ext_write_received + + + + + + + false + + + + + + pcie4_rbar + pcie4_rbar + Resizable bar Interface + + + + + + + bar_size + + + rbar_bar_size + + + + + function_number + + + rbar_function_number + + + + + write_enable_bar0 + + + rbar_write_enable_bar0 + + + + + write_enable_bar1 + + + rbar_write_enable_bar1 + + + + + write_enable_bar2 + + + rbar_write_enable_bar2 + + + + + write_enable_bar3 + + + rbar_write_enable_bar3 + + + + + write_enable_bar4 + + + rbar_write_enable_bar4 + + + + + write_enable_bar5 + + + rbar_write_enable_bar5 + + + + + + + false + + + + + + pcie4_cfg_mesg_tx + pcie4_cfg_mesg_tx + Configuration Transmit Message Interface + + + + + + + TRANSMIT + + + cfg_msg_transmit + + + + + TRANSMIT_DATA + + + cfg_msg_transmit_data + + + + + TRANSMIT_DONE + + + cfg_msg_transmit_done + + + + + TRANSMIT_TYPE + + + cfg_msg_transmit_type + + + + + + + true + + + + + + pcie4_cfg_mesg_rcvd + pcie4_cfg_mesg_rcvd + Configuration Received Message Interface + + + + + + + recd + + + cfg_msg_received + + + + + recd_data + + + cfg_msg_received_data + + + + + recd_type + + + cfg_msg_received_type + + + + + + + true + + + + + + pcie4_cfg_control + pcie4_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + bus_number + + + cfg_bus_number + + + + + config_space_enable + + + cfg_config_space_enable + + + + + ds_bus_number + + + cfg_ds_bus_number + + + + + ds_device_number + + + cfg_ds_device_number + + + + + ds_port_number + + + cfg_ds_port_number + + + + + dsn + + + cfg_dsn + + + + + err_cor_in + + + cfg_err_cor_in + + + + + err_uncor_in + + + cfg_err_uncor_in + + + + + flr_done + + + cfg_flr_done + + + + + flr_in_process + + + cfg_flr_in_process + + + + + hot_reset_in + + + cfg_hot_reset_in + + + + + hot_reset_out + + + cfg_hot_reset_out + + + + + link_training_enable + + + cfg_link_training_enable + + + + + power_state_change_ack + + + cfg_power_state_change_ack + + + + + power_state_change_interrupt + + + cfg_power_state_change_interrupt + + + + + req_pm_transition_l23_ready + + + cfg_req_pm_transition_l23_ready + + + + + vf_flr_done + + + cfg_vf_flr_done + + + + + vf_flr_func_num + + + cfg_vf_flr_func_num + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process + + + + + + + true + + + + + + pcie4_cfg_control_if + pcie4_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + bus_number + + + cfg_bus_number + + + + + config_space_enable + + + cfg_config_space_enable + + + + + ds_bus_number + + + cfg_ds_bus_number + + + + + ds_device_number + + + cfg_ds_device_number + + + + + ds_function_number + + + cfg_ds_function_number + + + + + ds_port_number + + + cfg_ds_port_number + + + + + dsn + + + cfg_dsn + + + + + err_cor_in + + + cfg_err_cor_in + + + + + err_uncor_in + + + cfg_err_uncor_in + + + + + flr_done + + + cfg_flr_done + + + + + flr_in_process + + + cfg_flr_in_process + + + + + hot_reset_in + + + cfg_hot_reset_in + + + + + hot_reset_out + + + cfg_hot_reset_out + + + + + link_training_enable + + + cfg_link_training_enable + + + + + pm_aspm_l1entry_reject + + + cfg_pm_aspm_l1_entry_reject + + + + + pm_aspm_tx_l0s_entry_disable + + + cfg_pm_aspm_tx_l0s_entry_disable + + + + + power_state_change_ack + + + cfg_power_state_change_ack + + + + + power_state_change_interrupt + + + cfg_power_state_change_interrupt + + + + + rbar_function_number + + + rbar_function_number + + + + + rbar_size + + + rbar_bar_size + + + + + req_pm_transition_l23_ready + + + cfg_req_pm_transition_l23_ready + + + + + vf_flr_done + + + cfg_vf_flr_done + + + + + vf_flr_func_num + + + cfg_vf_flr_func_num + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process + + + + + write_enable_rbar0 + + + rbar_write_enable_bar0 + + + + + write_enable_rbar1 + + + rbar_write_enable_bar1 + + + + + write_enable_rbar2 + + + rbar_write_enable_bar2 + + + + + write_enable_rbar3 + + + rbar_write_enable_bar3 + + + + + write_enable_rbar4 + + + rbar_write_enable_bar4 + + + + + write_enable_rbar5 + + + rbar_write_enable_bar5 + + + + + + + false + + + + + + pcie4_pcie_id + pcie4_pcie_id + PCIE 4 PCIE ID interface + + + + + + + subsys_vend_id + + + cfg_subsys_vend_id + + + + + vend_id + + + cfg_vend_id + + + + + + + false + + + + + + pcie4_pcie_id_pf0 + pcie4_pcie_id_pf0 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf0 + + + cfg_dev_id_pf0 + + + + + rev_id_pf0 + + + cfg_rev_id_pf0 + + + + + subsys_id_pf0 + + + cfg_subsys_id_pf0 + + + + + + + false + + + + + + pcie4_pcie_id_pf1 + pcie4_pcie_id_pf1 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf1 + + + cfg_dev_id_pf1 + + + + + rev_id_pf1 + + + cfg_rev_id_pf1 + + + + + subsys_id_pf1 + + + cfg_subsys_id_pf1 + + + + + + + false + + + + + + pcie4_pcie_id_pf2 + pcie4_pcie_id_pf2 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf2 + + + cfg_dev_id_pf2 + + + + + rev_id_pf2 + + + cfg_rev_id_pf2 + + + + + subsys_id_pf2 + + + cfg_subsys_id_pf2 + + + + + + + false + + + + + + pcie4_pcie_id_pf3 + pcie4_pcie_id_pf3 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf3 + + + cfg_dev_id_pf3 + + + + + rev_id_pf3 + + + cfg_rev_id_pf3 + + + + + subsys_id_pf3 + + + cfg_subsys_id_pf3 + + + + + + + false + + + + + + pcie4_cfg_status + pcie4_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req + + + + + cq_np_req_count + + + pcie_cq_np_req_count + + + + + current_speed + + + cfg_current_speed + + + + + err_cor_out + + + cfg_err_cor_out + + + + + err_fatal_out + + + cfg_err_fatal_out + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out + + + + + function_power_state + + + cfg_function_power_state + + + + + function_status + + + cfg_function_status + + + + + link_power_state + + + cfg_link_power_state + + + + + local_error_out + + + cfg_local_error_out + + + + + local_error_valid + + + cfg_local_error_valid + + + + + ltssm_state + + + cfg_ltssm_state + + + + + max_payload + + + cfg_max_payload + + + + + max_read_req + + + cfg_max_read_req + + + + + negotiated_width + + + cfg_negotiated_width + + + + + obff_enable + + + cfg_obff_enable + + + + + phy_link_down + + + cfg_phy_link_down + + + + + phy_link_status + + + cfg_phy_link_status + + + + + pl_status_change + + + cfg_pl_status_change + + + + + rcb_status + + + cfg_rcb_status + + + + + rq_seq_num0 + + + pcie_rq_seq_num0 + + + + + rq_seq_num1 + + + pcie_rq_seq_num1 + + + + + rq_seq_num_vld0 + + + pcie_rq_seq_num_vld0 + + + + + rq_seq_num_vld1 + + + pcie_rq_seq_num_vld1 + + + + + rq_tag0 + + + pcie_rq_tag0 + + + + + rq_tag1 + + + pcie_rq_tag1 + + + + + rq_tag_av + + + pcie_rq_tag_av + + + + + rq_tag_vld0 + + + pcie_rq_tag_vld0 + + + + + rq_tag_vld1 + + + pcie_rq_tag_vld1 + + + + + rx_pm_state + + + cfg_rx_pm_state + + + + + tph_requester_enable + + + cfg_tph_requester_enable + + + + + tph_st_mode + + + cfg_tph_st_mode + + + + + tx_pm_state + + + cfg_tx_pm_state + + + + + vf_power_state + + + cfg_vf_power_state + + + + + vf_status + + + cfg_vf_status + + + + + vf_tph_requester_enable + + + cfg_vf_tph_requester_enable + + + + + vf_tph_st_mode + + + cfg_vf_tph_st_mode + + + + + + + true + + + + + + pcie4_cfg_status_if + pcie4_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req + + + + + cq_np_req_count + + + pcie_cq_np_req_count + + + + + current_speed + + + cfg_current_speed + + + + + err_cor_out + + + cfg_err_cor_out + + + + + err_fatal_out + + + cfg_err_fatal_out + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out + + + + + function_power_state + + + cfg_function_power_state + + + + + function_status + + + cfg_function_status + + + + + link_power_state + + + cfg_link_power_state + + + + + local_error_out + + + cfg_local_error_out + + + + + local_error_valid + + + cfg_local_error_valid + + + + + ltssm_state + + + cfg_ltssm_state + + + + + max_payload + + + cfg_max_payload + + + + + max_read_req + + + cfg_max_read_req + + + + + negotiated_width + + + cfg_negotiated_width + + + + + obff_enable + + + cfg_obff_enable + + + + + phy_link_down + + + cfg_phy_link_down + + + + + phy_link_status + + + cfg_phy_link_status + + + + + pl_status_change + + + cfg_pl_status_change + + + + + rcb_status + + + cfg_rcb_status + + + + + rq_seq_num0 + + + pcie_rq_seq_num0 + + + + + rq_seq_num1 + + + pcie_rq_seq_num1 + + + + + rq_seq_num_vld0 + + + pcie_rq_seq_num_vld0 + + + + + rq_seq_num_vld1 + + + pcie_rq_seq_num_vld1 + + + + + rq_tag0 + + + pcie_rq_tag0 + + + + + rq_tag1 + + + pcie_rq_tag1 + + + + + rq_tag_av + + + pcie_rq_tag_av + + + + + rq_tag_vld0 + + + pcie_rq_tag_vld0 + + + + + rq_tag_vld1 + + + pcie_rq_tag_vld1 + + + + + rx_pm_state + + + cfg_rx_pm_state + + + + + tph_requester_enable + + + cfg_tph_requester_enable + + + + + tph_st_mode + + + cfg_tph_st_mode + + + + + tx_pm_state + + + cfg_tx_pm_state + + + + + vf_power_state + + + cfg_vf_power_state + + + + + vf_status + + + cfg_vf_status + + + + + vf_tph_requester_enable + + + cfg_vf_tph_requester_enable + + + + + vf_tph_st_mode + + + cfg_vf_tph_st_mode + + + + + + + false + + + + + + pcie4_transmit_fc + pcie4_transmit_fc + Transmit Flow Control Interfce + + + + + + + npd_av + + + pcie_tfc_npd_av + + + + + nph_av + + + pcie_tfc_nph_av + + + + + + + true + + + + + + pcie4_drp + pcie4_drp + PCIE DRP Interface + + + + + + + DADDR + + + drp_addr + + + + + DEN + + + drp_en + + + + + DI + + + drp_di + + + + + DO + + + drp_do + + + + + DRDY + + + drp_rdy + + + + + DWE + + + drp_we + + + + + + + false + + + + + + pcie4_drp_if + pcie4_drp + PCIE DRP Interface + + + + + + + DADDR + + + drp_addr + + + + + DEN + + + drp_en + + + + + DI + + + drp_di + + + + + DO + + + drp_do + + + + + DRDY + + + drp_rdy + + + + + DWE + + + drp_we + + + + + + + false + + + + + + CLK.sys_clk + CLK.sys_clk + sys_clk interface + + + + + + + CLK + + + sys_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.sys_clk_gt + CLK.sys_clk_gt + sys_clk_gt interface + + + + + + + CLK + + + sys_clk_gt + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.user_clk + CLK.user_clk + user_clk interface + + + + + + + CLK + + + user_clk + + + + + + ASSOCIATED_BUSIF + m_axis_cq:s_axis_cc:s_axis_rq:m_axis_rc + + + FREQ_HZ + 125000000 + + + ASSOCIATED_RESET + user_reset + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.mcap_clk + CLK.mcap_clk + mcap_clk interface + + + + + + + CLK + + + mcap_clk + + + + + + FREQ_HZ + 125000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + CLK.core_clk + CLK.core_clk + core_clk interface + + + + + + + CLK + + + core_clk + + + + + + FREQ_HZ + 500000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + CLK.gt_drp_clk + CLK.gt_drp_clk + gt_drp_clk interface + + + + + + + CLK + + + gt_drp_clk + + + + + + FREQ_HZ + 125000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + RST.user_reset + RST.user_reset + user_reset interface + + + + + + + RST + + + user_reset + + + + + + POLARITY + ACTIVE_HIGH + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + pcie4_pl + pcie4_pl + Physical Layer Interface + + + + + + + eq_in_progress + + + pl_eq_in_progress + + + + + eq_mismatch + + + pl_eq_mismatch + + + + + eq_phase + + + pl_eq_phase + + + + + gen2_upstream_prefer_deemph + + + pl_gen2_upstream_prefer_deemph + + + + + redo_eq + + + pl_redo_eq + + + + + redo_eq_pending + + + pl_redo_eq_pending + + + + + redo_eq_speed + + + pl_redo_eq_speed + + + + + + + false + + + + + + configure + configure + + + + + + + req_data + + + conf_req_data + + + + + req_ready + + + conf_req_ready + + + + + req_reg_num + + + conf_req_reg_num + + + + + req_type + + + conf_req_type + + + + + req_valid + + + conf_req_valid + + + + + resp_rdata + + + conf_resp_rdata + + + + + resp_valid + + + conf_resp_valid + + + + + + + false + + + + + + cap + cap + + + + + + + GNT + + + cap_gnt + + + + + REL + + + cap_rel + + + + + REQ + + + cap_req + + + + + + + false + + + + + + pcie4_ext_pipe_rp + pcie4_ext_pipe_rp + PCIE4 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_in + + + + + COMMANDS_OUT + + + common_commands_out + + + + + RX_0 + + + pipe_rx_0_sigs + + + + + RX_1 + + + pipe_rx_1_sigs + + + + + RX_2 + + + pipe_rx_2_sigs + + + + + RX_3 + + + pipe_rx_3_sigs + + + + + RX_4 + + + pipe_rx_4_sigs + + + + + RX_5 + + + pipe_rx_5_sigs + + + + + RX_6 + + + pipe_rx_6_sigs + + + + + RX_7 + + + pipe_rx_7_sigs + + + + + RX_8 + + + pipe_rx_8_sigs + + + + + RX_9 + + + pipe_rx_9_sigs + + + + + RX_10 + + + pipe_rx_10_sigs + + + + + RX_11 + + + pipe_rx_11_sigs + + + + + RX_12 + + + pipe_rx_12_sigs + + + + + RX_13 + + + pipe_rx_13_sigs + + + + + RX_14 + + + pipe_rx_14_sigs + + + + + RX_15 + + + pipe_rx_15_sigs + + + + + TX_0 + + + pipe_tx_0_sigs + + + + + TX_1 + + + pipe_tx_1_sigs + + + + + TX_2 + + + pipe_tx_2_sigs + + + + + TX_3 + + + pipe_tx_3_sigs + + + + + TX_4 + + + pipe_tx_4_sigs + + + + + TX_5 + + + pipe_tx_5_sigs + + + + + TX_6 + + + pipe_tx_6_sigs + + + + + TX_7 + + + pipe_tx_7_sigs + + + + + TX_8 + + + pipe_tx_8_sigs + + + + + TX_9 + + + pipe_tx_9_sigs + + + + + TX_10 + + + pipe_tx_10_sigs + + + + + TX_11 + + + pipe_tx_11_sigs + + + + + TX_12 + + + pipe_tx_12_sigs + + + + + TX_13 + + + pipe_tx_13_sigs + + + + + TX_14 + + + pipe_tx_14_sigs + + + + + TX_15 + + + pipe_tx_15_sigs + + + + + + + false + + + + + + pcie4_ext_pipe_ep + pcie4_ext_pipe_ep + PCIE4 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + RX_8 + + + pipe_tx_8_sigs + + + + + RX_9 + + + pipe_tx_9_sigs + + + + + RX_10 + + + pipe_tx_10_sigs + + + + + RX_11 + + + pipe_tx_11_sigs + + + + + RX_12 + + + pipe_tx_12_sigs + + + + + RX_13 + + + pipe_tx_13_sigs + + + + + RX_14 + + + pipe_tx_14_sigs + + + + + RX_15 + + + pipe_tx_15_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + 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rxprbssel + + + gt_rxprbssel + + + + + rxrecclkout + + + gt_rxrecclkout + + + + + rxresetdone + + + gt_rxresetdone + + + + + rxstatus + + + gt_rxstatus + + + + + rxsyncdone + + + gt_rxsyncdone + + + + + rxvalid + + + gt_rxvalid + + + + + txdlysresetdone + + + gt_txdlysresetdone + + + + + txelecidle + + + gt_txelecidle + + + + + txeq_ctrl + + + phy_txeq_ctrl + + + + + txeq_fsm + + + phy_txeq_fsm + + + + + txeq_preset + + + phy_txeq_preset + + + + + txinhibit + + + gt_txinhibit + + + + + txoutclk + + + gt_txoutclk + + + + + txoutclkfabric + + + gt_txoutclkfabric + + + + + txoutclkpcs + + + gt_txoutclkpcs + + + + + txpcsreset + + + gt_txpcsreset + + + + + txphaligndone + + + gt_txphaligndone + + + + + txphinitdone + + + gt_txphinitdone + + + + + txpmareset + + + gt_txpmareset + + + + + txpmaresetdone + + + gt_txpmaresetdone + + + + + txprbsforceerr + + + gt_txprbsforceerr + + + + + txprbssel + + + gt_txprbssel + + + + + txprogdivresetdone + + + gt_txprogdivresetdone + + + + + txresetdone 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gtrefclk00_in + + + + + gtrefclk01_in + + + gtrefclk01_in + + + + + gtrxreset_in + + + gtrxreset_in + + + + + gttxreset_in + + + gttxreset_in + + + + + gtwiz_reset_rx_done_in + + + gtwiz_reset_rx_done_in + + + + + gtwiz_reset_tx_done_in + + + gtwiz_reset_tx_done_in + + + + + gtwiz_userclk_rx_active_in + + + gtwiz_userclk_rx_active_in + + + + + gtwiz_userclk_tx_active_in + + + gtwiz_userclk_tx_active_in + + + + + loopback_in + + + loopback_in + + + + + pcieeqrxeqadaptdone_in + + + pcieeqrxeqadaptdone_in + + + + + pcierategen3_out + + + pcierategen3_out + + + + + pcierateidle_out + + + pcierateidle_out + + + + + pcierateqpll0_in + + + pcierateqpll0_in + + + + + pcierateqpll1_in + + + pcierateqpll1_in + + + + + pcierateqpllpd_out + + + pcierateqpllpd_out + + + + + pcierateqpllreset_out + + + pcierateqpllreset_out + + + + + pcierstidle_in + + + pcierstidle_in + + + + + pciersttxsyncstart_in + + + pciersttxsyncstart_in + + + + + pciesynctxsyncdone_out + + + pciesynctxsyncdone_out + + + + + pcieusergen3rdy_out + + + pcieusergen3rdy_out + + + + + pcieuserphystatusrst_out + + + pcieuserphystatusrst_out + + + + + pcieuserratedone_in + + + pcieuserratedone_in + + + + + pcieuserratestart_out + + + pcieuserratestart_out + + + + + phystatus_out + + + phystatus_out + + + + + qpll0freqlock_in + + + qpll0freqlock_in + + + + + qpll0lock_out + + + qpll0lock_out + + + + + qpll0outclk_out + + + qpll0outclk_out + + + + + qpll0outrefclk_out + + + qpll0outrefclk_out + + + + + qpll0pd_in + + + qpll0pd_in + + + + + qpll0reset_in + + + qpll0reset_in + + + + + qpll1freqlock_in + + + qpll1freqlock_in + + + + + qpll1lock_out + + + qpll1lock_out + + + + + qpll1outclk_out + + + qpll1outclk_out + + + + + qpll1outrefclk_out + + + qpll1outrefclk_out + + + + + qpll1pd_in + + + qpll1pd_in + + + + + qpll1reset_in + + + qpll1reset_in + + + + + rcalenb_in + + + rcalenb_in + + + + + resetovrd_in + + + resetovrd_in + + + + + rx8b10ben_in + + + rx8b10ben_in + + + + + rxbufreset_in + + + rxbufreset_in + + + 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rxdfetap3hold_in + + + + + rxdfetap4hold_in + + + rxdfetap4hold_in + + + + + rxdfetap5hold_in + + + rxdfetap5hold_in + + + + + rxdfetap6hold_in + + + rxdfetap6hold_in + + + + + rxdfetap7hold_in + + + rxdfetap7hold_in + + + + + rxdfetap8hold_in + + + rxdfetap8hold_in + + + + + rxdfetap9hold_in + + + rxdfetap9hold_in + + + + + rxdfetap10hold_in + + + rxdfetap10hold_in + + + + + rxdfetap11hold_in + + + rxdfetap11hold_in + + + + + rxdfetap12hold_in + + + rxdfetap12hold_in + + + + + rxdfetap13hold_in + + + rxdfetap13hold_in + + + + + rxdfetap14hold_in + + + rxdfetap14hold_in + + + + + rxdfetap15hold_in + + + rxdfetap15hold_in + + + + + rxdfeuthold_in + + + rxdfeuthold_in + + + + + rxdfevphold_in + + + rxdfevphold_in + + + + + rxdlysresetdone_out + + + rxdlysresetdone_out + + + + + rxelecidle_out + + + rxelecidle_out + + + + + rxlpmen_in + + + rxlpmen_in + + + + + rxlpmgchold_in + + + rxlpmgchold_in + + + + + rxlpmhfhold_in + + + rxlpmhfhold_in + + + + + rxlpmlfhold_in + + + rxlpmlfhold_in + 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TRUE + + + PF0_MSIX_CAP_NEXTPTR + Pf0 Msix Cap Nextptr + 0x70 + + + PF0_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + PF0_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + PF0_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + PF0_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + PF0_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + PF0_MSI_CAP_MULTIMSGCAP + Pf0 Msi Cap Multimsgcap + 0 + + + PF0_MSI_CAP_NEXTPTR + Pf0 Msi Cap Nextptr + 0x70 + + + PF0_PM_CAP_NEXTPTR + Pf0 Pm Cap Nextptr + 0x48 + + + PF0_PM_CAP_PMESUPPORT_D0 + Pf0 Pm Cap Pmesupport D0 + FALSE + + + PF0_PM_CAP_PMESUPPORT_D1 + Pf0 Pm Cap Pmesupport D1 + FALSE + + + PF0_PM_CAP_PMESUPPORT_D3HOT + Pf0 Pm Cap Pmesupport D3hot + FALSE + + + PF0_PM_CAP_SUPP_D1_STATE + Pf0 Pm Cap Supp D1 State + FALSE + + + PF0_REVISION_ID + Pf0 Revision Id + 0x00 + + + PF0_SRIOV_BAR0_APERTURE_SIZE + Pf0 Sriov Bar0 Aperture Size + 0x00 + + + PF0_SRIOV_BAR0_CONTROL + Pf0 Sriov Bar0 Control + 0x0 + + + PF0_SRIOV_BAR1_APERTURE_SIZE + Pf0 Sriov Bar1 Aperture Size + 0x00 + + + PF0_SRIOV_BAR1_CONTROL + Pf0 Sriov Bar1 Control + 0x0 + + + PF0_SRIOV_BAR2_APERTURE_SIZE + Pf0 Sriov Bar2 Aperture Size + 0x00 + + + PF0_SRIOV_BAR2_CONTROL + Pf0 Sriov Bar2 Control + 0x0 + + + PF0_SRIOV_BAR3_APERTURE_SIZE + Pf0 Sriov Bar3 Aperture Size + 0x00 + + + PF0_SRIOV_BAR3_CONTROL + Pf0 Sriov Bar3 Control + 0x0 + + + PF0_SRIOV_BAR4_APERTURE_SIZE + Pf0 Sriov Bar4 Aperture Size + 0x00 + + + PF0_SRIOV_BAR4_CONTROL + Pf0 Sriov Bar4 Control + 0x0 + + + PF0_SRIOV_BAR5_APERTURE_SIZE + Pf0 Sriov Bar5 Aperture Size + 0x00 + + + PF0_SRIOV_BAR5_CONTROL + Pf0 Sriov Bar5 Control + 0x0 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0x0000 + + + PF0_SRIOV_CAP_NEXTPTR + Pf0 Sriov Cap Nextptr + 0x000 + + + PF0_SRIOV_CAP_TOTAL_VF + Pf0 Sriov Cap Total Vf + 0x0000 + + + PF0_SRIOV_CAP_VER + Pf0 Sriov Cap Ver + 0x1 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 0x0000 + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0x0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 0x00000553 + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0x0000 + + + PF0_SUBSYSTEM_VENDOR_ID + Pf0 Subsystem Vendor Id + 0x10EE + + + PF0_SUBSYSTEM_ID + Pf0 Subsystem Id + 0x0007 + + + PF0_TPHR_CAP_ENABLE + Pf0 Tphr Cap Enable + FALSE + + + PF0_TPHR_CAP_NEXTPTR + Pf0 Tphr Cap Nextptr + 0x000 + + + PF0_TPHR_CAP_ST_MODE_SEL + Pf0 Tphr Cap St Mode Sel + 0x0 + + + PF0_TPHR_CAP_ST_TABLE_LOC + Pf0 Tphr Cap St Table Loc + 0x0 + + + PF0_TPHR_CAP_ST_TABLE_SIZE + Pf0 Tphr Cap St Table Size + 0x000 + + + PF0_TPHR_CAP_VER + Pf0 Tphr Cap Ver + 0x1 + + + PF1_TPHR_CAP_ST_MODE_SEL + Pf1 Tphr Cap St Mode Sel + 0x0 + + + PF2_TPHR_CAP_ST_MODE_SEL + Pf2 Tphr Cap St Mode Sel + 0x0 + + + PF3_TPHR_CAP_ST_MODE_SEL + Pf3 Tphr Cap St Mode Sel + 0x0 + + + PF0_TPHR_CAP_DEV_SPECIFIC_MODE + Pf0 Tphr Cap Dev Specific Mode + TRUE + + + PF0_TPHR_CAP_INT_VEC_MODE + Pf0 Tphr Cap Int Vec Mode + FALSE + + + PF0_SECONDARY_PCIE_CAP_NEXTPTR + Secondary Pcie Extended Capability Nextptr + 0x000 + + + MCAP_CAP_NEXTPTR + MCAP Cap Nextptr + 0x000 + + + PF0_VC_CAP_NEXTPTR + Pf0 Vc Cap Nextptr + 0x000 + + + SPARE_WORD1 + Secondary Pcie Extended Capability Nextptr + 0x00000000 + + + PF1_AER_CAP_NEXTPTR + Pf1 Aer Cap Nextptr + 0x000 + + + PF1_ARI_CAP_NEXTPTR + Pf1 Ari Cap Nextptr + 0x000 + + + PF1_BAR0_APERTURE_SIZE + Pf1 Bar0 Aperture Size + 0x009 + + + PF1_BAR0_CONTROL + Pf1 Bar0 Control + 0x4 + + + PF1_BAR1_APERTURE_SIZE + Pf1 Bar1 Aperture Size + 0x000 + + + PF1_BAR1_CONTROL + Pf1 Bar1 Control + 0x0 + + + PF1_BAR2_APERTURE_SIZE + Pf1 Bar2 Aperture Size + 0x000 + + + PF1_BAR2_CONTROL + Pf1 Bar2 Control + 0x0 + + + PF1_BAR3_APERTURE_SIZE + Pf1 Bar3 Aperture Size + 0x000 + + + PF1_BAR3_CONTROL + Pf1 Bar3 Control + 0x0 + + + PF1_BAR4_APERTURE_SIZE + Pf1 Bar4 Aperture Size + 0x000 + + + PF1_BAR4_CONTROL + Pf1 Bar4 Control + 0x0 + + + PF1_BAR5_APERTURE_SIZE + Pf1 Bar5 Aperture Size + 0x000 + + + PF1_BAR5_CONTROL + Pf1 Bar5 Control + 0x0 + + + PF1_CAPABILITY_POINTER + Pf1 Capability Pointer + 0x40 + + + PF1_CLASS_CODE + Pf1 Class Code + 0x058000 + + + PF1_DEVICE_ID + Pf1 Device Id + 0x9011 + + + PF1_DEV_CAP_MAX_PAYLOAD_SIZE + Pf1 Dev Cap Max Payload Size + 0x3 + + + PF1_DSN_CAP_NEXTPTR + Pf1 Dsn Cap Nextptr + 0x000 + + + PF1_EXPANSION_ROM_APERTURE_SIZE + Pf1 Expansion Rom Aperture Size + 0x000 + + + PF1_EXPANSION_ROM_ENABLE + Pf1 Expansion Rom Enable + FALSE + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + 0x0 + + + PF1_MSIX_CAP_NEXTPTR + Pf1 Msix Cap Nextptr + 0x70 + + + PF1_MSIX_CAP_PBA_BIR + Pf1 Msix Cap Pba Bir + 0 + + + PF1_MSIX_CAP_PBA_OFFSET + Pf1 Msix Cap Pba Offset + 0x00000000 + + + PF1_MSIX_CAP_TABLE_BIR + Pf1 Msix Cap Table Bir + 0 + + + PF1_MSIX_CAP_TABLE_OFFSET + Pf1 Msix Cap Table Offset + 0x00000000 + + + PF1_MSIX_CAP_TABLE_SIZE + Pf1 Msix Cap Table Size + 0x000 + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 0 + + + PF1_MSI_CAP_NEXTPTR + Pf1 Msi Cap Nextptr + 0x70 + + + PF1_PM_CAP_NEXTPTR + Pf1 Pm Cap Nextptr + 0x70 + + + PF1_REVISION_ID + Pf1 Revision Id + 0x00 + + + PF1_SRIOV_BAR0_APERTURE_SIZE + Pf1 Sriov Bar0 Aperture Size + 0x00 + + + PF1_SRIOV_BAR0_CONTROL + Pf1 Sriov Bar0 Control + 0x0 + + + PF1_SRIOV_BAR1_APERTURE_SIZE + Pf1 Sriov Bar1 Aperture Size + 0x00 + + + PF1_SRIOV_BAR1_CONTROL + Pf1 Sriov Bar1 Control + 0x0 + + + PF1_SRIOV_BAR2_APERTURE_SIZE + Pf1 Sriov Bar2 Aperture Size + 0x00 + + + PF1_SRIOV_BAR2_CONTROL + Pf1 Sriov Bar2 Control + 0x0 + + + PF1_SRIOV_BAR3_APERTURE_SIZE + Pf1 Sriov Bar3 Aperture Size + 0x00 + + + PF1_SRIOV_BAR3_CONTROL + Pf1 Sriov Bar3 Control + 0x0 + + + PF1_SRIOV_BAR4_APERTURE_SIZE + Pf1 Sriov Bar4 Aperture Size + 0x00 + + + PF1_SRIOV_BAR4_CONTROL + Pf1 Sriov Bar4 Control + 0x0 + + + PF1_SRIOV_BAR5_APERTURE_SIZE + Pf1 Sriov Bar5 Aperture Size + 0x00 + + + PF1_SRIOV_BAR5_CONTROL + Pf1 Sriov Bar5 Control + 0x0 + + + PF1_SRIOV_CAP_INITIAL_VF + Pf1 Sriov Cap Initial Vf + 0x0000 + + + PF1_SRIOV_CAP_NEXTPTR + Pf1 Sriov Cap Nextptr + 0x000 + + + PF1_SRIOV_CAP_TOTAL_VF + Pf1 Sriov Cap Total Vf + 0x0000 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 0x1 + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + 0x0000 + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0x0001 + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 0x00000553 + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0x0000 + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0x0007 + + + PF1_TPHR_CAP_NEXTPTR + Pf1 Tphr Cap Nextptr + 0x000 + + + PF2_AER_CAP_NEXTPTR + Pf2 Aer Cap Nextptr + 0x000 + + + PF2_ARI_CAP_NEXTPTR + Pf2 Ari Cap Nextptr + 0x000 + + + PF2_BAR0_APERTURE_SIZE + Pf2 Bar0 Aperture Size + 0x009 + + + PF2_BAR0_CONTROL + Pf2 Bar0 Control + 0x4 + + + PF2_BAR1_APERTURE_SIZE + Pf2 Bar1 Aperture Size + 0x000 + + + PF2_BAR1_CONTROL + Pf2 Bar1 Control + 0x0 + + + PF2_BAR2_APERTURE_SIZE + Pf2 Bar2 Aperture Size + 0x000 + + + PF2_BAR2_CONTROL + Pf2 Bar2 Control + 0x0 + + + PF2_BAR3_APERTURE_SIZE + Pf2 Bar3 Aperture Size + 0x000 + + + PF2_BAR3_CONTROL + Pf2 Bar3 Control + 0x0 + + + PF2_BAR4_APERTURE_SIZE + Pf2 Bar4 Aperture Size + 0x000 + + + PF2_BAR4_CONTROL + Pf2 Bar4 Control + 0x0 + + + PF2_BAR5_APERTURE_SIZE + Pf2 Bar5 Aperture Size + 0x000 + + + PF2_BAR5_CONTROL + Pf2 Bar5 Control + 0x0 + + + PF2_CAPABILITY_POINTER + Pf2 Capability Pointer + 0x40 + + + PF2_CLASS_CODE + Pf2 Class Code + 0x058000 + + + PF2_DEVICE_ID + Pf2 Device Id + 0x9438 + + + PF2_DEV_CAP_MAX_PAYLOAD_SIZE + Pf2 Dev Cap Max Payload Size + 0x3 + + + PF2_DSN_CAP_NEXTPTR + Pf2 Dsn Cap Nextptr + 0x000 + + + PF2_EXPANSION_ROM_APERTURE_SIZE + Pf2 Expansion Rom Aperture Size + 0x000 + + + PF2_EXPANSION_ROM_ENABLE + Pf2 Expansion Rom Enable + FALSE + + + PF2_INTERRUPT_PIN + Pf2 Interrupt Pin + 0x0 + + + PF2_MSIX_CAP_NEXTPTR + Pf2 Msix Cap Nextptr + 0x70 + + + PF2_MSIX_CAP_PBA_BIR + Pf2 Msix Cap Pba Bir + 0 + + + PF2_MSIX_CAP_PBA_OFFSET + Pf2 Msix Cap Pba Offset + 0x00000000 + + + PF2_MSIX_CAP_TABLE_BIR + Pf2 Msix Cap Table Bir + 0 + + + PF2_MSIX_CAP_TABLE_OFFSET + Pf2 Msix Cap Table Offset + 0x00000000 + + + PF2_MSIX_CAP_TABLE_SIZE + Pf2 Msix Cap Table Size + 0x000 + + + PF2_MSI_CAP_MULTIMSGCAP + Pf2 Msi Cap Multimsgcap + 0 + + + PF2_MSI_CAP_NEXTPTR + Pf2 Msi Cap Nextptr + 0x70 + + + PF2_PM_CAP_NEXTPTR + Pf2 Pm Cap Nextptr + 0x70 + + + PF2_REVISION_ID + Pf2 Revision Id + 0x00 + + + PF2_SRIOV_BAR0_APERTURE_SIZE + Pf2 Sriov Bar0 Aperture Size + 0x00 + + + PF2_SRIOV_BAR0_CONTROL + Pf2 Sriov Bar0 Control + 0x0 + + + PF2_SRIOV_BAR1_APERTURE_SIZE + Pf2 Sriov Bar1 Aperture Size + 0x00 + + + PF2_SRIOV_BAR1_CONTROL + Pf2 Sriov Bar1 Control + 0x0 + + + PF2_SRIOV_BAR2_APERTURE_SIZE + Pf2 Sriov Bar2 Aperture Size + 0x00 + + + PF2_SRIOV_BAR2_CONTROL + Pf2 Sriov Bar2 Control + 0x0 + + + PF2_SRIOV_BAR3_APERTURE_SIZE + Pf2 Sriov Bar3 Aperture Size + 0x00 + + + PF2_SRIOV_BAR3_CONTROL + Pf2 Sriov Bar3 Control + 0x0 + + + PF2_SRIOV_BAR4_APERTURE_SIZE + Pf2 Sriov Bar4 Aperture Size + 0x00 + + + PF2_SRIOV_BAR4_CONTROL + Pf2 Sriov Bar4 Control + 0x0 + + + PF2_SRIOV_BAR5_APERTURE_SIZE + Pf2 Sriov Bar5 Aperture Size + 0x00 + + + PF2_SRIOV_BAR5_CONTROL + Pf2 Sriov Bar5 Control + 0x0 + + + PF2_SRIOV_CAP_INITIAL_VF + Pf2 Sriov Cap Initial Vf + 0x0000 + + + PF2_SRIOV_CAP_NEXTPTR + Pf2 Sriov Cap Nextptr + 0x000 + + + PF2_SRIOV_CAP_TOTAL_VF + Pf2 Sriov Cap Total Vf + 0x0000 + + + PF2_SRIOV_CAP_VER + Pf2 Sriov Cap Ver + 0x1 + + + PF2_SRIOV_FIRST_VF_OFFSET + Pf2 Sriov First Vf Offset + 0x0000 + + + PF2_SRIOV_FUNC_DEP_LINK + Pf2 Sriov Func Dep Link + 0x0002 + + + PF2_SRIOV_SUPPORTED_PAGE_SIZE + Pf2 Sriov Supported Page Size + 0x00000553 + + + PF2_SRIOV_VF_DEVICE_ID + Pf2 Sriov Vf Device Id + 0x0000 + + + PF2_SUBSYSTEM_ID + Pf2 Subsystem Id + 0x0007 + + + PF2_TPHR_CAP_NEXTPTR + Pf2 Tphr Cap Nextptr + 0x000 + + + PF3_AER_CAP_NEXTPTR + Pf3 Aer Cap Nextptr + 0x000 + + + PF3_ARI_CAP_NEXTPTR + Pf3 Ari Cap Nextptr + 0x000 + + + PF3_BAR0_APERTURE_SIZE + Pf3 Bar0 Aperture Size + 0x009 + + + PF3_BAR0_CONTROL + Pf3 Bar0 Control + 0x4 + + + PF3_BAR1_APERTURE_SIZE + Pf3 Bar1 Aperture Size + 0x000 + + + PF3_BAR1_CONTROL + Pf3 Bar1 Control + 0x0 + + + PF3_BAR2_APERTURE_SIZE + Pf3 Bar2 Aperture Size + 0x000 + + + PF3_BAR2_CONTROL + Pf3 Bar2 Control + 0x0 + + + PF3_BAR3_APERTURE_SIZE + Pf3 Bar3 Aperture Size + 0x000 + + + PF3_BAR3_CONTROL + Pf3 Bar3 Control + 0x0 + + + PF3_BAR4_APERTURE_SIZE + Pf3 Bar4 Aperture Size + 0x000 + + + PF3_BAR4_CONTROL + Pf3 Bar4 Control + 0x0 + + + PF3_BAR5_APERTURE_SIZE + Pf3 Bar5 Aperture Size + 0x000 + + + PF3_BAR5_CONTROL + Pf3 Bar5 Control + 0x0 + + + PF3_CAPABILITY_POINTER + Pf3 Capability Pointer + 0x40 + + + PF3_CLASS_CODE + Pf3 Class Code + 0x058000 + + + PF3_DEVICE_ID + Pf3 Device Id + 0x9638 + + + PF3_DEV_CAP_MAX_PAYLOAD_SIZE + Pf3 Dev Cap Max Payload Size + 0x3 + + + PF3_DSN_CAP_NEXTPTR + Pf3 Dsn Cap Nextptr + 0x000 + + + PF3_EXPANSION_ROM_APERTURE_SIZE + Pf3 Expansion Rom Aperture Size + 0x000 + + + PF3_EXPANSION_ROM_ENABLE + Pf3 Expansion Rom Enable + FALSE + + + PF3_INTERRUPT_PIN + Pf3 Interrupt Pin + 0x0 + + + PF3_MSIX_CAP_NEXTPTR + Pf3 Msix Cap Nextptr + 0x70 + + + PF3_MSIX_CAP_PBA_BIR + Pf3 Msix Cap Pba Bir + 0 + + + PF3_MSIX_CAP_PBA_OFFSET + Pf3 Msix Cap Pba Offset + 0x00000000 + + + PF3_MSIX_CAP_TABLE_BIR + Pf3 Msix Cap Table Bir + 0 + + + PF3_MSIX_CAP_TABLE_OFFSET + Pf3 Msix Cap Table Offset + 0x00000000 + + + PF3_MSIX_CAP_TABLE_SIZE + Pf3 Msix Cap Table Size + 0x000 + + + PF3_MSI_CAP_MULTIMSGCAP + Pf3 Msi Cap Multimsgcap + 0 + + + PF3_MSI_CAP_NEXTPTR + Pf3 Msi Cap Nextptr + 0x70 + + + PF3_PM_CAP_NEXTPTR + Pf3 Pm Cap Nextptr + 0x70 + + + PF3_REVISION_ID + Pf3 Revision Id + 0x00 + + + PF3_SRIOV_BAR0_APERTURE_SIZE + Pf3 Sriov Bar0 Aperture Size + 0x00 + + + PF3_SRIOV_BAR0_CONTROL + Pf3 Sriov Bar0 Control + 0x0 + + + PF3_SRIOV_BAR1_APERTURE_SIZE + Pf3 Sriov Bar1 Aperture Size + 0x00 + + + PF3_SRIOV_BAR1_CONTROL + Pf3 Sriov Bar1 Control + 0x0 + + + PF3_SRIOV_BAR2_APERTURE_SIZE + Pf3 Sriov Bar2 Aperture Size + 0x00 + + + PF3_SRIOV_BAR2_CONTROL + Pf3 Sriov Bar2 Control + 0x0 + + + PF3_SRIOV_BAR3_APERTURE_SIZE + Pf3 Sriov Bar3 Aperture Size + 0x00 + + + PF3_SRIOV_BAR3_CONTROL + Pf3 Sriov Bar3 Control + 0x0 + + + PF3_SRIOV_BAR4_APERTURE_SIZE + Pf3 Sriov Bar4 Aperture Size + 0x00 + + + PF3_SRIOV_BAR4_CONTROL + Pf3 Sriov Bar4 Control + 0x0 + + + PF3_SRIOV_BAR5_APERTURE_SIZE + Pf3 Sriov Bar5 Aperture Size + 0x00 + + + PF3_SRIOV_BAR5_CONTROL + Pf3 Sriov Bar5 Control + 0x0 + + + PF3_SRIOV_CAP_INITIAL_VF + Pf3 Sriov Cap Initial Vf + 0x0000 + + + PF3_SRIOV_CAP_NEXTPTR + Pf3 Sriov Cap Nextptr + 0x000 + + + PF3_SRIOV_CAP_TOTAL_VF + Pf3 Sriov Cap Total Vf + 0x0000 + + + PF3_SRIOV_CAP_VER + Pf3 Sriov Cap Ver + 0x1 + + + PF3_SRIOV_FIRST_VF_OFFSET + Pf3 Sriov First Vf Offset + 0x0000 + + + PF3_SRIOV_FUNC_DEP_LINK + Pf3 Sriov Func Dep Link + 0x0003 + + + PF3_SRIOV_SUPPORTED_PAGE_SIZE + Pf3 Sriov Supported Page Size + 0x00000553 + + + PF3_SRIOV_VF_DEVICE_ID + Pf3 Sriov Vf Device Id + 0x0000 + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0x0007 + + + PF3_TPHR_CAP_NEXTPTR + Pf3 Tphr Cap Nextptr + 0x000 + + + PL_UPSTREAM_FACING + Pl Upstream Facing + TRUE + + + PL_DISABLE_LANE_REVERSAL + Pl Disable Lane Reversal + TRUE + + + PF0_MSI_CAP_PERVECMASKCAP + en pf0 msi per vec masking + FALSE + + + PF1_MSI_CAP_PERVECMASKCAP + en pf1 msi per vec masking + FALSE + + + PF2_MSI_CAP_PERVECMASKCAP + en pf2 msi per vec masking + FALSE + + + PF3_MSI_CAP_PERVECMASKCAP + en pf3 msi per vec masking + FALSE + + + SRIOV_CAP_ENABLE + Sriov Cap Enable + 0x0 + + + TL_CREDITS_CD + Tl Credits Cd + 0x000 + + + TL_CREDITS_CH + Tl Credits Ch + 0x00 + + + TL_CREDITS_NPD + Tl Credits Npd + 0x004 + + + TL_CREDITS_NPH + Tl Credits Nph + 0x20 + + + TL_CREDITS_PD + Tl Credits Pd + 0x3E0 + + + TL_CREDITS_PH + Tl Credits Ph + 0x20 + + + EXTENDED_CFG_EXTEND_INTERFACE_ENABLE + Tl Extended Cfg Extend Interface Enable + FALSE + + + EXT_XVC_VSEC_ENABLE + Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design + FALSE + + + LEGACY_CFG_EXTEND_INTERFACE_ENABLE + FALSE + + + ACS_EXT_CAP_ENABLE + FALSE + + + ACS_CAP_NEXTPTR + 0x000 + + + TL_LEGACY_MODE_ENABLE + Tl Legacy Mode Enable + FALSE + + + TL_PF_ENABLE_REG + 0 + + + VF0_CAPABILITY_POINTER + Vf0 Capability Pointer + 0x70 + + + TL_COMPLETION_RAM_SIZE + Completion Space + 0x2 + + + gen_x0y0_xdc + Generate X0Y0 XDC + 0 + + + gen_x0y1_xdc + Generate X0Y1 XDC + 0 + + + gen_x0y2_xdc + Generate X0Y2 XDC + 0 + + + gen_x0y3_xdc + Generate X0Y3 XDC + 0 + + + gen_x0y4_xdc + Generate X0Y4 XDC + 0 + + + gen_x0y5_xdc + Generate X0Y5 XDC + 0 + + + gen_x1y0_xdc + Generate X1Y0 XDC + 0 + + + gen_x1y1_xdc + Generate X1Y1 XDC + 0 + + + gen_x1y2_xdc + Generate X1Y2 XDC + 1 + + + gen_x1y3_xdc + Generate X1Y3 XDC + 0 + + + gen_x1y4_xdc + Generate X1Y4 XDC + 0 + + + gen_x1y5_xdc + Generate X1Y5 XDC + 0 + + + xlnx_ref_board + Xlnx Ref Board + 15 + + + pcie_blk_locn + Pcie Blk Locn + 8 + + + PIPE_SIM + FALSE + + + AXISTEN_IF_ENABLE_CLIENT_TAG + TRUE + + + PCIE_FAST_CONFIG + PCIE FAST CONFIG + NONE + + + EXT_STARTUP_PRIMITIVE + EXT STARTUP PRIMITIVE + FALSE + + + PL_INTERFACE + PL INTERFACE + FALSE + + + PCIE_CONFIGURATION + PCIE CONFIGURATION + FALSE + + + CFG_STATUS_IF + TRUE + + + TX_FC_IF + TRUE + + + CFG_EXT_IF + FALSE + + + CFG_FC_IF + TRUE + + + PER_FUNC_STATUS_IF + TRUE + + + CFG_MGMT_IF + TRUE + + + RCV_MSG_IF + TRUE + + + CFG_TX_MSG_IF + TRUE + + + CFG_CTL_IF + TRUE + + + CFG_PM_IF + TRUE + + + PCIE_ID_IF + FALSE + + + MSI_EN + TRUE + + + MSIX_EN + FALSE + + + PCIE4_DRP + FALSE + + + DIS_GT_WIZARD + FALSE + + + BMD_PIO_MODE + FALSE + + + SRIOV_EXD_MODE + FALSE + + + DBG_CHECKER + FALSE + + + ENABLE_IBERT + FALSE + + + GEN4_EIEOS_0S7 + TRUE + + + CTRL_SKIP_MASK + TRUE + + + ENABLE_JTAG_DBG + FALSE + + + ENABLE_LTSSM_DBG + FALSE + + + BROADCOM_SBR_WA + FALSE + + + TWO_PORT_SWITCH + FALSE + + + TWO_PORT_CONFIG + X8G3 + + + TRANSCEIVER_CTRL_STATUS_PORTS + FALSE + + + SHARED_LOGIC + 1 + + + GTWIZ_IN_CORE + 1 + + + GTCOM_IN_CORE + 2 + + + AXISTEN_IF_RX_PARITY_EN + FALSE + + + AXISTEN_IF_TX_PARITY_EN + FALSE + + + AXISTEN_IF_MSIX_RX_PARITY_EN + FALSE + + + LL_TX_TLP_PARITY_CHK + FALSE + + + LL_RX_TLP_PARITY_GEN + FALSE + + + TL2CFG_IF_PARITY_CHK + FALSE + + + AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE + FALSE + + + DEDICATE_PERST + FALSE + + + SYS_RESET_POLARITY + 0 + + + MCAP_ENABLEMENT + NONE + + + MCAP_FPGA_BITSTREAM_VERSION + MCAP Bitstream Version Register Value + 0x00000000 + + + EXT_CH_GT_DRP + FALSE + + + EN_GT_SELECTION + FALSE + + + SELECT_QUAD + GTY_Quad_227 + + + silicon_revision + Silicon Revision + Beta + + + DEV_PORT_TYPE + 0 + + + VFG0_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG0_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG0_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG0_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG0_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + VFG1_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG1_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG1_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG1_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG1_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + VFG2_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG2_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG2_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG2_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG2_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + VFG3_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG3_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG3_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG3_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG3_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + EN_PARITY + FALSE + + + INS_LOSS_PROFILE + ADD-IN_CARD + + + MSI_X_OPTIONS + None + + + COMPLETER_MODEL + FALSE + + + DBG_DESCRAMBLE_EN + FALSE + + + MSI_INT + MSI Ints + 32 + + + VU9P_BOARD + FALSE + + + PHY_LP_TXPRESET + 4 + + + IS_BOARD_PROJECT + Is Board Flow Enabled + 1 + + + GT_DRP_CLK_SRC + GT DRP Clk Source + 0 + + + FREE_RUN_FREQ + Free Run Freq + 1 + + + PM_ENABLE_L23_ENTRY + FALSE + + + AWS_MODE_VALUE + aws mode value + 0 + + + MULT_PF_DES + TRUE + + + EXT_SYS_CLK_BUFG + FALSE + + + AXISTEN_IF_ENABLE_MSG_ROUTE + 0x20000 + + + AXISTEN_IF_ENABLE_RX_MSG_INTFC + FALSE + + + ENABLE_MORE + FALSE + + + DISABLE_BRAM_PIPELINE + FALSE + + + DISABLE_EQ_SYNCHRONIZER + FALSE + + + ENABLE_AUTO_RXEQ + FALSE + + + THREE_PORT_SWITCH + FALSE + + + ENABLE_MULTIPF_AER + multi pf aer fix + FALSE + + + ENABLE_MSIX_32VEC + FALSE + + + ENABLE_CLKMUX + CLK-MUXING during perst + FALSE + + + RBAR_ENABLE + FALSE + + + PF0_RBAR_CAP_BAR0_UPPER + PF0 Resizable BAR0 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR0_LOWER + PF0 Resizable BAR0 Capability lower 32 bits + 0x0000fff0 + + + PF0_RBAR_CAP_BAR1_UPPER + PF0 Resizable BAR1 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR1_LOWER + PF0 Resizable BAR1 Capability lower 32 bits + 0x00000000 + + + PF0_RBAR_CAP_BAR2_UPPER + PF0 Resizable BAR2 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR2_LOWER + PF0 Resizable BAR2 Capability lower 32 bits + 0x00000000 + + + PF0_RBAR_CAP_BAR3_UPPER + PF0 Resizable BAR3 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR3_LOWER + PF0 Resizable BAR3 Capability lower 32 bits + 0x00000000 + + + PF0_RBAR_CAP_BAR4_UPPER + PF0 Resizable BAR4 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR4_LOWER + PF0 Resizable BAR4 Capability lower 32 bits + 0x00000000 + + + PF0_RBAR_CAP_BAR5_UPPER + PF0 Resizable BAR5 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR5_LOWER + PF0 Resizable BAR5 Capability lower 32 bits + 0x00000000 + + + PF1_RBAR_CAP_BAR0_UPPER + PF1 Resizable BAR0 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR0_LOWER + PF1 Resizable BAR0 Capability lower 32 bits + 0x0000fff0 + + + PF1_RBAR_CAP_BAR1_UPPER + PF1 Resizable BAR1 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR1_LOWER + PF1 Resizable BAR1 Capability lower 32 bits + 0x00000000 + + + PF1_RBAR_CAP_BAR2_UPPER + PF1 Resizable BAR2 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR2_LOWER + PF1 Resizable BAR2 Capability lower 32 bits + 0x00000000 + + + PF1_RBAR_CAP_BAR3_UPPER + PF1 Resizable BAR3 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR3_LOWER + PF1 Resizable BAR3 Capability lower 32 bits + 0x00000000 + + + PF1_RBAR_CAP_BAR4_UPPER + PF1 Resizable BAR4 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR4_LOWER + PF1 Resizable BAR4 Capability lower 32 bits + 0x00000000 + + + PF1_RBAR_CAP_BAR5_UPPER + PF1 Resizable BAR5 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR5_LOWER + PF1 Resizable BAR5 Capability lower 32 bits + 0x00000000 + + + PF2_RBAR_CAP_BAR0_UPPER + PF2 Resizable BAR0 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR0_LOWER + PF2 Resizable BAR0 Capability lower 32 bits + 0x0000fff0 + + + PF2_RBAR_CAP_BAR1_UPPER + PF2 Resizable BAR1 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR1_LOWER + PF2 Resizable BAR1 Capability lower 32 bits + 0x00000000 + + + PF2_RBAR_CAP_BAR2_UPPER + PF2 Resizable BAR2 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR2_LOWER + PF2 Resizable BAR2 Capability lower 32 bits + 0x00000000 + + + PF2_RBAR_CAP_BAR3_UPPER + PF2 Resizable BAR3 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR3_LOWER + PF2 Resizable BAR3 Capability lower 32 bits + 0x00000000 + + + PF2_RBAR_CAP_BAR4_UPPER + PF2 Resizable BAR4 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR4_LOWER + PF2 Resizable BAR4 Capability lower 32 bits + 0x00000000 + + + PF2_RBAR_CAP_BAR5_UPPER + PF2 Resizable BAR5 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR5_LOWER + PF2 Resizable BAR5 Capability lower 32 bits + 0x00000000 + + + PF3_RBAR_CAP_BAR0_UPPER + PF3 Resizable BAR0 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR0_LOWER + PF3 Resizable BAR0 Capability lower 32 bits + 0x0000fff0 + + + PF3_RBAR_CAP_BAR1_UPPER + PF3 Resizable BAR1 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR1_LOWER + PF3 Resizable BAR1 Capability lower 32 bits + 0x00000000 + + + PF3_RBAR_CAP_BAR2_UPPER + PF3 Resizable BAR2 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR2_LOWER + PF3 Resizable BAR2 Capability lower 32 bits + 0x00000000 + + + PF3_RBAR_CAP_BAR3_UPPER + PF3 Resizable BAR3 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR3_LOWER + PF3 Resizable BAR3 Capability lower 32 bits + 0x00000000 + + + PF3_RBAR_CAP_BAR4_UPPER + PF3 Resizable BAR4 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR4_LOWER + PF3 Resizable BAR4 Capability lower 32 bits + 0x00000000 + + + PF3_RBAR_CAP_BAR5_UPPER + PF3 Resizable BAR5 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR5_LOWER + PF3 Resizable BAR5 Capability lower 32 bits + 0x00000000 + + + RBAR_CAP_NEXTPTR + 0x000 + + + PF0_RBAR_NUM_BAR + 0x1 + + + PF1_RBAR_NUM_BAR + 0x1 + + + PF2_RBAR_NUM_BAR + 0x1 + + + PF3_RBAR_NUM_BAR + 0x1 + + + PF0_RBAR_BAR_INDEX_0 + 0x0 + + + PF0_RBAR_BAR_INDEX_1 + 0x7 + + + PF0_RBAR_BAR_INDEX_2 + 0x7 + + + PF0_RBAR_BAR_INDEX_3 + 0x7 + + + PF0_RBAR_BAR_INDEX_4 + 0x7 + + + PF0_RBAR_BAR_INDEX_5 + 0x7 + + + PF1_RBAR_BAR_INDEX_0 + 0x0 + + + PF1_RBAR_BAR_INDEX_1 + 0x7 + + + PF1_RBAR_BAR_INDEX_2 + 0x7 + + + PF1_RBAR_BAR_INDEX_3 + 0x7 + + + PF1_RBAR_BAR_INDEX_4 + 0x7 + + + PF1_RBAR_BAR_INDEX_5 + 0x7 + + + PF2_RBAR_BAR_INDEX_0 + 0x0 + + + PF2_RBAR_BAR_INDEX_1 + 0x7 + + + PF2_RBAR_BAR_INDEX_2 + 0x7 + + + PF2_RBAR_BAR_INDEX_3 + 0x7 + + + PF2_RBAR_BAR_INDEX_4 + 0x7 + + + PF2_RBAR_BAR_INDEX_5 + 0x7 + + + PF3_RBAR_BAR_INDEX_0 + 0x0 + + + PF3_RBAR_BAR_INDEX_1 + 0x7 + + + PF3_RBAR_BAR_INDEX_2 + 0x7 + + + PF3_RBAR_BAR_INDEX_3 + 0x7 + + + PF3_RBAR_BAR_INDEX_4 + 0x7 + + + PF3_RBAR_BAR_INDEX_5 + 0x7 + + + USE_STANDARD_INTERFACES + Use standard interfaces + FALSE + + + DMA_2RP + FALSE + + + SRIOV_ACTIVE_VFS + 252 + + + MASTER_GT_QUAD_INX + 3 + + + MASTER_GT_CONTAINER + 32 + + + QDMA_TPH_MSIX_BRAMS_DIS + FALSE + + + + + + choice_list_002f5e3f + PCI_Express_Endpoint_device + Legacy_PCI_Express_Endpoint_device + Root_Port_of_PCI_Express_Root_Complex + + + choice_list_0cee66fe + 1 + 4 + 64 + + + choice_list_0f93492c + Chip-to-Chip + Add-in_Card + Backplane + + + choice_list_165ed04b + 64 + + + choice_list_1e9fb93b + X1 + X2 + X4 + X8 + X16 + + + choice_list_24b724fb + Basic + Advanced + + + choice_list_34d65ff4 + 128 + + + choice_list_35d06715 + 2 + + + choice_list_38306dd1 + SOFT + HARD + + + choice_list_3ca2cbc7 + BAR_0 + + + choice_list_3d9ff82c + 500 + 250 + + + choice_list_52d29139 + Bytes + Kilobytes + Megabytes + Gigabytes + + + choice_list_574f38f3 + 2.5_GT/s + 5.0_GT/s + 8.0_GT/s + + + choice_list_589df8e9 + RAM + Other_memory_controller + Flash + + + choice_list_5e2921cd + Kilobytes + + + choice_list_5e45706a + 1_vector + 2_vectors + 4_vectors + 8_vectors + 16_vectors + 32_vectors + + + choice_list_61bc5fcf + 0 + 4 + 7 + 8 + 12 + 16 + 20 + 24 + 28 + 32 + 36 + 40 + 44 + 48 + 52 + 56 + 60 + 64 + 68 + 72 + 76 + 80 + 84 + 88 + 92 + 96 + 100 + 104 + 108 + 112 + 116 + 120 + 124 + 128 + 132 + 136 + 140 + 144 + 148 + 152 + 156 + 160 + 164 + 168 + 172 + 176 + 180 + 184 + 188 + 192 + 196 + 200 + 204 + 208 + 212 + 216 + 220 + 224 + 228 + 232 + 236 + 240 + 244 + 248 + 252 + + + choice_list_6b979ebc + 250 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_6eff49bd + ACTIVE_LOW + ACTIVE_HIGH + + + choice_list_75aee2a8 + X8G3 + X16G3 + + + choice_list_796ca877 + sample_smoke_test0 + sample_smoke_test1 + legacy_smoke_test + msi_smoke_test + msix_smoke_test + pio_writeReadBack_test0 + + + choice_list_7a7dde49 + true + false + + + choice_list_7d45a81a + 128_bytes + 256_bytes + 512_bytes + 1024_bytes + + + choice_list_8061eec5 + None + Tandem_PROM + Tandem_PCIe + Tandem_PCIe_with_Field_Updates + DFX_over_PCIe + + + choice_list_81a1639d + DWORD_Aligned + Address_Aligned + + + choice_list_847d868a + 1 + 2 + 3 + 4 + 5 + 6 + + + choice_list_88156f2e + QPLL1 + QPLL0 + + + choice_list_8b5e4915 + 4 + 5 + + + choice_list_8eea463a + X1Y2 + X1Y4 + + + choice_list_914704bd + 100_MHz + 125_MHz + + + choice_list_97bc19ec + 256_bit + + + choice_list_9aec9108 + Internal + External + + + choice_list_a30da595 + Custom + pcie_perstn + + + choice_list_a44ca313 + Custom + pci_express_x1 + pci_express_x16 + pci_express_x2 + pci_express_x4 + pci_express_x8 + + + choice_list_aa031417 + 1 + 2 + 3 + 4 + + + choice_list_abc20383 + GTY_Quad_227 + GTY_Quad_226 + GTY_Quad_225 + GTY_Quad_224 + + + choice_list_bdd7203f + True + False + + + choice_list_bea500ca + None + MSI-X_External + MSI-X_Internal + MSI-X_AXI4-Stream + + + choice_list_c15e8c67 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_c3d223d9 + Memory + + + choice_list_ca005b72 + No_ASPM + L1_Supported + + + choice_list_d123c74c + Bytes + Kilobytes + Megabytes + + + choice_list_d53faa96 + 100_MHz + 125_MHz + 250_MHz + + + choice_list_d85ad257 + 0 + + + choice_list_d992adf6 + Generic_XT_compatible_serial_controller + 16450_compatible_serial_controller + Parallel_port + IEEE_1284_controller + Multiport_serial_controller + 16650_compatible_serial_controller + IEEE_1284_target_device + Hayes_compatible_modem_with_16550_compatible_interface + ECP_1.X_compliant_parallel_port + 16850_compatible_serial_controller + Hayes_compatible_modem_with_16750_compatible_interface + Smart_Card + Bi_directional_parallel_port + Other_communications_device + GPIB(IEEE_488.1/2)_controller + 16550_compatible_serial_controller + Hayes_compatible_modem_with_16450_compatible_interface + 16750_compatible_serial_controller + Hayes_compatible_modem_with_16650_compatible_interface + Generic_modem + 16950_compatible_serial_controller + + + choice_list_dff1a45d + Wireless_controller + Satellite_communication_controllers + Data_acquisition_and_signal_processing_controllers + Processing_accelerators + Intelligent_I/O_controllers + Docking_stations + Device_was_built_before_Class_Code_definitions_were_finalized + Memory_controller + Simple_communication_controllers + Serial_bus_controllers + Encryption/Decryption_controllers + Display_controller + Multimedia_device + Input_devices + Mass_storage_controller + Processors + Device_does_not_fit_in_any_defined_classes + Bridge_device + Network_controller + Base_system_peripherals + + + choice_list_e9cf6440 + Disabled + 32bit_Enabled + 64bit_Enabled + + + choice_list_ec64e624 + N/A + + + choice_list_ecc4b9b7 + AU200 + + + choice_list_f1174048 + NONE + INTA + INTB + INTC + INTD + + + choice_list_f149a468 + Extreme + Good + + + choice_list_fc3456a9 + Disabled + Enabled + + + choice_pairs_3c87fcdb + 1 + 0 + + + choice_pairs_53749dec + 1 + 0 + + + choice_pairs_6f00a734 + 0 + 1 + 2 + + + + + xilinx_elaboratesubcores_view_fileset + + ip_0/xdma_pcie4_ip_gt.xci + xci + + + ip_0/xdma_pcie4_ip_gt.xml + xml + + + + The Xilinx UltraScale+ PCI Express Integrated Block (1-lane, 2-lane, 4-lane, 8-lane and 16-lane) in conjunction with flexible Ultra series architectural features such as integrated GTs (Gigabit Transceivers) and BRAM (Block RAMs) are used to implement a PCI Express Base Specification v3.1 compliant PCI Express Endpoint. + + + device_port_type + Device Port Type + PCI_Express_Endpoint_device + + + xlnx_ref_board + Xlnx Ref Board + AU200 + + + + true + + + + + + testname + test + sample_smoke_test0 + + + PL_LINK_CAP_MAX_LINK_SPEED + Pl Link Cap Max Link Speed + 8.0_GT/s + + + PL_LINK_CAP_MAX_LINK_WIDTH + Pl Link Cap Max Link Width + The Xilinx Ultrascale Series Gen3 Integrated Block for PCI Expressification v3.0 compliant PCI Express Endpoint. + X8 + + + REF_CLK_FREQ + Ref Clk Freq + 100_MHz + + + AXISTEN_IF_EXT_512_CQ_STRADDLE + Axisten If Rc Straddle + false + + + + false + + + + + + AXISTEN_IF_EXT_512_CC_STRADDLE + Axisten If Rc Straddle + false + + + AXISTEN_IF_EXT_512_RQ_STRADDLE + Axisten If Rc Straddle + false + + + + false + + + + + + AXISTEN_IF_EXT_512_RC_STRADDLE + Axisten If Rc Straddle + true + + + AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE + Axisten If 512 4TLP/2TLP Rc Straddle + false + + + + false + + + + + + AXISTEN_IF_RC_STRADDLE + Axisten If Rc Straddle + true + + + axisten_if_enable_client_tag + Enable Client Tag + true + + + PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE + Pf0 Aer Cap Ecrc Gen and Check Capable + false + + + type1_membase_memlimit_enable + Type1 Config MemBase and MemLimit + Enabled + + + type1_prefetchable_membase_memlimit + Type1 Config Prefetchable MemBase and MemLimit + 64bit_Enabled + + + PF0_CLASS_CODE + Pf0 Class Code + 070001 + + + + false + + + + + + PF0_DEVICE_ID + Pf0 Device Id + 9038 + + + PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 128b Cas Atomic Completer Support + false + + + PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 32b Atomic Completer Support + false + + + PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 64b Atomic Completer Support + false + + + PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT + Pf0 Dev Cap2 Tph Completer Support + false + + + PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE + Pf0 Dev Cap Function Level Reset Capable + false + + + PF0_INTERRUPT_PIN + Pf0 Interrupt Pin + INTA + + + PF0_LINK_STATUS_SLOT_CLOCK_CONFIG + Pf0 Link Status Slot Clock Config + true + + + PF0_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF0_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0 + + + + false + + + + + + PF0_MSI_CAP_MULTIMSGCAP + Pf0 Msi Cap Multimsgcap + 1_vector + + + PF0_PM_CAP_PMESUPPORT_D1 + Pf0 Pm Cap Pmesupport D1 + false + + + PF0_PM_CAP_PMESUPPORT_D3HOT + Pf0 Pm Cap Pmesupport D3hot + false + + + PF0_PM_CAP_SUPP_D1_STATE + Pf0 Pm Cap Supp D1 State + false + + + PF0_REVISION_ID + Pf0 Revision Id + 00 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 1 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 0 + + + + false + + + + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0000 + + + PF0_SUBSYSTEM_ID + Pf0 Subsystem Id + 0007 + + + PF1_CLASS_CODE + Pf1 Class Code + 058000 + + + PF1_DEVICE_ID + Pf1 Device Id + 9011 + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + NONE + + + PF1_MSIX_CAP_PBA_BIR + Pf1 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_BIR + Pf1 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_SIZE + Pf1 Msix Cap Table Size + 0 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_OFFSET + Pf1 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF1_MSIX_CAP_PBA_OFFSET + Pf1 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 1_vector + + + PF1_REVISION_ID + Pf1 Revision Id + 00 + + + PF1_SRIOV_CAP_INITIAL_VF + Pf1 Sriov Cap Initial Vf + 0 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 1 + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + 0 + + + + false + + + + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0001 + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0000 + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0007 + + + PF2_CLASS_CODE + Pf2 Class Code + 058000 + + + PF2_DEVICE_ID + Pf2 Device Id + 9438 + + + PF2_INTERRUPT_PIN + Pf2 Interrupt Pin + NONE + + + PF2_MSIX_CAP_PBA_BIR + Pf2 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_BIR + Pf2 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_SIZE + Pf2 Msix Cap Table Size + 0 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_OFFSET + Pf2 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF2_MSIX_CAP_PBA_OFFSET + Pf2 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF2_MSI_CAP_MULTIMSGCAP + Pf2 Msi Cap Multimsgcap + 1_vector + + + PF2_REVISION_ID + Pf2 Revision Id + 00 + + + PF2_SRIOV_CAP_INITIAL_VF + Pf2 Sriov Cap Initial Vf + 0 + + + PF2_SRIOV_CAP_VER + Pf2 Sriov Cap Ver + 1 + + + PF2_SRIOV_FIRST_VF_OFFSET + Pf2 Sriov First Vf Offset + 0 + + + + false + + + + + + PF2_SRIOV_FUNC_DEP_LINK + Pf2 Sriov Func Dep Link + 0002 + + + PF2_SRIOV_SUPPORTED_PAGE_SIZE + Pf2 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF2_SRIOV_VF_DEVICE_ID + Pf2 Sriov Vf Device Id + 0000 + + + PF2_SUBSYSTEM_ID + Pf2 Subsystem Id + 0007 + + + PF3_CLASS_CODE + Pf3 Class Code + 058000 + + + PF3_DEVICE_ID + Pf3 Device Id + 9638 + + + PF3_INTERRUPT_PIN + Pf3 Interrupt Pin + NONE + + + PF3_MSIX_CAP_PBA_BIR + Pf3 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_BIR + Pf3 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_SIZE + Pf3 Msix Cap Table Size + 0 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_OFFSET + Pf3 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF3_MSIX_CAP_PBA_OFFSET + Pf3 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF3_MSI_CAP_MULTIMSGCAP + Pf3 Msi Cap Multimsgcap + 1_vector + + + PF3_REVISION_ID + Pf3 Revision Id + 00 + + + PF3_SRIOV_CAP_INITIAL_VF + Pf3 Sriov Cap Initial Vf + 0 + + + PF3_SRIOV_CAP_VER + Pf3 Sriov Cap Ver + 1 + + + PF3_SRIOV_FIRST_VF_OFFSET + Pf3 Sriov First Vf Offset + 0 + + + + false + + + + + + PF3_SRIOV_FUNC_DEP_LINK + Pf3 Sriov Func Dep Link + 0003 + + + PF3_SRIOV_SUPPORTED_PAGE_SIZE + Pf3 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF3_SRIOV_VF_DEVICE_ID + Pf3 Sriov Vf Device Id + 0000 + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0007 + + + TL_PF_ENABLE_REG + 1 + + + SRIOV_CAP_ENABLE + Sriov Cap Enable + false + + + Component_Name + xdma_pcie4_ip + + + PF0_Use_Class_Code_Lookup_Assistant + false + + + PF1_Use_Class_Code_Lookup_Assistant + false + + + PF2_Use_Class_Code_Lookup_Assistant + false + + + PF3_Use_Class_Code_Lookup_Assistant + false + + + PF0_PM_CAP_PMESUPPORT_D0 + Pf0 Pm Cap Pmesupport D0 + false + + + PF0_SUBSYSTEM_VENDOR_ID + Pf0 Subsystem Vendor Id + 10EE + + + PF1_SUBSYSTEM_VENDOR_ID + Pf1 Subsystem Vendor Id + 10EE + + + PF2_SUBSYSTEM_VENDOR_ID + Pf2 Subsystem Vendor Id + 10EE + + + PF3_SUBSYSTEM_VENDOR_ID + Pf3 Subsystem Vendor Id + 10EE + + + pf1_sriov_bar5_scale + Pf1 Sriov Bar5 Scale + Kilobytes + + + + false + + + + + + pf2_sriov_bar5_scale + Pf2 Sriov Bar5 Scale + Kilobytes + + + + false + + + + + + pf3_sriov_bar5_scale + Pf3 Sriov Bar5 Scale + Kilobytes + + + + false + + + + + + pf0_class_code_sub + Pf0 Class Code Sub + 00 + + + pf1_sriov_bar4_type + Pf1 Sriov Bar4 Type + N/A + + + + false + + + + + + pf2_sriov_bar4_type + Pf2 Sriov Bar4 Type + N/A + + + + false + + + + + + pf3_sriov_bar4_type + Pf3 Sriov Bar4 Type + N/A + + + + false + + + + + + pf0_vc_cap_enabled + Pf0 Vc Cap Enabled + false + + + pf1_sriov_bar5_type + Pf1 Sriov Bar5 Type + N/A + + + + false + + + + + + pf2_sriov_bar5_type + Pf2 Sriov Bar5 Type + N/A + + + + false + + + + + + pf3_sriov_bar5_type + Pf3 Sriov Bar5 Type + N/A + + + + false + + + + + + pf1_sriov_bar0_enabled + Pf1 Sriov Bar0 Enabled + true + + + + false + + + + + + pf2_sriov_bar0_enabled + Pf2 Sriov Bar0 Enabled + true + + + + false + + + + + + pf3_sriov_bar0_enabled + Pf3 Sriov Bar0 Enabled + true + + + + false + + + + + + pf0_sriov_bar5_enabled + Pf0 Sriov Bar5 Enabled + false + + + pf2_sriov_bar5_enabled + Pf2 Sriov Bar5 Enabled + false + + + + false + + + + + + pf3_sriov_bar5_enabled + Pf3 Sriov Bar5 Enabled + false + + + + false + + + + + + pcie_blk_locn + Pcie Blk Locn + X1Y2 + + + pf0_sriov_bar1_64bit + Pf0 Sriov Bar1 64bit + false + + + + false + + + + + + pf1_class_code_base + Pf1 Class Code Base + 05 + + + pf2_class_code_base + Pf2 Class Code Base + 05 + + + pf3_class_code_base + Pf3 Class Code Base + 05 + + + pf1_sriov_bar3_prefetchable + Pf1 Sriov Bar3 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar3_prefetchable + Pf2 Sriov Bar3 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar3_prefetchable + Pf3 Sriov Bar3 Prefetchable + false + + + + false + + + + + + pf1_sriov_bar0_64bit + Pf1 Sriov Bar0 64bit + false + + + + false + + + + + + pf2_sriov_bar0_64bit + Pf2 Sriov Bar0 64bit + false + + + + false + + + + + + pf3_sriov_bar0_64bit + Pf3 Sriov Bar0 64bit + false + + + + false + + + + + + pf1_bar3_type + Pf1 Bar3 Type + N/A + + + + false + + + + + + pf2_bar3_type + Pf2 Bar3 Type + N/A + + + + false + + + + + + pf3_bar3_type + Pf3 Bar3 Type + N/A + + + + false + + + + + + pf2_bar2_enabled + Pf2 Bar2 Enabled + false + + + + false + + + + + + pf3_bar2_enabled + Pf3 Bar2 Enabled + false + + + + false + + + + + + pf1_bar2_enabled + Pf1 Bar2 Enabled + false + + + + false + + + + + + pf1_bar2_type + Pf1 Bar2 Type + N/A + + + + false + + + + + + pf1_bar2_64bit + Pf1 Bar2 64bit + false + + + + false + + + + + + pf1_bar2_prefetchable + Pf1 Bar2 Prefetchable + false + + + + false + + + + + + pf1_bar2_scale + Pf1 Bar2 Scale + Kilobytes + + + + false + + + + + + pf1_bar2_size + Pf1 Bar2 Size + 128 + + + + false + + + + + + pf0_class_code_interface + Pf0 Class Code Interface + 01 + + + pf0_sriov_bar1_scale + Pf0 Sriov Bar1 Scale + Kilobytes + + + + false + + + + + + pf1_bar4_type + Pf1 Bar4 Type + N/A + + + + false + + + + + + pf2_bar2_type + Pf2 Bar2 Type + N/A + + + + false + + + + + + pf2_bar2_64bit + Pf2 Bar2 64bit + false + + + + false + + + + + + pf2_bar2_prefetchable + Pf2 Bar2 Prefetchable + false + + + + false + + + + + + pf2_bar2_scale + Pf2 Bar2 Scale + Kilobytes + + + + false + + + + + + pf2_bar2_size + Pf2 Bar2 Size + 128 + + + + false + + + + + + pf2_bar4_type + Pf2 Bar4 Type + N/A + + + + false + + + + + + pf3_bar2_type + Pf3 Bar2 Type + N/A + + + + false + + + + + + pf3_bar2_64bit + Pf3 Bar2 64bit + false + + + + false + + + + + + pf3_bar2_prefetchable + Pf3 Bar2 Prefetchable + false + + + + false + + + + + + pf3_bar2_scale + Pf3 Bar2 Scale + Kilobytes + + + + false + + + + + + pf3_bar2_size + Pf3 Bar2 Size + 128 + + + + false + + + + + + pf3_bar4_type + Pf3 Bar4 Type + N/A + + + + false + + + + + + pf0_base_class_menu + Pf0 Base Class Menu + Simple_communication_controllers + + + pf0_sub_class_interface_menu + Pf0 Sub Class Interface Menu + 16450_compatible_serial_controller + + + pf1_sriov_bar0_scale + Pf1 Sriov Bar0 Scale + Kilobytes + + + + false + + + + + + pf1_expansion_rom_enabled + Pf1 Expansion Rom Enabled + false + + + + false + + + + + + pf0_sriov_bar0_enabled + Pf0 Sriov Bar0 Enabled + true + + + pf1_sriov_bar0_prefetchable + Pf1 Sriov Bar0 Prefetchable + false + + + + false + + + + + + pf1_bar5_type + Pf1 Bar5 Type + N/A + + + + false + + + + + + pf0_sriov_bar5_prefetchable + Pf0 Sriov Bar5 Prefetchable + false + + + pf1_sriov_bar1_enabled + Pf1 Sriov Bar1 Enabled + false + + + + false + + + + + + pf1_class_code_interface + Pf1 Class Code Interface + 00 + + + pf0_sriov_bar2_64bit + Pf0 Sriov Bar2 64bit + false + + + + false + + + + + + pf1_msix_enabled + Pf1 Msix Enabled + false + + + pf1_bar5_prefetchable + Pf1 Bar5 Prefetchable + false + + + pf1_sriov_bar1_64bit + Pf1 Sriov Bar1 64bit + false + + + + false + + + + + + pf1_bar3_64bit + Pf1 Bar3 64bit + false + + + + false + + + + + + pf0_sriov_bar2_prefetchable + Pf0 Sriov Bar2 Prefetchable + false + + + + false + + + + + + pf1_bar3_enabled + Pf1 Bar3 Enabled + false + + + + false + + + + + + pf0_sriov_bar2_scale + Pf0 Sriov Bar2 Scale + Kilobytes + + + + false + + + + + + pf1_sriov_bar1_scale + Pf1 Sriov Bar1 Scale + Kilobytes + + + + false + + + + + + pf1_bar3_scale + Pf1 Bar3 Scale + Kilobytes + + + + false + + + + + + pf0_sriov_bar1_enabled + Pf0 Sriov Bar1 Enabled + false + + + AXISTEN_IF_RQ_ALIGNMENT_MODE + DWORD_Aligned + + + AXISTEN_IF_CQ_ALIGNMENT_MODE + Address_Aligned + + + alignment_mode_256b + Alignment Mode + DWORD_Aligned + + + pf1_sriov_bar4_prefetchable + Pf1 Sriov Bar4 Prefetchable + false + + + + false + + + + + + pf1_sriov_bar2_enabled + Pf1 Sriov Bar2 Enabled + false + + + + false + + + + + + pf0_sriov_bar3_64bit + Pf0 Sriov Bar3 64bit + false + + + + false + + + + + + pf0_sriov_bar0_size + Pf0 Sriov Bar0 Size + 2 + + + pf1_sriov_bar2_64bit + Pf1 Sriov Bar2 64bit + false + + + + false + + + + + + pf1_bar4_64bit + Pf1 Bar4 64bit + false + + + + false + + + + + + pf0_sriov_bar1_size + Pf0 Sriov Bar1 Size + 2 + + + + false + + + + + + pf0_bar0_enabled + Pf0 Bar0 Enabled + true + + + pf0_bar0_type + Pf0 Bar0 Type + Memory + + + pf0_bar0_64bit + Pf0 Bar0 64bit + false + + + pf0_bar0_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar0_scale + Pf0 Bar0 Scale + Kilobytes + + + pf0_bar0_size + Pf0 Bar0 Size + 64 + + + pf0_bar1_enabled + Pf0 Bar1 Enabled + false + + + pf0_bar1_type + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf0_bar1_64bit + Pf0 Bar1 64bit + false + + + + false + + + + + + pf0_bar1_prefetchable + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf0_bar1_scale + Pf0 Bar1 Scale + Kilobytes + + + + false + + + + + + pf0_bar1_size + Pf0 Bar1 Size + 128 + + + + false + + + + + + pf0_bar2_enabled + Pf0 Bar2 Enabled + false + + + pf0_bar2_type + Pf0 Bar2 Type + N/A + + + + false + + + + + + pf0_bar2_64bit + Pf0 Bar2 64bit + false + + + + false + + + + + + pf0_bar2_prefetchable + Pf0 Bar2 Prefetchable + false + + + + false + + + + + + pf0_bar2_scale + Pf0 Bar2 Scale + Kilobytes + + + + false + + + + + + pf0_bar2_size + Pf0 Bar2 Size + 128 + + + + false + + + + + + pf0_bar3_enabled + Pf0 Bar3 Enabled + false + + + pf0_bar3_type + Pf0 Bar3 Type + N/A + + + + false + + + + + + pf0_bar3_64bit + Pf0 Bar3 64bit + false + + + + false + + + + + + pf0_bar3_prefetchable + Pf0 Bar3 Prefetchable + false + + + + false + + + + + + pf0_bar3_scale + Pf0 Bar3 Scale + Kilobytes + + + + false + + + + + + pf0_bar3_size + Pf0 Bar3 Size + 128 + + + + false + + + + + + pf0_bar4_enabled + Pf0 Bar4 Enabled + false + + + pf0_bar4_type + Pf0 Bar4 Type + N/A + + + + false + + + + + + pf0_bar4_64bit + Pf0 Bar4 64bit + false + + + + false + + + + + + pf0_bar4_prefetchable + Pf0 Bar4 Prefetchable + false + + + + false + + + + + + pf0_bar4_scale + Pf0 Bar4 Scale + Kilobytes + + + + false + + + + + + pf0_bar4_size + Pf0 Bar4 Size + 128 + + + + false + + + + + + pf0_bar5_enabled + Pf0 Bar5 Enabled + false + + + pf0_bar5_type + Pf0 Bar5 Type + N/A + + + + false + + + + + + pf0_bar5_prefetchable + Pf0 Bar5 Prefetchable + false + + + pf0_bar5_scale + Pf0 Bar5 Scale + Kilobytes + + + + false + + + + + + pf0_bar5_size + Pf0 Bar5 Size + 128 + + + + false + + + + + + pf0_sriov_bar3_scale + Pf0 Sriov Bar3 Scale + Kilobytes + + + + false + + + + + + pf1_bar4_enabled + Pf1 Bar4 Enabled + false + + + + false + + + + + + pf1_sriov_bar1_prefetchable + Pf1 Sriov Bar1 Prefetchable + false + + + + false + + + + + + pf0_sriov_bar2_size + Pf0 Sriov Bar2 Size + 2 + + + + false + + + + + + pf1_sriov_bar2_scale + Pf1 Sriov Bar2 Scale + Kilobytes + + + + false + + + + + + pf1_bar4_scale + Pf1 Bar4 Scale + Kilobytes + + + + false + + + + + + pf0_sriov_bar3_size + Pf0 Sriov Bar3 Size + 2 + + + + false + + + + + + pf0_sriov_bar2_enabled + Pf0 Sriov Bar2 Enabled + false + + + pf0_dev_cap_max_payload + Pf0 Dev Cap Max Payload + 1024_bytes + + + gen_x0y0 + Gen X0y0 + false + + + + false + + + + + + gen_x0y1 + Gen X0y1 + false + + + + false + + + + + + gen_x0y2 + Gen X0y2 + false + + + + false + + + + + + gen_x0y3 + Gen X0y3 + false + + + + false + + + + + + gen_x0y4 + Gen X0y4 + false + + + + false + + + + + + gen_x0y5 + Gen X0y5 + false + + + + false + + + + + + gen_x1y0 + Gen X1y0 + false + + + + false + + + + + + gen_x1y1 + Gen X1y1 + false + + + + false + + + + + + gen_x1y2 + Gen X1y2 + true + + + + false + + + + + + gen_x1y3 + Gen X1y3 + false + + + + false + + + + + + gen_x1y4 + Gen X1y4 + false + + + + false + + + + + + gen_x1y5 + Gen X1y5 + false + + + + false + + + + + + pf0_sriov_bar4_size + Pf0 Sriov Bar4 Size + 2 + + + + false + + + + + + pf1_expansion_rom_scale + Pf1 Expansion Rom Scale + Kilobytes + + + + false + + + + + + pf1_expansion_rom_size + Pf1 Expansion Rom Size + 2 + + + + false + + + + + + pf1_sriov_bar3_enabled + Pf1 Sriov Bar3 Enabled + false + + + + false + + + + + + pf0_sriov_bar4_64bit + Pf0 Sriov Bar4 64bit + false + + + + false + + + + + + pf0_sriov_bar5_size + Pf0 Sriov Bar5 Size + 2 + + + + false + + + + + + pf0_sriov_bar3_prefetchable + Pf0 Sriov Bar3 Prefetchable + false + + + + false + + + + + + pf1_sriov_bar3_64bit + Pf1 Sriov Bar3 64bit + false + + + + false + + + + + + pf0_expansion_rom_enabled + Pf0 Expansion Rom Enabled + false + + + pf0_sriov_bar4_scale + Pf0 Sriov Bar4 Scale + Kilobytes + + + + false + + + + + + pf1_base_class_menu + Pf1 Base Class Menu + Memory_controller + + + pf1_sub_class_interface_menu + Pf1 Sub Class Interface Menu + Other_memory_controller + + + pf0_sriov_bar0_type + Pf0 Sriov Bar0 Type + Memory + + + pf1_bar5_enabled + Pf1 Bar5 Enabled + false + + + + false + + + + + + pf1_bar3_prefetchable + Pf1 Bar3 Prefetchable + false + + + + false + + + + + + pf1_sriov_bar0_size + Pf1 Sriov Bar0 Size + 2 + + + + false + + + + + + pf1_sriov_bar3_scale + Pf1 Sriov Bar3 Scale + Kilobytes + + + + false + + + + + + pf1_bar5_scale + Pf1 Bar5 Scale + Kilobytes + + + + false + + + + + + pf1_class_code_sub + Pf1 Class Code Sub + 80 + + + extended_tag_field + Extended Tag Field + true + + + pf0_sriov_bar1_type + Pf0 Sriov Bar1 Type + N/A + + + + false + + + + + + pf0_sriov_bar0_prefetchable + Pf0 Sriov Bar0 Prefetchable + false + + + + false + + + + + + pf0_expansion_rom_scale + Pf0 Expansion Rom Scale + Kilobytes + + + + false + + + + + + pf0_expansion_rom_size + Pf0 Expansion Rom Size + 2 + + + + false + + + + + + pf1_sriov_bar1_size + Pf1 Sriov Bar1 Size + 2 + + + + false + + + + + + pf0_sriov_bar3_enabled + Pf0 Sriov Bar3 Enabled + false + + + pf1_sriov_bar5_prefetchable + Pf1 Sriov Bar5 Prefetchable + false + + + pf0_sriov_bar2_type + Pf0 Sriov Bar2 Type + N/A + + + + false + + + + + + vendor_id + Vendor Id + 10EE + + + pf1_vendor_id + Vendor Id + 10EE + + + pf2_vendor_id + Vendor Id + 10EE + + + pf3_vendor_id + Vendor Id + 10EE + + + pf0_tphr_enable + Pf0 Tphr Enable + false + + + pf1_sriov_bar2_size + Pf1 Sriov Bar2 Size + 2 + + + + false + + + + + + pf0_sriov_bar3_type + Pf0 Sriov Bar3 Type + N/A + + + + false + + + + + + pf1_sriov_bar3_size + Pf1 Sriov Bar3 Size + 2 + + + + false + + + + + + pf1_bar0_enabled + Pf1 Bar0 Enabled + true + + + + false + + + + + + pf1_bar0_type + Pf1 Bar0 Type + Memory + + + + false + + + + + + pf1_bar0_64bit + Pf1 Bar0 64bit + false + + + + false + + + + + + pf1_bar0_prefetchable + Pf1 Bar0 Prefetchable + false + + + + false + + + + + + pf1_bar0_scale + Pf1 Bar0 Scale + Kilobytes + + + + false + + + + + + pf1_bar0_size + Pf1 Bar0 Size + 64 + + + + false + + + + + + pf1_bar1_enabled + Pf1 Bar1 Enabled + false + + + + false + + + + + + pf1_bar1_type + Pf1 Bar1 Type + N/A + + + + false + + + + + + pf1_bar1_64bit + Pf1 Bar1 64bit + false + + + + false + + + + + + pf1_bar1_prefetchable + Pf1 Bar1 Prefetchable + false + + + + false + + + + + + pf1_bar1_scale + Pf1 Bar1 Scale + Kilobytes + + + + false + + + + + + pf1_bar1_size + Pf1 Bar1 Size + 128 + + + + false + + + + + + pf1_sriov_bar4_enabled + Pf1 Sriov Bar4 Enabled + false + + + + false + + + + + + pf0_sriov_bar4_type + Pf0 Sriov Bar4 Type + N/A + + + + false + + + + + + pf1_sriov_bar4_64bit + Pf1 Sriov Bar4 64bit + false + + + + false + + + + + + pf1_sriov_bar2_prefetchable + Pf1 Sriov Bar2 Prefetchable + false + + + + false + + + + + + pf0_sriov_cap_ver + Pf0 Sriov Cap Ver + 1 + + + pf1_sriov_bar4_size + Pf1 Sriov Bar4 Size + 2 + + + + false + + + + + + pf1_msi_enabled + Pf1 Msi Enabled + false + + + + false + + + + + + pf0_sriov_bar5_scale + Pf0 Sriov Bar5 Scale + Kilobytes + + + + false + + + + + + pf0_sriov_bar5_type + Pf0 Sriov Bar5 Type + N/A + + + + false + + + + + + ext_pcie_cfg_space_enabled + Ext Pcie Cfg Space Enabled + false + + + legacy_ext_pcie_cfg_space_enabled + Legacy Ext Pcie Cfg Space Enabled + false + + + ext_xvc_vsec_enable + Enable to add the PCIe XVC-VSEC to the Examlpe Design + false + + + + false + + + + + + acs_ext_cap_enable + ACS Ext Capability + false + + + pf1_sriov_bar4_scale + Pf1 Sriov Bar4 Scale + Kilobytes + + + + false + + + + + + pf1_sriov_bar5_size + Pf1 Sriov Bar5 Size + 2 + + + + false + + + + + + pf0_ari_enabled + Pf0 Ari Enabled + false + + + perf_level + Perf Level + Extreme + + + pf0_class_code_base + Pf0 Class Code Base + 07 + + + axisten_if_width + Axisten If Width + 256_bit + + + pf0_sriov_bar4_enabled + Pf0 Sriov Bar4 Enabled + false + + + pf1_sriov_bar0_type + Pf1 Sriov Bar0 Type + Memory + + + + false + + + + + + pf1_bar3_size + Pf1 Bar3 Size + 128 + + + + false + + + + + + pf0_sriov_bar4_prefetchable + Pf0 Sriov Bar4 Prefetchable + false + + + + false + + + + + + pf0_aer_enabled + Pf0 Aer Enabled + true + + + pf0_dsn_enabled + Pf0 Dsn Enabled + false + + + pf1_sriov_bar1_type + Pf1 Sriov Bar1 Type + N/A + + + + false + + + + + + pf0_sriov_bar0_64bit + Pf0 Sriov Bar0 64bit + false + + + pf1_bar4_size + Pf1 Bar4 Size + 128 + + + + false + + + + + + pf0_msi_enabled + Pf0 Msi Enabled + true + + + pf1_sriov_bar5_enabled + Pf1 Sriov Bar5 Enabled + false + + + + false + + + + + + pf1_sriov_bar2_type + Pf1 Sriov Bar2 Type + N/A + + + + false + + + + + + pf0_msix_enabled + Pf0 Msix Enabled + false + + + pf1_bar5_size + Pf1 Bar5 Size + 128 + + + + false + + + + + + pf1_bar4_prefetchable + Pf1 Bar4 Prefetchable + false + + + + false + + + + + + pf0_sriov_bar0_scale + Pf0 Sriov Bar0 Scale + Kilobytes + + + pf0_sriov_bar1_prefetchable + Pf0 Sriov Bar1 Prefetchable + false + + + + false + + + + + + pf1_sriov_bar3_type + Pf1 Sriov Bar3 Type + N/A + + + + false + + + + + + pf2_sriov_bar0_scale + Pf2 Sriov Bar0 Scale + Kilobytes + + + + false + + + + + + pf2_expansion_rom_enabled + Pf2 Expansion Rom Enabled + false + + + + false + + + + + + pf2_sriov_bar0_prefetchable + Pf2 Sriov Bar0 Prefetchable + false + + + + false + + + + + + pf2_bar5_type + Pf2 Bar5 Type + N/A + + + + false + + + + + + pf2_sriov_bar1_enabled + Pf2 Sriov Bar1 Enabled + false + + + + false + + + + + + pf2_class_code_interface + Pf2 Class Code Interface + 00 + + + pf2_msix_enabled + Pf2 Msix Enabled + false + + + pf2_bar5_prefetchable + Pf2 Bar5 Prefetchable + false + + + pf2_sriov_bar1_64bit + Pf2 Sriov Bar1 64bit + false + + + + false + + + + + + pf2_bar3_64bit + Pf2 Bar3 64bit + false + + + + false + + + + + + pf2_bar3_enabled + Pf2 Bar3 Enabled + false + + + + false + + + + + + pf2_sriov_bar1_scale + Pf2 Sriov Bar1 Scale + Kilobytes + + + + false + + + + + + pf2_bar3_scale + Pf2 Bar3 Scale + Kilobytes + + + + false + + + + + + pf2_sriov_bar4_prefetchable + Pf2 Sriov Bar4 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar2_enabled + Pf2 Sriov Bar2 Enabled + false + + + + false + + + + + + pf2_sriov_bar2_64bit + Pf2 Sriov Bar2 64bit + false + + + + false + + + + + + pf2_bar4_64bit + Pf2 Bar4 64bit + false + + + + false + + + + + + pf2_bar4_enabled + Pf2 Bar4 Enabled + false + + + + false + + + + + + pf2_sriov_bar1_prefetchable + Pf2 Sriov Bar1 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar2_scale + Pf2 Sriov Bar2 Scale + Kilobytes + + + + false + + + + + + pf2_bar4_scale + Pf2 Bar4 Scale + Kilobytes + + + + false + + + + + + pf2_expansion_rom_scale + Pf2 Expansion Rom Scale + Kilobytes + + + + false + + + + + + pf2_expansion_rom_size + Pf2 Expansion Rom Size + 2 + + + + false + + + + + + pf2_sriov_bar3_enabled + Pf2 Sriov Bar3 Enabled + false + + + + false + + + + + + pf2_sriov_bar3_64bit + Pf2 Sriov Bar3 64bit + false + + + + false + + + + + + pf2_base_class_menu + Pf2 Base Class Menu + Memory_controller + + + pf2_sub_class_interface_menu + Pf2 Sub Class Interface Menu + Other_memory_controller + + + pf2_bar5_enabled + Pf2 Bar5 Enabled + false + + + + false + + + + + + pf2_bar3_prefetchable + Pf2 Bar3 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar0_size + Pf2 Sriov Bar0 Size + 2 + + + + false + + + + + + pf2_sriov_bar3_scale + Pf2 Sriov Bar3 Scale + Kilobytes + + + + false + + + + + + pf2_bar5_scale + Pf2 Bar5 Scale + Kilobytes + + + + false + + + + + + pf2_class_code_sub + Pf2 Class Code Sub + 80 + + + pf2_sriov_bar1_size + Pf2 Sriov Bar1 Size + 2 + + + + false + + + + + + pf2_sriov_bar5_prefetchable + Pf2 Sriov Bar5 Prefetchable + false + + + pf2_sriov_bar2_size + Pf2 Sriov Bar2 Size + 2 + + + + false + + + + + + pf2_sriov_bar3_size + Pf2 Sriov Bar3 Size + 2 + + + + false + + + + + + pf2_bar0_enabled + Pf2 Bar0 Enabled + true + + + + false + + + + + + pf2_bar0_type + Pf2 Bar0 Type + Memory + + + + false + + + + + + pf2_bar0_64bit + Pf2 Bar0 64bit + false + + + + false + + + + + + pf2_bar0_prefetchable + Pf2 Bar0 Prefetchable + false + + + + false + + + + + + pf2_bar0_scale + Pf2 Bar0 Scale + Kilobytes + + + + false + + + + + + pf2_bar0_size + Pf2 Bar0 Size + 64 + + + + false + + + + + + pf2_bar1_enabled + Pf2 Bar1 Enabled + false + + + + false + + + + + + pf2_bar1_type + Pf2 Bar1 Type + N/A + + + + false + + + + + + pf2_bar1_64bit + Pf2 Bar1 64bit + false + + + + false + + + + + + pf2_bar1_prefetchable + Pf2 Bar1 Prefetchable + false + + + + false + + + + + + pf2_bar1_scale + Pf2 Bar1 Scale + Kilobytes + + + + false + + + + + + pf2_bar1_size + Pf2 Bar1 Size + 128 + + + + false + + + + + + pf2_sriov_bar4_enabled + Pf2 Sriov Bar4 Enabled + false + + + + false + + + + + + pf2_sriov_bar4_64bit + Pf2 Sriov Bar4 64bit + false + + + + false + + + + + + pf2_sriov_bar2_prefetchable + Pf2 Sriov Bar2 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar4_size + Pf2 Sriov Bar4 Size + 2 + + + + false + + + + + + pf2_msi_enabled + Pf2 Msi Enabled + false + + + + false + + + + + + pf2_sriov_bar4_scale + Pf2 Sriov Bar4 Scale + Kilobytes + + + + false + + + + + + pf2_sriov_bar5_size + Pf2 Sriov Bar5 Size + 2 + + + + false + + + + + + pf2_sriov_bar0_type + Pf2 Sriov Bar0 Type + Memory + + + + false + + + + + + pf2_bar3_size + Pf2 Bar3 Size + 128 + + + + false + + + + + + pf2_sriov_bar1_type + Pf2 Sriov Bar1 Type + N/A + + + + false + + + + + + pf2_bar4_size + Pf2 Bar4 Size + 128 + + + + false + + + + + + pf2_sriov_bar2_type + Pf2 Sriov Bar2 Type + N/A + + + + false + + + + + + pf2_bar5_size + Pf2 Bar5 Size + 128 + + + + false + + + + + + pf2_bar4_prefetchable + Pf2 Bar4 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar3_type + Pf2 Sriov Bar3 Type + N/A + + + + false + + + + + + pf3_sriov_bar0_scale + Pf3 Sriov Bar0 Scale + Kilobytes + + + + false + + + + + + pf3_expansion_rom_enabled + Pf3 Expansion Rom Enabled + false + + + + false + + + + + + pf3_sriov_bar0_prefetchable + Pf3 Sriov Bar0 Prefetchable + false + + + + false + + + + + + pf3_bar5_type + Pf3 Bar5 Type + N/A + + + + false + + + + + + pf3_sriov_bar1_enabled + Pf3 Sriov Bar1 Enabled + false + + + + false + + + + + + pf3_class_code_interface + Pf3 Class Code Interface + 00 + + + pf3_msix_enabled + Pf3 Msix Enabled + false + + + pf3_bar5_prefetchable + Pf3 Bar5 Prefetchable + false + + + pf3_sriov_bar1_64bit + Pf3 Sriov Bar1 64bit + false + + + + false + + + + + + pf3_bar3_64bit + Pf3 Bar3 64bit + false + + + + false + + + + + + pf3_bar3_enabled + Pf3 Bar3 Enabled + false + + + + false + + + + + + pf3_sriov_bar1_scale + Pf3 Sriov Bar1 Scale + Kilobytes + + + + false + + + + + + pf3_bar3_scale + Pf3 Bar3 Scale + Kilobytes + + + + false + + + + + + pf3_sriov_bar4_prefetchable + Pf3 Sriov Bar4 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar2_enabled + Pf3 Sriov Bar2 Enabled + false + + + + false + + + + + + pf3_sriov_bar2_64bit + Pf3 Sriov Bar2 64bit + false + + + + false + + + + + + pf3_bar4_64bit + Pf3 Bar4 64bit + false + + + + false + + + + + + pf3_bar4_enabled + Pf3 Bar4 Enabled + false + + + + false + + + + + + pf3_sriov_bar1_prefetchable + Pf3 Sriov Bar1 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar2_scale + Pf3 Sriov Bar2 Scale + Kilobytes + + + + false + + + + + + pf3_bar4_scale + Pf3 Bar4 Scale + Kilobytes + + + + false + + + + + + pf3_expansion_rom_scale + Pf3 Expansion Rom Scale + Kilobytes + + + + false + + + + + + pf3_expansion_rom_size + Pf3 Expansion Rom Size + 2 + + + + false + + + + + + pf3_sriov_bar3_enabled + Pf3 Sriov Bar3 Enabled + false + + + + false + + + + + + pf3_sriov_bar3_64bit + Pf3 Sriov Bar3 64bit + false + + + + false + + + + + + pf3_base_class_menu + Pf3 Base Class Menu + Memory_controller + + + pf3_sub_class_interface_menu + Pf3 Sub Class Interface Menu + Other_memory_controller + + + pf3_bar5_enabled + Pf3 Bar5 Enabled + false + + + + false + + + + + + pf3_bar3_prefetchable + Pf3 Bar3 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar0_size + Pf3 Sriov Bar0 Size + 2 + + + + false + + + + + + pf3_sriov_bar3_scale + Pf3 Sriov Bar3 Scale + Kilobytes + + + + false + + + + + + pf3_bar5_scale + Pf3 Bar5 Scale + Kilobytes + + + + false + + + + + + pf3_class_code_sub + Pf3 Class Code Sub + 80 + + + pf3_sriov_bar1_size + Pf3 Sriov Bar1 Size + 2 + + + + false + + + + + + pf3_sriov_bar5_prefetchable + Pf3 Sriov Bar5 Prefetchable + false + + + pf3_sriov_bar2_size + Pf3 Sriov Bar2 Size + 2 + + + + false + + + + + + pf3_sriov_bar3_size + Pf3 Sriov Bar3 Size + 2 + + + + false + + + + + + pf3_bar0_enabled + Pf3 Bar0 Enabled + true + + + + false + + + + + + pf3_bar0_type + Pf3 Bar0 Type + Memory + + + + false + + + + + + pf3_bar0_64bit + Pf3 Bar0 64bit + false + + + + false + + + + + + pf3_bar0_prefetchable + Pf3 Bar0 Prefetchable + false + + + + false + + + + + + pf3_bar0_scale + Pf3 Bar0 Scale + Kilobytes + + + + false + + + + + + pf3_bar0_size + Pf3 Bar0 Size + 64 + + + + false + + + + + + pf3_bar1_enabled + Pf3 Bar1 Enabled + false + + + + false + + + + + + pf3_bar1_type + Pf3 Bar1 Type + N/A + + + + false + + + + + + pf3_bar1_64bit + Pf3 Bar1 64bit + false + + + + false + + + + + + pf3_bar1_prefetchable + Pf3 Bar1 Prefetchable + false + + + + false + + + + + + pf3_bar1_scale + Pf3 Bar1 Scale + Kilobytes + + + + false + + + + + + pf3_bar1_size + Pf3 Bar1 Size + 128 + + + + false + + + + + + pf3_sriov_bar4_enabled + Pf3 Sriov Bar4 Enabled + false + + + + false + + + + + + pf3_sriov_bar4_64bit + Pf3 Sriov Bar4 64bit + false + + + + false + + + + + + pf3_sriov_bar2_prefetchable + Pf3 Sriov Bar2 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar4_size + Pf3 Sriov Bar4 Size + 2 + + + + false + + + + + + pf3_msi_enabled + Pf3 Msi Enabled + false + + + + false + + + + + + pf3_sriov_bar4_scale + Pf3 Sriov Bar4 Scale + Kilobytes + + + + false + + + + + + pf3_sriov_bar5_size + Pf3 Sriov Bar5 Size + 2 + + + + false + + + + + + pf3_sriov_bar0_type + Pf3 Sriov Bar0 Type + Memory + + + + false + + + + + + pf3_bar3_size + Pf3 Bar3 Size + 128 + + + + false + + + + + + pf3_sriov_bar1_type + Pf3 Sriov Bar1 Type + N/A + + + + false + + + + + + pf3_bar4_size + Pf3 Bar4 Size + 128 + + + + false + + + + + + pf3_sriov_bar2_type + Pf3 Sriov Bar2 Type + N/A + + + + false + + + + + + pf3_bar5_size + Pf3 Bar5 Size + 128 + + + + false + + + + + + pf3_bar4_prefetchable + Pf3 Bar4 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar3_type + Pf3 Sriov Bar3 Type + N/A + + + + false + + + + + + mode_selection + Mode + Advanced + + + pipe_sim + false + + + en_ext_clk + false + + + en_msi_per_vec_masking + false + + + coreclk_freq + CORE CLOCK FREQ + 500 + + + + true + + + + + + plltype + PLL TYPE + QPLL1 + + + axisten_freq + AXISTEN IF FREQ + 250 + + + aspm_support + ASPM Support + No_ASPM + + + SRIOV_CAP_ENABLE_EXT + SRIOV Cap Enable + false + + + cfg_fc_if + true + + + cfg_ext_if + false + + + cfg_status_if + true + + + per_func_status_if + true + + + cfg_mgmt_if + true + + + rcv_msg_if + true + + + cfg_tx_msg_if + true + + + cfg_ctl_if + true + + + tx_fc_if + true + + + en_pcie_drp + false + + + en_parity + false + + + en_pl_ifc + false + + + en_pcie_conf + false + + + dis_gt_wizard + false + + + bmd_pio_mode + false + + + sriov_exd_mode + false + + + dbg_checker + false + + + + false + + + + + + enable_ibert + false + + + two_port_switch + false + + + two_port_config + X8G3 + + + RX_PPM_OFFSET + Specify the PPM offset between received data and transmitted data + 0 + + + RX_SSC_PPM + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 15 + + + ins_loss_profile + Add-in_Card + + + + true + + + + + + enable_gen4 + true + + + local_test + false + + + en_transceiver_status_ports + false + + + + true + + + + + + Shared_Logic + 1 + + + gtwiz_in_core + 1 + + + gtcom_in_core + 2 + + + dedicate_perst + false + + + sys_reset_polarity + ACTIVE_LOW + + + mcap_enablement + MCAP Enable + None + + + mcap_fpga_bitstream_version + MCAP Bitstream Version Register Value + 00000000 + + + + false + + + + + + enable_code + 0000 + + + en_ext_ch_gt_drp + false + + + ext_startup_primitive + false + + + en_gt_selection + false + + + select_quad + GTY_Quad_227 + + + + false + + + + + + copy_pf0 + true + + + copy_sriov_pf0 + true + + + cfg_pm_if + true + + + pcie_id_if + FALSE + + + PL_DISABLE_LANE_REVERSAL + true + + + MSI_X_OPTIONS + None + + + completer_model + false + + + en_dbg_descramble + false + + + enable_jtag_dbg + false + + + + true + + + + + + enable_ltssm_dbg + false + + + + true + + + + + + tl_credits_cd + 15 + + + tl_credits_ch + 15 + + + set_finite_credit + false + + + gen4_eieos_0s7 + true + + + vu9p_board + false + + + ku15p_board + false + + + PHY_LP_TXPRESET + 4 + + + SYS_RST_N_BOARD_INTERFACE + Custom + + + PCIE_BOARD_INTERFACE + Custom + + + gt_drp_clk_src + GT DRP Clk Source + Internal + + + free_run_freq + Free Run Freq + 100_MHz + + + en_l23_entry + false + + + aws_mode_value + aws mode value + 0 + + + ext_sys_clk_bufg + false + + + mult_pf_des + true + + + axisten_if_enable_msg_route + 20000 + + + + true + + + + + + enable_more_clk + false + + + ctrl_skip_mask + true + + + disable_bram_pipeline + false + + + disable_eq_synchronizer + false + + + axisten_if_enable_rx_msg_intfc + false + + + axisten_if_enable_msg_route_override + true + + + enable_auto_rxeq + False + + + msix_type + MSI-X Type + HARD + + + three_port_switch + Three Port Switch Enable + false + + + disable_gt_loc + Disable GT loc constraint delivery + false + + + disconnect_hot_reset + disconnect hot_reset from user_reset + false + + + ku15p_gt_long_route + Enables KU15P GT long route + false + + + enable_mark_debug + false + + + enable_multipf_aer + false + + + master_cal_only + false + + + enable_multi_pcie + false + + + rbar_enable + false + + + pf0_rbar_num + Number of Resizable BARs for PF0 + 1 + + + pf1_rbar_num + Number of Resizable BARs for PF1 + 1 + + + pf2_rbar_num + Number of Resizable BARs for PF2 + 1 + + + pf3_rbar_num + Number of Resizable BARs for PF3 + 1 + + + pf0_bar0_index + PF0 BAR0 index + 0 + + + pf0_bar1_index + PF0 BAR1 index + 7 + + + pf0_bar2_index + PF0 BAR2 index + 7 + + + pf0_bar3_index + PF0 BAR3 index + 7 + + + pf0_bar4_index + PF0 BAR4 index + 7 + + + pf0_bar5_index + PF0 BAR5 index + 7 + + + pf1_bar0_index + PF0 BAR0 index + 0 + + + pf1_bar1_index + PF1 BAR1 index + 7 + + + pf1_bar2_index + PF1 BAR2 index + 7 + + + pf1_bar3_index + PF1 BAR3 index + 7 + + + pf1_bar4_index + PF1 BAR4 index + 7 + + + pf1_bar5_index + PF1 BAR5 index + 7 + + + pf2_bar0_index + PF2 BAR0 index + 0 + + + pf2_bar1_index + PF2 BAR1 index + 7 + + + pf2_bar2_index + PF2 BAR2 index + 7 + + + pf2_bar3_index + PF2 BAR3 index + 7 + + + pf2_bar4_index + PF2 BAR4 index + 7 + + + pf2_bar5_index + PF2 BAR5 index + 7 + + + pf3_bar0_index + PF3 BAR0 index + 0 + + + pf3_bar1_index + PF3 BAR1 index + 7 + + + pf3_bar2_index + PF3 BAR2 index + 7 + + + pf3_bar3_index + PF3 BAR3 index + 7 + + + pf3_bar4_index + PF3 BAR4 index + 7 + + + pf3_bar5_index + PF3 BAR5 index + 7 + + + pf0_rbar_cap_bar0 + PF0 RBAR CAP BAR0 + 0x00000000fff0 + + + pf0_rbar_cap_bar1 + PF0 RBAR CAP BAR1 + 0x000000000000 + + + pf0_rbar_cap_bar2 + PF0 RBAR CAP BAR2 + 0x000000000000 + + + pf0_rbar_cap_bar3 + PF0 RBAR CAP BAR3 + 0x000000000000 + + + pf0_rbar_cap_bar4 + PF0 RBAR CAP BAR4 + 0x000000000000 + + + pf0_rbar_cap_bar5 + PF0 RBAR CAP BAR5 + 0x000000000000 + + + pf1_rbar_cap_bar0 + PF1 RBAR CAP BAR0 + 0x00000000fff0 + + + pf1_rbar_cap_bar1 + PF1 RBAR CAP BAR1 + 0x000000000000 + + + pf1_rbar_cap_bar2 + PF1 RBAR CAP BAR2 + 0x000000000000 + + + pf1_rbar_cap_bar3 + PF1 RBAR CAP BAR3 + 0x000000000000 + + + pf1_rbar_cap_bar4 + PF1 RBAR CAP BAR4 + 0x000000000000 + + + pf1_rbar_cap_bar5 + PF1 RBAR CAP BAR5 + 0x000000000000 + + + pf2_rbar_cap_bar0 + PF2 RBAR CAP BAR0 + 0x00000000fff0 + + + pf2_rbar_cap_bar1 + PF2 RBAR CAP BAR1 + 0x000000000000 + + + pf2_rbar_cap_bar2 + PF2 RBAR CAP BAR2 + 0x000000000000 + + + pf2_rbar_cap_bar3 + PF2 RBAR CAP BAR3 + 0x000000000000 + + + pf2_rbar_cap_bar4 + PF2 RBAR CAP BAR4 + 0x000000000000 + + + pf2_rbar_cap_bar5 + PF2 RBAR CAP BAR5 + 0x000000000000 + + + pf3_rbar_cap_bar0 + PF3 RBAR CAP BAR0 + 0x00000000fff0 + + + pf3_rbar_cap_bar1 + PF3 RBAR CAP BAR1 + 0x000000000000 + + + pf3_rbar_cap_bar2 + PF3 RBAR CAP BAR2 + 0x000000000000 + + + pf3_rbar_cap_bar3 + PF3 RBAR CAP BAR3 + 0x000000000000 + + + pf3_rbar_cap_bar4 + PF3 RBAR CAP BAR4 + 0x000000000000 + + + pf3_rbar_cap_bar5 + PF3 RBAR CAP BAR5 + 0x000000000000 + + + VFG0_MSIX_CAP_PBA_OFFSET + vfg0 Msix Cap Pba Offset + 00000000 + + + VFG1_MSIX_CAP_PBA_OFFSET + vfg1 Msix Cap Pba Offset + 00000000 + + + VFG2_MSIX_CAP_PBA_OFFSET + vfg2 Msix Cap Pba Offset + 00000000 + + + VFG3_MSIX_CAP_PBA_OFFSET + vfg3 Msix Cap Pba Offset + 00000000 + + + VFG0_MSIX_CAP_TABLE_OFFSET + vfg0 Msix Cap table Offset + 00000000 + + + VFG1_MSIX_CAP_TABLE_OFFSET + vfg1 Msix Cap table Offset + 00000000 + + + VFG2_MSIX_CAP_TABLE_OFFSET + vfg2 Msix Cap table Offset + 00000000 + + + VFG3_MSIX_CAP_TABLE_OFFSET + vfg3 Msix Cap table Offset + 00000000 + + + VFG0_MSIX_CAP_TABLE_SIZE + vfg0 Msix Cap Table Size + 0 + + + VFG1_MSIX_CAP_TABLE_SIZE + vfg1 Msix Cap Table Size + 0 + + + VFG2_MSIX_CAP_TABLE_SIZE + vfg2 Msix Cap Table Size + 0 + + + VFG3_MSIX_CAP_TABLE_SIZE + vfg3 Msix Cap Table Size + 0 + + + enable_clkmux + false + + + use_msix_pfs_for_vfs + true + + + use_standard_interfaces + use standard interfaces for IPI design + false + + + dma_2rp + Truncate ports for 2RP DMA design + false + + + double_quad + false + + + enable_epyc_chipset_fix + false + + + disable_user_clock_root + true + + + enable_msix_32vec + false + + + broadcom_sbr_wa + false + + + MASTER_GT + GTHE4_CHANNEL_X49Y99 + + + qdma_tph_msix_brams_dis + false + + + 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Power for IP : 2.618 mW + + + + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f92be8b1 + 18 + 36 + 72 + 144 + 288 + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_eab86dfe + READ_FIRST + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + xdma_v4_1_8_blk_mem_64_reg_be + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Simple_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + true + + + + + + ECC + false + + + + true + + + + + + softecc + false + + + + true + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + 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Power for IP : 2.618 mW + + + + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f92be8b1 + 18 + 36 + 72 + 144 + 288 + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_eab86dfe + READ_FIRST + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + xdma_v4_1_8_blk_mem_64_noreg_be + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Simple_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + true + + + + + + ECC + false + + + + true + + + + + + softecc + false + + + + true + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + 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m_axis_h2c_tuser_2 + + + + + TVALID + + + m_axis_h2c_tvalid_2 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + S_AXIS_C2H_3 + S_AXIS_C2H_3 + + + + + + + TDATA + + + s_axis_c2h_tdata_3 + + + + + TKEEP + + + s_axis_c2h_tkeep_3 + + + + + TLAST + + + s_axis_c2h_tlast_3 + + + + + TREADY + + + s_axis_c2h_tready_3 + + + + + TUSER + + + s_axis_c2h_tuser_3 + + + + + TVALID + + + s_axis_c2h_tvalid_3 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + M_AXIS_H2C_3 + M_AXIS_H2C_3 + + + + + + + TDATA + + + m_axis_h2c_tdata_3 + + + + + TKEEP + + + m_axis_h2c_tkeep_3 + + + + + TLAST + + + m_axis_h2c_tlast_3 + + + + + TREADY + + + m_axis_h2c_tready_3 + + + + + TUSER + + + m_axis_h2c_tuser_3 + + + + + TVALID + + + m_axis_h2c_tvalid_3 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + m_axis_cq + m_axis_cq + The Completer Request interface is used to transmit Completion TLP's to the Client Application + + + + + + + TDATA + + + m_axis_cq_tdata_sd + + + + + TKEEP + + + m_axis_cq_tkeep_sd + + + + + TLAST + + + m_axis_cq_tlast_sd + + + + + TREADY + + + m_axis_cq_tready_sd + + + + + TUSER + + + m_axis_cq_tuser_sd + + + + + TVALID + + + m_axis_cq_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axis_cc + s_axis_cc + The Completer Completion Interface is used to transmit Completion TLP's + + + + + + + TDATA + + + s_axis_cc_tdata_sd + + + + + TKEEP + + + s_axis_cc_tkeep_sd + + + + + TLAST + + + s_axis_cc_tlast_sd + + + + + TREADY + + + s_axis_cc_tready_sd + + + + + TUSER + + + s_axis_cc_tuser_sd + + + + + TVALID + + + s_axis_cc_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axis_rq + s_axis_rq + The Requestor Request interface received requests TLP's from the Client Application + + + + + + + TDATA + + + s_axis_rq_tdata_sd + + + + + TKEEP + + + s_axis_rq_tkeep_sd + + + + + TLAST + + + s_axis_rq_tlast_sd + + + + + TREADY + + + s_axis_rq_tready_sd + + + + + TUSER + + + s_axis_rq_tuser_sd + + + + + TVALID + + + s_axis_rq_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + m_axis_rc + m_axis_rc + The Requestor Completer interface transmits completions to the client application + + + + + + + TDATA + + + m_axis_rc_tdata_sd + + + + + TKEEP + + + m_axis_rc_tkeep_sd + + + + + TLAST + + + m_axis_rc_tlast_sd + + + + + TREADY + + + m_axis_rc_tready_sd + + + + + TUSER + + + m_axis_rc_tuser_sd + + + + + TVALID + + + m_axis_rc_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + pcie4_cfg_mesg_tx + pcie4_cfg_mesg_tx + Configuration Transmit Message Interface + + + + + + + TRANSMIT + + + cfg_msg_transmit_sd + + + + + TRANSMIT_DATA + + + cfg_msg_transmit_data_sd + + + + + TRANSMIT_DONE + + + cfg_msg_transmit_done_sd + + + + + TRANSMIT_TYPE + + + cfg_msg_transmit_type_sd + + + + + + + false + + + + + + pcie4_cfg_mesg_rcvd + pcie4_cfg_mesg_rcvd + Configuration Received Message Interface + + + + + + + recd + + + cfg_msg_received_sd + + + + + recd_data + + + cfg_msg_received_data_sd + + + + + recd_type + + + cfg_msg_received_type_sd + + + + + + + false + + + + + + pcie4_cfg_status + pcie4_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req_sd + + + + + cq_np_req_count + + + pcie_cq_np_req_count_sd + + + + + current_speed + + + cfg_current_speed_sd + + + + + err_cor_out + + + cfg_err_cor_out_sd + + + + + err_fatal_out + + + cfg_err_fatal_out_sd + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out_sd + + + + + function_status + + + cfg_function_status_sd + + + + + local_error_out + + + cfg_local_error_out_sd + + + + + ltssm_state + + + cfg_ltssm_state_sd + + + + + max_payload + + + cfg_max_payload_sd + + + + + max_read_req + + + cfg_max_read_req_sd + + + + + negotiated_width + + + cfg_negotiated_width_sd + + + + + phy_link_down + + + cfg_phy_link_down_sd + + + + + phy_link_status + + + cfg_phy_link_status_sd + + + + + pl_status_change + + + cfg_pl_status_change_sd + + + + + rq_seq_num0 + + + pcie_rq_seq_num0_sd + + + + + rq_seq_num1 + + + pcie_rq_seq_num1_sd + + + + + rq_seq_num_vld0 + + + pcie_rq_seq_num_vld0_sd + + + + + rq_seq_num_vld1 + + + pcie_rq_seq_num_vld1_sd + + + + + tfc_npd_av + + + pcie_tfc_npd_av_sd + + + + + tfc_nph_av + + + pcie_tfc_nph_av_sd + + + + + + + false + + + + + + pcie4_cfg_status_if + pcie4_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req_sd + + + + + cq_np_req_count + + + pcie_cq_np_req_count_sd + + + + + current_speed + + + cfg_current_speed_sd + + + + + err_cor_out + + + cfg_err_cor_out_sd + + + + + err_fatal_out + + + cfg_err_fatal_out_sd + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out_sd + + + + + function_status + + + cfg_function_status_sd + + + + + local_error_out + + + cfg_local_error_out_sd + + + + + ltssm_state + + + cfg_ltssm_state_sd + + + + + max_payload + + + cfg_max_payload_sd + + + + + max_read_req + + + cfg_max_read_req_sd + + + + + negotiated_width + + + cfg_negotiated_width_sd + + + + + phy_link_down + + + cfg_phy_link_down_sd + + + + + phy_link_status + + + cfg_phy_link_status_sd + + + + + pl_status_change + + + cfg_pl_status_change_sd + + + + + rq_seq_num0 + + + pcie_rq_seq_num0_sd + + + + + rq_seq_num1 + + + pcie_rq_seq_num1_sd + + + + + rq_seq_num_vld0 + + + pcie_rq_seq_num_vld0_sd + + + + + rq_seq_num_vld1 + + + pcie_rq_seq_num_vld1_sd + + + + + + + false + + + + + + pcie4_transmit_fc_if + pcie4_transmit_fc + Transmit Flow Control Interfce + + + + + + + npd_av + + + pcie_tfc_npd_av_sd + + + + + nph_av + + + pcie_tfc_nph_av_sd + + + + + + + false + + + + + + pcie4_rbar + pcie4_rbar + Resizable bar Interface + + + + + + + bar_size + + + rbar_bar_size_sd + + + + + function_number + + + rbar_function_number_sd + + + + + write_enable_bar0 + + + rbar_write_enable_bar0_sd + + + + + write_enable_bar1 + + + rbar_write_enable_bar1_sd + + + + + write_enable_bar2 + + + rbar_write_enable_bar2_sd + + + + + write_enable_bar3 + + + rbar_write_enable_bar3_sd + + + + + write_enable_bar4 + + + rbar_write_enable_bar4_sd + + + + + write_enable_bar5 + + + rbar_write_enable_bar5_sd + + + + + + + false + + + + + + pcie4_cfg_control + pcie4_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + ds_bus_number + + + cfg_ds_bus_number_sd + + + + + ds_device_number + + + cfg_ds_device_number_sd + + + + + ds_function_number + + + cfg_ds_function_number_sd + + + + + ds_port_number + + + cfg_ds_port_number_sd + + + + + dsn + + + cfg_dsn_sd + + + + + err_cor_in + + + cfg_err_cor_in_sd + + + + + err_uncor_in + + + cfg_err_uncor_in_sd + + + + + flr_done + + + cfg_flr_done_sd + + + + + flr_in_process + + + cfg_flr_in_process_sd + + + + + hot_reset_out + + + cfg_hot_reset_out_sd + + + + + link_training_enable + + + cfg_link_training_enable_sd + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process_sd + + + + + + + false + + + + + + pcie4_cfg_control_if + pcie4_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + ds_bus_number + + + cfg_ds_bus_number_sd + + + + + ds_device_number + + + cfg_ds_device_number_sd + + + + + ds_function_number + + + cfg_ds_function_number_sd + + + + + ds_port_number + + + cfg_ds_port_number_sd + + + + + dsn + + + cfg_dsn_sd + + + + + err_cor_in + + + cfg_err_cor_in_sd + + + + + err_uncor_in + + + cfg_err_uncor_in_sd + + + + + flr_done + + + cfg_flr_done_sd + + + + + flr_in_process + + + cfg_flr_in_process_sd + + + + + hot_reset_out + + + cfg_hot_reset_out_sd + + + + + link_training_enable + + + cfg_link_training_enable_sd + + + + + rbar_function_number + + + rbar_function_number_sd + + + + + rbar_size + + + rbar_bar_size_sd + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process_sd + + + + + write_enable_rbar0 + + + rbar_write_enable_bar0_sd + + + + + write_enable_rbar1 + + + rbar_write_enable_bar1_sd + + + + + write_enable_rbar2 + + + rbar_write_enable_bar2_sd + + + + + write_enable_rbar3 + + + rbar_write_enable_bar3_sd + + + + + write_enable_rbar4 + + + rbar_write_enable_bar4_sd + + + + + write_enable_rbar5 + + + rbar_write_enable_bar5_sd + + + + + + + false + + + + + + pcie4_cfg_fc + pcie_cfg_fc + Configuration Flow Control INTERFACE + + + + + + + NPH + + + cfg_fc_nph_sd + + + + + SEL + + + cfg_fc_sel_sd + + + + + + + false + + + + + + pcie4_cfg_msi + pcie4_cfg_msi + PCIE MSI interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr_sd + + + + + data + + + cfg_interrupt_msi_data_sd + + + + + enable + + + cfg_interrupt_msi_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msi_int_sd + + + + + mask_update + + + cfg_interrupt_msi_mask_update_sd + + + + + pending_status + + + cfg_interrupt_msi_pending_status_sd + + + + + pending_status_data_enable + + + cfg_interrupt_msi_pending_status_data_enable_sd + + + + + pending_status_function_num + + + cfg_interrupt_msi_pending_status_function_num_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + tph_present + + + cfg_interrupt_msi_tph_present_sd + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag_sd + + + + + tph_type + + + cfg_interrupt_msi_tph_type_sd + + + + + + + false + + + + + + pcie4_cfg_msix_external + pcie4_cfg_msix_external + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_external_msix_with_msi_if + pcie4_cfg_external_msix_with_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_external_msix + pcie4_cfg_external_msix + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_msix_internal + pcie4_cfg_msix_internal + PCIE MSIx Int Interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + mint_vector + + + cfg_interrupt_msi_int_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + tph_present + + + cfg_interrupt_msi_tph_present_sd + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag_sd + + + + + tph_type + + + cfg_interrupt_msi_tph_type_sd + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending_sd + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_msix_internal_if + pcie4_cfg_msix_internal + PCIE MSIx Int Interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + mint_vector + + + cfg_interrupt_msi_int_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + tph_present + + + cfg_interrupt_msi_tph_present_sd + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag_sd + + + + + tph_type + + + cfg_interrupt_msi_tph_type_sd + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending_sd + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_external_msix_without_msi_if + pcie4_cfg_external_msix_without_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_interrupt + pcie4_cfg_interrupt + PCIE Legacy Interrupt + + + + + + + INTx_VECTOR + + + cfg_interrupt_int_sd + + + + + PENDING + + + cfg_interrupt_pending_sd + + + + + SENT + + + cfg_interrupt_sent_sd + + + + + + + false + + + + + + pcie_cfg_mgmt_sd + pcie4_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr_sd + + + + + BYTE_EN + + + cfg_mgmt_byte_enable_sd + + + + + DEBUG_ACCESS + + + cfg_mgmt_type1_cfg_reg_access_sd + + + + + FUNCTION_NUMBER + + + cfg_mgmt_function_number_sd + + + + + READ_DATA + + + cfg_mgmt_read_data_sd + + + + + READ_EN + + + cfg_mgmt_read_sd + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done_sd + + + + + WRITE_DATA + + + cfg_mgmt_write_data_sd + + + + + WRITE_EN + + + cfg_mgmt_write_sd + + + + + + + false + + + + + + pcie_cfg_mgmt_if + pcie4_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr_sd + + + + + BYTE_EN + + + cfg_mgmt_byte_enable_sd + + + + + DEBUG_ACCESS + + + cfg_mgmt_type1_cfg_reg_access_sd + + + + + FUNCTION_NUMBER + + + cfg_mgmt_function_number_sd + + + + + READ_DATA + + + cfg_mgmt_read_data_sd + + + + + READ_EN + + + cfg_mgmt_read_sd + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done_sd + + + + + WRITE_DATA + + + cfg_mgmt_write_data_sd + + + + + WRITE_EN + + + cfg_mgmt_write_sd + + + + + + + false + + + + + + pcie_cfg_mgmt + pcie_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr + + + + + BYTE_EN + + + cfg_mgmt_byte_enable + + + + + READ_DATA + + + cfg_mgmt_read_data + + + + + READ_EN + + + cfg_mgmt_read + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done + + + + + TYPE1_CFG_REG_ACCESS + + + cfg_mgmt_type1_cfg_reg_access + + + + + WRITE_DATA + + + cfg_mgmt_write_data + + + + + WRITE_EN + + + cfg_mgmt_write + + + + + + + true + + + + + + pcie_mgt + pcie_7x_mgt + + + + + + + rxn + + + pci_exp_rxn + + + + + rxp + + + pci_exp_rxp + + + + + txn + + + pci_exp_txn + + + + + txp + + + pci_exp_txp + + + + + + BOARD.ASSOCIATED_PARAM + PCIE_BOARD_INTERFACE + + + + required + + + + + + + + + true + + + + + + drp + drp + DRP interface + + + + + + + DADDR + + + drp_addr + + + + + DEN + + + drp_en + + + + + DI + + + drp_di + + + + + DO + + + drp_do + + + + + DRDY + + + drp_rdy + + + + + DWE + + + drp_we + + + + + + + false + + + + + + pcie_debug_ports + pcie_debug_ports + PCIe Debug Interface + + + + + + + cfg_current_speed + + + cfg_current_speed_o + + + + + cfg_err_cor + + + cfg_err_cor_o + + + + + cfg_err_fatal + + + cfg_err_fatal_o + + + + + cfg_err_nonfatal + + + cfg_err_nonfatal_o + + + + + cfg_local_error + + + cfg_local_error_o + + + + + cfg_local_error_valid + + + cfg_local_error_valid_o + + + + + cfg_ltssm_state + + + cfg_ltssm_state_o + + + + + cfg_negotiated_width + + + cfg_negotiated_width_o + + + + + + + false + + + + + + pcie4_pcie_id + pcie4_pcie_id + PCIE 4 PCIE ID interface + + + + + + + subsys_vend_id + + + cfg_subsys_vend_id + + + + + vend_id + + + cfg_vend_id + + + + + + + false + + + + + + pcie4_pcie_id_pf0 + pcie4_pcie_id_pf0 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf0 + + + cfg_dev_id_pf0 + + + + + rev_id_pf0 + + + cfg_rev_id_pf0 + + + + + subsys_id_pf0 + + + cfg_subsys_id_pf0 + + + + + + + false + + + + + + pcie4_pcie_id_pf1 + pcie4_pcie_id_pf1 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf1 + + + cfg_dev_id_pf1 + + + + + rev_id_pf1 + + + cfg_rev_id_pf1 + + + + + subsys_id_pf1 + + + cfg_subsys_id_pf1 + + + + + + + false + + + + + + pcie4_pcie_id_pf2 + pcie4_pcie_id_pf2 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf2 + + + cfg_dev_id_pf2 + + + + + rev_id_pf2 + + + cfg_rev_id_pf2 + + + + + subsys_id_pf2 + + + cfg_subsys_id_pf2 + + + + + + + false + + + + + + pcie4_pcie_id_pf3 + pcie4_pcie_id_pf3 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf3 + + + cfg_dev_id_pf3 + + + + + rev_id_pf3 + + + cfg_rev_id_pf3 + + + + + subsys_id_pf3 + + + cfg_subsys_id_pf3 + + + + + + + false + + + + + + pcie3_7x_transceiver_debug + pcie3_7x_transceiver_debug + Transceiver Debug Interface of pcie3_7x + + + + + + + cpll_lock + + + pipe_cpll_lock + + + + + debug + + + pipe_debug + + + + + debug_0 + + + pipe_debug_0 + + + + + debug_1 + + + pipe_debug_1 + + + + + debug_2 + + + pipe_debug_2 + + + + + debug_3 + + + pipe_debug_3 + + + + + debug_4 + + + pipe_debug_4 + + + + + debug_5 + + + pipe_debug_5 + + + + + debug_6 + + + pipe_debug_6 + + + + + debug_7 + + + pipe_debug_7 + + + + + debug_8 + + + pipe_debug_8 + + + + + debug_9 + + + pipe_debug_9 + + + + + dmonitorout + + + pipe_dmonitorout + + + + + drp_fsm + + + pipe_drp_fsm + + + + + eyescandataerror + + + pipe_eyescandataerror + + + + + gt_ch_drp_rdy + + + gt_ch_drp_rdy + + + + + loopback + + + pipe_loopback + + + + + qpll_lock + + + pipe_qpll_lock + + + + + qrst_fsm + + + pipe_qrst_fsm + + + + + qrst_idle + + + pipe_qrst_idle + + + + + rate_fsm + + + pipe_rate_fsm + + + + + rate_idle + + + pipe_rate_idle + + + + + rst_fsm + + + pipe_rst_fsm + + + + + rst_idle + + + pipe_rst_idle + + + + + rxbufstatus + + + pipe_rxbufstatus + + + + + rxcommadet + + + pipe_rxcommadet + + + + + rxdisperr + + + pipe_rxdisperr + + + + + rxdlysresetdone + + + pipe_rxdlysresetdone + + + + + rxnotintable + + + pipe_rxnotintable + + + + + rxphaligndone + + + pipe_rxphaligndone + + + + + rxpmaresetdone + + + pipe_rxpmaresetdone + + + + + rxprbscntreset + + + pipe_rxprbscntreset + + + + + rxprbserr + + + pipe_rxprbserr + + + + + rxprbssel + + + pipe_rxprbssel + + + + + rxstatus + + + pipe_rxstatus + + + + + rxsyncdone + + + pipe_rxsyncdone + + + + + sync_fsm_rx + + + pipe_sync_fsm_rx + + + + + sync_fsm_tx + + + pipe_sync_fsm_tx + + + + + txdlysresetdone + + + pipe_txdlysresetdone + + + + + txinhibit + + + pipe_txinhibit + + + + + txphaligndone + + + pipe_txphaligndone + + + + + txphinitdone + + + pipe_txphinitdone + + + + + txprbsforceerr + + + pipe_txprbsforceerr + + + + + txprbssel + + + pipe_txprbssel + + + + + + + false + + + + + + pcie3_us_transceiver_debug + pcie3_us_transceiver_debug + Transceiver Debug Interface of pcie3_us + + + + + + + bufgtdiv + + + gt_bufgtdiv + + + + + cpll_lock + + + gt_cplllock + + + + + dmonfiforeset + + + gt_dmonfiforeset + + + + + dmonitorclk + + + gt_dmonitorclk + + + + + dmonitorout + + + gt_dmonitorout + + + + + eyescandataerror + + + gt_eyescandataerror + + + + + gtpowergood + + + gt_gtpowergood + + + + + loopback + + + gt_loopback + + + + + pcieuserratedone + + + gt_pcieuserratedone + + + + + pcieuserratestart + + + gt_pcieuserratestart + + + + + phystatus + + + gt_phystatus + + + + + prst_n + + + phy_prst_n + + + + + qpll_lock + + + gt_qpll1lock + + + + + rate_idle + + + gt_pcierateidle + + + + + rrst_n + + + phy_rrst_n + + + + + rst_fsm + + + phy_rst_fsm + + + + + rst_idle + + + phy_rst_idle + + + + + rxbufstatus + + + gt_rxbufstatus + + + + + rxcdrlock + + + gt_rxcdrlock + + + + + rxcommadet + + + gt_rxcommadet + + + + + rxdlysresetdone + + + gt_rxdlysresetdone + + + + + rxeq_fsm + + + phy_rxeq_fsm + + + + + rxoutclk + + + gt_rxoutclk + + + + + rxphaligndone + + + gt_rxphaligndone + + + + + rxpmaresetdone + + + gt_rxpmaresetdone + + + + + rxprbscntreset + + + gt_rxprbscntreset + + + + + rxprbserr + + + gt_rxprbserr + + + + + rxprbssel + + + gt_rxprbssel + + + + + rxrecclkout + + + gt_rxrecclkout + + + + + rxresetdone + + + gt_rxresetdone + + + + + rxstatus + + + gt_rxstatus + + + + + rxsyncdone + + + gt_rxsyncdone + + + + + rxvalid + + + gt_rxvalid + + + + + txdlysresetdone + + + gt_txdlysresetdone + + + + + txelecidle + + + gt_txelecidle + + + + + txeq_ctrl + + + phy_txeq_ctrl + + + + + txeq_fsm + + + phy_txeq_fsm + + + + + txeq_preset + + + phy_txeq_preset + + + + + txinhibit + + + gt_txinhibit + + + + + txphaligndone + + + gt_txphaligndone + + + + + txphinitdone + + + gt_txphinitdone + + + + + txprbsforceerr + + + gt_txprbsforceerr + + + + + txprbssel + + + gt_txprbssel + + + + + txresetdone + + + gt_txresetdone + + + + + + + false + + + + + + pcie4_us_plus_transceiver_debug + pcie4_us_plus_transceiver_debug + Transceiver Debug Interface of pcie4_us_plus + + + + + + + bufgtdiv + + + gt_bufgtdiv + + + + + cpll_lock + + + gt_cplllock + + + + + dmonfiforeset + + + gt_dmonfiforeset + + + + + dmonitorclk + + + gt_dmonitorclk + + + + + dmonitorout + + + gt_dmonitorout + + + + + eyescandataerror + + + gt_eyescandataerror + + + + + gen34_eios_det + + + gt_gen34_eios_det + + + + + gtpowergood + + + gt_gtpowergood + + + + + loopback + + + gt_loopback + + + + + pcieuserratedone + + + gt_pcieuserratedone + + + + + pcieuserratestart + + + gt_pcieuserratestart + + + + + phystatus + + + gt_phystatus + + + + + prst_n + + + phy_prst_n + + + + + qpll0_lock + + + gt_qpll0lock + + + + + qpll1_lock + + + gt_qpll1lock + + + + + rate_idle + + + gt_pcierateidle + + + + + rrst_n + + + phy_rrst_n + + + + + rst_fsm + + + phy_rst_fsm + + + + + rst_idle + + + phy_rst_idle + + + + + rxbufreset + + + gt_rxbufreset + + + + + rxbufstatus + + + gt_rxbufstatus + + + + + rxcdrlock + + + gt_rxcdrlock + + + + + rxcdrreset + + + gt_rxcdrreset + + + + + rxcommadet + + + gt_rxcommadet + + + + + rxdfelpmreset + + + gt_rxdfelpmreset + + + + + rxdlysresetdone + + + gt_rxdlysresetdone + + + + + rxeq_fsm + + + phy_rxeq_fsm + + + + + rxoutclk + + + gt_rxoutclk + + + + + rxoutclkfabric + + + gt_rxoutclkfabric + + + + + rxoutclkpcs + + + gt_rxoutclkpcs + + + + + rxpcsreset + + + gt_rxpcsreset + + + + + rxphaligndone + + + gt_rxphaligndone + + + + + rxpmareset + + + gt_rxpmareset + + + + + rxpmaresetdone + + + gt_rxpmaresetdone + + + + + rxprbscntreset + + + gt_rxprbscntreset + + + + + rxprbserr + + + gt_rxprbserr + + + + + rxprbslocked + + + gt_rxprbslocked + + + + + rxprbssel + + + gt_rxprbssel + + + + + rxrecclkout + + + gt_rxrecclkout + + + + + rxresetdone + + + gt_rxresetdone + + + + + rxstatus + + + gt_rxstatus + + + + + rxsyncdone + + + gt_rxsyncdone + + + + + rxvalid + + + gt_rxvalid + + + + + txdlysresetdone + + + gt_txdlysresetdone + + + + + txelecidle + + + gt_txelecidle + + + + + txeq_ctrl + + + phy_txeq_ctrl + + + + + txeq_fsm + + + phy_txeq_fsm + + + + + txeq_preset + + + phy_txeq_preset + + + + + txinhibit + + + gt_txinhibit + + + + + txoutclk + + + gt_txoutclk + + + + + txoutclkfabric + + + gt_txoutclkfabric + + + + + txoutclkpcs + + + gt_txoutclkpcs + + + + + txpcsreset + + + gt_txpcsreset + + + + + txphaligndone + + + gt_txphaligndone + + + + + txphinitdone + + + gt_txphinitdone + + + + + txpmareset + + + gt_txpmareset + + + + + txpmaresetdone + + + gt_txpmaresetdone + + + + + txprbsforceerr + + + gt_txprbsforceerr + + + + + txprbssel + + + gt_txprbssel + + + + + txprogdivresetdone + + + gt_txprogdivresetdone + + + + + txresetdone + + + gt_txresetdone + + + + + txsyncdone + + + gt_txsyncdone + + + + + + + false + + + + + + pcie3_us_gt_if + pcie3_us_gt_if + GT Interface + + + + + + + bufgtce_out + + + bufgtce_us_out + + + + + bufgtcemask_out + + + bufgtcemask_us_out + + + + + bufgtdiv_out + + + bufgtdiv_us_out + + + + + bufgtreset_out + + + bufgtreset_us_out + + + + + bufgtrstmask_out + + + bufgtrstmask_us_out + + + + + cplllock_out + + + cplllock_us_out + + + + + cpllpd_in + + + cpllpd_us_in + + + + + cpllreset_in + + + cpllreset_us_in + + + + + dmonfiforeset_in + + + dmonfiforeset_us_in + + + + + dmonitorclk_in + + + dmonitorclk_us_in + + + + + dmonitorout_out + + + dmonitorout_us_out + + + + + drpaddr_in + + + drpaddr_us_in + + + + + drpclk_in + + + drpclk_us_in + + + + + drpdi_in + + + drpdi_us_in + + + + + drpdo_out + + + drpdo_us_out + + + + + drpen_in + + + drpen_us_in + + + + + drprdy_out + + + drprdy_us_out + + + + + drpwe_in + + + drpwe_us_in + + + + + eyescandataerror_out + + + eyescandataerror_us_out + + + + + eyescanreset_in + + + eyescanreset_us_in + + + + + gthrxn_in + + + gthrxn_us_in + + + + + gthrxp_in + + + gthrxp_us_in + + + + + gthtxn_out + + + gthtxn_us_out + + + + + gthtxp_out + + + gthtxp_us_out + + + + + gtpowergood_out + + + gtpowergood_us_out + + + + + gtrefclk0_in + + + gtrefclk0_us_in + + + + + gtrefclk01_in + + + gtrefclk01_us_in + + + + + gtrxreset_in + + + gtrxreset_us_in + + + + + gttxreset_in + + + gttxreset_us_in + + + + + gtwiz_reset_rx_done_in + + + gtwiz_reset_rx_done_us_in + + + + + gtwiz_reset_tx_done_in + + + gtwiz_reset_tx_done_us_in + + + + + gtwiz_userclk_rx_active_in + + + gtwiz_userclk_rx_active_us_in + + + + + gtwiz_userclk_tx_active_in + + + gtwiz_userclk_tx_active_us_in + + + + + gtwiz_userclk_tx_reset_in + + + gtwiz_userclk_tx_reset_us_in + + + + + loopback_in + + + loopback_us_in + + + + + pcieeqrxeqadaptdone_in + + + pcieeqrxeqadaptdone_us_in + + + + + pcierategen3_out + + + pcierategen3_us_out + + + + + pcierateidle_out + + + pcierateidle_us_out + + + + + pcierateqpllpd_out + + + pcierateqpllpd_us_out + + + + + pcierateqpllreset_out + + + pcierateqpllreset_us_out + + + + + pcierstidle_in + + + pcierstidle_us_in + + + + + pciersttxsyncstart_in + + + pciersttxsyncstart_us_in + + + + + pciesynctxsyncdone_out + + + pciesynctxsyncdone_us_out + + + + + pcieusergen3rdy_out + + + pcieusergen3rdy_us_out + + + + + pcieuserphystatusrst_out + + + pcieuserphystatusrst_us_out + + + + + pcieuserratedone_in + + + pcieuserratedone_us_in + + + + + pcieuserratestart_out + + + pcieuserratestart_us_out + + + + + pcsrsvdin_in + + + pcsrsvdin_us_in + + + + + pcsrsvdout_out + + + pcsrsvdout_us_out + + + + + phystatus_out + + + phystatus_us_out + + + + + qpll0clk_in + + + qpll0clk_us_in + + + + + qpll0refclk_in + + + qpll0refclk_us_in + + + + + qpll1clk_in + + + qpll1clk_us_in + + + + + qpll1lock_out + + + qpll1lock_us_out + + + + + qpll1outclk_out + + + qpll1outclk_us_out + + + + + qpll1outrefclk_out + + + qpll1outrefclk_us_out + + + + + qpll1pd_in + + + qpll1pd_us_in + + + + + qpll1refclk_in + + + qpll1refclk_us_in + + + + + qpll1reset_in + + + qpll1reset_us_in + + + + + qpllrsvd2_in + + + qpllrsvd2_us_in + + + + + qpllrsvd3_in + + + qpllrsvd3_us_in + + + + + rx8b10ben_in + + + rx8b10ben_us_in + + + + + rxbufreset_in + + + rxbufreset_us_in + + + + + rxbufstatus_out + + + rxbufstatus_us_out + + + + + rxbyteisaligned_out + + + rxbyteisaligned_us_out + + + + + rxbyterealign_out + + + rxbyterealign_us_out + + + + + rxcdrhold_in + + + rxcdrhold_us_in + + + + + rxcdrlock_out + + + rxcdrlock_us_out + + + + + rxclkcorcnt_out + + + rxclkcorcnt_us_out + + + + + rxcommadet_out + + + rxcommadet_us_out + + + + + rxcommadeten_in + + + rxcommadeten_us_in + + + + + rxctrl0_out + + + rxctrl0_us_out + + + + + rxctrl1_out + + + rxctrl1_us_out + + + + + rxctrl2_out + + + rxctrl2_us_out + + + + + rxctrl3_out + + + rxctrl3_us_out + + + + + rxdata_out + + + rxdata_us_out + + + + + rxdfeagchold_in + + + rxdfeagchold_us_in + + + + + rxdfecfokhold_in + + + rxdfecfokhold_us_in + + + + + rxdfekhhold_in + + + rxdfekhhold_us_in + + + + + rxdfelfhold_in + + + rxdfelfhold_us_in + + + + + rxdfetap2hold_in + + + rxdfetap2hold_us_in + + + + + rxdfetap3hold_in + + + rxdfetap3hold_us_in + + + + + rxdfetap4hold_in + + + rxdfetap4hold_us_in + + + + + rxdfetap5hold_in + + + rxdfetap5hold_us_in + + + + + rxdfetap6hold_in + + + rxdfetap6hold_us_in + + + + + rxdfetap7hold_in + + + rxdfetap7hold_us_in + + + + + rxdfetap8hold_in + + + rxdfetap8hold_us_in + + + + + rxdfetap9hold_in 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txsyncallin_us_in + + + + + txsyncdone_out + + + txsyncdone_us_out + + + + + txsyncin_in + + + txsyncin_us_in + + + + + txsyncmode_in + + + txsyncmode_us_in + + + + + txsyncout_out + + + txsyncout_us_out + + + + + txuserrdy_in + + + txuserrdy_us_in + + + + + txusrclk2_in + + + txusrclk2_us_in + + + + + txusrclk_in + + + txusrclk_us_in + + + + + + + false + + + + + + pcie4_gt_if + pcie4_gt_if + GT Interface + + + + + + + bufgtce_out + + + bufgtce_usp_out + + + + + bufgtcemask_out + + + bufgtcemask_usp_out + + + + + bufgtdiv_out + + + bufgtdiv_usp_out + + + + + bufgtreset_out + + + bufgtreset_usp_out + + + + + bufgtrstmask_out + + + bufgtrstmask_usp_out + + + + + cpllfreqlock_in + + + cpllfreqlock_usp_in + + + + + cplllock_out + + + cplllock_usp_out + + + + + cpllpd_in + + + cpllpd_usp_in + + + + + cpllreset_in + + + cpllreset_usp_in + + + + + dmonfiforeset_in + + + dmonfiforeset_usp_in + + + + + dmonitorclk_in + + + dmonitorclk_usp_in + + + + + dmonitorout_out + + + dmonitorout_usp_out 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pcierateidle_usp_out + + + + + pcierateqpll0_in + + + pcierateqpll0_usp_in + + + + + pcierateqpll1_in + + + pcierateqpll1_usp_in + + + + + pcierateqpllpd_out + + + pcierateqpllpd_usp_out + + + + + pcierateqpllreset_out + + + pcierateqpllreset_usp_out + + + + + pcierstidle_in + + + pcierstidle_usp_in + + + + + pciersttxsyncstart_in + + + pciersttxsyncstart_usp_in + + + + + pciesynctxsyncdone_out + + + pciesynctxsyncdone_usp_out + + + + + pcieusergen3rdy_out + + + pcieusergen3rdy_usp_out + + + + + pcieuserphystatusrst_out + + + pcieuserphystatusrst_usp_out + + + + + pcieuserratedone_in + + + pcieuserratedone_usp_in + + + + + pcieuserratestart_out + + + pcieuserratestart_usp_out + + + + + phystatus_out + + + phystatus_usp_out + + + + + qpll0freqlock_in + + + qpll0freqlock_usp_in + + + + + qpll0lock_out + + + qpll0lock_usp_out + + + + + qpll0outclk_out + + + qpll0outclk_usp_out + + + + + qpll0outrefclk_out + + + qpll0outrefclk_usp_out + + + + + qpll0pd_in + + + qpll0pd_usp_in + + + + + qpll0reset_in + + + qpll0reset_usp_in + + + + + qpll1freqlock_in + + + qpll1freqlock_usp_in + + + + + qpll1lock_out + + + qpll1lock_usp_out + + + + + qpll1outclk_out + + + qpll1outclk_usp_out + + + + + qpll1outrefclk_out + + + qpll1outrefclk_usp_out + + + + + qpll1pd_in + + + qpll1pd_usp_in + + + + + qpll1reset_in + + + qpll1reset_usp_in + + + + + rcalenb_in + + + rcalenb_usp_in + + + + + resetovrd_in + + + resetovrd_usp_in + + + + + rx8b10ben_in + + + rx8b10ben_usp_in + + + + + rxbufreset_in + + + rxbufreset_usp_in + + + + + rxbufstatus_out + + + rxbufstatus_usp_out + + + + + rxbyteisaligned_out + + + rxbyteisaligned_usp_out + + + + + rxbyterealign_out + + + rxbyterealign_usp_out + + + + + rxcdrfreqreset_in + + + rxcdrfreqreset_usp_in + + + + + rxcdrhold_in + + + rxcdrhold_usp_in + + + + + rxcdrlock_out + + + rxcdrlock_usp_out + + + + + rxcdrreset_in + + + rxcdrreset_usp_in + + + + + rxclkcorcnt_out + + + rxclkcorcnt_usp_out + + + + + rxcommadet_out + + + rxcommadet_usp_out + + + + + rxcommadeten_in + + + rxcommadeten_usp_in + + + + + rxctrl0_out + + + rxctrl0_usp_out + + + + + rxctrl1_out + + + rxctrl1_usp_out + + + + + rxctrl2_out + + + rxctrl2_usp_out + + + + + rxctrl3_out + + + rxctrl3_usp_out + + + + + rxdata_out + + + rxdata_usp_out + + + + + rxdfeagchold_in + + + rxdfeagchold_usp_in + + + + + rxdfecfokhold_in + + + rxdfecfokhold_usp_in + + + + + rxdfekhhold_in + + + rxdfekhhold_usp_in + + + + + rxdfelfhold_in + + + rxdfelfhold_usp_in + + + + + rxdfelpmreset_in + + + rxdfelpmreset_usp_in + + + + + rxdfetap2hold_in + + + rxdfetap2hold_usp_in + + + + + rxdfetap3hold_in + + + rxdfetap3hold_usp_in + + + + + rxdfetap4hold_in + + + rxdfetap4hold_usp_in + + + + + rxdfetap5hold_in + + + rxdfetap5hold_usp_in + + + + + rxdfetap6hold_in + + + rxdfetap6hold_usp_in + + + + + rxdfetap7hold_in + + + rxdfetap7hold_usp_in + + + + + rxdfetap8hold_in + + + rxdfetap8hold_usp_in + + + + + rxdfetap9hold_in + + + rxdfetap9hold_usp_in + + + + + rxdfetap10hold_in + + + rxdfetap10hold_usp_in + + + + + rxdfetap11hold_in + + + rxdfetap11hold_usp_in + + + + + rxdfetap12hold_in + + + rxdfetap12hold_usp_in + + + + + rxdfetap13hold_in + + + rxdfetap13hold_usp_in + + + + + rxdfetap14hold_in + + + rxdfetap14hold_usp_in + + + + + rxdfetap15hold_in + + + rxdfetap15hold_usp_in + + + + + rxdfeuthold_in + + + rxdfeuthold_usp_in + + + + + rxdfevphold_in + + + rxdfevphold_usp_in + + + + + rxdlysresetdone_out + + + rxdlysresetdone_usp_out + + + + + rxelecidle_out + + + rxelecidle_usp_out + + + + + rxlpmen_in + + + rxlpmen_usp_in + + + + + rxlpmgchold_in + + + rxlpmgchold_usp_in + + + + + rxlpmhfhold_in + + + rxlpmhfhold_usp_in + + + + + rxlpmlfhold_in + + + rxlpmlfhold_usp_in + + + + + rxlpmoshold_in + + + rxlpmoshold_usp_in + + + + + rxmcommaalignen_in + + + rxmcommaalignen_usp_in + + + + + rxoshold_in + + + rxoshold_usp_in + + + + + rxoutclk_out + + + rxoutclk_usp_out + + + + + rxoutclkfabric_out + + + rxoutclkfabric_usp_out + + + + + rxoutclkpcs_out + + + rxoutclkpcs_usp_out + + + + + rxpcommaalignen_in + + + rxpcommaalignen_usp_in + + + + + rxpcsreset_in + + + rxpcsreset_usp_in + + + + + rxpd_in + + + rxpd_usp_in + + + + + rxphaligndone_out + + + rxphaligndone_usp_out + + + + + rxpmareset_in + + + rxpmareset_usp_in + + + + + rxpmaresetdone_out + + + rxpmaresetdone_usp_out + + + + + rxpolarity_in + + + rxpolarity_usp_in + + + + + rxprbscntreset_in + + + rxprbscntreset_usp_in + + + + + rxprbserr_out + + + rxprbserr_usp_out + + + + + rxprbslocked_out + + + rxprbslocked_usp_out + + + + + rxprbssel_in + + + rxprbssel_usp_in + + + + + rxprogdivreset_in + + + rxprogdivreset_usp_in + + + + + rxrate_in + + + rxrate_usp_in + + + + + rxratedone_out + + + rxratedone_usp_out + + + + + rxratemode_in + + + rxratemode_usp_in + + + + + rxrecclkout_out + + + rxrecclkout_usp_out + + + + + rxresetdone_out + + + rxresetdone_usp_out + + + + + rxslide_in + + + rxslide_usp_in + + + + + rxstatus_out + + + rxstatus_usp_out + + + + + rxsyncdone_out + + + rxsyncdone_usp_out + + + + + rxtermination_in + + + rxtermination_usp_in + + + + + rxuserrdy_in + + + rxuserrdy_usp_in + + + + + rxusrclk2_in + + + rxusrclk2_usp_in + + + + + rxusrclk_in + + + rxusrclk_usp_in + + + + + rxvalid_out + + + rxvalid_usp_out + + + + + tx8b10ben_in + + + tx8b10ben_usp_in + + + + + txctrl0_in + + + txctrl0_usp_in + + + + + txctrl1_in + + + txctrl1_usp_in + + + + + txctrl2_in + + + txctrl2_usp_in + + + + + txdata_in + + + txdata_usp_in + + + + + txdeemph_in + + + txdeemph_usp_in + + + + + txdetectrx_in + + + txdetectrx_usp_in + + + + + txdiffctrl_in + + + txdiffctrl_usp_in + + + + + txdlybypass_in + + + txdlybypass_usp_in + + + + + txdlyen_in + + + txdlyen_usp_in + + + + + txdlyhold_in + + + txdlyhold_usp_in + + + + + txdlyovrden_in + + + txdlyovrden_usp_in + + + + + txdlysreset_in + + + txdlysreset_usp_in + + + + + txdlysresetdone_out + + + txdlysresetdone_usp_out + + + + + txdlyupdown_in + + + txdlyupdown_usp_in + + + + + txelecidle_in + + + txelecidle_usp_in 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txpmaresetdone_out + + + txpmaresetdone_usp_out + + + + + txpostcursor_in + + + txpostcursor_usp_in + + + + + txprbsforceerr_in + + + txprbsforceerr_usp_in + + + + + txprbssel_in + + + txprbssel_usp_in + + + + + txprecursor_in + + + txprecursor_usp_in + + + + + txprgdivresetdone_out + + + txprgdivresetdone_usp_out + + + + + txprogdivreset_in + + + txprogdivreset_usp_in + + + + + txrate_in + + + txrate_usp_in + + + + + txresetdone_out + + + txresetdone_usp_out + + + + + txswing_in + + + txswing_usp_in + + + + + txsyncallin_in + + + txsyncallin_usp_in + + + + + txsyncdone_out + + + txsyncdone_usp_out + + + + + txsyncin_in + + + txsyncin_usp_in + + + + + txsyncmode_in + + + txsyncmode_usp_in + + + + + txsyncout_out + + + txsyncout_usp_out + + + + + txuserrdy_in + + + txuserrdy_usp_in + + + + + txusrclk2_in + + + txusrclk2_usp_in + + + + + txusrclk_in + + + txusrclk_usp_in + + + + + + + false + + + + + + pcie_ext_ch_gt + pcie_ext_ch_gt + GT DRP interface + + + + + + + DADDR + + + ext_ch_gt_drpaddr + + + + + DEN + + + ext_ch_gt_drpen + + + + + DI + + + ext_ch_gt_drpdi + + + + + DO + + + ext_ch_gt_drpdo + + + + + DRDY + + + ext_ch_gt_drprdy + + + + + DWE + + + ext_ch_gt_drpwe + + + + + + + false + + + + + + pcie_cfg_ext + pcie4_cfg_ext + Configuration Extend Interface + + + + + + + function_number + + + cfg_ext_function_number + + + + + read_data + + + cfg_ext_read_data + + + + + read_data_valid + + + cfg_ext_read_data_valid + + + + + read_received + + + cfg_ext_read_received + + + + + register_number + + + cfg_ext_register_number + + + + + write_byte_enable + + + cfg_ext_write_byte_enable + + + + + write_data + + + cfg_ext_write_data + + + + + write_received + + + cfg_ext_write_received + + + + + + + false + + + + + + CLK.ext_ch_gt_drpclk + + + + + + + CLK + + + ext_ch_gt_drpclk + + + + + + ASSOCIATED_BUSIF + pcie_ext_ch_gt + + + FREQ_HZ + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + pcie_ext_pipe_rp_usp + pcie3_ext_pipe_rp_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_in + + + + + COMMANDS_OUT + + + common_commands_out + + + + + RX_0 + + + pipe_rx_0_sigs + + + + + RX_1 + + + pipe_rx_1_sigs + + + + + RX_2 + + + pipe_rx_2_sigs + + + + + RX_3 + + + pipe_rx_3_sigs + + + + + RX_4 + + + pipe_rx_4_sigs + + + + + RX_5 + + + pipe_rx_5_sigs + + + + + RX_6 + + + pipe_rx_6_sigs + + + + + RX_7 + + + pipe_rx_7_sigs + + + + + RX_8 + + + pipe_rx_8_sigs + + + + + RX_9 + + + pipe_rx_9_sigs + + + + + RX_10 + + + pipe_rx_10_sigs + + + + + RX_11 + + + pipe_rx_11_sigs + + + + + RX_12 + + + pipe_rx_12_sigs + + + + + RX_13 + + + pipe_rx_13_sigs + + + + + RX_14 + + + pipe_rx_14_sigs + + + + + RX_15 + + + pipe_rx_15_sigs + + + + + TX_0 + + + pipe_tx_0_sigs + + + + + TX_1 + + + pipe_tx_1_sigs + + + + + TX_2 + + + pipe_tx_2_sigs + + + + + TX_3 + + + pipe_tx_3_sigs + + + + + TX_4 + + + pipe_tx_4_sigs + + + + + TX_5 + + + pipe_tx_5_sigs + + + + + TX_6 + + + pipe_tx_6_sigs + + + + + TX_7 + + + pipe_tx_7_sigs + + + + + TX_8 + + + pipe_tx_8_sigs + + + + + TX_9 + + + pipe_tx_9_sigs + + + + + TX_10 + + + pipe_tx_10_sigs + + + + + TX_11 + + + pipe_tx_11_sigs + + + + + TX_12 + + + pipe_tx_12_sigs + + + + + TX_13 + + + pipe_tx_13_sigs + + + + + TX_14 + + + pipe_tx_14_sigs + + + + + TX_15 + + + pipe_tx_15_sigs + + + + + + + false + + + + + + pcie_ext_pipe_ep_usp + pcie3_ext_pipe_ep_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + RX_8 + + + pipe_tx_8_sigs + + + + + RX_9 + + + pipe_tx_9_sigs + + + + + RX_10 + + + pipe_tx_10_sigs + + + + + RX_11 + + + pipe_tx_11_sigs + + + + + RX_12 + + + pipe_tx_12_sigs + + + + + RX_13 + + + pipe_tx_13_sigs + + + + + RX_14 + + + pipe_tx_14_sigs + + + + + RX_15 + + + pipe_tx_15_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + TX_8 + + + pipe_rx_8_sigs + + + + + TX_9 + + + pipe_rx_9_sigs + + + + + TX_10 + + + pipe_rx_10_sigs + + + + + TX_11 + + + pipe_rx_11_sigs + + + + + TX_12 + + + pipe_rx_12_sigs + + + + + TX_13 + + + pipe_rx_13_sigs + + + + + TX_14 + + + pipe_rx_14_sigs + + + + + TX_15 + + + pipe_rx_15_sigs + + + + + + + false + + + + + + pcie_ext_pipe_ep_legacy_usp + pcie3_ext_pipe_ep_legacy_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + RX_8 + + + pipe_tx_8_sigs + + + + + RX_9 + + + pipe_tx_9_sigs + + + + + RX_10 + + + pipe_tx_10_sigs + + + + + RX_11 + + + pipe_tx_11_sigs + + + + + RX_12 + + + pipe_tx_12_sigs + + + + + RX_13 + + + pipe_tx_13_sigs + + + + + RX_14 + + + pipe_tx_14_sigs + + + + + RX_15 + + + pipe_tx_15_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + TX_8 + + + pipe_rx_8_sigs + + + + + TX_9 + + + pipe_rx_9_sigs + + + + + TX_10 + + + pipe_rx_10_sigs + + + + + TX_11 + + + pipe_rx_11_sigs + + + + + TX_12 + + + pipe_rx_12_sigs + + + + + TX_13 + + + pipe_rx_13_sigs + + + + + TX_14 + + + pipe_rx_14_sigs + + + + + TX_15 + + + pipe_rx_15_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_rp + pcie3_ext_pipe_rp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_in + + + + + COMMANDS_OUT + + + common_commands_out + + + + + RX_0 + + + pipe_rx_0_sigs + + + + + RX_1 + + + pipe_rx_1_sigs + + + + + RX_2 + + + pipe_rx_2_sigs + + + + + RX_3 + + + pipe_rx_3_sigs + + + + + RX_4 + + + pipe_rx_4_sigs + + + + + RX_5 + + + pipe_rx_5_sigs + + + + + RX_6 + + + pipe_rx_6_sigs + + + + + RX_7 + + + pipe_rx_7_sigs + + + + + TX_0 + + + pipe_tx_0_sigs + + + + + TX_1 + + + pipe_tx_1_sigs + + + + + TX_2 + + + pipe_tx_2_sigs + + + + + TX_3 + + + pipe_tx_3_sigs + + + + + TX_4 + + + pipe_tx_4_sigs + + + + + TX_5 + + + pipe_tx_5_sigs + + + + + TX_6 + + + pipe_tx_6_sigs + + + + + TX_7 + + + pipe_tx_7_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_ep + pcie3_ext_pipe_ep + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_ep_legacy + pcie3_ext_pipe_ep_legacy + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + + + false + + + + + + dsc_bypass_c2h_0 + dsc_bypass_c2h_0 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_0 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_0 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_0 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_0 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_0 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_0 + + + + + + + false + + + + + + dsc_bypass_c2h_1 + dsc_bypass_c2h_1 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_1 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_1 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_1 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_1 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_1 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_1 + + + + + + + false + + + + + + dsc_bypass_c2h_2 + dsc_bypass_c2h_2 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_2 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_2 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_2 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_2 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_2 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_2 + + + + + + + false + + + + + + dsc_bypass_c2h_3 + dsc_bypass_c2h_3 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_3 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_3 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_3 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_3 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_3 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_3 + + + + + + + false + + + + + + dsc_bypass_h2c_0 + dsc_bypass_h2c_0 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_0 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_0 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_0 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_0 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_0 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_0 + + + + + + + false + + + + + + dsc_bypass_h2c_1 + dsc_bypass_h2c_1 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_1 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_1 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_1 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_1 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_1 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_1 + + + + + + + false + + + + + + dsc_bypass_h2c_2 + dsc_bypass_h2c_2 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_2 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_2 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_2 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_2 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_2 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_2 + + + + + + + false + + + + + + dsc_bypass_h2c_3 + dsc_bypass_h2c_3 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_3 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_3 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_3 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_3 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_3 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_3 + + + + + + + false + + + + + + dma_status_ports + dma_status_ports + XDMA Status Ports Interface + + + + + + + c2h_sts0 + + + c2h_sts_0 + + + + + c2h_sts1 + + + c2h_sts_1 + + + + + c2h_sts2 + + + c2h_sts_2 + + + + + c2h_sts3 + + + c2h_sts_3 + + + + + h2c_sts0 + + + h2c_sts_0 + + + + + h2c_sts1 + + + h2c_sts_1 + + + + + h2c_sts2 + + + h2c_sts_2 + + + + + h2c_sts3 + + + h2c_sts_3 + + + + + + + false + + + + + + cap + cap + + + + + + + GNT + + + cap_gnt + + + + + REL + + + cap_rel + + + + + REQ + + + cap_req + + + + + + + false + + + + + + startup + startup + STARTUP Interface + + + + + + + cfgclk + + + startup_cfgclk + + + + + cfgmclk + + + startup_cfgmclk + + + + + di + + + startup_di + + + + + do + + + startup_do + + + + + dts + + + startup_dts + + + + + eos + + + startup_eos + + + + + fcsbo + + + startup_fcsbo + + + + + fcsbts + + + startup_fcsbts + + + + + gsr + + + startup_gsr + + + + + gts + + + startup_gts + + + + + keyclearb + + + startup_keyclearb + + + + + pack + + + startup_pack + + + + + preq + + + startup_preq + + + + + userdoneo + + + startup_usrdoneo + + + + + usrcclko + + + startup_usrcclko + + + + + usrclkts + + + startup_usrcclkts + + + + + usrdonets + + + startup_usrdonets + + + + + + + false + + + + + + atspri_s_axis_rq + atspri_s_axis_rq + The Requestor Request interface received requests TLP's from the Client Application + + + + + + + TDATA + + + atspri_s_axis_rq_tdata + + + + + TKEEP + + + atspri_s_axis_rq_tkeep + + + + + TLAST + + + atspri_s_axis_rq_tlast + + + + + TREADY + + + atspri_s_axis_rq_tready + + + + + TUSER + + + atspri_s_axis_rq_tuser + + + + + TVALID + + + atspri_s_axis_rq_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + atspri_m_axis_cq + atspri_m_axis_cq + The Completer Request interface is used to transmit Completion TLP's to the Client Application + + + + + + + TDATA + + + atspri_m_axis_cq_tdata + + + + + TKEEP + + + atspri_m_axis_cq_tkeep + + + + + TLAST + + + atspri_m_axis_cq_tlast + + + + + TREADY + + + atspri_m_axis_cq_tready + + + + + TUSER + + + atspri_m_axis_cq_tuser + + + + + TVALID + + + atspri_m_axis_cq_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + 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m_axis_cc_tlast_out + + + + + cc_tready_out + + + m_axis_cc_tready_out + + + + + cc_tuser_out + + + m_axis_cc_tuser_out + + + + + cc_tvalid_out + + + m_axis_cc_tvalid_out + + + + + cq_tdata_out + + + s_axis_cq_tdata_out + + + + + cq_tkeep_out + + + s_axis_cq_tkeep_out + + + + + cq_tlast_out + + + s_axis_cq_tlast_out + + + + + cq_tready_out + + + s_axis_cq_tready_out + + + + + cq_tuser_out + + + s_axis_cq_tuser_out + + + + + cq_tvalid_out + + + s_axis_cq_tvalid_out + + + + + rc_tdata_out + + + s_axis_rc_tdata_out + + + + + rc_tkeep_out + + + s_axis_rc_tkeep_out + + + + + rc_tlast_out + + + s_axis_rc_tlast_out + + + + + rc_tready_out + + + s_axis_rc_tready_out + + + + + rc_tuser_out + + + s_axis_rc_tuser_out + + + + + rc_tvalid_out + + + s_axis_rc_tvalid_out + + + + + rq_tdata_out + + + m_axis_rq_tdata_out + + + + + rq_tkeep_out + + + m_axis_rq_tkeep_out + + + + + rq_tlast_out + + + m_axis_rq_tlast_out + + + + + rq_tready_out + + + m_axis_rq_tready_out + + + + + rq_tuser_out + + + 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Pf0 Revision Id + 0x00 + + + PF0_SUBSYSTEM_VENDOR_ID + Pf0 Subsystem Vendor Id + 0x10EE + + + PF0_SUBSYSTEM_ID + Pf0 Subsystem Id + 0x0007 + + + PF0_CLASS_CODE + Pf0 Class Code + 0x070001 + + + PF1_VENDOR_ID + pf1 Vendor Id + 0x10EE + + + PF1_DEVICE_ID + Pf1 Device Id + 0x9111 + + + PF1_REVISION_ID + Pf1 Revision Id + 0x00 + + + PF1_SUBSYSTEM_VENDOR_ID + Pf1 Subsystem Vendor Id + 0x10EE + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0x0007 + + + PF1_CLASS_CODE + Pf1 Class Code + 0x070001 + + + PF2_DEVICE_ID + Pf2 Device Id + 0x9211 + + + PF2_REVISION_ID + Pf2 Revision Id + 0x00 + + + PF2_SUBSYSTEM_ID + Pf3 Subsystem Id + 0x0007 + + + PF3_DEVICE_ID + Pf3 Device Id + 0x9311 + + + PF3_REVISION_ID + Pf3 Revision Id + 0x00 + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0x0007 + + + AXILITE_MASTER_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x0D + + + AXILITE_MASTER_CONTROL + Pf0 Bar0 Control + 0x0 + + + XDMA_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x09 + + + XDMA_CONTROL + Pf0 Bar1 Control + 0x4 + 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XDMA_AXIST_BYPASS + FALSE + + + XDMA_RNUM_CHNL + 1 + + + XDMA_WNUM_CHNL + 1 + + + XDMA_AXILITE_SLAVE + FALSE + + + XDMA_NUM_USR_IRQ + 1 + + + XDMA_RNUM_RIDS + 32 + + + XDMA_WNUM_RIDS + 16 + + + C_M_AXI_ID_WIDTH + 4 + + + C_AXIBAR_NUM + 1 + + + C_FAMILY + virtexuplus + + + XDMA_NUM_PCIE_TAG + 256 + + + EN_AXI_MASTER_IF + Enable AXI Master IF + TRUE + + + EN_WCHNL_0 + TRUE + + + EN_WCHNL_1 + FALSE + + + EN_WCHNL_2 + FALSE + + + EN_WCHNL_3 + FALSE + + + EN_WCHNL_4 + FALSE + + + EN_WCHNL_5 + FALSE + + + EN_WCHNL_6 + FALSE + + + EN_WCHNL_7 + FALSE + + + EN_RCHNL_0 + TRUE + + + EN_RCHNL_1 + FALSE + + + EN_RCHNL_2 + FALSE + + + EN_RCHNL_3 + FALSE + + + EN_RCHNL_4 + FALSE + + + EN_RCHNL_5 + FALSE + + + EN_RCHNL_6 + FALSE + + + EN_RCHNL_7 + FALSE + + + XDMA_DSC_BYPASS + FALSE + + + C_METERING_ON + 1 + + + RX_DETECT + Receiver Detect + 0 + + + C_ATS_ENABLE + ATS Extended Capability Enable + FALSE + + + C_ATS_CAP_NEXTPTR + 0x000 + + + C_PR_CAP_NEXTPTR + 0x000 + + + C_PRI_ENABLE + Page Request Extended Capability Enable + FALSE + + + DSC_BYPASS_RD + 0 + + + DSC_BYPASS_WR + 0 + + + XDMA_STS_PORTS + FALSE + + + MSIX_ENABLED + FALSE + + + WR_CH0_ENABLED + FALSE + + + WR_CH1_ENABLED + FALSE + + + WR_CH2_ENABLED + FALSE + + + WR_CH3_ENABLED + FALSE + + + RD_CH0_ENABLED + FALSE + + + RD_CH1_ENABLED + FALSE + + + RD_CH2_ENABLED + FALSE + + + RD_CH3_ENABLED + FALSE + + + CFG_MGMT_IF + TRUE + + + RQ_SEQ_NUM_IGNORE + 0 + + + CFG_EXT_IF + FALSE + + + LEGACY_CFG_EXT_IF + FALSE + + + C_PARITY_CHECK + 0 + + + C_PARITY_GEN + 0 + + + C_PARITY_PROP + 0 + + + C_ECC_ENABLE + 0 + + + EN_DEBUG_PORTS + FALSE + + + VU9P_BOARD + FALSE + + + ENABLE_JTAG_DBG + FALSE + + + ENABLE_LTSSM_DBG + FALSE + + + ENABLE_IBERT + false + + + MM_SLAVE_EN + 0 + + + DMA_EN + 1 + + + C_AXIBAR_0 + 0x0000000000000000 + + + C_AXIBAR_1 + 0x0000000000000000 + + + C_AXIBAR_2 + 0x0000000000000000 + + + C_AXIBAR_3 + 0x0000000000000000 + + + C_AXIBAR_4 + 0x0000000000000000 + + + C_AXIBAR_5 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_0 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_1 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_2 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_3 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_4 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_5 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_0 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_1 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_2 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_3 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_4 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_5 + 0x0000000000000000 + + + EN_AXI_SLAVE_IF + Enable AXI Slave IF + TRUE + + + C_INCLUDE_BAROFFSET_REG + 1 + + + C_BASEADDR + 0x00001000 + + + C_HIGHADDR + 0x00001FFF + + + C_S_AXI_ID_WIDTH + 4 + + + C_S_AXI_NUM_READ + AXI Address width + 8 + + + C_M_AXI_NUM_READ + AXI Address width + 8 + + + C_M_AXI_NUM_READQ + AXI Address width + 2 + + + C_S_AXI_NUM_WRITE + AXI Address width + 8 + + + C_M_AXI_NUM_WRITE + AXI Address width + 16 + + + C_M_AXI_NUM_WRITE_SCALE + AXI Address width + 1 + + + MSIX_IMPL_EXT + FALSE + + + AXI_ACLK_LOOPBACK + FALSE + + + PF0_BAR0_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x0A + + + PF0_BAR0_CONTROL + Pf0 Bar0 Control + 0x4 + + + PF0_BAR1_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x05 + + + PF0_BAR1_CONTROL + Pf0 Bar1 Control + 0x0 + + + PF0_BAR2_APERTURE_SIZE + Pf0 Bar2 Aperture Size + 0x05 + + + PF0_BAR2_CONTROL + Pf0 Bar2 Control + 0x0 + + + PF0_BAR3_APERTURE_SIZE + Pf0 Bar3 Aperture Size + 0x05 + + + PF0_BAR3_CONTROL + Pf0 Bar3 Control + 0x0 + + + PF0_BAR4_APERTURE_SIZE + Pf0 Bar4 Aperture Size + 0x05 + + + PF0_BAR4_CONTROL + Pf0 Bar4 Control + 0x0 + + + PF0_BAR5_APERTURE_SIZE + Pf0 Bar5 Aperture Size + 0x05 + + + PF0_BAR5_CONTROL + Pf0 Bar5 Control + 0x0 + + + PF0_EXPANSION_ROM_APERTURE_SIZE + Pf0 Expansion Rom Aperture Size + 0x000 + + + PF0_EXPANSION_ROM_ENABLE + Pf0 Expansion Rom Enable + FALSE + + + PCIEBAR_NUM + 6 + + + C_PCIEBAR2AXIBAR_0 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_1 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_2 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_3 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_4 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_5 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_6 + 0x0000000000000000 + + + BARLITE1 + 0 + + + BARLITE2 + 7 + + + VCU118_BOARD + FALSE + + + SPLIT_DMA + FALSE + + + USE_STANDARD_INTERFACES + FALSE + + + DMA_2RP + FALSE + + + SRIOV_ACTIVE_VFS + 252 + + + PIPE_LINE_STAGE + 2 + + + AXIS_PIPE_LINE_STAGE + 0 + + + MULT_PF_DES + FALSE + + + PF_SWAP + FALSE + + + PF0_MSIX_TAR_ID + PF0 MSIX target ID + 0x08 + + + PF1_MSIX_TAR_ID + PF1 MSIX target ID + 0x09 + + + RUNBIT_FIX + FALSE + + + USRINT_EXPN + FALSE + + + xlnx_ref_board + AU200 + + + GTWIZ_IN_CORE + 1 + + + GTCOM_IN_CORE + 2 + + + INS_LOSS_PROFILE + Add-in_Card + + + FUNC_MODE + 1 + + + PF1_ENABLED + 0 + + + DMA_RESET_SOURCE_SEL + 0 + + + PF1_BAR0_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x12 + + + PF1_BAR0_CONTROL + Pf0 Bar0 Control + 0x4 + + + PF1_BAR1_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x0A + + + PF1_BAR1_CONTROL + Pf0 Bar1 Control + 0x0 + + + PF1_BAR2_APERTURE_SIZE + Pf0 Bar2 Aperture Size + 0x0A + + + PF1_BAR2_CONTROL + Pf0 Bar2 Control + 0x6 + + + PF1_BAR3_APERTURE_SIZE + Pf0 Bar3 Aperture Size + 0x0A + + + PF1_BAR3_CONTROL + Pf0 Bar3 Control + 0x0 + + + PF1_BAR4_APERTURE_SIZE + Pf0 Bar4 Aperture Size + 0x0A + + + PF1_BAR4_CONTROL + Pf0 Bar4 Control + 0x6 + + + PF1_BAR5_APERTURE_SIZE + Pf0 Bar5 Aperture Size + 0x0A + + + PF1_BAR5_CONTROL + Pf0 Bar5 Control + 0x0 + + + PF1_EXPANSION_ROM_APERTURE_SIZE + Pf1 Expansion Rom Aperture Size + 0x000 + + + PF1_EXPANSION_ROM_ENABLE + Pf1 Expansion Rom Enable + FALSE + + + PF1_PCIEBAR2AXIBAR_0 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_1 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_2 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_3 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_4 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_5 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_6 + 0x0000000000000000 + + + C_MSIX_INT_TABLE_EN + 0 + + + VU9P_TUL_EX + VU9P TUL board + FALSE + + + PCIE_BLK_TYPE + 0 + + + CCIX_ENABLE + Ccix Enable + FALSE + + + CCIX_DVSEC + Ccix Dvsec Enable + FALSE + + + EXT_SYS_CLK_BUFG + FALSE + + + C_NUM_OF_SC + 1 + + + USR_IRQ_EXDES + FALSE + + + AXI_VIP_IN_EXDES + FALSE + + + PIPE_DEBUG_EN + FALSE + + + XDMA_NON_INCREMENTAL_EXDES + FALSE + + + XDMA_ST_INFINITE_DESC_EXDES + FALSE + + + EXT_XVC_VSEC_ENABLE + Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design + FALSE + + + ACS_EXT_CAP_ENABLE + FALSE + + + EN_PCIE_DEBUG_PORTS + FALSE + + + MULTQ_EN + 0 + + + DMA_MM + 0 + + + DMA_ST + 1 + + + C_PCIE_PFS_SUPPORTED + 0 + + + C_SRIOV_EN + 0 + + + BARLITE_EXT_PF0 + 0x00 + + + BARLITE_EXT_PF1 + 0x00 + + + BARLITE_EXT_PF2 + 0x00 + + + BARLITE_EXT_PF3 + 0x00 + + + BARLITE_INT_PF0 + 0x01 + + + BARLITE_INT_PF1 + 0x00 + + + BARLITE_INT_PF2 + 0x00 + + + BARLITE_INT_PF3 + 0x00 + + + NUM_VFS_PF0 + 0 + + + NUM_VFS_PF1 + 0 + + + NUM_VFS_PF2 + 0 + + + NUM_VFS_PF3 + 0 + + + FIRSTVF_OFFSET_PF0 + 0 + + + FIRSTVF_OFFSET_PF1 + 0 + + + FIRSTVF_OFFSET_PF2 + 0 + + + FIRSTVF_OFFSET_PF3 + 0 + + + VF_BARLITE_EXT_PF0 + 0x00 + + + VF_BARLITE_EXT_PF1 + 0x00 + + + VF_BARLITE_EXT_PF2 + 0x00 + + + VF_BARLITE_EXT_PF3 + 0x00 + + + VF_BARLITE_INT_PF0 + 0x01 + + + VF_BARLITE_INT_PF1 + 0x01 + + + VF_BARLITE_INT_PF2 + 0x01 + + + VF_BARLITE_INT_PF3 + 0x01 + + + C_C2H_NUM_CHNL + 1 + + + C_H2C_NUM_CHNL + 1 + + + H2C_XDMA_CHNL + 0x0F + + + C2H_XDMA_CHNL + 0x0F + + + AXISTEN_IF_ENABLE_MSG_ROUTE + 0x00000 + + + ENABLE_MORE + FALSE + + + DISABLE_BRAM_PIPELINE + FALSE + + + DISABLE_EQ_SYNCHRONIZER + FALSE + + + C_ENABLE_RESOURCE_REDUCTION + FALSE + + + GEN4_EIEOS_0S7 + TRUE + + + C_S_AXI_SUPPORTS_NARROW_BURST + 0 + + + ENABLE_ATS_SWITCH + ATS Switch Enable + FALSE + + + C_ATS_SWITCH_UNIQUE_BDF + 1 + + + C_LAST_CORE_CAP_ADDR + 0x100 + + + C_VSEC_CAP_ADDR + 0x128 + + + SOFT_RESET_EN + FALSE + + + INTERRUPT_OUT_WIDTH + 1 + + + C_MSI_RX_PIN_EN + 0 + + + C_MSIX_RX_PIN_EN + 1 + + + C_INTX_RX_PIN_EN + 1 + + + MSIX_RX_DECODE_EN + FALSE + + + PCIE_ID_IF + FALSE + + + TL_PF_ENABLE_REG + 0 + + + AXSIZE_BYTE_ACCESS_EN + FALSE + + + SPLIT_DMA_SINGLE_PF + FALSE + + + RBAR_ENABLE + FALSE + + + C_SMMU_EN + 0 + + + C_M_AXI_AWUSER_WIDTH + 8 + + + C_M_AXI_ARUSER_WIDTH + 8 + + + C_SLAVE_READ_64OS_EN + 0 + + + FLR_ENABLE + FLR Enable + FALSE + + + SHELL_BRIDGE + 0 + + + MSIX_PCIE_INTERNAL + 0 + + + + + + choice_list_03bd623c + BAR_0 + BAR_1 + BAR_3:2 + BAR_5:4 + + + choice_list_08bf412c + 128 + 256 + 512 + + + choice_list_0be33969 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + + + choice_list_0d378f84 + Simple_communication_controllers + Device_was_built_before_Class_Code_definitions_were_finalized + Mass_storage_controller + Network_controller + Display_controller + Multimedia_device + Memory_controller + Base_system_peripherals + Input_devices + Docking_stations + Processors + Serial_bus_controllers + Wireless_controller + Intelligent_I/O_controllers + Satellite_communication_controllers + Processing_accelerators + + + choice_list_0f93492c + Chip-to-Chip + Add-in_Card + Backplane + + + choice_list_110bd32e + 2 + 4 + + + choice_list_1cfc6134 + 1 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_1e9fb93b + X1 + X2 + X4 + X8 + X16 + + + choice_list_24b724fb + Basic + Advanced + + + choice_list_2dba17cd + None + Check_Parity + Propagate_Parity + + + choice_list_34d65ff4 + 128 + + + choice_list_35d06715 + 2 + + + choice_list_38306dd1 + SOFT + HARD + + + choice_list_3ca2cbc7 + BAR_0 + + + choice_list_3cee6ea1 + 16450_compatible_serial_controller + 16550_compatible_serial_controller + 16650_compatible_serial_controller + 16750_compatible_serial_controller + 16850_compatible_serial_controller + 16950_compatible_serial_controller + Bi_directional_parallel_port + ECP_1.X_compliant_parallel_port + GPIB(IEEE_488.1/2)_controller + Generic_XT_compatible_serial_controller + Generic_modem + Hayes_compatible_modem_with_16450_compatible_interface + Hayes_compatible_modem_with_16550_compatible_interface + Hayes_compatible_modem_with_16650_compatible_interface + Hayes_compatible_modem_with_16750_compatible_interface + IEEE_1284_controller + IEEE_1284_target_device + Multiport_serial_controller + Other_communications_device + Parallel_port + Smart_Card + + + choice_list_4665eb01 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_list_47140c0d + 0000 + 0001 + + + choice_list_4e419c85 + Default + Falling_Edge + + + choice_list_52d29139 + Bytes + Kilobytes + Megabytes + Gigabytes + + + choice_list_574f38f3 + 2.5_GT/s + 5.0_GT/s + 8.0_GT/s + + + choice_list_57749bc8 + DMA + + + choice_list_589df8e9 + RAM + Other_memory_controller + Flash + + + choice_list_5e150e6c + 50us + 50ms + + + choice_list_5e2921cd + Kilobytes + + + choice_list_5e45706a + 1_vector + 2_vectors + 4_vectors + 8_vectors + 16_vectors + 32_vectors + + + choice_list_640e51e1 + DMA + AXI_Bridge + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_6a0870a7 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + 30 + 31 + + + choice_list_6b979ebc + 250 + + + choice_list_6eff49bd + ACTIVE_LOW + ACTIVE_HIGH + + + choice_list_7a7dde49 + true + false + + + choice_list_8061eec5 + None + Tandem_PROM + Tandem_PCIe + Tandem_PCIe_with_Field_Updates + DFX_over_PCIe + + + choice_list_8112d406 + 8 + 16 + 32 + + + choice_list_81ddc592 + Kilobytes + Megabytes + Gigabytes + Terabytes + Petabytes + Exabytes + + + choice_list_847d868a + 1 + 2 + 3 + 4 + 5 + 6 + + + choice_list_86c5d341 + 500 + + + choice_list_88156f2e + QPLL1 + QPLL0 + + + choice_list_8a9e69a3 + AXI_Lite_Master + DMA + + + choice_list_8aad6ae4 + 1 + 2 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_8b5e4915 + 4 + 5 + + + choice_list_8eea463a + X1Y2 + X1Y4 + + + choice_list_914704bd + 100_MHz + 125_MHz + + + choice_list_91b49d0b + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + + + choice_list_96d6a000 + Wireless_controller + Satellite_communication_controllers + Data_acquisition_and_signal_processing_controllers + Intelligent_I/O_controllers + Docking_stations + Processing_accelerators + Device_was_built_before_Class_Code_definitions_were_finalized + Memory_controller + Simple_communication_controllers + Serial_bus_controllers + Encryption/Decryption_controllers + Display_controller + Multimedia_device + Input_devices + Mass_storage_controller + Processors + Device_does_not_fit_in_any_defined_classes + Bridge_device + Network_controller + Base_system_peripherals + + + choice_list_97bc19ec + 256_bit + + + choice_list_9aec9108 + Internal + External + + + choice_list_9e15bd51 + CONSTANT + + + choice_list_9f5580fd + Pre-Production + + + choice_list_a30da595 + Custom + pcie_perstn + + + choice_list_a44ca313 + Custom + pci_express_x1 + pci_express_x16 + pci_express_x2 + pci_express_x4 + pci_express_x8 + + + choice_list_a71f3969 + AXI_Memory_Mapped + AXI_Stream + + + choice_list_aa031417 + 1 + 2 + 3 + 4 + + + choice_list_ab8591cd + PCI_Express_Endpoint_device + PCI_Express_Endpoint_device + + + choice_list_abc20383 + GTY_Quad_227 + GTY_Quad_226 + GTY_Quad_225 + GTY_Quad_224 + + + choice_list_ae9f88f6 + 1 + + + choice_list_b0ffef10 + 0 + 1 + 2 + 3 + 4 + 5 + 7 + + + choice_list_bdd7203f + True + False + + + choice_list_bea500ca + None + MSI-X_External + MSI-X_Internal + MSI-X_AXI4-Stream + + + choice_list_c15e8c67 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_c3d223d9 + Memory + + + choice_list_c63ab5b1 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + choice_list_ca005b72 + No_ASPM + L1_Supported + + + choice_list_ca108395 + 2 + 4 + 8 + 16 + 32 + + + choice_list_d123c74c + Bytes + Kilobytes + Megabytes + + + choice_list_d1e1a340 + Kilobytes + Megabytes + Gigabytes + + + choice_list_d53faa96 + 100_MHz + 125_MHz + 250_MHz + + + choice_list_d85ad257 + 0 + + + choice_list_df7cde9e + RAM + Flash + Other_memory_controller + + + choice_list_dff1a45d + Wireless_controller + Satellite_communication_controllers + Data_acquisition_and_signal_processing_controllers + Processing_accelerators + Intelligent_I/O_controllers + Docking_stations + Device_was_built_before_Class_Code_definitions_were_finalized + Memory_controller + Simple_communication_controllers + Serial_bus_controllers + Encryption/Decryption_controllers + Display_controller + Multimedia_device + Input_devices + Mass_storage_controller + Processors + Device_does_not_fit_in_any_defined_classes + Bridge_device + Network_controller + Base_system_peripherals + + + choice_list_e7c484ae + TRUE + FALSE + + + choice_list_e7f13338 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_e9cf6440 + Disabled + 32bit_Enabled + 64bit_Enabled + + + choice_list_ec64e624 + N/A + + + choice_list_ecc4b9b7 + AU200 + + + choice_list_f1174048 + NONE + INTA + INTB + INTC + INTD + + + choice_list_f94ec5c4 + 4 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_fab783d7 + User_Reset + Phy_Ready + + + choice_list_fc3456a9 + Disabled + Enabled + + + choice_list_fde36331 + Kilobytes + Megabytes + + + choice_list_fe1fb7c4 + 0 + 4 + 8 + 12 + 16 + + + choice_pairs_3c87fcdb + 1 + 0 + + + choice_pairs_53749dec + 1 + 0 + + + choice_pairs_6f00a734 + 0 + 1 + 2 + + + + + xilinx_elaboratesubcores_view_fileset + + ip_0/xdma_pcie4_ip.xci + xci + + + ip_0/xdma_pcie4_ip.xml + xml + + + ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci + xci + + + ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xml + xml + + + ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci + xci + + + ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xml + xml + + + + The Xilinx PCI Express DMA + + + Component_Name + xdma + + + functional_mode + Functional Mode + DMA + + + + true + + + + + + mode_selection + Mode + Basic + + + + true + + + + + + device_port_type + Device Port Type + PCI_Express_Endpoint_device + + + + false + + + + + + pcie_blk_locn + Pcie Blk Locn + X1Y2 + + + + true + + + + + + pl_link_cap_max_link_width + Pl Link Cap Max Link Width + X8 + + + + true + + + + + + pl_link_cap_max_link_speed + Pl Link Cap Max Link Speed + 8.0_GT/s + + + + true + + + + + + ref_clk_freq + 100_MHz + + + + true + + + + + + drp_clk_sel + Internal + + + + true + + + + + + free_run_freq + 100_MHz + + + + true + + + + + + axi_addr_width + AXI Address width + 64 + + + + false + + + + + + axi_data_width + AXI Data width + 256_bit + + + + true + + + + + + axisten_freq + AXIsten if freq + 250 + + + + true + + + + + + en_axi_slave_if + Enable AXI Slave Interface + true + + + + true + + + + + + en_axi_master_if + Enable AXI Master Interface + true + + + + true + + + + + + pipe_sim + false + + + + true + + + + + + en_ext_ch_gt_drp + false + + + + true + + + + + + en_pcie_drp + false + + + + true + + + + + + dedicate_perst + false + + + + false + + + + + + sys_reset_polarity + ACTIVE_LOW + + + + true + + + + + + mcap_enablement + MCAP Enable + None + + + mcap_fpga_bitstream_version + MCAP Bitstream Version Register Value + 00000000 + + + + false + + + + + + ext_startup_primitive + false + + + + false + + + + + + enable_code + 0000 + + + vendor_id + Vendor Id + 10EE + + + + true + + + + + + pf0_device_id + PF0 Device Id + 9038 + + + + true + + + + + + pf0_revision_id + PF0 Revision Id + 00 + + + + true + + + + + + pf0_subsystem_vendor_id + PF0 Subsystem Vendor Id + 10EE + + + + true + + + + + + pf0_subsystem_id + PF0 Subsystem Id + 0007 + + + + true + + + + + + pf0_Use_Class_Code_Lookup_Assistant + false + + + + true + + + + + + pf0_base_class_menu + Pf0 Base Class Menu + Simple_communication_controllers + + + + true + + + + + + pf0_class_code_base + Pf0 Class Code Base + 07 + + + + true + + + + + + pf0_sub_class_interface_menu + Pf0 Sub Class Interface Menu + 16450_compatible_serial_controller + + + + true + + + + + + pf0_class_code_sub + pf0 Class Code Sub + 00 + + + + true + + + + + + pf0_class_code_interface + pf0 Class Code Interface + 01 + + + + true + + + + + + pf0_class_code + pf0 Class Code + 070001 + + + + false + + + + + + axilite_master_en + false + + + + true + + + + + + axilite_master_size + 1 + + + + false + + + + + + axilite_master_scale + Megabytes + + + + false + + + + + + xdma_en + true + + + + false + + + + + + xdma_size + 64 + + + + false + + + + + + xdma_scale + Kilobytes + + + + false + + + + + + axist_bypass_en + false + + + + true + + + + + + axist_bypass_size + 1 + + + + false + + + + + + axist_bypass_scale + Megabytes + + + + false + + + + + + pciebar2axibar_axil_master + 0x00000000 + + + + false + + + + + + pciebar2axibar_xdma + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_axist_bypass + 0x0000000000000000 + + + + false + + + + + + pf0_interrupt_pin + pf0 Interrupt Pin + INTA + + + + true + + + + + + pf0_msi_enabled + pf0 Msi Enabled + true + + + + true + + + + + + pf0_msi_cap_multimsgcap + pf0 Msi Cap Multimsgcap + 1_vector + + + + true + + + + + + comp_timeout + 50ms + + + + true + + + + + + timeout0_sel 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modulation in PPM + 0 + + + INS_LOSS_NYQ + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 15 + + + PHY_LP_TXPRESET + Phy Lp Txpreset + 4 + + + coreclk_freq + CORE CLOCK FREQ + 500 + + + + false + + + + + + plltype + PLL TYPE + QPLL1 + + + xdma_axi_intf_mm + XDMA Interface + AXI_Stream + + + + true + + + + + + xdma_pcie_64bit_en + false + + + silicon_rev + Pre-Production + + + xdma_dsc_bypass + false + + + performance + false + + + pcie_extended_tag + true + + + rx_detect + Receiver Detect + Default + + + pf0_link_status_slot_clock_config + Pf0 Link Status Slot Clock Config + true + + + dsc_bypass_rd + 0000 + + + dsc_bypass_wr + 0000 + + + xdma_sts_ports + false + + + pf0_msix_enabled + Pf0 Msix Enabled + false + + + pf0_msix_cap_table_size + Pf0 Msix Cap Table Size + 000 + + + + false + + + + + + pf0_msix_cap_table_offset + Pf0 Msix Cap Table Offset + 00000000 + + + + false + + + + + + pf0_msix_cap_table_bir + Pf0 Msix Cap Table Bir + BAR_0 + + + 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0x0000000000000000 + + + + true + + + + + + axibar_highaddr_1 + 0x0000000000000000 + + + + false + + + + + + axibar_highaddr_2 + 0x0000000000000000 + + + + false + + + + + + axibar_highaddr_3 + 0x0000000000000000 + + + + false + + + + + + axibar_highaddr_4 + 0x0000000000000000 + + + + false + + + + + + axibar_highaddr_5 + 0x0000000000000000 + + + + false + + + + + + axibar2pciebar_0 + 0x0000000000000000 + + + + true + + + + + + axibar2pciebar_1 + 0x0000000000000000 + + + + false + + + + + + axibar2pciebar_2 + 0x0000000000000000 + + + + false + + + + + + axibar2pciebar_3 + 0x0000000000000000 + + + + false + + + + + + axibar2pciebar_4 + 0x0000000000000000 + + + + false + + + + + + axibar2pciebar_5 + 0x0000000000000000 + + + + false + + + + + + include_baroffset_reg + true + + + + false + + + + + + BASEADDR + 0x00001000 + + + + true + + + + + + HIGHADDR + 0x00001FFF + + + + true + + + + + + s_axi_id_width + 4 + + + + true + + + + + + c_m_axi_num_write + AXI Master outstanding write Transactions Selection + 8 + + + + true + + + + + + c_m_axi_num_read + AXI Master outstanding read Transactions Selection + 8 + + + + false + + + + + + c_m_axi_num_readq + AXI Master outstanding read Transactions Selection + 2 + + + c_s_axi_num_write + AXI Slave outstanding write Transactions Selection + 8 + + + + false + + + + + + c_s_axi_num_read + AXI Slave outstanding read Transactions Selection + 8 + + + + false + + + + + + pf0_msix_impl_locn + Pf0 Msix Implementation Location + Internal + + + + false + + + + + + axi_aclk_loopback + false + + + pf0_bar0_enabled + Pf0 Bar0 Enabled + true + + + + true + + + + + + pf0_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf0_bar0_size + Pf0 Bar0 Size + 128 + + + + true + + + + + + pf0_bar0_scale + Pf0 Bar0 Scale + Kilobytes + + + + true + + + + + + pf0_bar0_64bit + Pf0 Bar0 64bit + false + + + + true + + + + + + pf0_bar0_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar1_enabled + Pf0 Bar0 Enabled + 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Bar0 Scale + Kilobytes + + + + false + + + + + + pf0_bar3_64bit + Pf0 Bar0 64bit + false + + + + false + + + + + + pf0_bar3_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar4_enabled + Pf0 Bar0 Enabled + false + + + + false + + + + + + pf0_bar4_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf0_bar4_size + Pf0 Bar0 Size + 4 + + + + false + + + + + + pf0_bar4_scale + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf0_bar4_64bit + Pf0 Bar0 64bit + false + + + + false + + + + + + pf0_bar4_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar5_enabled + Pf0 Bar0 Enabled + false + + + + false + + + + + + pf0_bar5_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf0_bar5_size + Pf0 Bar0 Size + 4 + + + + false + + + + + + pf0_bar5_scale + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf0_bar5_64bit + Pf0 Bar0 64bit + false + + + + false + + + + + + pf0_bar5_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_6 + 0x0000000000000000 + + + + false + + + + + + bar_indicator + BAR_0 + + + + false + + + + + + bar0_indicator + 1 + + + + true + + + + + + bar1_indicator + 0 + + + + true + + + + + + bar2_indicator + 0 + + + + true + + + + + + bar3_indicator + 0 + + + + true + + + + + + bar4_indicator + 0 + + + + true + + + + + + bar5_indicator + 0 + + + + true + + + + + + barlite2 + 7 + + + en_dbg_descramble + false + + + vcu118_board + false + + + tl_pf_enable_reg + NUM PF Enable + 1 + + + pf1_vendor_id + Vendor Id + 10EE + + + pf1_device_id + PF1 Device Id + 1041 + + + pf1_class_code + Pf1 Class Code + 070001 + + + + false + + + + + + PF1_REVISION_ID + Pf1 Revision Id + 00 + + + PF1_SUBSYSTEM_VENDOR_ID + Pf1 Subsystem Vendor Id + 10EE + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0007 + + + PF1_Use_Class_Code_Lookup_Assistant + false + + + + true + + + + + + pf1_base_class_menu + Pf1 Base Class Menu + Simple_communication_controllers + + + pf1_class_code_base + Pf1 Class Code Base + 07 + + + + true + + + + + + pf1_class_code_sub + Pf1 Class Code Sub + 00 + + + + true + + + + + + pf1_sub_class_interface_menu + Pf1 Sub Class Interface Menu + 16450_compatible_serial_controller + + + + true + + + + + + pf1_class_code_interface + Pf1 Class Code Interface + 01 + + + + true + + + + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + NONE + + + pf1_msi_enabled + Pf1 Msi Enabled + false + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 1_vector + + + pf1_bar0_enabled + Pf1 Bar0 Enabled + true + + + pf1_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar0_size + Pf1 Bar0 Size + 32 + + + pf1_bar0_scale + Pf1 Bar0 Scale + Megabytes + + + pf1_bar0_64bit + Pf1 Bar0 64bit + false + + + pf1_bar0_prefetchable + Pf1 Bar0 Prefetchable + false + + + pf1_bar1_enabled + Pf1 Bar1 Enabled + true + + + pf1_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar1_size + Pf1 Bar1 Size + 128 + + + pf1_bar1_scale + Pf1 Bar1 Scale + Kilobytes + + + pf1_bar1_64bit + Pf1 Bar1 64bit + false + + + pf1_bar1_prefetchable + Pf1 Bar1 Prefetchable + false + + + pf1_bar2_enabled + Pf1 Bar2 Enabled + true + + + pf1_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar2_size + Pf1 Bar2 Size + 128 + + + pf1_bar2_scale + Pf1 Bar2 Scale + Kilobytes + + + pf1_bar2_64bit + Pf1 Bar2 64bit + true + + + pf1_bar2_prefetchable + Pf1 Bar2 Prefetchable + false + + + pf1_bar3_enabled + Pf1 Bar3 Enabled + false + + + + false + + + + + + pf1_bar3_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf1_bar3_size + Pf1 Bar3 Size + 128 + + + + false + + + + + + pf1_bar3_scale + Pf1 Bar3 Scale + Kilobytes + + + + false + + + + + + pf1_bar3_64bit + Pf1 Bar3 64bit + false + + + pf1_bar3_prefetchable + Pf1 Bar3 Prefetchable + false + + + + false + + + + + + pf1_bar4_enabled + Pf1 Bar4 Enabled + true + + + pf1_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar4_size + Pf1 Bar4 Size + 128 + + + pf1_bar4_scale + Pf1 Bar4 Scale + Kilobytes + + + pf1_bar4_64bit + Pf1 Bar4 64bit + true + + + pf1_bar4_prefetchable + Pf1 Bar4 Prefetchable + false + + + pf1_bar5_enabled + Pf1 Bar5 Enabled + false + + + + false + + + + + + pf1_bar5_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf1_bar5_size + Pf1 Bar5 Size + 128 + + + + false + + + + + + pf1_bar5_scale + Pf1 Bar5 Scale + Kilobytes + + + + false + + + + + + pf1_bar5_prefetchable + Pf1 Bar5 Prefetchable + false + + + + false + + + + + + pf2_device_id + PF2 Device Id + 1040 + + + pf2_class_code + pf2 Class Code + 058000 + + + PF2_REVISION_ID + pf2 Revision Id + 00 + + + PF2_SUBSYSTEM_VENDOR_ID + pf2 Subsystem Vendor Id + 10EE + + + PF2_SUBSYSTEM_ID + pf2 Subsystem Id + 0007 + + + PF2_Use_Class_Code_Lookup_Assistant + false + + + pf2_base_class_menu + pf2 Base Class Menu + Memory_controller + + + pf2_class_code_base + pf2 Class Code Base + 05 + + + pf2_class_code_sub + pf2 Class Code Sub + 80 + + + pf2_sub_class_interface_menu + pf2 Sub Class Interface Menu + Other_memory_controller + + + pf2_class_code_interface + pf2 Class Code Interface + 00 + + + PF2_INTERRUPT_PIN + pf2 Interrupt Pin + NONE + + + pf2_msi_enabled + pf2 Msi Enabled + false + + + PF2_MSI_CAP_MULTIMSGCAP + pf2 Msi Cap Multimsgcap + 1_vector + + + pf2_bar0_enabled + pf2 Bar0 Enabled + true + + + pf2_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar0_size + pf2 Bar0 Size + 128 + + + pf2_bar0_scale + pf2 Bar0 Scale + Kilobytes + + + pf2_bar0_64bit + pf2 Bar0 64bit + false + + + pf2_bar0_prefetchable + pf2 Bar0 Prefetchable + false + + + pf2_bar1_enabled + pf2 Bar1 Enabled + true + + + pf2_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar1_size + pf2 Bar1 Size + 128 + + + pf2_bar1_scale + pf2 Bar1 Scale + Kilobytes + + + pf2_bar1_64bit + pf2 Bar1 64bit + false + + + pf2_bar1_prefetchable + pf2 Bar1 Prefetchable + false + + + pf2_bar2_enabled + pf2 Bar2 Enabled + true + + + pf2_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar2_size + pf2 Bar2 Size + 128 + + + pf2_bar2_scale + pf2 Bar2 Scale + Kilobytes + + + pf2_bar2_64bit + pf2 Bar2 64bit + false + + + pf2_bar2_prefetchable + pf2 Bar2 Prefetchable + false + + + pf2_bar3_enabled + pf2 Bar3 Enabled + true + + + pf2_bar3_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar3_size + pf2 Bar3 Size + 128 + + + pf2_bar3_scale + pf2 Bar3 Scale + Kilobytes + + + pf2_bar3_64bit + pf2 Bar3 64bit + false + + + pf2_bar3_prefetchable + pf2 Bar3 Prefetchable + false + + + pf2_bar4_enabled + pf2 Bar4 Enabled + true + + + pf2_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar4_size + pf2 Bar4 Size + 128 + + + pf2_bar4_scale + pf2 Bar4 Scale + Kilobytes + + + pf2_bar4_64bit + pf2 Bar4 64bit + false + + + pf2_bar4_prefetchable + pf2 Bar4 Prefetchable + false + + + pf2_bar5_enabled + pf2 Bar5 Enabled + true + + + pf2_bar5_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar5_size + pf2 Bar5 Size + 128 + + + pf2_bar5_scale + pf2 Bar5 Scale + Kilobytes + + + pf2_bar5_prefetchable + pf2 Bar5 Prefetchable + false + + + pf3_device_id + PF3 Device Id + 1039 + + + pf3_class_code + Pf3 Class Code + 058000 + + + PF3_REVISION_ID + Pf3 Revision Id + 00 + + + PF3_SUBSYSTEM_VENDOR_ID + Pf3 Subsystem Vendor Id + 10EE + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0007 + + + PF3_Use_Class_Code_Lookup_Assistant + false + + + pf3_base_class_menu + Pf3 Base Class Menu + Memory_controller + + + pf3_class_code_base + Pf3 Class Code Base + 05 + + + pf3_class_code_sub + Pf3 Class Code Sub + 80 + + + pf3_sub_class_interface_menu + Pf3 Sub Class Interface Menu + Other_memory_controller + + + pf3_class_code_interface + Pf3 Class Code Interface + 00 + + + PF3_INTERRUPT_PIN + Pf3 Interrupt Pin + NONE + + + pf3_msi_enabled + Pf3 Msi Enabled + false + + + PF3_MSI_CAP_MULTIMSGCAP + Pf3 Msi Cap Multimsgcap + 1_vector + + + pf3_bar0_enabled + Pf3 Bar0 Enabled + true + + + pf3_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar0_size + Pf3 Bar0 Size + 128 + + + pf3_bar0_scale + Pf3 Bar0 Scale + Kilobytes + + + pf3_bar0_64bit + Pf3 Bar0 64bit + false + + + pf3_bar0_prefetchable + Pf3 Bar0 Prefetchable + false + + + pf3_bar1_enabled + Pf3 Bar1 Enabled + true + + + pf3_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar1_size + Pf3 Bar1 Size + 128 + + + pf3_bar1_scale + Pf3 Bar1 Scale + Kilobytes + + + pf3_bar1_64bit + Pf3 Bar1 64bit + false + + + pf3_bar1_prefetchable + Pf3 Bar1 Prefetchable + false + + + pf3_bar2_enabled + Pf3 Bar2 Enabled + true + + + pf3_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar2_size + Pf3 Bar2 Size + 128 + + + pf3_bar2_scale + Pf3 Bar2 Scale + Kilobytes + + + pf3_bar2_64bit + Pf3 Bar2 64bit + false + + + pf3_bar2_prefetchable + Pf3 Bar2 Prefetchable + false + + + pf3_bar3_enabled + Pf3 Bar3 Enabled + true + + + pf3_bar3_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar3_size + Pf3 Bar3 Size + 128 + + + pf3_bar3_scale + Pf3 Bar3 Scale + Kilobytes + + + pf3_bar3_64bit + Pf3 Bar3 64bit + false + + + pf3_bar3_prefetchable + Pf3 Bar3 Prefetchable + false + + + pf3_bar4_enabled + Pf3 Bar4 Enabled + true + + + pf3_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar4_size + Pf3 Bar4 Size + 128 + + + pf3_bar4_scale + Pf3 Bar4 Scale + Kilobytes + + + pf3_bar4_64bit + Pf3 Bar4 64bit + false + + + pf3_bar4_prefetchable + Pf3 Bar4 Prefetchable + false + + + pf3_bar5_enabled + Pf3 Bar5 Enabled + true + + + pf3_bar5_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar5_size + Pf3 Bar5 Size + 128 + + + pf3_bar5_scale + Pf3 Bar5 Scale + Kilobytes + + + pf3_bar5_prefetchable + Pf3 Bar5 Prefetchable + false + + + split_dma + false + + + split_dma_single_pf + false + + + mult_pf_des + false + + + pf_swap + false + + + prog_usr_irq_vec_map + false + + + rcfg_nph_fix_en + false + + + post_synth_sim_en + false + + + user_pf_two_axilite_bar_en + false + + + two_bypass_bar + false + + + xlnx_ref_board + Xlnx Ref Board + AU200 + + + + true + + + + + + en_l23_entry + false + + + pf1_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf1_pciebar2axibar_2 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf1_pciebar2axibar_4 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + pf1_pciebar2axibar_6 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf2_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf3_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + gtwiz_in_core_us + 1 + + + gtwiz_in_core_usp + 1 + + + dma_reset_source_sel + User_Reset + + + en_dma_and_bridge + false + + + en_coreclk_es1 + false + + + pipe_line_stage + number of Pipe Line Stages + 2 + + + + false + + + + + + axis_pipe_line_stage + number of Pipe Line Stages on PCIe axis interface + 0 + + + + false + + + + + + vu9p_tul_ex + false + + + vcu1525_ddr_ex + false + + + en_bridge + false + + + enable_ccix + FALSE + + + enable_dvsec + FALSE + + + ext_sys_clk_bufg + false + + + usr_irq_exdes + false + + + axi_vip_in_exdes + false + + + xdma_non_incremental_exdes + false + + + xdma_st_infinite_desc_exdes + false + + + gtcom_in_core_usp + 2 + + + en_mqdma + false + + + SRIOV_CAP_ENABLE + false + + + + false + + + + + + ext_xvc_vsec_enable + Enable to add the PCIe XVC-VSEC to the Examlpe Design + false + + + + false + + + + + + acs_ext_cap_enable + ACS Ext Capability + false + + + pf0_bar0_enabled_mqdma + Pf0 Bar1 Enabled + true + + + pf0_bar0_type_mqdma + Pf0 Bar0 Type + DMA + + + pf0_bar0_64bit_mqdma + Pf0 Bar0 64bit + false + + + pf0_bar0_prefetchable_mqdma + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar0_scale_mqdma + Pf0 Bar0 Scale + Kilobytes + + + pf0_bar0_size_mqdma + Pf0 Bar0 Size + 128 + + + pf0_bar1_enabled_mqdma + Pf0 Bar1 Enabled + false + + + pf0_bar1_type_mqdma + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf0_bar1_64bit_mqdma + Pf0 Bar1 64bit + false + + + + false + + + + + + pf0_bar1_prefetchable_mqdma + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf0_bar1_scale_mqdma + Pf0 Bar1 Scale + Kilobytes + + + + false + + + + + + pf0_bar1_size_mqdma + Pf0 Bar1 Size + 128 + + + + false + + + + + + pf0_bar2_enabled_mqdma + Pf0 Bar2 Enabled + false + + + pf0_bar2_type_mqdma + Pf0 Bar2 Type + N/A + + + + false + + + + + + pf0_bar2_64bit_mqdma + Pf0 Bar2 64bit + false + + + + false + + + + + + pf0_bar2_prefetchable_mqdma + Pf0 Bar2 Prefetchable + false + + + + false + + + + + + pf0_bar2_scale_mqdma + Pf0 Bar2 Scale + Kilobytes + + + + false + + + + + + pf0_bar2_size_mqdma + Pf0 Bar2 Size + 128 + + + + false + + + + + + pf0_bar3_enabled_mqdma + Pf0 Bar3 Enabled + false + + + pf0_bar3_type_mqdma + Pf0 Bar3 Type + N/A + + + + false + + + + + + pf0_bar3_64bit_mqdma + Pf0 Bar3 64bit + false + + + + false + + + + + + pf0_bar3_prefetchable_mqdma + Pf0 Bar3 Prefetchable + false + + + + false + + + + + + pf0_bar3_scale_mqdma + Pf0 Bar3 Scale + Kilobytes + + + + false + + + + + + pf0_bar3_size_mqdma + Pf0 Bar3 Size + 128 + + + + false + + + + + + pf0_bar4_enabled_mqdma + Pf0 Bar4 Enabled + false + + + pf0_bar4_type_mqdma + Pf0 Bar4 Type + N/A + + + + false + + + + + + pf0_bar4_64bit_mqdma + Pf0 Bar4 64bit + false + + + + false + + + + + + pf0_bar4_prefetchable_mqdma + Pf0 Bar4 Prefetchable + false + + + + false + + + + + + pf0_bar4_scale_mqdma + Pf0 Bar4 Scale + Kilobytes + + + + false + + + + + + pf0_bar4_size_mqdma + Pf0 Bar4 Size + 128 + + + + false + + + + + + pf0_bar5_enabled_mqdma + Pf0 Bar5 Enabled + false + + + pf0_bar5_type_mqdma + Pf0 Bar5 Type + N/A + + + + false + + + + + + pf0_bar5_prefetchable_mqdma + Pf0 Bar5 Prefetchable + false + + + pf0_bar5_scale_mqdma + Pf0 Bar5 Scale + Kilobytes + + + + false + + + + + + pf0_bar5_size_mqdma + Pf0 Bar5 Size + 128 + + + + false + + + + + + pf1_bar0_enabled_mqdma + Pf0 Bar0 Enabled + true + + + + false + + + + + + pf1_bar0_type_mqdma + Pf0 Bar0 Type + DMA + + + + false + + + + + + pf1_bar0_64bit_mqdma + Pf0 Bar0 64bit + false + + + + false + + + + + + pf1_bar0_prefetchable_mqdma + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf1_bar0_scale_mqdma + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf1_bar0_size_mqdma + Pf0 Bar0 Size + 128 + + + + false + + + + + + pf1_bar1_enabled_mqdma + Pf0 Bar1 Enabled + false + + + + false + + + + + + pf1_bar1_type_mqdma + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf1_bar1_64bit_mqdma + Pf0 Bar1 64bit + false + + + + false + + + + + + pf1_bar1_prefetchable_mqdma + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf1_bar1_scale_mqdma + Pf0 Bar1 Scale + Kilobytes + + + + false + + + + + + pf1_bar1_size_mqdma + Pf0 Bar1 Size + 128 + + + + false + + + + + + pf1_bar2_enabled_mqdma + Pf0 Bar2 Enabled + false + + + + false + + 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pf3_sriov_bar5_prefetchable + Pf0 Sriov Bar0 Prefetchable + false + + + pf3_sriov_bar5_size + Pf0 Sriov Bar0 Size + 2 + + + + false + + + + + + pf3_sriov_bar5_scale + Pf0 Sriov Bar0 Scale + Kilobytes + + + + false + + + + + + pcie_id_if + FALSE + + + pf0_vendor_id_mqdma + Vendor Id + 10EE + + + pf1_vendor_id_mqdma + Vendor Id + 10EE + + + pf2_vendor_id_mqdma + Vendor Id + 10EE + + + pf3_vendor_id_mqdma + Vendor Id + 10EE + + + PF0_DEVICE_ID_mqdma + Pf2 Device Id + 9038 + + + PF1_DEVICE_ID_mqdma + Pf2 Device Id + 0007 + + + PF2_DEVICE_ID_mqdma + Pf2 Device Id + 9038 + + + PF3_DEVICE_ID_mqdma + Pf3 Device Id + 9038 + + + PF0_REVISION_ID_mqdma + Pf2 Revision Id + 00 + + + PF1_REVISION_ID_mqdma + Pf2 Revision Id + 00 + + + PF2_REVISION_ID_mqdma + Pf2 Revision Id + 00 + + + PF3_REVISION_ID_mqdma + Pf3 Revision Id + 00 + + + PF0_SUBSYSTEM_VENDOR_ID_mqdma + Pf2 Subsystem Vendor Id + 10EE + + + PF1_SUBSYSTEM_VENDOR_ID_mqdma + Pf2 Subsystem Vendor Id + 10EE + + + PF2_SUBSYSTEM_VENDOR_ID_mqdma + Pf2 Subsystem Vendor Id + 10EE + + + PF3_SUBSYSTEM_VENDOR_ID_mqdma + Pf3 Subsystem Vendor Id + 10EE + + + PF0_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF1_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF2_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF3_SUBSYSTEM_ID_mqdma + Pf3 Subsystem Id + 0007 + + + pf0_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf1_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf2_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf3_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf0_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf0_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf0_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf0_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf0_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf0_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + pf1_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf1_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf1_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf1_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf1_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf1_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + pf2_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf2_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf2_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf2_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf2_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf2_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + pf3_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf3_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf3_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf3_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf3_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf3_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 1 + + + pf0_sriov_cap_ver + Pf0 Sriov Cap Ver + 1 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0000 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 0 + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 00000553 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 1 + + + + false + + + + + + PF1_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + 0 + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0001 + + + + false + + + + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 00000553 + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0000 + + + + false + + + + + + PF2_SRIOV_CAP_VER + Pf2 Sriov Cap Ver + 1 + + + + false + + + + + + PF2_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF2_SRIOV_FIRST_VF_OFFSET + Pf2 Sriov First Vf Offset + 0 + + + PF2_SRIOV_FUNC_DEP_LINK + Pf2 Sriov Func Dep Link + 0002 + + + + false + + + + + + PF2_SRIOV_SUPPORTED_PAGE_SIZE + Pf2 Sriov Supported Page Size + 00000553 + + + PF2_SRIOV_VF_DEVICE_ID + Pf2 Sriov Vf Device Id + 0000 + + + + false + + + + + + PF3_SRIOV_CAP_INITIAL_VF + Pf3 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF3_SRIOV_CAP_VER + Pf3 Sriov Cap Ver + 1 + + + + false + + + + + + PF3_SRIOV_FIRST_VF_OFFSET + Pf3 Sriov First Vf Offset + 0 + + + PF3_SRIOV_FUNC_DEP_LINK + Pf3 Sriov Func Dep Link + 0003 + + + + false + + + + + + PF3_SRIOV_SUPPORTED_PAGE_SIZE + Pf3 Sriov Supported Page Size + 00000553 + + + PF3_SRIOV_VF_DEVICE_ID + Pf3 Sriov Vf Device Id + 0000 + + + + false + + + + + + pf0_ari_enabled + Pf0 Ari Enabled + false + + + pf0_msix_enabled_mqdma + Pf0 Msix Enabled + false + + + pf1_msix_enabled_mqdma + Pf1 Msix Enabled + false + + + pf2_msix_enabled_mqdma + Pf2 Msix Enabled + false + + + pf3_msix_enabled_mqdma + Pf3 Msix Enabled + false + + + PF0_MSIX_CAP_TABLE_SIZE_mqdma + Pf0 Msix Cap Table Size + 000 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_SIZE_mqdma + Pf1 Msix Cap Table Size + 000 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_SIZE_mqdma + Pf2 Msix Cap Table Size + 000 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_SIZE_mqdma + Pf3 Msix Cap Table Size + 000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_OFFSET_mqdma + Pf0 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_OFFSET_mqdma + Pf1 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_OFFSET_mqdma + Pf2 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_OFFSET_mqdma + Pf3 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF0_MSIX_CAP_PBA_OFFSET_mqdma + Pf0 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF1_MSIX_CAP_PBA_OFFSET_mqdma + Pf1 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF2_MSIX_CAP_PBA_OFFSET_mqdma + Pf2 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF3_MSIX_CAP_PBA_OFFSET_mqdma + Pf3 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_PBA_BIR_mqdma + Pf0 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_PBA_BIR_mqdma + Pf1 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_PBA_BIR_mqdma + Pf2 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_PBA_BIR_mqdma + Pf3 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + MSI_X_OPTIONS + None + + + + false + + + + + + dsc_bypass_rd_out + 0000 + + + dsc_bypass_wr_out + 0000 + + + num_queues + 1 + + + enable_auto_rxeq + False + + + enable_pcie_debug + False + + + axisten_if_enable_msg_route + 27FFF + + + en_axi_mm_mqdma + true + + + + true + + + + + + en_axi_st_mqdma + false + + + + true + + + + + + enable_more_clk + false + + + tl_credits_cd + 15 + + + tl_credits_ch + 15 + + + set_finite_credit + false + + + disable_bram_pipeline + false + + + disable_eq_synchronizer + false + + + enable_resource_reduction + false + + + c_ats_enable + ATS Extended Capability Enable + false + + + c_pri_enable + Page Request Extended Capability Enable + false + + + usplus_es1_seqnum_bypass + false + + + bridge_registers_offset_enable + false + + + enable_gen4 + true + + + local_test + false + + + gen4_eieos_0s7 + true + + + c_s_axi_supports_narrow_burst + false + + + enable_ats_switch + FALSE + + + c_ats_switch_unique_bdf + 1 + + + ctrl_skip_mask + true + + + pf0_ats_enabled + Pf0 Ats Enabled + false + + + pf0_pri_enabled + Pf0 Pri Enabled + false + + + aspm_support + ASPM Support + No_ASPM + + + pf0_aer_cap_ecrc_gen_and_check_capable + false + + + gen_pipe_debug + false + + + soft_reset_en + DMA Bridge Reset + false + + + msi_rx_pin_en + FALSE + + + msix_rx_pin_en + TRUE + + + msix_rx_decode_en + FALSE + + + + false + + + + + + intx_rx_pin_en + true + + + msix_type + MSI-X Type + HARD + + + runbit_fix + false + + + axsize_byte_access_en + false + + + enable_lane_reversal + false + + + enable_mark_debug + false + + + master_cal_only + false + + + enable_multi_pcie + false + + + rbar_enable + false + + + pf0_rbar_num + Number of Resizable BARs for PF0 + 1 + + + pf1_rbar_num + Number of Resizable BARs for PF1 + 1 + + + pf2_rbar_num + Number of Resizable BARs for PF2 + 1 + + + pf3_rbar_num + Number of Resizable BARs for PF3 + 1 + + + pf0_bar0_index + PF0 BAR0 index + 0 + + + pf0_bar1_index + PF0 BAR1 index + 7 + + + pf0_bar2_index + PF0 BAR2 index + 7 + + + pf0_bar3_index + PF0 BAR3 index + 7 + + + pf0_bar4_index + PF0 BAR4 index + 7 + + + pf0_bar5_index + PF0 BAR5 index + 7 + + + pf1_bar0_index + PF0 BAR0 index + 0 + + + pf1_bar1_index + PF1 BAR1 index + 7 + + + pf1_bar2_index + PF1 BAR2 index + 7 + + + pf1_bar3_index + PF1 BAR3 index + 7 + + + pf1_bar4_index + PF1 BAR4 index + 7 + + + pf1_bar5_index + PF1 BAR5 index + 7 + + + pf2_bar0_index + PF2 BAR0 index + 0 + + + pf2_bar1_index + PF2 BAR1 index + 7 + + + pf2_bar2_index + PF2 BAR2 index + 7 + + + pf2_bar3_index + PF2 BAR3 index + 7 + + + pf2_bar4_index + PF2 BAR4 index + 7 + + + pf2_bar5_index + PF2 BAR5 index + 7 + + + pf3_bar0_index + PF3 BAR0 index + 0 + + + pf3_bar1_index + PF3 BAR1 index + 7 + + + pf3_bar2_index + PF3 BAR2 index + 7 + + + pf3_bar3_index + PF3 BAR3 index + 7 + + + pf3_bar4_index + PF3 BAR4 index + 7 + + + pf3_bar5_index + PF3 BAR5 index + 7 + + + pf0_rbar_cap_bar0 + PF0 RBAR CAP BAR0 + 0x00000000fff0 + + + pf0_rbar_cap_bar1 + PF0 RBAR CAP BAR1 + 0x000000000000 + + + pf0_rbar_cap_bar2 + PF0 RBAR CAP BAR2 + 0x000000000000 + + + pf0_rbar_cap_bar3 + PF0 RBAR CAP BAR3 + 0x000000000000 + + + pf0_rbar_cap_bar4 + PF0 RBAR CAP BAR4 + 0x000000000000 + + + pf0_rbar_cap_bar5 + PF0 RBAR CAP BAR5 + 0x000000000000 + + + pf1_rbar_cap_bar0 + PF1 RBAR CAP BAR0 + 0x00000000fff0 + + + pf1_rbar_cap_bar1 + PF1 RBAR CAP BAR1 + 0x000000000000 + + + pf1_rbar_cap_bar2 + PF1 RBAR CAP BAR2 + 0x000000000000 + + + pf1_rbar_cap_bar3 + PF1 RBAR CAP BAR3 + 0x000000000000 + + + pf1_rbar_cap_bar4 + PF1 RBAR CAP BAR4 + 0x000000000000 + + + pf1_rbar_cap_bar5 + PF1 RBAR CAP BAR5 + 0x000000000000 + + + pf2_rbar_cap_bar0 + PF2 RBAR CAP BAR0 + 0x00000000fff0 + + + pf2_rbar_cap_bar1 + PF2 RBAR CAP BAR1 + 0x000000000000 + + + pf2_rbar_cap_bar2 + PF2 RBAR CAP BAR2 + 0x000000000000 + + + pf2_rbar_cap_bar3 + PF2 RBAR CAP BAR3 + 0x000000000000 + + + pf2_rbar_cap_bar4 + PF2 RBAR CAP BAR4 + 0x000000000000 + + + pf2_rbar_cap_bar5 + PF2 RBAR CAP BAR5 + 0x000000000000 + + + pf3_rbar_cap_bar0 + PF3 RBAR CAP BAR0 + 0x00000000fff0 + + + pf3_rbar_cap_bar1 + PF3 RBAR CAP BAR1 + 0x000000000000 + + + pf3_rbar_cap_bar2 + PF3 RBAR CAP BAR2 + 0x000000000000 + + + pf3_rbar_cap_bar3 + PF3 RBAR CAP BAR3 + 0x000000000000 + + + pf3_rbar_cap_bar4 + PF3 RBAR CAP BAR4 + 0x000000000000 + + + pf3_rbar_cap_bar5 + PF3 RBAR CAP BAR5 + 0x000000000000 + + + mpsoc_pl_rp_enable + false + + + c_smmu_en + 0 + + + enable_slave_read_64os + false + + + m_axib_num_write_scale + 1 + + + disable_gt_loc + Disable GT loc constraint delivery + false + + + use_standard_interfaces + use standard interfaces for IPI design + false + + + dma_2rp + Truncate ports for 2RP DMA design + false + + + disable_user_clock_root + true + + + flr_enable + false + + + enable_epyc_chipset_fix + false + + + usrint_expn + false + + + shell_bridge + false + + + msix_pcie_internal + false + + + broadcom_sbr_wa + false + + + tl_tx_mux_strict_priority + false + + + + + DMA/Bridge Subsystem for PCI Express + + XPM_CDC + XPM_MEMORY + XPM_FIFO + + 8 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci b/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci new file mode 100644 index 0000000..c067a3c --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci @@ -0,0 +1,330 @@ + + + xilinx.com + xci + unknown + 1.0 + + + zq_calib_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 6 + 6 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 5.931282 mW + virtexuplus + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zq_calib_mem.mem + zq_calib_mem.mif + 0 + 1 + 0 + 0 + 1 + 64 + 64 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 64 + 64 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../coe/pr_zq.coe + ALL + zq_calib_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + true + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 64 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + virtexuplus + xilinx.com:au200:part0:1.3 + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml b/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml new file mode 100644 index 0000000..5be6cc5 --- /dev/null +++ b/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml @@ -0,0 +1,4185 @@ + + + xilinx.com + customized_ip + zq_calib_mem + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXI_SLAVE_S_AXI + AXI_SLAVE + AXI_SLAVE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARBURST + + + s_axi_arburst + + + + + ARID + + + s_axi_arid + + + + + ARLEN + + + s_axi_arlen + + + + + ARREADY + + + s_axi_arready + + + + + ARSIZE + + + s_axi_arsize + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWBURST + + + s_axi_awburst + + + + + AWID + + + s_axi_awid + + + + + AWLEN + + + s_axi_awlen + + + + + AWREADY + + + s_axi_awready + + + + + AWSIZE + + + s_axi_awsize + + + + + AWVALID + + + s_axi_awvalid + + + + + BID + + + s_axi_bid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RID + + + s_axi_rid + + + + + RLAST + + + s_axi_rlast + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WLAST + + + s_axi_wlast + + + + + WREADY + + + s_axi_wready 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C_HAS_SOFTECC_INPUT_REGS_A + 0 + + + C_HAS_SOFTECC_OUTPUT_REGS_B + 0 + + + C_USE_SOFTECC + 0 + + + C_USE_ECC + 0 + + + C_EN_ECC_PIPE + 0 + + + C_READ_LATENCY_A + 1 + + + C_READ_LATENCY_B + 1 + + + C_HAS_INJECTERR + 0 + + + C_SIM_COLLISION_CHECK + ALL + + + C_COMMON_CLK + 0 + + + C_DISABLE_WARN_BHV_COLL + 0 + + + C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 0 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 1 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 5.931282 mW + + + + + + choice_list_0e6ad450 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + zq_calib_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + false + + + + + + RD_ADDR_CHNG_B + false + + + + false + + + + + + Use_Error_Injection_Pins + false + + + + false + + + + + + Error_Injection_Type + Single_Bit_Error_Injection + + + + false + + + + + + Use_Byte_Write_Enable + false + + + + true + + + + + + Byte_Size + 9 + + + + false + + + + + + Algorithm + Minimum_Area + + + + true + + + + + + Primitive + 8kx2 + + + + false + + + + + + Assume_Synchronous_Clk + false + + + + false + + + + + + Write_Width_A + 64 + + + + true + + + + + + Write_Depth_A + 64 + + + + true + + + + + + Read_Width_A + 64 + + + + true + + + + + + Operating_Mode_A + WRITE_FIRST + + + + true + + + + + + Enable_A + Use_ENA_Pin + + + + true + + + + + + Write_Width_B + 64 + + + + false + + + + + + Read_Width_B + 64 + + + + false + + + + + + Operating_Mode_B + WRITE_FIRST + + + + false + + + + + + Enable_B + Always_Enabled + + + + false + + + + + + Register_PortA_Output_of_Memory_Primitives + false + + + + true + + + + + + Register_PortA_Output_of_Memory_Core + false + + + + true + + + + + + Use_REGCEA_Pin + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Primitives + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Core + false + + + + false + + + + + + Use_REGCEB_Pin + false + + + + false + + + + + + register_porta_input_of_softecc + false + + + + false + + + + + + register_portb_output_of_softecc + false + + + + false + + + + + + Pipeline_Stages + 0 + + + + false + + + + + + Load_Init_File + true + + + + true + + + + + + Coe_File + ../../../../coe/pr_zq.coe + + + + true + + + + + + Fill_Remaining_Memory_Locations + true + + + + true + + + + + + Remaining_Memory_Locations + 0 + + + + true + + + + + + Use_RSTA_Pin + false + + + + true + + + + + + Reset_Memory_Latch_A + false + + + + false + + + + + + Reset_Priority_A + CE + + + + false + + + + + + Output_Reset_Value_A + 0 + + + + false + + + + + + Use_RSTB_Pin + false + + + + false + + + + + + Reset_Memory_Latch_B + false + + + + false + + + + + + Reset_Priority_B + CE + + + + false + + + + + + Output_Reset_Value_B + 0 + + + + false + + + + + + Reset_Type + SYNC + + + + false + + + + + + Additional_Inputs_for_Power_Estimation + false + + + + true + + + + + + Port_A_Clock + 100 + + + + true + + + + + + Port_A_Write_Rate + 50 + + + + true + + + + + + Port_B_Clock + 0 + + + + true + + + + + + Port_B_Write_Rate + 0 + + + + true + + + + + + Port_A_Enable_Rate + 100 + + + + true + + + + + + Port_B_Enable_Rate + 0 + + + + true + + + + + + Collision_Warnings + ALL + + + + true + + + + + + Disable_Collision_Warnings + false + + + + true + + + + + + Disable_Out_of_Range_Warnings + false + + + + true + + + + + + use_bram_block + Stand_Alone + + + + true + + + + + + MEM_FILE + no_mem_loaded + + + + true + + + + + + CTRL_ECC_ALGO + NONE + + + + true + + + + + + EN_SAFETY_CKT + false + + + + false + + + + + + READ_LATENCY_A + 1 + + + + false + + + + + + READ_LATENCY_B + 1 + + + + false + + + + + + + + Block Memory Generator + + XPM_MEMORY + + 4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + + -- cgit v1.2.3