From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- projects/U200/verilog/project.vh | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 projects/U200/verilog/project.vh (limited to 'projects/U200/verilog/project.vh') diff --git a/projects/U200/verilog/project.vh b/projects/U200/verilog/project.vh new file mode 100644 index 0000000..8286cbd --- /dev/null +++ b/projects/U200/verilog/project.vh @@ -0,0 +1,31 @@ +`define UDIMM_x8 + +`ifdef UDIMM_x8 + + `define DQ_WIDTH 64 + `define ODT_WIDTH 2 + `define CS_WIDTH 2 + `define CKE_WIDTH 2 + `define CK_WIDTH 1 + `define ROW_ADDR_WIDTH 17 + +`elsif RDIMM_x8 + + `define DQ_WIDTH 72 + `define ODT_WIDTH 2 + `define CS_WIDTH 2 + `define CKE_WIDTH 2 + `define CK_WIDTH 1 + `define ROW_ADDR_WIDTH 17 + +`elsif RDIMM_x4 + + `define DQ_WIDTH 72 + `define ODT_WIDTH 2 + `define CS_WIDTH 2 + `define CKE_WIDTH 2 + `define CK_WIDTH 1 + `define ROW_ADDR_WIDTH 18 + +`endif + -- cgit v1.2.3