From 7721980589f4c7fa811689e815a77d63f2556497 Mon Sep 17 00:00:00 2001 From: Ataberk Date: Thu, 2 May 2024 17:22:05 +0200 Subject: Add sources for U50 HBM2 --- .../ip/c_counter_binary_0/c_counter_binary_0.veo | 66 +++++++++++++++++++ .../ip/c_counter_binary_0/c_counter_binary_0.vho | 77 ++++++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100755 projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.veo create mode 100755 projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.vho (limited to 'projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0') diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.veo new file mode 100755 index 0000000..3624678 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.veo @@ -0,0 +1,66 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:c_counter_binary:12.0 +// IP Revision: 14 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +c_counter_binary_0 your_instance_name ( + .CLK(CLK), // input wire CLK + .Q(Q) // output wire [15 : 0] Q +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file c_counter_binary_0.v when simulating +// the core, c_counter_binary_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.vho new file mode 100755 index 0000000..1bb607b --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.vho @@ -0,0 +1,77 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:c_counter_binary:12.0 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT c_counter_binary_0 + PORT ( + CLK : IN STD_LOGIC; + Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : c_counter_binary_0 + PORT MAP ( + CLK => CLK, + Q => Q + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file c_counter_binary_0.vhd when simulating +-- the core, c_counter_binary_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + -- cgit v1.2.3