From 7721980589f4c7fa811689e815a77d63f2556497 Mon Sep 17 00:00:00 2001 From: Ataberk Date: Thu, 2 May 2024 17:22:05 +0200 Subject: Add sources for U50 HBM2 --- .../ip/clk_wiz_0/clk_wiz_0.veo | 80 ++++++++++++++++++++++ .../ip/clk_wiz_0/clk_wiz_0_stub.v | 21 ++++++ .../ip/clk_wiz_0/clk_wiz_0_stub.vhdl | 30 ++++++++ 3 files changed, 131 insertions(+) create mode 100755 projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo create mode 100644 projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v create mode 100644 projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl (limited to 'projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0') diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo new file mode 100755 index 0000000..e02f568 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo @@ -0,0 +1,80 @@ + +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_150MHz__150.00000______0.000______50.0______127.220____105.461 +// clk_300MHz__300.00000______0.000______50.0______111.879____105.461 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clk_wiz_0 instance_name + ( + // Clock out ports + .clk_150MHz(clk_150MHz), // output clk_150MHz + .clk_300MHz(clk_300MHz), // output clk_300MHz + // Clock in ports + .clk_in1(clk_in1)); // input clk_in1 + +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100644 index 0000000..4a2e0b1 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,21 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:07 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module clk_wiz_0(clk_150MHz, clk_300MHz, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="clk_150MHz,clk_300MHz,clk_in1" */; + output clk_150MHz; + output clk_300MHz; + input clk_in1; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..0cc7f9e --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,30 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:07 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + clk_150MHz : out STD_LOGIC; + clk_300MHz : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + +end clk_wiz_0; + +architecture stub of clk_wiz_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_150MHz,clk_300MHz,clk_in1"; +begin +end; -- cgit v1.2.3