From 7721980589f4c7fa811689e815a77d63f2556497 Mon Sep 17 00:00:00 2001 From: Ataberk Date: Thu, 2 May 2024 17:22:05 +0200 Subject: Add sources for U50 HBM2 --- projects/U50-HBM/U50-HBM.ip_user_files/README.txt | 1 + .../axis_clock_converter/axis_clock_converter.veo | 78 + .../axis_clock_converter/axis_clock_converter.vho | 101 ++ .../axis_clock_converter_stub.v | 35 + .../axis_clock_converter_stub.vhdl | 43 + .../ip/c_counter_binary_0/c_counter_binary_0.veo | 66 + .../ip/c_counter_binary_0/c_counter_binary_0.vho | 77 + .../U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.veo | 76 + .../U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.vho | 97 ++ .../ip/cdc_fifo/cdc_fifo_stub.v | 32 + .../ip/cdc_fifo/cdc_fifo_stub.vhdl | 41 + .../ip/clk_wiz_0/clk_wiz_0.veo | 80 + .../ip/clk_wiz_0/clk_wiz_0_stub.v | 21 + .../ip/clk_wiz_0/clk_wiz_0_stub.vhdl | 30 + .../U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.veo | 75 + .../U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.vho | 95 ++ .../ip/cmd_fifo/cmd_fifo_stub.v | 31 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projects/U50-HBM/U50-HBM.ip_user_files/mem_init_files/ref.coe create mode 100755 projects/U50-HBM/U50-HBM.ip_user_files/mem_init_files/zq.coe (limited to 'projects/U50-HBM/U50-HBM.ip_user_files') diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/README.txt b/projects/U50-HBM/U50-HBM.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo new file mode 100755 index 0000000..84a68ee --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo @@ -0,0 +1,78 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axis_clock_converter:1.1 +// IP Revision: 23 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axis_clock_converter your_instance_name ( + .s_axis_aresetn(s_axis_aresetn), // input wire s_axis_aresetn + .m_axis_aresetn(m_axis_aresetn), // input wire m_axis_aresetn + .s_axis_aclk(s_axis_aclk), // input wire s_axis_aclk + .s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid + .s_axis_tready(s_axis_tready), // output wire s_axis_tready + .s_axis_tdata(s_axis_tdata), // input wire [255 : 0] s_axis_tdata + .s_axis_tkeep(s_axis_tkeep), // input wire [31 : 0] s_axis_tkeep + .s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast + .m_axis_aclk(m_axis_aclk), // input wire m_axis_aclk + .m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid + .m_axis_tready(m_axis_tready), // input wire m_axis_tready + .m_axis_tdata(m_axis_tdata), // output wire [255 : 0] m_axis_tdata + .m_axis_tkeep(m_axis_tkeep), // output wire [31 : 0] m_axis_tkeep + .m_axis_tlast(m_axis_tlast) // output wire m_axis_tlast +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axis_clock_converter.v when simulating +// the core, axis_clock_converter. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho new file mode 100755 index 0000000..62fdd7b --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho @@ -0,0 +1,101 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axis_clock_converter:1.1 +-- IP Revision: 23 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axis_clock_converter + PORT ( + s_axis_aresetn : IN STD_LOGIC; + m_axis_aresetn : IN STD_LOGIC; + s_axis_aclk : IN STD_LOGIC; + s_axis_tvalid : IN STD_LOGIC; + s_axis_tready : OUT STD_LOGIC; + s_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + s_axis_tkeep : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_tlast : IN STD_LOGIC; + m_axis_aclk : IN STD_LOGIC; + m_axis_tvalid : OUT STD_LOGIC; + m_axis_tready : IN STD_LOGIC; + m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + m_axis_tkeep : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_tlast : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axis_clock_converter + PORT MAP ( + s_axis_aresetn => s_axis_aresetn, + m_axis_aresetn => m_axis_aresetn, + s_axis_aclk => s_axis_aclk, + s_axis_tvalid => s_axis_tvalid, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata, + s_axis_tkeep => s_axis_tkeep, + s_axis_tlast => s_axis_tlast, + m_axis_aclk => m_axis_aclk, + m_axis_tvalid => m_axis_tvalid, + m_axis_tready => m_axis_tready, + m_axis_tdata => m_axis_tdata, + m_axis_tkeep => m_axis_tkeep, + m_axis_tlast => m_axis_tlast + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axis_clock_converter.vhd when simulating +-- the core, axis_clock_converter. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v new file mode 100644 index 0000000..b09eff7 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v @@ -0,0 +1,35 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:06 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter_stub.v +// Design : axis_clock_converter +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "axis_clock_converter_v1_1_23_axis_clock_converter,Vivado 2020.2" *) +module axis_clock_converter(s_axis_aresetn, m_axis_aresetn, s_axis_aclk, + s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tkeep, s_axis_tlast, m_axis_aclk, + m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tlast) +/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,m_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[255:0],s_axis_tkeep[31:0],s_axis_tlast,m_axis_aclk,m_axis_tvalid,m_axis_tready,m_axis_tdata[255:0],m_axis_tkeep[31:0],m_axis_tlast" */; + input s_axis_aresetn; + input m_axis_aresetn; + input s_axis_aclk; + input s_axis_tvalid; + output s_axis_tready; + input [255:0]s_axis_tdata; + input [31:0]s_axis_tkeep; + input s_axis_tlast; + input m_axis_aclk; + output m_axis_tvalid; + input m_axis_tready; + output [255:0]m_axis_tdata; + output [31:0]m_axis_tkeep; + output m_axis_tlast; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl new file mode 100644 index 0000000..7b85852 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl @@ -0,0 +1,43 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:06 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter_stub.vhdl +-- Design : axis_clock_converter +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity axis_clock_converter is + Port ( + s_axis_aresetn : in STD_LOGIC; + m_axis_aresetn : in STD_LOGIC; + s_axis_aclk : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + s_axis_tkeep : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axis_tlast : in STD_LOGIC; + m_axis_aclk : in STD_LOGIC; + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); + m_axis_tkeep : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axis_tlast : out STD_LOGIC + ); + +end axis_clock_converter; + +architecture stub of axis_clock_converter is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,m_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[255:0],s_axis_tkeep[31:0],s_axis_tlast,m_axis_aclk,m_axis_tvalid,m_axis_tready,m_axis_tdata[255:0],m_axis_tkeep[31:0],m_axis_tlast"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "axis_clock_converter_v1_1_23_axis_clock_converter,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.veo new file mode 100755 index 0000000..3624678 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.veo @@ -0,0 +1,66 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:c_counter_binary:12.0 +// IP Revision: 14 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +c_counter_binary_0 your_instance_name ( + .CLK(CLK), // input wire CLK + .Q(Q) // output wire [15 : 0] Q +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file c_counter_binary_0.v when simulating +// the core, c_counter_binary_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.vho new file mode 100755 index 0000000..1bb607b --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/c_counter_binary_0/c_counter_binary_0.vho @@ -0,0 +1,77 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:c_counter_binary:12.0 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT c_counter_binary_0 + PORT ( + CLK : IN STD_LOGIC; + Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : c_counter_binary_0 + PORT MAP ( + CLK => CLK, + Q => Q + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file c_counter_binary_0.vhd when simulating +-- the core, c_counter_binary_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.veo new file mode 100755 index 0000000..eacc00d --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.veo @@ -0,0 +1,76 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +cdc_fifo your_instance_name ( + .srst(srst), // input wire srst + .wr_clk(wr_clk), // input wire wr_clk + .rd_clk(rd_clk), // input wire rd_clk + .din(din), // input wire [511 : 0] din + .wr_en(wr_en), // input wire wr_en + .rd_en(rd_en), // input wire rd_en + .dout(dout), // output wire [511 : 0] dout + .full(full), // output wire full + .empty(empty), // output wire empty + .valid(valid), // output wire valid + .wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy + .rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file cdc_fifo.v when simulating +// the core, cdc_fifo. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.vho new file mode 100755 index 0000000..1f0fb6a --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo.vho @@ -0,0 +1,97 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fifo_generator:13.2 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT cdc_fifo + PORT ( + srst : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + valid : OUT STD_LOGIC; + wr_rst_busy : OUT STD_LOGIC; + rd_rst_busy : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : cdc_fifo + PORT MAP ( + srst => srst, + wr_clk => wr_clk, + rd_clk => rd_clk, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty, + valid => valid, + wr_rst_busy => wr_rst_busy, + rd_rst_busy => rd_rst_busy + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file cdc_fifo.vhd when simulating +-- the core, cdc_fifo. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.v new file mode 100644 index 0000000..5c3839f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.v @@ -0,0 +1,32 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:09 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cdc_fifo/cdc_fifo_stub.v +// Design : cdc_fifo +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *) +module cdc_fifo(srst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, + empty, valid, wr_rst_busy, rd_rst_busy) +/* synthesis syn_black_box black_box_pad_pin="srst,wr_clk,rd_clk,din[511:0],wr_en,rd_en,dout[511:0],full,empty,valid,wr_rst_busy,rd_rst_busy" */; + input srst; + input wr_clk; + input rd_clk; + input [511:0]din; + input wr_en; + input rd_en; + output [511:0]dout; + output full; + output empty; + output valid; + output wr_rst_busy; + output rd_rst_busy; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.vhdl new file mode 100644 index 0000000..a6cd581 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cdc_fifo/cdc_fifo_stub.vhdl @@ -0,0 +1,41 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:09 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cdc_fifo/cdc_fifo_stub.vhdl +-- Design : cdc_fifo +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity cdc_fifo is + Port ( + srst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 511 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 511 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + valid : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC + ); + +end cdc_fifo; + +architecture stub of cdc_fifo is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "srst,wr_clk,rd_clk,din[511:0],wr_en,rd_en,dout[511:0],full,empty,valid,wr_rst_busy,rd_rst_busy"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo new file mode 100755 index 0000000..e02f568 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo @@ -0,0 +1,80 @@ + +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_150MHz__150.00000______0.000______50.0______127.220____105.461 +// clk_300MHz__300.00000______0.000______50.0______111.879____105.461 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clk_wiz_0 instance_name + ( + // Clock out ports + .clk_150MHz(clk_150MHz), // output clk_150MHz + .clk_300MHz(clk_300MHz), // output clk_300MHz + // Clock in ports + .clk_in1(clk_in1)); // input clk_in1 + +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100644 index 0000000..4a2e0b1 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,21 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:07 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module clk_wiz_0(clk_150MHz, clk_300MHz, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="clk_150MHz,clk_300MHz,clk_in1" */; + output clk_150MHz; + output clk_300MHz; + input clk_in1; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..0cc7f9e --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,30 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:07 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + clk_150MHz : out STD_LOGIC; + clk_300MHz : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + +end clk_wiz_0; + +architecture stub of clk_wiz_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_150MHz,clk_300MHz,clk_in1"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.veo new file mode 100755 index 0000000..4a0a893 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.veo @@ -0,0 +1,75 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +cmd_fifo your_instance_name ( + .srst(srst), // input wire srst + .wr_clk(wr_clk), // input wire wr_clk + .rd_clk(rd_clk), // input wire rd_clk + .din(din), // input wire [127 : 0] din + .wr_en(wr_en), // input wire wr_en + .rd_en(rd_en), // input wire rd_en + .dout(dout), // output wire [63 : 0] dout + .full(full), // output wire full + .empty(empty), // output wire empty + .wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy + .rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file cmd_fifo.v when simulating +// the core, cmd_fifo. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.vho new file mode 100755 index 0000000..3dedecb --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo.vho @@ -0,0 +1,95 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fifo_generator:13.2 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT cmd_fifo + PORT ( + srst : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + wr_rst_busy : OUT STD_LOGIC; + rd_rst_busy : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : cmd_fifo + PORT MAP ( + srst => srst, + wr_clk => wr_clk, + rd_clk => rd_clk, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty, + wr_rst_busy => wr_rst_busy, + rd_rst_busy => rd_rst_busy + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file cmd_fifo.vhd when simulating +-- the core, cmd_fifo. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.v new file mode 100644 index 0000000..05d0459 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:22 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cmd_fifo/cmd_fifo_stub.v +// Design : cmd_fifo +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *) +module cmd_fifo(srst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, + empty, wr_rst_busy, rd_rst_busy) +/* synthesis syn_black_box black_box_pad_pin="srst,wr_clk,rd_clk,din[127:0],wr_en,rd_en,dout[63:0],full,empty,wr_rst_busy,rd_rst_busy" */; + input srst; + input wr_clk; + input rd_clk; + input [127:0]din; + input wr_en; + input rd_en; + output [63:0]dout; + output full; + output empty; + output wr_rst_busy; + output rd_rst_busy; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.vhdl new file mode 100644 index 0000000..478af91 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/cmd_fifo/cmd_fifo_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:22 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cmd_fifo/cmd_fifo_stub.vhdl +-- Design : cmd_fifo +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity cmd_fifo is + Port ( + srst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 127 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 63 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC + ); + +end cmd_fifo; + +architecture stub of cmd_fifo is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "srst,wr_clk,rd_clk,din[127:0],wr_en,rd_en,dout[63:0],full,empty,wr_rst_busy,rd_rst_busy"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.veo new file mode 100755 index 0000000..aa6f294 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.veo @@ -0,0 +1,892 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:hbm:1.0 +// IP Revision: 9 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +hbm_0 your_instance_name ( + .HBM_REF_CLK_0(HBM_REF_CLK_0), // input wire HBM_REF_CLK_0 + .HBM_REF_CLK_1(HBM_REF_CLK_1), // input wire HBM_REF_CLK_1 + .dfi_0_clk(dfi_0_clk), // input wire dfi_0_clk + .dfi_0_rst_n(dfi_0_rst_n), // input wire dfi_0_rst_n + .dfi_0_init_start(dfi_0_init_start), // input wire dfi_0_init_start + .dfi_0_aw_ck_p0(dfi_0_aw_ck_p0), // input wire [1 : 0] dfi_0_aw_ck_p0 + .dfi_0_aw_cke_p0(dfi_0_aw_cke_p0), // input wire [1 : 0] dfi_0_aw_cke_p0 + .dfi_0_aw_row_p0(dfi_0_aw_row_p0), // input wire [11 : 0] dfi_0_aw_row_p0 + .dfi_0_aw_col_p0(dfi_0_aw_col_p0), // input wire [15 : 0] dfi_0_aw_col_p0 + .dfi_0_dw_wrdata_p0(dfi_0_dw_wrdata_p0), // input wire [255 : 0] dfi_0_dw_wrdata_p0 + .dfi_0_dw_wrdata_mask_p0(dfi_0_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_0_dw_wrdata_mask_p0 + .dfi_0_dw_wrdata_dbi_p0(dfi_0_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_0_dw_wrdata_dbi_p0 + .dfi_0_dw_wrdata_par_p0(dfi_0_dw_wrdata_par_p0), // input wire [7 : 0] dfi_0_dw_wrdata_par_p0 + .dfi_0_dw_wrdata_dq_en_p0(dfi_0_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_0_dw_wrdata_dq_en_p0 + .dfi_0_dw_wrdata_par_en_p0(dfi_0_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_0_dw_wrdata_par_en_p0 + .dfi_0_aw_ck_p1(dfi_0_aw_ck_p1), // input wire [1 : 0] dfi_0_aw_ck_p1 + .dfi_0_aw_cke_p1(dfi_0_aw_cke_p1), // input wire [1 : 0] dfi_0_aw_cke_p1 + .dfi_0_aw_row_p1(dfi_0_aw_row_p1), // input wire [11 : 0] dfi_0_aw_row_p1 + .dfi_0_aw_col_p1(dfi_0_aw_col_p1), // input wire [15 : 0] dfi_0_aw_col_p1 + .dfi_0_dw_wrdata_p1(dfi_0_dw_wrdata_p1), // input wire [255 : 0] dfi_0_dw_wrdata_p1 + .dfi_0_dw_wrdata_mask_p1(dfi_0_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_0_dw_wrdata_mask_p1 + .dfi_0_dw_wrdata_dbi_p1(dfi_0_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_0_dw_wrdata_dbi_p1 + .dfi_0_dw_wrdata_par_p1(dfi_0_dw_wrdata_par_p1), // input wire [7 : 0] dfi_0_dw_wrdata_par_p1 + .dfi_0_dw_wrdata_dq_en_p1(dfi_0_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_0_dw_wrdata_dq_en_p1 + .dfi_0_dw_wrdata_par_en_p1(dfi_0_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_0_dw_wrdata_par_en_p1 + .dfi_0_aw_ck_dis(dfi_0_aw_ck_dis), // input wire dfi_0_aw_ck_dis + .dfi_0_lp_pwr_e_req(dfi_0_lp_pwr_e_req), // input wire dfi_0_lp_pwr_e_req + .dfi_0_lp_sr_e_req(dfi_0_lp_sr_e_req), // input wire dfi_0_lp_sr_e_req + .dfi_0_lp_pwr_x_req(dfi_0_lp_pwr_x_req), // input wire dfi_0_lp_pwr_x_req + .dfi_0_aw_tx_indx_ld(dfi_0_aw_tx_indx_ld), // input wire dfi_0_aw_tx_indx_ld + .dfi_0_dw_tx_indx_ld(dfi_0_dw_tx_indx_ld), // input wire dfi_0_dw_tx_indx_ld + .dfi_0_dw_rx_indx_ld(dfi_0_dw_rx_indx_ld), // input wire dfi_0_dw_rx_indx_ld + .dfi_0_ctrlupd_ack(dfi_0_ctrlupd_ack), // input wire dfi_0_ctrlupd_ack + .dfi_0_phyupd_req(dfi_0_phyupd_req), // input wire dfi_0_phyupd_req + .dfi_0_dw_wrdata_dqs_p0(dfi_0_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_0_dw_wrdata_dqs_p0 + .dfi_0_dw_wrdata_dqs_p1(dfi_0_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_0_dw_wrdata_dqs_p1 + .dfi_1_clk(dfi_1_clk), // input wire dfi_1_clk + .dfi_1_rst_n(dfi_1_rst_n), // input wire dfi_1_rst_n + .dfi_1_init_start(dfi_1_init_start), // input wire dfi_1_init_start + .dfi_1_aw_ck_p0(dfi_1_aw_ck_p0), // input wire [1 : 0] dfi_1_aw_ck_p0 + .dfi_1_aw_cke_p0(dfi_1_aw_cke_p0), // input wire [1 : 0] dfi_1_aw_cke_p0 + .dfi_1_aw_row_p0(dfi_1_aw_row_p0), // input wire [11 : 0] dfi_1_aw_row_p0 + .dfi_1_aw_col_p0(dfi_1_aw_col_p0), // input wire [15 : 0] dfi_1_aw_col_p0 + .dfi_1_dw_wrdata_p0(dfi_1_dw_wrdata_p0), // input wire [255 : 0] dfi_1_dw_wrdata_p0 + .dfi_1_dw_wrdata_mask_p0(dfi_1_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_1_dw_wrdata_mask_p0 + .dfi_1_dw_wrdata_dbi_p0(dfi_1_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_1_dw_wrdata_dbi_p0 + .dfi_1_dw_wrdata_par_p0(dfi_1_dw_wrdata_par_p0), // input wire [7 : 0] dfi_1_dw_wrdata_par_p0 + .dfi_1_dw_wrdata_dq_en_p0(dfi_1_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_1_dw_wrdata_dq_en_p0 + .dfi_1_dw_wrdata_par_en_p0(dfi_1_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_1_dw_wrdata_par_en_p0 + .dfi_1_aw_ck_p1(dfi_1_aw_ck_p1), // input wire [1 : 0] dfi_1_aw_ck_p1 + .dfi_1_aw_cke_p1(dfi_1_aw_cke_p1), // input wire [1 : 0] dfi_1_aw_cke_p1 + .dfi_1_aw_row_p1(dfi_1_aw_row_p1), // input wire [11 : 0] dfi_1_aw_row_p1 + .dfi_1_aw_col_p1(dfi_1_aw_col_p1), // input wire [15 : 0] dfi_1_aw_col_p1 + .dfi_1_dw_wrdata_p1(dfi_1_dw_wrdata_p1), // input wire [255 : 0] dfi_1_dw_wrdata_p1 + .dfi_1_dw_wrdata_mask_p1(dfi_1_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_1_dw_wrdata_mask_p1 + .dfi_1_dw_wrdata_dbi_p1(dfi_1_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_1_dw_wrdata_dbi_p1 + .dfi_1_dw_wrdata_par_p1(dfi_1_dw_wrdata_par_p1), // input wire [7 : 0] dfi_1_dw_wrdata_par_p1 + .dfi_1_dw_wrdata_dq_en_p1(dfi_1_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_1_dw_wrdata_dq_en_p1 + .dfi_1_dw_wrdata_par_en_p1(dfi_1_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_1_dw_wrdata_par_en_p1 + .dfi_1_aw_ck_dis(dfi_1_aw_ck_dis), // input wire dfi_1_aw_ck_dis + .dfi_1_lp_pwr_e_req(dfi_1_lp_pwr_e_req), // input wire dfi_1_lp_pwr_e_req + .dfi_1_lp_sr_e_req(dfi_1_lp_sr_e_req), // input wire dfi_1_lp_sr_e_req + .dfi_1_lp_pwr_x_req(dfi_1_lp_pwr_x_req), // input wire dfi_1_lp_pwr_x_req + .dfi_1_aw_tx_indx_ld(dfi_1_aw_tx_indx_ld), // input wire dfi_1_aw_tx_indx_ld + .dfi_1_dw_tx_indx_ld(dfi_1_dw_tx_indx_ld), // input wire dfi_1_dw_tx_indx_ld + .dfi_1_dw_rx_indx_ld(dfi_1_dw_rx_indx_ld), // input wire dfi_1_dw_rx_indx_ld + .dfi_1_ctrlupd_ack(dfi_1_ctrlupd_ack), // input wire dfi_1_ctrlupd_ack + .dfi_1_phyupd_req(dfi_1_phyupd_req), // input wire dfi_1_phyupd_req + .dfi_1_dw_wrdata_dqs_p0(dfi_1_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_1_dw_wrdata_dqs_p0 + .dfi_1_dw_wrdata_dqs_p1(dfi_1_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_1_dw_wrdata_dqs_p1 + .dfi_2_clk(dfi_2_clk), // input wire dfi_2_clk + .dfi_2_rst_n(dfi_2_rst_n), // input wire dfi_2_rst_n + .dfi_2_init_start(dfi_2_init_start), // input wire dfi_2_init_start + .dfi_2_aw_ck_p0(dfi_2_aw_ck_p0), // input wire [1 : 0] dfi_2_aw_ck_p0 + .dfi_2_aw_cke_p0(dfi_2_aw_cke_p0), // input wire [1 : 0] dfi_2_aw_cke_p0 + .dfi_2_aw_row_p0(dfi_2_aw_row_p0), // input wire [11 : 0] dfi_2_aw_row_p0 + .dfi_2_aw_col_p0(dfi_2_aw_col_p0), // input wire [15 : 0] dfi_2_aw_col_p0 + .dfi_2_dw_wrdata_p0(dfi_2_dw_wrdata_p0), // input wire [255 : 0] dfi_2_dw_wrdata_p0 + .dfi_2_dw_wrdata_mask_p0(dfi_2_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_2_dw_wrdata_mask_p0 + .dfi_2_dw_wrdata_dbi_p0(dfi_2_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_2_dw_wrdata_dbi_p0 + .dfi_2_dw_wrdata_par_p0(dfi_2_dw_wrdata_par_p0), // input wire [7 : 0] dfi_2_dw_wrdata_par_p0 + .dfi_2_dw_wrdata_dq_en_p0(dfi_2_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_2_dw_wrdata_dq_en_p0 + .dfi_2_dw_wrdata_par_en_p0(dfi_2_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_2_dw_wrdata_par_en_p0 + .dfi_2_aw_ck_p1(dfi_2_aw_ck_p1), // input wire [1 : 0] dfi_2_aw_ck_p1 + .dfi_2_aw_cke_p1(dfi_2_aw_cke_p1), // input wire [1 : 0] dfi_2_aw_cke_p1 + .dfi_2_aw_row_p1(dfi_2_aw_row_p1), // input wire [11 : 0] dfi_2_aw_row_p1 + .dfi_2_aw_col_p1(dfi_2_aw_col_p1), // input wire [15 : 0] dfi_2_aw_col_p1 + .dfi_2_dw_wrdata_p1(dfi_2_dw_wrdata_p1), // input wire [255 : 0] dfi_2_dw_wrdata_p1 + .dfi_2_dw_wrdata_mask_p1(dfi_2_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_2_dw_wrdata_mask_p1 + .dfi_2_dw_wrdata_dbi_p1(dfi_2_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_2_dw_wrdata_dbi_p1 + .dfi_2_dw_wrdata_par_p1(dfi_2_dw_wrdata_par_p1), // input wire [7 : 0] dfi_2_dw_wrdata_par_p1 + .dfi_2_dw_wrdata_dq_en_p1(dfi_2_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_2_dw_wrdata_dq_en_p1 + .dfi_2_dw_wrdata_par_en_p1(dfi_2_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_2_dw_wrdata_par_en_p1 + .dfi_2_aw_ck_dis(dfi_2_aw_ck_dis), // input wire dfi_2_aw_ck_dis + .dfi_2_lp_pwr_e_req(dfi_2_lp_pwr_e_req), // input wire dfi_2_lp_pwr_e_req + .dfi_2_lp_sr_e_req(dfi_2_lp_sr_e_req), // input wire dfi_2_lp_sr_e_req + .dfi_2_lp_pwr_x_req(dfi_2_lp_pwr_x_req), // input wire dfi_2_lp_pwr_x_req + .dfi_2_aw_tx_indx_ld(dfi_2_aw_tx_indx_ld), // input wire dfi_2_aw_tx_indx_ld + .dfi_2_dw_tx_indx_ld(dfi_2_dw_tx_indx_ld), // input wire dfi_2_dw_tx_indx_ld + .dfi_2_dw_rx_indx_ld(dfi_2_dw_rx_indx_ld), // input wire dfi_2_dw_rx_indx_ld + .dfi_2_ctrlupd_ack(dfi_2_ctrlupd_ack), // input wire dfi_2_ctrlupd_ack + .dfi_2_phyupd_req(dfi_2_phyupd_req), // input wire dfi_2_phyupd_req + .dfi_2_dw_wrdata_dqs_p0(dfi_2_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_2_dw_wrdata_dqs_p0 + .dfi_2_dw_wrdata_dqs_p1(dfi_2_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_2_dw_wrdata_dqs_p1 + .dfi_3_clk(dfi_3_clk), // input wire dfi_3_clk + .dfi_3_rst_n(dfi_3_rst_n), // input wire dfi_3_rst_n + .dfi_3_init_start(dfi_3_init_start), // input wire dfi_3_init_start + .dfi_3_aw_ck_p0(dfi_3_aw_ck_p0), // input wire [1 : 0] dfi_3_aw_ck_p0 + .dfi_3_aw_cke_p0(dfi_3_aw_cke_p0), // input wire [1 : 0] dfi_3_aw_cke_p0 + .dfi_3_aw_row_p0(dfi_3_aw_row_p0), // input wire [11 : 0] dfi_3_aw_row_p0 + .dfi_3_aw_col_p0(dfi_3_aw_col_p0), // input wire [15 : 0] dfi_3_aw_col_p0 + .dfi_3_dw_wrdata_p0(dfi_3_dw_wrdata_p0), // input wire [255 : 0] dfi_3_dw_wrdata_p0 + .dfi_3_dw_wrdata_mask_p0(dfi_3_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_3_dw_wrdata_mask_p0 + .dfi_3_dw_wrdata_dbi_p0(dfi_3_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_3_dw_wrdata_dbi_p0 + .dfi_3_dw_wrdata_par_p0(dfi_3_dw_wrdata_par_p0), // input wire [7 : 0] dfi_3_dw_wrdata_par_p0 + .dfi_3_dw_wrdata_dq_en_p0(dfi_3_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_3_dw_wrdata_dq_en_p0 + .dfi_3_dw_wrdata_par_en_p0(dfi_3_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_3_dw_wrdata_par_en_p0 + .dfi_3_aw_ck_p1(dfi_3_aw_ck_p1), // input wire [1 : 0] dfi_3_aw_ck_p1 + .dfi_3_aw_cke_p1(dfi_3_aw_cke_p1), // input wire [1 : 0] dfi_3_aw_cke_p1 + .dfi_3_aw_row_p1(dfi_3_aw_row_p1), // input wire [11 : 0] dfi_3_aw_row_p1 + .dfi_3_aw_col_p1(dfi_3_aw_col_p1), // input wire [15 : 0] dfi_3_aw_col_p1 + .dfi_3_dw_wrdata_p1(dfi_3_dw_wrdata_p1), // input wire [255 : 0] dfi_3_dw_wrdata_p1 + .dfi_3_dw_wrdata_mask_p1(dfi_3_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_3_dw_wrdata_mask_p1 + .dfi_3_dw_wrdata_dbi_p1(dfi_3_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_3_dw_wrdata_dbi_p1 + .dfi_3_dw_wrdata_par_p1(dfi_3_dw_wrdata_par_p1), // input wire [7 : 0] dfi_3_dw_wrdata_par_p1 + .dfi_3_dw_wrdata_dq_en_p1(dfi_3_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_3_dw_wrdata_dq_en_p1 + .dfi_3_dw_wrdata_par_en_p1(dfi_3_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_3_dw_wrdata_par_en_p1 + .dfi_3_aw_ck_dis(dfi_3_aw_ck_dis), // input wire dfi_3_aw_ck_dis + .dfi_3_lp_pwr_e_req(dfi_3_lp_pwr_e_req), // input wire dfi_3_lp_pwr_e_req + .dfi_3_lp_sr_e_req(dfi_3_lp_sr_e_req), // input wire dfi_3_lp_sr_e_req + .dfi_3_lp_pwr_x_req(dfi_3_lp_pwr_x_req), // input wire dfi_3_lp_pwr_x_req + .dfi_3_aw_tx_indx_ld(dfi_3_aw_tx_indx_ld), // input wire dfi_3_aw_tx_indx_ld + .dfi_3_dw_tx_indx_ld(dfi_3_dw_tx_indx_ld), // input wire dfi_3_dw_tx_indx_ld + .dfi_3_dw_rx_indx_ld(dfi_3_dw_rx_indx_ld), // input wire dfi_3_dw_rx_indx_ld + .dfi_3_ctrlupd_ack(dfi_3_ctrlupd_ack), // input wire dfi_3_ctrlupd_ack + .dfi_3_phyupd_req(dfi_3_phyupd_req), // input wire dfi_3_phyupd_req + .dfi_3_dw_wrdata_dqs_p0(dfi_3_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_3_dw_wrdata_dqs_p0 + .dfi_3_dw_wrdata_dqs_p1(dfi_3_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_3_dw_wrdata_dqs_p1 + .dfi_4_clk(dfi_4_clk), // input wire dfi_4_clk + .dfi_4_rst_n(dfi_4_rst_n), // input wire dfi_4_rst_n + .dfi_4_init_start(dfi_4_init_start), // input wire dfi_4_init_start + .dfi_4_aw_ck_p0(dfi_4_aw_ck_p0), // input wire [1 : 0] dfi_4_aw_ck_p0 + .dfi_4_aw_cke_p0(dfi_4_aw_cke_p0), // input wire [1 : 0] dfi_4_aw_cke_p0 + .dfi_4_aw_row_p0(dfi_4_aw_row_p0), // input wire [11 : 0] dfi_4_aw_row_p0 + .dfi_4_aw_col_p0(dfi_4_aw_col_p0), // input wire [15 : 0] dfi_4_aw_col_p0 + .dfi_4_dw_wrdata_p0(dfi_4_dw_wrdata_p0), // input wire [255 : 0] dfi_4_dw_wrdata_p0 + .dfi_4_dw_wrdata_mask_p0(dfi_4_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_4_dw_wrdata_mask_p0 + .dfi_4_dw_wrdata_dbi_p0(dfi_4_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_4_dw_wrdata_dbi_p0 + .dfi_4_dw_wrdata_par_p0(dfi_4_dw_wrdata_par_p0), // input wire [7 : 0] dfi_4_dw_wrdata_par_p0 + .dfi_4_dw_wrdata_dq_en_p0(dfi_4_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_4_dw_wrdata_dq_en_p0 + .dfi_4_dw_wrdata_par_en_p0(dfi_4_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_4_dw_wrdata_par_en_p0 + .dfi_4_aw_ck_p1(dfi_4_aw_ck_p1), // input wire [1 : 0] dfi_4_aw_ck_p1 + .dfi_4_aw_cke_p1(dfi_4_aw_cke_p1), // input wire [1 : 0] dfi_4_aw_cke_p1 + .dfi_4_aw_row_p1(dfi_4_aw_row_p1), // input wire [11 : 0] dfi_4_aw_row_p1 + .dfi_4_aw_col_p1(dfi_4_aw_col_p1), // input wire [15 : 0] dfi_4_aw_col_p1 + .dfi_4_dw_wrdata_p1(dfi_4_dw_wrdata_p1), // input wire [255 : 0] dfi_4_dw_wrdata_p1 + .dfi_4_dw_wrdata_mask_p1(dfi_4_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_4_dw_wrdata_mask_p1 + .dfi_4_dw_wrdata_dbi_p1(dfi_4_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_4_dw_wrdata_dbi_p1 + .dfi_4_dw_wrdata_par_p1(dfi_4_dw_wrdata_par_p1), // input wire [7 : 0] dfi_4_dw_wrdata_par_p1 + .dfi_4_dw_wrdata_dq_en_p1(dfi_4_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_4_dw_wrdata_dq_en_p1 + .dfi_4_dw_wrdata_par_en_p1(dfi_4_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_4_dw_wrdata_par_en_p1 + .dfi_4_aw_ck_dis(dfi_4_aw_ck_dis), // input wire dfi_4_aw_ck_dis + .dfi_4_lp_pwr_e_req(dfi_4_lp_pwr_e_req), // input wire dfi_4_lp_pwr_e_req + .dfi_4_lp_sr_e_req(dfi_4_lp_sr_e_req), // input wire dfi_4_lp_sr_e_req + .dfi_4_lp_pwr_x_req(dfi_4_lp_pwr_x_req), // input wire dfi_4_lp_pwr_x_req + .dfi_4_aw_tx_indx_ld(dfi_4_aw_tx_indx_ld), // input wire dfi_4_aw_tx_indx_ld + .dfi_4_dw_tx_indx_ld(dfi_4_dw_tx_indx_ld), // input wire dfi_4_dw_tx_indx_ld + .dfi_4_dw_rx_indx_ld(dfi_4_dw_rx_indx_ld), // input wire dfi_4_dw_rx_indx_ld + .dfi_4_ctrlupd_ack(dfi_4_ctrlupd_ack), // input wire dfi_4_ctrlupd_ack + .dfi_4_phyupd_req(dfi_4_phyupd_req), // input wire dfi_4_phyupd_req + .dfi_4_dw_wrdata_dqs_p0(dfi_4_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_4_dw_wrdata_dqs_p0 + .dfi_4_dw_wrdata_dqs_p1(dfi_4_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_4_dw_wrdata_dqs_p1 + .dfi_5_clk(dfi_5_clk), // input wire dfi_5_clk + .dfi_5_rst_n(dfi_5_rst_n), // input wire dfi_5_rst_n + .dfi_5_init_start(dfi_5_init_start), // input wire dfi_5_init_start + .dfi_5_aw_ck_p0(dfi_5_aw_ck_p0), // input wire [1 : 0] dfi_5_aw_ck_p0 + .dfi_5_aw_cke_p0(dfi_5_aw_cke_p0), // input wire [1 : 0] dfi_5_aw_cke_p0 + .dfi_5_aw_row_p0(dfi_5_aw_row_p0), // input wire [11 : 0] dfi_5_aw_row_p0 + .dfi_5_aw_col_p0(dfi_5_aw_col_p0), // input wire [15 : 0] dfi_5_aw_col_p0 + .dfi_5_dw_wrdata_p0(dfi_5_dw_wrdata_p0), // input wire [255 : 0] dfi_5_dw_wrdata_p0 + .dfi_5_dw_wrdata_mask_p0(dfi_5_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_5_dw_wrdata_mask_p0 + .dfi_5_dw_wrdata_dbi_p0(dfi_5_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_5_dw_wrdata_dbi_p0 + .dfi_5_dw_wrdata_par_p0(dfi_5_dw_wrdata_par_p0), // input wire [7 : 0] dfi_5_dw_wrdata_par_p0 + .dfi_5_dw_wrdata_dq_en_p0(dfi_5_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_5_dw_wrdata_dq_en_p0 + .dfi_5_dw_wrdata_par_en_p0(dfi_5_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_5_dw_wrdata_par_en_p0 + .dfi_5_aw_ck_p1(dfi_5_aw_ck_p1), // input wire [1 : 0] dfi_5_aw_ck_p1 + .dfi_5_aw_cke_p1(dfi_5_aw_cke_p1), // input wire [1 : 0] dfi_5_aw_cke_p1 + .dfi_5_aw_row_p1(dfi_5_aw_row_p1), // input wire [11 : 0] dfi_5_aw_row_p1 + .dfi_5_aw_col_p1(dfi_5_aw_col_p1), // input wire [15 : 0] dfi_5_aw_col_p1 + .dfi_5_dw_wrdata_p1(dfi_5_dw_wrdata_p1), // input wire [255 : 0] dfi_5_dw_wrdata_p1 + .dfi_5_dw_wrdata_mask_p1(dfi_5_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_5_dw_wrdata_mask_p1 + .dfi_5_dw_wrdata_dbi_p1(dfi_5_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_5_dw_wrdata_dbi_p1 + .dfi_5_dw_wrdata_par_p1(dfi_5_dw_wrdata_par_p1), // input wire [7 : 0] dfi_5_dw_wrdata_par_p1 + .dfi_5_dw_wrdata_dq_en_p1(dfi_5_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_5_dw_wrdata_dq_en_p1 + .dfi_5_dw_wrdata_par_en_p1(dfi_5_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_5_dw_wrdata_par_en_p1 + .dfi_5_aw_ck_dis(dfi_5_aw_ck_dis), // input wire dfi_5_aw_ck_dis + .dfi_5_lp_pwr_e_req(dfi_5_lp_pwr_e_req), // input wire dfi_5_lp_pwr_e_req + .dfi_5_lp_sr_e_req(dfi_5_lp_sr_e_req), // input wire dfi_5_lp_sr_e_req + .dfi_5_lp_pwr_x_req(dfi_5_lp_pwr_x_req), // input wire dfi_5_lp_pwr_x_req + .dfi_5_aw_tx_indx_ld(dfi_5_aw_tx_indx_ld), // input wire dfi_5_aw_tx_indx_ld + .dfi_5_dw_tx_indx_ld(dfi_5_dw_tx_indx_ld), // input wire dfi_5_dw_tx_indx_ld + .dfi_5_dw_rx_indx_ld(dfi_5_dw_rx_indx_ld), // input wire dfi_5_dw_rx_indx_ld + .dfi_5_ctrlupd_ack(dfi_5_ctrlupd_ack), // input wire dfi_5_ctrlupd_ack + .dfi_5_phyupd_req(dfi_5_phyupd_req), // input wire dfi_5_phyupd_req + .dfi_5_dw_wrdata_dqs_p0(dfi_5_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_5_dw_wrdata_dqs_p0 + .dfi_5_dw_wrdata_dqs_p1(dfi_5_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_5_dw_wrdata_dqs_p1 + .dfi_6_clk(dfi_6_clk), // input wire dfi_6_clk + .dfi_6_rst_n(dfi_6_rst_n), // input wire dfi_6_rst_n + .dfi_6_init_start(dfi_6_init_start), // input wire dfi_6_init_start + .dfi_6_aw_ck_p0(dfi_6_aw_ck_p0), // input wire [1 : 0] dfi_6_aw_ck_p0 + .dfi_6_aw_cke_p0(dfi_6_aw_cke_p0), // input wire [1 : 0] dfi_6_aw_cke_p0 + .dfi_6_aw_row_p0(dfi_6_aw_row_p0), // input wire [11 : 0] dfi_6_aw_row_p0 + .dfi_6_aw_col_p0(dfi_6_aw_col_p0), // input wire [15 : 0] dfi_6_aw_col_p0 + .dfi_6_dw_wrdata_p0(dfi_6_dw_wrdata_p0), // input wire [255 : 0] dfi_6_dw_wrdata_p0 + .dfi_6_dw_wrdata_mask_p0(dfi_6_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_6_dw_wrdata_mask_p0 + .dfi_6_dw_wrdata_dbi_p0(dfi_6_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_6_dw_wrdata_dbi_p0 + .dfi_6_dw_wrdata_par_p0(dfi_6_dw_wrdata_par_p0), // input wire [7 : 0] dfi_6_dw_wrdata_par_p0 + .dfi_6_dw_wrdata_dq_en_p0(dfi_6_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_6_dw_wrdata_dq_en_p0 + .dfi_6_dw_wrdata_par_en_p0(dfi_6_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_6_dw_wrdata_par_en_p0 + .dfi_6_aw_ck_p1(dfi_6_aw_ck_p1), // input wire [1 : 0] dfi_6_aw_ck_p1 + .dfi_6_aw_cke_p1(dfi_6_aw_cke_p1), // input wire [1 : 0] dfi_6_aw_cke_p1 + .dfi_6_aw_row_p1(dfi_6_aw_row_p1), // input wire [11 : 0] dfi_6_aw_row_p1 + .dfi_6_aw_col_p1(dfi_6_aw_col_p1), // input wire [15 : 0] dfi_6_aw_col_p1 + .dfi_6_dw_wrdata_p1(dfi_6_dw_wrdata_p1), // input wire [255 : 0] dfi_6_dw_wrdata_p1 + .dfi_6_dw_wrdata_mask_p1(dfi_6_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_6_dw_wrdata_mask_p1 + .dfi_6_dw_wrdata_dbi_p1(dfi_6_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_6_dw_wrdata_dbi_p1 + .dfi_6_dw_wrdata_par_p1(dfi_6_dw_wrdata_par_p1), // input wire [7 : 0] dfi_6_dw_wrdata_par_p1 + .dfi_6_dw_wrdata_dq_en_p1(dfi_6_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_6_dw_wrdata_dq_en_p1 + .dfi_6_dw_wrdata_par_en_p1(dfi_6_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_6_dw_wrdata_par_en_p1 + .dfi_6_aw_ck_dis(dfi_6_aw_ck_dis), // input wire dfi_6_aw_ck_dis + .dfi_6_lp_pwr_e_req(dfi_6_lp_pwr_e_req), // input wire dfi_6_lp_pwr_e_req + .dfi_6_lp_sr_e_req(dfi_6_lp_sr_e_req), // input wire dfi_6_lp_sr_e_req + .dfi_6_lp_pwr_x_req(dfi_6_lp_pwr_x_req), // input wire dfi_6_lp_pwr_x_req + .dfi_6_aw_tx_indx_ld(dfi_6_aw_tx_indx_ld), // input wire dfi_6_aw_tx_indx_ld + .dfi_6_dw_tx_indx_ld(dfi_6_dw_tx_indx_ld), // input wire dfi_6_dw_tx_indx_ld + .dfi_6_dw_rx_indx_ld(dfi_6_dw_rx_indx_ld), // input wire dfi_6_dw_rx_indx_ld + .dfi_6_ctrlupd_ack(dfi_6_ctrlupd_ack), // input wire dfi_6_ctrlupd_ack + .dfi_6_phyupd_req(dfi_6_phyupd_req), // input wire dfi_6_phyupd_req + .dfi_6_dw_wrdata_dqs_p0(dfi_6_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_6_dw_wrdata_dqs_p0 + .dfi_6_dw_wrdata_dqs_p1(dfi_6_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_6_dw_wrdata_dqs_p1 + .dfi_7_clk(dfi_7_clk), // input wire dfi_7_clk + .dfi_7_rst_n(dfi_7_rst_n), // input wire dfi_7_rst_n + .dfi_7_init_start(dfi_7_init_start), // input wire dfi_7_init_start + .dfi_7_aw_ck_p0(dfi_7_aw_ck_p0), // input wire [1 : 0] dfi_7_aw_ck_p0 + .dfi_7_aw_cke_p0(dfi_7_aw_cke_p0), // input wire [1 : 0] dfi_7_aw_cke_p0 + .dfi_7_aw_row_p0(dfi_7_aw_row_p0), // input wire [11 : 0] dfi_7_aw_row_p0 + .dfi_7_aw_col_p0(dfi_7_aw_col_p0), // input wire [15 : 0] dfi_7_aw_col_p0 + .dfi_7_dw_wrdata_p0(dfi_7_dw_wrdata_p0), // input wire [255 : 0] dfi_7_dw_wrdata_p0 + .dfi_7_dw_wrdata_mask_p0(dfi_7_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_7_dw_wrdata_mask_p0 + .dfi_7_dw_wrdata_dbi_p0(dfi_7_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_7_dw_wrdata_dbi_p0 + .dfi_7_dw_wrdata_par_p0(dfi_7_dw_wrdata_par_p0), // input wire [7 : 0] dfi_7_dw_wrdata_par_p0 + .dfi_7_dw_wrdata_dq_en_p0(dfi_7_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_7_dw_wrdata_dq_en_p0 + .dfi_7_dw_wrdata_par_en_p0(dfi_7_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_7_dw_wrdata_par_en_p0 + .dfi_7_aw_ck_p1(dfi_7_aw_ck_p1), // input wire [1 : 0] dfi_7_aw_ck_p1 + .dfi_7_aw_cke_p1(dfi_7_aw_cke_p1), // input wire [1 : 0] dfi_7_aw_cke_p1 + .dfi_7_aw_row_p1(dfi_7_aw_row_p1), // input wire [11 : 0] dfi_7_aw_row_p1 + .dfi_7_aw_col_p1(dfi_7_aw_col_p1), // input wire [15 : 0] dfi_7_aw_col_p1 + .dfi_7_dw_wrdata_p1(dfi_7_dw_wrdata_p1), // input wire [255 : 0] dfi_7_dw_wrdata_p1 + .dfi_7_dw_wrdata_mask_p1(dfi_7_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_7_dw_wrdata_mask_p1 + .dfi_7_dw_wrdata_dbi_p1(dfi_7_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_7_dw_wrdata_dbi_p1 + .dfi_7_dw_wrdata_par_p1(dfi_7_dw_wrdata_par_p1), // input wire [7 : 0] dfi_7_dw_wrdata_par_p1 + .dfi_7_dw_wrdata_dq_en_p1(dfi_7_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_7_dw_wrdata_dq_en_p1 + .dfi_7_dw_wrdata_par_en_p1(dfi_7_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_7_dw_wrdata_par_en_p1 + .dfi_7_aw_ck_dis(dfi_7_aw_ck_dis), // input wire dfi_7_aw_ck_dis + .dfi_7_lp_pwr_e_req(dfi_7_lp_pwr_e_req), // input wire dfi_7_lp_pwr_e_req + .dfi_7_lp_sr_e_req(dfi_7_lp_sr_e_req), // input wire dfi_7_lp_sr_e_req + .dfi_7_lp_pwr_x_req(dfi_7_lp_pwr_x_req), // input wire dfi_7_lp_pwr_x_req + .dfi_7_aw_tx_indx_ld(dfi_7_aw_tx_indx_ld), // input wire dfi_7_aw_tx_indx_ld + .dfi_7_dw_tx_indx_ld(dfi_7_dw_tx_indx_ld), // input wire dfi_7_dw_tx_indx_ld + .dfi_7_dw_rx_indx_ld(dfi_7_dw_rx_indx_ld), // input wire dfi_7_dw_rx_indx_ld + .dfi_7_ctrlupd_ack(dfi_7_ctrlupd_ack), // input wire dfi_7_ctrlupd_ack + .dfi_7_phyupd_req(dfi_7_phyupd_req), // input wire dfi_7_phyupd_req + .dfi_7_dw_wrdata_dqs_p0(dfi_7_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_7_dw_wrdata_dqs_p0 + .dfi_7_dw_wrdata_dqs_p1(dfi_7_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_7_dw_wrdata_dqs_p1 + .dfi_8_clk(dfi_8_clk), // input wire dfi_8_clk + .dfi_8_rst_n(dfi_8_rst_n), // input wire dfi_8_rst_n + .dfi_8_init_start(dfi_8_init_start), // input wire dfi_8_init_start + .dfi_8_aw_ck_p0(dfi_8_aw_ck_p0), // input wire [1 : 0] dfi_8_aw_ck_p0 + .dfi_8_aw_cke_p0(dfi_8_aw_cke_p0), // input wire [1 : 0] dfi_8_aw_cke_p0 + .dfi_8_aw_row_p0(dfi_8_aw_row_p0), // input wire [11 : 0] dfi_8_aw_row_p0 + .dfi_8_aw_col_p0(dfi_8_aw_col_p0), // input wire [15 : 0] dfi_8_aw_col_p0 + .dfi_8_dw_wrdata_p0(dfi_8_dw_wrdata_p0), // input wire [255 : 0] dfi_8_dw_wrdata_p0 + .dfi_8_dw_wrdata_mask_p0(dfi_8_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_8_dw_wrdata_mask_p0 + .dfi_8_dw_wrdata_dbi_p0(dfi_8_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_8_dw_wrdata_dbi_p0 + .dfi_8_dw_wrdata_par_p0(dfi_8_dw_wrdata_par_p0), // input wire [7 : 0] dfi_8_dw_wrdata_par_p0 + .dfi_8_dw_wrdata_dq_en_p0(dfi_8_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_8_dw_wrdata_dq_en_p0 + .dfi_8_dw_wrdata_par_en_p0(dfi_8_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_8_dw_wrdata_par_en_p0 + .dfi_8_aw_ck_p1(dfi_8_aw_ck_p1), // input wire [1 : 0] dfi_8_aw_ck_p1 + .dfi_8_aw_cke_p1(dfi_8_aw_cke_p1), // input wire [1 : 0] dfi_8_aw_cke_p1 + .dfi_8_aw_row_p1(dfi_8_aw_row_p1), // input wire [11 : 0] dfi_8_aw_row_p1 + .dfi_8_aw_col_p1(dfi_8_aw_col_p1), // input wire [15 : 0] dfi_8_aw_col_p1 + .dfi_8_dw_wrdata_p1(dfi_8_dw_wrdata_p1), // input wire [255 : 0] dfi_8_dw_wrdata_p1 + .dfi_8_dw_wrdata_mask_p1(dfi_8_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_8_dw_wrdata_mask_p1 + .dfi_8_dw_wrdata_dbi_p1(dfi_8_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_8_dw_wrdata_dbi_p1 + .dfi_8_dw_wrdata_par_p1(dfi_8_dw_wrdata_par_p1), // input wire [7 : 0] dfi_8_dw_wrdata_par_p1 + .dfi_8_dw_wrdata_dq_en_p1(dfi_8_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_8_dw_wrdata_dq_en_p1 + .dfi_8_dw_wrdata_par_en_p1(dfi_8_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_8_dw_wrdata_par_en_p1 + .dfi_8_aw_ck_dis(dfi_8_aw_ck_dis), // input wire dfi_8_aw_ck_dis + .dfi_8_lp_pwr_e_req(dfi_8_lp_pwr_e_req), // input wire dfi_8_lp_pwr_e_req + .dfi_8_lp_sr_e_req(dfi_8_lp_sr_e_req), // input wire dfi_8_lp_sr_e_req + .dfi_8_lp_pwr_x_req(dfi_8_lp_pwr_x_req), // input wire dfi_8_lp_pwr_x_req + .dfi_8_aw_tx_indx_ld(dfi_8_aw_tx_indx_ld), // input wire dfi_8_aw_tx_indx_ld + .dfi_8_dw_tx_indx_ld(dfi_8_dw_tx_indx_ld), // input wire dfi_8_dw_tx_indx_ld + .dfi_8_dw_rx_indx_ld(dfi_8_dw_rx_indx_ld), // input wire dfi_8_dw_rx_indx_ld + .dfi_8_ctrlupd_ack(dfi_8_ctrlupd_ack), // input wire dfi_8_ctrlupd_ack + .dfi_8_phyupd_req(dfi_8_phyupd_req), // input wire dfi_8_phyupd_req + .dfi_8_dw_wrdata_dqs_p0(dfi_8_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_8_dw_wrdata_dqs_p0 + .dfi_8_dw_wrdata_dqs_p1(dfi_8_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_8_dw_wrdata_dqs_p1 + .dfi_9_clk(dfi_9_clk), // input wire dfi_9_clk + .dfi_9_rst_n(dfi_9_rst_n), // input wire dfi_9_rst_n + .dfi_9_init_start(dfi_9_init_start), // input wire dfi_9_init_start + .dfi_9_aw_ck_p0(dfi_9_aw_ck_p0), // input wire [1 : 0] dfi_9_aw_ck_p0 + .dfi_9_aw_cke_p0(dfi_9_aw_cke_p0), // input wire [1 : 0] dfi_9_aw_cke_p0 + .dfi_9_aw_row_p0(dfi_9_aw_row_p0), // input wire [11 : 0] dfi_9_aw_row_p0 + .dfi_9_aw_col_p0(dfi_9_aw_col_p0), // input wire [15 : 0] dfi_9_aw_col_p0 + .dfi_9_dw_wrdata_p0(dfi_9_dw_wrdata_p0), // input wire [255 : 0] dfi_9_dw_wrdata_p0 + .dfi_9_dw_wrdata_mask_p0(dfi_9_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_9_dw_wrdata_mask_p0 + .dfi_9_dw_wrdata_dbi_p0(dfi_9_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_9_dw_wrdata_dbi_p0 + .dfi_9_dw_wrdata_par_p0(dfi_9_dw_wrdata_par_p0), // input wire [7 : 0] dfi_9_dw_wrdata_par_p0 + .dfi_9_dw_wrdata_dq_en_p0(dfi_9_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_9_dw_wrdata_dq_en_p0 + .dfi_9_dw_wrdata_par_en_p0(dfi_9_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_9_dw_wrdata_par_en_p0 + .dfi_9_aw_ck_p1(dfi_9_aw_ck_p1), // input wire [1 : 0] dfi_9_aw_ck_p1 + .dfi_9_aw_cke_p1(dfi_9_aw_cke_p1), // input wire [1 : 0] dfi_9_aw_cke_p1 + .dfi_9_aw_row_p1(dfi_9_aw_row_p1), // input wire [11 : 0] dfi_9_aw_row_p1 + .dfi_9_aw_col_p1(dfi_9_aw_col_p1), // input wire [15 : 0] dfi_9_aw_col_p1 + .dfi_9_dw_wrdata_p1(dfi_9_dw_wrdata_p1), // input wire [255 : 0] dfi_9_dw_wrdata_p1 + .dfi_9_dw_wrdata_mask_p1(dfi_9_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_9_dw_wrdata_mask_p1 + .dfi_9_dw_wrdata_dbi_p1(dfi_9_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_9_dw_wrdata_dbi_p1 + .dfi_9_dw_wrdata_par_p1(dfi_9_dw_wrdata_par_p1), // input wire [7 : 0] dfi_9_dw_wrdata_par_p1 + .dfi_9_dw_wrdata_dq_en_p1(dfi_9_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_9_dw_wrdata_dq_en_p1 + .dfi_9_dw_wrdata_par_en_p1(dfi_9_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_9_dw_wrdata_par_en_p1 + .dfi_9_aw_ck_dis(dfi_9_aw_ck_dis), // input wire dfi_9_aw_ck_dis + .dfi_9_lp_pwr_e_req(dfi_9_lp_pwr_e_req), // input wire dfi_9_lp_pwr_e_req + .dfi_9_lp_sr_e_req(dfi_9_lp_sr_e_req), // input wire dfi_9_lp_sr_e_req + .dfi_9_lp_pwr_x_req(dfi_9_lp_pwr_x_req), // input wire dfi_9_lp_pwr_x_req + .dfi_9_aw_tx_indx_ld(dfi_9_aw_tx_indx_ld), // input wire dfi_9_aw_tx_indx_ld + .dfi_9_dw_tx_indx_ld(dfi_9_dw_tx_indx_ld), // input wire dfi_9_dw_tx_indx_ld + .dfi_9_dw_rx_indx_ld(dfi_9_dw_rx_indx_ld), // input wire dfi_9_dw_rx_indx_ld + .dfi_9_ctrlupd_ack(dfi_9_ctrlupd_ack), // input wire dfi_9_ctrlupd_ack + .dfi_9_phyupd_req(dfi_9_phyupd_req), // input wire dfi_9_phyupd_req + .dfi_9_dw_wrdata_dqs_p0(dfi_9_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_9_dw_wrdata_dqs_p0 + .dfi_9_dw_wrdata_dqs_p1(dfi_9_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_9_dw_wrdata_dqs_p1 + .dfi_10_clk(dfi_10_clk), // input wire dfi_10_clk + .dfi_10_rst_n(dfi_10_rst_n), // input wire dfi_10_rst_n + .dfi_10_init_start(dfi_10_init_start), // input wire dfi_10_init_start + .dfi_10_aw_ck_p0(dfi_10_aw_ck_p0), // input wire [1 : 0] dfi_10_aw_ck_p0 + .dfi_10_aw_cke_p0(dfi_10_aw_cke_p0), // input wire [1 : 0] dfi_10_aw_cke_p0 + .dfi_10_aw_row_p0(dfi_10_aw_row_p0), // input wire [11 : 0] dfi_10_aw_row_p0 + .dfi_10_aw_col_p0(dfi_10_aw_col_p0), // input wire [15 : 0] dfi_10_aw_col_p0 + .dfi_10_dw_wrdata_p0(dfi_10_dw_wrdata_p0), // input wire [255 : 0] dfi_10_dw_wrdata_p0 + .dfi_10_dw_wrdata_mask_p0(dfi_10_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_10_dw_wrdata_mask_p0 + .dfi_10_dw_wrdata_dbi_p0(dfi_10_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_10_dw_wrdata_dbi_p0 + .dfi_10_dw_wrdata_par_p0(dfi_10_dw_wrdata_par_p0), // input wire [7 : 0] dfi_10_dw_wrdata_par_p0 + .dfi_10_dw_wrdata_dq_en_p0(dfi_10_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_10_dw_wrdata_dq_en_p0 + .dfi_10_dw_wrdata_par_en_p0(dfi_10_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_10_dw_wrdata_par_en_p0 + .dfi_10_aw_ck_p1(dfi_10_aw_ck_p1), // input wire [1 : 0] dfi_10_aw_ck_p1 + .dfi_10_aw_cke_p1(dfi_10_aw_cke_p1), // input wire [1 : 0] dfi_10_aw_cke_p1 + .dfi_10_aw_row_p1(dfi_10_aw_row_p1), // input wire [11 : 0] dfi_10_aw_row_p1 + .dfi_10_aw_col_p1(dfi_10_aw_col_p1), // input wire [15 : 0] dfi_10_aw_col_p1 + .dfi_10_dw_wrdata_p1(dfi_10_dw_wrdata_p1), // input wire [255 : 0] dfi_10_dw_wrdata_p1 + .dfi_10_dw_wrdata_mask_p1(dfi_10_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_10_dw_wrdata_mask_p1 + .dfi_10_dw_wrdata_dbi_p1(dfi_10_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_10_dw_wrdata_dbi_p1 + .dfi_10_dw_wrdata_par_p1(dfi_10_dw_wrdata_par_p1), // input wire [7 : 0] dfi_10_dw_wrdata_par_p1 + .dfi_10_dw_wrdata_dq_en_p1(dfi_10_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_10_dw_wrdata_dq_en_p1 + .dfi_10_dw_wrdata_par_en_p1(dfi_10_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_10_dw_wrdata_par_en_p1 + .dfi_10_aw_ck_dis(dfi_10_aw_ck_dis), // input wire dfi_10_aw_ck_dis + .dfi_10_lp_pwr_e_req(dfi_10_lp_pwr_e_req), // input wire dfi_10_lp_pwr_e_req + .dfi_10_lp_sr_e_req(dfi_10_lp_sr_e_req), // input wire dfi_10_lp_sr_e_req + .dfi_10_lp_pwr_x_req(dfi_10_lp_pwr_x_req), // input wire dfi_10_lp_pwr_x_req + .dfi_10_aw_tx_indx_ld(dfi_10_aw_tx_indx_ld), // input wire dfi_10_aw_tx_indx_ld + .dfi_10_dw_tx_indx_ld(dfi_10_dw_tx_indx_ld), // input wire dfi_10_dw_tx_indx_ld + .dfi_10_dw_rx_indx_ld(dfi_10_dw_rx_indx_ld), // input wire dfi_10_dw_rx_indx_ld + .dfi_10_ctrlupd_ack(dfi_10_ctrlupd_ack), // input wire dfi_10_ctrlupd_ack + .dfi_10_phyupd_req(dfi_10_phyupd_req), // input wire dfi_10_phyupd_req + .dfi_10_dw_wrdata_dqs_p0(dfi_10_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_10_dw_wrdata_dqs_p0 + .dfi_10_dw_wrdata_dqs_p1(dfi_10_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_10_dw_wrdata_dqs_p1 + .dfi_11_clk(dfi_11_clk), // input wire dfi_11_clk + .dfi_11_rst_n(dfi_11_rst_n), // input wire dfi_11_rst_n + .dfi_11_init_start(dfi_11_init_start), // input wire dfi_11_init_start + .dfi_11_aw_ck_p0(dfi_11_aw_ck_p0), // input wire [1 : 0] dfi_11_aw_ck_p0 + .dfi_11_aw_cke_p0(dfi_11_aw_cke_p0), // input wire [1 : 0] dfi_11_aw_cke_p0 + .dfi_11_aw_row_p0(dfi_11_aw_row_p0), // input wire [11 : 0] dfi_11_aw_row_p0 + .dfi_11_aw_col_p0(dfi_11_aw_col_p0), // input wire [15 : 0] dfi_11_aw_col_p0 + .dfi_11_dw_wrdata_p0(dfi_11_dw_wrdata_p0), // input wire [255 : 0] dfi_11_dw_wrdata_p0 + .dfi_11_dw_wrdata_mask_p0(dfi_11_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_11_dw_wrdata_mask_p0 + .dfi_11_dw_wrdata_dbi_p0(dfi_11_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_11_dw_wrdata_dbi_p0 + .dfi_11_dw_wrdata_par_p0(dfi_11_dw_wrdata_par_p0), // input wire [7 : 0] dfi_11_dw_wrdata_par_p0 + .dfi_11_dw_wrdata_dq_en_p0(dfi_11_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_11_dw_wrdata_dq_en_p0 + .dfi_11_dw_wrdata_par_en_p0(dfi_11_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_11_dw_wrdata_par_en_p0 + .dfi_11_aw_ck_p1(dfi_11_aw_ck_p1), // input wire [1 : 0] dfi_11_aw_ck_p1 + .dfi_11_aw_cke_p1(dfi_11_aw_cke_p1), // input wire [1 : 0] dfi_11_aw_cke_p1 + .dfi_11_aw_row_p1(dfi_11_aw_row_p1), // input wire [11 : 0] dfi_11_aw_row_p1 + .dfi_11_aw_col_p1(dfi_11_aw_col_p1), // input wire [15 : 0] dfi_11_aw_col_p1 + .dfi_11_dw_wrdata_p1(dfi_11_dw_wrdata_p1), // input wire [255 : 0] dfi_11_dw_wrdata_p1 + .dfi_11_dw_wrdata_mask_p1(dfi_11_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_11_dw_wrdata_mask_p1 + .dfi_11_dw_wrdata_dbi_p1(dfi_11_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_11_dw_wrdata_dbi_p1 + .dfi_11_dw_wrdata_par_p1(dfi_11_dw_wrdata_par_p1), // input wire [7 : 0] dfi_11_dw_wrdata_par_p1 + .dfi_11_dw_wrdata_dq_en_p1(dfi_11_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_11_dw_wrdata_dq_en_p1 + .dfi_11_dw_wrdata_par_en_p1(dfi_11_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_11_dw_wrdata_par_en_p1 + .dfi_11_aw_ck_dis(dfi_11_aw_ck_dis), // input wire dfi_11_aw_ck_dis + .dfi_11_lp_pwr_e_req(dfi_11_lp_pwr_e_req), // input wire dfi_11_lp_pwr_e_req + .dfi_11_lp_sr_e_req(dfi_11_lp_sr_e_req), // input wire dfi_11_lp_sr_e_req + .dfi_11_lp_pwr_x_req(dfi_11_lp_pwr_x_req), // input wire dfi_11_lp_pwr_x_req + .dfi_11_aw_tx_indx_ld(dfi_11_aw_tx_indx_ld), // input wire dfi_11_aw_tx_indx_ld + .dfi_11_dw_tx_indx_ld(dfi_11_dw_tx_indx_ld), // input wire dfi_11_dw_tx_indx_ld + .dfi_11_dw_rx_indx_ld(dfi_11_dw_rx_indx_ld), // input wire dfi_11_dw_rx_indx_ld + .dfi_11_ctrlupd_ack(dfi_11_ctrlupd_ack), // input wire dfi_11_ctrlupd_ack + .dfi_11_phyupd_req(dfi_11_phyupd_req), // input wire dfi_11_phyupd_req + .dfi_11_dw_wrdata_dqs_p0(dfi_11_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_11_dw_wrdata_dqs_p0 + .dfi_11_dw_wrdata_dqs_p1(dfi_11_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_11_dw_wrdata_dqs_p1 + .dfi_12_clk(dfi_12_clk), // input wire dfi_12_clk + .dfi_12_rst_n(dfi_12_rst_n), // input wire dfi_12_rst_n + .dfi_12_init_start(dfi_12_init_start), // input wire dfi_12_init_start + .dfi_12_aw_ck_p0(dfi_12_aw_ck_p0), // input wire [1 : 0] dfi_12_aw_ck_p0 + .dfi_12_aw_cke_p0(dfi_12_aw_cke_p0), // input wire [1 : 0] dfi_12_aw_cke_p0 + .dfi_12_aw_row_p0(dfi_12_aw_row_p0), // input wire [11 : 0] dfi_12_aw_row_p0 + .dfi_12_aw_col_p0(dfi_12_aw_col_p0), // input wire [15 : 0] dfi_12_aw_col_p0 + .dfi_12_dw_wrdata_p0(dfi_12_dw_wrdata_p0), // input wire [255 : 0] dfi_12_dw_wrdata_p0 + .dfi_12_dw_wrdata_mask_p0(dfi_12_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_12_dw_wrdata_mask_p0 + .dfi_12_dw_wrdata_dbi_p0(dfi_12_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_12_dw_wrdata_dbi_p0 + .dfi_12_dw_wrdata_par_p0(dfi_12_dw_wrdata_par_p0), // input wire [7 : 0] dfi_12_dw_wrdata_par_p0 + .dfi_12_dw_wrdata_dq_en_p0(dfi_12_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_12_dw_wrdata_dq_en_p0 + .dfi_12_dw_wrdata_par_en_p0(dfi_12_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_12_dw_wrdata_par_en_p0 + .dfi_12_aw_ck_p1(dfi_12_aw_ck_p1), // input wire [1 : 0] dfi_12_aw_ck_p1 + .dfi_12_aw_cke_p1(dfi_12_aw_cke_p1), // input wire [1 : 0] dfi_12_aw_cke_p1 + .dfi_12_aw_row_p1(dfi_12_aw_row_p1), // input wire [11 : 0] dfi_12_aw_row_p1 + .dfi_12_aw_col_p1(dfi_12_aw_col_p1), // input wire [15 : 0] dfi_12_aw_col_p1 + .dfi_12_dw_wrdata_p1(dfi_12_dw_wrdata_p1), // input wire [255 : 0] dfi_12_dw_wrdata_p1 + .dfi_12_dw_wrdata_mask_p1(dfi_12_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_12_dw_wrdata_mask_p1 + .dfi_12_dw_wrdata_dbi_p1(dfi_12_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_12_dw_wrdata_dbi_p1 + .dfi_12_dw_wrdata_par_p1(dfi_12_dw_wrdata_par_p1), // input wire [7 : 0] dfi_12_dw_wrdata_par_p1 + .dfi_12_dw_wrdata_dq_en_p1(dfi_12_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_12_dw_wrdata_dq_en_p1 + .dfi_12_dw_wrdata_par_en_p1(dfi_12_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_12_dw_wrdata_par_en_p1 + .dfi_12_aw_ck_dis(dfi_12_aw_ck_dis), // input wire dfi_12_aw_ck_dis + .dfi_12_lp_pwr_e_req(dfi_12_lp_pwr_e_req), // input wire dfi_12_lp_pwr_e_req + .dfi_12_lp_sr_e_req(dfi_12_lp_sr_e_req), // input wire dfi_12_lp_sr_e_req + .dfi_12_lp_pwr_x_req(dfi_12_lp_pwr_x_req), // input wire dfi_12_lp_pwr_x_req + .dfi_12_aw_tx_indx_ld(dfi_12_aw_tx_indx_ld), // input wire dfi_12_aw_tx_indx_ld + .dfi_12_dw_tx_indx_ld(dfi_12_dw_tx_indx_ld), // input wire dfi_12_dw_tx_indx_ld + .dfi_12_dw_rx_indx_ld(dfi_12_dw_rx_indx_ld), // input wire dfi_12_dw_rx_indx_ld + .dfi_12_ctrlupd_ack(dfi_12_ctrlupd_ack), // input wire dfi_12_ctrlupd_ack + .dfi_12_phyupd_req(dfi_12_phyupd_req), // input wire dfi_12_phyupd_req + .dfi_12_dw_wrdata_dqs_p0(dfi_12_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_12_dw_wrdata_dqs_p0 + .dfi_12_dw_wrdata_dqs_p1(dfi_12_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_12_dw_wrdata_dqs_p1 + .dfi_13_clk(dfi_13_clk), // input wire dfi_13_clk + .dfi_13_rst_n(dfi_13_rst_n), // input wire dfi_13_rst_n + .dfi_13_init_start(dfi_13_init_start), // input wire dfi_13_init_start + .dfi_13_aw_ck_p0(dfi_13_aw_ck_p0), // input wire [1 : 0] dfi_13_aw_ck_p0 + .dfi_13_aw_cke_p0(dfi_13_aw_cke_p0), // input wire [1 : 0] dfi_13_aw_cke_p0 + .dfi_13_aw_row_p0(dfi_13_aw_row_p0), // input wire [11 : 0] dfi_13_aw_row_p0 + .dfi_13_aw_col_p0(dfi_13_aw_col_p0), // input wire [15 : 0] dfi_13_aw_col_p0 + .dfi_13_dw_wrdata_p0(dfi_13_dw_wrdata_p0), // input wire [255 : 0] dfi_13_dw_wrdata_p0 + .dfi_13_dw_wrdata_mask_p0(dfi_13_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_13_dw_wrdata_mask_p0 + .dfi_13_dw_wrdata_dbi_p0(dfi_13_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_13_dw_wrdata_dbi_p0 + .dfi_13_dw_wrdata_par_p0(dfi_13_dw_wrdata_par_p0), // input wire [7 : 0] dfi_13_dw_wrdata_par_p0 + .dfi_13_dw_wrdata_dq_en_p0(dfi_13_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_13_dw_wrdata_dq_en_p0 + .dfi_13_dw_wrdata_par_en_p0(dfi_13_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_13_dw_wrdata_par_en_p0 + .dfi_13_aw_ck_p1(dfi_13_aw_ck_p1), // input wire [1 : 0] dfi_13_aw_ck_p1 + .dfi_13_aw_cke_p1(dfi_13_aw_cke_p1), // input wire [1 : 0] dfi_13_aw_cke_p1 + .dfi_13_aw_row_p1(dfi_13_aw_row_p1), // input wire [11 : 0] dfi_13_aw_row_p1 + .dfi_13_aw_col_p1(dfi_13_aw_col_p1), // input wire [15 : 0] dfi_13_aw_col_p1 + .dfi_13_dw_wrdata_p1(dfi_13_dw_wrdata_p1), // input wire [255 : 0] dfi_13_dw_wrdata_p1 + .dfi_13_dw_wrdata_mask_p1(dfi_13_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_13_dw_wrdata_mask_p1 + .dfi_13_dw_wrdata_dbi_p1(dfi_13_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_13_dw_wrdata_dbi_p1 + .dfi_13_dw_wrdata_par_p1(dfi_13_dw_wrdata_par_p1), // input wire [7 : 0] dfi_13_dw_wrdata_par_p1 + .dfi_13_dw_wrdata_dq_en_p1(dfi_13_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_13_dw_wrdata_dq_en_p1 + .dfi_13_dw_wrdata_par_en_p1(dfi_13_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_13_dw_wrdata_par_en_p1 + .dfi_13_aw_ck_dis(dfi_13_aw_ck_dis), // input wire dfi_13_aw_ck_dis + .dfi_13_lp_pwr_e_req(dfi_13_lp_pwr_e_req), // input wire dfi_13_lp_pwr_e_req + .dfi_13_lp_sr_e_req(dfi_13_lp_sr_e_req), // input wire dfi_13_lp_sr_e_req + .dfi_13_lp_pwr_x_req(dfi_13_lp_pwr_x_req), // input wire dfi_13_lp_pwr_x_req + .dfi_13_aw_tx_indx_ld(dfi_13_aw_tx_indx_ld), // input wire dfi_13_aw_tx_indx_ld + .dfi_13_dw_tx_indx_ld(dfi_13_dw_tx_indx_ld), // input wire dfi_13_dw_tx_indx_ld + .dfi_13_dw_rx_indx_ld(dfi_13_dw_rx_indx_ld), // input wire dfi_13_dw_rx_indx_ld + .dfi_13_ctrlupd_ack(dfi_13_ctrlupd_ack), // input wire dfi_13_ctrlupd_ack + .dfi_13_phyupd_req(dfi_13_phyupd_req), // input wire dfi_13_phyupd_req + .dfi_13_dw_wrdata_dqs_p0(dfi_13_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_13_dw_wrdata_dqs_p0 + .dfi_13_dw_wrdata_dqs_p1(dfi_13_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_13_dw_wrdata_dqs_p1 + .dfi_14_clk(dfi_14_clk), // input wire dfi_14_clk + .dfi_14_rst_n(dfi_14_rst_n), // input wire dfi_14_rst_n + .dfi_14_init_start(dfi_14_init_start), // input wire dfi_14_init_start + .dfi_14_aw_ck_p0(dfi_14_aw_ck_p0), // input wire [1 : 0] dfi_14_aw_ck_p0 + .dfi_14_aw_cke_p0(dfi_14_aw_cke_p0), // input wire [1 : 0] dfi_14_aw_cke_p0 + .dfi_14_aw_row_p0(dfi_14_aw_row_p0), // input wire [11 : 0] dfi_14_aw_row_p0 + .dfi_14_aw_col_p0(dfi_14_aw_col_p0), // input wire [15 : 0] dfi_14_aw_col_p0 + .dfi_14_dw_wrdata_p0(dfi_14_dw_wrdata_p0), // input wire [255 : 0] dfi_14_dw_wrdata_p0 + .dfi_14_dw_wrdata_mask_p0(dfi_14_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_14_dw_wrdata_mask_p0 + .dfi_14_dw_wrdata_dbi_p0(dfi_14_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_14_dw_wrdata_dbi_p0 + .dfi_14_dw_wrdata_par_p0(dfi_14_dw_wrdata_par_p0), // input wire [7 : 0] dfi_14_dw_wrdata_par_p0 + .dfi_14_dw_wrdata_dq_en_p0(dfi_14_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_14_dw_wrdata_dq_en_p0 + .dfi_14_dw_wrdata_par_en_p0(dfi_14_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_14_dw_wrdata_par_en_p0 + .dfi_14_aw_ck_p1(dfi_14_aw_ck_p1), // input wire [1 : 0] dfi_14_aw_ck_p1 + .dfi_14_aw_cke_p1(dfi_14_aw_cke_p1), // input wire [1 : 0] dfi_14_aw_cke_p1 + .dfi_14_aw_row_p1(dfi_14_aw_row_p1), // input wire [11 : 0] dfi_14_aw_row_p1 + .dfi_14_aw_col_p1(dfi_14_aw_col_p1), // input wire [15 : 0] dfi_14_aw_col_p1 + .dfi_14_dw_wrdata_p1(dfi_14_dw_wrdata_p1), // input wire [255 : 0] dfi_14_dw_wrdata_p1 + .dfi_14_dw_wrdata_mask_p1(dfi_14_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_14_dw_wrdata_mask_p1 + .dfi_14_dw_wrdata_dbi_p1(dfi_14_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_14_dw_wrdata_dbi_p1 + .dfi_14_dw_wrdata_par_p1(dfi_14_dw_wrdata_par_p1), // input wire [7 : 0] dfi_14_dw_wrdata_par_p1 + .dfi_14_dw_wrdata_dq_en_p1(dfi_14_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_14_dw_wrdata_dq_en_p1 + .dfi_14_dw_wrdata_par_en_p1(dfi_14_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_14_dw_wrdata_par_en_p1 + .dfi_14_aw_ck_dis(dfi_14_aw_ck_dis), // input wire dfi_14_aw_ck_dis + .dfi_14_lp_pwr_e_req(dfi_14_lp_pwr_e_req), // input wire dfi_14_lp_pwr_e_req + .dfi_14_lp_sr_e_req(dfi_14_lp_sr_e_req), // input wire dfi_14_lp_sr_e_req + .dfi_14_lp_pwr_x_req(dfi_14_lp_pwr_x_req), // input wire dfi_14_lp_pwr_x_req + .dfi_14_aw_tx_indx_ld(dfi_14_aw_tx_indx_ld), // input wire dfi_14_aw_tx_indx_ld + .dfi_14_dw_tx_indx_ld(dfi_14_dw_tx_indx_ld), // input wire dfi_14_dw_tx_indx_ld + .dfi_14_dw_rx_indx_ld(dfi_14_dw_rx_indx_ld), // input wire dfi_14_dw_rx_indx_ld + .dfi_14_ctrlupd_ack(dfi_14_ctrlupd_ack), // input wire dfi_14_ctrlupd_ack + .dfi_14_phyupd_req(dfi_14_phyupd_req), // input wire dfi_14_phyupd_req + .dfi_14_dw_wrdata_dqs_p0(dfi_14_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_14_dw_wrdata_dqs_p0 + .dfi_14_dw_wrdata_dqs_p1(dfi_14_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_14_dw_wrdata_dqs_p1 + .dfi_15_clk(dfi_15_clk), // input wire dfi_15_clk + .dfi_15_rst_n(dfi_15_rst_n), // input wire dfi_15_rst_n + .dfi_15_init_start(dfi_15_init_start), // input wire dfi_15_init_start + .dfi_15_aw_ck_p0(dfi_15_aw_ck_p0), // input wire [1 : 0] dfi_15_aw_ck_p0 + .dfi_15_aw_cke_p0(dfi_15_aw_cke_p0), // input wire [1 : 0] dfi_15_aw_cke_p0 + .dfi_15_aw_row_p0(dfi_15_aw_row_p0), // input wire [11 : 0] dfi_15_aw_row_p0 + .dfi_15_aw_col_p0(dfi_15_aw_col_p0), // input wire [15 : 0] dfi_15_aw_col_p0 + .dfi_15_dw_wrdata_p0(dfi_15_dw_wrdata_p0), // input wire [255 : 0] dfi_15_dw_wrdata_p0 + .dfi_15_dw_wrdata_mask_p0(dfi_15_dw_wrdata_mask_p0), // input wire [31 : 0] dfi_15_dw_wrdata_mask_p0 + .dfi_15_dw_wrdata_dbi_p0(dfi_15_dw_wrdata_dbi_p0), // input wire [31 : 0] dfi_15_dw_wrdata_dbi_p0 + .dfi_15_dw_wrdata_par_p0(dfi_15_dw_wrdata_par_p0), // input wire [7 : 0] dfi_15_dw_wrdata_par_p0 + .dfi_15_dw_wrdata_dq_en_p0(dfi_15_dw_wrdata_dq_en_p0), // input wire [7 : 0] dfi_15_dw_wrdata_dq_en_p0 + .dfi_15_dw_wrdata_par_en_p0(dfi_15_dw_wrdata_par_en_p0), // input wire [7 : 0] dfi_15_dw_wrdata_par_en_p0 + .dfi_15_aw_ck_p1(dfi_15_aw_ck_p1), // input wire [1 : 0] dfi_15_aw_ck_p1 + .dfi_15_aw_cke_p1(dfi_15_aw_cke_p1), // input wire [1 : 0] dfi_15_aw_cke_p1 + .dfi_15_aw_row_p1(dfi_15_aw_row_p1), // input wire [11 : 0] dfi_15_aw_row_p1 + .dfi_15_aw_col_p1(dfi_15_aw_col_p1), // input wire [15 : 0] dfi_15_aw_col_p1 + .dfi_15_dw_wrdata_p1(dfi_15_dw_wrdata_p1), // input wire [255 : 0] dfi_15_dw_wrdata_p1 + .dfi_15_dw_wrdata_mask_p1(dfi_15_dw_wrdata_mask_p1), // input wire [31 : 0] dfi_15_dw_wrdata_mask_p1 + .dfi_15_dw_wrdata_dbi_p1(dfi_15_dw_wrdata_dbi_p1), // input wire [31 : 0] dfi_15_dw_wrdata_dbi_p1 + .dfi_15_dw_wrdata_par_p1(dfi_15_dw_wrdata_par_p1), // input wire [7 : 0] dfi_15_dw_wrdata_par_p1 + .dfi_15_dw_wrdata_dq_en_p1(dfi_15_dw_wrdata_dq_en_p1), // input wire [7 : 0] dfi_15_dw_wrdata_dq_en_p1 + .dfi_15_dw_wrdata_par_en_p1(dfi_15_dw_wrdata_par_en_p1), // input wire [7 : 0] dfi_15_dw_wrdata_par_en_p1 + .dfi_15_aw_ck_dis(dfi_15_aw_ck_dis), // input wire dfi_15_aw_ck_dis + .dfi_15_lp_pwr_e_req(dfi_15_lp_pwr_e_req), // input wire dfi_15_lp_pwr_e_req + .dfi_15_lp_sr_e_req(dfi_15_lp_sr_e_req), // input wire dfi_15_lp_sr_e_req + .dfi_15_lp_pwr_x_req(dfi_15_lp_pwr_x_req), // input wire dfi_15_lp_pwr_x_req + .dfi_15_aw_tx_indx_ld(dfi_15_aw_tx_indx_ld), // input wire dfi_15_aw_tx_indx_ld + .dfi_15_dw_tx_indx_ld(dfi_15_dw_tx_indx_ld), // input wire dfi_15_dw_tx_indx_ld + .dfi_15_dw_rx_indx_ld(dfi_15_dw_rx_indx_ld), // input wire dfi_15_dw_rx_indx_ld + .dfi_15_ctrlupd_ack(dfi_15_ctrlupd_ack), // input wire dfi_15_ctrlupd_ack + .dfi_15_phyupd_req(dfi_15_phyupd_req), // input wire dfi_15_phyupd_req + .dfi_15_dw_wrdata_dqs_p0(dfi_15_dw_wrdata_dqs_p0), // input wire [7 : 0] dfi_15_dw_wrdata_dqs_p0 + .dfi_15_dw_wrdata_dqs_p1(dfi_15_dw_wrdata_dqs_p1), // input wire [7 : 0] dfi_15_dw_wrdata_dqs_p1 + .APB_0_PCLK(APB_0_PCLK), // input wire APB_0_PCLK + .APB_0_PRESET_N(APB_0_PRESET_N), // input wire APB_0_PRESET_N + .APB_1_PCLK(APB_1_PCLK), // input wire APB_1_PCLK + .APB_1_PRESET_N(APB_1_PRESET_N), // input wire APB_1_PRESET_N + .dfi_0_dw_rddata_p0(dfi_0_dw_rddata_p0), // output wire [255 : 0] dfi_0_dw_rddata_p0 + .dfi_0_dw_rddata_dm_p0(dfi_0_dw_rddata_dm_p0), // output wire [31 : 0] dfi_0_dw_rddata_dm_p0 + .dfi_0_dw_rddata_dbi_p0(dfi_0_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_0_dw_rddata_dbi_p0 + .dfi_0_dw_rddata_par_p0(dfi_0_dw_rddata_par_p0), // output wire [7 : 0] dfi_0_dw_rddata_par_p0 + .dfi_0_dw_rddata_p1(dfi_0_dw_rddata_p1), // output wire [255 : 0] dfi_0_dw_rddata_p1 + .dfi_0_dw_rddata_dm_p1(dfi_0_dw_rddata_dm_p1), // output wire [31 : 0] dfi_0_dw_rddata_dm_p1 + .dfi_0_dw_rddata_dbi_p1(dfi_0_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_0_dw_rddata_dbi_p1 + .dfi_0_dw_rddata_par_p1(dfi_0_dw_rddata_par_p1), // output wire [7 : 0] dfi_0_dw_rddata_par_p1 + .dfi_0_dbi_byte_disable(dfi_0_dbi_byte_disable), // output wire [15 : 0] dfi_0_dbi_byte_disable + .dfi_0_dw_rddata_valid(dfi_0_dw_rddata_valid), // output wire [3 : 0] dfi_0_dw_rddata_valid + .dfi_0_dw_derr_n(dfi_0_dw_derr_n), // output wire [7 : 0] dfi_0_dw_derr_n + .dfi_0_aw_aerr_n(dfi_0_aw_aerr_n), // output wire [1 : 0] dfi_0_aw_aerr_n + .dfi_0_ctrlupd_req(dfi_0_ctrlupd_req), // output wire dfi_0_ctrlupd_req + .dfi_0_phyupd_ack(dfi_0_phyupd_ack), // output wire dfi_0_phyupd_ack + .dfi_0_clk_init(dfi_0_clk_init), // output wire dfi_0_clk_init + .dfi_0_init_complete(dfi_0_init_complete), // output wire dfi_0_init_complete + .dfi_0_out_rst_n(dfi_0_out_rst_n), // output wire dfi_0_out_rst_n + .dfi_1_dw_rddata_p0(dfi_1_dw_rddata_p0), // output wire [255 : 0] dfi_1_dw_rddata_p0 + .dfi_1_dw_rddata_dm_p0(dfi_1_dw_rddata_dm_p0), // output wire [31 : 0] dfi_1_dw_rddata_dm_p0 + .dfi_1_dw_rddata_dbi_p0(dfi_1_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_1_dw_rddata_dbi_p0 + .dfi_1_dw_rddata_par_p0(dfi_1_dw_rddata_par_p0), // output wire [7 : 0] dfi_1_dw_rddata_par_p0 + .dfi_1_dw_rddata_p1(dfi_1_dw_rddata_p1), // output wire [255 : 0] dfi_1_dw_rddata_p1 + .dfi_1_dw_rddata_dm_p1(dfi_1_dw_rddata_dm_p1), // output wire [31 : 0] dfi_1_dw_rddata_dm_p1 + .dfi_1_dw_rddata_dbi_p1(dfi_1_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_1_dw_rddata_dbi_p1 + .dfi_1_dw_rddata_par_p1(dfi_1_dw_rddata_par_p1), // output wire [7 : 0] dfi_1_dw_rddata_par_p1 + .dfi_1_dbi_byte_disable(dfi_1_dbi_byte_disable), // output wire [15 : 0] dfi_1_dbi_byte_disable + .dfi_1_dw_rddata_valid(dfi_1_dw_rddata_valid), // output wire [3 : 0] dfi_1_dw_rddata_valid + .dfi_1_dw_derr_n(dfi_1_dw_derr_n), // output wire [7 : 0] dfi_1_dw_derr_n + .dfi_1_aw_aerr_n(dfi_1_aw_aerr_n), // output wire [1 : 0] dfi_1_aw_aerr_n + .dfi_1_ctrlupd_req(dfi_1_ctrlupd_req), // output wire dfi_1_ctrlupd_req + .dfi_1_phyupd_ack(dfi_1_phyupd_ack), // output wire dfi_1_phyupd_ack + .dfi_1_clk_init(dfi_1_clk_init), // output wire dfi_1_clk_init + .dfi_1_init_complete(dfi_1_init_complete), // output wire dfi_1_init_complete + .dfi_1_out_rst_n(dfi_1_out_rst_n), // output wire dfi_1_out_rst_n + .dfi_2_dw_rddata_p0(dfi_2_dw_rddata_p0), // output wire [255 : 0] dfi_2_dw_rddata_p0 + .dfi_2_dw_rddata_dm_p0(dfi_2_dw_rddata_dm_p0), // output wire [31 : 0] dfi_2_dw_rddata_dm_p0 + .dfi_2_dw_rddata_dbi_p0(dfi_2_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_2_dw_rddata_dbi_p0 + .dfi_2_dw_rddata_par_p0(dfi_2_dw_rddata_par_p0), // output wire [7 : 0] dfi_2_dw_rddata_par_p0 + .dfi_2_dw_rddata_p1(dfi_2_dw_rddata_p1), // output wire [255 : 0] dfi_2_dw_rddata_p1 + .dfi_2_dw_rddata_dm_p1(dfi_2_dw_rddata_dm_p1), // output wire [31 : 0] dfi_2_dw_rddata_dm_p1 + .dfi_2_dw_rddata_dbi_p1(dfi_2_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_2_dw_rddata_dbi_p1 + .dfi_2_dw_rddata_par_p1(dfi_2_dw_rddata_par_p1), // output wire [7 : 0] dfi_2_dw_rddata_par_p1 + .dfi_2_dbi_byte_disable(dfi_2_dbi_byte_disable), // output wire [15 : 0] dfi_2_dbi_byte_disable + .dfi_2_dw_rddata_valid(dfi_2_dw_rddata_valid), // output wire [3 : 0] dfi_2_dw_rddata_valid + .dfi_2_dw_derr_n(dfi_2_dw_derr_n), // output wire [7 : 0] dfi_2_dw_derr_n + .dfi_2_aw_aerr_n(dfi_2_aw_aerr_n), // output wire [1 : 0] dfi_2_aw_aerr_n + .dfi_2_ctrlupd_req(dfi_2_ctrlupd_req), // output wire dfi_2_ctrlupd_req + .dfi_2_phyupd_ack(dfi_2_phyupd_ack), // output wire dfi_2_phyupd_ack + .dfi_2_clk_init(dfi_2_clk_init), // output wire dfi_2_clk_init + .dfi_2_init_complete(dfi_2_init_complete), // output wire dfi_2_init_complete + .dfi_2_out_rst_n(dfi_2_out_rst_n), // output wire dfi_2_out_rst_n + .dfi_3_dw_rddata_p0(dfi_3_dw_rddata_p0), // output wire [255 : 0] dfi_3_dw_rddata_p0 + .dfi_3_dw_rddata_dm_p0(dfi_3_dw_rddata_dm_p0), // output wire [31 : 0] dfi_3_dw_rddata_dm_p0 + .dfi_3_dw_rddata_dbi_p0(dfi_3_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_3_dw_rddata_dbi_p0 + .dfi_3_dw_rddata_par_p0(dfi_3_dw_rddata_par_p0), // output wire [7 : 0] dfi_3_dw_rddata_par_p0 + .dfi_3_dw_rddata_p1(dfi_3_dw_rddata_p1), // output wire [255 : 0] dfi_3_dw_rddata_p1 + .dfi_3_dw_rddata_dm_p1(dfi_3_dw_rddata_dm_p1), // output wire [31 : 0] dfi_3_dw_rddata_dm_p1 + .dfi_3_dw_rddata_dbi_p1(dfi_3_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_3_dw_rddata_dbi_p1 + .dfi_3_dw_rddata_par_p1(dfi_3_dw_rddata_par_p1), // output wire [7 : 0] dfi_3_dw_rddata_par_p1 + .dfi_3_dbi_byte_disable(dfi_3_dbi_byte_disable), // output wire [15 : 0] dfi_3_dbi_byte_disable + .dfi_3_dw_rddata_valid(dfi_3_dw_rddata_valid), // output wire [3 : 0] dfi_3_dw_rddata_valid + .dfi_3_dw_derr_n(dfi_3_dw_derr_n), // output wire [7 : 0] dfi_3_dw_derr_n + .dfi_3_aw_aerr_n(dfi_3_aw_aerr_n), // output wire [1 : 0] dfi_3_aw_aerr_n + .dfi_3_ctrlupd_req(dfi_3_ctrlupd_req), // output wire dfi_3_ctrlupd_req + .dfi_3_phyupd_ack(dfi_3_phyupd_ack), // output wire dfi_3_phyupd_ack + .dfi_3_clk_init(dfi_3_clk_init), // output wire dfi_3_clk_init + .dfi_3_init_complete(dfi_3_init_complete), // output wire dfi_3_init_complete + .dfi_3_out_rst_n(dfi_3_out_rst_n), // output wire dfi_3_out_rst_n + .dfi_4_dw_rddata_p0(dfi_4_dw_rddata_p0), // output wire [255 : 0] dfi_4_dw_rddata_p0 + .dfi_4_dw_rddata_dm_p0(dfi_4_dw_rddata_dm_p0), // output wire [31 : 0] dfi_4_dw_rddata_dm_p0 + .dfi_4_dw_rddata_dbi_p0(dfi_4_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_4_dw_rddata_dbi_p0 + .dfi_4_dw_rddata_par_p0(dfi_4_dw_rddata_par_p0), // output wire [7 : 0] dfi_4_dw_rddata_par_p0 + .dfi_4_dw_rddata_p1(dfi_4_dw_rddata_p1), // output wire [255 : 0] dfi_4_dw_rddata_p1 + .dfi_4_dw_rddata_dm_p1(dfi_4_dw_rddata_dm_p1), // output wire [31 : 0] dfi_4_dw_rddata_dm_p1 + .dfi_4_dw_rddata_dbi_p1(dfi_4_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_4_dw_rddata_dbi_p1 + .dfi_4_dw_rddata_par_p1(dfi_4_dw_rddata_par_p1), // output wire [7 : 0] dfi_4_dw_rddata_par_p1 + .dfi_4_dbi_byte_disable(dfi_4_dbi_byte_disable), // output wire [15 : 0] dfi_4_dbi_byte_disable + .dfi_4_dw_rddata_valid(dfi_4_dw_rddata_valid), // output wire [3 : 0] dfi_4_dw_rddata_valid + .dfi_4_dw_derr_n(dfi_4_dw_derr_n), // output wire [7 : 0] dfi_4_dw_derr_n + .dfi_4_aw_aerr_n(dfi_4_aw_aerr_n), // output wire [1 : 0] dfi_4_aw_aerr_n + .dfi_4_ctrlupd_req(dfi_4_ctrlupd_req), // output wire dfi_4_ctrlupd_req + .dfi_4_phyupd_ack(dfi_4_phyupd_ack), // output wire dfi_4_phyupd_ack + .dfi_4_clk_init(dfi_4_clk_init), // output wire dfi_4_clk_init + .dfi_4_init_complete(dfi_4_init_complete), // output wire dfi_4_init_complete + .dfi_4_out_rst_n(dfi_4_out_rst_n), // output wire dfi_4_out_rst_n + .dfi_5_dw_rddata_p0(dfi_5_dw_rddata_p0), // output wire [255 : 0] dfi_5_dw_rddata_p0 + .dfi_5_dw_rddata_dm_p0(dfi_5_dw_rddata_dm_p0), // output wire [31 : 0] dfi_5_dw_rddata_dm_p0 + .dfi_5_dw_rddata_dbi_p0(dfi_5_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_5_dw_rddata_dbi_p0 + .dfi_5_dw_rddata_par_p0(dfi_5_dw_rddata_par_p0), // output wire [7 : 0] dfi_5_dw_rddata_par_p0 + .dfi_5_dw_rddata_p1(dfi_5_dw_rddata_p1), // output wire [255 : 0] dfi_5_dw_rddata_p1 + .dfi_5_dw_rddata_dm_p1(dfi_5_dw_rddata_dm_p1), // output wire [31 : 0] dfi_5_dw_rddata_dm_p1 + .dfi_5_dw_rddata_dbi_p1(dfi_5_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_5_dw_rddata_dbi_p1 + .dfi_5_dw_rddata_par_p1(dfi_5_dw_rddata_par_p1), // output wire [7 : 0] dfi_5_dw_rddata_par_p1 + .dfi_5_dbi_byte_disable(dfi_5_dbi_byte_disable), // output wire [15 : 0] dfi_5_dbi_byte_disable + .dfi_5_dw_rddata_valid(dfi_5_dw_rddata_valid), // output wire [3 : 0] dfi_5_dw_rddata_valid + .dfi_5_dw_derr_n(dfi_5_dw_derr_n), // output wire [7 : 0] dfi_5_dw_derr_n + .dfi_5_aw_aerr_n(dfi_5_aw_aerr_n), // output wire [1 : 0] dfi_5_aw_aerr_n + .dfi_5_ctrlupd_req(dfi_5_ctrlupd_req), // output wire dfi_5_ctrlupd_req + .dfi_5_phyupd_ack(dfi_5_phyupd_ack), // output wire dfi_5_phyupd_ack + .dfi_5_clk_init(dfi_5_clk_init), // output wire dfi_5_clk_init + .dfi_5_init_complete(dfi_5_init_complete), // output wire dfi_5_init_complete + .dfi_5_out_rst_n(dfi_5_out_rst_n), // output wire dfi_5_out_rst_n + .dfi_6_dw_rddata_p0(dfi_6_dw_rddata_p0), // output wire [255 : 0] dfi_6_dw_rddata_p0 + .dfi_6_dw_rddata_dm_p0(dfi_6_dw_rddata_dm_p0), // output wire [31 : 0] dfi_6_dw_rddata_dm_p0 + .dfi_6_dw_rddata_dbi_p0(dfi_6_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_6_dw_rddata_dbi_p0 + .dfi_6_dw_rddata_par_p0(dfi_6_dw_rddata_par_p0), // output wire [7 : 0] dfi_6_dw_rddata_par_p0 + .dfi_6_dw_rddata_p1(dfi_6_dw_rddata_p1), // output wire [255 : 0] dfi_6_dw_rddata_p1 + .dfi_6_dw_rddata_dm_p1(dfi_6_dw_rddata_dm_p1), // output wire [31 : 0] dfi_6_dw_rddata_dm_p1 + .dfi_6_dw_rddata_dbi_p1(dfi_6_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_6_dw_rddata_dbi_p1 + .dfi_6_dw_rddata_par_p1(dfi_6_dw_rddata_par_p1), // output wire [7 : 0] dfi_6_dw_rddata_par_p1 + .dfi_6_dbi_byte_disable(dfi_6_dbi_byte_disable), // output wire [15 : 0] dfi_6_dbi_byte_disable + .dfi_6_dw_rddata_valid(dfi_6_dw_rddata_valid), // output wire [3 : 0] dfi_6_dw_rddata_valid + .dfi_6_dw_derr_n(dfi_6_dw_derr_n), // output wire [7 : 0] dfi_6_dw_derr_n + .dfi_6_aw_aerr_n(dfi_6_aw_aerr_n), // output wire [1 : 0] dfi_6_aw_aerr_n + .dfi_6_ctrlupd_req(dfi_6_ctrlupd_req), // output wire dfi_6_ctrlupd_req + .dfi_6_phyupd_ack(dfi_6_phyupd_ack), // output wire dfi_6_phyupd_ack + .dfi_6_clk_init(dfi_6_clk_init), // output wire dfi_6_clk_init + .dfi_6_init_complete(dfi_6_init_complete), // output wire dfi_6_init_complete + .dfi_6_out_rst_n(dfi_6_out_rst_n), // output wire dfi_6_out_rst_n + .dfi_7_dw_rddata_p0(dfi_7_dw_rddata_p0), // output wire [255 : 0] dfi_7_dw_rddata_p0 + .dfi_7_dw_rddata_dm_p0(dfi_7_dw_rddata_dm_p0), // output wire [31 : 0] dfi_7_dw_rddata_dm_p0 + .dfi_7_dw_rddata_dbi_p0(dfi_7_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_7_dw_rddata_dbi_p0 + .dfi_7_dw_rddata_par_p0(dfi_7_dw_rddata_par_p0), // output wire [7 : 0] dfi_7_dw_rddata_par_p0 + .dfi_7_dw_rddata_p1(dfi_7_dw_rddata_p1), // output wire [255 : 0] dfi_7_dw_rddata_p1 + .dfi_7_dw_rddata_dm_p1(dfi_7_dw_rddata_dm_p1), // output wire [31 : 0] dfi_7_dw_rddata_dm_p1 + .dfi_7_dw_rddata_dbi_p1(dfi_7_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_7_dw_rddata_dbi_p1 + .dfi_7_dw_rddata_par_p1(dfi_7_dw_rddata_par_p1), // output wire [7 : 0] dfi_7_dw_rddata_par_p1 + .dfi_7_dbi_byte_disable(dfi_7_dbi_byte_disable), // output wire [15 : 0] dfi_7_dbi_byte_disable + .dfi_7_dw_rddata_valid(dfi_7_dw_rddata_valid), // output wire [3 : 0] dfi_7_dw_rddata_valid + .dfi_7_dw_derr_n(dfi_7_dw_derr_n), // output wire [7 : 0] dfi_7_dw_derr_n + .dfi_7_aw_aerr_n(dfi_7_aw_aerr_n), // output wire [1 : 0] dfi_7_aw_aerr_n + .dfi_7_ctrlupd_req(dfi_7_ctrlupd_req), // output wire dfi_7_ctrlupd_req + .dfi_7_phyupd_ack(dfi_7_phyupd_ack), // output wire dfi_7_phyupd_ack + .dfi_7_clk_init(dfi_7_clk_init), // output wire dfi_7_clk_init + .dfi_7_init_complete(dfi_7_init_complete), // output wire dfi_7_init_complete + .dfi_7_out_rst_n(dfi_7_out_rst_n), // output wire dfi_7_out_rst_n + .dfi_8_dw_rddata_p0(dfi_8_dw_rddata_p0), // output wire [255 : 0] dfi_8_dw_rddata_p0 + .dfi_8_dw_rddata_dm_p0(dfi_8_dw_rddata_dm_p0), // output wire [31 : 0] dfi_8_dw_rddata_dm_p0 + .dfi_8_dw_rddata_dbi_p0(dfi_8_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_8_dw_rddata_dbi_p0 + .dfi_8_dw_rddata_par_p0(dfi_8_dw_rddata_par_p0), // output wire [7 : 0] dfi_8_dw_rddata_par_p0 + .dfi_8_dw_rddata_p1(dfi_8_dw_rddata_p1), // output wire [255 : 0] dfi_8_dw_rddata_p1 + .dfi_8_dw_rddata_dm_p1(dfi_8_dw_rddata_dm_p1), // output wire [31 : 0] dfi_8_dw_rddata_dm_p1 + .dfi_8_dw_rddata_dbi_p1(dfi_8_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_8_dw_rddata_dbi_p1 + .dfi_8_dw_rddata_par_p1(dfi_8_dw_rddata_par_p1), // output wire [7 : 0] dfi_8_dw_rddata_par_p1 + .dfi_8_dbi_byte_disable(dfi_8_dbi_byte_disable), // output wire [15 : 0] dfi_8_dbi_byte_disable + .dfi_8_dw_rddata_valid(dfi_8_dw_rddata_valid), // output wire [3 : 0] dfi_8_dw_rddata_valid + .dfi_8_dw_derr_n(dfi_8_dw_derr_n), // output wire [7 : 0] dfi_8_dw_derr_n + .dfi_8_aw_aerr_n(dfi_8_aw_aerr_n), // output wire [1 : 0] dfi_8_aw_aerr_n + .dfi_8_ctrlupd_req(dfi_8_ctrlupd_req), // output wire dfi_8_ctrlupd_req + .dfi_8_phyupd_ack(dfi_8_phyupd_ack), // output wire dfi_8_phyupd_ack + .dfi_8_clk_init(dfi_8_clk_init), // output wire dfi_8_clk_init + .dfi_8_init_complete(dfi_8_init_complete), // output wire dfi_8_init_complete + .dfi_8_out_rst_n(dfi_8_out_rst_n), // output wire dfi_8_out_rst_n + .dfi_9_dw_rddata_p0(dfi_9_dw_rddata_p0), // output wire [255 : 0] dfi_9_dw_rddata_p0 + .dfi_9_dw_rddata_dm_p0(dfi_9_dw_rddata_dm_p0), // output wire [31 : 0] dfi_9_dw_rddata_dm_p0 + .dfi_9_dw_rddata_dbi_p0(dfi_9_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_9_dw_rddata_dbi_p0 + .dfi_9_dw_rddata_par_p0(dfi_9_dw_rddata_par_p0), // output wire [7 : 0] dfi_9_dw_rddata_par_p0 + .dfi_9_dw_rddata_p1(dfi_9_dw_rddata_p1), // output wire [255 : 0] dfi_9_dw_rddata_p1 + .dfi_9_dw_rddata_dm_p1(dfi_9_dw_rddata_dm_p1), // output wire [31 : 0] dfi_9_dw_rddata_dm_p1 + .dfi_9_dw_rddata_dbi_p1(dfi_9_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_9_dw_rddata_dbi_p1 + .dfi_9_dw_rddata_par_p1(dfi_9_dw_rddata_par_p1), // output wire [7 : 0] dfi_9_dw_rddata_par_p1 + .dfi_9_dbi_byte_disable(dfi_9_dbi_byte_disable), // output wire [15 : 0] dfi_9_dbi_byte_disable + .dfi_9_dw_rddata_valid(dfi_9_dw_rddata_valid), // output wire [3 : 0] dfi_9_dw_rddata_valid + .dfi_9_dw_derr_n(dfi_9_dw_derr_n), // output wire [7 : 0] dfi_9_dw_derr_n + .dfi_9_aw_aerr_n(dfi_9_aw_aerr_n), // output wire [1 : 0] dfi_9_aw_aerr_n + .dfi_9_ctrlupd_req(dfi_9_ctrlupd_req), // output wire dfi_9_ctrlupd_req + .dfi_9_phyupd_ack(dfi_9_phyupd_ack), // output wire dfi_9_phyupd_ack + .dfi_9_clk_init(dfi_9_clk_init), // output wire dfi_9_clk_init + .dfi_9_init_complete(dfi_9_init_complete), // output wire dfi_9_init_complete + .dfi_9_out_rst_n(dfi_9_out_rst_n), // output wire dfi_9_out_rst_n + .dfi_10_dw_rddata_p0(dfi_10_dw_rddata_p0), // output wire [255 : 0] dfi_10_dw_rddata_p0 + .dfi_10_dw_rddata_dm_p0(dfi_10_dw_rddata_dm_p0), // output wire [31 : 0] dfi_10_dw_rddata_dm_p0 + .dfi_10_dw_rddata_dbi_p0(dfi_10_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_10_dw_rddata_dbi_p0 + .dfi_10_dw_rddata_par_p0(dfi_10_dw_rddata_par_p0), // output wire [7 : 0] dfi_10_dw_rddata_par_p0 + .dfi_10_dw_rddata_p1(dfi_10_dw_rddata_p1), // output wire [255 : 0] dfi_10_dw_rddata_p1 + .dfi_10_dw_rddata_dm_p1(dfi_10_dw_rddata_dm_p1), // output wire [31 : 0] dfi_10_dw_rddata_dm_p1 + .dfi_10_dw_rddata_dbi_p1(dfi_10_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_10_dw_rddata_dbi_p1 + .dfi_10_dw_rddata_par_p1(dfi_10_dw_rddata_par_p1), // output wire [7 : 0] dfi_10_dw_rddata_par_p1 + .dfi_10_dbi_byte_disable(dfi_10_dbi_byte_disable), // output wire [15 : 0] dfi_10_dbi_byte_disable + .dfi_10_dw_rddata_valid(dfi_10_dw_rddata_valid), // output wire [3 : 0] dfi_10_dw_rddata_valid + .dfi_10_dw_derr_n(dfi_10_dw_derr_n), // output wire [7 : 0] dfi_10_dw_derr_n + .dfi_10_aw_aerr_n(dfi_10_aw_aerr_n), // output wire [1 : 0] dfi_10_aw_aerr_n + .dfi_10_ctrlupd_req(dfi_10_ctrlupd_req), // output wire dfi_10_ctrlupd_req + .dfi_10_phyupd_ack(dfi_10_phyupd_ack), // output wire dfi_10_phyupd_ack + .dfi_10_clk_init(dfi_10_clk_init), // output wire dfi_10_clk_init + .dfi_10_init_complete(dfi_10_init_complete), // output wire dfi_10_init_complete + .dfi_10_out_rst_n(dfi_10_out_rst_n), // output wire dfi_10_out_rst_n + .dfi_11_dw_rddata_p0(dfi_11_dw_rddata_p0), // output wire [255 : 0] dfi_11_dw_rddata_p0 + .dfi_11_dw_rddata_dm_p0(dfi_11_dw_rddata_dm_p0), // output wire [31 : 0] dfi_11_dw_rddata_dm_p0 + .dfi_11_dw_rddata_dbi_p0(dfi_11_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_11_dw_rddata_dbi_p0 + .dfi_11_dw_rddata_par_p0(dfi_11_dw_rddata_par_p0), // output wire [7 : 0] dfi_11_dw_rddata_par_p0 + .dfi_11_dw_rddata_p1(dfi_11_dw_rddata_p1), // output wire [255 : 0] dfi_11_dw_rddata_p1 + .dfi_11_dw_rddata_dm_p1(dfi_11_dw_rddata_dm_p1), // output wire [31 : 0] dfi_11_dw_rddata_dm_p1 + .dfi_11_dw_rddata_dbi_p1(dfi_11_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_11_dw_rddata_dbi_p1 + .dfi_11_dw_rddata_par_p1(dfi_11_dw_rddata_par_p1), // output wire [7 : 0] dfi_11_dw_rddata_par_p1 + .dfi_11_dbi_byte_disable(dfi_11_dbi_byte_disable), // output wire [15 : 0] dfi_11_dbi_byte_disable + .dfi_11_dw_rddata_valid(dfi_11_dw_rddata_valid), // output wire [3 : 0] dfi_11_dw_rddata_valid + .dfi_11_dw_derr_n(dfi_11_dw_derr_n), // output wire [7 : 0] dfi_11_dw_derr_n + .dfi_11_aw_aerr_n(dfi_11_aw_aerr_n), // output wire [1 : 0] dfi_11_aw_aerr_n + .dfi_11_ctrlupd_req(dfi_11_ctrlupd_req), // output wire dfi_11_ctrlupd_req + .dfi_11_phyupd_ack(dfi_11_phyupd_ack), // output wire dfi_11_phyupd_ack + .dfi_11_clk_init(dfi_11_clk_init), // output wire dfi_11_clk_init + .dfi_11_init_complete(dfi_11_init_complete), // output wire dfi_11_init_complete + .dfi_11_out_rst_n(dfi_11_out_rst_n), // output wire dfi_11_out_rst_n + .dfi_12_dw_rddata_p0(dfi_12_dw_rddata_p0), // output wire [255 : 0] dfi_12_dw_rddata_p0 + .dfi_12_dw_rddata_dm_p0(dfi_12_dw_rddata_dm_p0), // output wire [31 : 0] dfi_12_dw_rddata_dm_p0 + .dfi_12_dw_rddata_dbi_p0(dfi_12_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_12_dw_rddata_dbi_p0 + .dfi_12_dw_rddata_par_p0(dfi_12_dw_rddata_par_p0), // output wire [7 : 0] dfi_12_dw_rddata_par_p0 + .dfi_12_dw_rddata_p1(dfi_12_dw_rddata_p1), // output wire [255 : 0] dfi_12_dw_rddata_p1 + .dfi_12_dw_rddata_dm_p1(dfi_12_dw_rddata_dm_p1), // output wire [31 : 0] dfi_12_dw_rddata_dm_p1 + .dfi_12_dw_rddata_dbi_p1(dfi_12_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_12_dw_rddata_dbi_p1 + .dfi_12_dw_rddata_par_p1(dfi_12_dw_rddata_par_p1), // output wire [7 : 0] dfi_12_dw_rddata_par_p1 + .dfi_12_dbi_byte_disable(dfi_12_dbi_byte_disable), // output wire [15 : 0] dfi_12_dbi_byte_disable + .dfi_12_dw_rddata_valid(dfi_12_dw_rddata_valid), // output wire [3 : 0] dfi_12_dw_rddata_valid + .dfi_12_dw_derr_n(dfi_12_dw_derr_n), // output wire [7 : 0] dfi_12_dw_derr_n + .dfi_12_aw_aerr_n(dfi_12_aw_aerr_n), // output wire [1 : 0] dfi_12_aw_aerr_n + .dfi_12_ctrlupd_req(dfi_12_ctrlupd_req), // output wire dfi_12_ctrlupd_req + .dfi_12_phyupd_ack(dfi_12_phyupd_ack), // output wire dfi_12_phyupd_ack + .dfi_12_clk_init(dfi_12_clk_init), // output wire dfi_12_clk_init + .dfi_12_init_complete(dfi_12_init_complete), // output wire dfi_12_init_complete + .dfi_12_out_rst_n(dfi_12_out_rst_n), // output wire dfi_12_out_rst_n + .dfi_13_dw_rddata_p0(dfi_13_dw_rddata_p0), // output wire [255 : 0] dfi_13_dw_rddata_p0 + .dfi_13_dw_rddata_dm_p0(dfi_13_dw_rddata_dm_p0), // output wire [31 : 0] dfi_13_dw_rddata_dm_p0 + .dfi_13_dw_rddata_dbi_p0(dfi_13_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_13_dw_rddata_dbi_p0 + .dfi_13_dw_rddata_par_p0(dfi_13_dw_rddata_par_p0), // output wire [7 : 0] dfi_13_dw_rddata_par_p0 + .dfi_13_dw_rddata_p1(dfi_13_dw_rddata_p1), // output wire [255 : 0] dfi_13_dw_rddata_p1 + .dfi_13_dw_rddata_dm_p1(dfi_13_dw_rddata_dm_p1), // output wire [31 : 0] dfi_13_dw_rddata_dm_p1 + .dfi_13_dw_rddata_dbi_p1(dfi_13_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_13_dw_rddata_dbi_p1 + .dfi_13_dw_rddata_par_p1(dfi_13_dw_rddata_par_p1), // output wire [7 : 0] dfi_13_dw_rddata_par_p1 + .dfi_13_dbi_byte_disable(dfi_13_dbi_byte_disable), // output wire [15 : 0] dfi_13_dbi_byte_disable + .dfi_13_dw_rddata_valid(dfi_13_dw_rddata_valid), // output wire [3 : 0] dfi_13_dw_rddata_valid + .dfi_13_dw_derr_n(dfi_13_dw_derr_n), // output wire [7 : 0] dfi_13_dw_derr_n + .dfi_13_aw_aerr_n(dfi_13_aw_aerr_n), // output wire [1 : 0] dfi_13_aw_aerr_n + .dfi_13_ctrlupd_req(dfi_13_ctrlupd_req), // output wire dfi_13_ctrlupd_req + .dfi_13_phyupd_ack(dfi_13_phyupd_ack), // output wire dfi_13_phyupd_ack + .dfi_13_clk_init(dfi_13_clk_init), // output wire dfi_13_clk_init + .dfi_13_init_complete(dfi_13_init_complete), // output wire dfi_13_init_complete + .dfi_13_out_rst_n(dfi_13_out_rst_n), // output wire dfi_13_out_rst_n + .dfi_14_dw_rddata_p0(dfi_14_dw_rddata_p0), // output wire [255 : 0] dfi_14_dw_rddata_p0 + .dfi_14_dw_rddata_dm_p0(dfi_14_dw_rddata_dm_p0), // output wire [31 : 0] dfi_14_dw_rddata_dm_p0 + .dfi_14_dw_rddata_dbi_p0(dfi_14_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_14_dw_rddata_dbi_p0 + .dfi_14_dw_rddata_par_p0(dfi_14_dw_rddata_par_p0), // output wire [7 : 0] dfi_14_dw_rddata_par_p0 + .dfi_14_dw_rddata_p1(dfi_14_dw_rddata_p1), // output wire [255 : 0] dfi_14_dw_rddata_p1 + .dfi_14_dw_rddata_dm_p1(dfi_14_dw_rddata_dm_p1), // output wire [31 : 0] dfi_14_dw_rddata_dm_p1 + .dfi_14_dw_rddata_dbi_p1(dfi_14_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_14_dw_rddata_dbi_p1 + .dfi_14_dw_rddata_par_p1(dfi_14_dw_rddata_par_p1), // output wire [7 : 0] dfi_14_dw_rddata_par_p1 + .dfi_14_dbi_byte_disable(dfi_14_dbi_byte_disable), // output wire [15 : 0] dfi_14_dbi_byte_disable + .dfi_14_dw_rddata_valid(dfi_14_dw_rddata_valid), // output wire [3 : 0] dfi_14_dw_rddata_valid + .dfi_14_dw_derr_n(dfi_14_dw_derr_n), // output wire [7 : 0] dfi_14_dw_derr_n + .dfi_14_aw_aerr_n(dfi_14_aw_aerr_n), // output wire [1 : 0] dfi_14_aw_aerr_n + .dfi_14_ctrlupd_req(dfi_14_ctrlupd_req), // output wire dfi_14_ctrlupd_req + .dfi_14_phyupd_ack(dfi_14_phyupd_ack), // output wire dfi_14_phyupd_ack + .dfi_14_clk_init(dfi_14_clk_init), // output wire dfi_14_clk_init + .dfi_14_init_complete(dfi_14_init_complete), // output wire dfi_14_init_complete + .dfi_14_out_rst_n(dfi_14_out_rst_n), // output wire dfi_14_out_rst_n + .dfi_15_dw_rddata_p0(dfi_15_dw_rddata_p0), // output wire [255 : 0] dfi_15_dw_rddata_p0 + .dfi_15_dw_rddata_dm_p0(dfi_15_dw_rddata_dm_p0), // output wire [31 : 0] dfi_15_dw_rddata_dm_p0 + .dfi_15_dw_rddata_dbi_p0(dfi_15_dw_rddata_dbi_p0), // output wire [31 : 0] dfi_15_dw_rddata_dbi_p0 + .dfi_15_dw_rddata_par_p0(dfi_15_dw_rddata_par_p0), // output wire [7 : 0] dfi_15_dw_rddata_par_p0 + .dfi_15_dw_rddata_p1(dfi_15_dw_rddata_p1), // output wire [255 : 0] dfi_15_dw_rddata_p1 + .dfi_15_dw_rddata_dm_p1(dfi_15_dw_rddata_dm_p1), // output wire [31 : 0] dfi_15_dw_rddata_dm_p1 + .dfi_15_dw_rddata_dbi_p1(dfi_15_dw_rddata_dbi_p1), // output wire [31 : 0] dfi_15_dw_rddata_dbi_p1 + .dfi_15_dw_rddata_par_p1(dfi_15_dw_rddata_par_p1), // output wire [7 : 0] dfi_15_dw_rddata_par_p1 + .dfi_15_dbi_byte_disable(dfi_15_dbi_byte_disable), // output wire [15 : 0] dfi_15_dbi_byte_disable + .dfi_15_dw_rddata_valid(dfi_15_dw_rddata_valid), // output wire [3 : 0] dfi_15_dw_rddata_valid + .dfi_15_dw_derr_n(dfi_15_dw_derr_n), // output wire [7 : 0] dfi_15_dw_derr_n + .dfi_15_aw_aerr_n(dfi_15_aw_aerr_n), // output wire [1 : 0] dfi_15_aw_aerr_n + .dfi_15_ctrlupd_req(dfi_15_ctrlupd_req), // output wire dfi_15_ctrlupd_req + .dfi_15_phyupd_ack(dfi_15_phyupd_ack), // output wire dfi_15_phyupd_ack + .dfi_15_clk_init(dfi_15_clk_init), // output wire dfi_15_clk_init + .dfi_15_init_complete(dfi_15_init_complete), // output wire dfi_15_init_complete + .dfi_15_out_rst_n(dfi_15_out_rst_n), // output wire dfi_15_out_rst_n + .apb_complete_0(apb_complete_0), // output wire apb_complete_0 + .apb_complete_1(apb_complete_1), // output wire apb_complete_1 + .DRAM_0_STAT_CATTRIP(DRAM_0_STAT_CATTRIP), // output wire DRAM_0_STAT_CATTRIP + .DRAM_0_STAT_TEMP(DRAM_0_STAT_TEMP), // output wire [6 : 0] DRAM_0_STAT_TEMP + .DRAM_1_STAT_CATTRIP(DRAM_1_STAT_CATTRIP), // output wire DRAM_1_STAT_CATTRIP + .DRAM_1_STAT_TEMP(DRAM_1_STAT_TEMP) // output wire [6 : 0] DRAM_1_STAT_TEMP +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file hbm_0.v when simulating +// the core, hbm_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.vho new file mode 100755 index 0000000..a1292d5 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0.vho @@ -0,0 +1,1729 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:hbm:1.0 +-- IP Revision: 9 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT hbm_0 + PORT ( + HBM_REF_CLK_0 : IN STD_LOGIC; + HBM_REF_CLK_1 : IN STD_LOGIC; + dfi_0_clk : IN STD_LOGIC; + dfi_0_rst_n : IN STD_LOGIC; + dfi_0_init_start : IN STD_LOGIC; + dfi_0_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_0_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_0_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_0_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_0_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_0_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_0_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_0_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_0_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_0_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_0_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_aw_ck_dis : IN STD_LOGIC; + dfi_0_lp_pwr_e_req : IN STD_LOGIC; + dfi_0_lp_sr_e_req : IN STD_LOGIC; + dfi_0_lp_pwr_x_req : IN STD_LOGIC; + dfi_0_aw_tx_indx_ld : IN STD_LOGIC; + dfi_0_dw_tx_indx_ld : IN STD_LOGIC; + dfi_0_dw_rx_indx_ld : IN STD_LOGIC; + dfi_0_ctrlupd_ack : IN STD_LOGIC; + dfi_0_phyupd_req : IN STD_LOGIC; + dfi_0_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_clk : IN STD_LOGIC; + dfi_1_rst_n : IN STD_LOGIC; + dfi_1_init_start : IN STD_LOGIC; + dfi_1_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_1_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_1_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_1_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_1_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_1_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_1_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_1_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_1_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_1_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_1_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_aw_ck_dis : IN STD_LOGIC; + dfi_1_lp_pwr_e_req : IN STD_LOGIC; + dfi_1_lp_sr_e_req : IN STD_LOGIC; + dfi_1_lp_pwr_x_req : IN STD_LOGIC; + dfi_1_aw_tx_indx_ld : IN STD_LOGIC; + dfi_1_dw_tx_indx_ld : IN STD_LOGIC; + dfi_1_dw_rx_indx_ld : IN STD_LOGIC; + dfi_1_ctrlupd_ack : IN STD_LOGIC; + dfi_1_phyupd_req : IN STD_LOGIC; + dfi_1_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_clk : IN STD_LOGIC; + dfi_2_rst_n : IN STD_LOGIC; + dfi_2_init_start : IN STD_LOGIC; + dfi_2_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_2_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_2_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_2_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_2_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_2_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_2_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_2_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_2_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_2_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_2_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_aw_ck_dis : IN STD_LOGIC; + dfi_2_lp_pwr_e_req : IN STD_LOGIC; + dfi_2_lp_sr_e_req : IN STD_LOGIC; + dfi_2_lp_pwr_x_req : IN STD_LOGIC; + dfi_2_aw_tx_indx_ld : IN STD_LOGIC; + dfi_2_dw_tx_indx_ld : IN STD_LOGIC; + dfi_2_dw_rx_indx_ld : IN STD_LOGIC; + dfi_2_ctrlupd_ack : IN STD_LOGIC; + dfi_2_phyupd_req : IN STD_LOGIC; + dfi_2_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_clk : IN STD_LOGIC; + dfi_3_rst_n : IN STD_LOGIC; + dfi_3_init_start : IN STD_LOGIC; + dfi_3_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_3_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_3_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_3_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_3_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_3_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_3_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_3_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_3_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_3_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_3_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_aw_ck_dis : IN STD_LOGIC; + dfi_3_lp_pwr_e_req : IN STD_LOGIC; + dfi_3_lp_sr_e_req : IN STD_LOGIC; + dfi_3_lp_pwr_x_req : IN STD_LOGIC; + dfi_3_aw_tx_indx_ld : IN STD_LOGIC; + dfi_3_dw_tx_indx_ld : IN STD_LOGIC; + dfi_3_dw_rx_indx_ld : IN STD_LOGIC; + dfi_3_ctrlupd_ack : IN STD_LOGIC; + dfi_3_phyupd_req : IN STD_LOGIC; + dfi_3_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_clk : IN STD_LOGIC; + dfi_4_rst_n : IN STD_LOGIC; + dfi_4_init_start : IN STD_LOGIC; + dfi_4_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_4_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_4_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_4_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_4_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_4_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_4_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_4_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_4_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_4_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_4_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_aw_ck_dis : IN STD_LOGIC; + dfi_4_lp_pwr_e_req : IN STD_LOGIC; + dfi_4_lp_sr_e_req : IN STD_LOGIC; + dfi_4_lp_pwr_x_req : IN STD_LOGIC; + dfi_4_aw_tx_indx_ld : IN STD_LOGIC; + dfi_4_dw_tx_indx_ld : IN STD_LOGIC; + dfi_4_dw_rx_indx_ld : IN STD_LOGIC; + dfi_4_ctrlupd_ack : IN STD_LOGIC; + dfi_4_phyupd_req : IN STD_LOGIC; + dfi_4_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_clk : IN STD_LOGIC; + dfi_5_rst_n : IN STD_LOGIC; + dfi_5_init_start : IN STD_LOGIC; + dfi_5_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_5_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_5_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_5_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_5_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_5_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_5_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_5_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_5_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_5_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_5_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_aw_ck_dis : IN STD_LOGIC; + dfi_5_lp_pwr_e_req : IN STD_LOGIC; + dfi_5_lp_sr_e_req : IN STD_LOGIC; + dfi_5_lp_pwr_x_req : IN STD_LOGIC; + dfi_5_aw_tx_indx_ld : IN STD_LOGIC; + dfi_5_dw_tx_indx_ld : IN STD_LOGIC; + dfi_5_dw_rx_indx_ld : IN STD_LOGIC; + dfi_5_ctrlupd_ack : IN STD_LOGIC; + dfi_5_phyupd_req : IN STD_LOGIC; + dfi_5_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_clk : IN STD_LOGIC; + dfi_6_rst_n : IN STD_LOGIC; + dfi_6_init_start : IN STD_LOGIC; + dfi_6_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_6_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_6_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_6_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_6_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_6_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_6_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_6_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_6_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_6_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_6_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_aw_ck_dis : IN STD_LOGIC; + dfi_6_lp_pwr_e_req : IN STD_LOGIC; + dfi_6_lp_sr_e_req : IN STD_LOGIC; + dfi_6_lp_pwr_x_req : IN STD_LOGIC; + dfi_6_aw_tx_indx_ld : IN STD_LOGIC; + dfi_6_dw_tx_indx_ld : IN STD_LOGIC; + dfi_6_dw_rx_indx_ld : IN STD_LOGIC; + dfi_6_ctrlupd_ack : IN STD_LOGIC; + dfi_6_phyupd_req : IN STD_LOGIC; + dfi_6_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_clk : IN STD_LOGIC; + dfi_7_rst_n : IN STD_LOGIC; + dfi_7_init_start : IN STD_LOGIC; + dfi_7_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_7_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_7_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_7_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_7_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_7_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_7_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_7_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_7_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_7_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_7_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_aw_ck_dis : IN STD_LOGIC; + dfi_7_lp_pwr_e_req : IN STD_LOGIC; + dfi_7_lp_sr_e_req : IN STD_LOGIC; + dfi_7_lp_pwr_x_req : IN STD_LOGIC; + dfi_7_aw_tx_indx_ld : IN STD_LOGIC; + dfi_7_dw_tx_indx_ld : IN STD_LOGIC; + dfi_7_dw_rx_indx_ld : IN STD_LOGIC; + dfi_7_ctrlupd_ack : IN STD_LOGIC; + dfi_7_phyupd_req : IN STD_LOGIC; + dfi_7_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_clk : IN STD_LOGIC; + dfi_8_rst_n : IN STD_LOGIC; + dfi_8_init_start : IN STD_LOGIC; + dfi_8_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_8_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_8_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_8_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_8_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_8_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_8_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_8_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_8_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_8_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_8_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_aw_ck_dis : IN STD_LOGIC; + dfi_8_lp_pwr_e_req : IN STD_LOGIC; + dfi_8_lp_sr_e_req : IN STD_LOGIC; + dfi_8_lp_pwr_x_req : IN STD_LOGIC; + dfi_8_aw_tx_indx_ld : IN STD_LOGIC; + dfi_8_dw_tx_indx_ld : IN STD_LOGIC; + dfi_8_dw_rx_indx_ld : IN STD_LOGIC; + dfi_8_ctrlupd_ack : IN STD_LOGIC; + dfi_8_phyupd_req : IN STD_LOGIC; + dfi_8_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_clk : IN STD_LOGIC; + dfi_9_rst_n : IN STD_LOGIC; + dfi_9_init_start : IN STD_LOGIC; + dfi_9_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_9_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_9_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_9_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_9_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_9_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_9_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_9_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_9_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_9_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_9_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_aw_ck_dis : IN STD_LOGIC; + dfi_9_lp_pwr_e_req : IN STD_LOGIC; + dfi_9_lp_sr_e_req : IN STD_LOGIC; + dfi_9_lp_pwr_x_req : IN STD_LOGIC; + dfi_9_aw_tx_indx_ld : IN STD_LOGIC; + dfi_9_dw_tx_indx_ld : IN STD_LOGIC; + dfi_9_dw_rx_indx_ld : IN STD_LOGIC; + dfi_9_ctrlupd_ack : IN STD_LOGIC; + dfi_9_phyupd_req : IN STD_LOGIC; + dfi_9_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_clk : IN STD_LOGIC; + dfi_10_rst_n : IN STD_LOGIC; + dfi_10_init_start : IN STD_LOGIC; + dfi_10_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_10_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_10_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_10_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_10_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_10_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_10_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_10_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_10_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_10_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_10_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_aw_ck_dis : IN STD_LOGIC; + dfi_10_lp_pwr_e_req : IN STD_LOGIC; + dfi_10_lp_sr_e_req : IN STD_LOGIC; + dfi_10_lp_pwr_x_req : IN STD_LOGIC; + dfi_10_aw_tx_indx_ld : IN STD_LOGIC; + dfi_10_dw_tx_indx_ld : IN STD_LOGIC; + dfi_10_dw_rx_indx_ld : IN STD_LOGIC; + dfi_10_ctrlupd_ack : IN STD_LOGIC; + dfi_10_phyupd_req : IN STD_LOGIC; + dfi_10_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_clk : IN STD_LOGIC; + dfi_11_rst_n : IN STD_LOGIC; + dfi_11_init_start : IN STD_LOGIC; + dfi_11_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_11_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_11_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_11_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_11_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_11_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_11_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_11_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_11_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_11_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_11_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_aw_ck_dis : IN STD_LOGIC; + dfi_11_lp_pwr_e_req : IN STD_LOGIC; + dfi_11_lp_sr_e_req : IN STD_LOGIC; + dfi_11_lp_pwr_x_req : IN STD_LOGIC; + dfi_11_aw_tx_indx_ld : IN STD_LOGIC; + dfi_11_dw_tx_indx_ld : IN STD_LOGIC; + dfi_11_dw_rx_indx_ld : IN STD_LOGIC; + dfi_11_ctrlupd_ack : IN STD_LOGIC; + dfi_11_phyupd_req : IN STD_LOGIC; + dfi_11_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_clk : IN STD_LOGIC; + dfi_12_rst_n : IN STD_LOGIC; + dfi_12_init_start : IN STD_LOGIC; + dfi_12_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_12_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_12_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_12_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_12_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_12_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_12_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_12_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_12_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_12_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_12_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_aw_ck_dis : IN STD_LOGIC; + dfi_12_lp_pwr_e_req : IN STD_LOGIC; + dfi_12_lp_sr_e_req : IN STD_LOGIC; + dfi_12_lp_pwr_x_req : IN STD_LOGIC; + dfi_12_aw_tx_indx_ld : IN STD_LOGIC; + dfi_12_dw_tx_indx_ld : IN STD_LOGIC; + dfi_12_dw_rx_indx_ld : IN STD_LOGIC; + dfi_12_ctrlupd_ack : IN STD_LOGIC; + dfi_12_phyupd_req : IN STD_LOGIC; + dfi_12_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_clk : IN STD_LOGIC; + dfi_13_rst_n : IN STD_LOGIC; + dfi_13_init_start : IN STD_LOGIC; + dfi_13_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_13_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_13_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_13_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_13_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_13_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_13_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_13_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_13_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_13_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_13_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_aw_ck_dis : IN STD_LOGIC; + dfi_13_lp_pwr_e_req : IN STD_LOGIC; + dfi_13_lp_sr_e_req : IN STD_LOGIC; + dfi_13_lp_pwr_x_req : IN STD_LOGIC; + dfi_13_aw_tx_indx_ld : IN STD_LOGIC; + dfi_13_dw_tx_indx_ld : IN STD_LOGIC; + dfi_13_dw_rx_indx_ld : IN STD_LOGIC; + dfi_13_ctrlupd_ack : IN STD_LOGIC; + dfi_13_phyupd_req : IN STD_LOGIC; + dfi_13_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_clk : IN STD_LOGIC; + dfi_14_rst_n : IN STD_LOGIC; + dfi_14_init_start : IN STD_LOGIC; + dfi_14_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_14_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_14_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_14_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_14_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_14_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_14_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_14_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_14_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_14_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_14_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_aw_ck_dis : IN STD_LOGIC; + dfi_14_lp_pwr_e_req : IN STD_LOGIC; + dfi_14_lp_sr_e_req : IN STD_LOGIC; + dfi_14_lp_pwr_x_req : IN STD_LOGIC; + dfi_14_aw_tx_indx_ld : IN STD_LOGIC; + dfi_14_dw_tx_indx_ld : IN STD_LOGIC; + dfi_14_dw_rx_indx_ld : IN STD_LOGIC; + dfi_14_ctrlupd_ack : IN STD_LOGIC; + dfi_14_phyupd_req : IN STD_LOGIC; + dfi_14_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_clk : IN STD_LOGIC; + dfi_15_rst_n : IN STD_LOGIC; + dfi_15_init_start : IN STD_LOGIC; + dfi_15_aw_ck_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_15_aw_cke_p0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_15_aw_row_p0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_15_aw_col_p0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_15_dw_wrdata_p0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_15_dw_wrdata_mask_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_wrdata_dbi_p0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_wrdata_par_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_wrdata_dq_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_wrdata_par_en_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_aw_ck_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_15_aw_cke_p1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_15_aw_row_p1 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dfi_15_aw_col_p1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_15_dw_wrdata_p1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_15_dw_wrdata_mask_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_wrdata_dbi_p1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_wrdata_par_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_wrdata_dq_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_wrdata_par_en_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_aw_ck_dis : IN STD_LOGIC; + dfi_15_lp_pwr_e_req : IN STD_LOGIC; + dfi_15_lp_sr_e_req : IN STD_LOGIC; + dfi_15_lp_pwr_x_req : IN STD_LOGIC; + dfi_15_aw_tx_indx_ld : IN STD_LOGIC; + dfi_15_dw_tx_indx_ld : IN STD_LOGIC; + dfi_15_dw_rx_indx_ld : IN STD_LOGIC; + dfi_15_ctrlupd_ack : IN STD_LOGIC; + dfi_15_phyupd_req : IN STD_LOGIC; + dfi_15_dw_wrdata_dqs_p0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_wrdata_dqs_p1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + APB_0_PCLK : IN STD_LOGIC; + APB_0_PRESET_N : IN STD_LOGIC; + APB_1_PCLK : IN STD_LOGIC; + APB_1_PRESET_N : IN STD_LOGIC; + dfi_0_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_0_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_0_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_0_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_0_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_0_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_0_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_0_ctrlupd_req : OUT STD_LOGIC; + dfi_0_phyupd_ack : OUT STD_LOGIC; + dfi_0_clk_init : OUT STD_LOGIC; + dfi_0_init_complete : OUT STD_LOGIC; + dfi_0_out_rst_n : OUT STD_LOGIC; + dfi_1_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_1_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_1_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_1_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_1_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_1_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_1_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_1_ctrlupd_req : OUT STD_LOGIC; + dfi_1_phyupd_ack : OUT STD_LOGIC; + dfi_1_clk_init : OUT STD_LOGIC; + dfi_1_init_complete : OUT STD_LOGIC; + dfi_1_out_rst_n : OUT STD_LOGIC; + dfi_2_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_2_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_2_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_2_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_2_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_2_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_2_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_2_ctrlupd_req : OUT STD_LOGIC; + dfi_2_phyupd_ack : OUT STD_LOGIC; + dfi_2_clk_init : OUT STD_LOGIC; + dfi_2_init_complete : OUT STD_LOGIC; + dfi_2_out_rst_n : OUT STD_LOGIC; + dfi_3_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_3_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_3_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_3_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_3_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_3_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_3_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_3_ctrlupd_req : OUT STD_LOGIC; + dfi_3_phyupd_ack : OUT STD_LOGIC; + dfi_3_clk_init : OUT STD_LOGIC; + dfi_3_init_complete : OUT STD_LOGIC; + dfi_3_out_rst_n : OUT STD_LOGIC; + dfi_4_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_4_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_4_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_4_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_4_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_4_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_4_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_4_ctrlupd_req : OUT STD_LOGIC; + dfi_4_phyupd_ack : OUT STD_LOGIC; + dfi_4_clk_init : OUT STD_LOGIC; + dfi_4_init_complete : OUT STD_LOGIC; + dfi_4_out_rst_n : OUT STD_LOGIC; + dfi_5_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_5_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_5_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_5_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_5_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_5_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_5_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_5_ctrlupd_req : OUT STD_LOGIC; + dfi_5_phyupd_ack : OUT STD_LOGIC; + dfi_5_clk_init : OUT STD_LOGIC; + dfi_5_init_complete : OUT STD_LOGIC; + dfi_5_out_rst_n : OUT STD_LOGIC; + dfi_6_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_6_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_6_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_6_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_6_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_6_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_6_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_6_ctrlupd_req : OUT STD_LOGIC; + dfi_6_phyupd_ack : OUT STD_LOGIC; + dfi_6_clk_init : OUT STD_LOGIC; + dfi_6_init_complete : OUT STD_LOGIC; + dfi_6_out_rst_n : OUT STD_LOGIC; + dfi_7_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_7_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_7_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_7_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_7_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_7_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_7_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_7_ctrlupd_req : OUT STD_LOGIC; + dfi_7_phyupd_ack : OUT STD_LOGIC; + dfi_7_clk_init : OUT STD_LOGIC; + dfi_7_init_complete : OUT STD_LOGIC; + dfi_7_out_rst_n : OUT STD_LOGIC; + dfi_8_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_8_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_8_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_8_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_8_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_8_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_8_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_8_ctrlupd_req : OUT STD_LOGIC; + dfi_8_phyupd_ack : OUT STD_LOGIC; + dfi_8_clk_init : OUT STD_LOGIC; + dfi_8_init_complete : OUT STD_LOGIC; + dfi_8_out_rst_n : OUT STD_LOGIC; + dfi_9_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_9_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_9_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_9_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_9_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_9_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_9_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_9_ctrlupd_req : OUT STD_LOGIC; + dfi_9_phyupd_ack : OUT STD_LOGIC; + dfi_9_clk_init : OUT STD_LOGIC; + dfi_9_init_complete : OUT STD_LOGIC; + dfi_9_out_rst_n : OUT STD_LOGIC; + dfi_10_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_10_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_10_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_10_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_10_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_10_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_10_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_10_ctrlupd_req : OUT STD_LOGIC; + dfi_10_phyupd_ack : OUT STD_LOGIC; + dfi_10_clk_init : OUT STD_LOGIC; + dfi_10_init_complete : OUT STD_LOGIC; + dfi_10_out_rst_n : OUT STD_LOGIC; + dfi_11_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_11_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_11_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_11_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_11_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_11_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_11_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_11_ctrlupd_req : OUT STD_LOGIC; + dfi_11_phyupd_ack : OUT STD_LOGIC; + dfi_11_clk_init : OUT STD_LOGIC; + dfi_11_init_complete : OUT STD_LOGIC; + dfi_11_out_rst_n : OUT STD_LOGIC; + dfi_12_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_12_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_12_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_12_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_12_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_12_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_12_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_12_ctrlupd_req : OUT STD_LOGIC; + dfi_12_phyupd_ack : OUT STD_LOGIC; + dfi_12_clk_init : OUT STD_LOGIC; + dfi_12_init_complete : OUT STD_LOGIC; + dfi_12_out_rst_n : OUT STD_LOGIC; + dfi_13_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_13_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_13_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_13_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_13_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_13_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_13_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_13_ctrlupd_req : OUT STD_LOGIC; + dfi_13_phyupd_ack : OUT STD_LOGIC; + dfi_13_clk_init : OUT STD_LOGIC; + dfi_13_init_complete : OUT STD_LOGIC; + dfi_13_out_rst_n : OUT STD_LOGIC; + dfi_14_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_14_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_14_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_14_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_14_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_14_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_14_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_14_ctrlupd_req : OUT STD_LOGIC; + dfi_14_phyupd_ack : OUT STD_LOGIC; + dfi_14_clk_init : OUT STD_LOGIC; + dfi_14_init_complete : OUT STD_LOGIC; + dfi_14_out_rst_n : OUT STD_LOGIC; + dfi_15_dw_rddata_p0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_15_dw_rddata_dm_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_rddata_dbi_p0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_rddata_par_p0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dw_rddata_p1 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + dfi_15_dw_rddata_dm_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_rddata_dbi_p1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dfi_15_dw_rddata_par_p1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_dbi_byte_disable : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dfi_15_dw_rddata_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dfi_15_dw_derr_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dfi_15_aw_aerr_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dfi_15_ctrlupd_req : OUT STD_LOGIC; + dfi_15_phyupd_ack : OUT STD_LOGIC; + dfi_15_clk_init : OUT STD_LOGIC; + dfi_15_init_complete : OUT STD_LOGIC; + dfi_15_out_rst_n : OUT STD_LOGIC; + apb_complete_0 : OUT STD_LOGIC; + apb_complete_1 : OUT STD_LOGIC; + DRAM_0_STAT_CATTRIP : OUT STD_LOGIC; + DRAM_0_STAT_TEMP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); + DRAM_1_STAT_CATTRIP : OUT STD_LOGIC; + DRAM_1_STAT_TEMP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : hbm_0 + PORT MAP ( + HBM_REF_CLK_0 => HBM_REF_CLK_0, + HBM_REF_CLK_1 => HBM_REF_CLK_1, + dfi_0_clk => dfi_0_clk, + dfi_0_rst_n => dfi_0_rst_n, + dfi_0_init_start => dfi_0_init_start, + dfi_0_aw_ck_p0 => dfi_0_aw_ck_p0, + dfi_0_aw_cke_p0 => dfi_0_aw_cke_p0, + dfi_0_aw_row_p0 => dfi_0_aw_row_p0, + dfi_0_aw_col_p0 => dfi_0_aw_col_p0, + dfi_0_dw_wrdata_p0 => dfi_0_dw_wrdata_p0, + dfi_0_dw_wrdata_mask_p0 => dfi_0_dw_wrdata_mask_p0, + dfi_0_dw_wrdata_dbi_p0 => dfi_0_dw_wrdata_dbi_p0, + dfi_0_dw_wrdata_par_p0 => dfi_0_dw_wrdata_par_p0, + dfi_0_dw_wrdata_dq_en_p0 => dfi_0_dw_wrdata_dq_en_p0, + dfi_0_dw_wrdata_par_en_p0 => dfi_0_dw_wrdata_par_en_p0, + dfi_0_aw_ck_p1 => dfi_0_aw_ck_p1, + dfi_0_aw_cke_p1 => dfi_0_aw_cke_p1, + dfi_0_aw_row_p1 => dfi_0_aw_row_p1, + dfi_0_aw_col_p1 => dfi_0_aw_col_p1, + dfi_0_dw_wrdata_p1 => dfi_0_dw_wrdata_p1, + dfi_0_dw_wrdata_mask_p1 => dfi_0_dw_wrdata_mask_p1, + dfi_0_dw_wrdata_dbi_p1 => dfi_0_dw_wrdata_dbi_p1, + dfi_0_dw_wrdata_par_p1 => dfi_0_dw_wrdata_par_p1, + dfi_0_dw_wrdata_dq_en_p1 => dfi_0_dw_wrdata_dq_en_p1, + dfi_0_dw_wrdata_par_en_p1 => dfi_0_dw_wrdata_par_en_p1, + dfi_0_aw_ck_dis => dfi_0_aw_ck_dis, + dfi_0_lp_pwr_e_req => dfi_0_lp_pwr_e_req, + dfi_0_lp_sr_e_req => dfi_0_lp_sr_e_req, + dfi_0_lp_pwr_x_req => dfi_0_lp_pwr_x_req, + dfi_0_aw_tx_indx_ld => dfi_0_aw_tx_indx_ld, + dfi_0_dw_tx_indx_ld => dfi_0_dw_tx_indx_ld, + dfi_0_dw_rx_indx_ld => dfi_0_dw_rx_indx_ld, + dfi_0_ctrlupd_ack => dfi_0_ctrlupd_ack, + dfi_0_phyupd_req => dfi_0_phyupd_req, + dfi_0_dw_wrdata_dqs_p0 => dfi_0_dw_wrdata_dqs_p0, + dfi_0_dw_wrdata_dqs_p1 => dfi_0_dw_wrdata_dqs_p1, + dfi_1_clk => dfi_1_clk, + dfi_1_rst_n => dfi_1_rst_n, + dfi_1_init_start => dfi_1_init_start, + dfi_1_aw_ck_p0 => dfi_1_aw_ck_p0, + dfi_1_aw_cke_p0 => dfi_1_aw_cke_p0, + dfi_1_aw_row_p0 => dfi_1_aw_row_p0, + dfi_1_aw_col_p0 => dfi_1_aw_col_p0, + dfi_1_dw_wrdata_p0 => dfi_1_dw_wrdata_p0, + dfi_1_dw_wrdata_mask_p0 => dfi_1_dw_wrdata_mask_p0, + dfi_1_dw_wrdata_dbi_p0 => dfi_1_dw_wrdata_dbi_p0, + dfi_1_dw_wrdata_par_p0 => dfi_1_dw_wrdata_par_p0, + dfi_1_dw_wrdata_dq_en_p0 => dfi_1_dw_wrdata_dq_en_p0, + dfi_1_dw_wrdata_par_en_p0 => dfi_1_dw_wrdata_par_en_p0, + dfi_1_aw_ck_p1 => dfi_1_aw_ck_p1, + dfi_1_aw_cke_p1 => dfi_1_aw_cke_p1, + dfi_1_aw_row_p1 => dfi_1_aw_row_p1, + dfi_1_aw_col_p1 => dfi_1_aw_col_p1, + dfi_1_dw_wrdata_p1 => dfi_1_dw_wrdata_p1, + dfi_1_dw_wrdata_mask_p1 => dfi_1_dw_wrdata_mask_p1, + dfi_1_dw_wrdata_dbi_p1 => dfi_1_dw_wrdata_dbi_p1, + dfi_1_dw_wrdata_par_p1 => dfi_1_dw_wrdata_par_p1, + dfi_1_dw_wrdata_dq_en_p1 => dfi_1_dw_wrdata_dq_en_p1, + dfi_1_dw_wrdata_par_en_p1 => dfi_1_dw_wrdata_par_en_p1, + dfi_1_aw_ck_dis => dfi_1_aw_ck_dis, + dfi_1_lp_pwr_e_req => dfi_1_lp_pwr_e_req, + dfi_1_lp_sr_e_req => dfi_1_lp_sr_e_req, + dfi_1_lp_pwr_x_req => dfi_1_lp_pwr_x_req, + dfi_1_aw_tx_indx_ld => dfi_1_aw_tx_indx_ld, + dfi_1_dw_tx_indx_ld => dfi_1_dw_tx_indx_ld, + dfi_1_dw_rx_indx_ld => dfi_1_dw_rx_indx_ld, + dfi_1_ctrlupd_ack => dfi_1_ctrlupd_ack, + dfi_1_phyupd_req => dfi_1_phyupd_req, + dfi_1_dw_wrdata_dqs_p0 => dfi_1_dw_wrdata_dqs_p0, + dfi_1_dw_wrdata_dqs_p1 => dfi_1_dw_wrdata_dqs_p1, + dfi_2_clk => dfi_2_clk, + dfi_2_rst_n => dfi_2_rst_n, + dfi_2_init_start => dfi_2_init_start, + dfi_2_aw_ck_p0 => dfi_2_aw_ck_p0, + dfi_2_aw_cke_p0 => dfi_2_aw_cke_p0, + dfi_2_aw_row_p0 => dfi_2_aw_row_p0, + dfi_2_aw_col_p0 => dfi_2_aw_col_p0, + dfi_2_dw_wrdata_p0 => dfi_2_dw_wrdata_p0, + dfi_2_dw_wrdata_mask_p0 => dfi_2_dw_wrdata_mask_p0, + dfi_2_dw_wrdata_dbi_p0 => dfi_2_dw_wrdata_dbi_p0, + dfi_2_dw_wrdata_par_p0 => dfi_2_dw_wrdata_par_p0, + dfi_2_dw_wrdata_dq_en_p0 => dfi_2_dw_wrdata_dq_en_p0, + dfi_2_dw_wrdata_par_en_p0 => dfi_2_dw_wrdata_par_en_p0, + dfi_2_aw_ck_p1 => dfi_2_aw_ck_p1, + dfi_2_aw_cke_p1 => dfi_2_aw_cke_p1, + dfi_2_aw_row_p1 => dfi_2_aw_row_p1, + dfi_2_aw_col_p1 => dfi_2_aw_col_p1, + dfi_2_dw_wrdata_p1 => dfi_2_dw_wrdata_p1, + dfi_2_dw_wrdata_mask_p1 => dfi_2_dw_wrdata_mask_p1, + dfi_2_dw_wrdata_dbi_p1 => dfi_2_dw_wrdata_dbi_p1, + dfi_2_dw_wrdata_par_p1 => dfi_2_dw_wrdata_par_p1, + dfi_2_dw_wrdata_dq_en_p1 => dfi_2_dw_wrdata_dq_en_p1, + dfi_2_dw_wrdata_par_en_p1 => dfi_2_dw_wrdata_par_en_p1, + dfi_2_aw_ck_dis => dfi_2_aw_ck_dis, + dfi_2_lp_pwr_e_req => dfi_2_lp_pwr_e_req, + dfi_2_lp_sr_e_req => dfi_2_lp_sr_e_req, + dfi_2_lp_pwr_x_req => dfi_2_lp_pwr_x_req, + dfi_2_aw_tx_indx_ld => dfi_2_aw_tx_indx_ld, + dfi_2_dw_tx_indx_ld => dfi_2_dw_tx_indx_ld, + dfi_2_dw_rx_indx_ld => dfi_2_dw_rx_indx_ld, + dfi_2_ctrlupd_ack => dfi_2_ctrlupd_ack, + dfi_2_phyupd_req => dfi_2_phyupd_req, + dfi_2_dw_wrdata_dqs_p0 => dfi_2_dw_wrdata_dqs_p0, + dfi_2_dw_wrdata_dqs_p1 => dfi_2_dw_wrdata_dqs_p1, + dfi_3_clk => dfi_3_clk, + dfi_3_rst_n => dfi_3_rst_n, + dfi_3_init_start => dfi_3_init_start, + dfi_3_aw_ck_p0 => dfi_3_aw_ck_p0, + dfi_3_aw_cke_p0 => dfi_3_aw_cke_p0, + dfi_3_aw_row_p0 => dfi_3_aw_row_p0, + dfi_3_aw_col_p0 => dfi_3_aw_col_p0, + dfi_3_dw_wrdata_p0 => dfi_3_dw_wrdata_p0, + dfi_3_dw_wrdata_mask_p0 => dfi_3_dw_wrdata_mask_p0, + dfi_3_dw_wrdata_dbi_p0 => dfi_3_dw_wrdata_dbi_p0, + dfi_3_dw_wrdata_par_p0 => dfi_3_dw_wrdata_par_p0, + dfi_3_dw_wrdata_dq_en_p0 => dfi_3_dw_wrdata_dq_en_p0, + dfi_3_dw_wrdata_par_en_p0 => dfi_3_dw_wrdata_par_en_p0, + dfi_3_aw_ck_p1 => dfi_3_aw_ck_p1, + dfi_3_aw_cke_p1 => dfi_3_aw_cke_p1, + dfi_3_aw_row_p1 => dfi_3_aw_row_p1, + dfi_3_aw_col_p1 => dfi_3_aw_col_p1, + dfi_3_dw_wrdata_p1 => dfi_3_dw_wrdata_p1, + dfi_3_dw_wrdata_mask_p1 => dfi_3_dw_wrdata_mask_p1, + dfi_3_dw_wrdata_dbi_p1 => dfi_3_dw_wrdata_dbi_p1, + dfi_3_dw_wrdata_par_p1 => dfi_3_dw_wrdata_par_p1, + dfi_3_dw_wrdata_dq_en_p1 => dfi_3_dw_wrdata_dq_en_p1, + dfi_3_dw_wrdata_par_en_p1 => dfi_3_dw_wrdata_par_en_p1, + dfi_3_aw_ck_dis => dfi_3_aw_ck_dis, + dfi_3_lp_pwr_e_req => dfi_3_lp_pwr_e_req, + dfi_3_lp_sr_e_req => dfi_3_lp_sr_e_req, + dfi_3_lp_pwr_x_req => dfi_3_lp_pwr_x_req, + dfi_3_aw_tx_indx_ld => dfi_3_aw_tx_indx_ld, + dfi_3_dw_tx_indx_ld => dfi_3_dw_tx_indx_ld, + dfi_3_dw_rx_indx_ld => dfi_3_dw_rx_indx_ld, + dfi_3_ctrlupd_ack => dfi_3_ctrlupd_ack, + dfi_3_phyupd_req => dfi_3_phyupd_req, + dfi_3_dw_wrdata_dqs_p0 => dfi_3_dw_wrdata_dqs_p0, + dfi_3_dw_wrdata_dqs_p1 => dfi_3_dw_wrdata_dqs_p1, + dfi_4_clk => dfi_4_clk, + dfi_4_rst_n => dfi_4_rst_n, + dfi_4_init_start => dfi_4_init_start, + dfi_4_aw_ck_p0 => dfi_4_aw_ck_p0, + dfi_4_aw_cke_p0 => dfi_4_aw_cke_p0, + dfi_4_aw_row_p0 => dfi_4_aw_row_p0, + dfi_4_aw_col_p0 => dfi_4_aw_col_p0, + dfi_4_dw_wrdata_p0 => dfi_4_dw_wrdata_p0, + dfi_4_dw_wrdata_mask_p0 => dfi_4_dw_wrdata_mask_p0, + dfi_4_dw_wrdata_dbi_p0 => dfi_4_dw_wrdata_dbi_p0, + dfi_4_dw_wrdata_par_p0 => dfi_4_dw_wrdata_par_p0, + dfi_4_dw_wrdata_dq_en_p0 => dfi_4_dw_wrdata_dq_en_p0, + dfi_4_dw_wrdata_par_en_p0 => dfi_4_dw_wrdata_par_en_p0, + dfi_4_aw_ck_p1 => dfi_4_aw_ck_p1, + dfi_4_aw_cke_p1 => dfi_4_aw_cke_p1, + dfi_4_aw_row_p1 => dfi_4_aw_row_p1, + dfi_4_aw_col_p1 => dfi_4_aw_col_p1, + dfi_4_dw_wrdata_p1 => dfi_4_dw_wrdata_p1, + dfi_4_dw_wrdata_mask_p1 => dfi_4_dw_wrdata_mask_p1, + dfi_4_dw_wrdata_dbi_p1 => dfi_4_dw_wrdata_dbi_p1, + dfi_4_dw_wrdata_par_p1 => dfi_4_dw_wrdata_par_p1, + dfi_4_dw_wrdata_dq_en_p1 => dfi_4_dw_wrdata_dq_en_p1, + dfi_4_dw_wrdata_par_en_p1 => dfi_4_dw_wrdata_par_en_p1, + dfi_4_aw_ck_dis => dfi_4_aw_ck_dis, + dfi_4_lp_pwr_e_req => dfi_4_lp_pwr_e_req, + dfi_4_lp_sr_e_req => dfi_4_lp_sr_e_req, + dfi_4_lp_pwr_x_req => dfi_4_lp_pwr_x_req, + dfi_4_aw_tx_indx_ld => dfi_4_aw_tx_indx_ld, + dfi_4_dw_tx_indx_ld => dfi_4_dw_tx_indx_ld, + dfi_4_dw_rx_indx_ld => dfi_4_dw_rx_indx_ld, + dfi_4_ctrlupd_ack => dfi_4_ctrlupd_ack, + dfi_4_phyupd_req => dfi_4_phyupd_req, + dfi_4_dw_wrdata_dqs_p0 => dfi_4_dw_wrdata_dqs_p0, + dfi_4_dw_wrdata_dqs_p1 => dfi_4_dw_wrdata_dqs_p1, + dfi_5_clk => dfi_5_clk, + dfi_5_rst_n => dfi_5_rst_n, + dfi_5_init_start => dfi_5_init_start, + dfi_5_aw_ck_p0 => dfi_5_aw_ck_p0, + dfi_5_aw_cke_p0 => dfi_5_aw_cke_p0, + dfi_5_aw_row_p0 => dfi_5_aw_row_p0, + dfi_5_aw_col_p0 => dfi_5_aw_col_p0, + dfi_5_dw_wrdata_p0 => dfi_5_dw_wrdata_p0, + dfi_5_dw_wrdata_mask_p0 => dfi_5_dw_wrdata_mask_p0, + dfi_5_dw_wrdata_dbi_p0 => dfi_5_dw_wrdata_dbi_p0, + dfi_5_dw_wrdata_par_p0 => dfi_5_dw_wrdata_par_p0, + dfi_5_dw_wrdata_dq_en_p0 => dfi_5_dw_wrdata_dq_en_p0, + dfi_5_dw_wrdata_par_en_p0 => dfi_5_dw_wrdata_par_en_p0, + dfi_5_aw_ck_p1 => dfi_5_aw_ck_p1, + dfi_5_aw_cke_p1 => dfi_5_aw_cke_p1, + dfi_5_aw_row_p1 => dfi_5_aw_row_p1, + dfi_5_aw_col_p1 => dfi_5_aw_col_p1, + dfi_5_dw_wrdata_p1 => dfi_5_dw_wrdata_p1, + dfi_5_dw_wrdata_mask_p1 => dfi_5_dw_wrdata_mask_p1, + dfi_5_dw_wrdata_dbi_p1 => dfi_5_dw_wrdata_dbi_p1, + dfi_5_dw_wrdata_par_p1 => dfi_5_dw_wrdata_par_p1, + dfi_5_dw_wrdata_dq_en_p1 => dfi_5_dw_wrdata_dq_en_p1, + dfi_5_dw_wrdata_par_en_p1 => dfi_5_dw_wrdata_par_en_p1, + dfi_5_aw_ck_dis => dfi_5_aw_ck_dis, + dfi_5_lp_pwr_e_req => dfi_5_lp_pwr_e_req, + dfi_5_lp_sr_e_req => dfi_5_lp_sr_e_req, + dfi_5_lp_pwr_x_req => dfi_5_lp_pwr_x_req, + dfi_5_aw_tx_indx_ld => dfi_5_aw_tx_indx_ld, + dfi_5_dw_tx_indx_ld => dfi_5_dw_tx_indx_ld, + dfi_5_dw_rx_indx_ld => dfi_5_dw_rx_indx_ld, + dfi_5_ctrlupd_ack => dfi_5_ctrlupd_ack, + dfi_5_phyupd_req => dfi_5_phyupd_req, + dfi_5_dw_wrdata_dqs_p0 => dfi_5_dw_wrdata_dqs_p0, + dfi_5_dw_wrdata_dqs_p1 => dfi_5_dw_wrdata_dqs_p1, + dfi_6_clk => dfi_6_clk, + dfi_6_rst_n => dfi_6_rst_n, + dfi_6_init_start => dfi_6_init_start, + dfi_6_aw_ck_p0 => dfi_6_aw_ck_p0, + dfi_6_aw_cke_p0 => dfi_6_aw_cke_p0, + dfi_6_aw_row_p0 => dfi_6_aw_row_p0, + dfi_6_aw_col_p0 => dfi_6_aw_col_p0, + dfi_6_dw_wrdata_p0 => dfi_6_dw_wrdata_p0, + dfi_6_dw_wrdata_mask_p0 => dfi_6_dw_wrdata_mask_p0, + dfi_6_dw_wrdata_dbi_p0 => dfi_6_dw_wrdata_dbi_p0, + dfi_6_dw_wrdata_par_p0 => dfi_6_dw_wrdata_par_p0, + dfi_6_dw_wrdata_dq_en_p0 => dfi_6_dw_wrdata_dq_en_p0, + dfi_6_dw_wrdata_par_en_p0 => dfi_6_dw_wrdata_par_en_p0, + dfi_6_aw_ck_p1 => dfi_6_aw_ck_p1, + dfi_6_aw_cke_p1 => dfi_6_aw_cke_p1, + dfi_6_aw_row_p1 => dfi_6_aw_row_p1, + dfi_6_aw_col_p1 => dfi_6_aw_col_p1, + dfi_6_dw_wrdata_p1 => dfi_6_dw_wrdata_p1, + dfi_6_dw_wrdata_mask_p1 => dfi_6_dw_wrdata_mask_p1, + dfi_6_dw_wrdata_dbi_p1 => dfi_6_dw_wrdata_dbi_p1, + dfi_6_dw_wrdata_par_p1 => dfi_6_dw_wrdata_par_p1, + dfi_6_dw_wrdata_dq_en_p1 => dfi_6_dw_wrdata_dq_en_p1, + dfi_6_dw_wrdata_par_en_p1 => dfi_6_dw_wrdata_par_en_p1, + dfi_6_aw_ck_dis => dfi_6_aw_ck_dis, + dfi_6_lp_pwr_e_req => dfi_6_lp_pwr_e_req, + dfi_6_lp_sr_e_req => dfi_6_lp_sr_e_req, + dfi_6_lp_pwr_x_req => dfi_6_lp_pwr_x_req, + dfi_6_aw_tx_indx_ld => dfi_6_aw_tx_indx_ld, + dfi_6_dw_tx_indx_ld => dfi_6_dw_tx_indx_ld, + dfi_6_dw_rx_indx_ld => dfi_6_dw_rx_indx_ld, + dfi_6_ctrlupd_ack => dfi_6_ctrlupd_ack, + dfi_6_phyupd_req => dfi_6_phyupd_req, + dfi_6_dw_wrdata_dqs_p0 => dfi_6_dw_wrdata_dqs_p0, + dfi_6_dw_wrdata_dqs_p1 => dfi_6_dw_wrdata_dqs_p1, + dfi_7_clk => dfi_7_clk, + dfi_7_rst_n => dfi_7_rst_n, + dfi_7_init_start => dfi_7_init_start, + dfi_7_aw_ck_p0 => dfi_7_aw_ck_p0, + dfi_7_aw_cke_p0 => dfi_7_aw_cke_p0, + dfi_7_aw_row_p0 => dfi_7_aw_row_p0, + dfi_7_aw_col_p0 => dfi_7_aw_col_p0, + dfi_7_dw_wrdata_p0 => dfi_7_dw_wrdata_p0, + dfi_7_dw_wrdata_mask_p0 => dfi_7_dw_wrdata_mask_p0, + dfi_7_dw_wrdata_dbi_p0 => dfi_7_dw_wrdata_dbi_p0, + dfi_7_dw_wrdata_par_p0 => dfi_7_dw_wrdata_par_p0, + dfi_7_dw_wrdata_dq_en_p0 => dfi_7_dw_wrdata_dq_en_p0, + dfi_7_dw_wrdata_par_en_p0 => dfi_7_dw_wrdata_par_en_p0, + dfi_7_aw_ck_p1 => dfi_7_aw_ck_p1, + dfi_7_aw_cke_p1 => dfi_7_aw_cke_p1, + dfi_7_aw_row_p1 => dfi_7_aw_row_p1, + dfi_7_aw_col_p1 => dfi_7_aw_col_p1, + dfi_7_dw_wrdata_p1 => dfi_7_dw_wrdata_p1, + dfi_7_dw_wrdata_mask_p1 => dfi_7_dw_wrdata_mask_p1, + dfi_7_dw_wrdata_dbi_p1 => dfi_7_dw_wrdata_dbi_p1, + dfi_7_dw_wrdata_par_p1 => dfi_7_dw_wrdata_par_p1, + dfi_7_dw_wrdata_dq_en_p1 => dfi_7_dw_wrdata_dq_en_p1, + dfi_7_dw_wrdata_par_en_p1 => dfi_7_dw_wrdata_par_en_p1, + dfi_7_aw_ck_dis => dfi_7_aw_ck_dis, + dfi_7_lp_pwr_e_req => dfi_7_lp_pwr_e_req, + dfi_7_lp_sr_e_req => dfi_7_lp_sr_e_req, + dfi_7_lp_pwr_x_req => dfi_7_lp_pwr_x_req, + dfi_7_aw_tx_indx_ld => dfi_7_aw_tx_indx_ld, + dfi_7_dw_tx_indx_ld => dfi_7_dw_tx_indx_ld, + dfi_7_dw_rx_indx_ld => dfi_7_dw_rx_indx_ld, + dfi_7_ctrlupd_ack => dfi_7_ctrlupd_ack, + dfi_7_phyupd_req => dfi_7_phyupd_req, + dfi_7_dw_wrdata_dqs_p0 => dfi_7_dw_wrdata_dqs_p0, + dfi_7_dw_wrdata_dqs_p1 => dfi_7_dw_wrdata_dqs_p1, + dfi_8_clk => dfi_8_clk, + dfi_8_rst_n => dfi_8_rst_n, + dfi_8_init_start => dfi_8_init_start, + dfi_8_aw_ck_p0 => dfi_8_aw_ck_p0, + dfi_8_aw_cke_p0 => dfi_8_aw_cke_p0, + dfi_8_aw_row_p0 => dfi_8_aw_row_p0, + dfi_8_aw_col_p0 => dfi_8_aw_col_p0, + dfi_8_dw_wrdata_p0 => dfi_8_dw_wrdata_p0, + dfi_8_dw_wrdata_mask_p0 => dfi_8_dw_wrdata_mask_p0, + dfi_8_dw_wrdata_dbi_p0 => dfi_8_dw_wrdata_dbi_p0, + dfi_8_dw_wrdata_par_p0 => dfi_8_dw_wrdata_par_p0, + dfi_8_dw_wrdata_dq_en_p0 => dfi_8_dw_wrdata_dq_en_p0, + dfi_8_dw_wrdata_par_en_p0 => dfi_8_dw_wrdata_par_en_p0, + dfi_8_aw_ck_p1 => dfi_8_aw_ck_p1, + dfi_8_aw_cke_p1 => dfi_8_aw_cke_p1, + dfi_8_aw_row_p1 => dfi_8_aw_row_p1, + dfi_8_aw_col_p1 => dfi_8_aw_col_p1, + dfi_8_dw_wrdata_p1 => dfi_8_dw_wrdata_p1, + dfi_8_dw_wrdata_mask_p1 => dfi_8_dw_wrdata_mask_p1, + dfi_8_dw_wrdata_dbi_p1 => dfi_8_dw_wrdata_dbi_p1, + dfi_8_dw_wrdata_par_p1 => dfi_8_dw_wrdata_par_p1, + dfi_8_dw_wrdata_dq_en_p1 => dfi_8_dw_wrdata_dq_en_p1, + dfi_8_dw_wrdata_par_en_p1 => dfi_8_dw_wrdata_par_en_p1, + dfi_8_aw_ck_dis => dfi_8_aw_ck_dis, + dfi_8_lp_pwr_e_req => dfi_8_lp_pwr_e_req, + dfi_8_lp_sr_e_req => dfi_8_lp_sr_e_req, + dfi_8_lp_pwr_x_req => dfi_8_lp_pwr_x_req, + dfi_8_aw_tx_indx_ld => dfi_8_aw_tx_indx_ld, + dfi_8_dw_tx_indx_ld => dfi_8_dw_tx_indx_ld, + dfi_8_dw_rx_indx_ld => dfi_8_dw_rx_indx_ld, + dfi_8_ctrlupd_ack => dfi_8_ctrlupd_ack, + dfi_8_phyupd_req => dfi_8_phyupd_req, + dfi_8_dw_wrdata_dqs_p0 => dfi_8_dw_wrdata_dqs_p0, + dfi_8_dw_wrdata_dqs_p1 => dfi_8_dw_wrdata_dqs_p1, + dfi_9_clk => dfi_9_clk, + dfi_9_rst_n => dfi_9_rst_n, + dfi_9_init_start => dfi_9_init_start, + dfi_9_aw_ck_p0 => dfi_9_aw_ck_p0, + dfi_9_aw_cke_p0 => dfi_9_aw_cke_p0, + dfi_9_aw_row_p0 => dfi_9_aw_row_p0, + dfi_9_aw_col_p0 => dfi_9_aw_col_p0, + dfi_9_dw_wrdata_p0 => dfi_9_dw_wrdata_p0, + dfi_9_dw_wrdata_mask_p0 => dfi_9_dw_wrdata_mask_p0, + dfi_9_dw_wrdata_dbi_p0 => dfi_9_dw_wrdata_dbi_p0, + dfi_9_dw_wrdata_par_p0 => dfi_9_dw_wrdata_par_p0, + dfi_9_dw_wrdata_dq_en_p0 => dfi_9_dw_wrdata_dq_en_p0, + dfi_9_dw_wrdata_par_en_p0 => dfi_9_dw_wrdata_par_en_p0, + dfi_9_aw_ck_p1 => dfi_9_aw_ck_p1, + dfi_9_aw_cke_p1 => dfi_9_aw_cke_p1, + dfi_9_aw_row_p1 => dfi_9_aw_row_p1, + dfi_9_aw_col_p1 => dfi_9_aw_col_p1, + dfi_9_dw_wrdata_p1 => dfi_9_dw_wrdata_p1, + dfi_9_dw_wrdata_mask_p1 => dfi_9_dw_wrdata_mask_p1, + dfi_9_dw_wrdata_dbi_p1 => dfi_9_dw_wrdata_dbi_p1, + dfi_9_dw_wrdata_par_p1 => dfi_9_dw_wrdata_par_p1, + dfi_9_dw_wrdata_dq_en_p1 => dfi_9_dw_wrdata_dq_en_p1, + dfi_9_dw_wrdata_par_en_p1 => dfi_9_dw_wrdata_par_en_p1, + dfi_9_aw_ck_dis => dfi_9_aw_ck_dis, + dfi_9_lp_pwr_e_req => dfi_9_lp_pwr_e_req, + dfi_9_lp_sr_e_req => dfi_9_lp_sr_e_req, + dfi_9_lp_pwr_x_req => dfi_9_lp_pwr_x_req, + dfi_9_aw_tx_indx_ld => dfi_9_aw_tx_indx_ld, + dfi_9_dw_tx_indx_ld => dfi_9_dw_tx_indx_ld, + dfi_9_dw_rx_indx_ld => dfi_9_dw_rx_indx_ld, + dfi_9_ctrlupd_ack => dfi_9_ctrlupd_ack, + dfi_9_phyupd_req => dfi_9_phyupd_req, + dfi_9_dw_wrdata_dqs_p0 => dfi_9_dw_wrdata_dqs_p0, + dfi_9_dw_wrdata_dqs_p1 => dfi_9_dw_wrdata_dqs_p1, + dfi_10_clk => dfi_10_clk, + dfi_10_rst_n => dfi_10_rst_n, + dfi_10_init_start => dfi_10_init_start, + dfi_10_aw_ck_p0 => dfi_10_aw_ck_p0, + dfi_10_aw_cke_p0 => dfi_10_aw_cke_p0, + dfi_10_aw_row_p0 => dfi_10_aw_row_p0, + dfi_10_aw_col_p0 => dfi_10_aw_col_p0, + dfi_10_dw_wrdata_p0 => dfi_10_dw_wrdata_p0, + dfi_10_dw_wrdata_mask_p0 => dfi_10_dw_wrdata_mask_p0, + dfi_10_dw_wrdata_dbi_p0 => dfi_10_dw_wrdata_dbi_p0, + dfi_10_dw_wrdata_par_p0 => dfi_10_dw_wrdata_par_p0, + dfi_10_dw_wrdata_dq_en_p0 => dfi_10_dw_wrdata_dq_en_p0, + dfi_10_dw_wrdata_par_en_p0 => dfi_10_dw_wrdata_par_en_p0, + dfi_10_aw_ck_p1 => dfi_10_aw_ck_p1, + dfi_10_aw_cke_p1 => dfi_10_aw_cke_p1, + dfi_10_aw_row_p1 => dfi_10_aw_row_p1, + dfi_10_aw_col_p1 => dfi_10_aw_col_p1, + dfi_10_dw_wrdata_p1 => dfi_10_dw_wrdata_p1, + dfi_10_dw_wrdata_mask_p1 => dfi_10_dw_wrdata_mask_p1, + dfi_10_dw_wrdata_dbi_p1 => dfi_10_dw_wrdata_dbi_p1, + dfi_10_dw_wrdata_par_p1 => dfi_10_dw_wrdata_par_p1, + dfi_10_dw_wrdata_dq_en_p1 => dfi_10_dw_wrdata_dq_en_p1, + dfi_10_dw_wrdata_par_en_p1 => dfi_10_dw_wrdata_par_en_p1, + dfi_10_aw_ck_dis => dfi_10_aw_ck_dis, + dfi_10_lp_pwr_e_req => dfi_10_lp_pwr_e_req, + dfi_10_lp_sr_e_req => dfi_10_lp_sr_e_req, + dfi_10_lp_pwr_x_req => dfi_10_lp_pwr_x_req, + dfi_10_aw_tx_indx_ld => dfi_10_aw_tx_indx_ld, + dfi_10_dw_tx_indx_ld => dfi_10_dw_tx_indx_ld, + dfi_10_dw_rx_indx_ld => dfi_10_dw_rx_indx_ld, + dfi_10_ctrlupd_ack => dfi_10_ctrlupd_ack, + dfi_10_phyupd_req => dfi_10_phyupd_req, + dfi_10_dw_wrdata_dqs_p0 => dfi_10_dw_wrdata_dqs_p0, + dfi_10_dw_wrdata_dqs_p1 => dfi_10_dw_wrdata_dqs_p1, + dfi_11_clk => dfi_11_clk, + dfi_11_rst_n => dfi_11_rst_n, + dfi_11_init_start => dfi_11_init_start, + dfi_11_aw_ck_p0 => dfi_11_aw_ck_p0, + dfi_11_aw_cke_p0 => dfi_11_aw_cke_p0, + dfi_11_aw_row_p0 => dfi_11_aw_row_p0, + dfi_11_aw_col_p0 => dfi_11_aw_col_p0, + dfi_11_dw_wrdata_p0 => dfi_11_dw_wrdata_p0, + dfi_11_dw_wrdata_mask_p0 => dfi_11_dw_wrdata_mask_p0, + dfi_11_dw_wrdata_dbi_p0 => dfi_11_dw_wrdata_dbi_p0, + dfi_11_dw_wrdata_par_p0 => dfi_11_dw_wrdata_par_p0, + dfi_11_dw_wrdata_dq_en_p0 => dfi_11_dw_wrdata_dq_en_p0, + dfi_11_dw_wrdata_par_en_p0 => dfi_11_dw_wrdata_par_en_p0, + dfi_11_aw_ck_p1 => dfi_11_aw_ck_p1, + dfi_11_aw_cke_p1 => dfi_11_aw_cke_p1, + dfi_11_aw_row_p1 => dfi_11_aw_row_p1, + dfi_11_aw_col_p1 => dfi_11_aw_col_p1, + dfi_11_dw_wrdata_p1 => dfi_11_dw_wrdata_p1, + dfi_11_dw_wrdata_mask_p1 => dfi_11_dw_wrdata_mask_p1, + dfi_11_dw_wrdata_dbi_p1 => dfi_11_dw_wrdata_dbi_p1, + dfi_11_dw_wrdata_par_p1 => dfi_11_dw_wrdata_par_p1, + dfi_11_dw_wrdata_dq_en_p1 => dfi_11_dw_wrdata_dq_en_p1, + dfi_11_dw_wrdata_par_en_p1 => dfi_11_dw_wrdata_par_en_p1, + dfi_11_aw_ck_dis => dfi_11_aw_ck_dis, + dfi_11_lp_pwr_e_req => dfi_11_lp_pwr_e_req, + dfi_11_lp_sr_e_req => dfi_11_lp_sr_e_req, + dfi_11_lp_pwr_x_req => dfi_11_lp_pwr_x_req, + dfi_11_aw_tx_indx_ld => dfi_11_aw_tx_indx_ld, + dfi_11_dw_tx_indx_ld => dfi_11_dw_tx_indx_ld, + dfi_11_dw_rx_indx_ld => dfi_11_dw_rx_indx_ld, + dfi_11_ctrlupd_ack => dfi_11_ctrlupd_ack, + dfi_11_phyupd_req => dfi_11_phyupd_req, + dfi_11_dw_wrdata_dqs_p0 => dfi_11_dw_wrdata_dqs_p0, + dfi_11_dw_wrdata_dqs_p1 => dfi_11_dw_wrdata_dqs_p1, + dfi_12_clk => dfi_12_clk, + dfi_12_rst_n => dfi_12_rst_n, + dfi_12_init_start => dfi_12_init_start, + dfi_12_aw_ck_p0 => dfi_12_aw_ck_p0, + dfi_12_aw_cke_p0 => dfi_12_aw_cke_p0, + dfi_12_aw_row_p0 => dfi_12_aw_row_p0, + dfi_12_aw_col_p0 => dfi_12_aw_col_p0, + dfi_12_dw_wrdata_p0 => dfi_12_dw_wrdata_p0, + dfi_12_dw_wrdata_mask_p0 => dfi_12_dw_wrdata_mask_p0, + dfi_12_dw_wrdata_dbi_p0 => dfi_12_dw_wrdata_dbi_p0, + dfi_12_dw_wrdata_par_p0 => dfi_12_dw_wrdata_par_p0, + dfi_12_dw_wrdata_dq_en_p0 => dfi_12_dw_wrdata_dq_en_p0, + dfi_12_dw_wrdata_par_en_p0 => dfi_12_dw_wrdata_par_en_p0, + dfi_12_aw_ck_p1 => dfi_12_aw_ck_p1, + dfi_12_aw_cke_p1 => dfi_12_aw_cke_p1, + dfi_12_aw_row_p1 => dfi_12_aw_row_p1, + dfi_12_aw_col_p1 => dfi_12_aw_col_p1, + dfi_12_dw_wrdata_p1 => dfi_12_dw_wrdata_p1, + dfi_12_dw_wrdata_mask_p1 => dfi_12_dw_wrdata_mask_p1, + dfi_12_dw_wrdata_dbi_p1 => dfi_12_dw_wrdata_dbi_p1, + dfi_12_dw_wrdata_par_p1 => dfi_12_dw_wrdata_par_p1, + dfi_12_dw_wrdata_dq_en_p1 => dfi_12_dw_wrdata_dq_en_p1, + dfi_12_dw_wrdata_par_en_p1 => dfi_12_dw_wrdata_par_en_p1, + dfi_12_aw_ck_dis => dfi_12_aw_ck_dis, + dfi_12_lp_pwr_e_req => dfi_12_lp_pwr_e_req, + dfi_12_lp_sr_e_req => dfi_12_lp_sr_e_req, + dfi_12_lp_pwr_x_req => dfi_12_lp_pwr_x_req, + dfi_12_aw_tx_indx_ld => dfi_12_aw_tx_indx_ld, + dfi_12_dw_tx_indx_ld => dfi_12_dw_tx_indx_ld, + dfi_12_dw_rx_indx_ld => dfi_12_dw_rx_indx_ld, + dfi_12_ctrlupd_ack => dfi_12_ctrlupd_ack, + dfi_12_phyupd_req => dfi_12_phyupd_req, + dfi_12_dw_wrdata_dqs_p0 => dfi_12_dw_wrdata_dqs_p0, + dfi_12_dw_wrdata_dqs_p1 => dfi_12_dw_wrdata_dqs_p1, + dfi_13_clk => dfi_13_clk, + dfi_13_rst_n => dfi_13_rst_n, + dfi_13_init_start => dfi_13_init_start, + dfi_13_aw_ck_p0 => dfi_13_aw_ck_p0, + dfi_13_aw_cke_p0 => dfi_13_aw_cke_p0, + dfi_13_aw_row_p0 => dfi_13_aw_row_p0, + dfi_13_aw_col_p0 => dfi_13_aw_col_p0, + dfi_13_dw_wrdata_p0 => dfi_13_dw_wrdata_p0, + dfi_13_dw_wrdata_mask_p0 => dfi_13_dw_wrdata_mask_p0, + dfi_13_dw_wrdata_dbi_p0 => dfi_13_dw_wrdata_dbi_p0, + dfi_13_dw_wrdata_par_p0 => dfi_13_dw_wrdata_par_p0, + dfi_13_dw_wrdata_dq_en_p0 => dfi_13_dw_wrdata_dq_en_p0, + dfi_13_dw_wrdata_par_en_p0 => dfi_13_dw_wrdata_par_en_p0, + dfi_13_aw_ck_p1 => dfi_13_aw_ck_p1, + dfi_13_aw_cke_p1 => dfi_13_aw_cke_p1, + dfi_13_aw_row_p1 => dfi_13_aw_row_p1, + dfi_13_aw_col_p1 => dfi_13_aw_col_p1, + dfi_13_dw_wrdata_p1 => dfi_13_dw_wrdata_p1, + dfi_13_dw_wrdata_mask_p1 => dfi_13_dw_wrdata_mask_p1, + dfi_13_dw_wrdata_dbi_p1 => dfi_13_dw_wrdata_dbi_p1, + dfi_13_dw_wrdata_par_p1 => dfi_13_dw_wrdata_par_p1, + dfi_13_dw_wrdata_dq_en_p1 => dfi_13_dw_wrdata_dq_en_p1, + dfi_13_dw_wrdata_par_en_p1 => dfi_13_dw_wrdata_par_en_p1, + dfi_13_aw_ck_dis => dfi_13_aw_ck_dis, + dfi_13_lp_pwr_e_req => dfi_13_lp_pwr_e_req, + dfi_13_lp_sr_e_req => dfi_13_lp_sr_e_req, + dfi_13_lp_pwr_x_req => dfi_13_lp_pwr_x_req, + dfi_13_aw_tx_indx_ld => dfi_13_aw_tx_indx_ld, + dfi_13_dw_tx_indx_ld => dfi_13_dw_tx_indx_ld, + dfi_13_dw_rx_indx_ld => dfi_13_dw_rx_indx_ld, + dfi_13_ctrlupd_ack => dfi_13_ctrlupd_ack, + dfi_13_phyupd_req => dfi_13_phyupd_req, + dfi_13_dw_wrdata_dqs_p0 => dfi_13_dw_wrdata_dqs_p0, + dfi_13_dw_wrdata_dqs_p1 => dfi_13_dw_wrdata_dqs_p1, + dfi_14_clk => dfi_14_clk, + dfi_14_rst_n => dfi_14_rst_n, + dfi_14_init_start => dfi_14_init_start, + dfi_14_aw_ck_p0 => dfi_14_aw_ck_p0, + dfi_14_aw_cke_p0 => dfi_14_aw_cke_p0, + dfi_14_aw_row_p0 => dfi_14_aw_row_p0, + dfi_14_aw_col_p0 => dfi_14_aw_col_p0, + dfi_14_dw_wrdata_p0 => dfi_14_dw_wrdata_p0, + dfi_14_dw_wrdata_mask_p0 => dfi_14_dw_wrdata_mask_p0, + dfi_14_dw_wrdata_dbi_p0 => dfi_14_dw_wrdata_dbi_p0, + dfi_14_dw_wrdata_par_p0 => dfi_14_dw_wrdata_par_p0, + dfi_14_dw_wrdata_dq_en_p0 => dfi_14_dw_wrdata_dq_en_p0, + dfi_14_dw_wrdata_par_en_p0 => dfi_14_dw_wrdata_par_en_p0, + dfi_14_aw_ck_p1 => dfi_14_aw_ck_p1, + dfi_14_aw_cke_p1 => dfi_14_aw_cke_p1, + dfi_14_aw_row_p1 => dfi_14_aw_row_p1, + dfi_14_aw_col_p1 => dfi_14_aw_col_p1, + dfi_14_dw_wrdata_p1 => dfi_14_dw_wrdata_p1, + dfi_14_dw_wrdata_mask_p1 => dfi_14_dw_wrdata_mask_p1, + dfi_14_dw_wrdata_dbi_p1 => dfi_14_dw_wrdata_dbi_p1, + dfi_14_dw_wrdata_par_p1 => dfi_14_dw_wrdata_par_p1, + dfi_14_dw_wrdata_dq_en_p1 => dfi_14_dw_wrdata_dq_en_p1, + dfi_14_dw_wrdata_par_en_p1 => dfi_14_dw_wrdata_par_en_p1, + dfi_14_aw_ck_dis => dfi_14_aw_ck_dis, + dfi_14_lp_pwr_e_req => dfi_14_lp_pwr_e_req, + dfi_14_lp_sr_e_req => dfi_14_lp_sr_e_req, + dfi_14_lp_pwr_x_req => dfi_14_lp_pwr_x_req, + dfi_14_aw_tx_indx_ld => dfi_14_aw_tx_indx_ld, + dfi_14_dw_tx_indx_ld => dfi_14_dw_tx_indx_ld, + dfi_14_dw_rx_indx_ld => dfi_14_dw_rx_indx_ld, + dfi_14_ctrlupd_ack => dfi_14_ctrlupd_ack, + dfi_14_phyupd_req => dfi_14_phyupd_req, + dfi_14_dw_wrdata_dqs_p0 => dfi_14_dw_wrdata_dqs_p0, + dfi_14_dw_wrdata_dqs_p1 => dfi_14_dw_wrdata_dqs_p1, + dfi_15_clk => dfi_15_clk, + dfi_15_rst_n => dfi_15_rst_n, + dfi_15_init_start => dfi_15_init_start, + dfi_15_aw_ck_p0 => dfi_15_aw_ck_p0, + dfi_15_aw_cke_p0 => dfi_15_aw_cke_p0, + dfi_15_aw_row_p0 => dfi_15_aw_row_p0, + dfi_15_aw_col_p0 => dfi_15_aw_col_p0, + dfi_15_dw_wrdata_p0 => dfi_15_dw_wrdata_p0, + dfi_15_dw_wrdata_mask_p0 => dfi_15_dw_wrdata_mask_p0, + dfi_15_dw_wrdata_dbi_p0 => dfi_15_dw_wrdata_dbi_p0, + dfi_15_dw_wrdata_par_p0 => dfi_15_dw_wrdata_par_p0, + dfi_15_dw_wrdata_dq_en_p0 => dfi_15_dw_wrdata_dq_en_p0, + dfi_15_dw_wrdata_par_en_p0 => dfi_15_dw_wrdata_par_en_p0, + dfi_15_aw_ck_p1 => dfi_15_aw_ck_p1, + dfi_15_aw_cke_p1 => dfi_15_aw_cke_p1, + dfi_15_aw_row_p1 => dfi_15_aw_row_p1, + dfi_15_aw_col_p1 => dfi_15_aw_col_p1, + dfi_15_dw_wrdata_p1 => dfi_15_dw_wrdata_p1, + dfi_15_dw_wrdata_mask_p1 => dfi_15_dw_wrdata_mask_p1, + dfi_15_dw_wrdata_dbi_p1 => dfi_15_dw_wrdata_dbi_p1, + dfi_15_dw_wrdata_par_p1 => dfi_15_dw_wrdata_par_p1, + dfi_15_dw_wrdata_dq_en_p1 => dfi_15_dw_wrdata_dq_en_p1, + dfi_15_dw_wrdata_par_en_p1 => dfi_15_dw_wrdata_par_en_p1, + dfi_15_aw_ck_dis => dfi_15_aw_ck_dis, + dfi_15_lp_pwr_e_req => dfi_15_lp_pwr_e_req, + dfi_15_lp_sr_e_req => dfi_15_lp_sr_e_req, + dfi_15_lp_pwr_x_req => dfi_15_lp_pwr_x_req, + dfi_15_aw_tx_indx_ld => dfi_15_aw_tx_indx_ld, + dfi_15_dw_tx_indx_ld => dfi_15_dw_tx_indx_ld, + dfi_15_dw_rx_indx_ld => dfi_15_dw_rx_indx_ld, + dfi_15_ctrlupd_ack => dfi_15_ctrlupd_ack, + dfi_15_phyupd_req => dfi_15_phyupd_req, + dfi_15_dw_wrdata_dqs_p0 => dfi_15_dw_wrdata_dqs_p0, + dfi_15_dw_wrdata_dqs_p1 => dfi_15_dw_wrdata_dqs_p1, + APB_0_PCLK => APB_0_PCLK, + APB_0_PRESET_N => APB_0_PRESET_N, + APB_1_PCLK => APB_1_PCLK, + APB_1_PRESET_N => APB_1_PRESET_N, + dfi_0_dw_rddata_p0 => dfi_0_dw_rddata_p0, + dfi_0_dw_rddata_dm_p0 => dfi_0_dw_rddata_dm_p0, + dfi_0_dw_rddata_dbi_p0 => dfi_0_dw_rddata_dbi_p0, + dfi_0_dw_rddata_par_p0 => dfi_0_dw_rddata_par_p0, + dfi_0_dw_rddata_p1 => dfi_0_dw_rddata_p1, + dfi_0_dw_rddata_dm_p1 => dfi_0_dw_rddata_dm_p1, + dfi_0_dw_rddata_dbi_p1 => dfi_0_dw_rddata_dbi_p1, + dfi_0_dw_rddata_par_p1 => dfi_0_dw_rddata_par_p1, + dfi_0_dbi_byte_disable => dfi_0_dbi_byte_disable, + dfi_0_dw_rddata_valid => dfi_0_dw_rddata_valid, + dfi_0_dw_derr_n => dfi_0_dw_derr_n, + dfi_0_aw_aerr_n => dfi_0_aw_aerr_n, + dfi_0_ctrlupd_req => dfi_0_ctrlupd_req, + dfi_0_phyupd_ack => dfi_0_phyupd_ack, + dfi_0_clk_init => dfi_0_clk_init, + dfi_0_init_complete => dfi_0_init_complete, + dfi_0_out_rst_n => dfi_0_out_rst_n, + dfi_1_dw_rddata_p0 => dfi_1_dw_rddata_p0, + dfi_1_dw_rddata_dm_p0 => dfi_1_dw_rddata_dm_p0, + dfi_1_dw_rddata_dbi_p0 => dfi_1_dw_rddata_dbi_p0, + dfi_1_dw_rddata_par_p0 => dfi_1_dw_rddata_par_p0, + dfi_1_dw_rddata_p1 => dfi_1_dw_rddata_p1, + dfi_1_dw_rddata_dm_p1 => dfi_1_dw_rddata_dm_p1, + dfi_1_dw_rddata_dbi_p1 => dfi_1_dw_rddata_dbi_p1, + dfi_1_dw_rddata_par_p1 => dfi_1_dw_rddata_par_p1, + dfi_1_dbi_byte_disable => dfi_1_dbi_byte_disable, + dfi_1_dw_rddata_valid => dfi_1_dw_rddata_valid, + dfi_1_dw_derr_n => dfi_1_dw_derr_n, + dfi_1_aw_aerr_n => dfi_1_aw_aerr_n, + dfi_1_ctrlupd_req => dfi_1_ctrlupd_req, + dfi_1_phyupd_ack => dfi_1_phyupd_ack, + dfi_1_clk_init => dfi_1_clk_init, + dfi_1_init_complete => dfi_1_init_complete, + dfi_1_out_rst_n => dfi_1_out_rst_n, + dfi_2_dw_rddata_p0 => dfi_2_dw_rddata_p0, + dfi_2_dw_rddata_dm_p0 => dfi_2_dw_rddata_dm_p0, + dfi_2_dw_rddata_dbi_p0 => dfi_2_dw_rddata_dbi_p0, + dfi_2_dw_rddata_par_p0 => dfi_2_dw_rddata_par_p0, + dfi_2_dw_rddata_p1 => dfi_2_dw_rddata_p1, + dfi_2_dw_rddata_dm_p1 => dfi_2_dw_rddata_dm_p1, + dfi_2_dw_rddata_dbi_p1 => dfi_2_dw_rddata_dbi_p1, + dfi_2_dw_rddata_par_p1 => dfi_2_dw_rddata_par_p1, + dfi_2_dbi_byte_disable => dfi_2_dbi_byte_disable, + dfi_2_dw_rddata_valid => dfi_2_dw_rddata_valid, + dfi_2_dw_derr_n => dfi_2_dw_derr_n, + dfi_2_aw_aerr_n => dfi_2_aw_aerr_n, + dfi_2_ctrlupd_req => dfi_2_ctrlupd_req, + dfi_2_phyupd_ack => dfi_2_phyupd_ack, + dfi_2_clk_init => dfi_2_clk_init, + dfi_2_init_complete => dfi_2_init_complete, + dfi_2_out_rst_n => dfi_2_out_rst_n, + dfi_3_dw_rddata_p0 => dfi_3_dw_rddata_p0, + dfi_3_dw_rddata_dm_p0 => dfi_3_dw_rddata_dm_p0, + dfi_3_dw_rddata_dbi_p0 => dfi_3_dw_rddata_dbi_p0, + dfi_3_dw_rddata_par_p0 => dfi_3_dw_rddata_par_p0, + dfi_3_dw_rddata_p1 => dfi_3_dw_rddata_p1, + dfi_3_dw_rddata_dm_p1 => dfi_3_dw_rddata_dm_p1, + dfi_3_dw_rddata_dbi_p1 => dfi_3_dw_rddata_dbi_p1, + dfi_3_dw_rddata_par_p1 => dfi_3_dw_rddata_par_p1, + dfi_3_dbi_byte_disable => dfi_3_dbi_byte_disable, + dfi_3_dw_rddata_valid => dfi_3_dw_rddata_valid, + dfi_3_dw_derr_n => dfi_3_dw_derr_n, + dfi_3_aw_aerr_n => dfi_3_aw_aerr_n, + dfi_3_ctrlupd_req => dfi_3_ctrlupd_req, + dfi_3_phyupd_ack => dfi_3_phyupd_ack, + dfi_3_clk_init => dfi_3_clk_init, + dfi_3_init_complete => dfi_3_init_complete, + dfi_3_out_rst_n => dfi_3_out_rst_n, + dfi_4_dw_rddata_p0 => dfi_4_dw_rddata_p0, + dfi_4_dw_rddata_dm_p0 => dfi_4_dw_rddata_dm_p0, + dfi_4_dw_rddata_dbi_p0 => dfi_4_dw_rddata_dbi_p0, + dfi_4_dw_rddata_par_p0 => dfi_4_dw_rddata_par_p0, + dfi_4_dw_rddata_p1 => dfi_4_dw_rddata_p1, + dfi_4_dw_rddata_dm_p1 => dfi_4_dw_rddata_dm_p1, + dfi_4_dw_rddata_dbi_p1 => dfi_4_dw_rddata_dbi_p1, + dfi_4_dw_rddata_par_p1 => dfi_4_dw_rddata_par_p1, + dfi_4_dbi_byte_disable => dfi_4_dbi_byte_disable, + dfi_4_dw_rddata_valid => dfi_4_dw_rddata_valid, + dfi_4_dw_derr_n => dfi_4_dw_derr_n, + dfi_4_aw_aerr_n => dfi_4_aw_aerr_n, + dfi_4_ctrlupd_req => dfi_4_ctrlupd_req, + dfi_4_phyupd_ack => dfi_4_phyupd_ack, + dfi_4_clk_init => dfi_4_clk_init, + dfi_4_init_complete => dfi_4_init_complete, + dfi_4_out_rst_n => dfi_4_out_rst_n, + dfi_5_dw_rddata_p0 => dfi_5_dw_rddata_p0, + dfi_5_dw_rddata_dm_p0 => dfi_5_dw_rddata_dm_p0, + dfi_5_dw_rddata_dbi_p0 => dfi_5_dw_rddata_dbi_p0, + dfi_5_dw_rddata_par_p0 => dfi_5_dw_rddata_par_p0, + dfi_5_dw_rddata_p1 => dfi_5_dw_rddata_p1, + dfi_5_dw_rddata_dm_p1 => dfi_5_dw_rddata_dm_p1, + dfi_5_dw_rddata_dbi_p1 => dfi_5_dw_rddata_dbi_p1, + dfi_5_dw_rddata_par_p1 => dfi_5_dw_rddata_par_p1, + dfi_5_dbi_byte_disable => dfi_5_dbi_byte_disable, + dfi_5_dw_rddata_valid => dfi_5_dw_rddata_valid, + dfi_5_dw_derr_n => dfi_5_dw_derr_n, + dfi_5_aw_aerr_n => dfi_5_aw_aerr_n, + dfi_5_ctrlupd_req => dfi_5_ctrlupd_req, + dfi_5_phyupd_ack => dfi_5_phyupd_ack, + dfi_5_clk_init => dfi_5_clk_init, + dfi_5_init_complete => dfi_5_init_complete, + dfi_5_out_rst_n => dfi_5_out_rst_n, + dfi_6_dw_rddata_p0 => dfi_6_dw_rddata_p0, + dfi_6_dw_rddata_dm_p0 => dfi_6_dw_rddata_dm_p0, + dfi_6_dw_rddata_dbi_p0 => dfi_6_dw_rddata_dbi_p0, + dfi_6_dw_rddata_par_p0 => dfi_6_dw_rddata_par_p0, + dfi_6_dw_rddata_p1 => dfi_6_dw_rddata_p1, + dfi_6_dw_rddata_dm_p1 => dfi_6_dw_rddata_dm_p1, + dfi_6_dw_rddata_dbi_p1 => dfi_6_dw_rddata_dbi_p1, + dfi_6_dw_rddata_par_p1 => dfi_6_dw_rddata_par_p1, + dfi_6_dbi_byte_disable => dfi_6_dbi_byte_disable, + dfi_6_dw_rddata_valid => dfi_6_dw_rddata_valid, + dfi_6_dw_derr_n => dfi_6_dw_derr_n, + dfi_6_aw_aerr_n => dfi_6_aw_aerr_n, + dfi_6_ctrlupd_req => dfi_6_ctrlupd_req, + dfi_6_phyupd_ack => dfi_6_phyupd_ack, + dfi_6_clk_init => dfi_6_clk_init, + dfi_6_init_complete => dfi_6_init_complete, + dfi_6_out_rst_n => dfi_6_out_rst_n, + dfi_7_dw_rddata_p0 => dfi_7_dw_rddata_p0, + dfi_7_dw_rddata_dm_p0 => dfi_7_dw_rddata_dm_p0, + dfi_7_dw_rddata_dbi_p0 => dfi_7_dw_rddata_dbi_p0, + dfi_7_dw_rddata_par_p0 => dfi_7_dw_rddata_par_p0, + dfi_7_dw_rddata_p1 => dfi_7_dw_rddata_p1, + dfi_7_dw_rddata_dm_p1 => dfi_7_dw_rddata_dm_p1, + dfi_7_dw_rddata_dbi_p1 => dfi_7_dw_rddata_dbi_p1, + dfi_7_dw_rddata_par_p1 => dfi_7_dw_rddata_par_p1, + dfi_7_dbi_byte_disable => dfi_7_dbi_byte_disable, + dfi_7_dw_rddata_valid => dfi_7_dw_rddata_valid, + dfi_7_dw_derr_n => dfi_7_dw_derr_n, + dfi_7_aw_aerr_n => dfi_7_aw_aerr_n, + dfi_7_ctrlupd_req => dfi_7_ctrlupd_req, + dfi_7_phyupd_ack => dfi_7_phyupd_ack, + dfi_7_clk_init => dfi_7_clk_init, + dfi_7_init_complete => dfi_7_init_complete, + dfi_7_out_rst_n => dfi_7_out_rst_n, + dfi_8_dw_rddata_p0 => dfi_8_dw_rddata_p0, + dfi_8_dw_rddata_dm_p0 => dfi_8_dw_rddata_dm_p0, + dfi_8_dw_rddata_dbi_p0 => dfi_8_dw_rddata_dbi_p0, + dfi_8_dw_rddata_par_p0 => dfi_8_dw_rddata_par_p0, + dfi_8_dw_rddata_p1 => dfi_8_dw_rddata_p1, + dfi_8_dw_rddata_dm_p1 => dfi_8_dw_rddata_dm_p1, + dfi_8_dw_rddata_dbi_p1 => dfi_8_dw_rddata_dbi_p1, + dfi_8_dw_rddata_par_p1 => dfi_8_dw_rddata_par_p1, + dfi_8_dbi_byte_disable => dfi_8_dbi_byte_disable, + dfi_8_dw_rddata_valid => dfi_8_dw_rddata_valid, + dfi_8_dw_derr_n => dfi_8_dw_derr_n, + dfi_8_aw_aerr_n => dfi_8_aw_aerr_n, + dfi_8_ctrlupd_req => dfi_8_ctrlupd_req, + dfi_8_phyupd_ack => dfi_8_phyupd_ack, + dfi_8_clk_init => dfi_8_clk_init, + dfi_8_init_complete => dfi_8_init_complete, + dfi_8_out_rst_n => dfi_8_out_rst_n, + dfi_9_dw_rddata_p0 => dfi_9_dw_rddata_p0, + dfi_9_dw_rddata_dm_p0 => dfi_9_dw_rddata_dm_p0, + dfi_9_dw_rddata_dbi_p0 => dfi_9_dw_rddata_dbi_p0, + dfi_9_dw_rddata_par_p0 => dfi_9_dw_rddata_par_p0, + dfi_9_dw_rddata_p1 => dfi_9_dw_rddata_p1, + dfi_9_dw_rddata_dm_p1 => dfi_9_dw_rddata_dm_p1, + dfi_9_dw_rddata_dbi_p1 => dfi_9_dw_rddata_dbi_p1, + dfi_9_dw_rddata_par_p1 => dfi_9_dw_rddata_par_p1, + dfi_9_dbi_byte_disable => dfi_9_dbi_byte_disable, + dfi_9_dw_rddata_valid => dfi_9_dw_rddata_valid, + dfi_9_dw_derr_n => dfi_9_dw_derr_n, + dfi_9_aw_aerr_n => dfi_9_aw_aerr_n, + dfi_9_ctrlupd_req => dfi_9_ctrlupd_req, + dfi_9_phyupd_ack => dfi_9_phyupd_ack, + dfi_9_clk_init => dfi_9_clk_init, + dfi_9_init_complete => dfi_9_init_complete, + dfi_9_out_rst_n => dfi_9_out_rst_n, + dfi_10_dw_rddata_p0 => dfi_10_dw_rddata_p0, + dfi_10_dw_rddata_dm_p0 => dfi_10_dw_rddata_dm_p0, + dfi_10_dw_rddata_dbi_p0 => dfi_10_dw_rddata_dbi_p0, + dfi_10_dw_rddata_par_p0 => dfi_10_dw_rddata_par_p0, + dfi_10_dw_rddata_p1 => dfi_10_dw_rddata_p1, + dfi_10_dw_rddata_dm_p1 => dfi_10_dw_rddata_dm_p1, + dfi_10_dw_rddata_dbi_p1 => dfi_10_dw_rddata_dbi_p1, + dfi_10_dw_rddata_par_p1 => dfi_10_dw_rddata_par_p1, + dfi_10_dbi_byte_disable => dfi_10_dbi_byte_disable, + dfi_10_dw_rddata_valid => dfi_10_dw_rddata_valid, + dfi_10_dw_derr_n => dfi_10_dw_derr_n, + dfi_10_aw_aerr_n => dfi_10_aw_aerr_n, + dfi_10_ctrlupd_req => dfi_10_ctrlupd_req, + dfi_10_phyupd_ack => dfi_10_phyupd_ack, + dfi_10_clk_init => dfi_10_clk_init, + dfi_10_init_complete => dfi_10_init_complete, + dfi_10_out_rst_n => dfi_10_out_rst_n, + dfi_11_dw_rddata_p0 => dfi_11_dw_rddata_p0, + dfi_11_dw_rddata_dm_p0 => dfi_11_dw_rddata_dm_p0, + dfi_11_dw_rddata_dbi_p0 => dfi_11_dw_rddata_dbi_p0, + dfi_11_dw_rddata_par_p0 => dfi_11_dw_rddata_par_p0, + dfi_11_dw_rddata_p1 => dfi_11_dw_rddata_p1, + dfi_11_dw_rddata_dm_p1 => dfi_11_dw_rddata_dm_p1, + dfi_11_dw_rddata_dbi_p1 => dfi_11_dw_rddata_dbi_p1, + dfi_11_dw_rddata_par_p1 => dfi_11_dw_rddata_par_p1, + dfi_11_dbi_byte_disable => dfi_11_dbi_byte_disable, + dfi_11_dw_rddata_valid => dfi_11_dw_rddata_valid, + dfi_11_dw_derr_n => dfi_11_dw_derr_n, + dfi_11_aw_aerr_n => dfi_11_aw_aerr_n, + dfi_11_ctrlupd_req => dfi_11_ctrlupd_req, + dfi_11_phyupd_ack => dfi_11_phyupd_ack, + dfi_11_clk_init => dfi_11_clk_init, + dfi_11_init_complete => dfi_11_init_complete, + dfi_11_out_rst_n => dfi_11_out_rst_n, + dfi_12_dw_rddata_p0 => dfi_12_dw_rddata_p0, + dfi_12_dw_rddata_dm_p0 => dfi_12_dw_rddata_dm_p0, + dfi_12_dw_rddata_dbi_p0 => dfi_12_dw_rddata_dbi_p0, + dfi_12_dw_rddata_par_p0 => dfi_12_dw_rddata_par_p0, + dfi_12_dw_rddata_p1 => dfi_12_dw_rddata_p1, + dfi_12_dw_rddata_dm_p1 => dfi_12_dw_rddata_dm_p1, + dfi_12_dw_rddata_dbi_p1 => dfi_12_dw_rddata_dbi_p1, + dfi_12_dw_rddata_par_p1 => dfi_12_dw_rddata_par_p1, + dfi_12_dbi_byte_disable => dfi_12_dbi_byte_disable, + dfi_12_dw_rddata_valid => dfi_12_dw_rddata_valid, + dfi_12_dw_derr_n => dfi_12_dw_derr_n, + dfi_12_aw_aerr_n => dfi_12_aw_aerr_n, + dfi_12_ctrlupd_req => dfi_12_ctrlupd_req, + dfi_12_phyupd_ack => dfi_12_phyupd_ack, + dfi_12_clk_init => dfi_12_clk_init, + dfi_12_init_complete => dfi_12_init_complete, + dfi_12_out_rst_n => dfi_12_out_rst_n, + dfi_13_dw_rddata_p0 => dfi_13_dw_rddata_p0, + dfi_13_dw_rddata_dm_p0 => dfi_13_dw_rddata_dm_p0, + dfi_13_dw_rddata_dbi_p0 => dfi_13_dw_rddata_dbi_p0, + dfi_13_dw_rddata_par_p0 => dfi_13_dw_rddata_par_p0, + dfi_13_dw_rddata_p1 => dfi_13_dw_rddata_p1, + dfi_13_dw_rddata_dm_p1 => dfi_13_dw_rddata_dm_p1, + dfi_13_dw_rddata_dbi_p1 => dfi_13_dw_rddata_dbi_p1, + dfi_13_dw_rddata_par_p1 => dfi_13_dw_rddata_par_p1, + dfi_13_dbi_byte_disable => dfi_13_dbi_byte_disable, + dfi_13_dw_rddata_valid => dfi_13_dw_rddata_valid, + dfi_13_dw_derr_n => dfi_13_dw_derr_n, + dfi_13_aw_aerr_n => dfi_13_aw_aerr_n, + dfi_13_ctrlupd_req => dfi_13_ctrlupd_req, + dfi_13_phyupd_ack => dfi_13_phyupd_ack, + dfi_13_clk_init => dfi_13_clk_init, + dfi_13_init_complete => dfi_13_init_complete, + dfi_13_out_rst_n => dfi_13_out_rst_n, + dfi_14_dw_rddata_p0 => dfi_14_dw_rddata_p0, + dfi_14_dw_rddata_dm_p0 => dfi_14_dw_rddata_dm_p0, + dfi_14_dw_rddata_dbi_p0 => dfi_14_dw_rddata_dbi_p0, + dfi_14_dw_rddata_par_p0 => dfi_14_dw_rddata_par_p0, + dfi_14_dw_rddata_p1 => dfi_14_dw_rddata_p1, + dfi_14_dw_rddata_dm_p1 => dfi_14_dw_rddata_dm_p1, + dfi_14_dw_rddata_dbi_p1 => dfi_14_dw_rddata_dbi_p1, + dfi_14_dw_rddata_par_p1 => dfi_14_dw_rddata_par_p1, + dfi_14_dbi_byte_disable => dfi_14_dbi_byte_disable, + dfi_14_dw_rddata_valid => dfi_14_dw_rddata_valid, + dfi_14_dw_derr_n => dfi_14_dw_derr_n, + dfi_14_aw_aerr_n => dfi_14_aw_aerr_n, + dfi_14_ctrlupd_req => dfi_14_ctrlupd_req, + dfi_14_phyupd_ack => dfi_14_phyupd_ack, + dfi_14_clk_init => dfi_14_clk_init, + dfi_14_init_complete => dfi_14_init_complete, + dfi_14_out_rst_n => dfi_14_out_rst_n, + dfi_15_dw_rddata_p0 => dfi_15_dw_rddata_p0, + dfi_15_dw_rddata_dm_p0 => dfi_15_dw_rddata_dm_p0, + dfi_15_dw_rddata_dbi_p0 => dfi_15_dw_rddata_dbi_p0, + dfi_15_dw_rddata_par_p0 => dfi_15_dw_rddata_par_p0, + dfi_15_dw_rddata_p1 => dfi_15_dw_rddata_p1, + dfi_15_dw_rddata_dm_p1 => dfi_15_dw_rddata_dm_p1, + dfi_15_dw_rddata_dbi_p1 => dfi_15_dw_rddata_dbi_p1, + dfi_15_dw_rddata_par_p1 => dfi_15_dw_rddata_par_p1, + dfi_15_dbi_byte_disable => dfi_15_dbi_byte_disable, + dfi_15_dw_rddata_valid => dfi_15_dw_rddata_valid, + dfi_15_dw_derr_n => dfi_15_dw_derr_n, + dfi_15_aw_aerr_n => dfi_15_aw_aerr_n, + dfi_15_ctrlupd_req => dfi_15_ctrlupd_req, + dfi_15_phyupd_ack => dfi_15_phyupd_ack, + dfi_15_clk_init => dfi_15_clk_init, + dfi_15_init_complete => dfi_15_init_complete, + dfi_15_out_rst_n => dfi_15_out_rst_n, + apb_complete_0 => apb_complete_0, + apb_complete_1 => apb_complete_1, + DRAM_0_STAT_CATTRIP => DRAM_0_STAT_CATTRIP, + DRAM_0_STAT_TEMP => DRAM_0_STAT_TEMP, + DRAM_1_STAT_CATTRIP => DRAM_1_STAT_CATTRIP, + DRAM_1_STAT_TEMP => DRAM_1_STAT_TEMP + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file hbm_0.vhd when simulating +-- the core, hbm_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.v new file mode 100644 index 0000000..7463743 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.v @@ -0,0 +1,1070 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:36:26 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/hbm_0/hbm_0_stub.v +// Design : hbm_0 +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "hbm_v1_0_9,Vivado 2020.2" *) +module hbm_0(HBM_REF_CLK_0, HBM_REF_CLK_1, dfi_0_clk, + dfi_0_rst_n, dfi_0_init_start, dfi_0_aw_ck_p0, dfi_0_aw_cke_p0, dfi_0_aw_row_p0, + dfi_0_aw_col_p0, dfi_0_dw_wrdata_p0, dfi_0_dw_wrdata_mask_p0, dfi_0_dw_wrdata_dbi_p0, + dfi_0_dw_wrdata_par_p0, dfi_0_dw_wrdata_dq_en_p0, dfi_0_dw_wrdata_par_en_p0, + dfi_0_aw_ck_p1, dfi_0_aw_cke_p1, dfi_0_aw_row_p1, dfi_0_aw_col_p1, dfi_0_dw_wrdata_p1, + dfi_0_dw_wrdata_mask_p1, dfi_0_dw_wrdata_dbi_p1, dfi_0_dw_wrdata_par_p1, + dfi_0_dw_wrdata_dq_en_p1, dfi_0_dw_wrdata_par_en_p1, dfi_0_aw_ck_dis, + dfi_0_lp_pwr_e_req, dfi_0_lp_sr_e_req, dfi_0_lp_pwr_x_req, dfi_0_aw_tx_indx_ld, + dfi_0_dw_tx_indx_ld, dfi_0_dw_rx_indx_ld, dfi_0_ctrlupd_ack, dfi_0_phyupd_req, + dfi_0_dw_wrdata_dqs_p0, dfi_0_dw_wrdata_dqs_p1, dfi_1_clk, dfi_1_rst_n, dfi_1_init_start, + dfi_1_aw_ck_p0, dfi_1_aw_cke_p0, dfi_1_aw_row_p0, dfi_1_aw_col_p0, dfi_1_dw_wrdata_p0, + dfi_1_dw_wrdata_mask_p0, dfi_1_dw_wrdata_dbi_p0, dfi_1_dw_wrdata_par_p0, + dfi_1_dw_wrdata_dq_en_p0, dfi_1_dw_wrdata_par_en_p0, dfi_1_aw_ck_p1, dfi_1_aw_cke_p1, + dfi_1_aw_row_p1, dfi_1_aw_col_p1, dfi_1_dw_wrdata_p1, dfi_1_dw_wrdata_mask_p1, + dfi_1_dw_wrdata_dbi_p1, dfi_1_dw_wrdata_par_p1, dfi_1_dw_wrdata_dq_en_p1, + dfi_1_dw_wrdata_par_en_p1, dfi_1_aw_ck_dis, dfi_1_lp_pwr_e_req, dfi_1_lp_sr_e_req, + dfi_1_lp_pwr_x_req, dfi_1_aw_tx_indx_ld, dfi_1_dw_tx_indx_ld, dfi_1_dw_rx_indx_ld, + dfi_1_ctrlupd_ack, dfi_1_phyupd_req, dfi_1_dw_wrdata_dqs_p0, dfi_1_dw_wrdata_dqs_p1, + dfi_2_clk, dfi_2_rst_n, dfi_2_init_start, dfi_2_aw_ck_p0, dfi_2_aw_cke_p0, dfi_2_aw_row_p0, + dfi_2_aw_col_p0, dfi_2_dw_wrdata_p0, dfi_2_dw_wrdata_mask_p0, dfi_2_dw_wrdata_dbi_p0, + dfi_2_dw_wrdata_par_p0, dfi_2_dw_wrdata_dq_en_p0, dfi_2_dw_wrdata_par_en_p0, + dfi_2_aw_ck_p1, dfi_2_aw_cke_p1, dfi_2_aw_row_p1, dfi_2_aw_col_p1, dfi_2_dw_wrdata_p1, + dfi_2_dw_wrdata_mask_p1, dfi_2_dw_wrdata_dbi_p1, dfi_2_dw_wrdata_par_p1, + dfi_2_dw_wrdata_dq_en_p1, dfi_2_dw_wrdata_par_en_p1, dfi_2_aw_ck_dis, + dfi_2_lp_pwr_e_req, dfi_2_lp_sr_e_req, dfi_2_lp_pwr_x_req, dfi_2_aw_tx_indx_ld, + dfi_2_dw_tx_indx_ld, dfi_2_dw_rx_indx_ld, dfi_2_ctrlupd_ack, dfi_2_phyupd_req, + dfi_2_dw_wrdata_dqs_p0, dfi_2_dw_wrdata_dqs_p1, dfi_3_clk, dfi_3_rst_n, dfi_3_init_start, + dfi_3_aw_ck_p0, dfi_3_aw_cke_p0, dfi_3_aw_row_p0, dfi_3_aw_col_p0, dfi_3_dw_wrdata_p0, + dfi_3_dw_wrdata_mask_p0, dfi_3_dw_wrdata_dbi_p0, dfi_3_dw_wrdata_par_p0, + dfi_3_dw_wrdata_dq_en_p0, dfi_3_dw_wrdata_par_en_p0, dfi_3_aw_ck_p1, dfi_3_aw_cke_p1, + dfi_3_aw_row_p1, dfi_3_aw_col_p1, dfi_3_dw_wrdata_p1, dfi_3_dw_wrdata_mask_p1, + dfi_3_dw_wrdata_dbi_p1, dfi_3_dw_wrdata_par_p1, dfi_3_dw_wrdata_dq_en_p1, + dfi_3_dw_wrdata_par_en_p1, dfi_3_aw_ck_dis, dfi_3_lp_pwr_e_req, dfi_3_lp_sr_e_req, + dfi_3_lp_pwr_x_req, dfi_3_aw_tx_indx_ld, dfi_3_dw_tx_indx_ld, dfi_3_dw_rx_indx_ld, + dfi_3_ctrlupd_ack, dfi_3_phyupd_req, dfi_3_dw_wrdata_dqs_p0, dfi_3_dw_wrdata_dqs_p1, + dfi_4_clk, dfi_4_rst_n, dfi_4_init_start, dfi_4_aw_ck_p0, dfi_4_aw_cke_p0, dfi_4_aw_row_p0, + dfi_4_aw_col_p0, dfi_4_dw_wrdata_p0, dfi_4_dw_wrdata_mask_p0, dfi_4_dw_wrdata_dbi_p0, + dfi_4_dw_wrdata_par_p0, dfi_4_dw_wrdata_dq_en_p0, dfi_4_dw_wrdata_par_en_p0, + dfi_4_aw_ck_p1, dfi_4_aw_cke_p1, dfi_4_aw_row_p1, dfi_4_aw_col_p1, dfi_4_dw_wrdata_p1, + dfi_4_dw_wrdata_mask_p1, dfi_4_dw_wrdata_dbi_p1, dfi_4_dw_wrdata_par_p1, + dfi_4_dw_wrdata_dq_en_p1, dfi_4_dw_wrdata_par_en_p1, dfi_4_aw_ck_dis, + dfi_4_lp_pwr_e_req, dfi_4_lp_sr_e_req, dfi_4_lp_pwr_x_req, dfi_4_aw_tx_indx_ld, + dfi_4_dw_tx_indx_ld, dfi_4_dw_rx_indx_ld, dfi_4_ctrlupd_ack, dfi_4_phyupd_req, + dfi_4_dw_wrdata_dqs_p0, dfi_4_dw_wrdata_dqs_p1, dfi_5_clk, dfi_5_rst_n, dfi_5_init_start, + dfi_5_aw_ck_p0, dfi_5_aw_cke_p0, dfi_5_aw_row_p0, dfi_5_aw_col_p0, dfi_5_dw_wrdata_p0, + dfi_5_dw_wrdata_mask_p0, dfi_5_dw_wrdata_dbi_p0, dfi_5_dw_wrdata_par_p0, + dfi_5_dw_wrdata_dq_en_p0, dfi_5_dw_wrdata_par_en_p0, dfi_5_aw_ck_p1, dfi_5_aw_cke_p1, + dfi_5_aw_row_p1, dfi_5_aw_col_p1, dfi_5_dw_wrdata_p1, dfi_5_dw_wrdata_mask_p1, + dfi_5_dw_wrdata_dbi_p1, dfi_5_dw_wrdata_par_p1, dfi_5_dw_wrdata_dq_en_p1, + dfi_5_dw_wrdata_par_en_p1, dfi_5_aw_ck_dis, dfi_5_lp_pwr_e_req, dfi_5_lp_sr_e_req, + dfi_5_lp_pwr_x_req, dfi_5_aw_tx_indx_ld, dfi_5_dw_tx_indx_ld, dfi_5_dw_rx_indx_ld, + dfi_5_ctrlupd_ack, dfi_5_phyupd_req, dfi_5_dw_wrdata_dqs_p0, dfi_5_dw_wrdata_dqs_p1, + dfi_6_clk, dfi_6_rst_n, dfi_6_init_start, dfi_6_aw_ck_p0, dfi_6_aw_cke_p0, dfi_6_aw_row_p0, + dfi_6_aw_col_p0, dfi_6_dw_wrdata_p0, dfi_6_dw_wrdata_mask_p0, dfi_6_dw_wrdata_dbi_p0, + dfi_6_dw_wrdata_par_p0, dfi_6_dw_wrdata_dq_en_p0, dfi_6_dw_wrdata_par_en_p0, + dfi_6_aw_ck_p1, dfi_6_aw_cke_p1, dfi_6_aw_row_p1, dfi_6_aw_col_p1, dfi_6_dw_wrdata_p1, + dfi_6_dw_wrdata_mask_p1, dfi_6_dw_wrdata_dbi_p1, dfi_6_dw_wrdata_par_p1, + dfi_6_dw_wrdata_dq_en_p1, dfi_6_dw_wrdata_par_en_p1, dfi_6_aw_ck_dis, + dfi_6_lp_pwr_e_req, dfi_6_lp_sr_e_req, dfi_6_lp_pwr_x_req, dfi_6_aw_tx_indx_ld, + dfi_6_dw_tx_indx_ld, dfi_6_dw_rx_indx_ld, dfi_6_ctrlupd_ack, dfi_6_phyupd_req, + dfi_6_dw_wrdata_dqs_p0, dfi_6_dw_wrdata_dqs_p1, dfi_7_clk, dfi_7_rst_n, dfi_7_init_start, + dfi_7_aw_ck_p0, dfi_7_aw_cke_p0, dfi_7_aw_row_p0, dfi_7_aw_col_p0, dfi_7_dw_wrdata_p0, + dfi_7_dw_wrdata_mask_p0, dfi_7_dw_wrdata_dbi_p0, dfi_7_dw_wrdata_par_p0, + dfi_7_dw_wrdata_dq_en_p0, dfi_7_dw_wrdata_par_en_p0, dfi_7_aw_ck_p1, dfi_7_aw_cke_p1, + dfi_7_aw_row_p1, dfi_7_aw_col_p1, dfi_7_dw_wrdata_p1, dfi_7_dw_wrdata_mask_p1, + dfi_7_dw_wrdata_dbi_p1, dfi_7_dw_wrdata_par_p1, dfi_7_dw_wrdata_dq_en_p1, + dfi_7_dw_wrdata_par_en_p1, dfi_7_aw_ck_dis, dfi_7_lp_pwr_e_req, dfi_7_lp_sr_e_req, + dfi_7_lp_pwr_x_req, dfi_7_aw_tx_indx_ld, dfi_7_dw_tx_indx_ld, dfi_7_dw_rx_indx_ld, + dfi_7_ctrlupd_ack, dfi_7_phyupd_req, dfi_7_dw_wrdata_dqs_p0, dfi_7_dw_wrdata_dqs_p1, + dfi_8_clk, dfi_8_rst_n, dfi_8_init_start, dfi_8_aw_ck_p0, dfi_8_aw_cke_p0, dfi_8_aw_row_p0, + dfi_8_aw_col_p0, dfi_8_dw_wrdata_p0, dfi_8_dw_wrdata_mask_p0, dfi_8_dw_wrdata_dbi_p0, + dfi_8_dw_wrdata_par_p0, dfi_8_dw_wrdata_dq_en_p0, dfi_8_dw_wrdata_par_en_p0, + dfi_8_aw_ck_p1, dfi_8_aw_cke_p1, dfi_8_aw_row_p1, dfi_8_aw_col_p1, dfi_8_dw_wrdata_p1, + dfi_8_dw_wrdata_mask_p1, dfi_8_dw_wrdata_dbi_p1, dfi_8_dw_wrdata_par_p1, + dfi_8_dw_wrdata_dq_en_p1, dfi_8_dw_wrdata_par_en_p1, dfi_8_aw_ck_dis, + dfi_8_lp_pwr_e_req, dfi_8_lp_sr_e_req, dfi_8_lp_pwr_x_req, dfi_8_aw_tx_indx_ld, + dfi_8_dw_tx_indx_ld, dfi_8_dw_rx_indx_ld, dfi_8_ctrlupd_ack, dfi_8_phyupd_req, + dfi_8_dw_wrdata_dqs_p0, dfi_8_dw_wrdata_dqs_p1, dfi_9_clk, dfi_9_rst_n, dfi_9_init_start, + dfi_9_aw_ck_p0, dfi_9_aw_cke_p0, dfi_9_aw_row_p0, dfi_9_aw_col_p0, dfi_9_dw_wrdata_p0, + dfi_9_dw_wrdata_mask_p0, dfi_9_dw_wrdata_dbi_p0, dfi_9_dw_wrdata_par_p0, + dfi_9_dw_wrdata_dq_en_p0, dfi_9_dw_wrdata_par_en_p0, dfi_9_aw_ck_p1, dfi_9_aw_cke_p1, + dfi_9_aw_row_p1, dfi_9_aw_col_p1, dfi_9_dw_wrdata_p1, dfi_9_dw_wrdata_mask_p1, + dfi_9_dw_wrdata_dbi_p1, dfi_9_dw_wrdata_par_p1, dfi_9_dw_wrdata_dq_en_p1, + dfi_9_dw_wrdata_par_en_p1, dfi_9_aw_ck_dis, dfi_9_lp_pwr_e_req, dfi_9_lp_sr_e_req, + dfi_9_lp_pwr_x_req, dfi_9_aw_tx_indx_ld, dfi_9_dw_tx_indx_ld, dfi_9_dw_rx_indx_ld, + dfi_9_ctrlupd_ack, dfi_9_phyupd_req, dfi_9_dw_wrdata_dqs_p0, dfi_9_dw_wrdata_dqs_p1, + dfi_10_clk, dfi_10_rst_n, dfi_10_init_start, dfi_10_aw_ck_p0, dfi_10_aw_cke_p0, + dfi_10_aw_row_p0, dfi_10_aw_col_p0, dfi_10_dw_wrdata_p0, dfi_10_dw_wrdata_mask_p0, + dfi_10_dw_wrdata_dbi_p0, dfi_10_dw_wrdata_par_p0, dfi_10_dw_wrdata_dq_en_p0, + dfi_10_dw_wrdata_par_en_p0, dfi_10_aw_ck_p1, dfi_10_aw_cke_p1, dfi_10_aw_row_p1, + dfi_10_aw_col_p1, dfi_10_dw_wrdata_p1, dfi_10_dw_wrdata_mask_p1, + dfi_10_dw_wrdata_dbi_p1, dfi_10_dw_wrdata_par_p1, dfi_10_dw_wrdata_dq_en_p1, + dfi_10_dw_wrdata_par_en_p1, dfi_10_aw_ck_dis, dfi_10_lp_pwr_e_req, dfi_10_lp_sr_e_req, + dfi_10_lp_pwr_x_req, dfi_10_aw_tx_indx_ld, dfi_10_dw_tx_indx_ld, dfi_10_dw_rx_indx_ld, + dfi_10_ctrlupd_ack, dfi_10_phyupd_req, dfi_10_dw_wrdata_dqs_p0, + dfi_10_dw_wrdata_dqs_p1, dfi_11_clk, dfi_11_rst_n, dfi_11_init_start, dfi_11_aw_ck_p0, + dfi_11_aw_cke_p0, dfi_11_aw_row_p0, dfi_11_aw_col_p0, dfi_11_dw_wrdata_p0, + dfi_11_dw_wrdata_mask_p0, dfi_11_dw_wrdata_dbi_p0, dfi_11_dw_wrdata_par_p0, + dfi_11_dw_wrdata_dq_en_p0, dfi_11_dw_wrdata_par_en_p0, dfi_11_aw_ck_p1, + dfi_11_aw_cke_p1, dfi_11_aw_row_p1, dfi_11_aw_col_p1, dfi_11_dw_wrdata_p1, + dfi_11_dw_wrdata_mask_p1, dfi_11_dw_wrdata_dbi_p1, dfi_11_dw_wrdata_par_p1, + dfi_11_dw_wrdata_dq_en_p1, dfi_11_dw_wrdata_par_en_p1, dfi_11_aw_ck_dis, + dfi_11_lp_pwr_e_req, dfi_11_lp_sr_e_req, dfi_11_lp_pwr_x_req, dfi_11_aw_tx_indx_ld, + dfi_11_dw_tx_indx_ld, dfi_11_dw_rx_indx_ld, dfi_11_ctrlupd_ack, dfi_11_phyupd_req, + dfi_11_dw_wrdata_dqs_p0, dfi_11_dw_wrdata_dqs_p1, dfi_12_clk, dfi_12_rst_n, + dfi_12_init_start, dfi_12_aw_ck_p0, dfi_12_aw_cke_p0, dfi_12_aw_row_p0, dfi_12_aw_col_p0, + dfi_12_dw_wrdata_p0, dfi_12_dw_wrdata_mask_p0, dfi_12_dw_wrdata_dbi_p0, + dfi_12_dw_wrdata_par_p0, dfi_12_dw_wrdata_dq_en_p0, dfi_12_dw_wrdata_par_en_p0, + dfi_12_aw_ck_p1, dfi_12_aw_cke_p1, dfi_12_aw_row_p1, dfi_12_aw_col_p1, + dfi_12_dw_wrdata_p1, dfi_12_dw_wrdata_mask_p1, dfi_12_dw_wrdata_dbi_p1, + dfi_12_dw_wrdata_par_p1, dfi_12_dw_wrdata_dq_en_p1, dfi_12_dw_wrdata_par_en_p1, + dfi_12_aw_ck_dis, dfi_12_lp_pwr_e_req, dfi_12_lp_sr_e_req, dfi_12_lp_pwr_x_req, + dfi_12_aw_tx_indx_ld, dfi_12_dw_tx_indx_ld, dfi_12_dw_rx_indx_ld, dfi_12_ctrlupd_ack, + dfi_12_phyupd_req, dfi_12_dw_wrdata_dqs_p0, dfi_12_dw_wrdata_dqs_p1, dfi_13_clk, + dfi_13_rst_n, dfi_13_init_start, dfi_13_aw_ck_p0, dfi_13_aw_cke_p0, dfi_13_aw_row_p0, + dfi_13_aw_col_p0, dfi_13_dw_wrdata_p0, dfi_13_dw_wrdata_mask_p0, + dfi_13_dw_wrdata_dbi_p0, dfi_13_dw_wrdata_par_p0, dfi_13_dw_wrdata_dq_en_p0, + dfi_13_dw_wrdata_par_en_p0, dfi_13_aw_ck_p1, dfi_13_aw_cke_p1, dfi_13_aw_row_p1, + dfi_13_aw_col_p1, dfi_13_dw_wrdata_p1, dfi_13_dw_wrdata_mask_p1, + dfi_13_dw_wrdata_dbi_p1, dfi_13_dw_wrdata_par_p1, dfi_13_dw_wrdata_dq_en_p1, + dfi_13_dw_wrdata_par_en_p1, dfi_13_aw_ck_dis, dfi_13_lp_pwr_e_req, dfi_13_lp_sr_e_req, + dfi_13_lp_pwr_x_req, dfi_13_aw_tx_indx_ld, dfi_13_dw_tx_indx_ld, dfi_13_dw_rx_indx_ld, + dfi_13_ctrlupd_ack, dfi_13_phyupd_req, dfi_13_dw_wrdata_dqs_p0, + dfi_13_dw_wrdata_dqs_p1, dfi_14_clk, dfi_14_rst_n, dfi_14_init_start, dfi_14_aw_ck_p0, + dfi_14_aw_cke_p0, dfi_14_aw_row_p0, dfi_14_aw_col_p0, dfi_14_dw_wrdata_p0, + dfi_14_dw_wrdata_mask_p0, dfi_14_dw_wrdata_dbi_p0, dfi_14_dw_wrdata_par_p0, + dfi_14_dw_wrdata_dq_en_p0, dfi_14_dw_wrdata_par_en_p0, dfi_14_aw_ck_p1, + dfi_14_aw_cke_p1, dfi_14_aw_row_p1, dfi_14_aw_col_p1, dfi_14_dw_wrdata_p1, + dfi_14_dw_wrdata_mask_p1, dfi_14_dw_wrdata_dbi_p1, dfi_14_dw_wrdata_par_p1, + dfi_14_dw_wrdata_dq_en_p1, dfi_14_dw_wrdata_par_en_p1, dfi_14_aw_ck_dis, + dfi_14_lp_pwr_e_req, dfi_14_lp_sr_e_req, dfi_14_lp_pwr_x_req, dfi_14_aw_tx_indx_ld, + dfi_14_dw_tx_indx_ld, dfi_14_dw_rx_indx_ld, dfi_14_ctrlupd_ack, dfi_14_phyupd_req, + dfi_14_dw_wrdata_dqs_p0, dfi_14_dw_wrdata_dqs_p1, dfi_15_clk, dfi_15_rst_n, + dfi_15_init_start, dfi_15_aw_ck_p0, dfi_15_aw_cke_p0, dfi_15_aw_row_p0, dfi_15_aw_col_p0, + dfi_15_dw_wrdata_p0, dfi_15_dw_wrdata_mask_p0, dfi_15_dw_wrdata_dbi_p0, + dfi_15_dw_wrdata_par_p0, dfi_15_dw_wrdata_dq_en_p0, dfi_15_dw_wrdata_par_en_p0, + dfi_15_aw_ck_p1, dfi_15_aw_cke_p1, dfi_15_aw_row_p1, dfi_15_aw_col_p1, + dfi_15_dw_wrdata_p1, dfi_15_dw_wrdata_mask_p1, dfi_15_dw_wrdata_dbi_p1, + dfi_15_dw_wrdata_par_p1, dfi_15_dw_wrdata_dq_en_p1, dfi_15_dw_wrdata_par_en_p1, + dfi_15_aw_ck_dis, dfi_15_lp_pwr_e_req, dfi_15_lp_sr_e_req, dfi_15_lp_pwr_x_req, + dfi_15_aw_tx_indx_ld, dfi_15_dw_tx_indx_ld, dfi_15_dw_rx_indx_ld, dfi_15_ctrlupd_ack, + dfi_15_phyupd_req, dfi_15_dw_wrdata_dqs_p0, dfi_15_dw_wrdata_dqs_p1, APB_0_PCLK, + APB_0_PRESET_N, APB_1_PCLK, APB_1_PRESET_N, dfi_0_dw_rddata_p0, dfi_0_dw_rddata_dm_p0, + dfi_0_dw_rddata_dbi_p0, dfi_0_dw_rddata_par_p0, dfi_0_dw_rddata_p1, + dfi_0_dw_rddata_dm_p1, dfi_0_dw_rddata_dbi_p1, dfi_0_dw_rddata_par_p1, + dfi_0_dbi_byte_disable, dfi_0_dw_rddata_valid, dfi_0_dw_derr_n, dfi_0_aw_aerr_n, + dfi_0_ctrlupd_req, dfi_0_phyupd_ack, dfi_0_clk_init, dfi_0_init_complete, + dfi_0_out_rst_n, dfi_1_dw_rddata_p0, dfi_1_dw_rddata_dm_p0, dfi_1_dw_rddata_dbi_p0, + dfi_1_dw_rddata_par_p0, dfi_1_dw_rddata_p1, dfi_1_dw_rddata_dm_p1, + dfi_1_dw_rddata_dbi_p1, dfi_1_dw_rddata_par_p1, dfi_1_dbi_byte_disable, + dfi_1_dw_rddata_valid, dfi_1_dw_derr_n, dfi_1_aw_aerr_n, dfi_1_ctrlupd_req, + dfi_1_phyupd_ack, dfi_1_clk_init, dfi_1_init_complete, dfi_1_out_rst_n, + dfi_2_dw_rddata_p0, dfi_2_dw_rddata_dm_p0, dfi_2_dw_rddata_dbi_p0, + dfi_2_dw_rddata_par_p0, dfi_2_dw_rddata_p1, dfi_2_dw_rddata_dm_p1, + dfi_2_dw_rddata_dbi_p1, dfi_2_dw_rddata_par_p1, dfi_2_dbi_byte_disable, + dfi_2_dw_rddata_valid, dfi_2_dw_derr_n, dfi_2_aw_aerr_n, dfi_2_ctrlupd_req, + dfi_2_phyupd_ack, dfi_2_clk_init, dfi_2_init_complete, dfi_2_out_rst_n, + dfi_3_dw_rddata_p0, dfi_3_dw_rddata_dm_p0, dfi_3_dw_rddata_dbi_p0, + dfi_3_dw_rddata_par_p0, dfi_3_dw_rddata_p1, dfi_3_dw_rddata_dm_p1, + dfi_3_dw_rddata_dbi_p1, dfi_3_dw_rddata_par_p1, dfi_3_dbi_byte_disable, + dfi_3_dw_rddata_valid, dfi_3_dw_derr_n, dfi_3_aw_aerr_n, dfi_3_ctrlupd_req, + dfi_3_phyupd_ack, dfi_3_clk_init, dfi_3_init_complete, dfi_3_out_rst_n, + dfi_4_dw_rddata_p0, dfi_4_dw_rddata_dm_p0, dfi_4_dw_rddata_dbi_p0, + dfi_4_dw_rddata_par_p0, dfi_4_dw_rddata_p1, dfi_4_dw_rddata_dm_p1, + dfi_4_dw_rddata_dbi_p1, dfi_4_dw_rddata_par_p1, dfi_4_dbi_byte_disable, + dfi_4_dw_rddata_valid, dfi_4_dw_derr_n, dfi_4_aw_aerr_n, dfi_4_ctrlupd_req, + dfi_4_phyupd_ack, dfi_4_clk_init, dfi_4_init_complete, dfi_4_out_rst_n, + dfi_5_dw_rddata_p0, dfi_5_dw_rddata_dm_p0, dfi_5_dw_rddata_dbi_p0, + dfi_5_dw_rddata_par_p0, dfi_5_dw_rddata_p1, dfi_5_dw_rddata_dm_p1, + dfi_5_dw_rddata_dbi_p1, dfi_5_dw_rddata_par_p1, dfi_5_dbi_byte_disable, + dfi_5_dw_rddata_valid, dfi_5_dw_derr_n, dfi_5_aw_aerr_n, dfi_5_ctrlupd_req, + dfi_5_phyupd_ack, dfi_5_clk_init, dfi_5_init_complete, dfi_5_out_rst_n, + dfi_6_dw_rddata_p0, dfi_6_dw_rddata_dm_p0, dfi_6_dw_rddata_dbi_p0, + dfi_6_dw_rddata_par_p0, dfi_6_dw_rddata_p1, dfi_6_dw_rddata_dm_p1, + dfi_6_dw_rddata_dbi_p1, dfi_6_dw_rddata_par_p1, dfi_6_dbi_byte_disable, + dfi_6_dw_rddata_valid, dfi_6_dw_derr_n, dfi_6_aw_aerr_n, dfi_6_ctrlupd_req, + dfi_6_phyupd_ack, dfi_6_clk_init, dfi_6_init_complete, dfi_6_out_rst_n, + dfi_7_dw_rddata_p0, dfi_7_dw_rddata_dm_p0, dfi_7_dw_rddata_dbi_p0, + dfi_7_dw_rddata_par_p0, dfi_7_dw_rddata_p1, dfi_7_dw_rddata_dm_p1, + dfi_7_dw_rddata_dbi_p1, dfi_7_dw_rddata_par_p1, dfi_7_dbi_byte_disable, + dfi_7_dw_rddata_valid, dfi_7_dw_derr_n, dfi_7_aw_aerr_n, dfi_7_ctrlupd_req, + dfi_7_phyupd_ack, dfi_7_clk_init, dfi_7_init_complete, dfi_7_out_rst_n, + dfi_8_dw_rddata_p0, dfi_8_dw_rddata_dm_p0, dfi_8_dw_rddata_dbi_p0, + dfi_8_dw_rddata_par_p0, dfi_8_dw_rddata_p1, dfi_8_dw_rddata_dm_p1, + dfi_8_dw_rddata_dbi_p1, dfi_8_dw_rddata_par_p1, dfi_8_dbi_byte_disable, + dfi_8_dw_rddata_valid, dfi_8_dw_derr_n, dfi_8_aw_aerr_n, dfi_8_ctrlupd_req, + dfi_8_phyupd_ack, dfi_8_clk_init, dfi_8_init_complete, dfi_8_out_rst_n, + dfi_9_dw_rddata_p0, dfi_9_dw_rddata_dm_p0, dfi_9_dw_rddata_dbi_p0, + dfi_9_dw_rddata_par_p0, dfi_9_dw_rddata_p1, dfi_9_dw_rddata_dm_p1, + dfi_9_dw_rddata_dbi_p1, dfi_9_dw_rddata_par_p1, dfi_9_dbi_byte_disable, + dfi_9_dw_rddata_valid, dfi_9_dw_derr_n, dfi_9_aw_aerr_n, dfi_9_ctrlupd_req, + dfi_9_phyupd_ack, dfi_9_clk_init, dfi_9_init_complete, dfi_9_out_rst_n, + dfi_10_dw_rddata_p0, dfi_10_dw_rddata_dm_p0, dfi_10_dw_rddata_dbi_p0, + dfi_10_dw_rddata_par_p0, dfi_10_dw_rddata_p1, dfi_10_dw_rddata_dm_p1, + dfi_10_dw_rddata_dbi_p1, dfi_10_dw_rddata_par_p1, dfi_10_dbi_byte_disable, + dfi_10_dw_rddata_valid, dfi_10_dw_derr_n, dfi_10_aw_aerr_n, dfi_10_ctrlupd_req, + dfi_10_phyupd_ack, dfi_10_clk_init, dfi_10_init_complete, dfi_10_out_rst_n, + dfi_11_dw_rddata_p0, dfi_11_dw_rddata_dm_p0, dfi_11_dw_rddata_dbi_p0, + dfi_11_dw_rddata_par_p0, dfi_11_dw_rddata_p1, dfi_11_dw_rddata_dm_p1, + dfi_11_dw_rddata_dbi_p1, dfi_11_dw_rddata_par_p1, dfi_11_dbi_byte_disable, + dfi_11_dw_rddata_valid, dfi_11_dw_derr_n, dfi_11_aw_aerr_n, dfi_11_ctrlupd_req, + dfi_11_phyupd_ack, dfi_11_clk_init, dfi_11_init_complete, dfi_11_out_rst_n, + dfi_12_dw_rddata_p0, dfi_12_dw_rddata_dm_p0, dfi_12_dw_rddata_dbi_p0, + dfi_12_dw_rddata_par_p0, dfi_12_dw_rddata_p1, dfi_12_dw_rddata_dm_p1, + dfi_12_dw_rddata_dbi_p1, dfi_12_dw_rddata_par_p1, dfi_12_dbi_byte_disable, + dfi_12_dw_rddata_valid, dfi_12_dw_derr_n, dfi_12_aw_aerr_n, dfi_12_ctrlupd_req, + dfi_12_phyupd_ack, dfi_12_clk_init, dfi_12_init_complete, dfi_12_out_rst_n, + dfi_13_dw_rddata_p0, dfi_13_dw_rddata_dm_p0, dfi_13_dw_rddata_dbi_p0, + dfi_13_dw_rddata_par_p0, dfi_13_dw_rddata_p1, dfi_13_dw_rddata_dm_p1, + dfi_13_dw_rddata_dbi_p1, dfi_13_dw_rddata_par_p1, dfi_13_dbi_byte_disable, + dfi_13_dw_rddata_valid, dfi_13_dw_derr_n, dfi_13_aw_aerr_n, dfi_13_ctrlupd_req, + dfi_13_phyupd_ack, dfi_13_clk_init, dfi_13_init_complete, dfi_13_out_rst_n, + dfi_14_dw_rddata_p0, dfi_14_dw_rddata_dm_p0, dfi_14_dw_rddata_dbi_p0, + dfi_14_dw_rddata_par_p0, dfi_14_dw_rddata_p1, dfi_14_dw_rddata_dm_p1, + dfi_14_dw_rddata_dbi_p1, dfi_14_dw_rddata_par_p1, dfi_14_dbi_byte_disable, + dfi_14_dw_rddata_valid, dfi_14_dw_derr_n, dfi_14_aw_aerr_n, dfi_14_ctrlupd_req, + dfi_14_phyupd_ack, dfi_14_clk_init, dfi_14_init_complete, dfi_14_out_rst_n, + dfi_15_dw_rddata_p0, dfi_15_dw_rddata_dm_p0, dfi_15_dw_rddata_dbi_p0, + dfi_15_dw_rddata_par_p0, dfi_15_dw_rddata_p1, dfi_15_dw_rddata_dm_p1, + dfi_15_dw_rddata_dbi_p1, dfi_15_dw_rddata_par_p1, dfi_15_dbi_byte_disable, + dfi_15_dw_rddata_valid, dfi_15_dw_derr_n, dfi_15_aw_aerr_n, dfi_15_ctrlupd_req, + dfi_15_phyupd_ack, dfi_15_clk_init, dfi_15_init_complete, dfi_15_out_rst_n, + apb_complete_0, apb_complete_1, DRAM_0_STAT_CATTRIP, DRAM_0_STAT_TEMP, + DRAM_1_STAT_CATTRIP, DRAM_1_STAT_TEMP) +/* synthesis syn_black_box black_box_pad_pin="HBM_REF_CLK_0,HBM_REF_CLK_1,dfi_0_clk,dfi_0_rst_n,dfi_0_init_start,dfi_0_aw_ck_p0[1:0],dfi_0_aw_cke_p0[1:0],dfi_0_aw_row_p0[11:0],dfi_0_aw_col_p0[15:0],dfi_0_dw_wrdata_p0[255:0],dfi_0_dw_wrdata_mask_p0[31:0],dfi_0_dw_wrdata_dbi_p0[31:0],dfi_0_dw_wrdata_par_p0[7:0],dfi_0_dw_wrdata_dq_en_p0[7:0],dfi_0_dw_wrdata_par_en_p0[7:0],dfi_0_aw_ck_p1[1:0],dfi_0_aw_cke_p1[1:0],dfi_0_aw_row_p1[11:0],dfi_0_aw_col_p1[15:0],dfi_0_dw_wrdata_p1[255:0],dfi_0_dw_wrdata_mask_p1[31:0],dfi_0_dw_wrdata_dbi_p1[31:0],dfi_0_dw_wrdata_par_p1[7:0],dfi_0_dw_wrdata_dq_en_p1[7:0],dfi_0_dw_wrdata_par_en_p1[7:0],dfi_0_aw_ck_dis,dfi_0_lp_pwr_e_req,dfi_0_lp_sr_e_req,dfi_0_lp_pwr_x_req,dfi_0_aw_tx_indx_ld,dfi_0_dw_tx_indx_ld,dfi_0_dw_rx_indx_ld,dfi_0_ctrlupd_ack,dfi_0_phyupd_req,dfi_0_dw_wrdata_dqs_p0[7:0],dfi_0_dw_wrdata_dqs_p1[7:0],dfi_1_clk,dfi_1_rst_n,dfi_1_init_start,dfi_1_aw_ck_p0[1:0],dfi_1_aw_cke_p0[1:0],dfi_1_aw_row_p0[11:0],dfi_1_aw_col_p0[15:0],dfi_1_dw_wrdata_p0[255:0],dfi_1_dw_wrdata_mask_p0[31:0],dfi_1_dw_wrdata_dbi_p0[31:0],dfi_1_dw_wrdata_par_p0[7:0],dfi_1_dw_wrdata_dq_en_p0[7:0],dfi_1_dw_wrdata_par_en_p0[7:0],dfi_1_aw_ck_p1[1:0],dfi_1_aw_cke_p1[1:0],dfi_1_aw_row_p1[11:0],dfi_1_aw_col_p1[15:0],dfi_1_dw_wrdata_p1[255:0],dfi_1_dw_wrdata_mask_p1[31:0],dfi_1_dw_wrdata_dbi_p1[31:0],dfi_1_dw_wrdata_par_p1[7:0],dfi_1_dw_wrdata_dq_en_p1[7:0],dfi_1_dw_wrdata_par_en_p1[7:0],dfi_1_aw_ck_dis,dfi_1_lp_pwr_e_req,dfi_1_lp_sr_e_req,dfi_1_lp_pwr_x_req,dfi_1_aw_tx_indx_ld,dfi_1_dw_tx_indx_ld,dfi_1_dw_rx_indx_ld,dfi_1_ctrlupd_ack,dfi_1_phyupd_req,dfi_1_dw_wrdata_dqs_p0[7:0],dfi_1_dw_wrdata_dqs_p1[7:0],dfi_2_clk,dfi_2_rst_n,dfi_2_init_start,dfi_2_aw_ck_p0[1:0],dfi_2_aw_cke_p0[1:0],dfi_2_aw_row_p0[11:0],dfi_2_aw_col_p0[15:0],dfi_2_dw_wrdata_p0[255:0],dfi_2_dw_wrdata_mask_p0[31:0],dfi_2_dw_wrdata_dbi_p0[31:0],dfi_2_dw_wrdata_par_p0[7:0],dfi_2_dw_wrdata_dq_en_p0[7:0],dfi_2_dw_wrdata_par_en_p0[7:0],dfi_2_aw_ck_p1[1:0],dfi_2_aw_cke_p1[1:0],dfi_2_aw_row_p1[11:0],dfi_2_aw_col_p1[15:0],dfi_2_dw_wrdata_p1[255:0],dfi_2_dw_wrdata_mask_p1[31:0],dfi_2_dw_wrdata_dbi_p1[31:0],dfi_2_dw_wrdata_par_p1[7:0],dfi_2_dw_wrdata_dq_en_p1[7:0],dfi_2_dw_wrdata_par_en_p1[7:0],dfi_2_aw_ck_dis,dfi_2_lp_pwr_e_req,dfi_2_lp_sr_e_req,dfi_2_lp_pwr_x_req,dfi_2_aw_tx_indx_ld,dfi_2_dw_tx_indx_ld,dfi_2_dw_rx_indx_ld,dfi_2_ctrlupd_ack,dfi_2_phyupd_req,dfi_2_dw_wrdata_dqs_p0[7:0],dfi_2_dw_wrdata_dqs_p1[7:0],dfi_3_clk,dfi_3_rst_n,dfi_3_init_start,dfi_3_aw_ck_p0[1:0],dfi_3_aw_cke_p0[1:0],dfi_3_aw_row_p0[11:0],dfi_3_aw_col_p0[15:0],dfi_3_dw_wrdata_p0[255:0],dfi_3_dw_wrdata_mask_p0[31:0],dfi_3_dw_wrdata_dbi_p0[31:0],dfi_3_dw_wrdata_par_p0[7:0],dfi_3_dw_wrdata_dq_en_p0[7:0],dfi_3_dw_wrdata_par_en_p0[7:0],dfi_3_aw_ck_p1[1:0],dfi_3_aw_cke_p1[1:0],dfi_3_aw_row_p1[11:0],dfi_3_aw_col_p1[15:0],dfi_3_dw_wrdata_p1[255:0],dfi_3_dw_wrdata_mask_p1[31:0],dfi_3_dw_wrdata_dbi_p1[31:0],dfi_3_dw_wrdata_par_p1[7:0],dfi_3_dw_wrdata_dq_en_p1[7:0],dfi_3_dw_wrdata_par_en_p1[7:0],dfi_3_aw_ck_dis,dfi_3_lp_pwr_e_req,dfi_3_lp_sr_e_req,dfi_3_lp_pwr_x_req,dfi_3_aw_tx_indx_ld,dfi_3_dw_tx_indx_ld,dfi_3_dw_rx_indx_ld,dfi_3_ctrlupd_ack,dfi_3_phyupd_req,dfi_3_dw_wrdata_dqs_p0[7:0],dfi_3_dw_wrdata_dqs_p1[7:0],dfi_4_clk,dfi_4_rst_n,dfi_4_init_start,dfi_4_aw_ck_p0[1:0],dfi_4_aw_cke_p0[1:0],dfi_4_aw_row_p0[11:0],dfi_4_aw_col_p0[15:0],dfi_4_dw_wrdata_p0[255:0],dfi_4_dw_wrdata_mask_p0[31:0],dfi_4_dw_wrdata_dbi_p0[31:0],dfi_4_dw_wrdata_par_p0[7:0],dfi_4_dw_wrdata_dq_en_p0[7:0],dfi_4_dw_wrdata_par_en_p0[7:0],dfi_4_aw_ck_p1[1:0],dfi_4_aw_cke_p1[1:0],dfi_4_aw_row_p1[11:0],dfi_4_aw_col_p1[15:0],dfi_4_dw_wrdata_p1[255:0],dfi_4_dw_wrdata_mask_p1[31:0],dfi_4_dw_wrdata_dbi_p1[31:0],dfi_4_dw_wrdata_par_p1[7:0],dfi_4_dw_wrdata_dq_en_p1[7:0],dfi_4_dw_wrdata_par_en_p1[7:0],dfi_4_aw_ck_dis,dfi_4_lp_pwr_e_req,dfi_4_lp_sr_e_req,dfi_4_lp_pwr_x_req,dfi_4_aw_tx_indx_ld,dfi_4_dw_tx_indx_ld,dfi_4_dw_rx_indx_ld,dfi_4_ctrlupd_ack,dfi_4_phyupd_req,dfi_4_dw_wrdata_dqs_p0[7:0],dfi_4_dw_wrdata_dqs_p1[7:0],dfi_5_clk,dfi_5_rst_n,dfi_5_init_start,dfi_5_aw_ck_p0[1:0],dfi_5_aw_cke_p0[1:0],dfi_5_aw_row_p0[11:0],dfi_5_aw_col_p0[15:0],dfi_5_dw_wrdata_p0[255:0],dfi_5_dw_wrdata_mask_p0[31:0],dfi_5_dw_wrdata_dbi_p0[31:0],dfi_5_dw_wrdata_par_p0[7:0],dfi_5_dw_wrdata_dq_en_p0[7:0],dfi_5_dw_wrdata_par_en_p0[7:0],dfi_5_aw_ck_p1[1:0],dfi_5_aw_cke_p1[1:0],dfi_5_aw_row_p1[11:0],dfi_5_aw_col_p1[15:0],dfi_5_dw_wrdata_p1[255:0],dfi_5_dw_wrdata_mask_p1[31:0],dfi_5_dw_wrdata_dbi_p1[31:0],dfi_5_dw_wrdata_par_p1[7:0],dfi_5_dw_wrdata_dq_en_p1[7:0],dfi_5_dw_wrdata_par_en_p1[7:0],dfi_5_aw_ck_dis,dfi_5_lp_pwr_e_req,dfi_5_lp_sr_e_req,dfi_5_lp_pwr_x_req,dfi_5_aw_tx_indx_ld,dfi_5_dw_tx_indx_ld,dfi_5_dw_rx_indx_ld,dfi_5_ctrlupd_ack,dfi_5_phyupd_req,dfi_5_dw_wrdata_dqs_p0[7:0],dfi_5_dw_wrdata_dqs_p1[7:0],dfi_6_clk,dfi_6_rst_n,dfi_6_init_start,dfi_6_aw_ck_p0[1:0],dfi_6_aw_cke_p0[1:0],dfi_6_aw_row_p0[11:0],dfi_6_aw_col_p0[15:0],dfi_6_dw_wrdata_p0[255:0],dfi_6_dw_wrdata_mask_p0[31:0],dfi_6_dw_wrdata_dbi_p0[31:0],dfi_6_dw_wrdata_par_p0[7:0],dfi_6_dw_wrdata_dq_en_p0[7:0],dfi_6_dw_wrdata_par_en_p0[7:0],dfi_6_aw_ck_p1[1:0],dfi_6_aw_cke_p1[1:0],dfi_6_aw_row_p1[11:0],dfi_6_aw_col_p1[15:0],dfi_6_dw_wrdata_p1[255:0],dfi_6_dw_wrdata_mask_p1[31:0],dfi_6_dw_wrdata_dbi_p1[31:0],dfi_6_dw_wrdata_par_p1[7:0],dfi_6_dw_wrdata_dq_en_p1[7:0],dfi_6_dw_wrdata_par_en_p1[7:0],dfi_6_aw_ck_dis,dfi_6_lp_pwr_e_req,dfi_6_lp_sr_e_req,dfi_6_lp_pwr_x_req,dfi_6_aw_tx_indx_ld,dfi_6_dw_tx_indx_ld,dfi_6_dw_rx_indx_ld,dfi_6_ctrlupd_ack,dfi_6_phyupd_req,dfi_6_dw_wrdata_dqs_p0[7:0],dfi_6_dw_wrdata_dqs_p1[7:0],dfi_7_clk,dfi_7_rst_n,dfi_7_init_start,dfi_7_aw_ck_p0[1:0],dfi_7_aw_cke_p0[1:0],dfi_7_aw_row_p0[11:0],dfi_7_aw_col_p0[15:0],dfi_7_dw_wrdata_p0[255:0],dfi_7_dw_wrdata_mask_p0[31:0],dfi_7_dw_wrdata_dbi_p0[31:0],dfi_7_dw_wrdata_par_p0[7:0],dfi_7_dw_wrdata_dq_en_p0[7:0],dfi_7_dw_wrdata_par_en_p0[7:0],dfi_7_aw_ck_p1[1:0],dfi_7_aw_cke_p1[1:0],dfi_7_aw_row_p1[11:0],dfi_7_aw_col_p1[15:0],dfi_7_dw_wrdata_p1[255:0],dfi_7_dw_wrdata_mask_p1[31:0],dfi_7_dw_wrdata_dbi_p1[31:0],dfi_7_dw_wrdata_par_p1[7:0],dfi_7_dw_wrdata_dq_en_p1[7:0],dfi_7_dw_wrdata_par_en_p1[7:0],dfi_7_aw_ck_dis,dfi_7_lp_pwr_e_req,dfi_7_lp_sr_e_req,dfi_7_lp_pwr_x_req,dfi_7_aw_tx_indx_ld,dfi_7_dw_tx_indx_ld,dfi_7_dw_rx_indx_ld,dfi_7_ctrlupd_ack,dfi_7_phyupd_req,dfi_7_dw_wrdata_dqs_p0[7:0],dfi_7_dw_wrdata_dqs_p1[7:0],dfi_8_clk,dfi_8_rst_n,dfi_8_init_start,dfi_8_aw_ck_p0[1:0],dfi_8_aw_cke_p0[1:0],dfi_8_aw_row_p0[11:0],dfi_8_aw_col_p0[15:0],dfi_8_dw_wrdata_p0[255:0],dfi_8_dw_wrdata_mask_p0[31:0],dfi_8_dw_wrdata_dbi_p0[31:0],dfi_8_dw_wrdata_par_p0[7:0],dfi_8_dw_wrdata_dq_en_p0[7:0],dfi_8_dw_wrdata_par_en_p0[7:0],dfi_8_aw_ck_p1[1:0],dfi_8_aw_cke_p1[1:0],dfi_8_aw_row_p1[11:0],dfi_8_aw_col_p1[15:0],dfi_8_dw_wrdata_p1[255:0],dfi_8_dw_wrdata_mask_p1[31:0],dfi_8_dw_wrdata_dbi_p1[31:0],dfi_8_dw_wrdata_par_p1[7:0],dfi_8_dw_wrdata_dq_en_p1[7:0],dfi_8_dw_wrdata_par_en_p1[7:0],dfi_8_aw_ck_dis,dfi_8_lp_pwr_e_req,dfi_8_lp_sr_e_req,dfi_8_lp_pwr_x_req,dfi_8_aw_tx_indx_ld,dfi_8_dw_tx_indx_ld,dfi_8_dw_rx_indx_ld,dfi_8_ctrlupd_ack,dfi_8_phyupd_req,dfi_8_dw_wrdata_dqs_p0[7:0],dfi_8_dw_wrdata_dqs_p1[7:0],dfi_9_clk,dfi_9_rst_n,dfi_9_init_start,dfi_9_aw_ck_p0[1:0],dfi_9_aw_cke_p0[1:0],dfi_9_aw_row_p0[11:0],dfi_9_aw_col_p0[15:0],dfi_9_dw_wrdata_p0[255:0],dfi_9_dw_wrdata_mask_p0[31:0],dfi_9_dw_wrdata_dbi_p0[31:0],dfi_9_dw_wrdata_par_p0[7:0],dfi_9_dw_wrdata_dq_en_p0[7:0],dfi_9_dw_wrdata_par_en_p0[7:0],dfi_9_aw_ck_p1[1:0],dfi_9_aw_cke_p1[1:0],dfi_9_aw_row_p1[11:0],dfi_9_aw_col_p1[15:0],dfi_9_dw_wrdata_p1[255:0],dfi_9_dw_wrdata_mask_p1[31:0],dfi_9_dw_wrdata_dbi_p1[31:0],dfi_9_dw_wrdata_par_p1[7:0],dfi_9_dw_wrdata_dq_en_p1[7:0],dfi_9_dw_wrdata_par_en_p1[7:0],dfi_9_aw_ck_dis,dfi_9_lp_pwr_e_req,dfi_9_lp_sr_e_req,dfi_9_lp_pwr_x_req,dfi_9_aw_tx_indx_ld,dfi_9_dw_tx_indx_ld,dfi_9_dw_rx_indx_ld,dfi_9_ctrlupd_ack,dfi_9_phyupd_req,dfi_9_dw_wrdata_dqs_p0[7:0],dfi_9_dw_wrdata_dqs_p1[7:0],dfi_10_clk,dfi_10_rst_n,dfi_10_init_start,dfi_10_aw_ck_p0[1:0],dfi_10_aw_cke_p0[1:0],dfi_10_aw_row_p0[11:0],dfi_10_aw_col_p0[15:0],dfi_10_dw_wrdata_p0[255:0],dfi_10_dw_wrdata_mask_p0[31:0],dfi_10_dw_wrdata_dbi_p0[31:0],dfi_10_dw_wrdata_par_p0[7:0],dfi_10_dw_wrdata_dq_en_p0[7:0],dfi_10_dw_wrdata_par_en_p0[7:0],dfi_10_aw_ck_p1[1:0],dfi_10_aw_cke_p1[1:0],dfi_10_aw_row_p1[11:0],dfi_10_aw_col_p1[15:0],dfi_10_dw_wrdata_p1[255:0],dfi_10_dw_wrdata_mask_p1[31:0],dfi_10_dw_wrdata_dbi_p1[31:0],dfi_10_dw_wrdata_par_p1[7:0],dfi_10_dw_wrdata_dq_en_p1[7:0],dfi_10_dw_wrdata_par_en_p1[7:0],dfi_10_aw_ck_dis,dfi_10_lp_pwr_e_req,dfi_10_lp_sr_e_req,dfi_10_lp_pwr_x_req,dfi_10_aw_tx_indx_ld,dfi_10_dw_tx_indx_ld,dfi_10_dw_rx_indx_ld,dfi_10_ctrlupd_ack,dfi_10_phyupd_req,dfi_10_dw_wrdata_dqs_p0[7:0],dfi_10_dw_wrdata_dqs_p1[7:0],dfi_11_clk,dfi_11_rst_n,dfi_11_init_start,dfi_11_aw_ck_p0[1:0],dfi_11_aw_cke_p0[1:0],dfi_11_aw_row_p0[11:0],dfi_11_aw_col_p0[15:0],dfi_11_dw_wrdata_p0[255:0],dfi_11_dw_wrdata_mask_p0[31:0],dfi_11_dw_wrdata_dbi_p0[31:0],dfi_11_dw_wrdata_par_p0[7:0],dfi_11_dw_wrdata_dq_en_p0[7:0],dfi_11_dw_wrdata_par_en_p0[7:0],dfi_11_aw_ck_p1[1:0],dfi_11_aw_cke_p1[1:0],dfi_11_aw_row_p1[11:0],dfi_11_aw_col_p1[15:0],dfi_11_dw_wrdata_p1[255:0],dfi_11_dw_wrdata_mask_p1[31:0],dfi_11_dw_wrdata_dbi_p1[31:0],dfi_11_dw_wrdata_par_p1[7:0],dfi_11_dw_wrdata_dq_en_p1[7:0],dfi_11_dw_wrdata_par_en_p1[7:0],dfi_11_aw_ck_dis,dfi_11_lp_pwr_e_req,dfi_11_lp_sr_e_req,dfi_11_lp_pwr_x_req,dfi_11_aw_tx_indx_ld,dfi_11_dw_tx_indx_ld,dfi_11_dw_rx_indx_ld,dfi_11_ctrlupd_ack,dfi_11_phyupd_req,dfi_11_dw_wrdata_dqs_p0[7:0],dfi_11_dw_wrdata_dqs_p1[7:0],dfi_12_clk,dfi_12_rst_n,dfi_12_init_start,dfi_12_aw_ck_p0[1:0],dfi_12_aw_cke_p0[1:0],dfi_12_aw_row_p0[11:0],dfi_12_aw_col_p0[15:0],dfi_12_dw_wrdata_p0[255:0],dfi_12_dw_wrdata_mask_p0[31:0],dfi_12_dw_wrdata_dbi_p0[31:0],dfi_12_dw_wrdata_par_p0[7:0],dfi_12_dw_wrdata_dq_en_p0[7:0],dfi_12_dw_wrdata_par_en_p0[7:0],dfi_12_aw_ck_p1[1:0],dfi_12_aw_cke_p1[1:0],dfi_12_aw_row_p1[11:0],dfi_12_aw_col_p1[15:0],dfi_12_dw_wrdata_p1[255:0],dfi_12_dw_wrdata_mask_p1[31:0],dfi_12_dw_wrdata_dbi_p1[31:0],dfi_12_dw_wrdata_par_p1[7:0],dfi_12_dw_wrdata_dq_en_p1[7:0],dfi_12_dw_wrdata_par_en_p1[7:0],dfi_12_aw_ck_dis,dfi_12_lp_pwr_e_req,dfi_12_lp_sr_e_req,dfi_12_lp_pwr_x_req,dfi_12_aw_tx_indx_ld,dfi_12_dw_tx_indx_ld,dfi_12_dw_rx_indx_ld,dfi_12_ctrlupd_ack,dfi_12_phyupd_req,dfi_12_dw_wrdata_dqs_p0[7:0],dfi_12_dw_wrdata_dqs_p1[7:0],dfi_13_clk,dfi_13_rst_n,dfi_13_init_start,dfi_13_aw_ck_p0[1:0],dfi_13_aw_cke_p0[1:0],dfi_13_aw_row_p0[11:0],dfi_13_aw_col_p0[15:0],dfi_13_dw_wrdata_p0[255:0],dfi_13_dw_wrdata_mask_p0[31:0],dfi_13_dw_wrdata_dbi_p0[31:0],dfi_13_dw_wrdata_par_p0[7:0],dfi_13_dw_wrdata_dq_en_p0[7:0],dfi_13_dw_wrdata_par_en_p0[7:0],dfi_13_aw_ck_p1[1:0],dfi_13_aw_cke_p1[1:0],dfi_13_aw_row_p1[11:0],dfi_13_aw_col_p1[15:0],dfi_13_dw_wrdata_p1[255:0],dfi_13_dw_wrdata_mask_p1[31:0],dfi_13_dw_wrdata_dbi_p1[31:0],dfi_13_dw_wrdata_par_p1[7:0],dfi_13_dw_wrdata_dq_en_p1[7:0],dfi_13_dw_wrdata_par_en_p1[7:0],dfi_13_aw_ck_dis,dfi_13_lp_pwr_e_req,dfi_13_lp_sr_e_req,dfi_13_lp_pwr_x_req,dfi_13_aw_tx_indx_ld,dfi_13_dw_tx_indx_ld,dfi_13_dw_rx_indx_ld,dfi_13_ctrlupd_ack,dfi_13_phyupd_req,dfi_13_dw_wrdata_dqs_p0[7:0],dfi_13_dw_wrdata_dqs_p1[7:0],dfi_14_clk,dfi_14_rst_n,dfi_14_init_start,dfi_14_aw_ck_p0[1:0],dfi_14_aw_cke_p0[1:0],dfi_14_aw_row_p0[11:0],dfi_14_aw_col_p0[15:0],dfi_14_dw_wrdata_p0[255:0],dfi_14_dw_wrdata_mask_p0[31:0],dfi_14_dw_wrdata_dbi_p0[31:0],dfi_14_dw_wrdata_par_p0[7:0],dfi_14_dw_wrdata_dq_en_p0[7:0],dfi_14_dw_wrdata_par_en_p0[7:0],dfi_14_aw_ck_p1[1:0],dfi_14_aw_cke_p1[1:0],dfi_14_aw_row_p1[11:0],dfi_14_aw_col_p1[15:0],dfi_14_dw_wrdata_p1[255:0],dfi_14_dw_wrdata_mask_p1[31:0],dfi_14_dw_wrdata_dbi_p1[31:0],dfi_14_dw_wrdata_par_p1[7:0],dfi_14_dw_wrdata_dq_en_p1[7:0],dfi_14_dw_wrdata_par_en_p1[7:0],dfi_14_aw_ck_dis,dfi_14_lp_pwr_e_req,dfi_14_lp_sr_e_req,dfi_14_lp_pwr_x_req,dfi_14_aw_tx_indx_ld,dfi_14_dw_tx_indx_ld,dfi_14_dw_rx_indx_ld,dfi_14_ctrlupd_ack,dfi_14_phyupd_req,dfi_14_dw_wrdata_dqs_p0[7:0],dfi_14_dw_wrdata_dqs_p1[7:0],dfi_15_clk,dfi_15_rst_n,dfi_15_init_start,dfi_15_aw_ck_p0[1:0],dfi_15_aw_cke_p0[1:0],dfi_15_aw_row_p0[11:0],dfi_15_aw_col_p0[15:0],dfi_15_dw_wrdata_p0[255:0],dfi_15_dw_wrdata_mask_p0[31:0],dfi_15_dw_wrdata_dbi_p0[31:0],dfi_15_dw_wrdata_par_p0[7:0],dfi_15_dw_wrdata_dq_en_p0[7:0],dfi_15_dw_wrdata_par_en_p0[7:0],dfi_15_aw_ck_p1[1:0],dfi_15_aw_cke_p1[1:0],dfi_15_aw_row_p1[11:0],dfi_15_aw_col_p1[15:0],dfi_15_dw_wrdata_p1[255:0],dfi_15_dw_wrdata_mask_p1[31:0],dfi_15_dw_wrdata_dbi_p1[31:0],dfi_15_dw_wrdata_par_p1[7:0],dfi_15_dw_wrdata_dq_en_p1[7:0],dfi_15_dw_wrdata_par_en_p1[7:0],dfi_15_aw_ck_dis,dfi_15_lp_pwr_e_req,dfi_15_lp_sr_e_req,dfi_15_lp_pwr_x_req,dfi_15_aw_tx_indx_ld,dfi_15_dw_tx_indx_ld,dfi_15_dw_rx_indx_ld,dfi_15_ctrlupd_ack,dfi_15_phyupd_req,dfi_15_dw_wrdata_dqs_p0[7:0],dfi_15_dw_wrdata_dqs_p1[7:0],APB_0_PCLK,APB_0_PRESET_N,APB_1_PCLK,APB_1_PRESET_N,dfi_0_dw_rddata_p0[255:0],dfi_0_dw_rddata_dm_p0[31:0],dfi_0_dw_rddata_dbi_p0[31:0],dfi_0_dw_rddata_par_p0[7:0],dfi_0_dw_rddata_p1[255:0],dfi_0_dw_rddata_dm_p1[31:0],dfi_0_dw_rddata_dbi_p1[31:0],dfi_0_dw_rddata_par_p1[7:0],dfi_0_dbi_byte_disable[15:0],dfi_0_dw_rddata_valid[3:0],dfi_0_dw_derr_n[7:0],dfi_0_aw_aerr_n[1:0],dfi_0_ctrlupd_req,dfi_0_phyupd_ack,dfi_0_clk_init,dfi_0_init_complete,dfi_0_out_rst_n,dfi_1_dw_rddata_p0[255:0],dfi_1_dw_rddata_dm_p0[31:0],dfi_1_dw_rddata_dbi_p0[31:0],dfi_1_dw_rddata_par_p0[7:0],dfi_1_dw_rddata_p1[255:0],dfi_1_dw_rddata_dm_p1[31:0],dfi_1_dw_rddata_dbi_p1[31:0],dfi_1_dw_rddata_par_p1[7:0],dfi_1_dbi_byte_disable[15:0],dfi_1_dw_rddata_valid[3:0],dfi_1_dw_derr_n[7:0],dfi_1_aw_aerr_n[1:0],dfi_1_ctrlupd_req,dfi_1_phyupd_ack,dfi_1_clk_init,dfi_1_init_complete,dfi_1_out_rst_n,dfi_2_dw_rddata_p0[255:0],dfi_2_dw_rddata_dm_p0[31:0],dfi_2_dw_rddata_dbi_p0[31:0],dfi_2_dw_rddata_par_p0[7:0],dfi_2_dw_rddata_p1[255:0],dfi_2_dw_rddata_dm_p1[31:0],dfi_2_dw_rddata_dbi_p1[31:0],dfi_2_dw_rddata_par_p1[7:0],dfi_2_dbi_byte_disable[15:0],dfi_2_dw_rddata_valid[3:0],dfi_2_dw_derr_n[7:0],dfi_2_aw_aerr_n[1:0],dfi_2_ctrlupd_req,dfi_2_phyupd_ack,dfi_2_clk_init,dfi_2_init_complete,dfi_2_out_rst_n,dfi_3_dw_rddata_p0[255:0],dfi_3_dw_rddata_dm_p0[31:0],dfi_3_dw_rddata_dbi_p0[31:0],dfi_3_dw_rddata_par_p0[7:0],dfi_3_dw_rddata_p1[255:0],dfi_3_dw_rddata_dm_p1[31:0],dfi_3_dw_rddata_dbi_p1[31:0],dfi_3_dw_rddata_par_p1[7:0],dfi_3_dbi_byte_disable[15:0],dfi_3_dw_rddata_valid[3:0],dfi_3_dw_derr_n[7:0],dfi_3_aw_aerr_n[1:0],dfi_3_ctrlupd_req,dfi_3_phyupd_ack,dfi_3_clk_init,dfi_3_init_complete,dfi_3_out_rst_n,dfi_4_dw_rddata_p0[255:0],dfi_4_dw_rddata_dm_p0[31:0],dfi_4_dw_rddata_dbi_p0[31:0],dfi_4_dw_rddata_par_p0[7:0],dfi_4_dw_rddata_p1[255:0],dfi_4_dw_rddata_dm_p1[31:0],dfi_4_dw_rddata_dbi_p1[31:0],dfi_4_dw_rddata_par_p1[7:0],dfi_4_dbi_byte_disable[15:0],dfi_4_dw_rddata_valid[3:0],dfi_4_dw_derr_n[7:0],dfi_4_aw_aerr_n[1:0],dfi_4_ctrlupd_req,dfi_4_phyupd_ack,dfi_4_clk_init,dfi_4_init_complete,dfi_4_out_rst_n,dfi_5_dw_rddata_p0[255:0],dfi_5_dw_rddata_dm_p0[31:0],dfi_5_dw_rddata_dbi_p0[31:0],dfi_5_dw_rddata_par_p0[7:0],dfi_5_dw_rddata_p1[255:0],dfi_5_dw_rddata_dm_p1[31:0],dfi_5_dw_rddata_dbi_p1[31:0],dfi_5_dw_rddata_par_p1[7:0],dfi_5_dbi_byte_disable[15:0],dfi_5_dw_rddata_valid[3:0],dfi_5_dw_derr_n[7:0],dfi_5_aw_aerr_n[1:0],dfi_5_ctrlupd_req,dfi_5_phyupd_ack,dfi_5_clk_init,dfi_5_init_complete,dfi_5_out_rst_n,dfi_6_dw_rddata_p0[255:0],dfi_6_dw_rddata_dm_p0[31:0],dfi_6_dw_rddata_dbi_p0[31:0],dfi_6_dw_rddata_par_p0[7:0],dfi_6_dw_rddata_p1[255:0],dfi_6_dw_rddata_dm_p1[31:0],dfi_6_dw_rddata_dbi_p1[31:0],dfi_6_dw_rddata_par_p1[7:0],dfi_6_dbi_byte_disable[15:0],dfi_6_dw_rddata_valid[3:0],dfi_6_dw_derr_n[7:0],dfi_6_aw_aerr_n[1:0],dfi_6_ctrlupd_req,dfi_6_phyupd_ack,dfi_6_clk_init,dfi_6_init_complete,dfi_6_out_rst_n,dfi_7_dw_rddata_p0[255:0],dfi_7_dw_rddata_dm_p0[31:0],dfi_7_dw_rddata_dbi_p0[31:0],dfi_7_dw_rddata_par_p0[7:0],dfi_7_dw_rddata_p1[255:0],dfi_7_dw_rddata_dm_p1[31:0],dfi_7_dw_rddata_dbi_p1[31:0],dfi_7_dw_rddata_par_p1[7:0],dfi_7_dbi_byte_disable[15:0],dfi_7_dw_rddata_valid[3:0],dfi_7_dw_derr_n[7:0],dfi_7_aw_aerr_n[1:0],dfi_7_ctrlupd_req,dfi_7_phyupd_ack,dfi_7_clk_init,dfi_7_init_complete,dfi_7_out_rst_n,dfi_8_dw_rddata_p0[255:0],dfi_8_dw_rddata_dm_p0[31:0],dfi_8_dw_rddata_dbi_p0[31:0],dfi_8_dw_rddata_par_p0[7:0],dfi_8_dw_rddata_p1[255:0],dfi_8_dw_rddata_dm_p1[31:0],dfi_8_dw_rddata_dbi_p1[31:0],dfi_8_dw_rddata_par_p1[7:0],dfi_8_dbi_byte_disable[15:0],dfi_8_dw_rddata_valid[3:0],dfi_8_dw_derr_n[7:0],dfi_8_aw_aerr_n[1:0],dfi_8_ctrlupd_req,dfi_8_phyupd_ack,dfi_8_clk_init,dfi_8_init_complete,dfi_8_out_rst_n,dfi_9_dw_rddata_p0[255:0],dfi_9_dw_rddata_dm_p0[31:0],dfi_9_dw_rddata_dbi_p0[31:0],dfi_9_dw_rddata_par_p0[7:0],dfi_9_dw_rddata_p1[255:0],dfi_9_dw_rddata_dm_p1[31:0],dfi_9_dw_rddata_dbi_p1[31:0],dfi_9_dw_rddata_par_p1[7:0],dfi_9_dbi_byte_disable[15:0],dfi_9_dw_rddata_valid[3:0],dfi_9_dw_derr_n[7:0],dfi_9_aw_aerr_n[1:0],dfi_9_ctrlupd_req,dfi_9_phyupd_ack,dfi_9_clk_init,dfi_9_init_complete,dfi_9_out_rst_n,dfi_10_dw_rddata_p0[255:0],dfi_10_dw_rddata_dm_p0[31:0],dfi_10_dw_rddata_dbi_p0[31:0],dfi_10_dw_rddata_par_p0[7:0],dfi_10_dw_rddata_p1[255:0],dfi_10_dw_rddata_dm_p1[31:0],dfi_10_dw_rddata_dbi_p1[31:0],dfi_10_dw_rddata_par_p1[7:0],dfi_10_dbi_byte_disable[15:0],dfi_10_dw_rddata_valid[3:0],dfi_10_dw_derr_n[7:0],dfi_10_aw_aerr_n[1:0],dfi_10_ctrlupd_req,dfi_10_phyupd_ack,dfi_10_clk_init,dfi_10_init_complete,dfi_10_out_rst_n,dfi_11_dw_rddata_p0[255:0],dfi_11_dw_rddata_dm_p0[31:0],dfi_11_dw_rddata_dbi_p0[31:0],dfi_11_dw_rddata_par_p0[7:0],dfi_11_dw_rddata_p1[255:0],dfi_11_dw_rddata_dm_p1[31:0],dfi_11_dw_rddata_dbi_p1[31:0],dfi_11_dw_rddata_par_p1[7:0],dfi_11_dbi_byte_disable[15:0],dfi_11_dw_rddata_valid[3:0],dfi_11_dw_derr_n[7:0],dfi_11_aw_aerr_n[1:0],dfi_11_ctrlupd_req,dfi_11_phyupd_ack,dfi_11_clk_init,dfi_11_init_complete,dfi_11_out_rst_n,dfi_12_dw_rddata_p0[255:0],dfi_12_dw_rddata_dm_p0[31:0],dfi_12_dw_rddata_dbi_p0[31:0],dfi_12_dw_rddata_par_p0[7:0],dfi_12_dw_rddata_p1[255:0],dfi_12_dw_rddata_dm_p1[31:0],dfi_12_dw_rddata_dbi_p1[31:0],dfi_12_dw_rddata_par_p1[7:0],dfi_12_dbi_byte_disable[15:0],dfi_12_dw_rddata_valid[3:0],dfi_12_dw_derr_n[7:0],dfi_12_aw_aerr_n[1:0],dfi_12_ctrlupd_req,dfi_12_phyupd_ack,dfi_12_clk_init,dfi_12_init_complete,dfi_12_out_rst_n,dfi_13_dw_rddata_p0[255:0],dfi_13_dw_rddata_dm_p0[31:0],dfi_13_dw_rddata_dbi_p0[31:0],dfi_13_dw_rddata_par_p0[7:0],dfi_13_dw_rddata_p1[255:0],dfi_13_dw_rddata_dm_p1[31:0],dfi_13_dw_rddata_dbi_p1[31:0],dfi_13_dw_rddata_par_p1[7:0],dfi_13_dbi_byte_disable[15:0],dfi_13_dw_rddata_valid[3:0],dfi_13_dw_derr_n[7:0],dfi_13_aw_aerr_n[1:0],dfi_13_ctrlupd_req,dfi_13_phyupd_ack,dfi_13_clk_init,dfi_13_init_complete,dfi_13_out_rst_n,dfi_14_dw_rddata_p0[255:0],dfi_14_dw_rddata_dm_p0[31:0],dfi_14_dw_rddata_dbi_p0[31:0],dfi_14_dw_rddata_par_p0[7:0],dfi_14_dw_rddata_p1[255:0],dfi_14_dw_rddata_dm_p1[31:0],dfi_14_dw_rddata_dbi_p1[31:0],dfi_14_dw_rddata_par_p1[7:0],dfi_14_dbi_byte_disable[15:0],dfi_14_dw_rddata_valid[3:0],dfi_14_dw_derr_n[7:0],dfi_14_aw_aerr_n[1:0],dfi_14_ctrlupd_req,dfi_14_phyupd_ack,dfi_14_clk_init,dfi_14_init_complete,dfi_14_out_rst_n,dfi_15_dw_rddata_p0[255:0],dfi_15_dw_rddata_dm_p0[31:0],dfi_15_dw_rddata_dbi_p0[31:0],dfi_15_dw_rddata_par_p0[7:0],dfi_15_dw_rddata_p1[255:0],dfi_15_dw_rddata_dm_p1[31:0],dfi_15_dw_rddata_dbi_p1[31:0],dfi_15_dw_rddata_par_p1[7:0],dfi_15_dbi_byte_disable[15:0],dfi_15_dw_rddata_valid[3:0],dfi_15_dw_derr_n[7:0],dfi_15_aw_aerr_n[1:0],dfi_15_ctrlupd_req,dfi_15_phyupd_ack,dfi_15_clk_init,dfi_15_init_complete,dfi_15_out_rst_n,apb_complete_0,apb_complete_1,DRAM_0_STAT_CATTRIP,DRAM_0_STAT_TEMP[6:0],DRAM_1_STAT_CATTRIP,DRAM_1_STAT_TEMP[6:0]" */; + input HBM_REF_CLK_0; + input HBM_REF_CLK_1; + input dfi_0_clk; + input dfi_0_rst_n; + input dfi_0_init_start; + input [1:0]dfi_0_aw_ck_p0; + input [1:0]dfi_0_aw_cke_p0; + input [11:0]dfi_0_aw_row_p0; + input [15:0]dfi_0_aw_col_p0; + input [255:0]dfi_0_dw_wrdata_p0; + input [31:0]dfi_0_dw_wrdata_mask_p0; + input [31:0]dfi_0_dw_wrdata_dbi_p0; + input [7:0]dfi_0_dw_wrdata_par_p0; + input [7:0]dfi_0_dw_wrdata_dq_en_p0; + input [7:0]dfi_0_dw_wrdata_par_en_p0; + input [1:0]dfi_0_aw_ck_p1; + input [1:0]dfi_0_aw_cke_p1; + input [11:0]dfi_0_aw_row_p1; + input [15:0]dfi_0_aw_col_p1; + input [255:0]dfi_0_dw_wrdata_p1; + input [31:0]dfi_0_dw_wrdata_mask_p1; + input [31:0]dfi_0_dw_wrdata_dbi_p1; + input [7:0]dfi_0_dw_wrdata_par_p1; + input [7:0]dfi_0_dw_wrdata_dq_en_p1; + input [7:0]dfi_0_dw_wrdata_par_en_p1; + input dfi_0_aw_ck_dis; + input dfi_0_lp_pwr_e_req; + input dfi_0_lp_sr_e_req; + input dfi_0_lp_pwr_x_req; + input dfi_0_aw_tx_indx_ld; + input dfi_0_dw_tx_indx_ld; + input dfi_0_dw_rx_indx_ld; + input dfi_0_ctrlupd_ack; + input dfi_0_phyupd_req; + input [7:0]dfi_0_dw_wrdata_dqs_p0; + input [7:0]dfi_0_dw_wrdata_dqs_p1; + input dfi_1_clk; + input dfi_1_rst_n; + input dfi_1_init_start; + input [1:0]dfi_1_aw_ck_p0; + input [1:0]dfi_1_aw_cke_p0; + input [11:0]dfi_1_aw_row_p0; + input [15:0]dfi_1_aw_col_p0; + input [255:0]dfi_1_dw_wrdata_p0; + input [31:0]dfi_1_dw_wrdata_mask_p0; + input [31:0]dfi_1_dw_wrdata_dbi_p0; + input [7:0]dfi_1_dw_wrdata_par_p0; + input [7:0]dfi_1_dw_wrdata_dq_en_p0; + input [7:0]dfi_1_dw_wrdata_par_en_p0; + input [1:0]dfi_1_aw_ck_p1; + input [1:0]dfi_1_aw_cke_p1; + input [11:0]dfi_1_aw_row_p1; + input [15:0]dfi_1_aw_col_p1; + input [255:0]dfi_1_dw_wrdata_p1; + input [31:0]dfi_1_dw_wrdata_mask_p1; + input [31:0]dfi_1_dw_wrdata_dbi_p1; + input [7:0]dfi_1_dw_wrdata_par_p1; + input [7:0]dfi_1_dw_wrdata_dq_en_p1; + input [7:0]dfi_1_dw_wrdata_par_en_p1; + input dfi_1_aw_ck_dis; + input dfi_1_lp_pwr_e_req; + input dfi_1_lp_sr_e_req; + input dfi_1_lp_pwr_x_req; + input dfi_1_aw_tx_indx_ld; + input dfi_1_dw_tx_indx_ld; + input dfi_1_dw_rx_indx_ld; + input dfi_1_ctrlupd_ack; + input dfi_1_phyupd_req; + input [7:0]dfi_1_dw_wrdata_dqs_p0; + input [7:0]dfi_1_dw_wrdata_dqs_p1; + input dfi_2_clk; + input dfi_2_rst_n; + input dfi_2_init_start; + input [1:0]dfi_2_aw_ck_p0; + input [1:0]dfi_2_aw_cke_p0; + input [11:0]dfi_2_aw_row_p0; + input [15:0]dfi_2_aw_col_p0; + input [255:0]dfi_2_dw_wrdata_p0; + input [31:0]dfi_2_dw_wrdata_mask_p0; + input [31:0]dfi_2_dw_wrdata_dbi_p0; + input [7:0]dfi_2_dw_wrdata_par_p0; + input [7:0]dfi_2_dw_wrdata_dq_en_p0; + input [7:0]dfi_2_dw_wrdata_par_en_p0; + input [1:0]dfi_2_aw_ck_p1; + input [1:0]dfi_2_aw_cke_p1; + input [11:0]dfi_2_aw_row_p1; + input [15:0]dfi_2_aw_col_p1; + input [255:0]dfi_2_dw_wrdata_p1; + input [31:0]dfi_2_dw_wrdata_mask_p1; + input [31:0]dfi_2_dw_wrdata_dbi_p1; + input [7:0]dfi_2_dw_wrdata_par_p1; + input [7:0]dfi_2_dw_wrdata_dq_en_p1; + input [7:0]dfi_2_dw_wrdata_par_en_p1; + input dfi_2_aw_ck_dis; + input dfi_2_lp_pwr_e_req; + input dfi_2_lp_sr_e_req; + input dfi_2_lp_pwr_x_req; + input dfi_2_aw_tx_indx_ld; + input dfi_2_dw_tx_indx_ld; + input dfi_2_dw_rx_indx_ld; + input dfi_2_ctrlupd_ack; + input dfi_2_phyupd_req; + input [7:0]dfi_2_dw_wrdata_dqs_p0; + input [7:0]dfi_2_dw_wrdata_dqs_p1; + input dfi_3_clk; + input dfi_3_rst_n; + input dfi_3_init_start; + input [1:0]dfi_3_aw_ck_p0; + input [1:0]dfi_3_aw_cke_p0; + input [11:0]dfi_3_aw_row_p0; + input [15:0]dfi_3_aw_col_p0; + input [255:0]dfi_3_dw_wrdata_p0; + input [31:0]dfi_3_dw_wrdata_mask_p0; + input [31:0]dfi_3_dw_wrdata_dbi_p0; + input [7:0]dfi_3_dw_wrdata_par_p0; + input [7:0]dfi_3_dw_wrdata_dq_en_p0; + input [7:0]dfi_3_dw_wrdata_par_en_p0; + input [1:0]dfi_3_aw_ck_p1; + input [1:0]dfi_3_aw_cke_p1; + input [11:0]dfi_3_aw_row_p1; + input [15:0]dfi_3_aw_col_p1; + input [255:0]dfi_3_dw_wrdata_p1; + input [31:0]dfi_3_dw_wrdata_mask_p1; + input [31:0]dfi_3_dw_wrdata_dbi_p1; + input [7:0]dfi_3_dw_wrdata_par_p1; + input [7:0]dfi_3_dw_wrdata_dq_en_p1; + input [7:0]dfi_3_dw_wrdata_par_en_p1; + input dfi_3_aw_ck_dis; + input dfi_3_lp_pwr_e_req; + input dfi_3_lp_sr_e_req; + input dfi_3_lp_pwr_x_req; + input dfi_3_aw_tx_indx_ld; + input dfi_3_dw_tx_indx_ld; + input dfi_3_dw_rx_indx_ld; + input dfi_3_ctrlupd_ack; + input dfi_3_phyupd_req; + input [7:0]dfi_3_dw_wrdata_dqs_p0; + input [7:0]dfi_3_dw_wrdata_dqs_p1; + input dfi_4_clk; + input dfi_4_rst_n; + input dfi_4_init_start; + input [1:0]dfi_4_aw_ck_p0; + input [1:0]dfi_4_aw_cke_p0; + input [11:0]dfi_4_aw_row_p0; + input [15:0]dfi_4_aw_col_p0; + input [255:0]dfi_4_dw_wrdata_p0; + input [31:0]dfi_4_dw_wrdata_mask_p0; + input [31:0]dfi_4_dw_wrdata_dbi_p0; + input [7:0]dfi_4_dw_wrdata_par_p0; + input [7:0]dfi_4_dw_wrdata_dq_en_p0; + input [7:0]dfi_4_dw_wrdata_par_en_p0; + input [1:0]dfi_4_aw_ck_p1; + input [1:0]dfi_4_aw_cke_p1; + input [11:0]dfi_4_aw_row_p1; + input [15:0]dfi_4_aw_col_p1; + input [255:0]dfi_4_dw_wrdata_p1; + input [31:0]dfi_4_dw_wrdata_mask_p1; + input [31:0]dfi_4_dw_wrdata_dbi_p1; + input [7:0]dfi_4_dw_wrdata_par_p1; + input [7:0]dfi_4_dw_wrdata_dq_en_p1; + input [7:0]dfi_4_dw_wrdata_par_en_p1; + input dfi_4_aw_ck_dis; + input dfi_4_lp_pwr_e_req; + input dfi_4_lp_sr_e_req; + input dfi_4_lp_pwr_x_req; + input dfi_4_aw_tx_indx_ld; + input dfi_4_dw_tx_indx_ld; + input dfi_4_dw_rx_indx_ld; + input dfi_4_ctrlupd_ack; + input dfi_4_phyupd_req; + input [7:0]dfi_4_dw_wrdata_dqs_p0; + input [7:0]dfi_4_dw_wrdata_dqs_p1; + input dfi_5_clk; + input dfi_5_rst_n; + input dfi_5_init_start; + input [1:0]dfi_5_aw_ck_p0; + input [1:0]dfi_5_aw_cke_p0; + input [11:0]dfi_5_aw_row_p0; + input [15:0]dfi_5_aw_col_p0; + input [255:0]dfi_5_dw_wrdata_p0; + input [31:0]dfi_5_dw_wrdata_mask_p0; + input [31:0]dfi_5_dw_wrdata_dbi_p0; + input [7:0]dfi_5_dw_wrdata_par_p0; + input [7:0]dfi_5_dw_wrdata_dq_en_p0; + input [7:0]dfi_5_dw_wrdata_par_en_p0; + input [1:0]dfi_5_aw_ck_p1; + input [1:0]dfi_5_aw_cke_p1; + input [11:0]dfi_5_aw_row_p1; + input [15:0]dfi_5_aw_col_p1; + input [255:0]dfi_5_dw_wrdata_p1; + input [31:0]dfi_5_dw_wrdata_mask_p1; + input [31:0]dfi_5_dw_wrdata_dbi_p1; + input [7:0]dfi_5_dw_wrdata_par_p1; + input [7:0]dfi_5_dw_wrdata_dq_en_p1; + input [7:0]dfi_5_dw_wrdata_par_en_p1; + input dfi_5_aw_ck_dis; + input dfi_5_lp_pwr_e_req; + input dfi_5_lp_sr_e_req; + input dfi_5_lp_pwr_x_req; + input dfi_5_aw_tx_indx_ld; + input dfi_5_dw_tx_indx_ld; + input dfi_5_dw_rx_indx_ld; + input dfi_5_ctrlupd_ack; + input dfi_5_phyupd_req; + input [7:0]dfi_5_dw_wrdata_dqs_p0; + input [7:0]dfi_5_dw_wrdata_dqs_p1; + input dfi_6_clk; + input dfi_6_rst_n; + input dfi_6_init_start; + input [1:0]dfi_6_aw_ck_p0; + input [1:0]dfi_6_aw_cke_p0; + input [11:0]dfi_6_aw_row_p0; + input [15:0]dfi_6_aw_col_p0; + input [255:0]dfi_6_dw_wrdata_p0; + input [31:0]dfi_6_dw_wrdata_mask_p0; + input [31:0]dfi_6_dw_wrdata_dbi_p0; + input [7:0]dfi_6_dw_wrdata_par_p0; + input [7:0]dfi_6_dw_wrdata_dq_en_p0; + input [7:0]dfi_6_dw_wrdata_par_en_p0; + input [1:0]dfi_6_aw_ck_p1; + input [1:0]dfi_6_aw_cke_p1; + input [11:0]dfi_6_aw_row_p1; + input [15:0]dfi_6_aw_col_p1; + input [255:0]dfi_6_dw_wrdata_p1; + input [31:0]dfi_6_dw_wrdata_mask_p1; + input [31:0]dfi_6_dw_wrdata_dbi_p1; + input [7:0]dfi_6_dw_wrdata_par_p1; + input [7:0]dfi_6_dw_wrdata_dq_en_p1; + input [7:0]dfi_6_dw_wrdata_par_en_p1; + input dfi_6_aw_ck_dis; + input dfi_6_lp_pwr_e_req; + input dfi_6_lp_sr_e_req; + input dfi_6_lp_pwr_x_req; + input dfi_6_aw_tx_indx_ld; + input dfi_6_dw_tx_indx_ld; + input dfi_6_dw_rx_indx_ld; + input dfi_6_ctrlupd_ack; + input dfi_6_phyupd_req; + input [7:0]dfi_6_dw_wrdata_dqs_p0; + input [7:0]dfi_6_dw_wrdata_dqs_p1; + input dfi_7_clk; + input dfi_7_rst_n; + input dfi_7_init_start; + input [1:0]dfi_7_aw_ck_p0; + input [1:0]dfi_7_aw_cke_p0; + input [11:0]dfi_7_aw_row_p0; + input [15:0]dfi_7_aw_col_p0; + input [255:0]dfi_7_dw_wrdata_p0; + input [31:0]dfi_7_dw_wrdata_mask_p0; + input [31:0]dfi_7_dw_wrdata_dbi_p0; + input [7:0]dfi_7_dw_wrdata_par_p0; + input [7:0]dfi_7_dw_wrdata_dq_en_p0; + input [7:0]dfi_7_dw_wrdata_par_en_p0; + input [1:0]dfi_7_aw_ck_p1; + input [1:0]dfi_7_aw_cke_p1; + input [11:0]dfi_7_aw_row_p1; + input [15:0]dfi_7_aw_col_p1; + input [255:0]dfi_7_dw_wrdata_p1; + input [31:0]dfi_7_dw_wrdata_mask_p1; + input [31:0]dfi_7_dw_wrdata_dbi_p1; + input [7:0]dfi_7_dw_wrdata_par_p1; + input [7:0]dfi_7_dw_wrdata_dq_en_p1; + input [7:0]dfi_7_dw_wrdata_par_en_p1; + input dfi_7_aw_ck_dis; + input dfi_7_lp_pwr_e_req; + input dfi_7_lp_sr_e_req; + input dfi_7_lp_pwr_x_req; + input dfi_7_aw_tx_indx_ld; + input dfi_7_dw_tx_indx_ld; + input dfi_7_dw_rx_indx_ld; + input dfi_7_ctrlupd_ack; + input dfi_7_phyupd_req; + input [7:0]dfi_7_dw_wrdata_dqs_p0; + input [7:0]dfi_7_dw_wrdata_dqs_p1; + input dfi_8_clk; + input dfi_8_rst_n; + input dfi_8_init_start; + input [1:0]dfi_8_aw_ck_p0; + input [1:0]dfi_8_aw_cke_p0; + input [11:0]dfi_8_aw_row_p0; + input [15:0]dfi_8_aw_col_p0; + input [255:0]dfi_8_dw_wrdata_p0; + input [31:0]dfi_8_dw_wrdata_mask_p0; + input [31:0]dfi_8_dw_wrdata_dbi_p0; + input [7:0]dfi_8_dw_wrdata_par_p0; + input [7:0]dfi_8_dw_wrdata_dq_en_p0; + input [7:0]dfi_8_dw_wrdata_par_en_p0; + input [1:0]dfi_8_aw_ck_p1; + input [1:0]dfi_8_aw_cke_p1; + input [11:0]dfi_8_aw_row_p1; + input [15:0]dfi_8_aw_col_p1; + input [255:0]dfi_8_dw_wrdata_p1; + input [31:0]dfi_8_dw_wrdata_mask_p1; + input [31:0]dfi_8_dw_wrdata_dbi_p1; + input [7:0]dfi_8_dw_wrdata_par_p1; + input [7:0]dfi_8_dw_wrdata_dq_en_p1; + input [7:0]dfi_8_dw_wrdata_par_en_p1; + input dfi_8_aw_ck_dis; + input dfi_8_lp_pwr_e_req; + input dfi_8_lp_sr_e_req; + input dfi_8_lp_pwr_x_req; + input dfi_8_aw_tx_indx_ld; + input dfi_8_dw_tx_indx_ld; + input dfi_8_dw_rx_indx_ld; + input dfi_8_ctrlupd_ack; + input dfi_8_phyupd_req; + input [7:0]dfi_8_dw_wrdata_dqs_p0; + input [7:0]dfi_8_dw_wrdata_dqs_p1; + input dfi_9_clk; + input dfi_9_rst_n; + input dfi_9_init_start; + input [1:0]dfi_9_aw_ck_p0; + input [1:0]dfi_9_aw_cke_p0; + input [11:0]dfi_9_aw_row_p0; + input [15:0]dfi_9_aw_col_p0; + input [255:0]dfi_9_dw_wrdata_p0; + input [31:0]dfi_9_dw_wrdata_mask_p0; + input [31:0]dfi_9_dw_wrdata_dbi_p0; + input [7:0]dfi_9_dw_wrdata_par_p0; + input [7:0]dfi_9_dw_wrdata_dq_en_p0; + input [7:0]dfi_9_dw_wrdata_par_en_p0; + input [1:0]dfi_9_aw_ck_p1; + input [1:0]dfi_9_aw_cke_p1; + input [11:0]dfi_9_aw_row_p1; + input [15:0]dfi_9_aw_col_p1; + input [255:0]dfi_9_dw_wrdata_p1; + input [31:0]dfi_9_dw_wrdata_mask_p1; + input [31:0]dfi_9_dw_wrdata_dbi_p1; + input [7:0]dfi_9_dw_wrdata_par_p1; + input [7:0]dfi_9_dw_wrdata_dq_en_p1; + input [7:0]dfi_9_dw_wrdata_par_en_p1; + input dfi_9_aw_ck_dis; + input dfi_9_lp_pwr_e_req; + input dfi_9_lp_sr_e_req; + input dfi_9_lp_pwr_x_req; + input dfi_9_aw_tx_indx_ld; + input dfi_9_dw_tx_indx_ld; + input dfi_9_dw_rx_indx_ld; + input dfi_9_ctrlupd_ack; + input dfi_9_phyupd_req; + input [7:0]dfi_9_dw_wrdata_dqs_p0; + input [7:0]dfi_9_dw_wrdata_dqs_p1; + input dfi_10_clk; + input dfi_10_rst_n; + input dfi_10_init_start; + input [1:0]dfi_10_aw_ck_p0; + input [1:0]dfi_10_aw_cke_p0; + input [11:0]dfi_10_aw_row_p0; + input [15:0]dfi_10_aw_col_p0; + input [255:0]dfi_10_dw_wrdata_p0; + input [31:0]dfi_10_dw_wrdata_mask_p0; + input [31:0]dfi_10_dw_wrdata_dbi_p0; + input [7:0]dfi_10_dw_wrdata_par_p0; + input [7:0]dfi_10_dw_wrdata_dq_en_p0; + input [7:0]dfi_10_dw_wrdata_par_en_p0; + input [1:0]dfi_10_aw_ck_p1; + input [1:0]dfi_10_aw_cke_p1; + input [11:0]dfi_10_aw_row_p1; + input [15:0]dfi_10_aw_col_p1; + input [255:0]dfi_10_dw_wrdata_p1; + input [31:0]dfi_10_dw_wrdata_mask_p1; + input [31:0]dfi_10_dw_wrdata_dbi_p1; + input [7:0]dfi_10_dw_wrdata_par_p1; + input [7:0]dfi_10_dw_wrdata_dq_en_p1; + input [7:0]dfi_10_dw_wrdata_par_en_p1; + input dfi_10_aw_ck_dis; + input dfi_10_lp_pwr_e_req; + input dfi_10_lp_sr_e_req; + input dfi_10_lp_pwr_x_req; + input dfi_10_aw_tx_indx_ld; + input dfi_10_dw_tx_indx_ld; + input dfi_10_dw_rx_indx_ld; + input dfi_10_ctrlupd_ack; + input dfi_10_phyupd_req; + input [7:0]dfi_10_dw_wrdata_dqs_p0; + input [7:0]dfi_10_dw_wrdata_dqs_p1; + input dfi_11_clk; + input dfi_11_rst_n; + input dfi_11_init_start; + input [1:0]dfi_11_aw_ck_p0; + input [1:0]dfi_11_aw_cke_p0; + input [11:0]dfi_11_aw_row_p0; + input [15:0]dfi_11_aw_col_p0; + input [255:0]dfi_11_dw_wrdata_p0; + input [31:0]dfi_11_dw_wrdata_mask_p0; + input [31:0]dfi_11_dw_wrdata_dbi_p0; + input [7:0]dfi_11_dw_wrdata_par_p0; + input [7:0]dfi_11_dw_wrdata_dq_en_p0; + input [7:0]dfi_11_dw_wrdata_par_en_p0; + input [1:0]dfi_11_aw_ck_p1; + input [1:0]dfi_11_aw_cke_p1; + input [11:0]dfi_11_aw_row_p1; + input [15:0]dfi_11_aw_col_p1; + input [255:0]dfi_11_dw_wrdata_p1; + input [31:0]dfi_11_dw_wrdata_mask_p1; + input [31:0]dfi_11_dw_wrdata_dbi_p1; + input [7:0]dfi_11_dw_wrdata_par_p1; + input [7:0]dfi_11_dw_wrdata_dq_en_p1; + input [7:0]dfi_11_dw_wrdata_par_en_p1; + input dfi_11_aw_ck_dis; + input dfi_11_lp_pwr_e_req; + input dfi_11_lp_sr_e_req; + input dfi_11_lp_pwr_x_req; + input dfi_11_aw_tx_indx_ld; + input dfi_11_dw_tx_indx_ld; + input dfi_11_dw_rx_indx_ld; + input dfi_11_ctrlupd_ack; + input dfi_11_phyupd_req; + input [7:0]dfi_11_dw_wrdata_dqs_p0; + input [7:0]dfi_11_dw_wrdata_dqs_p1; + input dfi_12_clk; + input dfi_12_rst_n; + input dfi_12_init_start; + input [1:0]dfi_12_aw_ck_p0; + input [1:0]dfi_12_aw_cke_p0; + input [11:0]dfi_12_aw_row_p0; + input [15:0]dfi_12_aw_col_p0; + input [255:0]dfi_12_dw_wrdata_p0; + input [31:0]dfi_12_dw_wrdata_mask_p0; + input [31:0]dfi_12_dw_wrdata_dbi_p0; + input [7:0]dfi_12_dw_wrdata_par_p0; + input [7:0]dfi_12_dw_wrdata_dq_en_p0; + input [7:0]dfi_12_dw_wrdata_par_en_p0; + input [1:0]dfi_12_aw_ck_p1; + input [1:0]dfi_12_aw_cke_p1; + input [11:0]dfi_12_aw_row_p1; + input [15:0]dfi_12_aw_col_p1; + input [255:0]dfi_12_dw_wrdata_p1; + input [31:0]dfi_12_dw_wrdata_mask_p1; + input [31:0]dfi_12_dw_wrdata_dbi_p1; + input [7:0]dfi_12_dw_wrdata_par_p1; + input [7:0]dfi_12_dw_wrdata_dq_en_p1; + input [7:0]dfi_12_dw_wrdata_par_en_p1; + input dfi_12_aw_ck_dis; + input dfi_12_lp_pwr_e_req; + input dfi_12_lp_sr_e_req; + input dfi_12_lp_pwr_x_req; + input dfi_12_aw_tx_indx_ld; + input dfi_12_dw_tx_indx_ld; + input dfi_12_dw_rx_indx_ld; + input dfi_12_ctrlupd_ack; + input dfi_12_phyupd_req; + input [7:0]dfi_12_dw_wrdata_dqs_p0; + input [7:0]dfi_12_dw_wrdata_dqs_p1; + input dfi_13_clk; + input dfi_13_rst_n; + input dfi_13_init_start; + input [1:0]dfi_13_aw_ck_p0; + input [1:0]dfi_13_aw_cke_p0; + input [11:0]dfi_13_aw_row_p0; + input [15:0]dfi_13_aw_col_p0; + input [255:0]dfi_13_dw_wrdata_p0; + input [31:0]dfi_13_dw_wrdata_mask_p0; + input [31:0]dfi_13_dw_wrdata_dbi_p0; + input [7:0]dfi_13_dw_wrdata_par_p0; + input [7:0]dfi_13_dw_wrdata_dq_en_p0; + input [7:0]dfi_13_dw_wrdata_par_en_p0; + input [1:0]dfi_13_aw_ck_p1; + input [1:0]dfi_13_aw_cke_p1; + input [11:0]dfi_13_aw_row_p1; + input [15:0]dfi_13_aw_col_p1; + input [255:0]dfi_13_dw_wrdata_p1; + input [31:0]dfi_13_dw_wrdata_mask_p1; + input [31:0]dfi_13_dw_wrdata_dbi_p1; + input [7:0]dfi_13_dw_wrdata_par_p1; + input [7:0]dfi_13_dw_wrdata_dq_en_p1; + input [7:0]dfi_13_dw_wrdata_par_en_p1; + input dfi_13_aw_ck_dis; + input dfi_13_lp_pwr_e_req; + input dfi_13_lp_sr_e_req; + input dfi_13_lp_pwr_x_req; + input dfi_13_aw_tx_indx_ld; + input dfi_13_dw_tx_indx_ld; + input dfi_13_dw_rx_indx_ld; + input dfi_13_ctrlupd_ack; + input dfi_13_phyupd_req; + input [7:0]dfi_13_dw_wrdata_dqs_p0; + input [7:0]dfi_13_dw_wrdata_dqs_p1; + input dfi_14_clk; + input dfi_14_rst_n; + input dfi_14_init_start; + input [1:0]dfi_14_aw_ck_p0; + input [1:0]dfi_14_aw_cke_p0; + input [11:0]dfi_14_aw_row_p0; + input [15:0]dfi_14_aw_col_p0; + input [255:0]dfi_14_dw_wrdata_p0; + input [31:0]dfi_14_dw_wrdata_mask_p0; + input [31:0]dfi_14_dw_wrdata_dbi_p0; + input [7:0]dfi_14_dw_wrdata_par_p0; + input [7:0]dfi_14_dw_wrdata_dq_en_p0; + input [7:0]dfi_14_dw_wrdata_par_en_p0; + input [1:0]dfi_14_aw_ck_p1; + input [1:0]dfi_14_aw_cke_p1; + input [11:0]dfi_14_aw_row_p1; + input [15:0]dfi_14_aw_col_p1; + input [255:0]dfi_14_dw_wrdata_p1; + input [31:0]dfi_14_dw_wrdata_mask_p1; + input [31:0]dfi_14_dw_wrdata_dbi_p1; + input [7:0]dfi_14_dw_wrdata_par_p1; + input [7:0]dfi_14_dw_wrdata_dq_en_p1; + input [7:0]dfi_14_dw_wrdata_par_en_p1; + input dfi_14_aw_ck_dis; + input dfi_14_lp_pwr_e_req; + input dfi_14_lp_sr_e_req; + input dfi_14_lp_pwr_x_req; + input dfi_14_aw_tx_indx_ld; + input dfi_14_dw_tx_indx_ld; + input dfi_14_dw_rx_indx_ld; + input dfi_14_ctrlupd_ack; + input dfi_14_phyupd_req; + input [7:0]dfi_14_dw_wrdata_dqs_p0; + input [7:0]dfi_14_dw_wrdata_dqs_p1; + input dfi_15_clk; + input dfi_15_rst_n; + input dfi_15_init_start; + input [1:0]dfi_15_aw_ck_p0; + input [1:0]dfi_15_aw_cke_p0; + input [11:0]dfi_15_aw_row_p0; + input [15:0]dfi_15_aw_col_p0; + input [255:0]dfi_15_dw_wrdata_p0; + input [31:0]dfi_15_dw_wrdata_mask_p0; + input [31:0]dfi_15_dw_wrdata_dbi_p0; + input [7:0]dfi_15_dw_wrdata_par_p0; + input [7:0]dfi_15_dw_wrdata_dq_en_p0; + input [7:0]dfi_15_dw_wrdata_par_en_p0; + input [1:0]dfi_15_aw_ck_p1; + input [1:0]dfi_15_aw_cke_p1; + input [11:0]dfi_15_aw_row_p1; + input [15:0]dfi_15_aw_col_p1; + input [255:0]dfi_15_dw_wrdata_p1; + input [31:0]dfi_15_dw_wrdata_mask_p1; + input [31:0]dfi_15_dw_wrdata_dbi_p1; + input [7:0]dfi_15_dw_wrdata_par_p1; + input [7:0]dfi_15_dw_wrdata_dq_en_p1; + input [7:0]dfi_15_dw_wrdata_par_en_p1; + input dfi_15_aw_ck_dis; + input dfi_15_lp_pwr_e_req; + input dfi_15_lp_sr_e_req; + input dfi_15_lp_pwr_x_req; + input dfi_15_aw_tx_indx_ld; + input dfi_15_dw_tx_indx_ld; + input dfi_15_dw_rx_indx_ld; + input dfi_15_ctrlupd_ack; + input dfi_15_phyupd_req; + input [7:0]dfi_15_dw_wrdata_dqs_p0; + input [7:0]dfi_15_dw_wrdata_dqs_p1; + input APB_0_PCLK; + input APB_0_PRESET_N; + input APB_1_PCLK; + input APB_1_PRESET_N; + output [255:0]dfi_0_dw_rddata_p0; + output [31:0]dfi_0_dw_rddata_dm_p0; + output [31:0]dfi_0_dw_rddata_dbi_p0; + output [7:0]dfi_0_dw_rddata_par_p0; + output [255:0]dfi_0_dw_rddata_p1; + output [31:0]dfi_0_dw_rddata_dm_p1; + output [31:0]dfi_0_dw_rddata_dbi_p1; + output [7:0]dfi_0_dw_rddata_par_p1; + output [15:0]dfi_0_dbi_byte_disable; + output [3:0]dfi_0_dw_rddata_valid; + output [7:0]dfi_0_dw_derr_n; + output [1:0]dfi_0_aw_aerr_n; + output dfi_0_ctrlupd_req; + output dfi_0_phyupd_ack; + output dfi_0_clk_init; + output dfi_0_init_complete; + output dfi_0_out_rst_n; + output [255:0]dfi_1_dw_rddata_p0; + output [31:0]dfi_1_dw_rddata_dm_p0; + output [31:0]dfi_1_dw_rddata_dbi_p0; + output [7:0]dfi_1_dw_rddata_par_p0; + output [255:0]dfi_1_dw_rddata_p1; + output [31:0]dfi_1_dw_rddata_dm_p1; + output [31:0]dfi_1_dw_rddata_dbi_p1; + output [7:0]dfi_1_dw_rddata_par_p1; + output [15:0]dfi_1_dbi_byte_disable; + output [3:0]dfi_1_dw_rddata_valid; + output [7:0]dfi_1_dw_derr_n; + output [1:0]dfi_1_aw_aerr_n; + output dfi_1_ctrlupd_req; + output dfi_1_phyupd_ack; + output dfi_1_clk_init; + output dfi_1_init_complete; + output dfi_1_out_rst_n; + output [255:0]dfi_2_dw_rddata_p0; + output [31:0]dfi_2_dw_rddata_dm_p0; + output [31:0]dfi_2_dw_rddata_dbi_p0; + output [7:0]dfi_2_dw_rddata_par_p0; + output [255:0]dfi_2_dw_rddata_p1; + output [31:0]dfi_2_dw_rddata_dm_p1; + output [31:0]dfi_2_dw_rddata_dbi_p1; + output [7:0]dfi_2_dw_rddata_par_p1; + output [15:0]dfi_2_dbi_byte_disable; + output [3:0]dfi_2_dw_rddata_valid; + output [7:0]dfi_2_dw_derr_n; + output [1:0]dfi_2_aw_aerr_n; + output dfi_2_ctrlupd_req; + output dfi_2_phyupd_ack; + output dfi_2_clk_init; + output dfi_2_init_complete; + output dfi_2_out_rst_n; + output [255:0]dfi_3_dw_rddata_p0; + output [31:0]dfi_3_dw_rddata_dm_p0; + output [31:0]dfi_3_dw_rddata_dbi_p0; + output [7:0]dfi_3_dw_rddata_par_p0; + output [255:0]dfi_3_dw_rddata_p1; + output [31:0]dfi_3_dw_rddata_dm_p1; + output [31:0]dfi_3_dw_rddata_dbi_p1; + output [7:0]dfi_3_dw_rddata_par_p1; + output [15:0]dfi_3_dbi_byte_disable; + output [3:0]dfi_3_dw_rddata_valid; + output [7:0]dfi_3_dw_derr_n; + output [1:0]dfi_3_aw_aerr_n; + output dfi_3_ctrlupd_req; + output dfi_3_phyupd_ack; + output dfi_3_clk_init; + output dfi_3_init_complete; + output dfi_3_out_rst_n; + output [255:0]dfi_4_dw_rddata_p0; + output [31:0]dfi_4_dw_rddata_dm_p0; + output [31:0]dfi_4_dw_rddata_dbi_p0; + output [7:0]dfi_4_dw_rddata_par_p0; + output [255:0]dfi_4_dw_rddata_p1; + output [31:0]dfi_4_dw_rddata_dm_p1; + output [31:0]dfi_4_dw_rddata_dbi_p1; + output [7:0]dfi_4_dw_rddata_par_p1; + output [15:0]dfi_4_dbi_byte_disable; + output [3:0]dfi_4_dw_rddata_valid; + output [7:0]dfi_4_dw_derr_n; + output [1:0]dfi_4_aw_aerr_n; + output dfi_4_ctrlupd_req; + output dfi_4_phyupd_ack; + output dfi_4_clk_init; + output dfi_4_init_complete; + output dfi_4_out_rst_n; + output [255:0]dfi_5_dw_rddata_p0; + output [31:0]dfi_5_dw_rddata_dm_p0; + output [31:0]dfi_5_dw_rddata_dbi_p0; + output [7:0]dfi_5_dw_rddata_par_p0; + output [255:0]dfi_5_dw_rddata_p1; + output [31:0]dfi_5_dw_rddata_dm_p1; + output [31:0]dfi_5_dw_rddata_dbi_p1; + output [7:0]dfi_5_dw_rddata_par_p1; + output [15:0]dfi_5_dbi_byte_disable; + output [3:0]dfi_5_dw_rddata_valid; + output [7:0]dfi_5_dw_derr_n; + output [1:0]dfi_5_aw_aerr_n; + output dfi_5_ctrlupd_req; + output dfi_5_phyupd_ack; + output dfi_5_clk_init; + output dfi_5_init_complete; + output dfi_5_out_rst_n; + output [255:0]dfi_6_dw_rddata_p0; + output [31:0]dfi_6_dw_rddata_dm_p0; + output [31:0]dfi_6_dw_rddata_dbi_p0; + output [7:0]dfi_6_dw_rddata_par_p0; + output [255:0]dfi_6_dw_rddata_p1; + output [31:0]dfi_6_dw_rddata_dm_p1; + output [31:0]dfi_6_dw_rddata_dbi_p1; + output [7:0]dfi_6_dw_rddata_par_p1; + output [15:0]dfi_6_dbi_byte_disable; + output [3:0]dfi_6_dw_rddata_valid; + output [7:0]dfi_6_dw_derr_n; + output [1:0]dfi_6_aw_aerr_n; + output dfi_6_ctrlupd_req; + output dfi_6_phyupd_ack; + output dfi_6_clk_init; + output dfi_6_init_complete; + output dfi_6_out_rst_n; + output [255:0]dfi_7_dw_rddata_p0; + output [31:0]dfi_7_dw_rddata_dm_p0; + output [31:0]dfi_7_dw_rddata_dbi_p0; + output [7:0]dfi_7_dw_rddata_par_p0; + output [255:0]dfi_7_dw_rddata_p1; + output [31:0]dfi_7_dw_rddata_dm_p1; + output [31:0]dfi_7_dw_rddata_dbi_p1; + output [7:0]dfi_7_dw_rddata_par_p1; + output [15:0]dfi_7_dbi_byte_disable; + output [3:0]dfi_7_dw_rddata_valid; + output [7:0]dfi_7_dw_derr_n; + output [1:0]dfi_7_aw_aerr_n; + output dfi_7_ctrlupd_req; + output dfi_7_phyupd_ack; + output dfi_7_clk_init; + output dfi_7_init_complete; + output dfi_7_out_rst_n; + output [255:0]dfi_8_dw_rddata_p0; + output [31:0]dfi_8_dw_rddata_dm_p0; + output [31:0]dfi_8_dw_rddata_dbi_p0; + output [7:0]dfi_8_dw_rddata_par_p0; + output [255:0]dfi_8_dw_rddata_p1; + output [31:0]dfi_8_dw_rddata_dm_p1; + output [31:0]dfi_8_dw_rddata_dbi_p1; + output [7:0]dfi_8_dw_rddata_par_p1; + output [15:0]dfi_8_dbi_byte_disable; + output [3:0]dfi_8_dw_rddata_valid; + output [7:0]dfi_8_dw_derr_n; + output [1:0]dfi_8_aw_aerr_n; + output dfi_8_ctrlupd_req; + output dfi_8_phyupd_ack; + output dfi_8_clk_init; + output dfi_8_init_complete; + output dfi_8_out_rst_n; + output [255:0]dfi_9_dw_rddata_p0; + output [31:0]dfi_9_dw_rddata_dm_p0; + output [31:0]dfi_9_dw_rddata_dbi_p0; + output [7:0]dfi_9_dw_rddata_par_p0; + output [255:0]dfi_9_dw_rddata_p1; + output [31:0]dfi_9_dw_rddata_dm_p1; + output [31:0]dfi_9_dw_rddata_dbi_p1; + output [7:0]dfi_9_dw_rddata_par_p1; + output [15:0]dfi_9_dbi_byte_disable; + output [3:0]dfi_9_dw_rddata_valid; + output [7:0]dfi_9_dw_derr_n; + output [1:0]dfi_9_aw_aerr_n; + output dfi_9_ctrlupd_req; + output dfi_9_phyupd_ack; + output dfi_9_clk_init; + output dfi_9_init_complete; + output dfi_9_out_rst_n; + output [255:0]dfi_10_dw_rddata_p0; + output [31:0]dfi_10_dw_rddata_dm_p0; + output [31:0]dfi_10_dw_rddata_dbi_p0; + output [7:0]dfi_10_dw_rddata_par_p0; + output [255:0]dfi_10_dw_rddata_p1; + output [31:0]dfi_10_dw_rddata_dm_p1; + output [31:0]dfi_10_dw_rddata_dbi_p1; + output [7:0]dfi_10_dw_rddata_par_p1; + output [15:0]dfi_10_dbi_byte_disable; + output [3:0]dfi_10_dw_rddata_valid; + output [7:0]dfi_10_dw_derr_n; + output [1:0]dfi_10_aw_aerr_n; + output dfi_10_ctrlupd_req; + output dfi_10_phyupd_ack; + output dfi_10_clk_init; + output dfi_10_init_complete; + output dfi_10_out_rst_n; + output [255:0]dfi_11_dw_rddata_p0; + output [31:0]dfi_11_dw_rddata_dm_p0; + output [31:0]dfi_11_dw_rddata_dbi_p0; + output [7:0]dfi_11_dw_rddata_par_p0; + output [255:0]dfi_11_dw_rddata_p1; + output [31:0]dfi_11_dw_rddata_dm_p1; + output [31:0]dfi_11_dw_rddata_dbi_p1; + output [7:0]dfi_11_dw_rddata_par_p1; + output [15:0]dfi_11_dbi_byte_disable; + output [3:0]dfi_11_dw_rddata_valid; + output [7:0]dfi_11_dw_derr_n; + output [1:0]dfi_11_aw_aerr_n; + output dfi_11_ctrlupd_req; + output dfi_11_phyupd_ack; + output dfi_11_clk_init; + output dfi_11_init_complete; + output dfi_11_out_rst_n; + output [255:0]dfi_12_dw_rddata_p0; + output [31:0]dfi_12_dw_rddata_dm_p0; + output [31:0]dfi_12_dw_rddata_dbi_p0; + output [7:0]dfi_12_dw_rddata_par_p0; + output [255:0]dfi_12_dw_rddata_p1; + output [31:0]dfi_12_dw_rddata_dm_p1; + output [31:0]dfi_12_dw_rddata_dbi_p1; + output [7:0]dfi_12_dw_rddata_par_p1; + output [15:0]dfi_12_dbi_byte_disable; + output [3:0]dfi_12_dw_rddata_valid; + output [7:0]dfi_12_dw_derr_n; + output [1:0]dfi_12_aw_aerr_n; + output dfi_12_ctrlupd_req; + output dfi_12_phyupd_ack; + output dfi_12_clk_init; + output dfi_12_init_complete; + output dfi_12_out_rst_n; + output [255:0]dfi_13_dw_rddata_p0; + output [31:0]dfi_13_dw_rddata_dm_p0; + output [31:0]dfi_13_dw_rddata_dbi_p0; + output [7:0]dfi_13_dw_rddata_par_p0; + output [255:0]dfi_13_dw_rddata_p1; + output [31:0]dfi_13_dw_rddata_dm_p1; + output [31:0]dfi_13_dw_rddata_dbi_p1; + output [7:0]dfi_13_dw_rddata_par_p1; + output [15:0]dfi_13_dbi_byte_disable; + output [3:0]dfi_13_dw_rddata_valid; + output [7:0]dfi_13_dw_derr_n; + output [1:0]dfi_13_aw_aerr_n; + output dfi_13_ctrlupd_req; + output dfi_13_phyupd_ack; + output dfi_13_clk_init; + output dfi_13_init_complete; + output dfi_13_out_rst_n; + output [255:0]dfi_14_dw_rddata_p0; + output [31:0]dfi_14_dw_rddata_dm_p0; + output [31:0]dfi_14_dw_rddata_dbi_p0; + output [7:0]dfi_14_dw_rddata_par_p0; + output [255:0]dfi_14_dw_rddata_p1; + output [31:0]dfi_14_dw_rddata_dm_p1; + output [31:0]dfi_14_dw_rddata_dbi_p1; + output [7:0]dfi_14_dw_rddata_par_p1; + output [15:0]dfi_14_dbi_byte_disable; + output [3:0]dfi_14_dw_rddata_valid; + output [7:0]dfi_14_dw_derr_n; + output [1:0]dfi_14_aw_aerr_n; + output dfi_14_ctrlupd_req; + output dfi_14_phyupd_ack; + output dfi_14_clk_init; + output dfi_14_init_complete; + output dfi_14_out_rst_n; + output [255:0]dfi_15_dw_rddata_p0; + output [31:0]dfi_15_dw_rddata_dm_p0; + output [31:0]dfi_15_dw_rddata_dbi_p0; + output [7:0]dfi_15_dw_rddata_par_p0; + output [255:0]dfi_15_dw_rddata_p1; + output [31:0]dfi_15_dw_rddata_dm_p1; + output [31:0]dfi_15_dw_rddata_dbi_p1; + output [7:0]dfi_15_dw_rddata_par_p1; + output [15:0]dfi_15_dbi_byte_disable; + output [3:0]dfi_15_dw_rddata_valid; + output [7:0]dfi_15_dw_derr_n; + output [1:0]dfi_15_aw_aerr_n; + output dfi_15_ctrlupd_req; + output dfi_15_phyupd_ack; + output dfi_15_clk_init; + output dfi_15_init_complete; + output dfi_15_out_rst_n; + output apb_complete_0; + output apb_complete_1; + output DRAM_0_STAT_CATTRIP; + output [6:0]DRAM_0_STAT_TEMP; + output DRAM_1_STAT_CATTRIP; + output [6:0]DRAM_1_STAT_TEMP; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.vhdl new file mode 100644 index 0000000..4da8c2a --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/hbm_0/hbm_0_stub.vhdl @@ -0,0 +1,857 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:36:26 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/hbm_0/hbm_0_stub.vhdl +-- Design : hbm_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity hbm_0 is + Port ( + HBM_REF_CLK_0 : in STD_LOGIC; + HBM_REF_CLK_1 : in STD_LOGIC; + dfi_0_clk : in STD_LOGIC; + dfi_0_rst_n : in STD_LOGIC; + dfi_0_init_start : in STD_LOGIC; + dfi_0_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_0_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_0_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_0_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_0_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_0_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_0_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_0_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_0_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_0_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_0_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_aw_ck_dis : in STD_LOGIC; + dfi_0_lp_pwr_e_req : in STD_LOGIC; + dfi_0_lp_sr_e_req : in STD_LOGIC; + dfi_0_lp_pwr_x_req : in STD_LOGIC; + dfi_0_aw_tx_indx_ld : in STD_LOGIC; + dfi_0_dw_tx_indx_ld : in STD_LOGIC; + dfi_0_dw_rx_indx_ld : in STD_LOGIC; + dfi_0_ctrlupd_ack : in STD_LOGIC; + dfi_0_phyupd_req : in STD_LOGIC; + dfi_0_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_clk : in STD_LOGIC; + dfi_1_rst_n : in STD_LOGIC; + dfi_1_init_start : in STD_LOGIC; + dfi_1_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_1_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_1_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_1_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_1_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_1_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_1_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_1_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_1_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_1_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_1_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_aw_ck_dis : in STD_LOGIC; + dfi_1_lp_pwr_e_req : in STD_LOGIC; + dfi_1_lp_sr_e_req : in STD_LOGIC; + dfi_1_lp_pwr_x_req : in STD_LOGIC; + dfi_1_aw_tx_indx_ld : in STD_LOGIC; + dfi_1_dw_tx_indx_ld : in STD_LOGIC; + dfi_1_dw_rx_indx_ld : in STD_LOGIC; + dfi_1_ctrlupd_ack : in STD_LOGIC; + dfi_1_phyupd_req : in STD_LOGIC; + dfi_1_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_clk : in STD_LOGIC; + dfi_2_rst_n : in STD_LOGIC; + dfi_2_init_start : in STD_LOGIC; + dfi_2_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_2_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_2_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_2_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_2_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_2_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_2_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_2_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_2_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_2_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_2_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_aw_ck_dis : in STD_LOGIC; + dfi_2_lp_pwr_e_req : in STD_LOGIC; + dfi_2_lp_sr_e_req : in STD_LOGIC; + dfi_2_lp_pwr_x_req : in STD_LOGIC; + dfi_2_aw_tx_indx_ld : in STD_LOGIC; + dfi_2_dw_tx_indx_ld : in STD_LOGIC; + dfi_2_dw_rx_indx_ld : in STD_LOGIC; + dfi_2_ctrlupd_ack : in STD_LOGIC; + dfi_2_phyupd_req : in STD_LOGIC; + dfi_2_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_clk : in STD_LOGIC; + dfi_3_rst_n : in STD_LOGIC; + dfi_3_init_start : in STD_LOGIC; + dfi_3_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_3_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_3_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_3_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_3_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_3_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_3_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_3_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_3_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_3_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_3_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_aw_ck_dis : in STD_LOGIC; + dfi_3_lp_pwr_e_req : in STD_LOGIC; + dfi_3_lp_sr_e_req : in STD_LOGIC; + dfi_3_lp_pwr_x_req : in STD_LOGIC; + dfi_3_aw_tx_indx_ld : in STD_LOGIC; + dfi_3_dw_tx_indx_ld : in STD_LOGIC; + dfi_3_dw_rx_indx_ld : in STD_LOGIC; + dfi_3_ctrlupd_ack : in STD_LOGIC; + dfi_3_phyupd_req : in STD_LOGIC; + dfi_3_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_clk : in STD_LOGIC; + dfi_4_rst_n : in STD_LOGIC; + dfi_4_init_start : in STD_LOGIC; + dfi_4_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_4_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_4_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_4_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_4_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_4_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_4_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_4_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_4_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_4_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_4_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_aw_ck_dis : in STD_LOGIC; + dfi_4_lp_pwr_e_req : in STD_LOGIC; + dfi_4_lp_sr_e_req : in STD_LOGIC; + dfi_4_lp_pwr_x_req : in STD_LOGIC; + dfi_4_aw_tx_indx_ld : in STD_LOGIC; + dfi_4_dw_tx_indx_ld : in STD_LOGIC; + dfi_4_dw_rx_indx_ld : in STD_LOGIC; + dfi_4_ctrlupd_ack : in STD_LOGIC; + dfi_4_phyupd_req : in STD_LOGIC; + dfi_4_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_clk : in STD_LOGIC; + dfi_5_rst_n : in STD_LOGIC; + dfi_5_init_start : in STD_LOGIC; + dfi_5_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_5_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_5_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_5_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_5_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_5_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_5_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_5_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_5_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_5_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_5_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_aw_ck_dis : in STD_LOGIC; + dfi_5_lp_pwr_e_req : in STD_LOGIC; + dfi_5_lp_sr_e_req : in STD_LOGIC; + dfi_5_lp_pwr_x_req : in STD_LOGIC; + dfi_5_aw_tx_indx_ld : in STD_LOGIC; + dfi_5_dw_tx_indx_ld : in STD_LOGIC; + dfi_5_dw_rx_indx_ld : in STD_LOGIC; + dfi_5_ctrlupd_ack : in STD_LOGIC; + dfi_5_phyupd_req : in STD_LOGIC; + dfi_5_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_clk : in STD_LOGIC; + dfi_6_rst_n : in STD_LOGIC; + dfi_6_init_start : in STD_LOGIC; + dfi_6_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_6_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_6_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_6_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_6_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_6_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_6_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_6_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_6_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_6_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_6_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_aw_ck_dis : in STD_LOGIC; + dfi_6_lp_pwr_e_req : in STD_LOGIC; + dfi_6_lp_sr_e_req : in STD_LOGIC; + dfi_6_lp_pwr_x_req : in STD_LOGIC; + dfi_6_aw_tx_indx_ld : in STD_LOGIC; + dfi_6_dw_tx_indx_ld : in STD_LOGIC; + dfi_6_dw_rx_indx_ld : in STD_LOGIC; + dfi_6_ctrlupd_ack : in STD_LOGIC; + dfi_6_phyupd_req : in STD_LOGIC; + dfi_6_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_clk : in STD_LOGIC; + dfi_7_rst_n : in STD_LOGIC; + dfi_7_init_start : in STD_LOGIC; + dfi_7_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_7_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_7_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_7_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_7_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_7_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_7_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_7_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_7_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_7_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_7_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_aw_ck_dis : in STD_LOGIC; + dfi_7_lp_pwr_e_req : in STD_LOGIC; + dfi_7_lp_sr_e_req : in STD_LOGIC; + dfi_7_lp_pwr_x_req : in STD_LOGIC; + dfi_7_aw_tx_indx_ld : in STD_LOGIC; + dfi_7_dw_tx_indx_ld : in STD_LOGIC; + dfi_7_dw_rx_indx_ld : in STD_LOGIC; + dfi_7_ctrlupd_ack : in STD_LOGIC; + dfi_7_phyupd_req : in STD_LOGIC; + dfi_7_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_clk : in STD_LOGIC; + dfi_8_rst_n : in STD_LOGIC; + dfi_8_init_start : in STD_LOGIC; + dfi_8_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_8_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_8_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_8_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_8_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_8_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_8_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_8_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_8_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_8_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_8_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_aw_ck_dis : in STD_LOGIC; + dfi_8_lp_pwr_e_req : in STD_LOGIC; + dfi_8_lp_sr_e_req : in STD_LOGIC; + dfi_8_lp_pwr_x_req : in STD_LOGIC; + dfi_8_aw_tx_indx_ld : in STD_LOGIC; + dfi_8_dw_tx_indx_ld : in STD_LOGIC; + dfi_8_dw_rx_indx_ld : in STD_LOGIC; + dfi_8_ctrlupd_ack : in STD_LOGIC; + dfi_8_phyupd_req : in STD_LOGIC; + dfi_8_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_clk : in STD_LOGIC; + dfi_9_rst_n : in STD_LOGIC; + dfi_9_init_start : in STD_LOGIC; + dfi_9_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_9_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_9_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_9_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_9_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_9_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_9_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_9_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_9_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_9_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_9_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_aw_ck_dis : in STD_LOGIC; + dfi_9_lp_pwr_e_req : in STD_LOGIC; + dfi_9_lp_sr_e_req : in STD_LOGIC; + dfi_9_lp_pwr_x_req : in STD_LOGIC; + dfi_9_aw_tx_indx_ld : in STD_LOGIC; + dfi_9_dw_tx_indx_ld : in STD_LOGIC; + dfi_9_dw_rx_indx_ld : in STD_LOGIC; + dfi_9_ctrlupd_ack : in STD_LOGIC; + dfi_9_phyupd_req : in STD_LOGIC; + dfi_9_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_clk : in STD_LOGIC; + dfi_10_rst_n : in STD_LOGIC; + dfi_10_init_start : in STD_LOGIC; + dfi_10_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_10_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_10_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_10_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_10_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_10_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_10_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_10_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_10_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_10_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_10_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_aw_ck_dis : in STD_LOGIC; + dfi_10_lp_pwr_e_req : in STD_LOGIC; + dfi_10_lp_sr_e_req : in STD_LOGIC; + dfi_10_lp_pwr_x_req : in STD_LOGIC; + dfi_10_aw_tx_indx_ld : in STD_LOGIC; + dfi_10_dw_tx_indx_ld : in STD_LOGIC; + dfi_10_dw_rx_indx_ld : in STD_LOGIC; + dfi_10_ctrlupd_ack : in STD_LOGIC; + dfi_10_phyupd_req : in STD_LOGIC; + dfi_10_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_clk : in STD_LOGIC; + dfi_11_rst_n : in STD_LOGIC; + dfi_11_init_start : in STD_LOGIC; + dfi_11_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_11_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_11_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_11_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_11_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_11_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_11_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_11_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_11_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_11_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_11_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_aw_ck_dis : in STD_LOGIC; + dfi_11_lp_pwr_e_req : in STD_LOGIC; + dfi_11_lp_sr_e_req : in STD_LOGIC; + dfi_11_lp_pwr_x_req : in STD_LOGIC; + dfi_11_aw_tx_indx_ld : in STD_LOGIC; + dfi_11_dw_tx_indx_ld : in STD_LOGIC; + dfi_11_dw_rx_indx_ld : in STD_LOGIC; + dfi_11_ctrlupd_ack : in STD_LOGIC; + dfi_11_phyupd_req : in STD_LOGIC; + dfi_11_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_clk : in STD_LOGIC; + dfi_12_rst_n : in STD_LOGIC; + dfi_12_init_start : in STD_LOGIC; + dfi_12_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_12_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_12_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_12_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_12_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_12_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_12_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_12_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_12_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_12_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_12_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_aw_ck_dis : in STD_LOGIC; + dfi_12_lp_pwr_e_req : in STD_LOGIC; + dfi_12_lp_sr_e_req : in STD_LOGIC; + dfi_12_lp_pwr_x_req : in STD_LOGIC; + dfi_12_aw_tx_indx_ld : in STD_LOGIC; + dfi_12_dw_tx_indx_ld : in STD_LOGIC; + dfi_12_dw_rx_indx_ld : in STD_LOGIC; + dfi_12_ctrlupd_ack : in STD_LOGIC; + dfi_12_phyupd_req : in STD_LOGIC; + dfi_12_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_clk : in STD_LOGIC; + dfi_13_rst_n : in STD_LOGIC; + dfi_13_init_start : in STD_LOGIC; + dfi_13_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_13_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_13_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_13_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_13_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_13_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_13_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_13_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_13_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_13_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_13_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_aw_ck_dis : in STD_LOGIC; + dfi_13_lp_pwr_e_req : in STD_LOGIC; + dfi_13_lp_sr_e_req : in STD_LOGIC; + dfi_13_lp_pwr_x_req : in STD_LOGIC; + dfi_13_aw_tx_indx_ld : in STD_LOGIC; + dfi_13_dw_tx_indx_ld : in STD_LOGIC; + dfi_13_dw_rx_indx_ld : in STD_LOGIC; + dfi_13_ctrlupd_ack : in STD_LOGIC; + dfi_13_phyupd_req : in STD_LOGIC; + dfi_13_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_clk : in STD_LOGIC; + dfi_14_rst_n : in STD_LOGIC; + dfi_14_init_start : in STD_LOGIC; + dfi_14_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_14_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_14_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_14_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_14_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_14_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_14_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_14_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_14_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_14_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_14_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_aw_ck_dis : in STD_LOGIC; + dfi_14_lp_pwr_e_req : in STD_LOGIC; + dfi_14_lp_sr_e_req : in STD_LOGIC; + dfi_14_lp_pwr_x_req : in STD_LOGIC; + dfi_14_aw_tx_indx_ld : in STD_LOGIC; + dfi_14_dw_tx_indx_ld : in STD_LOGIC; + dfi_14_dw_rx_indx_ld : in STD_LOGIC; + dfi_14_ctrlupd_ack : in STD_LOGIC; + dfi_14_phyupd_req : in STD_LOGIC; + dfi_14_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_clk : in STD_LOGIC; + dfi_15_rst_n : in STD_LOGIC; + dfi_15_init_start : in STD_LOGIC; + dfi_15_aw_ck_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_15_aw_cke_p0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_15_aw_row_p0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_15_aw_col_p0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_15_dw_wrdata_p0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_15_dw_wrdata_mask_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_wrdata_dbi_p0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_wrdata_par_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_wrdata_dq_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_wrdata_par_en_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_aw_ck_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_15_aw_cke_p1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_15_aw_row_p1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dfi_15_aw_col_p1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_15_dw_wrdata_p1 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_15_dw_wrdata_mask_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_wrdata_dbi_p1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_wrdata_par_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_wrdata_dq_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_wrdata_par_en_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_aw_ck_dis : in STD_LOGIC; + dfi_15_lp_pwr_e_req : in STD_LOGIC; + dfi_15_lp_sr_e_req : in STD_LOGIC; + dfi_15_lp_pwr_x_req : in STD_LOGIC; + dfi_15_aw_tx_indx_ld : in STD_LOGIC; + dfi_15_dw_tx_indx_ld : in STD_LOGIC; + dfi_15_dw_rx_indx_ld : in STD_LOGIC; + dfi_15_ctrlupd_ack : in STD_LOGIC; + dfi_15_phyupd_req : in STD_LOGIC; + dfi_15_dw_wrdata_dqs_p0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_wrdata_dqs_p1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + APB_0_PCLK : in STD_LOGIC; + APB_0_PRESET_N : in STD_LOGIC; + APB_1_PCLK : in STD_LOGIC; + APB_1_PRESET_N : in STD_LOGIC; + dfi_0_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_0_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_0_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_0_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_0_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_0_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_0_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_0_ctrlupd_req : out STD_LOGIC; + dfi_0_phyupd_ack : out STD_LOGIC; + dfi_0_clk_init : out STD_LOGIC; + dfi_0_init_complete : out STD_LOGIC; + dfi_0_out_rst_n : out STD_LOGIC; + dfi_1_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_1_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_1_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_1_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_1_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_1_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_1_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_1_ctrlupd_req : out STD_LOGIC; + dfi_1_phyupd_ack : out STD_LOGIC; + dfi_1_clk_init : out STD_LOGIC; + dfi_1_init_complete : out STD_LOGIC; + dfi_1_out_rst_n : out STD_LOGIC; + dfi_2_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_2_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_2_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_2_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_2_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_2_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_2_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_2_ctrlupd_req : out STD_LOGIC; + dfi_2_phyupd_ack : out STD_LOGIC; + dfi_2_clk_init : out STD_LOGIC; + dfi_2_init_complete : out STD_LOGIC; + dfi_2_out_rst_n : out STD_LOGIC; + dfi_3_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_3_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_3_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_3_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_3_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_3_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_3_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_3_ctrlupd_req : out STD_LOGIC; + dfi_3_phyupd_ack : out STD_LOGIC; + dfi_3_clk_init : out STD_LOGIC; + dfi_3_init_complete : out STD_LOGIC; + dfi_3_out_rst_n : out STD_LOGIC; + dfi_4_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_4_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_4_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_4_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_4_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_4_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_4_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_4_ctrlupd_req : out STD_LOGIC; + dfi_4_phyupd_ack : out STD_LOGIC; + dfi_4_clk_init : out STD_LOGIC; + dfi_4_init_complete : out STD_LOGIC; + dfi_4_out_rst_n : out STD_LOGIC; + dfi_5_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_5_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_5_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_5_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_5_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_5_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_5_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_5_ctrlupd_req : out STD_LOGIC; + dfi_5_phyupd_ack : out STD_LOGIC; + dfi_5_clk_init : out STD_LOGIC; + dfi_5_init_complete : out STD_LOGIC; + dfi_5_out_rst_n : out STD_LOGIC; + dfi_6_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_6_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_6_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_6_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_6_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_6_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_6_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_6_ctrlupd_req : out STD_LOGIC; + dfi_6_phyupd_ack : out STD_LOGIC; + dfi_6_clk_init : out STD_LOGIC; + dfi_6_init_complete : out STD_LOGIC; + dfi_6_out_rst_n : out STD_LOGIC; + dfi_7_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_7_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_7_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_7_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_7_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_7_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_7_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_7_ctrlupd_req : out STD_LOGIC; + dfi_7_phyupd_ack : out STD_LOGIC; + dfi_7_clk_init : out STD_LOGIC; + dfi_7_init_complete : out STD_LOGIC; + dfi_7_out_rst_n : out STD_LOGIC; + dfi_8_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_8_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_8_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_8_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_8_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_8_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_8_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_8_ctrlupd_req : out STD_LOGIC; + dfi_8_phyupd_ack : out STD_LOGIC; + dfi_8_clk_init : out STD_LOGIC; + dfi_8_init_complete : out STD_LOGIC; + dfi_8_out_rst_n : out STD_LOGIC; + dfi_9_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_9_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_9_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_9_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_9_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_9_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_9_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_9_ctrlupd_req : out STD_LOGIC; + dfi_9_phyupd_ack : out STD_LOGIC; + dfi_9_clk_init : out STD_LOGIC; + dfi_9_init_complete : out STD_LOGIC; + dfi_9_out_rst_n : out STD_LOGIC; + dfi_10_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_10_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_10_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_10_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_10_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_10_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_10_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_10_ctrlupd_req : out STD_LOGIC; + dfi_10_phyupd_ack : out STD_LOGIC; + dfi_10_clk_init : out STD_LOGIC; + dfi_10_init_complete : out STD_LOGIC; + dfi_10_out_rst_n : out STD_LOGIC; + dfi_11_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_11_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_11_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_11_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_11_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_11_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_11_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_11_ctrlupd_req : out STD_LOGIC; + dfi_11_phyupd_ack : out STD_LOGIC; + dfi_11_clk_init : out STD_LOGIC; + dfi_11_init_complete : out STD_LOGIC; + dfi_11_out_rst_n : out STD_LOGIC; + dfi_12_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_12_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_12_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_12_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_12_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_12_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_12_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_12_ctrlupd_req : out STD_LOGIC; + dfi_12_phyupd_ack : out STD_LOGIC; + dfi_12_clk_init : out STD_LOGIC; + dfi_12_init_complete : out STD_LOGIC; + dfi_12_out_rst_n : out STD_LOGIC; + dfi_13_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_13_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_13_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_13_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_13_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_13_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_13_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_13_ctrlupd_req : out STD_LOGIC; + dfi_13_phyupd_ack : out STD_LOGIC; + dfi_13_clk_init : out STD_LOGIC; + dfi_13_init_complete : out STD_LOGIC; + dfi_13_out_rst_n : out STD_LOGIC; + dfi_14_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_14_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_14_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_14_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_14_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_14_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_14_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_14_ctrlupd_req : out STD_LOGIC; + dfi_14_phyupd_ack : out STD_LOGIC; + dfi_14_clk_init : out STD_LOGIC; + dfi_14_init_complete : out STD_LOGIC; + dfi_14_out_rst_n : out STD_LOGIC; + dfi_15_dw_rddata_p0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_15_dw_rddata_dm_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_rddata_dbi_p0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_rddata_par_p0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dw_rddata_p1 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dfi_15_dw_rddata_dm_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_rddata_dbi_p1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + dfi_15_dw_rddata_par_p1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_dbi_byte_disable : out STD_LOGIC_VECTOR ( 15 downto 0 ); + dfi_15_dw_rddata_valid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + dfi_15_dw_derr_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); + dfi_15_aw_aerr_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); + dfi_15_ctrlupd_req : out STD_LOGIC; + dfi_15_phyupd_ack : out STD_LOGIC; + dfi_15_clk_init : out STD_LOGIC; + dfi_15_init_complete : out STD_LOGIC; + dfi_15_out_rst_n : out STD_LOGIC; + apb_complete_0 : out STD_LOGIC; + apb_complete_1 : out STD_LOGIC; + DRAM_0_STAT_CATTRIP : out STD_LOGIC; + DRAM_0_STAT_TEMP : out STD_LOGIC_VECTOR ( 6 downto 0 ); + DRAM_1_STAT_CATTRIP : out STD_LOGIC; + DRAM_1_STAT_TEMP : out STD_LOGIC_VECTOR ( 6 downto 0 ) + ); + +end hbm_0; + +architecture stub of hbm_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "HBM_REF_CLK_0,HBM_REF_CLK_1,dfi_0_clk,dfi_0_rst_n,dfi_0_init_start,dfi_0_aw_ck_p0[1:0],dfi_0_aw_cke_p0[1:0],dfi_0_aw_row_p0[11:0],dfi_0_aw_col_p0[15:0],dfi_0_dw_wrdata_p0[255:0],dfi_0_dw_wrdata_mask_p0[31:0],dfi_0_dw_wrdata_dbi_p0[31:0],dfi_0_dw_wrdata_par_p0[7:0],dfi_0_dw_wrdata_dq_en_p0[7:0],dfi_0_dw_wrdata_par_en_p0[7:0],dfi_0_aw_ck_p1[1:0],dfi_0_aw_cke_p1[1:0],dfi_0_aw_row_p1[11:0],dfi_0_aw_col_p1[15:0],dfi_0_dw_wrdata_p1[255:0],dfi_0_dw_wrdata_mask_p1[31:0],dfi_0_dw_wrdata_dbi_p1[31:0],dfi_0_dw_wrdata_par_p1[7:0],dfi_0_dw_wrdata_dq_en_p1[7:0],dfi_0_dw_wrdata_par_en_p1[7:0],dfi_0_aw_ck_dis,dfi_0_lp_pwr_e_req,dfi_0_lp_sr_e_req,dfi_0_lp_pwr_x_req,dfi_0_aw_tx_indx_ld,dfi_0_dw_tx_indx_ld,dfi_0_dw_rx_indx_ld,dfi_0_ctrlupd_ack,dfi_0_phyupd_req,dfi_0_dw_wrdata_dqs_p0[7:0],dfi_0_dw_wrdata_dqs_p1[7:0],dfi_1_clk,dfi_1_rst_n,dfi_1_init_start,dfi_1_aw_ck_p0[1:0],dfi_1_aw_cke_p0[1:0],dfi_1_aw_row_p0[11:0],dfi_1_aw_col_p0[15:0],dfi_1_dw_wrdata_p0[255:0],dfi_1_dw_wrdata_mask_p0[31:0],dfi_1_dw_wrdata_dbi_p0[31:0],dfi_1_dw_wrdata_par_p0[7:0],dfi_1_dw_wrdata_dq_en_p0[7:0],dfi_1_dw_wrdata_par_en_p0[7:0],dfi_1_aw_ck_p1[1:0],dfi_1_aw_cke_p1[1:0],dfi_1_aw_row_p1[11:0],dfi_1_aw_col_p1[15:0],dfi_1_dw_wrdata_p1[255:0],dfi_1_dw_wrdata_mask_p1[31:0],dfi_1_dw_wrdata_dbi_p1[31:0],dfi_1_dw_wrdata_par_p1[7:0],dfi_1_dw_wrdata_dq_en_p1[7:0],dfi_1_dw_wrdata_par_en_p1[7:0],dfi_1_aw_ck_dis,dfi_1_lp_pwr_e_req,dfi_1_lp_sr_e_req,dfi_1_lp_pwr_x_req,dfi_1_aw_tx_indx_ld,dfi_1_dw_tx_indx_ld,dfi_1_dw_rx_indx_ld,dfi_1_ctrlupd_ack,dfi_1_phyupd_req,dfi_1_dw_wrdata_dqs_p0[7:0],dfi_1_dw_wrdata_dqs_p1[7:0],dfi_2_clk,dfi_2_rst_n,dfi_2_init_start,dfi_2_aw_ck_p0[1:0],dfi_2_aw_cke_p0[1:0],dfi_2_aw_row_p0[11:0],dfi_2_aw_col_p0[15:0],dfi_2_dw_wrdata_p0[255:0],dfi_2_dw_wrdata_mask_p0[31:0],dfi_2_dw_wrdata_dbi_p0[31:0],dfi_2_dw_wrdata_par_p0[7:0],dfi_2_dw_wrdata_dq_en_p0[7:0],dfi_2_dw_wrdata_par_en_p0[7:0],dfi_2_aw_ck_p1[1:0],dfi_2_aw_cke_p1[1:0],dfi_2_aw_row_p1[11:0],dfi_2_aw_col_p1[15:0],dfi_2_dw_wrdata_p1[255:0],dfi_2_dw_wrdata_mask_p1[31:0],dfi_2_dw_wrdata_dbi_p1[31:0],dfi_2_dw_wrdata_par_p1[7:0],dfi_2_dw_wrdata_dq_en_p1[7:0],dfi_2_dw_wrdata_par_en_p1[7:0],dfi_2_aw_ck_dis,dfi_2_lp_pwr_e_req,dfi_2_lp_sr_e_req,dfi_2_lp_pwr_x_req,dfi_2_aw_tx_indx_ld,dfi_2_dw_tx_indx_ld,dfi_2_dw_rx_indx_ld,dfi_2_ctrlupd_ack,dfi_2_phyupd_req,dfi_2_dw_wrdata_dqs_p0[7:0],dfi_2_dw_wrdata_dqs_p1[7:0],dfi_3_clk,dfi_3_rst_n,dfi_3_init_start,dfi_3_aw_ck_p0[1:0],dfi_3_aw_cke_p0[1:0],dfi_3_aw_row_p0[11:0],dfi_3_aw_col_p0[15:0],dfi_3_dw_wrdata_p0[255:0],dfi_3_dw_wrdata_mask_p0[31:0],dfi_3_dw_wrdata_dbi_p0[31:0],dfi_3_dw_wrdata_par_p0[7:0],dfi_3_dw_wrdata_dq_en_p0[7:0],dfi_3_dw_wrdata_par_en_p0[7:0],dfi_3_aw_ck_p1[1:0],dfi_3_aw_cke_p1[1:0],dfi_3_aw_row_p1[11:0],dfi_3_aw_col_p1[15:0],dfi_3_dw_wrdata_p1[255:0],dfi_3_dw_wrdata_mask_p1[31:0],dfi_3_dw_wrdata_dbi_p1[31:0],dfi_3_dw_wrdata_par_p1[7:0],dfi_3_dw_wrdata_dq_en_p1[7:0],dfi_3_dw_wrdata_par_en_p1[7:0],dfi_3_aw_ck_dis,dfi_3_lp_pwr_e_req,dfi_3_lp_sr_e_req,dfi_3_lp_pwr_x_req,dfi_3_aw_tx_indx_ld,dfi_3_dw_tx_indx_ld,dfi_3_dw_rx_indx_ld,dfi_3_ctrlupd_ack,dfi_3_phyupd_req,dfi_3_dw_wrdata_dqs_p0[7:0],dfi_3_dw_wrdata_dqs_p1[7:0],dfi_4_clk,dfi_4_rst_n,dfi_4_init_start,dfi_4_aw_ck_p0[1:0],dfi_4_aw_cke_p0[1:0],dfi_4_aw_row_p0[11:0],dfi_4_aw_col_p0[15:0],dfi_4_dw_wrdata_p0[255:0],dfi_4_dw_wrdata_mask_p0[31:0],dfi_4_dw_wrdata_dbi_p0[31:0],dfi_4_dw_wrdata_par_p0[7:0],dfi_4_dw_wrdata_dq_en_p0[7:0],dfi_4_dw_wrdata_par_en_p0[7:0],dfi_4_aw_ck_p1[1:0],dfi_4_aw_cke_p1[1:0],dfi_4_aw_row_p1[11:0],dfi_4_aw_col_p1[15:0],dfi_4_dw_wrdata_p1[255:0],dfi_4_dw_wrdata_mask_p1[31:0],dfi_4_dw_wrdata_dbi_p1[31:0],dfi_4_dw_wrdata_par_p1[7:0],dfi_4_dw_wrdata_dq_en_p1[7:0],dfi_4_dw_wrdata_par_en_p1[7:0],dfi_4_aw_ck_dis,dfi_4_lp_pwr_e_req,dfi_4_lp_sr_e_req,dfi_4_lp_pwr_x_req,dfi_4_aw_tx_indx_ld,dfi_4_dw_tx_indx_ld,dfi_4_dw_rx_indx_ld,dfi_4_ctrlupd_ack,dfi_4_phyupd_req,dfi_4_dw_wrdata_dqs_p0[7:0],dfi_4_dw_wrdata_dqs_p1[7:0],dfi_5_clk,dfi_5_rst_n,dfi_5_init_start,dfi_5_aw_ck_p0[1:0],dfi_5_aw_cke_p0[1:0],dfi_5_aw_row_p0[11:0],dfi_5_aw_col_p0[15:0],dfi_5_dw_wrdata_p0[255:0],dfi_5_dw_wrdata_mask_p0[31:0],dfi_5_dw_wrdata_dbi_p0[31:0],dfi_5_dw_wrdata_par_p0[7:0],dfi_5_dw_wrdata_dq_en_p0[7:0],dfi_5_dw_wrdata_par_en_p0[7:0],dfi_5_aw_ck_p1[1:0],dfi_5_aw_cke_p1[1:0],dfi_5_aw_row_p1[11:0],dfi_5_aw_col_p1[15:0],dfi_5_dw_wrdata_p1[255:0],dfi_5_dw_wrdata_mask_p1[31:0],dfi_5_dw_wrdata_dbi_p1[31:0],dfi_5_dw_wrdata_par_p1[7:0],dfi_5_dw_wrdata_dq_en_p1[7:0],dfi_5_dw_wrdata_par_en_p1[7:0],dfi_5_aw_ck_dis,dfi_5_lp_pwr_e_req,dfi_5_lp_sr_e_req,dfi_5_lp_pwr_x_req,dfi_5_aw_tx_indx_ld,dfi_5_dw_tx_indx_ld,dfi_5_dw_rx_indx_ld,dfi_5_ctrlupd_ack,dfi_5_phyupd_req,dfi_5_dw_wrdata_dqs_p0[7:0],dfi_5_dw_wrdata_dqs_p1[7:0],dfi_6_clk,dfi_6_rst_n,dfi_6_init_start,dfi_6_aw_ck_p0[1:0],dfi_6_aw_cke_p0[1:0],dfi_6_aw_row_p0[11:0],dfi_6_aw_col_p0[15:0],dfi_6_dw_wrdata_p0[255:0],dfi_6_dw_wrdata_mask_p0[31:0],dfi_6_dw_wrdata_dbi_p0[31:0],dfi_6_dw_wrdata_par_p0[7:0],dfi_6_dw_wrdata_dq_en_p0[7:0],dfi_6_dw_wrdata_par_en_p0[7:0],dfi_6_aw_ck_p1[1:0],dfi_6_aw_cke_p1[1:0],dfi_6_aw_row_p1[11:0],dfi_6_aw_col_p1[15:0],dfi_6_dw_wrdata_p1[255:0],dfi_6_dw_wrdata_mask_p1[31:0],dfi_6_dw_wrdata_dbi_p1[31:0],dfi_6_dw_wrdata_par_p1[7:0],dfi_6_dw_wrdata_dq_en_p1[7:0],dfi_6_dw_wrdata_par_en_p1[7:0],dfi_6_aw_ck_dis,dfi_6_lp_pwr_e_req,dfi_6_lp_sr_e_req,dfi_6_lp_pwr_x_req,dfi_6_aw_tx_indx_ld,dfi_6_dw_tx_indx_ld,dfi_6_dw_rx_indx_ld,dfi_6_ctrlupd_ack,dfi_6_phyupd_req,dfi_6_dw_wrdata_dqs_p0[7:0],dfi_6_dw_wrdata_dqs_p1[7:0],dfi_7_clk,dfi_7_rst_n,dfi_7_init_start,dfi_7_aw_ck_p0[1:0],dfi_7_aw_cke_p0[1:0],dfi_7_aw_row_p0[11:0],dfi_7_aw_col_p0[15:0],dfi_7_dw_wrdata_p0[255:0],dfi_7_dw_wrdata_mask_p0[31:0],dfi_7_dw_wrdata_dbi_p0[31:0],dfi_7_dw_wrdata_par_p0[7:0],dfi_7_dw_wrdata_dq_en_p0[7:0],dfi_7_dw_wrdata_par_en_p0[7:0],dfi_7_aw_ck_p1[1:0],dfi_7_aw_cke_p1[1:0],dfi_7_aw_row_p1[11:0],dfi_7_aw_col_p1[15:0],dfi_7_dw_wrdata_p1[255:0],dfi_7_dw_wrdata_mask_p1[31:0],dfi_7_dw_wrdata_dbi_p1[31:0],dfi_7_dw_wrdata_par_p1[7:0],dfi_7_dw_wrdata_dq_en_p1[7:0],dfi_7_dw_wrdata_par_en_p1[7:0],dfi_7_aw_ck_dis,dfi_7_lp_pwr_e_req,dfi_7_lp_sr_e_req,dfi_7_lp_pwr_x_req,dfi_7_aw_tx_indx_ld,dfi_7_dw_tx_indx_ld,dfi_7_dw_rx_indx_ld,dfi_7_ctrlupd_ack,dfi_7_phyupd_req,dfi_7_dw_wrdata_dqs_p0[7:0],dfi_7_dw_wrdata_dqs_p1[7:0],dfi_8_clk,dfi_8_rst_n,dfi_8_init_start,dfi_8_aw_ck_p0[1:0],dfi_8_aw_cke_p0[1:0],dfi_8_aw_row_p0[11:0],dfi_8_aw_col_p0[15:0],dfi_8_dw_wrdata_p0[255:0],dfi_8_dw_wrdata_mask_p0[31:0],dfi_8_dw_wrdata_dbi_p0[31:0],dfi_8_dw_wrdata_par_p0[7:0],dfi_8_dw_wrdata_dq_en_p0[7:0],dfi_8_dw_wrdata_par_en_p0[7:0],dfi_8_aw_ck_p1[1:0],dfi_8_aw_cke_p1[1:0],dfi_8_aw_row_p1[11:0],dfi_8_aw_col_p1[15:0],dfi_8_dw_wrdata_p1[255:0],dfi_8_dw_wrdata_mask_p1[31:0],dfi_8_dw_wrdata_dbi_p1[31:0],dfi_8_dw_wrdata_par_p1[7:0],dfi_8_dw_wrdata_dq_en_p1[7:0],dfi_8_dw_wrdata_par_en_p1[7:0],dfi_8_aw_ck_dis,dfi_8_lp_pwr_e_req,dfi_8_lp_sr_e_req,dfi_8_lp_pwr_x_req,dfi_8_aw_tx_indx_ld,dfi_8_dw_tx_indx_ld,dfi_8_dw_rx_indx_ld,dfi_8_ctrlupd_ack,dfi_8_phyupd_req,dfi_8_dw_wrdata_dqs_p0[7:0],dfi_8_dw_wrdata_dqs_p1[7:0],dfi_9_clk,dfi_9_rst_n,dfi_9_init_start,dfi_9_aw_ck_p0[1:0],dfi_9_aw_cke_p0[1:0],dfi_9_aw_row_p0[11:0],dfi_9_aw_col_p0[15:0],dfi_9_dw_wrdata_p0[255:0],dfi_9_dw_wrdata_mask_p0[31:0],dfi_9_dw_wrdata_dbi_p0[31:0],dfi_9_dw_wrdata_par_p0[7:0],dfi_9_dw_wrdata_dq_en_p0[7:0],dfi_9_dw_wrdata_par_en_p0[7:0],dfi_9_aw_ck_p1[1:0],dfi_9_aw_cke_p1[1:0],dfi_9_aw_row_p1[11:0],dfi_9_aw_col_p1[15:0],dfi_9_dw_wrdata_p1[255:0],dfi_9_dw_wrdata_mask_p1[31:0],dfi_9_dw_wrdata_dbi_p1[31:0],dfi_9_dw_wrdata_par_p1[7:0],dfi_9_dw_wrdata_dq_en_p1[7:0],dfi_9_dw_wrdata_par_en_p1[7:0],dfi_9_aw_ck_dis,dfi_9_lp_pwr_e_req,dfi_9_lp_sr_e_req,dfi_9_lp_pwr_x_req,dfi_9_aw_tx_indx_ld,dfi_9_dw_tx_indx_ld,dfi_9_dw_rx_indx_ld,dfi_9_ctrlupd_ack,dfi_9_phyupd_req,dfi_9_dw_wrdata_dqs_p0[7:0],dfi_9_dw_wrdata_dqs_p1[7:0],dfi_10_clk,dfi_10_rst_n,dfi_10_init_start,dfi_10_aw_ck_p0[1:0],dfi_10_aw_cke_p0[1:0],dfi_10_aw_row_p0[11:0],dfi_10_aw_col_p0[15:0],dfi_10_dw_wrdata_p0[255:0],dfi_10_dw_wrdata_mask_p0[31:0],dfi_10_dw_wrdata_dbi_p0[31:0],dfi_10_dw_wrdata_par_p0[7:0],dfi_10_dw_wrdata_dq_en_p0[7:0],dfi_10_dw_wrdata_par_en_p0[7:0],dfi_10_aw_ck_p1[1:0],dfi_10_aw_cke_p1[1:0],dfi_10_aw_row_p1[11:0],dfi_10_aw_col_p1[15:0],dfi_10_dw_wrdata_p1[255:0],dfi_10_dw_wrdata_mask_p1[31:0],dfi_10_dw_wrdata_dbi_p1[31:0],dfi_10_dw_wrdata_par_p1[7:0],dfi_10_dw_wrdata_dq_en_p1[7:0],dfi_10_dw_wrdata_par_en_p1[7:0],dfi_10_aw_ck_dis,dfi_10_lp_pwr_e_req,dfi_10_lp_sr_e_req,dfi_10_lp_pwr_x_req,dfi_10_aw_tx_indx_ld,dfi_10_dw_tx_indx_ld,dfi_10_dw_rx_indx_ld,dfi_10_ctrlupd_ack,dfi_10_phyupd_req,dfi_10_dw_wrdata_dqs_p0[7:0],dfi_10_dw_wrdata_dqs_p1[7:0],dfi_11_clk,dfi_11_rst_n,dfi_11_init_start,dfi_11_aw_ck_p0[1:0],dfi_11_aw_cke_p0[1:0],dfi_11_aw_row_p0[11:0],dfi_11_aw_col_p0[15:0],dfi_11_dw_wrdata_p0[255:0],dfi_11_dw_wrdata_mask_p0[31:0],dfi_11_dw_wrdata_dbi_p0[31:0],dfi_11_dw_wrdata_par_p0[7:0],dfi_11_dw_wrdata_dq_en_p0[7:0],dfi_11_dw_wrdata_par_en_p0[7:0],dfi_11_aw_ck_p1[1:0],dfi_11_aw_cke_p1[1:0],dfi_11_aw_row_p1[11:0],dfi_11_aw_col_p1[15:0],dfi_11_dw_wrdata_p1[255:0],dfi_11_dw_wrdata_mask_p1[31:0],dfi_11_dw_wrdata_dbi_p1[31:0],dfi_11_dw_wrdata_par_p1[7:0],dfi_11_dw_wrdata_dq_en_p1[7:0],dfi_11_dw_wrdata_par_en_p1[7:0],dfi_11_aw_ck_dis,dfi_11_lp_pwr_e_req,dfi_11_lp_sr_e_req,dfi_11_lp_pwr_x_req,dfi_11_aw_tx_indx_ld,dfi_11_dw_tx_indx_ld,dfi_11_dw_rx_indx_ld,dfi_11_ctrlupd_ack,dfi_11_phyupd_req,dfi_11_dw_wrdata_dqs_p0[7:0],dfi_11_dw_wrdata_dqs_p1[7:0],dfi_12_clk,dfi_12_rst_n,dfi_12_init_start,dfi_12_aw_ck_p0[1:0],dfi_12_aw_cke_p0[1:0],dfi_12_aw_row_p0[11:0],dfi_12_aw_col_p0[15:0],dfi_12_dw_wrdata_p0[255:0],dfi_12_dw_wrdata_mask_p0[31:0],dfi_12_dw_wrdata_dbi_p0[31:0],dfi_12_dw_wrdata_par_p0[7:0],dfi_12_dw_wrdata_dq_en_p0[7:0],dfi_12_dw_wrdata_par_en_p0[7:0],dfi_12_aw_ck_p1[1:0],dfi_12_aw_cke_p1[1:0],dfi_12_aw_row_p1[11:0],dfi_12_aw_col_p1[15:0],dfi_12_dw_wrdata_p1[255:0],dfi_12_dw_wrdata_mask_p1[31:0],dfi_12_dw_wrdata_dbi_p1[31:0],dfi_12_dw_wrdata_par_p1[7:0],dfi_12_dw_wrdata_dq_en_p1[7:0],dfi_12_dw_wrdata_par_en_p1[7:0],dfi_12_aw_ck_dis,dfi_12_lp_pwr_e_req,dfi_12_lp_sr_e_req,dfi_12_lp_pwr_x_req,dfi_12_aw_tx_indx_ld,dfi_12_dw_tx_indx_ld,dfi_12_dw_rx_indx_ld,dfi_12_ctrlupd_ack,dfi_12_phyupd_req,dfi_12_dw_wrdata_dqs_p0[7:0],dfi_12_dw_wrdata_dqs_p1[7:0],dfi_13_clk,dfi_13_rst_n,dfi_13_init_start,dfi_13_aw_ck_p0[1:0],dfi_13_aw_cke_p0[1:0],dfi_13_aw_row_p0[11:0],dfi_13_aw_col_p0[15:0],dfi_13_dw_wrdata_p0[255:0],dfi_13_dw_wrdata_mask_p0[31:0],dfi_13_dw_wrdata_dbi_p0[31:0],dfi_13_dw_wrdata_par_p0[7:0],dfi_13_dw_wrdata_dq_en_p0[7:0],dfi_13_dw_wrdata_par_en_p0[7:0],dfi_13_aw_ck_p1[1:0],dfi_13_aw_cke_p1[1:0],dfi_13_aw_row_p1[11:0],dfi_13_aw_col_p1[15:0],dfi_13_dw_wrdata_p1[255:0],dfi_13_dw_wrdata_mask_p1[31:0],dfi_13_dw_wrdata_dbi_p1[31:0],dfi_13_dw_wrdata_par_p1[7:0],dfi_13_dw_wrdata_dq_en_p1[7:0],dfi_13_dw_wrdata_par_en_p1[7:0],dfi_13_aw_ck_dis,dfi_13_lp_pwr_e_req,dfi_13_lp_sr_e_req,dfi_13_lp_pwr_x_req,dfi_13_aw_tx_indx_ld,dfi_13_dw_tx_indx_ld,dfi_13_dw_rx_indx_ld,dfi_13_ctrlupd_ack,dfi_13_phyupd_req,dfi_13_dw_wrdata_dqs_p0[7:0],dfi_13_dw_wrdata_dqs_p1[7:0],dfi_14_clk,dfi_14_rst_n,dfi_14_init_start,dfi_14_aw_ck_p0[1:0],dfi_14_aw_cke_p0[1:0],dfi_14_aw_row_p0[11:0],dfi_14_aw_col_p0[15:0],dfi_14_dw_wrdata_p0[255:0],dfi_14_dw_wrdata_mask_p0[31:0],dfi_14_dw_wrdata_dbi_p0[31:0],dfi_14_dw_wrdata_par_p0[7:0],dfi_14_dw_wrdata_dq_en_p0[7:0],dfi_14_dw_wrdata_par_en_p0[7:0],dfi_14_aw_ck_p1[1:0],dfi_14_aw_cke_p1[1:0],dfi_14_aw_row_p1[11:0],dfi_14_aw_col_p1[15:0],dfi_14_dw_wrdata_p1[255:0],dfi_14_dw_wrdata_mask_p1[31:0],dfi_14_dw_wrdata_dbi_p1[31:0],dfi_14_dw_wrdata_par_p1[7:0],dfi_14_dw_wrdata_dq_en_p1[7:0],dfi_14_dw_wrdata_par_en_p1[7:0],dfi_14_aw_ck_dis,dfi_14_lp_pwr_e_req,dfi_14_lp_sr_e_req,dfi_14_lp_pwr_x_req,dfi_14_aw_tx_indx_ld,dfi_14_dw_tx_indx_ld,dfi_14_dw_rx_indx_ld,dfi_14_ctrlupd_ack,dfi_14_phyupd_req,dfi_14_dw_wrdata_dqs_p0[7:0],dfi_14_dw_wrdata_dqs_p1[7:0],dfi_15_clk,dfi_15_rst_n,dfi_15_init_start,dfi_15_aw_ck_p0[1:0],dfi_15_aw_cke_p0[1:0],dfi_15_aw_row_p0[11:0],dfi_15_aw_col_p0[15:0],dfi_15_dw_wrdata_p0[255:0],dfi_15_dw_wrdata_mask_p0[31:0],dfi_15_dw_wrdata_dbi_p0[31:0],dfi_15_dw_wrdata_par_p0[7:0],dfi_15_dw_wrdata_dq_en_p0[7:0],dfi_15_dw_wrdata_par_en_p0[7:0],dfi_15_aw_ck_p1[1:0],dfi_15_aw_cke_p1[1:0],dfi_15_aw_row_p1[11:0],dfi_15_aw_col_p1[15:0],dfi_15_dw_wrdata_p1[255:0],dfi_15_dw_wrdata_mask_p1[31:0],dfi_15_dw_wrdata_dbi_p1[31:0],dfi_15_dw_wrdata_par_p1[7:0],dfi_15_dw_wrdata_dq_en_p1[7:0],dfi_15_dw_wrdata_par_en_p1[7:0],dfi_15_aw_ck_dis,dfi_15_lp_pwr_e_req,dfi_15_lp_sr_e_req,dfi_15_lp_pwr_x_req,dfi_15_aw_tx_indx_ld,dfi_15_dw_tx_indx_ld,dfi_15_dw_rx_indx_ld,dfi_15_ctrlupd_ack,dfi_15_phyupd_req,dfi_15_dw_wrdata_dqs_p0[7:0],dfi_15_dw_wrdata_dqs_p1[7:0],APB_0_PCLK,APB_0_PRESET_N,APB_1_PCLK,APB_1_PRESET_N,dfi_0_dw_rddata_p0[255:0],dfi_0_dw_rddata_dm_p0[31:0],dfi_0_dw_rddata_dbi_p0[31:0],dfi_0_dw_rddata_par_p0[7:0],dfi_0_dw_rddata_p1[255:0],dfi_0_dw_rddata_dm_p1[31:0],dfi_0_dw_rddata_dbi_p1[31:0],dfi_0_dw_rddata_par_p1[7:0],dfi_0_dbi_byte_disable[15:0],dfi_0_dw_rddata_valid[3:0],dfi_0_dw_derr_n[7:0],dfi_0_aw_aerr_n[1:0],dfi_0_ctrlupd_req,dfi_0_phyupd_ack,dfi_0_clk_init,dfi_0_init_complete,dfi_0_out_rst_n,dfi_1_dw_rddata_p0[255:0],dfi_1_dw_rddata_dm_p0[31:0],dfi_1_dw_rddata_dbi_p0[31:0],dfi_1_dw_rddata_par_p0[7:0],dfi_1_dw_rddata_p1[255:0],dfi_1_dw_rddata_dm_p1[31:0],dfi_1_dw_rddata_dbi_p1[31:0],dfi_1_dw_rddata_par_p1[7:0],dfi_1_dbi_byte_disable[15:0],dfi_1_dw_rddata_valid[3:0],dfi_1_dw_derr_n[7:0],dfi_1_aw_aerr_n[1:0],dfi_1_ctrlupd_req,dfi_1_phyupd_ack,dfi_1_clk_init,dfi_1_init_complete,dfi_1_out_rst_n,dfi_2_dw_rddata_p0[255:0],dfi_2_dw_rddata_dm_p0[31:0],dfi_2_dw_rddata_dbi_p0[31:0],dfi_2_dw_rddata_par_p0[7:0],dfi_2_dw_rddata_p1[255:0],dfi_2_dw_rddata_dm_p1[31:0],dfi_2_dw_rddata_dbi_p1[31:0],dfi_2_dw_rddata_par_p1[7:0],dfi_2_dbi_byte_disable[15:0],dfi_2_dw_rddata_valid[3:0],dfi_2_dw_derr_n[7:0],dfi_2_aw_aerr_n[1:0],dfi_2_ctrlupd_req,dfi_2_phyupd_ack,dfi_2_clk_init,dfi_2_init_complete,dfi_2_out_rst_n,dfi_3_dw_rddata_p0[255:0],dfi_3_dw_rddata_dm_p0[31:0],dfi_3_dw_rddata_dbi_p0[31:0],dfi_3_dw_rddata_par_p0[7:0],dfi_3_dw_rddata_p1[255:0],dfi_3_dw_rddata_dm_p1[31:0],dfi_3_dw_rddata_dbi_p1[31:0],dfi_3_dw_rddata_par_p1[7:0],dfi_3_dbi_byte_disable[15:0],dfi_3_dw_rddata_valid[3:0],dfi_3_dw_derr_n[7:0],dfi_3_aw_aerr_n[1:0],dfi_3_ctrlupd_req,dfi_3_phyupd_ack,dfi_3_clk_init,dfi_3_init_complete,dfi_3_out_rst_n,dfi_4_dw_rddata_p0[255:0],dfi_4_dw_rddata_dm_p0[31:0],dfi_4_dw_rddata_dbi_p0[31:0],dfi_4_dw_rddata_par_p0[7:0],dfi_4_dw_rddata_p1[255:0],dfi_4_dw_rddata_dm_p1[31:0],dfi_4_dw_rddata_dbi_p1[31:0],dfi_4_dw_rddata_par_p1[7:0],dfi_4_dbi_byte_disable[15:0],dfi_4_dw_rddata_valid[3:0],dfi_4_dw_derr_n[7:0],dfi_4_aw_aerr_n[1:0],dfi_4_ctrlupd_req,dfi_4_phyupd_ack,dfi_4_clk_init,dfi_4_init_complete,dfi_4_out_rst_n,dfi_5_dw_rddata_p0[255:0],dfi_5_dw_rddata_dm_p0[31:0],dfi_5_dw_rddata_dbi_p0[31:0],dfi_5_dw_rddata_par_p0[7:0],dfi_5_dw_rddata_p1[255:0],dfi_5_dw_rddata_dm_p1[31:0],dfi_5_dw_rddata_dbi_p1[31:0],dfi_5_dw_rddata_par_p1[7:0],dfi_5_dbi_byte_disable[15:0],dfi_5_dw_rddata_valid[3:0],dfi_5_dw_derr_n[7:0],dfi_5_aw_aerr_n[1:0],dfi_5_ctrlupd_req,dfi_5_phyupd_ack,dfi_5_clk_init,dfi_5_init_complete,dfi_5_out_rst_n,dfi_6_dw_rddata_p0[255:0],dfi_6_dw_rddata_dm_p0[31:0],dfi_6_dw_rddata_dbi_p0[31:0],dfi_6_dw_rddata_par_p0[7:0],dfi_6_dw_rddata_p1[255:0],dfi_6_dw_rddata_dm_p1[31:0],dfi_6_dw_rddata_dbi_p1[31:0],dfi_6_dw_rddata_par_p1[7:0],dfi_6_dbi_byte_disable[15:0],dfi_6_dw_rddata_valid[3:0],dfi_6_dw_derr_n[7:0],dfi_6_aw_aerr_n[1:0],dfi_6_ctrlupd_req,dfi_6_phyupd_ack,dfi_6_clk_init,dfi_6_init_complete,dfi_6_out_rst_n,dfi_7_dw_rddata_p0[255:0],dfi_7_dw_rddata_dm_p0[31:0],dfi_7_dw_rddata_dbi_p0[31:0],dfi_7_dw_rddata_par_p0[7:0],dfi_7_dw_rddata_p1[255:0],dfi_7_dw_rddata_dm_p1[31:0],dfi_7_dw_rddata_dbi_p1[31:0],dfi_7_dw_rddata_par_p1[7:0],dfi_7_dbi_byte_disable[15:0],dfi_7_dw_rddata_valid[3:0],dfi_7_dw_derr_n[7:0],dfi_7_aw_aerr_n[1:0],dfi_7_ctrlupd_req,dfi_7_phyupd_ack,dfi_7_clk_init,dfi_7_init_complete,dfi_7_out_rst_n,dfi_8_dw_rddata_p0[255:0],dfi_8_dw_rddata_dm_p0[31:0],dfi_8_dw_rddata_dbi_p0[31:0],dfi_8_dw_rddata_par_p0[7:0],dfi_8_dw_rddata_p1[255:0],dfi_8_dw_rddata_dm_p1[31:0],dfi_8_dw_rddata_dbi_p1[31:0],dfi_8_dw_rddata_par_p1[7:0],dfi_8_dbi_byte_disable[15:0],dfi_8_dw_rddata_valid[3:0],dfi_8_dw_derr_n[7:0],dfi_8_aw_aerr_n[1:0],dfi_8_ctrlupd_req,dfi_8_phyupd_ack,dfi_8_clk_init,dfi_8_init_complete,dfi_8_out_rst_n,dfi_9_dw_rddata_p0[255:0],dfi_9_dw_rddata_dm_p0[31:0],dfi_9_dw_rddata_dbi_p0[31:0],dfi_9_dw_rddata_par_p0[7:0],dfi_9_dw_rddata_p1[255:0],dfi_9_dw_rddata_dm_p1[31:0],dfi_9_dw_rddata_dbi_p1[31:0],dfi_9_dw_rddata_par_p1[7:0],dfi_9_dbi_byte_disable[15:0],dfi_9_dw_rddata_valid[3:0],dfi_9_dw_derr_n[7:0],dfi_9_aw_aerr_n[1:0],dfi_9_ctrlupd_req,dfi_9_phyupd_ack,dfi_9_clk_init,dfi_9_init_complete,dfi_9_out_rst_n,dfi_10_dw_rddata_p0[255:0],dfi_10_dw_rddata_dm_p0[31:0],dfi_10_dw_rddata_dbi_p0[31:0],dfi_10_dw_rddata_par_p0[7:0],dfi_10_dw_rddata_p1[255:0],dfi_10_dw_rddata_dm_p1[31:0],dfi_10_dw_rddata_dbi_p1[31:0],dfi_10_dw_rddata_par_p1[7:0],dfi_10_dbi_byte_disable[15:0],dfi_10_dw_rddata_valid[3:0],dfi_10_dw_derr_n[7:0],dfi_10_aw_aerr_n[1:0],dfi_10_ctrlupd_req,dfi_10_phyupd_ack,dfi_10_clk_init,dfi_10_init_complete,dfi_10_out_rst_n,dfi_11_dw_rddata_p0[255:0],dfi_11_dw_rddata_dm_p0[31:0],dfi_11_dw_rddata_dbi_p0[31:0],dfi_11_dw_rddata_par_p0[7:0],dfi_11_dw_rddata_p1[255:0],dfi_11_dw_rddata_dm_p1[31:0],dfi_11_dw_rddata_dbi_p1[31:0],dfi_11_dw_rddata_par_p1[7:0],dfi_11_dbi_byte_disable[15:0],dfi_11_dw_rddata_valid[3:0],dfi_11_dw_derr_n[7:0],dfi_11_aw_aerr_n[1:0],dfi_11_ctrlupd_req,dfi_11_phyupd_ack,dfi_11_clk_init,dfi_11_init_complete,dfi_11_out_rst_n,dfi_12_dw_rddata_p0[255:0],dfi_12_dw_rddata_dm_p0[31:0],dfi_12_dw_rddata_dbi_p0[31:0],dfi_12_dw_rddata_par_p0[7:0],dfi_12_dw_rddata_p1[255:0],dfi_12_dw_rddata_dm_p1[31:0],dfi_12_dw_rddata_dbi_p1[31:0],dfi_12_dw_rddata_par_p1[7:0],dfi_12_dbi_byte_disable[15:0],dfi_12_dw_rddata_valid[3:0],dfi_12_dw_derr_n[7:0],dfi_12_aw_aerr_n[1:0],dfi_12_ctrlupd_req,dfi_12_phyupd_ack,dfi_12_clk_init,dfi_12_init_complete,dfi_12_out_rst_n,dfi_13_dw_rddata_p0[255:0],dfi_13_dw_rddata_dm_p0[31:0],dfi_13_dw_rddata_dbi_p0[31:0],dfi_13_dw_rddata_par_p0[7:0],dfi_13_dw_rddata_p1[255:0],dfi_13_dw_rddata_dm_p1[31:0],dfi_13_dw_rddata_dbi_p1[31:0],dfi_13_dw_rddata_par_p1[7:0],dfi_13_dbi_byte_disable[15:0],dfi_13_dw_rddata_valid[3:0],dfi_13_dw_derr_n[7:0],dfi_13_aw_aerr_n[1:0],dfi_13_ctrlupd_req,dfi_13_phyupd_ack,dfi_13_clk_init,dfi_13_init_complete,dfi_13_out_rst_n,dfi_14_dw_rddata_p0[255:0],dfi_14_dw_rddata_dm_p0[31:0],dfi_14_dw_rddata_dbi_p0[31:0],dfi_14_dw_rddata_par_p0[7:0],dfi_14_dw_rddata_p1[255:0],dfi_14_dw_rddata_dm_p1[31:0],dfi_14_dw_rddata_dbi_p1[31:0],dfi_14_dw_rddata_par_p1[7:0],dfi_14_dbi_byte_disable[15:0],dfi_14_dw_rddata_valid[3:0],dfi_14_dw_derr_n[7:0],dfi_14_aw_aerr_n[1:0],dfi_14_ctrlupd_req,dfi_14_phyupd_ack,dfi_14_clk_init,dfi_14_init_complete,dfi_14_out_rst_n,dfi_15_dw_rddata_p0[255:0],dfi_15_dw_rddata_dm_p0[31:0],dfi_15_dw_rddata_dbi_p0[31:0],dfi_15_dw_rddata_par_p0[7:0],dfi_15_dw_rddata_p1[255:0],dfi_15_dw_rddata_dm_p1[31:0],dfi_15_dw_rddata_dbi_p1[31:0],dfi_15_dw_rddata_par_p1[7:0],dfi_15_dbi_byte_disable[15:0],dfi_15_dw_rddata_valid[3:0],dfi_15_dw_derr_n[7:0],dfi_15_aw_aerr_n[1:0],dfi_15_ctrlupd_req,dfi_15_phyupd_ack,dfi_15_clk_init,dfi_15_init_complete,dfi_15_out_rst_n,apb_complete_0,apb_complete_1,DRAM_0_STAT_CATTRIP,DRAM_0_STAT_TEMP[6:0],DRAM_1_STAT_CATTRIP,DRAM_1_STAT_TEMP[6:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "hbm_v1_0_9,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo new file mode 100755 index 0000000..f6b9dee --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +instr_blk_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [10 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file instr_blk_mem.v when simulating +// the core, instr_blk_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho new file mode 100755 index 0000000..90d7f09 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT instr_blk_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : instr_blk_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file instr_blk_mem.vhd when simulating +-- the core, instr_blk_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v new file mode 100644 index 0000000..0131dc3 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:12 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem_stub.v +// Design : instr_blk_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module instr_blk_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[10:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [10:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl new file mode 100644 index 0000000..df27e48 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:12 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem_stub.vhdl +-- Design : instr_blk_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity instr_blk_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end instr_blk_mem; + +architecture stub of instr_blk_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[10:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo new file mode 100755 index 0000000..a025769 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +instr_blk_mem_sim your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [9 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file instr_blk_mem_sim.v when simulating +// the core, instr_blk_mem_sim. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho new file mode 100755 index 0000000..3eccade --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT instr_blk_mem_sim + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : instr_blk_mem_sim + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file instr_blk_mem_sim.vhd when simulating +-- the core, instr_blk_mem_sim. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v new file mode 100644 index 0000000..66874ff --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:16 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v +// Design : instr_blk_mem_sim +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module instr_blk_mem_sim(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [9:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl new file mode 100644 index 0000000..9e7993f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:16 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl +-- Design : instr_blk_mem_sim +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity instr_blk_mem_sim is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end instr_blk_mem_sim; + +architecture stub of instr_blk_mem_sim is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[9:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.veo new file mode 100755 index 0000000..4d42d6c --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +pr_read_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [4 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file pr_read_mem.v when simulating +// the core, pr_read_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.vho new file mode 100755 index 0000000..7680138 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT pr_read_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : pr_read_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file pr_read_mem.vhd when simulating +-- the core, pr_read_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v new file mode 100644 index 0000000..330eea1 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:11 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem_stub.v +// Design : pr_read_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module pr_read_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[4:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [4:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl new file mode 100644 index 0000000..1a52518 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:11 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem_stub.vhdl +-- Design : pr_read_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity pr_read_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 4 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end pr_read_mem; + +architecture stub of pr_read_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[4:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo new file mode 100755 index 0000000..ba9a615 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +pr_ref_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [6 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file pr_ref_mem.v when simulating +// the core, pr_ref_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho new file mode 100755 index 0000000..387e5f3 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT pr_ref_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : pr_ref_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file pr_ref_mem.vhd when simulating +-- the core, pr_ref_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v new file mode 100644 index 0000000..25fb46b --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:11 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem_stub.v +// Design : pr_ref_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module pr_ref_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[6:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [6:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl new file mode 100644 index 0000000..4cbf052 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:12 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem_stub.vhdl +-- Design : pr_ref_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity pr_ref_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end pr_ref_mem; + +architecture stub of pr_ref_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[6:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.veo new file mode 100755 index 0000000..14fbb52 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.veo @@ -0,0 +1,77 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +rdback_fifo your_instance_name ( + .clk(clk), // input wire clk + .srst(srst), // input wire srst + .din(din), // input wire [511 : 0] din + .wr_en(wr_en), // input wire wr_en + .rd_en(rd_en), // input wire rd_en + .dout(dout), // output wire [255 : 0] dout + .full(full), // output wire full + .empty(empty), // output wire empty + .valid(valid), // output wire valid + .prog_full(prog_full), // output wire prog_full + .prog_empty(prog_empty), // output wire prog_empty + .wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy + .rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file rdback_fifo.v when simulating +// the core, rdback_fifo. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.vho new file mode 100755 index 0000000..2d2c0ed --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo.vho @@ -0,0 +1,99 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fifo_generator:13.2 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT rdback_fifo + PORT ( + clk : IN STD_LOGIC; + srst : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + valid : OUT STD_LOGIC; + prog_full : OUT STD_LOGIC; + prog_empty : OUT STD_LOGIC; + wr_rst_busy : OUT STD_LOGIC; + rd_rst_busy : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : rdback_fifo + PORT MAP ( + clk => clk, + srst => srst, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty, + valid => valid, + prog_full => prog_full, + prog_empty => prog_empty, + wr_rst_busy => wr_rst_busy, + rd_rst_busy => rd_rst_busy + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file rdback_fifo.vhd when simulating +-- the core, rdback_fifo. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v new file mode 100644 index 0000000..fe6e59e --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v @@ -0,0 +1,33 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:08 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/rdback_fifo/rdback_fifo_stub.v +// Design : rdback_fifo +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *) +module rdback_fifo(clk, srst, din, wr_en, rd_en, dout, full, empty, valid, + prog_full, prog_empty, wr_rst_busy, rd_rst_busy) +/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[511:0],wr_en,rd_en,dout[255:0],full,empty,valid,prog_full,prog_empty,wr_rst_busy,rd_rst_busy" */; + input clk; + input srst; + input [511:0]din; + input wr_en; + input rd_en; + output [255:0]dout; + output full; + output empty; + output valid; + output prog_full; + output prog_empty; + output wr_rst_busy; + output rd_rst_busy; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl new file mode 100644 index 0000000..2fba8e6 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl @@ -0,0 +1,42 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:08 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/rdback_fifo/rdback_fifo_stub.vhdl +-- Design : rdback_fifo +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity rdback_fifo is + Port ( + clk : in STD_LOGIC; + srst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 511 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 255 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + valid : out STD_LOGIC; + prog_full : out STD_LOGIC; + prog_empty : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC + ); + +end rdback_fifo; + +architecture stub of rdback_fifo is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,srst,din[511:0],wr_en,rd_en,dout[255:0],full,empty,valid,prog_full,prog_empty,wr_rst_busy,rd_rst_busy"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.veo new file mode 100755 index 0000000..2e2c1b0 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +scratchpad your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [9 : 0] addra + .dina(dina), // input wire [31 : 0] dina + .douta(douta) // output wire [31 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file scratchpad.v when simulating +// the core, scratchpad. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.vho new file mode 100755 index 0000000..8d2d151 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT scratchpad + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : scratchpad + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file scratchpad.vhd when simulating +-- the core, scratchpad. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.v new file mode 100644 index 0000000..7122b49 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:10 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad_stub.v +// Design : scratchpad +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module scratchpad(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[31:0],douta[31:0]" */; + input clka; + input ena; + input [0:0]wea; + input [9:0]addra; + input [31:0]dina; + output [31:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl new file mode 100644 index 0000000..044c890 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:10 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad_stub.vhdl +-- Design : scratchpad +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity scratchpad is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 31 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end scratchpad; + +architecture stub of scratchpad is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[9:0],dina[31:0],douta[31:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.veo new file mode 100755 index 0000000..4dcafaf --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.veo @@ -0,0 +1,75 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +wrdata_fifo your_instance_name ( + .srst(srst), // input wire srst + .wr_clk(wr_clk), // input wire wr_clk + .rd_clk(rd_clk), // input wire rd_clk + .din(din), // input wire [1023 : 0] din + .wr_en(wr_en), // input wire wr_en + .rd_en(rd_en), // input wire rd_en + .dout(dout), // output wire [511 : 0] dout + .full(full), // output wire full + .empty(empty), // output wire empty + .wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy + .rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file wrdata_fifo.v when simulating +// the core, wrdata_fifo. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.vho new file mode 100755 index 0000000..adacf54 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.vho @@ -0,0 +1,95 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fifo_generator:13.2 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT wrdata_fifo + PORT ( + srst : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(1023 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + wr_rst_busy : OUT STD_LOGIC; + rd_rst_busy : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : wrdata_fifo + PORT MAP ( + srst => srst, + wr_clk => wr_clk, + rd_clk => rd_clk, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty, + wr_rst_busy => wr_rst_busy, + rd_rst_busy => rd_rst_busy + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file wrdata_fifo.vhd when simulating +-- the core, wrdata_fifo. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.v new file mode 100644 index 0000000..7f976bf --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:18 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/wrdata_fifo/wrdata_fifo_stub.v +// Design : wrdata_fifo +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *) +module wrdata_fifo(srst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, + empty, wr_rst_busy, rd_rst_busy) +/* synthesis syn_black_box black_box_pad_pin="srst,wr_clk,rd_clk,din[1023:0],wr_en,rd_en,dout[511:0],full,empty,wr_rst_busy,rd_rst_busy" */; + input srst; + input wr_clk; + input rd_clk; + input [1023:0]din; + input wr_en; + input rd_en; + output [511:0]dout; + output full; + output empty; + output wr_rst_busy; + output rd_rst_busy; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.vhdl new file mode 100644 index 0000000..bbfea6f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:18 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/wrdata_fifo/wrdata_fifo_stub.vhdl +-- Design : wrdata_fifo +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity wrdata_fifo is + Port ( + srst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 1023 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 511 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC + ); + +end wrdata_fifo; + +architecture stub of wrdata_fifo is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "srst,wr_clk,rd_clk,din[1023:0],wr_en,rd_en,dout[511:0],full,empty,wr_rst_busy,rd_rst_busy"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.veo new file mode 100755 index 0000000..bd81a3c --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.veo @@ -0,0 +1,95 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:xdma:4.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +xdma your_instance_name ( + .sys_clk(sys_clk), // input wire sys_clk + .sys_clk_gt(sys_clk_gt), // input wire sys_clk_gt + .sys_rst_n(sys_rst_n), // input wire sys_rst_n + .user_lnk_up(user_lnk_up), // output wire user_lnk_up + .pci_exp_txp(pci_exp_txp), // output wire [7 : 0] pci_exp_txp + .pci_exp_txn(pci_exp_txn), // output wire [7 : 0] pci_exp_txn + .pci_exp_rxp(pci_exp_rxp), // input wire [7 : 0] pci_exp_rxp + .pci_exp_rxn(pci_exp_rxn), // input wire [7 : 0] pci_exp_rxn + .axi_aclk(axi_aclk), // output wire axi_aclk + .axi_aresetn(axi_aresetn), // output wire axi_aresetn + .usr_irq_req(usr_irq_req), // input wire [0 : 0] usr_irq_req + .usr_irq_ack(usr_irq_ack), // output wire [0 : 0] usr_irq_ack + .msi_enable(msi_enable), // output wire msi_enable + .msi_vector_width(msi_vector_width), // output wire [2 : 0] msi_vector_width + .cfg_mgmt_addr(cfg_mgmt_addr), // input wire [18 : 0] cfg_mgmt_addr + .cfg_mgmt_write(cfg_mgmt_write), // input wire cfg_mgmt_write + .cfg_mgmt_write_data(cfg_mgmt_write_data), // input wire [31 : 0] cfg_mgmt_write_data + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), // input wire [3 : 0] cfg_mgmt_byte_enable + .cfg_mgmt_read(cfg_mgmt_read), // input wire cfg_mgmt_read + .cfg_mgmt_read_data(cfg_mgmt_read_data), // output wire [31 : 0] cfg_mgmt_read_data + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), // output wire cfg_mgmt_read_write_done + .s_axis_c2h_tdata_0(s_axis_c2h_tdata_0), // input wire [255 : 0] s_axis_c2h_tdata_0 + .s_axis_c2h_tlast_0(s_axis_c2h_tlast_0), // input wire s_axis_c2h_tlast_0 + .s_axis_c2h_tvalid_0(s_axis_c2h_tvalid_0), // input wire s_axis_c2h_tvalid_0 + .s_axis_c2h_tready_0(s_axis_c2h_tready_0), // output wire s_axis_c2h_tready_0 + .s_axis_c2h_tkeep_0(s_axis_c2h_tkeep_0), // input wire [31 : 0] s_axis_c2h_tkeep_0 + .m_axis_h2c_tdata_0(m_axis_h2c_tdata_0), // output wire [255 : 0] m_axis_h2c_tdata_0 + .m_axis_h2c_tlast_0(m_axis_h2c_tlast_0), // output wire m_axis_h2c_tlast_0 + .m_axis_h2c_tvalid_0(m_axis_h2c_tvalid_0), // output wire m_axis_h2c_tvalid_0 + .m_axis_h2c_tready_0(m_axis_h2c_tready_0), // input wire m_axis_h2c_tready_0 + .m_axis_h2c_tkeep_0(m_axis_h2c_tkeep_0) // output wire [31 : 0] m_axis_h2c_tkeep_0 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file xdma.v when simulating +// the core, xdma. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.vho new file mode 100755 index 0000000..52e712f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma.vho @@ -0,0 +1,135 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:xdma:4.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT xdma + PORT ( + sys_clk : IN STD_LOGIC; + sys_clk_gt : IN STD_LOGIC; + sys_rst_n : IN STD_LOGIC; + user_lnk_up : OUT STD_LOGIC; + pci_exp_txp : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + pci_exp_txn : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + pci_exp_rxp : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + pci_exp_rxn : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + axi_aclk : OUT STD_LOGIC; + axi_aresetn : OUT STD_LOGIC; + usr_irq_req : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + usr_irq_ack : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + msi_enable : OUT STD_LOGIC; + msi_vector_width : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + cfg_mgmt_addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0); + cfg_mgmt_write : IN STD_LOGIC; + cfg_mgmt_write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_mgmt_byte_enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + cfg_mgmt_read : IN STD_LOGIC; + cfg_mgmt_read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_mgmt_read_write_done : OUT STD_LOGIC; + s_axis_c2h_tdata_0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + s_axis_c2h_tlast_0 : IN STD_LOGIC; + s_axis_c2h_tvalid_0 : IN STD_LOGIC; + s_axis_c2h_tready_0 : OUT STD_LOGIC; + s_axis_c2h_tkeep_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_h2c_tdata_0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + m_axis_h2c_tlast_0 : OUT STD_LOGIC; + m_axis_h2c_tvalid_0 : OUT STD_LOGIC; + m_axis_h2c_tready_0 : IN STD_LOGIC; + m_axis_h2c_tkeep_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : xdma + PORT MAP ( + sys_clk => sys_clk, + sys_clk_gt => sys_clk_gt, + sys_rst_n => sys_rst_n, + user_lnk_up => user_lnk_up, + pci_exp_txp => pci_exp_txp, + pci_exp_txn => pci_exp_txn, + pci_exp_rxp => pci_exp_rxp, + pci_exp_rxn => pci_exp_rxn, + axi_aclk => axi_aclk, + axi_aresetn => axi_aresetn, + usr_irq_req => usr_irq_req, + usr_irq_ack => usr_irq_ack, + msi_enable => msi_enable, + msi_vector_width => msi_vector_width, + cfg_mgmt_addr => cfg_mgmt_addr, + cfg_mgmt_write => cfg_mgmt_write, + cfg_mgmt_write_data => cfg_mgmt_write_data, + cfg_mgmt_byte_enable => cfg_mgmt_byte_enable, + cfg_mgmt_read => cfg_mgmt_read, + cfg_mgmt_read_data => cfg_mgmt_read_data, + cfg_mgmt_read_write_done => cfg_mgmt_read_write_done, + s_axis_c2h_tdata_0 => s_axis_c2h_tdata_0, + s_axis_c2h_tlast_0 => s_axis_c2h_tlast_0, + s_axis_c2h_tvalid_0 => s_axis_c2h_tvalid_0, + s_axis_c2h_tready_0 => s_axis_c2h_tready_0, + s_axis_c2h_tkeep_0 => s_axis_c2h_tkeep_0, + m_axis_h2c_tdata_0 => m_axis_h2c_tdata_0, + m_axis_h2c_tlast_0 => m_axis_h2c_tlast_0, + m_axis_h2c_tvalid_0 => m_axis_h2c_tvalid_0, + m_axis_h2c_tready_0 => m_axis_h2c_tready_0, + m_axis_h2c_tkeep_0 => m_axis_h2c_tkeep_0 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file xdma.vhd when simulating +-- the core, xdma. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.v new file mode 100644 index 0000000..b3aa0af --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.v @@ -0,0 +1,56 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:37:02 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/xdma_stub.v +// Design : xdma +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "xdma_core_top,Vivado 2020.2" *) +module xdma(sys_clk, sys_clk_gt, sys_rst_n, user_lnk_up, + pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, axi_aclk, axi_aresetn, usr_irq_req, + usr_irq_ack, msi_enable, msi_vector_width, cfg_mgmt_addr, cfg_mgmt_write, + cfg_mgmt_write_data, cfg_mgmt_byte_enable, cfg_mgmt_read, cfg_mgmt_read_data, + cfg_mgmt_read_write_done, s_axis_c2h_tdata_0, s_axis_c2h_tlast_0, s_axis_c2h_tvalid_0, + s_axis_c2h_tready_0, s_axis_c2h_tkeep_0, m_axis_h2c_tdata_0, m_axis_h2c_tlast_0, + m_axis_h2c_tvalid_0, m_axis_h2c_tready_0, m_axis_h2c_tkeep_0) +/* synthesis syn_black_box black_box_pad_pin="sys_clk,sys_clk_gt,sys_rst_n,user_lnk_up,pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,s_axis_c2h_tdata_0[255:0],s_axis_c2h_tlast_0,s_axis_c2h_tvalid_0,s_axis_c2h_tready_0,s_axis_c2h_tkeep_0[31:0],m_axis_h2c_tdata_0[255:0],m_axis_h2c_tlast_0,m_axis_h2c_tvalid_0,m_axis_h2c_tready_0,m_axis_h2c_tkeep_0[31:0]" */; + input sys_clk; + input sys_clk_gt; + input sys_rst_n; + output user_lnk_up; + output [7:0]pci_exp_txp; + output [7:0]pci_exp_txn; + input [7:0]pci_exp_rxp; + input [7:0]pci_exp_rxn; + output axi_aclk; + output axi_aresetn; + input [0:0]usr_irq_req; + output [0:0]usr_irq_ack; + output msi_enable; + output [2:0]msi_vector_width; + input [18:0]cfg_mgmt_addr; + input cfg_mgmt_write; + input [31:0]cfg_mgmt_write_data; + input [3:0]cfg_mgmt_byte_enable; + input cfg_mgmt_read; + output [31:0]cfg_mgmt_read_data; + output cfg_mgmt_read_write_done; + input [255:0]s_axis_c2h_tdata_0; + input s_axis_c2h_tlast_0; + input s_axis_c2h_tvalid_0; + output s_axis_c2h_tready_0; + input [31:0]s_axis_c2h_tkeep_0; + output [255:0]m_axis_h2c_tdata_0; + output m_axis_h2c_tlast_0; + output m_axis_h2c_tvalid_0; + input m_axis_h2c_tready_0; + output [31:0]m_axis_h2c_tkeep_0; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.vhdl new file mode 100644 index 0000000..9e6a49f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/xdma/xdma_stub.vhdl @@ -0,0 +1,60 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:37:02 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/xdma_stub.vhdl +-- Design : xdma +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity xdma is + Port ( + sys_clk : in STD_LOGIC; + sys_clk_gt : in STD_LOGIC; + sys_rst_n : in STD_LOGIC; + user_lnk_up : out STD_LOGIC; + pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); + pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); + pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); + axi_aclk : out STD_LOGIC; + axi_aresetn : out STD_LOGIC; + usr_irq_req : in STD_LOGIC_VECTOR ( 0 to 0 ); + usr_irq_ack : out STD_LOGIC_VECTOR ( 0 to 0 ); + msi_enable : out STD_LOGIC; + msi_vector_width : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 ); + cfg_mgmt_write : in STD_LOGIC; + cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_mgmt_read : in STD_LOGIC; + cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_read_write_done : out STD_LOGIC; + s_axis_c2h_tdata_0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + s_axis_c2h_tlast_0 : in STD_LOGIC; + s_axis_c2h_tvalid_0 : in STD_LOGIC; + s_axis_c2h_tready_0 : out STD_LOGIC; + s_axis_c2h_tkeep_0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axis_h2c_tdata_0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + m_axis_h2c_tlast_0 : out STD_LOGIC; + m_axis_h2c_tvalid_0 : out STD_LOGIC; + m_axis_h2c_tready_0 : in STD_LOGIC; + m_axis_h2c_tkeep_0 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end xdma; + +architecture stub of xdma is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "sys_clk,sys_clk_gt,sys_rst_n,user_lnk_up,pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,s_axis_c2h_tdata_0[255:0],s_axis_c2h_tlast_0,s_axis_c2h_tvalid_0,s_axis_c2h_tready_0,s_axis_c2h_tkeep_0[31:0],m_axis_h2c_tdata_0[255:0],m_axis_h2c_tlast_0,m_axis_h2c_tvalid_0,m_axis_h2c_tready_0,m_axis_h2c_tkeep_0[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "xdma_core_top,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo new file mode 100755 index 0000000..a437d51 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +zq_calib_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [6 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file zq_calib_mem.v when simulating +// the core, zq_calib_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho new file mode 100755 index 0000000..d9e1b0c --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT zq_calib_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : zq_calib_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file zq_calib_mem.vhd when simulating +-- the core, zq_calib_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v new file mode 100644 index 0000000..4515302 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:33:12 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem_stub.v +// Design : zq_calib_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module zq_calib_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[6:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [6:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl new file mode 100644 index 0000000..0c3fee3 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:33:12 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem_stub.vhdl +-- Design : zq_calib_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity zq_calib_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end zq_calib_mem; + +architecture stub of zq_calib_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[6:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/mem_init_files/program.coe b/projects/U50-HBM/U50-HBM.ip_user_files/mem_init_files/program.coe new file mode 100755 index 0000000..c59a1d2 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/mem_init_files/program.coe @@ -0,0 +1,549 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0000000000000110000000000000000000000000100010000000000000000000, +0000000000000110000000000000000000000000101100000000000100000000, +0000000000000110000000000000000000000000000000000000000010000000, +0000000000000110000000000000000000000000000100000000000000010000, +0000000000000110000000000000000000000000001000000000000000010000, +0000000000000110000000000000000000000000011100000000000000000000, +0000000000000110000000000000000000000000011000000000000000000000, +0000000000000110000000000000000000000000010000000000000000000000, +0000000000000110000000000000000000000000001100000000000000000000, +0000000000000110000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000111, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100111, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, 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