From 7721980589f4c7fa811689e815a77d63f2556497 Mon Sep 17 00:00:00 2001 From: Ataberk Date: Thu, 2 May 2024 17:22:05 +0200 Subject: Add sources for U50 HBM2 --- .../ip/c_counter_binary_0/c_counter_binary_0.xci | 109 +++ .../ip/c_counter_binary_0/c_counter_binary_0.xml | 927 +++++++++++++++++++++ 2 files changed, 1036 insertions(+) create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xml (limited to 'projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0') diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xci b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xci new file mode 100644 index 0000000..b49a36f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xci @@ -0,0 +1,109 @@ + + + xilinx.com + xci + unknown + 1.0 + + + c_counter_binary_0 + + + + 10000000 + 0 + 0 + 0.000 + undef + undef + undef + 0 + undef + undef + undef + undef + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 16 + virtexuplusHBM + 0 + false + c_counter_binary_0 + UP + 0 + Manual + 1 + Fabric + 1 + 1 + Manual + false + Active_High + 16 + false + false + false + 0 + false + Reset_Overrides_Set + Sync_Overrides_CE + false + 1 + virtexuplusHBM + xilinx.com:au50:part0:1.3 + + xcu50 + fsvh2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 14 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xml b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xml new file mode 100644 index 0000000..013246f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xml @@ -0,0 +1,927 @@ + + + xilinx.com + customized_ip + c_counter_binary_0 + 1.0 + + + sset_intf + + + + + + + DATA + + + SSET + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + clk_intf + + + + + + + CLK + + + CLK + + + + + + ASSOCIATED_BUSIF + q_intf:thresh0_intf:l_intf:load_intf:up_intf:sinit_intf:sset_intf + + + ASSOCIATED_RESET + SCLR + + + ASSOCIATED_CLKEN + CE + + + FREQ_HZ + clk + 10000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + sclr_intf + + + + + + + RST + + + SCLR + + + + + + POLARITY + ACTIVE_HIGH + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + ce_intf + + + + + + + CE + + + CE + + + + + + POLARITY + ACTIVE_HIGH + + + + + sinit_intf + + + + + + + DATA + + + SINIT + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + up_intf + + + + + + + DATA + + + UP + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + load_intf + + + + + + + DATA + + + LOAD + + + + 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false + + + + + + THRESH0 + + out + + + std_logic + dummy_view + + + + 0x1 + + + + + + false + + + + + + Q + + out + + 15 + 0 + + + + std_logic_vector + dummy_view + + + + + + + + C_IMPLEMENTATION + 0 + + + C_VERBOSITY + 0 + + + C_XDEVICEFAMILY + virtexuplusHBM + + + C_WIDTH + 16 + + + C_HAS_CE + 0 + + + C_HAS_SCLR + 0 + + + C_RESTRICT_COUNT + 0 + + + C_COUNT_TO + 1 + + + C_COUNT_BY + 1 + + + C_COUNT_MODE + 0 + + + C_THRESH0_VALUE + 1 + + + C_CE_OVERRIDES_SYNC + 0 + + + C_HAS_THRESH0 + 0 + + + C_HAS_LOAD + 0 + + + C_LOAD_LOW + 0 + + + C_LATENCY + 1 + + + C_FB_LATENCY + 0 + + + C_AINIT_VAL + 0 + + + C_SINIT_VAL + 0 + + + C_SCLR_OVERRIDES_SSET + 1 + + + C_HAS_SSET + 0 + + + C_HAS_SINIT + 0 + + + + + + choice_list_424c9206 + Reset_Overrides_Set + Set_Overrides_Reset + + + choice_list_57191ce7 + UP + DOWN + UPDOWN + + + choice_list_70f31904 + Fabric + DSP48 + + + choice_list_93ab811d + Automatic + Manual + + + choice_list_dd432bf4 + CE_Overrides_Sync + Sync_Overrides_CE + + + choice_list_eb22ba99 + Active_High + Active_Low + + + The Xilinx LogiCORE Binary Counter creates up counters, down counters, and up/down counters with output widths ranging up to 256 bits. The upper count limit is user programmable, and the counter's increment value can either be user-defined, or specified via an external input port. + + + Component_Name + c_counter_binary_0 + + + Implementation + Fabric + + + + true + + + + + + Output_Width + 16 + + + + true + + + + + + Increment_Value + 1 + + + + true + + + + + + Restrict_Count + false + + + + true + + + + + + Final_Count_Value + 1 + + + + false + + + + + + Count_Mode + UP + + + + true + + + + + + Sync_Threshold_Output + false + + + + true + + + + + + Threshold_Value + 1 + + + + false + + + + + + CE + false + + + + true + + + + + + SCLR + false + + + + true + + + + + + SSET + false + + + + true + + + + + + SINIT + false + + + + true + + + + + + SINIT_Value + 0 + + + + false + + + + + + SyncCtrlPriority + Reset_Overrides_Set + + + + false + + + + + + Sync_CE_Priority + Sync_Overrides_CE + + + + false + + + + + + AINIT_Value + 0 + + + + true + + + + + + Load + false + + + + true + + + + + + Latency_Configuration + Manual + + + + true + + + + + + Latency + 1 + + + + true + + + + + + Fb_Latency_Configuration + Manual + + + + true + + + + + + Fb_Latency + 0 + + + + true + + + + + + Load_Sense + Active_High + + + + false + + + + + + + + Binary Counter + 14 + + + + + + + 2020.2 + + + + + + + + -- cgit v1.2.3