From 7721980589f4c7fa811689e815a77d63f2556497 Mon Sep 17 00:00:00 2001 From: Ataberk Date: Thu, 2 May 2024 17:22:05 +0200 Subject: Add sources for U50 HBM2 --- .../sources_1/ip/rdback_fifo/rdback_fifo.xci | 580 +++++++++++++++++++++ 1 file changed, 580 insertions(+) create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci (limited to 'projects/U50-HBM/U50-HBM.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci') diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci new file mode 100644 index 0000000..2fb8110 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci @@ -0,0 +1,580 @@ + + + xilinx.com + xci + unknown + 1.0 + + + rdback_fifo + + + + + + 100000000 + 0 + 0 + 0.000 + + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 1 + 0 + 10 + BlankString + 512 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 256 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + virtexuplusHBM + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 6 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 4 + BlankString + 1 + 0 + 0 + 0 + 0 + 1 + 1kx36 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 895 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 894 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 2048 + 1 + 11 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + rdback_fifo + 64 + false + 10 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Builtin_FIFO + 0 + 895 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 894 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 512 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 256 + 2048 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + Single_Programmable_Empty_Threshold_Constant + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + Single_Programmable_Full_Threshold_Constant + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 11 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Synchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + true + false + false + true + Active_High + 0 + false + Active_High + 1 + false + 10 + true + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtexuplusHBM + xilinx.com:au50:part0:1.3 + + xcu50 + fsvh2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.2.3