From 7721980589f4c7fa811689e815a77d63f2556497 Mon Sep 17 00:00:00 2001 From: Ataberk Date: Thu, 2 May 2024 17:22:05 +0200 Subject: Add sources for U50 HBM2 --- .../U50-HBM/U50-HBM.srcs/sim_1/new/sim_tb_top.v | 43 + .../axis_clock_converter/axis_clock_converter.xci | 133 + .../axis_clock_converter/axis_clock_converter.xml | 1478 + .../ip/c_counter_binary_0/c_counter_binary_0.xci | 109 + .../ip/c_counter_binary_0/c_counter_binary_0.xml | 927 + .../sources_1/ip/cdc_fifo/cdc_fifo.xci | 583 + .../sources_1/ip/cdc_fifo/cdc_fifo.xml | 10810 ++ .../sources_1/ip/clk_wiz_0/clk_wiz_0.xci | 747 + .../sources_1/ip/clk_wiz_0/clk_wiz_0.xml | 4695 + .../sources_1/ip/cmd_fifo/cmd_fifo.xci | 583 + .../sources_1/ip/cmd_fifo/cmd_fifo.xml | 10807 ++ .../U50-HBM.srcs/sources_1/ip/hbm_0/hbm_0.xci | 7676 + .../U50-HBM.srcs/sources_1/ip/hbm_0/hbm_0.xml | 159882 ++++++++++++++++++ .../sources_1/ip/instr_blk_mem/instr_blk_mem.xci | 317 + .../sources_1/ip/instr_blk_mem/instr_blk_mem.xml | 4180 + .../ip/instr_blk_mem_sim/instr_blk_mem_sim.xci | 318 + .../ip/instr_blk_mem_sim/instr_blk_mem_sim.xml | 4181 + .../sources_1/ip/pr_read_mem/pr_read_mem.xci | 318 + .../sources_1/ip/pr_read_mem/pr_read_mem.xml | 4180 + .../sources_1/ip/pr_ref_mem/pr_ref_mem.xci | 318 + .../sources_1/ip/pr_ref_mem/pr_ref_mem.xml | 4181 + .../sources_1/ip/rdback_fifo/rdback_fifo.xci | 580 + .../sources_1/ip/rdback_fifo/rdback_fifo.xml | 10791 ++ .../sources_1/ip/scratchpad/scratchpad.xci | 316 + .../sources_1/ip/scratchpad/scratchpad.xml | 4179 + .../sources_1/ip/wrdata_fifo/wrdata_fifo.xci | 583 + .../sources_1/ip/wrdata_fifo/wrdata_fifo.xml | 10807 ++ .../ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xci | 1433 + .../ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xml | 22837 +++ .../sources_1/ip/xdma/ip_0/xdma_pcie4c_ip.xci | 1642 + .../sources_1/ip/xdma/ip_0/xdma_pcie4c_ip.xml | 31789 ++++ .../ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci | 328 + .../ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xml | 4188 + .../xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci | 328 + .../xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xml | 4188 + .../U50-HBM.srcs/sources_1/ip/xdma/xdma.xci | 2286 + .../U50-HBM.srcs/sources_1/ip/xdma/xdma.xml | 60393 +++++++ .../sources_1/ip/zq_calib_mem/zq_calib_mem.xci | 318 + .../sources_1/ip/zq_calib_mem/zq_calib_mem.xml | 4181 + 39 files changed, 377633 insertions(+) create mode 100644 projects/U50-HBM/U50-HBM.srcs/sim_1/new/sim_tb_top.v create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cdc_fifo/cdc_fifo.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cdc_fifo/cdc_fifo.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cmd_fifo/cmd_fifo.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cmd_fifo/cmd_fifo.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/hbm_0/hbm_0.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/hbm_0/hbm_0.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/wrdata_fifo/wrdata_fifo.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/wrdata_fifo/wrdata_fifo.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4c_ip.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4c_ip.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/xdma.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/xdma.xml create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci create mode 100644 projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml (limited to 'projects/U50-HBM/U50-HBM.srcs') diff --git a/projects/U50-HBM/U50-HBM.srcs/sim_1/new/sim_tb_top.v b/projects/U50-HBM/U50-HBM.srcs/sim_1/new/sim_tb_top.v new file mode 100644 index 0000000..0f3824f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sim_1/new/sim_tb_top.v @@ -0,0 +1,43 @@ +`timescale 1ps / 1ps + +module sim_tb_top; + + // common signals + reg c0_sys_clk_p; + reg c0_sys_clk_n; + reg sys_rst_l; + + softmc_top UUT( + .c0_sys_clk_p(c0_sys_clk_p), + .c0_sys_clk_n(c0_sys_clk_n), + .sys_rst_l(sys_rst_l) + + ); + + initial + c0_sys_clk_p = 1'b0; + always + c0_sys_clk_p = #(10000/2.0) ~c0_sys_clk_p; + + initial + c0_sys_clk_n = 1'b1; + always + c0_sys_clk_n = #(10000/2.0) ~c0_sys_clk_n; + + + initial begin + sys_rst_l = 1'b0; + #200000; + sys_rst_l = 1'b0; + #4500000; + sys_rst_l = 1'b1; + end + + + + + + + + +endmodule diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci new file mode 100644 index 0000000..aa02768 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci @@ -0,0 +1,133 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axis_clock_converter + + + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + ACTIVE_LOW + + + + 100000000 + 0 + 0 + 0.000 + 0 + ACTIVE_LOW + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + ACTIVE_LOW + + + + 100000000 + 0 + 0 + 0.000 + 0 + ACTIVE_LOW + 0 + 0b00000000000000000000000000011011 + 256 + 1 + 1 + 1 + virtexuplusHBM + 1 + 2 + 2 + 1 + 0 + 1:2 + axis_clock_converter + 1 + 1 + 0 + 1 + 2 + 32 + 0 + 0 + 0 + virtexuplusHBM + xilinx.com:au50:part0:1.3 + + xcu50 + fsvh2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 23 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml new file mode 100644 index 0000000..6bf8248 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml @@ -0,0 +1,1478 @@ + + + xilinx.com + customized_ip + axis_clock_converter + 1.0 + + + S_AXIS + S_AXIS + + + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TDATA + + + s_axis_tdata + + + + + TSTRB + + + s_axis_tstrb + + + + + TKEEP + + + s_axis_tkeep + + + + + TLAST + + + s_axis_tlast + + + + + TID + + + s_axis_tid + + + + + TDEST + + + s_axis_tdest + + + + + TUSER + + + s_axis_tuser + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + 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7:1 + 6:1 + 5:1 + 4:1 + 3:1 + 2:1 + 1:1 + 1:2 + 1:3 + 1:4 + 1:5 + 1:6 + 1:7 + 1:8 + 1:9 + 1:10 + 1:11 + 1:12 + 1:13 + 1:14 + 1:15 + 1:16 + + + choice_pairs_37189c7b + 0 + 1 + + + choice_pairs_7e3eb5e2 + 0 + 1 + 2 + 3 + + + The AXI4-Stream Clock Converter IP provides the infrastructure to change the clocking rate between a AXI4-Stream master and slave. + + + TDATA_NUM_BYTES + TDATA Width (bytes) + 32 + + + + true + + + + + + TID_WIDTH + TID Width (bits) + 0 + + + + true + + + + + + TDEST_WIDTH + TDEST Width (bits) + 0 + + + + true + + + + + + TUSER_WIDTH + TUSER Width (bits) + 0 + + + + true + + + + + + IS_ACLK_ASYNC + Asynchronous Clocks + 1 + + + + true + + + + + + HAS_TSTRB + Enable TSTRB + 0 + + + + true + + + + + + HAS_TKEEP + Enable TKEEP + 1 + + + + true + + + + + + HAS_TLAST + Enable TLAST + 1 + + + + true + + + + + + SYNCHRONIZATION_STAGES + Synchronization Stages across Cross Clock Domain Logic + 2 + + + + true + + + + + + ACLK_RATIO + SI to MI Clock Ratio + 1:2 + + + + false + + + + + + ACLKEN_CONV_MODE + ACLKEN Conversion Mode + 0 + + + + true + + + + + + Component_Name + axis_clock_converter + + + + + AXI4-Stream Clock Converter + + XPM_CDC + XPM_FIFO + + 23 + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xci b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xci new file mode 100644 index 0000000..b49a36f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xci @@ -0,0 +1,109 @@ + + + xilinx.com + xci + unknown + 1.0 + + + c_counter_binary_0 + + + + 10000000 + 0 + 0 + 0.000 + undef + undef + undef + 0 + undef + undef + undef + undef + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 16 + virtexuplusHBM + 0 + false + c_counter_binary_0 + UP + 0 + Manual + 1 + Fabric + 1 + 1 + Manual + false + Active_High + 16 + false + false + false + 0 + false + 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C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_01387ad0 + 512 + 128 + 256 + 512 + 1024 + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_1359732e + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + + + choice_list_165ed04b + 64 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_19452de4 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_40558afa + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + choice_pairs_ef3e87e1 + Embedded_Reg + + + choice_pairs_f78383bc + Synchronous_Reset + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + cdc_fifo + + + + true + + + + + + Fifo_Implementation + Independent_Clocks_Builtin_FIFO + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + false + + + + true + + + + + + Input_Data_Width + 512 + + + + true + + + + + + Input_Depth + 2048 + + + + true + + + + + + Output_Data_Width + 512 + + + + false + + + + + + Output_Depth + 2048 + + + + false + + + + + + Enable_ECC + false + + + + true + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + false + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + false + + + + + + Full_Flags_Reset_Value + 0 + + + + false + + + + + + Use_Dout_Reset + true + + + + false + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + true + + + + + + Almost_Full_Flag + false + + + + false + + + + + + Almost_Empty_Flag + false + + + + false + + + + + + Valid_Flag + true + + + + true + + + + + + Valid_Sense + Active_High + + + + true + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + false + + + + false + + + + + + Data_Count_Width + 11 + + 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false + + + + + + READ_WRITE_MODE + READ_WRITE + + + + true + + + + + + ID_WIDTH + 0 + + + + false + + + + + + ADDRESS_WIDTH + 32 + + + + false + + + + + + DATA_WIDTH + 64 + + + + false + + + + + + AWUSER_Width + 0 + + + + false + + + + + + WUSER_Width + 0 + + + + false + + + + + + BUSER_Width + 0 + + + + false + + + + + + ARUSER_Width + 0 + + + + false + + + + + + RUSER_Width + 0 + + + + false + + + + + + TDATA_NUM_BYTES + 1 + + + + true + + + + + + TID_WIDTH + 0 + + + + false + + + + + + TDEST_WIDTH + 0 + + + + false + + + + + + TUSER_WIDTH + 4 + + + + false + + + + + + Enable_TREADY + true + + + + false + + + + + + Enable_TLAST + false + + + + true + + + + + + HAS_TSTRB + false + + + + false + + + + + + TSTRB_WIDTH + 1 + + + + false + + + + + + HAS_TKEEP + false + + + + false + + + + + + TKEEP_WIDTH + 1 + + + + false + + + + + + wach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wach + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wach + false + + + + false + + + + + + Inject_Sbit_Error_wach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wach + false + + + + false + + + + + + Input_Depth_wach + 16 + + + + true + + + + + + Enable_Data_Counts_wach + false + + + + false + + + + + + Programmable_Full_Type_wach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wdch + false + + + + false + + + + + + Inject_Sbit_Error_wdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wdch + false + + + + false + + + + + + Input_Depth_wdch + 1024 + + + + true + + + + + + Enable_Data_Counts_wdch + false + + + + false + + + + + + Programmable_Full_Type_wdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wrch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wrch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wrch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wrch + false + + + + false + + + + + + Inject_Sbit_Error_wrch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wrch + false + + + + false + + + + + + Input_Depth_wrch + 16 + + + + true + + + + + + Enable_Data_Counts_wrch + false + + + + false + + + + + + Programmable_Full_Type_wrch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wrch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wrch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wrch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rach + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rach + false + + + + false + + + + + + Inject_Sbit_Error_rach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rach + false + + + + false + + + + + + Input_Depth_rach + 16 + + + + true + + + + + + Enable_Data_Counts_rach + false + + + + false + + + + + + Programmable_Full_Type_rach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rdch + false + + + + false + + + + + + Inject_Sbit_Error_rdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rdch + false + + + + false + + + + + + Input_Depth_rdch + 1024 + + + + true + + + + + + Enable_Data_Counts_rdch + false + + + + false + + + + + + Programmable_Full_Type_rdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + axis_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_axis + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_axis + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_axis + false + + + + false + + + + + + Inject_Sbit_Error_axis + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_axis + Double Bit Error Injection + false + + + + false + + + + + + Input_Depth_axis + 1024 + + + + true + + + + + + Enable_Data_Counts_axis + false + + + + false + + + + + + Programmable_Full_Type_axis + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_axis + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_axis + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_axis + Empty Threshold Assert Value + 1022 + + + + false + + + + + + Register_Slice_Mode_wach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wrch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_axis + Register Slice Options + Fully_Registered + + + + true + + + + + + Underflow_Flag_AXI + Underflow Flag + false + + + + false + + + + + + Underflow_Sense_AXI + Underflow (Read Error) + Active_High + + + + false + + + + + + Overflow_Flag_AXI + Overflow Flag + false + + + + false + + + + + + Overflow_Sense_AXI + Overflow (Write Error) + Active_High + + + + false + + + + + + Disable_Timing_Violations_AXI + false + + + + true + + + + + + Add_NGC_Constraint_AXI + false + + + + true + + + + + + Enable_Common_Underflow + false + + + + true + + + + + + Enable_Common_Overflow + false + + + + true + + + + + + enable_read_pointer_increment_by2 + false + + + + true + + + + + + Use_Embedded_Registers_axis + false + + + + false + + + + + + enable_low_latency + false + + + + true + + + + + + use_dout_register + false + + + + false + + + + + + Master_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Slave_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Output_Register_Type + Embedded_Reg + + + + true + + + + + + Enable_Safety_Circuit + false + + + + false + + + + + + Enable_ECC_Type + Hard_ECC + + + + false + + + + + + C_SELECT_XPM + 0 + + + + + FIFO Generator + + XPM_MEMORY + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci new file mode 100644 index 0000000..d77c81a --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -0,0 +1,747 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_0 + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.000 + + + + 100000000 + 0 + 0 + 0.000 + + + + 100000000 + 0 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + PLL + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 100.0 + 0000 + 0000 + 150.00000 + 0000 + 0000 + 300.00000 + BUFG + 50.0 + false + 150.00000 + 0.000 + 50.000 + 150 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 300.00000 + 0.000 + 50.000 + 300 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_150MHz + clk_300MHz + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.5 + 1.5 + 1.5 + 1.5 + 1.5 + 1.5 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________100.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 9.000 + 0.000 + FALSE + 10.000 + 10.000 + 6.000 + 0.500 + 0.000 + FALSE + 3 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 1 + None + 0.010 + 0.010 + FALSE + 128.000 + 2.000 + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_150MHz__150.00000______0.000______50.0______127.220____105.461 + clk_300MHz__300.00000______0.000______50.0______111.879____105.461 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + 128.000 + 1.000 + LATENCY + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + Auto + AUTO + 100.000 + 0.010 + 10.000 + No_buffer + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1500.000 + 750.000 + clk_wiz_0 + PLL + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + Buffer + 127.220 + false + 105.461 + 50.000 + 150 + 0.000 + 1 + true + Buffer + 111.879 + false + 105.461 + 50.000 + 300 + 0.000 + 1 + true + Buffer + 115.831 + false + 87.180 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_150MHz + false + clk_300MHz + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_0 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 9 + 0.000 + false + 10.000 + 10.000 + 6 + 0.500 + 0.000 + false + 3 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + AUTO + 1 + None + 0.010 + 0.010 + false + 2 + false + false + LATENCY + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + Auto + mmcm_adv + 100.000 + 0.010 + 10.000 + No_buffer + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + virtexuplusHBM + xilinx.com:au50:part0:1.3 + + xcu50 + fsvh2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml new file mode 100644 index 0000000..7ee1e36 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml @@ -0,0 +1,4695 @@ + + + xilinx.com + customized_ip + clk_wiz_0 + 1.0 + + + s_axi_lite + S_AXI_LITE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 1 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + 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100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + ref_clk + ref_clk + + + + + + + CLK + + + ref_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axi_resetn + S_AXI_RESETN + + + + + + + RST + + + s_axi_aresetn + + + + + + ASSOCIATED_RESET + aresetn + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + intr + Intr + + + + + + + INTERRUPT + + + interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + none + + + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + CLK_IN1_D + CLK_IN1_D + Differential Clock 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100.0 + + + C_ENABLE_CLOCK_MONITOR + 0 + + + C_ENABLE_USER_CLOCK0 + 0 + + + C_ENABLE_USER_CLOCK1 + 0 + + + C_ENABLE_USER_CLOCK2 + 0 + + + C_ENABLE_USER_CLOCK3 + 0 + + + C_Enable_PLL0 + 0 + + + C_Enable_PLL1 + 0 + + + C_REF_CLK_FREQ + 100.0 + + + C_PRECISION + 1 + + + C_CLKOUT3_USED + 0 + + + C_CLKOUT4_USED + 0 + + + C_CLKOUT5_USED + 0 + + + C_CLKOUT6_USED + 0 + + + C_CLKOUT7_USED + 0 + + + C_USE_CLKOUT1_BAR + 0 + + + C_USE_CLKOUT2_BAR + 0 + + + C_USE_CLKOUT3_BAR + 0 + + + C_USE_CLKOUT4_BAR + 0 + + + c_component_name + clk_wiz_0 + + + C_PLATFORM + UNKNOWN + + + C_USE_FREQ_SYNTH + 1 + + + C_USE_PHASE_ALIGNMENT + 0 + + + C_PRIM_IN_JITTER + 0.010 + + + C_SECONDARY_IN_JITTER + 0.010 + + + C_JITTER_SEL + No_Jitter + + + C_USE_MIN_POWER + 0 + + + C_USE_MIN_O_JITTER + 0 + + + C_USE_MAX_I_JITTER + 0 + + + C_USE_DYN_PHASE_SHIFT + 0 + + + C_USE_INCLK_SWITCHOVER + 0 + + + C_USE_DYN_RECONFIG + 0 + + + C_USE_SPREAD_SPECTRUM + 0 + + + C_USE_FAST_SIMULATION + 0 + + + C_PRIMTYPE_SEL + AUTO + + + C_USE_CLK_VALID + 0 + + + C_PRIM_IN_FREQ + 100.000 + + + C_PRIM_IN_TIMEPERIOD + 10.000 + + + C_IN_FREQ_UNITS + Units_MHz + + + C_SECONDARY_IN_FREQ + 100.000 + + + C_SECONDARY_IN_TIMEPERIOD + 10.000 + + + C_FEEDBACK_SOURCE + FDBK_AUTO + + + C_PRIM_SOURCE + No_buffer + + + C_PHASESHIFT_MODE + LATENCY + + + C_SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + C_CLKFB_IN_SIGNALING + SINGLE + + + C_USE_RESET + 0 + + + C_RESET_LOW + 0 + + + C_USE_LOCKED + 0 + + + C_USE_INCLK_STOPPED + 0 + + + C_USE_CLKFB_STOPPED + 0 + + + C_USE_POWER_DOWN + 0 + + + C_USE_STATUS + 0 + + + C_USE_FREEZE + 0 + + + C_NUM_OUT_CLKS + 2 + + + C_CLKOUT1_DRIVES + BUFG + + + C_CLKOUT2_DRIVES + BUFG + + + C_CLKOUT3_DRIVES + BUFG + + + C_CLKOUT4_DRIVES + BUFG + + + C_CLKOUT5_DRIVES + BUFG + + + C_CLKOUT6_DRIVES + BUFG + + + C_CLKOUT7_DRIVES + BUFG + + + C_INCLK_SUM_ROW0 + Input Clock Freq (MHz) Input Jitter (UI) + + + C_INCLK_SUM_ROW1 + __primary_________100.000____________0.010 + + + C_INCLK_SUM_ROW2 + no_secondary_input_clock + + + C_OUTCLK_SUM_ROW0A + C Outclk Sum Row0a + Output Output Phase Duty Cycle Pk-to-Pk Phase + + + C_OUTCLK_SUM_ROW0B + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + + + C_OUTCLK_SUM_ROW1 + clk_150MHz__150.00000______0.000______50.0______127.220____105.461 + + + C_OUTCLK_SUM_ROW2 + clk_300MHz__300.00000______0.000______50.0______111.879____105.461 + + + C_OUTCLK_SUM_ROW3 + no_CLK_OUT3_output + + + C_OUTCLK_SUM_ROW4 + no_CLK_OUT4_output + + + C_OUTCLK_SUM_ROW5 + no_CLK_OUT5_output + + + C_OUTCLK_SUM_ROW6 + no_CLK_OUT6_output + + + C_OUTCLK_SUM_ROW7 + no_CLK_OUT7_output + + + C_CLKOUT1_REQUESTED_OUT_FREQ + 150 + + + C_CLKOUT2_REQUESTED_OUT_FREQ + 300 + + + C_CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT1_REQUESTED_PHASE + 0.000 + + + C_CLKOUT2_REQUESTED_PHASE + 0.000 + + + C_CLKOUT3_REQUESTED_PHASE + 0.000 + + + C_CLKOUT4_REQUESTED_PHASE + 0.000 + + + C_CLKOUT5_REQUESTED_PHASE + 0.000 + + + C_CLKOUT6_REQUESTED_PHASE + 0.000 + + + C_CLKOUT7_REQUESTED_PHASE + 0.000 + + + C_CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT1_OUT_FREQ + 150.00000 + + + C_CLKOUT2_OUT_FREQ + 300.00000 + + + C_CLKOUT3_OUT_FREQ + 100.000 + + + C_CLKOUT4_OUT_FREQ + 100.000 + + + C_CLKOUT5_OUT_FREQ + 100.000 + + + C_CLKOUT6_OUT_FREQ + 100.000 + + + C_CLKOUT7_OUT_FREQ + 100.000 + + + C_CLKOUT1_PHASE + 0.000 + + + C_CLKOUT2_PHASE + 0.000 + + + C_CLKOUT3_PHASE + 0.000 + + + C_CLKOUT4_PHASE + 0.000 + + + C_CLKOUT5_PHASE + 0.000 + + + C_CLKOUT6_PHASE + 0.000 + + + C_CLKOUT7_PHASE + 0.000 + + + C_CLKOUT1_DUTY_CYCLE + 50.0 + + + C_CLKOUT2_DUTY_CYCLE + 50.0 + + + C_CLKOUT3_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_DUTY_CYCLE + 50.000 + + + C_USE_SAFE_CLOCK_STARTUP + 0 + + + C_USE_CLOCK_SEQUENCING + 0 + + + C_CLKOUT1_SEQUENCE_NUMBER + 1 + + + C_CLKOUT2_SEQUENCE_NUMBER + 1 + + + C_CLKOUT3_SEQUENCE_NUMBER + 1 + + + C_CLKOUT4_SEQUENCE_NUMBER + 1 + + + C_CLKOUT5_SEQUENCE_NUMBER + 1 + + + C_CLKOUT6_SEQUENCE_NUMBER + 1 + + + C_CLKOUT7_SEQUENCE_NUMBER + 1 + + + C_MMCM_NOTES + None + + + C_MMCM_BANDWIDTH + OPTIMIZED + + + C_MMCM_CLKFBOUT_MULT_F + 9.000 + + + C_MMCM_CLKIN1_PERIOD + 10.000 + + + C_MMCM_CLKIN2_PERIOD + 10.000 + + + C_MMCM_CLKOUT4_CASCADE + FALSE + + + C_MMCM_CLOCK_HOLD + FALSE + + + C_MMCM_COMPENSATION + AUTO + + + C_MMCM_DIVCLK_DIVIDE + 1 + + + C_MMCM_REF_JITTER1 + 0.010 + + + C_MMCM_REF_JITTER2 + 0.010 + + + C_MMCM_STARTUP_WAIT + FALSE + + + C_MMCM_CLKOUT0_DIVIDE_F + 6.000 + + + C_MMCM_CLKOUT1_DIVIDE + 3 + + + C_MMCM_CLKOUT2_DIVIDE + 1 + + + C_MMCM_CLKOUT3_DIVIDE + 1 + + + C_MMCM_CLKOUT4_DIVIDE + 1 + + + C_MMCM_CLKOUT5_DIVIDE + 1 + + + C_MMCM_CLKOUT6_DIVIDE + 1 + + + C_MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKFBOUT_PHASE + 0.000 + + + C_MMCM_CLKOUT0_PHASE + 0.000 + + + C_MMCM_CLKOUT1_PHASE + 0.000 + + + C_MMCM_CLKOUT2_PHASE + 0.000 + + + C_MMCM_CLKOUT3_PHASE + 0.000 + + + C_MMCM_CLKOUT4_PHASE + 0.000 + + + C_MMCM_CLKOUT5_PHASE + 0.000 + + + C_MMCM_CLKOUT6_PHASE + 0.000 + + + C_MMCM_CLKFBOUT_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT0_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT1_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT2_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT3_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT4_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT5_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT6_USE_FINE_PS + FALSE + + + C_PLL_NOTES + No notes + + + C_PLL_BANDWIDTH + OPTIMIZED + + + C_PLL_CLK_FEEDBACK + CLKFBOUT + + + C_PLL_CLKFBOUT_MULT + 1 + + + C_PLL_CLKIN_PERIOD + 1.000 + + + C_PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + C_PLL_DIVCLK_DIVIDE + 1 + + + C_PLL_REF_JITTER + 0.010 + + + C_PLL_CLKOUT0_DIVIDE + 1 + + + C_PLL_CLKOUT1_DIVIDE + 1 + + + C_PLL_CLKOUT2_DIVIDE + 1 + + + C_PLL_CLKOUT3_DIVIDE + 1 + + + C_PLL_CLKOUT4_DIVIDE + 1 + + + C_PLL_CLKOUT5_DIVIDE + 1 + + + C_PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_PLL_CLKFBOUT_PHASE + 0.000 + + + C_PLL_CLKOUT0_PHASE + 0.000 + + + C_PLL_CLKOUT1_PHASE + 0.000 + + + C_PLL_CLKOUT2_PHASE + 0.000 + + + C_PLL_CLKOUT3_PHASE + 0.000 + + + C_PLL_CLKOUT4_PHASE + 0.000 + + + C_PLL_CLKOUT5_PHASE + 0.000 + + + C_CLOCK_MGR_TYPE + NA + + + C_OVERRIDE_MMCM + 0 + + + C_OVERRIDE_PLL + 0 + + + C_PRIMARY_PORT + clk_in1 + + + C_SECONDARY_PORT + clk_in2 + + + C_CLK_OUT1_PORT + clk_150MHz + + + C_CLK_OUT2_PORT + clk_300MHz + + + C_CLK_OUT3_PORT + clk_out3 + + + C_CLK_OUT4_PORT + clk_out4 + + + C_CLK_OUT5_PORT + clk_out5 + + + C_CLK_OUT6_PORT + clk_out6 + + + C_CLK_OUT7_PORT + clk_out7 + + + C_RESET_PORT + reset + + + C_LOCKED_PORT + locked + + + C_CLKFB_IN_PORT + clkfb_in + + + C_CLKFB_IN_P_PORT + clkfb_in_p + + + C_CLKFB_IN_N_PORT + clkfb_in_n + + + C_CLKFB_OUT_PORT + clkfb_out + + + C_CLKFB_OUT_P_PORT + clkfb_out_p + + + C_CLKFB_OUT_N_PORT + clkfb_out_n + + + C_POWER_DOWN_PORT + power_down + + + C_DADDR_PORT + daddr + + + C_DCLK_PORT + dclk + + + C_DRDY_PORT + drdy + + + C_DWE_PORT + dwe + + + C_DIN_PORT + din + + + C_DOUT_PORT + dout + + + C_DEN_PORT + den + + + C_PSCLK_PORT + psclk + + + C_PSEN_PORT + psen + + + C_PSINCDEC_PORT + psincdec + + + C_PSDONE_PORT + psdone + + + C_CLK_VALID_PORT + CLK_VALID + + + C_STATUS_PORT + STATUS + + + C_CLK_IN_SEL_PORT + clk_in_sel + + + C_INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + C_CLKFB_STOPPED_PORT + clkfb_stopped + + + C_CLKIN1_JITTER_PS + 100.0 + + + C_CLKIN2_JITTER_PS + 100.0 + + + C_PRIMITIVE + Auto + + + C_SS_MODE + CENTER_HIGH + + + C_SS_MOD_PERIOD + 4000 + + + C_SS_MOD_TIME + 0.004 + + + C_HAS_CDDC + 0 + + + C_CDDCDONE_PORT + cddcdone + + + C_CDDCREQ_PORT + cddcreq + + + C_CLKOUTPHY_MODE + VCO + + + C_ENABLE_CLKOUTPHY + 0 + + + C_INTERFACE_SELECTION + 0 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 11 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_POWER_REG + 0000 + + + C_CLKOUT0_1 + 0000 + + + C_CLKOUT0_2 + 0000 + + + C_CLKOUT1_1 + 0000 + + + C_CLKOUT1_2 + 0000 + + + C_CLKOUT2_1 + 0000 + + + C_CLKOUT2_2 + 0000 + + + C_CLKOUT3_1 + 0000 + + + C_CLKOUT3_2 + 0000 + + + C_CLKOUT4_1 + 0000 + + + C_CLKOUT4_2 + 0000 + + + C_CLKOUT5_1 + 0000 + + + C_CLKOUT5_2 + 0000 + + + C_CLKOUT6_1 + 0000 + + + C_CLKOUT6_2 + 0000 + + + C_CLKFBOUT_1 + 0000 + + + C_CLKFBOUT_2 + 0000 + + + C_DIVCLK + 0000 + + + C_LOCK_1 + 0000 + + + C_LOCK_2 + 0000 + + + C_LOCK_3 + 0000 + + + C_FILTER_1 + 0000 + + + C_FILTER_2 + 0000 + + + C_DIVIDE1_AUTO + 1 + + + C_DIVIDE2_AUTO + 0.5 + + + C_DIVIDE3_AUTO + 1.5 + + + C_DIVIDE4_AUTO + 1.5 + + + C_DIVIDE5_AUTO + 1.5 + + + C_DIVIDE6_AUTO + 1.5 + + + C_DIVIDE7_AUTO + 1.5 + + + C_PLLBUFGCEDIV + false + + + C_MMCMBUFGCEDIV + false + + + C_PLLBUFGCEDIV1 + false + + + C_PLLBUFGCEDIV2 + false + + + C_PLLBUFGCEDIV3 + false + + + C_PLLBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV1 + false + + + C_MMCMBUFGCEDIV2 + false + + + C_MMCMBUFGCEDIV3 + false + + + C_MMCMBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV5 + false + + + C_MMCMBUFGCEDIV6 + false + + + C_MMCMBUFGCEDIV7 + false + + + C_CLKOUT1_MATCHED_ROUTING + false + + + C_CLKOUT2_MATCHED_ROUTING + false + + + C_CLKOUT3_MATCHED_ROUTING + false + + + C_CLKOUT4_MATCHED_ROUTING + false + + + C_CLKOUT5_MATCHED_ROUTING + false + + + C_CLKOUT6_MATCHED_ROUTING + false + + + C_CLKOUT7_MATCHED_ROUTING + false + + + C_CLKOUT0_ACTUAL_FREQ + 150.00000 + + + C_CLKOUT1_ACTUAL_FREQ + 300.00000 + + + C_CLKOUT2_ACTUAL_FREQ + 100.000 + + + C_CLKOUT3_ACTUAL_FREQ + 100.000 + + + C_CLKOUT4_ACTUAL_FREQ + 100.000 + + + C_CLKOUT5_ACTUAL_FREQ + 100.000 + + + C_CLKOUT6_ACTUAL_FREQ + 100.000 + + + C_M_MAX + 128.000 + + + C_M_MIN + 2.000 + + + C_D_MAX + 93.000 + + + C_D_MIN + 1.000 + + + C_O_MAX + 128.000 + + + C_O_MIN + 1.000 + + + C_VCO_MIN + 750.000 + + + C_VCO_MAX + 1500.000 + + + + + + choice_list_1d3de01d + WAVEFORM + LATENCY + + + choice_list_876bfc32 + UI + PS + + + choice_list_a9bdfce0 + LOW + HIGH + OPTIMIZED + + + choice_list_ac75ef1e + Custom + + + choice_list_b9d38208 + CLKFBOUT + CLKOUT0 + + + choice_list_d0ea4aeb + MMCM + PLL + Auto + + + choice_pairs_035ca1c3 + SYSTEM_SYNCHRONOUS + SOURCE_SYNCHRONOUS + INTERNAL + EXTERNAL + + + choice_pairs_0920eb1b + Custom + sys_diff_clock + + + choice_pairs_11d71346 + Single_ended_clock_capable_pin + Differential_clock_capable_pin + Global_buffer + No_buffer + + + choice_pairs_15c806d5 + FDBK_AUTO + FDBK_AUTO_OFFCHIP + FDBK_ONCHIP + FDBK_OFFCHIP + + + choice_pairs_39d99e50 + Buffer + Buffer_with_CE + BUFG + BUFGCE + BUFGCE_DIV + No_buffer + + + choice_pairs_3c2d3ec7 + SINGLE + DIFF + + + choice_pairs_77d3d587 + MMCM + PLL + BUFGCE_DIV + + + choice_pairs_8b28f1f7 + Enable_AXI + Enable_DRP + + + choice_pairs_8eea9b32 + Units_MHz + Units_ns + + + choice_pairs_94e02745 + AUTO + EXTERNAL + INTERNAL + BUF_IN + ZHOLD + + + choice_pairs_a4fbc00c + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a7c40375 + Custom + cmc_clk + hbm_clk + pcie_refclk + qsfp_161mhz + qsfp_322mhz + + + choice_pairs_a8642b4c + No_Jitter + Min_O_Jitter + Max_I_Jitter + + + choice_pairs_c5ef7212 + Units_UI + Units_ps + + + choice_pairs_e1c87518 + REL_PRIMARY + REL_SECONDARY + + + choice_pairs_f4e10086 + CENTER_HIGH + CENTER_LOW + DOWN_HIGH + DOWN_LOW + + + choice_pairs_f669c2f5 + frequency + Time + + + The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. + + + Component_Name + clk_wiz_0 + + + USER_CLK_FREQ0 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ1 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ2 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ3 + User Frequency(MHz) + 100.0 + + + ENABLE_CLOCK_MONITOR + Enable Clock Monitoring + false + + + ENABLE_USER_CLOCK0 + User Clock + false + + + ENABLE_USER_CLOCK1 + User Clock + false + + + ENABLE_USER_CLOCK2 + User Clock + false + + + ENABLE_USER_CLOCK3 + User Clock + false + + + Enable_PLL0 + User Clock + false + + + Enable_PLL1 + User Clock + false + + + REF_CLK_FREQ + Reference Frequency(MHz) + 100.0 + + + PRECISION + Tolerance(MHz) + 1 + + + PRIMITIVE + Primitive + Auto + + + PRIMTYPE_SEL + Primtype Sel + mmcm_adv + + + CLOCK_MGR_TYPE + Clock Mgr Type + auto + + + USE_FREQ_SYNTH + true + + + USE_SPREAD_SPECTRUM + false + + + USE_PHASE_ALIGNMENT + false + + + USE_MIN_POWER + false + + + USE_DYN_PHASE_SHIFT + false + + + USE_DYN_RECONFIG + false + + + JITTER_SEL + No_Jitter + + + PRIM_IN_FREQ + 100.000 + + + PRIM_IN_TIMEPERIOD + 10.000 + + + IN_FREQ_UNITS + Units_MHz + + + PHASESHIFT_MODE + LATENCY + + + IN_JITTER_UNITS + Units_UI + + + RELATIVE_INCLK + REL_PRIMARY + + + USE_INCLK_SWITCHOVER + false + + + SECONDARY_IN_FREQ + 100.000 + + + SECONDARY_IN_TIMEPERIOD + 10.000 + + + SECONDARY_PORT + clk_in2 + + + SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + JITTER_OPTIONS + UI + + + CLKIN1_UI_JITTER + 0.010 + + + CLKIN2_UI_JITTER + 0.010 + + + PRIM_IN_JITTER + 0.010 + + + SECONDARY_IN_JITTER + 0.010 + + + CLKIN1_JITTER_PS + 100.0 + + + CLKIN2_JITTER_PS + 100.0 + + + CLKOUT1_USED + true + + + CLKOUT2_USED + true + + + CLKOUT3_USED + false + + + CLKOUT4_USED + false + + + CLKOUT5_USED + false + + + CLKOUT6_USED + false + + + CLKOUT7_USED + false + + + NUM_OUT_CLKS + 2 + + + CLK_OUT1_USE_FINE_PS_GUI + false + + + CLK_OUT2_USE_FINE_PS_GUI + false + + + CLK_OUT3_USE_FINE_PS_GUI + false + + + CLK_OUT4_USE_FINE_PS_GUI + false + + + CLK_OUT5_USE_FINE_PS_GUI + false + + + CLK_OUT6_USE_FINE_PS_GUI + false + + + CLK_OUT7_USE_FINE_PS_GUI + false + + + PRIMARY_PORT + clk_in1 + + + CLK_OUT1_PORT + clk_150MHz + + + CLK_OUT2_PORT + clk_300MHz + + + CLK_OUT3_PORT + clk_out3 + + + CLK_OUT4_PORT + clk_out4 + + + CLK_OUT5_PORT + clk_out5 + + + CLK_OUT6_PORT + clk_out6 + + + CLK_OUT7_PORT + clk_out7 + + + DADDR_PORT + daddr + + + DCLK_PORT + dclk + + + DRDY_PORT + drdy + + + DWE_PORT + dwe + + + DIN_PORT + din + + + DOUT_PORT + dout + + + DEN_PORT + den + + + PSCLK_PORT + psclk + + + PSEN_PORT + psen + + + PSINCDEC_PORT + psincdec + + + PSDONE_PORT + psdone + + + CLKOUT1_REQUESTED_OUT_FREQ + 150 + + + CLKOUT1_REQUESTED_PHASE + 0.000 + + + CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT2_REQUESTED_OUT_FREQ + 300 + + + CLKOUT2_REQUESTED_PHASE + 0.000 + + + CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT3_REQUESTED_PHASE + 0.000 + + + CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT4_REQUESTED_PHASE + 0.000 + + + CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT5_REQUESTED_PHASE + 0.000 + + + CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT6_REQUESTED_PHASE + 0.000 + + + CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT7_REQUESTED_PHASE + 0.000 + + + CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + USE_MAX_I_JITTER + false + + + USE_MIN_O_JITTER + false + + + CLKOUT1_MATCHED_ROUTING + false + + + CLKOUT2_MATCHED_ROUTING + false + + + CLKOUT3_MATCHED_ROUTING + false + + + CLKOUT4_MATCHED_ROUTING + false + + + CLKOUT5_MATCHED_ROUTING + false + + + CLKOUT6_MATCHED_ROUTING + false + + + CLKOUT7_MATCHED_ROUTING + false + + + PRIM_SOURCE + No_buffer + + + CLKOUT1_DRIVES + Buffer + + + CLKOUT2_DRIVES + Buffer + + + CLKOUT3_DRIVES + Buffer + + + CLKOUT4_DRIVES + Buffer + + + CLKOUT5_DRIVES + Buffer + + + CLKOUT6_DRIVES + Buffer + + + CLKOUT7_DRIVES + Buffer + + + FEEDBACK_SOURCE + FDBK_AUTO + + + CLKFB_IN_SIGNALING + SINGLE + + + CLKFB_IN_PORT + clkfb_in + + + CLKFB_IN_P_PORT + clkfb_in_p + + + CLKFB_IN_N_PORT + clkfb_in_n + + + CLKFB_OUT_PORT + clkfb_out + + + CLKFB_OUT_P_PORT + clkfb_out_p + + + CLKFB_OUT_N_PORT + clkfb_out_n + + + PLATFORM + UNKNOWN + + + SUMMARY_STRINGS + empty + + + USE_LOCKED + false + + + CALC_DONE + empty + + + USE_RESET + false + + + USE_POWER_DOWN + false + + + USE_STATUS + false + + + USE_FREEZE + false + + + USE_CLK_VALID + false + + + USE_INCLK_STOPPED + false + + + USE_CLKFB_STOPPED + false + + + RESET_PORT + reset + + + LOCKED_PORT + locked + + + POWER_DOWN_PORT + power_down + + + CLK_VALID_PORT + CLK_VALID + + + STATUS_PORT + STATUS + + + CLK_IN_SEL_PORT + clk_in_sel + + + INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + CLKFB_STOPPED_PORT + clkfb_stopped + + + SS_MODE + CENTER_HIGH + + + SS_MOD_FREQ + 250 + + + SS_MOD_TIME + 0.004 + + + OVERRIDE_MMCM + false + + + MMCM_NOTES + None + + + MMCM_DIVCLK_DIVIDE + 1 + + + MMCM_BANDWIDTH + OPTIMIZED + + + MMCM_CLKFBOUT_MULT_F + 9 + + + MMCM_CLKFBOUT_PHASE + 0.000 + + + MMCM_CLKFBOUT_USE_FINE_PS + false + + + MMCM_CLKIN1_PERIOD + 10.000 + + + MMCM_CLKIN2_PERIOD + 10.000 + + + MMCM_CLKOUT4_CASCADE + false + + + MMCM_CLOCK_HOLD + false + + + MMCM_COMPENSATION + AUTO + + + MMCM_REF_JITTER1 + 0.010 + + + MMCM_REF_JITTER2 + 0.010 + + + MMCM_STARTUP_WAIT + false + + + MMCM_CLKOUT0_DIVIDE_F + 6 + + + MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT0_PHASE + 0.000 + + + MMCM_CLKOUT0_USE_FINE_PS + false + + + MMCM_CLKOUT1_DIVIDE + 3 + + + MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT1_PHASE + 0.000 + + + MMCM_CLKOUT1_USE_FINE_PS + false + + + MMCM_CLKOUT2_DIVIDE + 1 + + + MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT2_PHASE + 0.000 + + + MMCM_CLKOUT2_USE_FINE_PS + false + + + MMCM_CLKOUT3_DIVIDE + 1 + + + MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT3_PHASE + 0.000 + + + MMCM_CLKOUT3_USE_FINE_PS + false + + + MMCM_CLKOUT4_DIVIDE + 1 + + + MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT4_PHASE + 0.000 + + + MMCM_CLKOUT4_USE_FINE_PS + false + + + MMCM_CLKOUT5_DIVIDE + 1 + + + MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT5_PHASE + 0.000 + + + MMCM_CLKOUT5_USE_FINE_PS + false + + + MMCM_CLKOUT6_DIVIDE + 1 + + + MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT6_PHASE + 0.000 + + + MMCM_CLKOUT6_USE_FINE_PS + false + + + OVERRIDE_PLL + false + + + PLL_NOTES + None + + + PLL_BANDWIDTH + OPTIMIZED + + + PLL_CLKFBOUT_MULT + 4 + + + PLL_CLKFBOUT_PHASE + 0.000 + + + PLL_CLK_FEEDBACK + CLKFBOUT + + + PLL_DIVCLK_DIVIDE + 1 + + + PLL_CLKIN_PERIOD + 10.000 + + + PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + PLL_REF_JITTER + 0.010 + + + PLL_CLKOUT0_DIVIDE + 1 + + + PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT0_PHASE + 0.000 + + + PLL_CLKOUT1_DIVIDE + 1 + + + PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT1_PHASE + 0.000 + + + PLL_CLKOUT2_DIVIDE + 1 + + + PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT2_PHASE + 0.000 + + + PLL_CLKOUT3_DIVIDE + 1 + + + PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT3_PHASE + 0.000 + + + PLL_CLKOUT4_DIVIDE + 1 + + + PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT4_PHASE + 0.000 + + + PLL_CLKOUT5_DIVIDE + 1 + + + PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT5_PHASE + 0.000 + + + RESET_TYPE + Reset Type + ACTIVE_HIGH + + + USE_SAFE_CLOCK_STARTUP + false + + + USE_CLOCK_SEQUENCING + false + + + CLKOUT1_SEQUENCE_NUMBER + 1 + + + CLKOUT2_SEQUENCE_NUMBER + 1 + + + CLKOUT3_SEQUENCE_NUMBER + 1 + + + CLKOUT4_SEQUENCE_NUMBER + 1 + + + CLKOUT5_SEQUENCE_NUMBER + 1 + + + CLKOUT6_SEQUENCE_NUMBER + 1 + + + CLKOUT7_SEQUENCE_NUMBER + 1 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_IN1_BOARD_INTERFACE + Custom + + + CLK_IN2_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN1_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN2_BOARD_INTERFACE + Custom + + + AUTO_PRIMITIVE + PLL + + + RESET_BOARD_INTERFACE + Custom + + + ENABLE_CDDC + false + + + CDDCDONE_PORT + cddcdone + + + CDDCREQ_PORT + cddcreq + + + ENABLE_CLKOUTPHY + false + + + CLKOUTPHY_REQUESTED_FREQ + 600.000 + + + CLKOUT1_JITTER + Clkout1 Jitter + 127.220 + + + CLKOUT1_PHASE_ERROR + Clkout1 Phase + 105.461 + + + CLKOUT2_JITTER + Clkout2 Jitter + 111.879 + + + CLKOUT2_PHASE_ERROR + Clkout2 Phase + 105.461 + + + CLKOUT3_JITTER + Clkout3 Jitter + 115.831 + + + CLKOUT3_PHASE_ERROR + Clkout3 Phase + 87.180 + + + CLKOUT4_JITTER + Clkout4 Jitter + 0.0 + + + CLKOUT4_PHASE_ERROR + Clkout4 Phase + 0.0 + + + CLKOUT5_JITTER + Clkout5 Jitter + 0.0 + + + CLKOUT5_PHASE_ERROR + Clkout5 Phase + 0.0 + + + CLKOUT6_JITTER + Clkout6 Jitter + 0.0 + + + CLKOUT6_PHASE_ERROR + Clkout6 Phase + 0.0 + + + CLKOUT7_JITTER + Clkout7 Jitter + 0.0 + + + CLKOUT7_PHASE_ERROR + Clkout7 Phase + 0.0 + + + INPUT_MODE + frequency + + + INTERFACE_SELECTION + Enable_AXI + + + AXI_DRP + Write DRP registers + false + + + PHASE_DUTY_CONFIG + Phase Duty Cycle Config + false + + + + + Clocking Wizard + + XPM_CDC + + 6 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cmd_fifo/cmd_fifo.xci b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cmd_fifo/cmd_fifo.xci new file mode 100644 index 0000000..74db541 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/cmd_fifo/cmd_fifo.xci @@ -0,0 +1,583 @@ + + + xilinx.com + xci + unknown + 1.0 + + + cmd_fifo + + + + + + 100000000 + 0 + 0 + 0.000 + + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 300000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 150000000 + 0 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 9 + BlankString + 128 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 64 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + virtexuplusHBM + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 6 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 4 + BlankString + 1 + 0 + 0 + 0 + 2 + 1 + 512x72 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 510 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 509 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 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axis_prog_full + + out + + + STD_LOGIC + dummy_view + + + + 0 + + + + + + false + + + + + + axis_prog_empty + + out + + + STD_LOGIC + dummy_view + + + + 1 + + + + + + false + + + + + + + + C_COMMON_CLOCK + 0 + + + C_SELECT_XPM + 0 + + + C_COUNT_TYPE + 0 + + + C_DATA_COUNT_WIDTH + 9 + + + C_DEFAULT_VALUE + BlankString + + + C_DIN_WIDTH + 128 + + + C_DOUT_RST_VAL + 0 + + + C_DOUT_WIDTH + 64 + + + C_ENABLE_RLOCS + 0 + + + C_FAMILY + virtexuplusHBM + + + C_FULL_FLAGS_RST_VAL + 0 + + + C_HAS_ALMOST_EMPTY + 0 + + + C_HAS_ALMOST_FULL + 0 + + + C_HAS_BACKUP + 0 + + + C_HAS_DATA_COUNT + 0 + + + C_HAS_INT_CLK + 0 + + + C_HAS_MEMINIT_FILE + 0 + + + C_HAS_OVERFLOW + 0 + + + C_HAS_RD_DATA_COUNT + 0 + + + C_HAS_RD_RST + 0 + + + C_HAS_RST + 0 + + + C_HAS_SRST + 1 + + + C_HAS_UNDERFLOW + 0 + + + C_HAS_VALID + 0 + + + C_HAS_WR_ACK + 0 + + + C_HAS_WR_DATA_COUNT + 0 + + + C_HAS_WR_RST + 0 + + + C_IMPLEMENTATION_TYPE + 6 + + + C_INIT_WR_PNTR_VAL + 0 + + + C_MEMORY_TYPE + 4 + + + C_MIF_FILE_NAME + BlankString + + + C_OPTIMIZATION_MODE + 0 + + + C_OVERFLOW_LOW + 0 + + + C_PRELOAD_LATENCY + 2 + + + C_PRELOAD_REGS + 1 + + + C_PRIM_FIFO_TYPE + 512x72 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL + 2 + + + C_PROG_EMPTY_THRESH_NEGATE_VAL + 3 + + + C_PROG_EMPTY_TYPE + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL + 510 + + + C_PROG_FULL_THRESH_NEGATE_VAL + 509 + + + C_PROG_FULL_TYPE + 0 + + + C_RD_DATA_COUNT_WIDTH + 10 + + + C_RD_DEPTH + 1024 + + + C_RD_FREQ + 300 + + + C_RD_PNTR_WIDTH + 10 + + + C_UNDERFLOW_LOW + 0 + + + C_USE_DOUT_RST + 1 + + + C_USE_ECC + 0 + + + C_USE_EMBEDDED_REG + 1 + + + C_USE_PIPELINE_REG + 0 + + + C_POWER_SAVING_MODE + 0 + + + C_USE_FIFO16_FLAGS + 0 + + + C_USE_FWFT_DATA_COUNT + 0 + + + C_VALID_LOW + 0 + + + C_WR_ACK_LOW + 0 + + + C_WR_DATA_COUNT_WIDTH + 9 + + + C_WR_DEPTH + 512 + + + C_WR_FREQ + 150 + + + C_WR_PNTR_WIDTH + 9 + + + C_WR_RESPONSE_LATENCY + 1 + + + C_MSGON_VAL + 1 + + + C_ENABLE_RST_SYNC + 1 + + + C_EN_SAFETY_CKT + 0 + + + C_ERROR_INJECTION_TYPE + 0 + + + C_SYNCHRONIZER_STAGE + 2 + + + C_INTERFACE_TYPE + 0 + + + C_AXI_TYPE + 1 + + + C_HAS_AXI_WR_CHANNEL + 1 + + + C_HAS_AXI_RD_CHANNEL + 1 + + + C_HAS_SLAVE_CE + 0 + + + C_HAS_MASTER_CE + 0 + + + C_ADD_NGC_CONSTRAINT + 0 + + + C_USE_COMMON_OVERFLOW + 0 + + + C_USE_COMMON_UNDERFLOW + 0 + + + C_USE_DEFAULT_SETTINGS + 0 + + + C_AXI_ID_WIDTH + 1 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 64 + + + C_AXI_LEN_WIDTH + 8 + + + C_AXI_LOCK_WIDTH + 1 + + + C_HAS_AXI_ID + 0 + + + C_HAS_AXI_AWUSER + 0 + + + C_HAS_AXI_WUSER + 0 + + + C_HAS_AXI_BUSER + 0 + + + C_HAS_AXI_ARUSER + 0 + + + C_HAS_AXI_RUSER + 0 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_HAS_AXIS_TDATA + 1 + + + C_HAS_AXIS_TID + 0 + + + C_HAS_AXIS_TDEST + 0 + + + C_HAS_AXIS_TUSER + 1 + + + C_HAS_AXIS_TREADY + 1 + + + C_HAS_AXIS_TLAST + 0 + + + C_HAS_AXIS_TSTRB + 0 + + + C_HAS_AXIS_TKEEP + 0 + + + C_AXIS_TDATA_WIDTH + 8 + + + C_AXIS_TID_WIDTH + 1 + + + C_AXIS_TDEST_WIDTH + 1 + + + C_AXIS_TUSER_WIDTH + 4 + + + C_AXIS_TSTRB_WIDTH + 1 + + + C_AXIS_TKEEP_WIDTH + 1 + + + C_WACH_TYPE + 0 + + + C_WDCH_TYPE + 0 + + + C_WRCH_TYPE + 0 + + + C_RACH_TYPE + 0 + + + C_RDCH_TYPE + 0 + + + C_AXIS_TYPE + 0 + + + C_IMPLEMENTATION_TYPE_WACH + 1 + + + C_IMPLEMENTATION_TYPE_WDCH + 1 + + + C_IMPLEMENTATION_TYPE_WRCH + 1 + + + C_IMPLEMENTATION_TYPE_RACH + 1 + + + C_IMPLEMENTATION_TYPE_RDCH + 1 + + + C_IMPLEMENTATION_TYPE_AXIS + 1 + + + C_APPLICATION_TYPE_WACH + 0 + + + C_APPLICATION_TYPE_WDCH + 0 + + + C_APPLICATION_TYPE_WRCH + 0 + + + C_APPLICATION_TYPE_RACH + 0 + + + C_APPLICATION_TYPE_RDCH + 0 + + + C_APPLICATION_TYPE_AXIS + 0 + + + C_PRIM_FIFO_TYPE_WACH + 512x36 + + + C_PRIM_FIFO_TYPE_WDCH + 512x72 + + + C_PRIM_FIFO_TYPE_WRCH + 512x36 + + + C_PRIM_FIFO_TYPE_RACH + 512x36 + + + C_PRIM_FIFO_TYPE_RDCH + 512x72 + + + C_PRIM_FIFO_TYPE_AXIS + 1kx18 + + + C_USE_ECC_WACH + 0 + + + C_USE_ECC_WDCH + 0 + + + C_USE_ECC_WRCH + 0 + + + C_USE_ECC_RACH + 0 + + + C_USE_ECC_RDCH + 0 + + + C_USE_ECC_AXIS + 0 + + + C_ERROR_INJECTION_TYPE_WACH + 0 + + + C_ERROR_INJECTION_TYPE_WDCH + 0 + + + C_ERROR_INJECTION_TYPE_WRCH + 0 + + + C_ERROR_INJECTION_TYPE_RACH + 0 + + + C_ERROR_INJECTION_TYPE_RDCH + 0 + + + C_ERROR_INJECTION_TYPE_AXIS + 0 + + + C_DIN_WIDTH_WACH + 1 + + + C_DIN_WIDTH_WDCH + 64 + + + C_DIN_WIDTH_WRCH + 2 + + + C_DIN_WIDTH_RACH + 32 + + + C_DIN_WIDTH_RDCH + 64 + + + C_DIN_WIDTH_AXIS + 1 + + + C_WR_DEPTH_WACH + 16 + + + C_WR_DEPTH_WDCH + 1024 + + + C_WR_DEPTH_WRCH + 16 + + + C_WR_DEPTH_RACH + 16 + + + C_WR_DEPTH_RDCH + 1024 + + + C_WR_DEPTH_AXIS + 1024 + + + C_WR_PNTR_WIDTH_WACH + 4 + + + C_WR_PNTR_WIDTH_WDCH + 10 + + + C_WR_PNTR_WIDTH_WRCH + 4 + + + C_WR_PNTR_WIDTH_RACH + 4 + + + C_WR_PNTR_WIDTH_RDCH + 10 + + + C_WR_PNTR_WIDTH_AXIS + 10 + + + C_HAS_DATA_COUNTS_WACH + 0 + + + C_HAS_DATA_COUNTS_WDCH + 0 + + + C_HAS_DATA_COUNTS_WRCH + 0 + + + C_HAS_DATA_COUNTS_RACH + 0 + + + C_HAS_DATA_COUNTS_RDCH + 0 + + + C_HAS_DATA_COUNTS_AXIS + 0 + + + C_HAS_PROG_FLAGS_WACH + 0 + + + C_HAS_PROG_FLAGS_WDCH + 0 + + + C_HAS_PROG_FLAGS_WRCH + 0 + + + C_HAS_PROG_FLAGS_RACH + 0 + + + C_HAS_PROG_FLAGS_RDCH + 0 + + + C_HAS_PROG_FLAGS_AXIS + 0 + + + C_PROG_FULL_TYPE_WACH + 0 + + + C_PROG_FULL_TYPE_WDCH + 0 + + + C_PROG_FULL_TYPE_WRCH + 0 + + + C_PROG_FULL_TYPE_RACH + 0 + + + C_PROG_FULL_TYPE_RDCH + 0 + + + C_PROG_FULL_TYPE_AXIS + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WRCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_165ed04b + 64 + + + choice_list_62eb4a48 + 512 + 1024 + 2048 + 4096 + 8192 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_75e45d2a + 16 + 32 + 64 + 128 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_19452de4 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_40558afa + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + choice_pairs_ef3e87e1 + Embedded_Reg + + + choice_pairs_f78383bc + Synchronous_Reset + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + cmd_fifo + + + + true + + + + + + Fifo_Implementation + Independent_Clocks_Builtin_FIFO + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + true + + + + true + + + + + + Input_Data_Width + 128 + + + + true + + + + + + Input_Depth + 512 + + + + true + + + + + + Output_Data_Width + 64 + + + + true + + + + + + Output_Depth + 1024 + + + + false + + + + + + Enable_ECC + false + + + + false + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + false + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + false + + + + + + Full_Flags_Reset_Value + 0 + + + + false + + + + + + Use_Dout_Reset + true + + + + false + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + true + + + + + + Almost_Full_Flag + false + + + + false + + + + + + Almost_Empty_Flag + false + + + + false + + + + + + Valid_Flag + false + + + + true + + + + + + Valid_Sense + Active_High + + + + false + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + false + + + + false + + + + + + Data_Count_Width + 9 + + + + false + + + + + + Write_Data_Count + false + + + + false + + + + + + Write_Data_Count_Width + 9 + + + + false + + + + + + Read_Data_Count + false + + + + false + + + + + + Read_Data_Count_Width + 10 + + + + false + + + + + + Disable_Timing_Violations + false + + + + false + + + + + + Read_Clock_Frequency + 300 + + + + true + + + + + + Write_Clock_Frequency + 150 + + + + true + + + + + + Programmable_Full_Type + No_Programmable_Full_Threshold + + + + true + + + + + + Full_Threshold_Assert_Value + 510 + + + + false + + + + + + Full_Threshold_Negate_Value + 509 + + + + false + + + + + + Programmable_Empty_Type + No_Programmable_Empty_Threshold + + + + true + + + + + + Empty_Threshold_Assert_Value + 2 + + + + false + + + + + + Empty_Threshold_Negate_Value + 3 + + + + false + + + + + + PROTOCOL + AXI4 + + + + false + + + + + + Clock_Type_AXI + Common_Clock + + + + true + + + + + + HAS_ACLKEN + false + + + + false + + + + + + Clock_Enable_Type + Slave_Interface_Clock_Enable + + + + false + + + + + + READ_WRITE_MODE + READ_WRITE + + + + true + + + + + + ID_WIDTH + 0 + + + + false + + + + + + ADDRESS_WIDTH + 32 + + + + false + + + + + + DATA_WIDTH + 64 + + + + false + + + + + + AWUSER_Width + 0 + + + + false + + + + + + WUSER_Width + 0 + + + + false + + + + + + BUSER_Width + 0 + + + + false + + + + + + ARUSER_Width + 0 + + + + false + + + + + + RUSER_Width + 0 + + + + false + + + + + + TDATA_NUM_BYTES + 1 + + + + true + + + + + + TID_WIDTH + 0 + + + + false + + + + + + TDEST_WIDTH + 0 + + + + false + + + + + + TUSER_WIDTH + 4 + + + + false + + + + + + Enable_TREADY + true + + + + false + + + + + + Enable_TLAST + false + + + + true + + + + + + HAS_TSTRB + false + + + + false + + + + + + TSTRB_WIDTH + 1 + + + + false + + + + + + HAS_TKEEP + false + + + + false + + + + + + TKEEP_WIDTH + 1 + + + + false + + + + + + wach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wach + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wach + false + + + + false + + + + + + Inject_Sbit_Error_wach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wach + false + + + + false + + + + + + Input_Depth_wach + 16 + + + + true + + + + + + Enable_Data_Counts_wach + false + + + + false + + + + + + Programmable_Full_Type_wach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wdch + false + + + + false + + + + + + Inject_Sbit_Error_wdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wdch + false + + + + false + + + + + + Input_Depth_wdch + 1024 + + + + true + + + + + + Enable_Data_Counts_wdch + false + + + + false + + + + + + Programmable_Full_Type_wdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wrch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wrch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wrch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wrch + false + + + + false + + + + + + Inject_Sbit_Error_wrch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wrch + false + + + + false + + + + + + Input_Depth_wrch + 16 + + + + true + + + + + + Enable_Data_Counts_wrch + false + + + + false + + + + + + Programmable_Full_Type_wrch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wrch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wrch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wrch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rach + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rach + FIFO Application Type + Data_FIFO + + + + false + + + + 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AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_22_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_22_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_23_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_23_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + 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SAXI_14_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_14_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_15_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_15_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_16_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 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rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_19_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_19_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_20_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_20_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_21_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_21_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_22_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_22_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_23_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_23_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_24_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_24_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_25_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_25_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_26_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_26_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_27_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_27_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_28_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_28_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_29_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_29_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_30_8HI_wr_socket + AXIMM Write Socket + AXIMM socket for write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + width + 256 + + + + + + + 1 + + + + + SAXI_30_8HI_rd_socket + AXIMM Read Socket + AXIMM socket for read + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + width + 256 + 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+ + + CLK_SEL_02 + FALSE + + + CLK_SEL_03 + FALSE + + + CLK_SEL_04 + FALSE + + + CLK_SEL_05 + FALSE + + + CLK_SEL_06 + FALSE + + + CLK_SEL_07 + TRUE + + + CLK_SEL_08 + FALSE + + + CLK_SEL_09 + FALSE + + + CLK_SEL_10 + FALSE + + + CLK_SEL_11 + FALSE + + + CLK_SEL_12 + FALSE + + + CLK_SEL_13 + FALSE + + + CLK_SEL_14 + FALSE + + + CLK_SEL_15 + FALSE + + + CLK_SEL_16 + FALSE + + + CLK_SEL_17 + FALSE + + + CLK_SEL_18 + FALSE + + + CLK_SEL_19 + FALSE + + + CLK_SEL_20 + FALSE + + + CLK_SEL_21 + FALSE + + + CLK_SEL_22 + FALSE + + + CLK_SEL_23 + TRUE + + + CLK_SEL_24 + FALSE + + + CLK_SEL_25 + FALSE + + + CLK_SEL_26 + FALSE + + + CLK_SEL_27 + FALSE + + + CLK_SEL_28 + FALSE + + + CLK_SEL_29 + FALSE + + + CLK_SEL_30 + FALSE + + + CLK_SEL_31 + FALSE + + + DATARATE_STACK_0 + 1200 + + + DATARATE_STACK_1 + 1200 + + + READ_PERCENT_00 + 40 + + + READ_PERCENT_01 + 40 + + + READ_PERCENT_02 + 40 + + + READ_PERCENT_03 + 40 + + + READ_PERCENT_04 + 40 + + + READ_PERCENT_05 + 40 + + + READ_PERCENT_06 + 40 + + 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WRITE_PERCENT_11 + 40 + + + WRITE_PERCENT_12 + 40 + + + WRITE_PERCENT_13 + 40 + + + WRITE_PERCENT_14 + 40 + + + WRITE_PERCENT_15 + 40 + + + WRITE_PERCENT_16 + 40 + + + WRITE_PERCENT_17 + 40 + + + WRITE_PERCENT_18 + 40 + + + WRITE_PERCENT_19 + 40 + + + WRITE_PERCENT_20 + 40 + + + WRITE_PERCENT_21 + 40 + + + WRITE_PERCENT_22 + 40 + + + WRITE_PERCENT_23 + 40 + + + WRITE_PERCENT_24 + 40 + + + WRITE_PERCENT_25 + 40 + + + WRITE_PERCENT_26 + 40 + + + WRITE_PERCENT_27 + 40 + + + WRITE_PERCENT_28 + 40 + + + WRITE_PERCENT_29 + 40 + + + WRITE_PERCENT_30 + 40 + + + WRITE_PERCENT_31 + 40 + + + PAGEHIT_PERCENT_00 + 75 + + + PAGEHIT_PERCENT_01 + 75 + + + MC_ENABLE_00 + FALSE + + + MC_ENABLE_01 + FALSE + + + MC_ENABLE_02 + FALSE + + + MC_ENABLE_03 + FALSE + + + MC_ENABLE_04 + FALSE + + + MC_ENABLE_05 + FALSE + + + MC_ENABLE_06 + FALSE + + + MC_ENABLE_07 + FALSE + + + MC_ENABLE_08 + FALSE + + + MC_ENABLE_09 + FALSE + + + MC_ENABLE_10 + FALSE + + + MC_ENABLE_11 + FALSE + + + MC_ENABLE_12 + FALSE + + + MC_ENABLE_13 + FALSE + + + MC_ENABLE_14 + FALSE + + + MC_ENABLE_15 + FALSE + + + MC_ENABLE_APB_00 + FALSE + + + MC_ENABLE_APB_01 + FALSE + + + PHY_ENABLE_00 + TRUE + + + PHY_ENABLE_01 + TRUE + + + PHY_ENABLE_02 + TRUE + + + PHY_ENABLE_03 + TRUE + + + PHY_ENABLE_04 + TRUE + + + PHY_ENABLE_05 + TRUE + + + PHY_ENABLE_06 + TRUE + + + PHY_ENABLE_07 + TRUE + + + PHY_ENABLE_08 + TRUE + + + PHY_ENABLE_09 + TRUE + + + PHY_ENABLE_10 + TRUE + + + PHY_ENABLE_11 + TRUE + + + PHY_ENABLE_12 + TRUE + + + PHY_ENABLE_13 + TRUE + + + PHY_ENABLE_14 + TRUE + + + PHY_ENABLE_15 + TRUE + + + PHY_ENABLE_16 + TRUE + + + PHY_ENABLE_17 + TRUE + + + PHY_ENABLE_18 + TRUE + + + PHY_ENABLE_19 + TRUE + + + PHY_ENABLE_20 + TRUE + + + PHY_ENABLE_21 + TRUE + + + PHY_ENABLE_22 + TRUE + + + PHY_ENABLE_23 + TRUE + + + PHY_ENABLE_24 + TRUE + + + PHY_ENABLE_25 + TRUE + + + PHY_ENABLE_26 + TRUE + + + PHY_ENABLE_27 + TRUE + + + PHY_ENABLE_28 + TRUE + + + PHY_ENABLE_29 + TRUE + + + PHY_ENABLE_30 + TRUE + + + PHY_ENABLE_31 + TRUE + + + PHY_ENABLE_APB_00 + TRUE + + + PHY_ENABLE_APB_01 + TRUE + + + USER_MC0_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC1_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC2_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC3_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC4_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC5_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC6_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC7_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC8_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC9_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC10_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC11_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC12_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC13_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC14_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + USER_MC15_ADDR_BIT + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + simulation.tlm + + + + + SAXI_00 + true + + + simulation.tlm + + + + + SAXI_01 + true + + + simulation.tlm + + + + + SAXI_02 + true + + + simulation.tlm + + + + + SAXI_03 + true + + + simulation.tlm + + + + + SAXI_04 + true + + + simulation.tlm + + + + + SAXI_05 + true + + + simulation.tlm + + + + + SAXI_06 + true + + + simulation.tlm + + + + + SAXI_07 + true + + + simulation.tlm + + + + + SAXI_08 + true + + + simulation.tlm + + + + + SAXI_09 + true + + + simulation.tlm + + + + + SAXI_10 + true + + + simulation.tlm + + + + + SAXI_11 + true + + + simulation.tlm + + + + + SAXI_12 + true + + + simulation.tlm + + + + + SAXI_13 + true + + + simulation.tlm + + + + + SAXI_14 + true + + + simulation.tlm + + + + + SAXI_15 + true + + + simulation.tlm + + + + + SAXI_16 + true + + + simulation.tlm + + + + + SAXI_17 + true + + + simulation.tlm + + + + + SAXI_18 + true + + + simulation.tlm + + + + + SAXI_19 + true + + + simulation.tlm + + + + + SAXI_20 + true + + + simulation.tlm + + + + + SAXI_21 + true + + + simulation.tlm + + + + + SAXI_22 + true + + + simulation.tlm + + + + + SAXI_23 + true + + + simulation.tlm + + + + + SAXI_24 + true + + + simulation.tlm + + + + + SAXI_25 + true + + + simulation.tlm + + + + + SAXI_26 + true + + + simulation.tlm + + + + + SAXI_27 + true + + + simulation.tlm + + + + + SAXI_28 + true + + + simulation.tlm + + + + + SAXI_29 + true + + + simulation.tlm + + + + + SAXI_30 + true + + + simulation.tlm + + + + + SAXI_31 + true + + + simulation.tlm + + + + + STACK_8HI + false + + + simulation.tlm + + + + + + + + choice_list_09f2b396 + NON_SYNTHESIZABLE + SYNTHESIZABLE + + + choice_list_0ccad734 + 450 + + + choice_list_0da07c0e + ROW_BANK_COLUMN + ROW_COLUMN_BANK + BANK_ROW_COLUMN + 14R-2BA-1BG-5C-1BG + 2BA-14R-1BG-5C-1BG + + + choice_list_153d9765 + 4GB + 8GB + + + choice_list_15f907ff + 100 + 104 + 109 + 114 + 120 + 126 + 133 + 141 + 150 + 160 + 171 + 185 + 200 + 218 + 240 + 267 + 300 + + + choice_list_30725cf7 + LEFT + RIGHT + + + choice_list_3aa546d8 + MULTIPLE + + + choice_list_56638a14 + UC1899 + UC1299 + + + choice_list_606e5fda + AXI_16_ACLK + AXI_17_ACLK + AXI_18_ACLK + AXI_19_ACLK + AXI_20_ACLK + AXI_21_ACLK + AXI_22_ACLK + AXI_23_ACLK + AXI_24_ACLK + AXI_25_ACLK + AXI_26_ACLK + AXI_27_ACLK + AXI_28_ACLK + AXI_29_ACLK + AXI_30_ACLK + AXI_31_ACLK + + + choice_list_6330c9d2 + 10 + + + choice_list_7167c927 + Controller_and_Physical_Layer + Physical_Layer_Only + + + choice_list_7873c525 + div4 + + + choice_list_7a7dde49 + true + false + + + choice_list_811163c2 + User_Defined + Linear + Random + + + choice_list_8aad6ae4 + 1 + 2 + + + choice_list_99269739 + 32 + 33 + 36 + + + choice_list_b9d8ad80 + yes + no + + + choice_list_c2b73541 + TRUE + FALSEE + FALSE + + + choice_list_c3f33c2a + 100 + 101 + 102 + 103 + 104 + 105 + 106 + 107 + 108 + 109 + 110 + 111 + 112 + 113 + 114 + 115 + 116 + 117 + 118 + 119 + 120 + 121 + 122 + 123 + 124 + 125 + 126 + 127 + 128 + 129 + 130 + 131 + 132 + 133 + 134 + 135 + 136 + 137 + 138 + 139 + 140 + 141 + 142 + 143 + 144 + 145 + 146 + 147 + 148 + 149 + 150 + 151 + 152 + 153 + 154 + 155 + 156 + 157 + 158 + 159 + 160 + 161 + 162 + 163 + 164 + 165 + 166 + 167 + 168 + 169 + 170 + 171 + 172 + 173 + 174 + 175 + 176 + 177 + 178 + 179 + 180 + 181 + 182 + 183 + 184 + 185 + 186 + 187 + 188 + 189 + 190 + 191 + 192 + 193 + 194 + 195 + 196 + 197 + 198 + 199 + 200 + 201 + 202 + 203 + 204 + 205 + 206 + 207 + 208 + 209 + 210 + 211 + 212 + 213 + 214 + 215 + 216 + 217 + 218 + 219 + 220 + 221 + 222 + 223 + 224 + 225 + 226 + 227 + 228 + 229 + 230 + 231 + 232 + 233 + 234 + 235 + 236 + 237 + 238 + 239 + 240 + 241 + 242 + 243 + 244 + 245 + 246 + 247 + 248 + 249 + 250 + 251 + 252 + 253 + 254 + 255 + 256 + 257 + 258 + 259 + 260 + 261 + 262 + 263 + 264 + 265 + 266 + 267 + 268 + 269 + 270 + 271 + 272 + 273 + 274 + 275 + 276 + 277 + 278 + 279 + 280 + 281 + 282 + 283 + 284 + 285 + 286 + 287 + 288 + 289 + 290 + 291 + 292 + 293 + 294 + 295 + 296 + 297 + 298 + 300 + + + choice_list_e42ba42f + false + true + + + choice_list_e7c484ae + TRUE + FALSE + + + choice_list_f099505f + div4 + div8 + + + choice_list_ff2e97f4 + AXI_00_ACLK + AXI_01_ACLK + AXI_02_ACLK + AXI_03_ACLK + AXI_04_ACLK + AXI_05_ACLK + AXI_06_ACLK + AXI_07_ACLK + AXI_08_ACLK + AXI_09_ACLK + AXI_10_ACLK + AXI_11_ACLK + AXI_12_ACLK + AXI_13_ACLK + AXI_14_ACLK + AXI_15_ACLK + + + HBM Memory Interface IP + + + USER_CTRL_PHY_MODE + Physical_Layer_Only + + + USER_EN_PHY_ONLY + TRUE + + + USER_INIT_TIMEOUT_VAL + 10000000 + + + USER_AXI_ADDR_SIZE + 36 + + + USER_EN_VNC + FALSE + + + USER_EN_LOW_FREQ + FALSE + + + USER_DEBUG_EN + FALSE + + + USER_DIS_REF_CLK_BUFG + FALSE + + + USER_XSDB_EN + FALSE + + + USER_XSDB_INTF_EN + FALSE + + + USER_INIT_BYPASS + FALSE + + + USER_SINGLE_STACK_SELECTION + LEFT + + + + false + + + + + + USER_HBM_DENSITY + 8GB + + + USER_HBM_STACK + 2 + + + USER_MEMORY_DISPLAY + 8192 + + + + false + + + + + + USER_AUTO_POPULATE + yes + + + USER_SWITCH_ENABLE_00 + FALSE + + + + false + + + + + + USER_SWITCH_ENABLE_01 + FALSE + + + + false + + + + + + USER_HBM_REF_CLK_0 + 100 + + + USER_HBM_REF_CLK_PS_0 + 5000.00 + + + USER_HBM_REF_CLK_XDC_0 + 10.00 + + + USER_HBM_REF_CLK_PS_1 + 5000.00 + + + USER_HBM_REF_CLK_XDC_1 + 10.00 + + + USER_HBM_CLKOUTDIV_0 + 2 + + + USER_HBM_FBDIV_0 + 24 + + + USER_HBM_CP_0 + 6 + + + USER_HBM_RES_0 + 1 + + + USER_HBM_LFHF_0 + 3 + + + USER_HBM_LOCK_REF_DLY_0 + 27 + + + USER_HBM_LOCK_FB_DLY_0 + 27 + + + USER_HBM_LOCK_CNT_0 + 1000 + + + USER_HBM_HEX_CP_RES_0 + 0x00001600 + + + USER_HBM_HEX_CP_0 + 0x00000000 + + + USER_HBM_HEX_LOCK_FB_REF_DLY_0 + 0x00001b1b + + + USER_HBM_HEX_LOCK_CNT_0 + 0x00000000 + + + USER_HBM_HEX_FBDIV_CLKOUTDIV_0 + 0x00000602 + + + USER_HBM_CP_1 + 6 + + + USER_HBM_RES_1 + 1 + + + USER_HBM_LFHF_1 + 3 + + + USER_HBM_LOCK_REF_DLY_1 + 27 + + + USER_HBM_LOCK_FB_DLY_1 + 27 + + + USER_HBM_LOCK_CNT_1 + 1000 + + + USER_HBM_REF_CLK_1 + 100 + + + USER_HBM_CLKOUTDIV_1 + 2 + + + USER_HBM_FBDIV_1 + 24 + + + USER_HBM_HEX_CP_RES_1 + 0x00001600 + + + USER_HBM_HEX_CP_1 + 0x00000000 + + + USER_HBM_HEX_LOCK_FB_REF_DLY_1 + 0x00001b1b + + + USER_HBM_HEX_LOCK_CNT_1 + 0x00000000 + + + USER_HBM_HEX_FBDIV_CLKOUTDIV_1 + 0x00000602 + + + USER_HBM_TCK_0 + 600 + + + USER_HBM_TCK_0_PERIOD + 1.6666666666666667 + + + USER_HYNIX_MEM + false + + + USER_tRC_0 + 0x1D + + + USER_tRAS_0 + 0x14 + + + USER_tRCDRD_0 + 0x09 + + + USER_tRCDWR_0 + 0x06 + + + USER_tRRDL_0 + 0x03 + + + USER_tRRDS_0 + 0x03 + + + USER_tFAW_0 + 0x00A + + + USER_tRTP_0 + 0x05 + + + USER_tRTP_1 + 0x05 + + + USER_tRTP_2 + 0x05 + + + USER_tRTP_3 + 0x05 + + + USER_tRTP_4 + 0x05 + + + USER_tRTP_5 + 0x05 + + + USER_tRTP_6 + 0x05 + + + USER_tRTP_7 + 0x05 + + + USER_tRTP_8 + 0x05 + + + USER_tRTP_9 + 0x05 + + + USER_tRTP_10 + 0x05 + + + USER_tRTP_11 + 0x05 + + + USER_tRTP_12 + 0x05 + + + USER_tRTP_13 + 0x05 + + + USER_tRTP_14 + 0x05 + + + USER_tRTP_15 + 0x05 + + + USER_tRP_0 + 0x09 + + + USER_tWR_0 + 0x0A + + + USER_tWR_1 + 0x0A + + + USER_tWR_2 + 0x0F + + + USER_tWR_3 + 0x0F + + + USER_tWR_4 + 0x0F + + + USER_tWR_5 + 0x0F + + + USER_tWR_6 + 0x0F + + + USER_tWR_7 + 0x0F + + + USER_tWR_8 + 0x0F + + + USER_tWR_9 + 0x0F + + + USER_tWR_10 + 0x0F + + + USER_tWR_11 + 0x0F + + + USER_tWR_12 + 0x0F + + + USER_tWR_13 + 0x0F + + + USER_tWR_14 + 0x0F + + + USER_tWR_15 + 0x0F + + + USER_tWTRL_0 + 0x6 + + + USER_tWTRS_0 + 0x3 + + + USER_tXP_0 + 0x05 + + + USER_tRFC_0 + 0x09C + + + USER_tRFCSB_0 + 0x60 + + + USER_tRREFD_0 + 0x5 + + + USER_WL_0 + 0x07 + + + USER_RL_0 + 0x16 + + + USER_RL_1 + 0x16 + + + USER_RL_2 + 0x16 + + + USER_RL_3 + 0x16 + + + USER_RL_4 + 0x16 + + + USER_RL_5 + 0x16 + + + USER_RL_6 + 0x16 + + + USER_RL_7 + 0x16 + + + USER_RL_8 + 0x16 + + + USER_RL_9 + 0x16 + + + USER_RL_10 + 0x16 + + + USER_RL_11 + 0x16 + + + USER_RL_12 + 0x16 + + + USER_RL_13 + 0x16 + + + USER_RL_14 + 0x16 + + + USER_RL_15 + 0x16 + + + USER_tRC_1 + 0x1D + + + USER_tRAS_1 + 0x14 + + + USER_tRCDRD_1 + 0x09 + + + USER_tRCDWR_1 + 0x06 + + + USER_tRRDL_1 + 0x03 + + + USER_tRRDS_1 + 0x03 + + + USER_tFAW_1 + 0x00A + + + USER_tRP_1 + 0x09 + + + USER_tWTRL_1 + 0x6 + + + USER_tWTRS_1 + 0x3 + + + USER_tXP_1 + 0x05 + + + USER_tRFC_1 + 0x09C + + + USER_tRFCSB_1 + 0x60 + + + USER_tRREFD_1 + 0x5 + + + USER_WL_1 + 0x07 + + + USER_APB_PCLK_0 + 100 + + + USER_APB_PCLK_PERIOD_0 + 10.0 + + + USER_TEMP_POLL_PERIOD_0 + 1.0 + + + USER_TEMP_POLL_CNT_0 + 100000 + + + USER_APB_PCLK_1 + 100 + + + USER_APB_PCLK_PERIOD_1 + 10.0 + + + USER_TEMP_POLL_PERIOD_1 + 1.0 + + + USER_TEMP_POLL_CNT_1 + 100000 + + + USER_MC0_POP_EN + false + + + USER_MC1_POP_EN + false + + + USER_MC2_POP_EN + false + + + USER_MC3_POP_EN + false + + + USER_MC4_POP_EN + false + + + USER_MC5_POP_EN + false + + + USER_MC6_POP_EN + false + + + USER_MC7_POP_EN + false + + + USER_MC8_POP_EN + false + + + USER_MC9_POP_EN + false + + + USER_MC10_POP_EN + false + + + USER_MC11_POP_EN + false + + + USER_MC12_POP_EN + false + + + USER_MC13_POP_EN + false + + + USER_MC14_POP_EN + false + + + USER_MC15_POP_EN + false + + + USER_MC0_TRAFFIC_OPTION + User_Defined + + + USER_MC1_TRAFFIC_OPTION + User_Defined + + + USER_MC2_TRAFFIC_OPTION + User_Defined + + + USER_MC3_TRAFFIC_OPTION + User_Defined + + + USER_MC4_TRAFFIC_OPTION + User_Defined + + + USER_MC5_TRAFFIC_OPTION + User_Defined + + + USER_MC6_TRAFFIC_OPTION + User_Defined + + + USER_MC7_TRAFFIC_OPTION + User_Defined + + + USER_MC8_TRAFFIC_OPTION + User_Defined + + + USER_MC9_TRAFFIC_OPTION + User_Defined + + + USER_MC10_TRAFFIC_OPTION + User_Defined + + + USER_MC11_TRAFFIC_OPTION + User_Defined + + + USER_MC12_TRAFFIC_OPTION + User_Defined + + + USER_MC13_TRAFFIC_OPTION + User_Defined + + + USER_MC14_TRAFFIC_OPTION + User_Defined + + + USER_MC15_TRAFFIC_OPTION + User_Defined + + + USER_HBM_TCK_1 + 600 + + + USER_HBM_TCK_1_PERIOD + 1.6666666666666667 + + + USER_LINE_RATE_0 + div4 + + + USER_LINE_RATE_1 + div4 + + + USER_LINE_RATE_2 + div4 + + + USER_LINE_RATE_3 + div4 + + + USER_LINE_RATE_4 + div4 + + + USER_LINE_RATE_5 + div4 + + + USER_LINE_RATE_6 + div4 + + + USER_LINE_RATE_7 + div4 + + + USER_LINE_RATE_8 + div4 + + + USER_LINE_RATE_9 + div4 + + + USER_LINE_RATE_10 + div4 + + + USER_LINE_RATE_11 + div4 + + + USER_LINE_RATE_12 + div4 + + + USER_LINE_RATE_13 + div4 + + + USER_LINE_RATE_14 + div4 + + + USER_LINE_RATE_15 + div4 + + + USER_HBM_REF_OUT_CLK_0 + 1200 + + + USER_HBM_REF_OUT_CLK_1 + 1200 + + + USER_ENABLE_VT_TRACKING_0 + false + + + USER_ENABLE_VT_TRACKING_1 + false + + + USER_ENABLE_VT_TRACKING_2 + false + + + USER_ENABLE_VT_TRACKING_3 + false + + + USER_ENABLE_VT_TRACKING_4 + false + + + USER_ENABLE_VT_TRACKING_5 + false + + + USER_ENABLE_VT_TRACKING_6 + false + + + USER_ENABLE_VT_TRACKING_7 + false + + + USER_ENABLE_VT_TRACKING_8 + false + + + USER_ENABLE_VT_TRACKING_9 + false + + + USER_ENABLE_VT_TRACKING_10 + false + + + USER_ENABLE_VT_TRACKING_11 + false + + + USER_ENABLE_VT_TRACKING_12 + false + + + USER_ENABLE_VT_TRACKING_13 + false + + + USER_ENABLE_VT_TRACKING_14 + false + + + USER_ENABLE_VT_TRACKING_15 + false + + + USER_ENABLE_DQS_TRAINING_0 + false + + + USER_ENABLE_DQS_TRAINING_1 + false + + + USER_ENABLE_DQS_TRAINING_2 + false + + + USER_ENABLE_DQS_TRAINING_3 + false + + + USER_ENABLE_DQS_TRAINING_4 + false + + + USER_ENABLE_DQS_TRAINING_5 + false + + + USER_ENABLE_DQS_TRAINING_6 + false + + + USER_ENABLE_DQS_TRAINING_7 + false + + + USER_ENABLE_DQS_TRAINING_8 + false + + + USER_ENABLE_DQS_TRAINING_9 + false + + + USER_ENABLE_DQS_TRAINING_10 + false + + + USER_ENABLE_DQS_TRAINING_11 + false + + + USER_ENABLE_DQS_TRAINING_12 + false + + + USER_ENABLE_DQS_TRAINING_13 + false + + + USER_ENABLE_DQS_TRAINING_14 + false + + + USER_ENABLE_DQS_TRAINING_15 + false + + + USER_MC0_WRITE_DBI_EN + true + + + USER_MC1_WRITE_DBI_EN + true + + + USER_MC2_WRITE_DBI_EN + true + + + USER_MC3_WRITE_DBI_EN + true + + + USER_MC4_WRITE_DBI_EN + true + + + USER_MC5_WRITE_DBI_EN + true + + + USER_MC6_WRITE_DBI_EN + true + + + USER_MC7_WRITE_DBI_EN + true + + + USER_MC8_WRITE_DBI_EN + true + + + USER_MC9_WRITE_DBI_EN + true + + + USER_MC10_WRITE_DBI_EN + true + + + USER_MC11_WRITE_DBI_EN + true + + + USER_MC12_WRITE_DBI_EN + true + + + USER_MC13_WRITE_DBI_EN + true + + + USER_MC14_WRITE_DBI_EN + true + + + USER_MC15_WRITE_DBI_EN + true + + + USER_MC0_READ_DBI_EN + true + + + USER_MC1_READ_DBI_EN + true + + + USER_MC2_READ_DBI_EN + true + + + USER_MC3_READ_DBI_EN + true + + + USER_MC4_READ_DBI_EN + true + + + USER_MC5_READ_DBI_EN + true + + + USER_MC6_READ_DBI_EN + true + + + USER_MC7_READ_DBI_EN + true + + + USER_MC8_READ_DBI_EN + true + + + USER_MC9_READ_DBI_EN + true + + + USER_MC10_READ_DBI_EN + true + + + USER_MC11_READ_DBI_EN + true + + + USER_MC12_READ_DBI_EN + true + + + USER_MC13_READ_DBI_EN + true + + + USER_MC14_READ_DBI_EN + true + + + USER_MC15_READ_DBI_EN + true + + + USER_CLK_SEL_LIST0 + AXI_07_ACLK + + + + false + + + + + + USER_CLK_SEL_LIST1 + AXI_23_ACLK + + + + false + + + + + + USER_CLK_SEL_00 + FALSE + + + USER_CLK_SEL_01 + FALSE + + + USER_CLK_SEL_02 + FALSE + + + USER_CLK_SEL_03 + FALSE + + + USER_CLK_SEL_04 + FALSE + + + USER_CLK_SEL_05 + FALSE + + + USER_CLK_SEL_06 + FALSE + + + USER_CLK_SEL_07 + FALSE + + + USER_CLK_SEL_08 + FALSE + + + USER_CLK_SEL_09 + FALSE + + + USER_CLK_SEL_10 + FALSE + + + USER_CLK_SEL_11 + FALSE + + + USER_CLK_SEL_12 + FALSE + + + USER_CLK_SEL_13 + FALSE + + + USER_CLK_SEL_14 + FALSE + + + USER_CLK_SEL_15 + FALSE + + + USER_CLK_SEL_16 + FALSE + + + USER_CLK_SEL_17 + FALSE + + + USER_CLK_SEL_18 + FALSE + + + USER_CLK_SEL_19 + FALSE + + + USER_CLK_SEL_20 + FALSE + + + USER_CLK_SEL_21 + FALSE + + + USER_CLK_SEL_22 + FALSE + + + USER_CLK_SEL_23 + FALSE + + + USER_CLK_SEL_24 + FALSE + + + USER_CLK_SEL_25 + FALSE + + + USER_CLK_SEL_26 + FALSE + + + USER_CLK_SEL_27 + FALSE + + + USER_CLK_SEL_28 + FALSE + + + USER_CLK_SEL_29 + FALSE + + + USER_CLK_SEL_30 + FALSE + + + USER_CLK_SEL_31 + FALSE + + + USER_MC_ENABLE_00 + FALSE + + + + false + + + + + + USER_MC_ENABLE_01 + FALSE + + + + false + + + + + + USER_MC_ENABLE_02 + FALSE + + + + false + + + + + + USER_MC_ENABLE_03 + FALSE + + + + false + + + + + + USER_MC_ENABLE_04 + FALSE + + + + false + + + + + + USER_MC_ENABLE_05 + FALSE + + + + false + + + + + + USER_MC_ENABLE_06 + FALSE + + + + false + + + + + + USER_MC_ENABLE_07 + FALSE + + + + false + + + + + + USER_MC_ENABLE_08 + FALSE + + + + false + + + + + + USER_MC_ENABLE_09 + FALSE + + + + false + + + + + + USER_MC_ENABLE_10 + FALSE + + + + false + + + + + + USER_MC_ENABLE_11 + FALSE + + + + false + + + + + + USER_MC_ENABLE_12 + FALSE + + + + false + + + + + + USER_MC_ENABLE_13 + FALSE + + + + false + + + + + + USER_MC_ENABLE_14 + FALSE + + + + false + + + + + + USER_MC_ENABLE_15 + FALSE + + + + false + + + + + + USER_MC_ENABLE_APB_00 + FALSE + + + USER_MC_ENABLE_APB_01 + FALSE + + + USER_MC0_MANUAL_ADDR_MAP_SEL + false + + + USER_MC0_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC1_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC2_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC3_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC4_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC5_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC6_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC7_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC8_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC9_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC10_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC11_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC12_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC13_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC14_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC15_PRE_DEF_ADDR_MAP_SEL + ROW_BANK_COLUMN + + + + false + + + + + + USER_MC0_WRITE_READ_REGROUPING + false + + + USER_MC1_WRITE_READ_REGROUPING + false + + + USER_MC2_WRITE_READ_REGROUPING + false + + + USER_MC3_WRITE_READ_REGROUPING + false + + + USER_MC4_WRITE_READ_REGROUPING + false + + + USER_MC5_WRITE_READ_REGROUPING + false + + + USER_MC6_WRITE_READ_REGROUPING + false + + + USER_MC7_WRITE_READ_REGROUPING + false + + + USER_MC8_WRITE_READ_REGROUPING + false + + + USER_MC9_WRITE_READ_REGROUPING + false + + + USER_MC10_WRITE_READ_REGROUPING + false + + + USER_MC11_WRITE_READ_REGROUPING + false + + + USER_MC12_WRITE_READ_REGROUPING + false + + + USER_MC13_WRITE_READ_REGROUPING + false + + + USER_MC14_WRITE_READ_REGROUPING + false + + + USER_MC15_WRITE_READ_REGROUPING + false + + + USER_MC0_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC1_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC2_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC3_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC4_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC5_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC6_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC7_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC8_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC9_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC10_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC11_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC12_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC13_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC14_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC15_LOOKAHEAD_SBRF + false + + + + false + + + + + + USER_MC0_CLOSE_PAGE_REORDER + false + + + USER_MC1_CLOSE_PAGE_REORDER + false + + + USER_MC2_CLOSE_PAGE_REORDER + false + + + USER_MC3_CLOSE_PAGE_REORDER + false + + + USER_MC4_CLOSE_PAGE_REORDER + false + + + USER_MC5_CLOSE_PAGE_REORDER + false + + + USER_MC6_CLOSE_PAGE_REORDER + false + + + USER_MC7_CLOSE_PAGE_REORDER + false + + + USER_MC8_CLOSE_PAGE_REORDER + false + + + USER_MC9_CLOSE_PAGE_REORDER + false + + + USER_MC10_CLOSE_PAGE_REORDER + false + + + USER_MC11_CLOSE_PAGE_REORDER + false + + + USER_MC12_CLOSE_PAGE_REORDER + false + + + USER_MC13_CLOSE_PAGE_REORDER + false + + + USER_MC14_CLOSE_PAGE_REORDER + false + + + USER_MC15_CLOSE_PAGE_REORDER + false + + + USER_MC0_REF_TEMP_COMP + false + + + USER_MC1_REF_TEMP_COMP + false + + + USER_MC2_REF_TEMP_COMP + false + + + USER_MC3_REF_TEMP_COMP + false + + + USER_MC4_REF_TEMP_COMP + false + + + USER_MC5_REF_TEMP_COMP + false + + + USER_MC6_REF_TEMP_COMP + false + + + USER_MC7_REF_TEMP_COMP + false + + + USER_MC8_REF_TEMP_COMP + false + + + USER_MC9_REF_TEMP_COMP + false + + + USER_MC10_REF_TEMP_COMP + false + + + USER_MC11_REF_TEMP_COMP + false + + + USER_MC12_REF_TEMP_COMP + false + + + USER_MC13_REF_TEMP_COMP + false + + + USER_MC14_REF_TEMP_COMP + false + + + USER_MC15_REF_TEMP_COMP + false + + + USER_MC0_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC1_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC2_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC3_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC4_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC5_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC6_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC7_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC8_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC9_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC10_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC11_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC12_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC13_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC14_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC15_IDLE_ENTR_SELF_REFRESH_MODE + 0x00000000 + + + USER_MC0_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC1_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC2_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC3_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC4_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC5_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC6_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC7_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC8_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC9_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC10_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC11_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC12_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC13_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC14_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC15_IDLE_ENTR_PWR_DOWN_MODE + 0x00000000 + + + USER_MC0_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC1_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC2_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC3_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC4_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC5_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC6_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC7_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC8_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC9_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC10_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC11_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC12_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC13_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC14_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC15_TEMP_CTRL_SELF_REF_INTVL + false + + + USER_MC0_ECC_BYPASS + false + + + USER_MC1_ECC_BYPASS + false + + + USER_MC2_ECC_BYPASS + false + + + USER_MC3_ECC_BYPASS + false + + + USER_MC4_ECC_BYPASS + false + + + USER_MC5_ECC_BYPASS + false + + + USER_MC6_ECC_BYPASS + false + + + USER_MC7_ECC_BYPASS + false + + + USER_MC8_ECC_BYPASS + false + + + USER_MC9_ECC_BYPASS + false + + + USER_MC10_ECC_BYPASS + false + + + USER_MC11_ECC_BYPASS + false + + + USER_MC12_ECC_BYPASS + false + + + USER_MC13_ECC_BYPASS + false + + + USER_MC14_ECC_BYPASS + false + + + USER_MC15_ECC_BYPASS + false + + + USER_MC0_ENABLE_ECC_CORRECTION + false + + + USER_MC1_ENABLE_ECC_CORRECTION + false + + + USER_MC2_ENABLE_ECC_CORRECTION + false + + + USER_MC3_ENABLE_ECC_CORRECTION + false + + + USER_MC4_ENABLE_ECC_CORRECTION + false + + + USER_MC5_ENABLE_ECC_CORRECTION + false + + + USER_MC6_ENABLE_ECC_CORRECTION + false + + + USER_MC7_ENABLE_ECC_CORRECTION + false + + + USER_MC8_ENABLE_ECC_CORRECTION + false + + + USER_MC9_ENABLE_ECC_CORRECTION + false + + + USER_MC10_ENABLE_ECC_CORRECTION + false + + + USER_MC11_ENABLE_ECC_CORRECTION + false + + + USER_MC12_ENABLE_ECC_CORRECTION + false + + + USER_MC13_ENABLE_ECC_CORRECTION + false + + + USER_MC14_ENABLE_ECC_CORRECTION + false + + + USER_MC15_ENABLE_ECC_CORRECTION + false + + + USER_MC0_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC1_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC2_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC3_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC4_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC5_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC6_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC7_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC8_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC9_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC10_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC11_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC12_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC13_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC14_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC15_ECC_SCRUB_BITS + 0 + + + + false + + + + + + USER_MC0_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC1_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC2_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC3_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC4_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC5_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC6_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC7_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC8_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC9_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC10_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC11_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC12_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC13_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC14_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC15_ENABLE_ECC_SCRUBBING + false + + + + false + + + + + + USER_MC0_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC1_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC2_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC3_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC4_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC5_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC6_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC7_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC8_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC9_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC10_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC11_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC12_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC13_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC14_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC15_ECC_SCRUB_PERIOD + 0x0002 + + + + false + + + + + + USER_MC0_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC1_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC2_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC3_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC4_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC5_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC6_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC7_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC8_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC9_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC10_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC11_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC12_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC13_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC14_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC15_INITILIZE_MEM_USING_ECC_SCRUB + false + + + + false + + + + + + USER_MC0_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC1_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC2_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC3_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC4_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC5_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC6_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC7_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC8_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC9_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC10_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC11_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC12_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC13_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC14_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC15_INITILIZE_MEM_USING_RMW_ECC_SCRUB + false + + + + false + + + + + + USER_MC0_MANUAL_REFRESH_SEL + false + + + USER_MC0_MANUAL_ADV_OPTIONS + false + + + USER_MC0_COL_ADDR_LOW + 0x4 + + + USER_MC0_COL_ADDR_HIGH + 0xa + + + USER_MC0_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC0_LADDR_BA5_MAP + 0x00 + + + USER_MC0_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC0_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC0_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC0_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC0_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC0_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC0_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC0_BG_INTERLEAVE_EN + true + + + USER_MC0_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC0_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC0_REF_CMD_PERIOD + 0x0924 + + + USER_MC0_EN_SBREF + false + + + USER_MC0_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC0_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_STACK_8HI + false + + + USER_MC0_LOOKAHEAD_PCH + true + + + USER_MC0_LOOKAHEAD_ACT + true + + + USER_MC0_REORDER_EN + true + + + USER_MC0_REORDER_RW_ONLY + false + + + USER_MC0_REORDER_QUEUE_EN + true + + + USER_MC0_MAINTAIN_COHERENCY + true + + + USER_MC0_Q_AGE_LIMIT + 0x7f + + + USER_MC0_EN_DATA_MASK + true + + + USER_MC0_INIT_PERR_RETRY_EN + false + + + USER_MC0_USER_PARITY_EN + false + + + USER_MC0_DQ_PARITY_EN + false + + + USER_MC0_RD_DQ_PARITY_EN + false + + + USER_MC0_WR_DQ_PARITY_EN + false + + + USER_MC0_CA_PARITY_EN + false + + + USER_MC0_HBM_CB_EN + false + + + USER_MC0_DM_EN + true + + + + false + + + + + + USER_MC0_RMW_EN + false + + + + false + + + + + + USER_MC1_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC1_MANUAL_REFRESH_SEL + false + + + USER_MC1_MANUAL_ADV_OPTIONS + false + + + USER_MC1_COL_ADDR_LOW + 0x4 + + + USER_MC1_COL_ADDR_HIGH + 0x4 + + + USER_MC1_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC1_LADDR_BA5_MAP + 0x05 + + + USER_MC1_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC1_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC1_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC1_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC1_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC1_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC1_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC1_BG_INTERLEAVE_EN + true + + + USER_MC1_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC1_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC1_REF_CMD_PERIOD + 0x0924 + + + USER_MC1_EN_SBREF + false + + + USER_MC1_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC1_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC1_LOOKAHEAD_PCH + true + + + USER_MC1_LOOKAHEAD_ACT + true + + + USER_MC1_REORDER_EN + true + + + USER_MC1_REORDER_RW_ONLY + false + + + USER_MC1_REORDER_QUEUE_EN + true + + + USER_MC1_MAINTAIN_COHERENCY + true + + + USER_MC1_Q_AGE_LIMIT + 0x7f + + + USER_MC1_EN_DATA_MASK + true + + + USER_MC1_INIT_PERR_RETRY_EN + false + + + USER_MC1_USER_PARITY_EN + false + + + USER_MC1_DQ_PARITY_EN + false + + + USER_MC1_RD_DQ_PARITY_EN + false + + + USER_MC1_WR_DQ_PARITY_EN + false + + + USER_MC1_CA_PARITY_EN + false + + + USER_MC1_HBM_CB_EN + false + + + USER_MC1_DM_EN + true + + + + false + + + + + + USER_MC1_RMW_EN + false + + + + false + + + + + + USER_MC2_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC2_MANUAL_REFRESH_SEL + false + + + USER_MC2_MANUAL_ADV_OPTIONS + false + + + USER_MC2_COL_ADDR_LOW + 0x4 + + + USER_MC2_COL_ADDR_HIGH + 0x4 + + + USER_MC2_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC2_LADDR_BA5_MAP + 0x05 + + + USER_MC2_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC2_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC2_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC2_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC2_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC2_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC2_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC2_BG_INTERLEAVE_EN + true + + + USER_MC2_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC2_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC2_REF_CMD_PERIOD + 0x0924 + + + USER_MC2_EN_SBREF + false + + + USER_MC2_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC2_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC2_LOOKAHEAD_PCH + true + + + USER_MC2_LOOKAHEAD_ACT + true + + + USER_MC2_REORDER_EN + true + + + USER_MC2_REORDER_RW_ONLY + false + + + USER_MC2_REORDER_QUEUE_EN + true + + + USER_MC2_MAINTAIN_COHERENCY + true + + + USER_MC2_Q_AGE_LIMIT + 0x7f + + + USER_MC2_EN_DATA_MASK + true + + + USER_MC2_INIT_PERR_RETRY_EN + false + + + USER_MC2_USER_PARITY_EN + false + + + USER_MC2_DQ_PARITY_EN + false + + + USER_MC2_RD_DQ_PARITY_EN + false + + + USER_MC2_WR_DQ_PARITY_EN + false + + + USER_MC2_CA_PARITY_EN + false + + + USER_MC2_HBM_CB_EN + false + + + USER_MC2_DM_EN + true + + + + false + + + + + + USER_MC2_RMW_EN + false + + + + false + + + + + + USER_MC3_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC3_MANUAL_REFRESH_SEL + false + + + USER_MC3_MANUAL_ADV_OPTIONS + false + + + USER_MC3_COL_ADDR_LOW + 0x4 + + + USER_MC3_COL_ADDR_HIGH + 0x4 + + + USER_MC3_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC3_LADDR_BA5_MAP + 0x05 + + + USER_MC3_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC3_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC3_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC3_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC3_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC3_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC3_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC3_BG_INTERLEAVE_EN + true + + + USER_MC3_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC3_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC3_REF_CMD_PERIOD + 0x0924 + + + USER_MC3_EN_SBREF + false + + + USER_MC3_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC3_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC3_LOOKAHEAD_PCH + true + + + USER_MC3_LOOKAHEAD_ACT + true + + + USER_MC3_REORDER_EN + true + + + USER_MC3_REORDER_RW_ONLY + false + + + USER_MC3_REORDER_QUEUE_EN + true + + + USER_MC3_MAINTAIN_COHERENCY + true + + + USER_MC3_Q_AGE_LIMIT + 0x7f + + + USER_MC3_EN_DATA_MASK + true + + + USER_MC3_INIT_PERR_RETRY_EN + false + + + USER_MC3_USER_PARITY_EN + false + + + USER_MC3_DQ_PARITY_EN + false + + + USER_MC3_RD_DQ_PARITY_EN + false + + + USER_MC3_WR_DQ_PARITY_EN + false + + + USER_MC3_CA_PARITY_EN + false + + + USER_MC3_HBM_CB_EN + false + + + USER_MC3_DM_EN + true + + + + false + + + + + + USER_MC3_RMW_EN + false + + + + false + + + + + + USER_MC4_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC4_MANUAL_REFRESH_SEL + false + + + USER_MC4_MANUAL_ADV_OPTIONS + false + + + USER_MC4_COL_ADDR_LOW + 0x4 + + + USER_MC4_COL_ADDR_HIGH + 0x4 + + + USER_MC4_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC4_LADDR_BA5_MAP + 0x05 + + + USER_MC4_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC4_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC4_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC4_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC4_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC4_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC4_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC4_BG_INTERLEAVE_EN + true + + + USER_MC4_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC4_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC4_REF_CMD_PERIOD + 0x0924 + + + USER_MC4_EN_SBREF + false + + + USER_MC4_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC4_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC4_LOOKAHEAD_PCH + true + + + USER_MC4_LOOKAHEAD_ACT + true + + + USER_MC4_REORDER_EN + true + + + USER_MC4_REORDER_RW_ONLY + false + + + USER_MC4_REORDER_QUEUE_EN + true + + + USER_MC4_MAINTAIN_COHERENCY + true + + + USER_MC4_Q_AGE_LIMIT + 0x7f + + + USER_MC4_EN_DATA_MASK + true + + + USER_MC4_INIT_PERR_RETRY_EN + false + + + USER_MC4_USER_PARITY_EN + false + + + USER_MC4_DQ_PARITY_EN + false + + + USER_MC4_RD_DQ_PARITY_EN + false + + + USER_MC4_WR_DQ_PARITY_EN + false + + + USER_MC4_CA_PARITY_EN + false + + + USER_MC4_HBM_CB_EN + false + + + USER_MC4_DM_EN + true + + + + false + + + + + + USER_MC4_RMW_EN + false + + + + false + + + + + + USER_MC5_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC5_MANUAL_REFRESH_SEL + false + + + USER_MC5_MANUAL_ADV_OPTIONS + false + + + USER_MC5_COL_ADDR_LOW + 0x4 + + + USER_MC5_COL_ADDR_HIGH + 0x4 + + + USER_MC5_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC5_LADDR_BA5_MAP + 0x05 + + + USER_MC5_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC5_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC5_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC5_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC5_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC5_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC5_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC5_BG_INTERLEAVE_EN + true + + + USER_MC5_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC5_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC5_REF_CMD_PERIOD + 0x0924 + + + USER_MC5_EN_SBREF + false + + + USER_MC5_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC5_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC5_LOOKAHEAD_PCH + true + + + USER_MC5_LOOKAHEAD_ACT + true + + + USER_MC5_REORDER_EN + true + + + USER_MC5_REORDER_RW_ONLY + false + + + USER_MC5_REORDER_QUEUE_EN + true + + + USER_MC5_MAINTAIN_COHERENCY + true + + + USER_MC5_Q_AGE_LIMIT + 0x7f + + + USER_MC5_EN_DATA_MASK + true + + + USER_MC5_INIT_PERR_RETRY_EN + false + + + USER_MC5_USER_PARITY_EN + false + + + USER_MC5_DQ_PARITY_EN + false + + + USER_MC5_RD_DQ_PARITY_EN + false + + + USER_MC5_WR_DQ_PARITY_EN + false + + + USER_MC5_CA_PARITY_EN + false + + + USER_MC5_HBM_CB_EN + false + + + USER_MC5_DM_EN + true + + + + false + + + + + + USER_MC5_RMW_EN + false + + + + false + + + + + + USER_MC6_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC6_MANUAL_REFRESH_SEL + false + + + USER_MC6_MANUAL_ADV_OPTIONS + false + + + USER_MC6_COL_ADDR_LOW + 0x4 + + + USER_MC6_COL_ADDR_HIGH + 0x4 + + + USER_MC6_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC6_LADDR_BA5_MAP + 0x05 + + + USER_MC6_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC6_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC6_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC6_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC6_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC6_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC6_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC6_BG_INTERLEAVE_EN + true + + + USER_MC6_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC6_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC6_REF_CMD_PERIOD + 0x0924 + + + USER_MC6_EN_SBREF + false + + + USER_MC6_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC6_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC6_LOOKAHEAD_PCH + true + + + USER_MC6_LOOKAHEAD_ACT + true + + + USER_MC6_REORDER_EN + true + + + USER_MC6_REORDER_RW_ONLY + false + + + USER_MC6_REORDER_QUEUE_EN + true + + + USER_MC6_MAINTAIN_COHERENCY + true + + + USER_MC6_Q_AGE_LIMIT + 0x7f + + + USER_MC6_EN_DATA_MASK + true + + + USER_MC6_INIT_PERR_RETRY_EN + false + + + USER_MC6_USER_PARITY_EN + false + + + USER_MC6_DQ_PARITY_EN + false + + + USER_MC6_RD_DQ_PARITY_EN + false + + + USER_MC6_WR_DQ_PARITY_EN + false + + + USER_MC6_CA_PARITY_EN + false + + + USER_MC6_HBM_CB_EN + false + + + USER_MC6_DM_EN + true + + + + false + + + + + + USER_MC6_RMW_EN + false + + + + false + + + + + + USER_MC7_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC7_MANUAL_REFRESH_SEL + false + + + USER_MC7_MANUAL_ADV_OPTIONS + false + + + USER_MC7_COL_ADDR_LOW + 0x4 + + + USER_MC7_COL_ADDR_HIGH + 0x4 + + + USER_MC7_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC7_LADDR_BA5_MAP + 0x05 + + + USER_MC7_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC7_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC7_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC7_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC7_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC7_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC7_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC7_BG_INTERLEAVE_EN + true + + + USER_MC7_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC7_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC7_REF_CMD_PERIOD + 0x0924 + + + USER_MC7_EN_SBREF + false + + + USER_MC7_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC7_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC7_LOOKAHEAD_PCH + true + + + USER_MC7_LOOKAHEAD_ACT + true + + + USER_MC7_REORDER_EN + true + + + USER_MC7_REORDER_RW_ONLY + false + + + USER_MC7_REORDER_QUEUE_EN + true + + + USER_MC7_MAINTAIN_COHERENCY + true + + + USER_MC7_Q_AGE_LIMIT + 0x7f + + + USER_MC7_EN_DATA_MASK + true + + + USER_MC7_INIT_PERR_RETRY_EN + false + + + USER_MC7_USER_PARITY_EN + false + + + USER_MC7_DQ_PARITY_EN + false + + + USER_MC7_RD_DQ_PARITY_EN + false + + + USER_MC7_WR_DQ_PARITY_EN + false + + + USER_MC7_CA_PARITY_EN + false + + + USER_MC7_HBM_CB_EN + false + + + USER_MC7_DM_EN + true + + + + false + + + + + + USER_MC7_RMW_EN + false + + + + false + + + + + + USER_MC8_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC8_MANUAL_REFRESH_SEL + false + + + USER_MC8_MANUAL_ADV_OPTIONS + false + + + USER_MC8_COL_ADDR_LOW + 0x4 + + + USER_MC8_COL_ADDR_HIGH + 0x4 + + + USER_MC8_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC8_LADDR_BA5_MAP + 0x05 + + + USER_MC8_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC8_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC8_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC8_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC8_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC8_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC8_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC8_BG_INTERLEAVE_EN + true + + + USER_MC8_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC8_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC8_REF_CMD_PERIOD + 0x0924 + + + USER_MC8_EN_SBREF + false + + + USER_MC8_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC8_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC8_LOOKAHEAD_PCH + true + + + USER_MC8_LOOKAHEAD_ACT + true + + + USER_MC8_REORDER_EN + true + + + USER_MC8_REORDER_RW_ONLY + false + + + USER_MC8_REORDER_QUEUE_EN + true + + + USER_MC8_MAINTAIN_COHERENCY + true + + + USER_MC8_Q_AGE_LIMIT + 0x7f + + + USER_MC8_EN_DATA_MASK + true + + + USER_MC8_INIT_PERR_RETRY_EN + false + + + USER_MC8_USER_PARITY_EN + false + + + USER_MC8_DQ_PARITY_EN + false + + + USER_MC8_RD_DQ_PARITY_EN + false + + + USER_MC8_WR_DQ_PARITY_EN + false + + + USER_MC8_CA_PARITY_EN + false + + + USER_MC8_HBM_CB_EN + false + + + USER_MC8_DM_EN + true + + + + false + + + + + + USER_MC8_RMW_EN + false + + + + false + + + + + + USER_MC9_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC9_MANUAL_REFRESH_SEL + false + + + USER_MC9_MANUAL_ADV_OPTIONS + false + + + USER_MC9_COL_ADDR_LOW + 0x4 + + + USER_MC9_COL_ADDR_HIGH + 0x4 + + + USER_MC9_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC9_LADDR_BA5_MAP + 0x05 + + + USER_MC9_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC9_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC9_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC9_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC9_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC9_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC9_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC9_BG_INTERLEAVE_EN + true + + + USER_MC9_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC9_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC9_REF_CMD_PERIOD + 0x0924 + + + USER_MC9_EN_SBREF + false + + + USER_MC9_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC9_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC9_LOOKAHEAD_PCH + true + + + USER_MC9_LOOKAHEAD_ACT + true + + + USER_MC9_REORDER_EN + true + + + USER_MC9_REORDER_RW_ONLY + false + + + USER_MC9_REORDER_QUEUE_EN + true + + + USER_MC9_MAINTAIN_COHERENCY + true + + + USER_MC9_Q_AGE_LIMIT + 0x7f + + + USER_MC9_EN_DATA_MASK + true + + + USER_MC9_INIT_PERR_RETRY_EN + false + + + USER_MC9_USER_PARITY_EN + false + + + USER_MC9_DQ_PARITY_EN + false + + + USER_MC9_RD_DQ_PARITY_EN + false + + + USER_MC9_WR_DQ_PARITY_EN + false + + + USER_MC9_CA_PARITY_EN + false + + + USER_MC9_HBM_CB_EN + false + + + USER_MC9_DM_EN + true + + + + false + + + + + + USER_MC9_RMW_EN + false + + + + false + + + + + + USER_MC10_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC10_MANUAL_REFRESH_SEL + false + + + USER_MC10_MANUAL_ADV_OPTIONS + false + + + USER_MC10_COL_ADDR_LOW + 0x4 + + + USER_MC10_COL_ADDR_HIGH + 0x4 + + + USER_MC10_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC10_LADDR_BA5_MAP + 0x05 + + + USER_MC10_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC10_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC10_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC10_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC10_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC10_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC10_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC10_BG_INTERLEAVE_EN + true + + + USER_MC10_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC10_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC10_REF_CMD_PERIOD + 0x0924 + + + USER_MC10_EN_SBREF + false + + + USER_MC10_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC10_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC10_LOOKAHEAD_PCH + true + + + USER_MC10_LOOKAHEAD_ACT + true + + + USER_MC10_REORDER_EN + true + + + USER_MC10_REORDER_RW_ONLY + false + + + USER_MC10_REORDER_QUEUE_EN + true + + + USER_MC10_MAINTAIN_COHERENCY + true + + + USER_MC10_Q_AGE_LIMIT + 0x7f + + + USER_MC10_EN_DATA_MASK + true + + + USER_MC10_INIT_PERR_RETRY_EN + false + + + USER_MC10_USER_PARITY_EN + false + + + USER_MC10_DQ_PARITY_EN + false + + + USER_MC10_RD_DQ_PARITY_EN + false + + + USER_MC10_WR_DQ_PARITY_EN + false + + + USER_MC10_CA_PARITY_EN + false + + + USER_MC10_HBM_CB_EN + false + + + USER_MC10_DM_EN + true + + + + false + + + + + + USER_MC10_RMW_EN + false + + + + false + + + + + + USER_MC11_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC11_MANUAL_REFRESH_SEL + false + + + USER_MC11_MANUAL_ADV_OPTIONS + false + + + USER_MC11_COL_ADDR_LOW + 0x4 + + + USER_MC11_COL_ADDR_HIGH + 0x4 + + + USER_MC11_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC11_LADDR_BA5_MAP + 0x05 + + + USER_MC11_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC11_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC11_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC11_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC11_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC11_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC11_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC11_BG_INTERLEAVE_EN + true + + + USER_MC11_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC11_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC11_REF_CMD_PERIOD + 0x0924 + + + USER_MC11_EN_SBREF + false + + + USER_MC11_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC11_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC11_LOOKAHEAD_PCH + true + + + USER_MC11_LOOKAHEAD_ACT + true + + + USER_MC11_REORDER_EN + true + + + USER_MC11_REORDER_RW_ONLY + false + + + USER_MC11_REORDER_QUEUE_EN + true + + + USER_MC11_MAINTAIN_COHERENCY + true + + + USER_MC11_Q_AGE_LIMIT + 0x7f + + + USER_MC11_EN_DATA_MASK + true + + + USER_MC11_INIT_PERR_RETRY_EN + false + + + USER_MC11_USER_PARITY_EN + false + + + USER_MC11_DQ_PARITY_EN + false + + + USER_MC11_RD_DQ_PARITY_EN + false + + + USER_MC11_WR_DQ_PARITY_EN + false + + + USER_MC11_CA_PARITY_EN + false + + + USER_MC11_HBM_CB_EN + false + + + USER_MC11_DM_EN + true + + + + false + + + + + + USER_MC11_RMW_EN + false + + + + false + + + + + + USER_MC12_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC12_MANUAL_REFRESH_SEL + false + + + USER_MC12_MANUAL_ADV_OPTIONS + false + + + USER_MC12_COL_ADDR_LOW + 0x4 + + + USER_MC12_COL_ADDR_HIGH + 0x4 + + + USER_MC12_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC12_LADDR_BA5_MAP + 0x05 + + + USER_MC12_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC12_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC12_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC12_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC12_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC12_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC12_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC12_BG_INTERLEAVE_EN + true + + + USER_MC12_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC12_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC12_REF_CMD_PERIOD + 0x0924 + + + USER_MC12_EN_SBREF + false + + + USER_MC12_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC12_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC12_LOOKAHEAD_PCH + true + + + USER_MC12_LOOKAHEAD_ACT + true + + + USER_MC12_REORDER_EN + true + + + USER_MC12_REORDER_RW_ONLY + false + + + USER_MC12_REORDER_QUEUE_EN + true + + + USER_MC12_MAINTAIN_COHERENCY + true + + + USER_MC12_Q_AGE_LIMIT + 0x7f + + + USER_MC12_EN_DATA_MASK + true + + + USER_MC12_INIT_PERR_RETRY_EN + false + + + USER_MC12_USER_PARITY_EN + false + + + USER_MC12_DQ_PARITY_EN + false + + + USER_MC12_RD_DQ_PARITY_EN + false + + + USER_MC12_WR_DQ_PARITY_EN + false + + + USER_MC12_CA_PARITY_EN + false + + + USER_MC12_HBM_CB_EN + false + + + USER_MC12_DM_EN + true + + + + false + + + + + + USER_MC12_RMW_EN + false + + + + false + + + + + + USER_MC13_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC13_MANUAL_REFRESH_SEL + false + + + USER_MC13_MANUAL_ADV_OPTIONS + false + + + USER_MC13_COL_ADDR_LOW + 0x4 + + + USER_MC13_COL_ADDR_HIGH + 0x4 + + + USER_MC13_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC13_LADDR_BA5_MAP + 0x05 + + + USER_MC13_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC13_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC13_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC13_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC13_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC13_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC13_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC13_BG_INTERLEAVE_EN + true + + + USER_MC13_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC13_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC13_REF_CMD_PERIOD + 0x0924 + + + USER_MC13_EN_SBREF + false + + + USER_MC13_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC13_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC13_LOOKAHEAD_PCH + true + + + USER_MC13_LOOKAHEAD_ACT + true + + + USER_MC13_REORDER_EN + true + + + USER_MC13_REORDER_RW_ONLY + false + + + USER_MC13_REORDER_QUEUE_EN + true + + + USER_MC13_MAINTAIN_COHERENCY + true + + + USER_MC13_Q_AGE_LIMIT + 0x7f + + + USER_MC13_EN_DATA_MASK + true + + + USER_MC13_INIT_PERR_RETRY_EN + false + + + USER_MC13_USER_PARITY_EN + false + + + USER_MC13_DQ_PARITY_EN + false + + + USER_MC13_RD_DQ_PARITY_EN + false + + + USER_MC13_WR_DQ_PARITY_EN + false + + + USER_MC13_CA_PARITY_EN + false + + + USER_MC13_HBM_CB_EN + false + + + USER_MC13_DM_EN + true + + + + false + + + + + + USER_MC13_RMW_EN + false + + + + false + + + + + + USER_MC14_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC14_MANUAL_REFRESH_SEL + false + + + USER_MC14_MANUAL_ADV_OPTIONS + false + + + USER_MC14_COL_ADDR_LOW + 0x4 + + + USER_MC14_COL_ADDR_HIGH + 0x4 + + + USER_MC14_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC14_LADDR_BA5_MAP + 0x05 + + + USER_MC14_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC14_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC14_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC14_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC14_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC14_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC14_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC14_BG_INTERLEAVE_EN + true + + + USER_MC14_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC14_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC14_REF_CMD_PERIOD + 0x0924 + + + USER_MC14_EN_SBREF + false + + + USER_MC14_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC14_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC14_LOOKAHEAD_PCH + true + + + USER_MC14_LOOKAHEAD_ACT + true + + + USER_MC14_REORDER_EN + true + + + USER_MC14_REORDER_RW_ONLY + false + + + USER_MC14_REORDER_QUEUE_EN + true + + + USER_MC14_MAINTAIN_COHERENCY + true + + + USER_MC14_Q_AGE_LIMIT + 0x7f + + + USER_MC14_EN_DATA_MASK + true + + + USER_MC14_INIT_PERR_RETRY_EN + false + + + USER_MC14_USER_PARITY_EN + false + + + USER_MC14_DQ_PARITY_EN + false + + + USER_MC14_RD_DQ_PARITY_EN + false + + + USER_MC14_WR_DQ_PARITY_EN + false + + + USER_MC14_CA_PARITY_EN + false + + + USER_MC14_HBM_CB_EN + false + + + USER_MC14_DM_EN + true + + + + false + + + + + + USER_MC14_RMW_EN + false + + + + false + + + + + + USER_MC15_MANUAL_ADDR_MAP_SEL + false + + + + false + + + + + + USER_MC15_MANUAL_REFRESH_SEL + false + + + USER_MC15_MANUAL_ADV_OPTIONS + false + + + USER_MC15_COL_ADDR_LOW + 0x4 + + + USER_MC15_COL_ADDR_HIGH + 0x4 + + + USER_MC15_LADDR_BA0_BA4_MAP + 0x00282248 + + + USER_MC15_LADDR_BA5_MAP + 0x05 + + + USER_MC15_LADDR_RA0_RA4_MAP + 0x0f38d30b + + + USER_MC15_LADDR_RA5_RA9_MAP + 0x55134914 + + + USER_MC15_LADDR_RA10_RA14_MAP + 0x00061759 + + + USER_MC15_LADDR_RA15_RA17_MAP + 0x00000 + + + USER_MC15_LADDR_CA0_CA4_MAP + 0xc61440c0 + + + USER_MC15_LADDR_CA5_CA9_MAP + 0x00000001 + + + USER_MC15_LADDR_CA10_CA15_MAP + 0x00000000 + + + USER_MC15_BG_INTERLEAVE_EN + true + + + USER_MC15_EN_TEMP_CTRL_REF_MODE + false + + + USER_MC15_EN_TEMP_COMP_SF_PERIOD + false + + + USER_MC15_REF_CMD_PERIOD + 0x0924 + + + USER_MC15_EN_SBREF + false + + + USER_MC15_BURST_RW_REFRESH_HOLDOFF + false + + + USER_MC15_SBREF_ISSUE_PER + 0x01e + + + + false + + + + + + USER_MC15_LOOKAHEAD_PCH + true + + + USER_MC15_LOOKAHEAD_ACT + true + + + USER_MC15_REORDER_EN + true + + + USER_MC15_REORDER_RW_ONLY + false + + + USER_MC15_REORDER_QUEUE_EN + true + + + USER_MC15_MAINTAIN_COHERENCY + true + + + USER_MC15_Q_AGE_LIMIT + 0x7f + + + USER_MC15_EN_DATA_MASK + true + + + USER_MC15_INIT_PERR_RETRY_EN + false + + + USER_MC15_USER_PARITY_EN + false + + + USER_MC15_DQ_PARITY_EN + false + + + USER_MC15_RD_DQ_PARITY_EN + false + + + USER_MC15_WR_DQ_PARITY_EN + false + + + USER_MC15_CA_PARITY_EN + false + + + USER_MC15_HBM_CB_EN + false + + + USER_MC15_DM_EN + true + + + + false + + + + + + USER_MC15_RMW_EN + false + + + + false + + + + + + USER_MC0_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC0_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC1_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC1_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC2_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC2_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC3_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC3_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC4_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC4_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC5_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC5_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC6_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC6_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC7_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC7_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC8_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC8_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC9_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC9_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC10_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC10_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC11_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC11_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC12_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC12_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC13_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC13_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC14_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC14_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC15_RA0_RA13_MAPPING + 0x61759551349140f38d30b + + + USER_MC15_CA0_CA5_MAP + 0x1c61440c0 + + + USER_MC0_ADDR_BIT + MC0 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC1_ADDR_BIT + MC1 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC2_ADDR_BIT + MC2 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC3_ADDR_BIT + MC2 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC4_ADDR_BIT + MC4 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC5_ADDR_BIT + MC5 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC6_ADDR_BIT + MC6 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC7_ADDR_BIT + MC7 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC8_ADDR_BIT + MC8 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC9_ADDR_BIT + MC9 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC10_ADDR_BIT + MC10 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC11_ADDR_BIT + MC11 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC12_ADDR_BIT + MC12 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC13_ADDR_BIT + MC13 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC14_ADDR_BIT + MC14 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_MC15_ADDR_BIT + MC15 Address Map + NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 + + + + false + + + + + + USER_READ_PERCENT_00 + 40 + + + USER_READ_PERCENT_01 + 40 + + + USER_READ_PERCENT_02 + 40 + + + USER_READ_PERCENT_03 + 40 + + + USER_READ_PERCENT_04 + 40 + + + USER_READ_PERCENT_05 + 40 + + + USER_READ_PERCENT_06 + 40 + + + USER_READ_PERCENT_07 + 40 + + + USER_READ_PERCENT_08 + 40 + + + USER_READ_PERCENT_09 + 40 + + + USER_READ_PERCENT_10 + 40 + + + USER_READ_PERCENT_11 + 40 + + + USER_READ_PERCENT_12 + 40 + + + USER_READ_PERCENT_13 + 40 + + + USER_READ_PERCENT_14 + 40 + + + USER_READ_PERCENT_15 + 40 + + + USER_READ_PERCENT_16 + 40 + + + USER_READ_PERCENT_17 + 40 + + + USER_READ_PERCENT_18 + 40 + + + USER_READ_PERCENT_19 + 40 + + + USER_READ_PERCENT_20 + 40 + + + USER_READ_PERCENT_21 + 40 + + + USER_READ_PERCENT_22 + 40 + + + USER_READ_PERCENT_23 + 40 + + + USER_READ_PERCENT_24 + 40 + + + USER_READ_PERCENT_25 + 40 + + + USER_READ_PERCENT_26 + 40 + + + USER_READ_PERCENT_27 + 40 + + + USER_READ_PERCENT_28 + 40 + + + USER_READ_PERCENT_29 + 40 + + + USER_READ_PERCENT_30 + 40 + + + USER_READ_PERCENT_31 + 40 + + + USER_WRITE_PERCENT_00 + 40 + + + USER_WRITE_PERCENT_01 + 40 + + + USER_WRITE_PERCENT_02 + 40 + + + USER_WRITE_PERCENT_03 + 40 + + + USER_WRITE_PERCENT_04 + 40 + + + USER_WRITE_PERCENT_05 + 40 + + + USER_WRITE_PERCENT_06 + 40 + + + USER_WRITE_PERCENT_07 + 40 + + + USER_WRITE_PERCENT_08 + 40 + + + USER_WRITE_PERCENT_09 + 40 + + + USER_WRITE_PERCENT_10 + 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Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + instr_blk_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + 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C_READ_WIDTH_B + 64 + + + C_WRITE_DEPTH_B + 1024 + + + C_READ_DEPTH_B + 1024 + + + C_ADDRB_WIDTH + 10 + + + C_HAS_MEM_OUTPUT_REGS_A + 0 + + + C_HAS_MEM_OUTPUT_REGS_B + 0 + + + C_HAS_MUX_OUTPUT_REGS_A + 0 + + + C_HAS_MUX_OUTPUT_REGS_B + 0 + + + C_MUX_PIPELINE_STAGES + 0 + + + C_HAS_SOFTECC_INPUT_REGS_A + 0 + + + C_HAS_SOFTECC_OUTPUT_REGS_B + 0 + + + C_USE_SOFTECC + 0 + + + C_USE_ECC + 0 + + + C_EN_ECC_PIPE + 0 + + + C_READ_LATENCY_A + 1 + + + C_READ_LATENCY_B + 1 + + + C_HAS_INJECTERR + 0 + + + C_SIM_COLLISION_CHECK + ALL + + + C_COMMON_CLK + 0 + + + C_DISABLE_WARN_BHV_COLL + 0 + + + C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 0 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 2 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 4.238151 mW + + + + + + choice_list_0e6ad450 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + instr_blk_mem_sim + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + 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false + + + + true + + + + + + Use_REGCEA_Pin + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Primitives + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Core + false + + + + false + + + + + + Use_REGCEB_Pin + false + + + + false + + + + + + register_porta_input_of_softecc + false + + + + false + + + + + + register_portb_output_of_softecc + false + + + + false + + + + + + Pipeline_Stages + 0 + + + + false + + + + + + Load_Init_File + true + + + + true + + + + + + Coe_File + ../../../../coe/program.coe + + + + true + + + + + + Fill_Remaining_Memory_Locations + false + + + + true + + + + + + Remaining_Memory_Locations + 0 + + + + false + + + + + + Use_RSTA_Pin + false + + + + true + + + + + + Reset_Memory_Latch_A + false + + + + false + + + + + + Reset_Priority_A + CE + + + + false + + + + + + Output_Reset_Value_A + 0 + + + + false + + + + + + Use_RSTB_Pin + false + + + + false + + + + + + Reset_Memory_Latch_B + false + + + + false + + + + + + Reset_Priority_B + CE + + + + false + + + + + + Output_Reset_Value_B + 0 + + + + false + + + + + + Reset_Type + SYNC + + + + false + + + + + + Additional_Inputs_for_Power_Estimation + false + + + + true + + + + + + Port_A_Clock + 100 + + + + true + + + + + + Port_A_Write_Rate + 50 + + + + true + + + + + + Port_B_Clock + 0 + + + + true + + + + + + Port_B_Write_Rate + 0 + + + + true + + + + + + Port_A_Enable_Rate + 100 + + + + true + + + + + + Port_B_Enable_Rate + 0 + + + + true + + + + + + Collision_Warnings + ALL + + + + true + + + + + + Disable_Collision_Warnings + false + + + + true + + + + + + Disable_Out_of_Range_Warnings + false + + + + true + + + + + + use_bram_block + Stand_Alone + + + + true + + + + + + MEM_FILE + no_mem_loaded + + + + true + + + + + + CTRL_ECC_ALGO + NONE + + + + true + + + + + + EN_SAFETY_CKT + false + + + + false + + + + + + READ_LATENCY_A + 1 + + + + false + + + + + + READ_LATENCY_B + 1 + + + + false + + + + + + + + Block Memory Generator + + XPM_MEMORY + + 4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci new file mode 100644 index 0000000..2473e53 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci @@ -0,0 +1,318 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pr_read_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.000 + 0 + 5 + 5 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 5.931282 mW + virtexuplusHBM + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + pr_read_mem.mem + pr_read_mem.mif + 0 + 1 + 0 + 0 + 1 + 32 + 32 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 32 + 32 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + virtexuplusHBM + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../coe/read.coe + ALL + pr_read_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 32 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + virtexuplusHBM + xilinx.com:au50:part0:1.3 + + xcu50 + fsvh2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xml b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xml new file mode 100644 index 0000000..a4158ab --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xml @@ -0,0 +1,4180 @@ + + + xilinx.com + customized_ip + pr_read_mem + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXI_SLAVE_S_AXI + AXI_SLAVE + AXI_SLAVE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARBURST + + + s_axi_arburst + + + + + ARID + + + s_axi_arid + + + + + ARLEN + + + s_axi_arlen + + + + + ARREADY + + + s_axi_arready + + + + + ARSIZE + + + s_axi_arsize + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWBURST + + + s_axi_awburst + + + + + AWID + + + s_axi_awid + + + + + AWLEN + + + s_axi_awlen + + + + + AWREADY + + + s_axi_awready + + + + + AWSIZE + + + s_axi_awsize + + + + + AWVALID + + + s_axi_awvalid + + + + + BID + + + s_axi_bid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RID + + + s_axi_rid + + + + + RLAST + + + s_axi_rlast + + + + + RREADY + + + s_axi_rready + + + + + RRESP + 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+ + C_AXI_ID_WIDTH + 4 + + + C_MEM_TYPE + 0 + + + C_BYTE_SIZE + 9 + + + C_ALGORITHM + 1 + + + C_PRIM_TYPE + 1 + + + C_LOAD_INIT_FILE + 1 + + + C_INIT_FILE_NAME + pr_read_mem.mif + + + C_INIT_FILE + pr_read_mem.mem + + + C_USE_DEFAULT_DATA + 0 + + + C_DEFAULT_DATA + 0 + + + C_HAS_RSTA + 0 + + + C_RST_PRIORITY_A + CE + + + C_RSTRAM_A + 0 + + + C_INITA_VAL + 0 + + + C_HAS_ENA + 1 + + + C_HAS_REGCEA + 0 + + + C_USE_BYTE_WEA + 0 + + + C_WEA_WIDTH + 1 + + + C_WRITE_MODE_A + WRITE_FIRST + + + C_WRITE_WIDTH_A + 64 + + + C_READ_WIDTH_A + 64 + + + C_WRITE_DEPTH_A + 32 + + + C_READ_DEPTH_A + 32 + + + C_ADDRA_WIDTH + 5 + + + C_HAS_RSTB + 0 + + + C_RST_PRIORITY_B + CE + + + C_RSTRAM_B + 0 + + + C_INITB_VAL + 0 + + + C_HAS_ENB + 0 + + + C_HAS_REGCEB + 0 + + + C_USE_BYTE_WEB + 0 + + + C_WEB_WIDTH + 1 + + + C_WRITE_MODE_B + WRITE_FIRST + + + C_WRITE_WIDTH_B + 64 + + + C_READ_WIDTH_B + 64 + + + C_WRITE_DEPTH_B + 32 + + + C_READ_DEPTH_B + 32 + + + C_ADDRB_WIDTH + 5 + + + C_HAS_MEM_OUTPUT_REGS_A + 0 + + + C_HAS_MEM_OUTPUT_REGS_B + 0 + + + C_HAS_MUX_OUTPUT_REGS_A + 0 + + + C_HAS_MUX_OUTPUT_REGS_B + 0 + + + C_MUX_PIPELINE_STAGES + 0 + + + C_HAS_SOFTECC_INPUT_REGS_A + 0 + + + C_HAS_SOFTECC_OUTPUT_REGS_B + 0 + + + C_USE_SOFTECC + 0 + + + C_USE_ECC + 0 + + + C_EN_ECC_PIPE + 0 + + + C_READ_LATENCY_A + 1 + + + C_READ_LATENCY_B + 1 + + + C_HAS_INJECTERR + 0 + + + C_SIM_COLLISION_CHECK + ALL + + + C_COMMON_CLK + 0 + + + C_DISABLE_WARN_BHV_COLL + 0 + + + C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 0 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 1 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 5.931282 mW + + + + + + choice_list_402310f0 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + pr_read_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + 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CE + + + + false + + + + + + Output_Reset_Value_B + 0 + + + + false + + + + + + Reset_Type + SYNC + + + + false + + + + + + Additional_Inputs_for_Power_Estimation + false + + + + true + + + + + + Port_A_Clock + 100 + + + + true + + + + + + Port_A_Write_Rate + 50 + + + + true + + + + + + Port_B_Clock + 0 + + + + true + + + + + + Port_B_Write_Rate + 0 + + + + true + + + + + + Port_A_Enable_Rate + 100 + + + + true + + + + + + Port_B_Enable_Rate + 0 + + + + true + + + + + + Collision_Warnings + ALL + + + + true + + + + + + Disable_Collision_Warnings + false + + + + true + + + + + + Disable_Out_of_Range_Warnings + false + + + + true + + + + + + use_bram_block + Stand_Alone + + + + true + + + + + + MEM_FILE + no_mem_loaded + + + + true + + + + + + CTRL_ECC_ALGO + NONE + + + + true + + + + + + EN_SAFETY_CKT + false + + + + false + + + + + + READ_LATENCY_A + 1 + + + + false + + + + + + READ_LATENCY_B + 1 + + + + false + + + + + + + + Block Memory Generator + + XPM_MEMORY + + 4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci new file mode 100644 index 0000000..48fdc62 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci @@ -0,0 +1,318 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pr_ref_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.000 + 0 + 7 + 7 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 5.931282 mW + virtexuplusHBM + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + pr_ref_mem.mem + pr_ref_mem.mif + 0 + 1 + 0 + 0 + 1 + 128 + 128 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 128 + 128 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + virtexuplusHBM + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../coe/ref.coe + ALL + pr_ref_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 128 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + virtexuplusHBM + xilinx.com:au50:part0:1.3 + + xcu50 + fsvh2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml new file mode 100644 index 0000000..6a6704f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml @@ -0,0 +1,4181 @@ + + + xilinx.com + customized_ip + pr_ref_mem + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset 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choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. 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C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_165ed04b + 64 + + + choice_list_22f447d7 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_62eb4a48 + 512 + 1024 + 2048 + 4096 + 8192 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_19452de4 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_40558afa + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + choice_pairs_ef3e87e1 + Embedded_Reg + + + choice_pairs_f78383bc + Synchronous_Reset + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + rdback_fifo + + + + true + + + + + + Fifo_Implementation + Common_Clock_Builtin_FIFO + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + First_Word_Fall_Through + + + + true + + + + + + asymmetric_port_width + true + + + + true + + + + + + Input_Data_Width + 512 + + + + true + + + + + + Input_Depth + 1024 + + + + true + + + + + + Output_Data_Width + 256 + + + + true + + + + + + Output_Depth + 2048 + + + + false + + + + + + Enable_ECC + false + + + + false + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + false + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + false + + + + + + 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+ use_dout_register + false + + + + false + + + + + + Master_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Slave_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Output_Register_Type + Embedded_Reg + + + + true + + + + + + Enable_Safety_Circuit + false + + + + false + + + + + + Enable_ECC_Type + Hard_ECC + + + + false + + + + + + C_SELECT_XPM + 0 + + + + + FIFO Generator + + XPM_MEMORY + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad.xci b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad.xci new file mode 100644 index 0000000..9e8ae6d --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad.xci @@ -0,0 +1,316 @@ + + + xilinx.com + xci + unknown + 1.0 + + + scratchpad + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.000 + 0 + 10 + 10 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 2.119075 mW + virtexuplusHBM + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + scratchpad.mem + no_coe_file_loaded + 0 + 0 + 0 + 0 + 1 + 1024 + 1024 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1024 + 1024 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + virtexuplusHBM + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + no_coe_file_loaded + ALL + scratchpad + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 1024 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + virtexuplusHBM + xilinx.com:au50:part0:1.3 + + xcu50 + fsvh2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad.xml b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad.xml new file mode 100644 index 0000000..db7fc7b --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad.xml @@ -0,0 +1,4179 @@ + + + xilinx.com + customized_ip + scratchpad + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXI_SLAVE_S_AXI + AXI_SLAVE + AXI_SLAVE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARBURST + + + s_axi_arburst + + + + + ARID + + + s_axi_arid + + + + + ARLEN + + + s_axi_arlen + + + + + ARREADY + + + s_axi_arready + + + + + ARSIZE + + + s_axi_arsize + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWBURST + + + s_axi_awburst + + + + + AWID + + + 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Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + scratchpad + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + 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dummy_view + + + + 1 + + + + + + false + + + + + + + + C_COMMON_CLOCK + 0 + + + C_SELECT_XPM + 0 + + + C_COUNT_TYPE + 0 + + + C_DATA_COUNT_WIDTH + 9 + + + C_DEFAULT_VALUE + BlankString + + + C_DIN_WIDTH + 1024 + + + C_DOUT_RST_VAL + 0 + + + C_DOUT_WIDTH + 512 + + + C_ENABLE_RLOCS + 0 + + + C_FAMILY + virtexuplusHBM + + + C_FULL_FLAGS_RST_VAL + 0 + + + C_HAS_ALMOST_EMPTY + 0 + + + C_HAS_ALMOST_FULL + 0 + + + C_HAS_BACKUP + 0 + + + C_HAS_DATA_COUNT + 0 + + + C_HAS_INT_CLK + 0 + + + C_HAS_MEMINIT_FILE + 0 + + + C_HAS_OVERFLOW + 0 + + + C_HAS_RD_DATA_COUNT + 0 + + + C_HAS_RD_RST + 0 + + + C_HAS_RST + 0 + + + C_HAS_SRST + 1 + + + C_HAS_UNDERFLOW + 0 + + + C_HAS_VALID + 0 + + + C_HAS_WR_ACK + 0 + + + C_HAS_WR_DATA_COUNT + 0 + + + C_HAS_WR_RST + 0 + + + C_IMPLEMENTATION_TYPE + 6 + + + C_INIT_WR_PNTR_VAL + 0 + + + C_MEMORY_TYPE + 4 + + + C_MIF_FILE_NAME + BlankString + + + C_OPTIMIZATION_MODE + 0 + + + C_OVERFLOW_LOW + 0 + + + C_PRELOAD_LATENCY + 2 + + + C_PRELOAD_REGS + 1 + + + C_PRIM_FIFO_TYPE + 512x72 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL + 2 + + + C_PROG_EMPTY_THRESH_NEGATE_VAL + 3 + + + C_PROG_EMPTY_TYPE + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL + 510 + + + C_PROG_FULL_THRESH_NEGATE_VAL + 509 + + + C_PROG_FULL_TYPE + 0 + + + C_RD_DATA_COUNT_WIDTH + 10 + + + C_RD_DEPTH + 1024 + + + C_RD_FREQ + 300 + + + C_RD_PNTR_WIDTH + 10 + + + C_UNDERFLOW_LOW + 0 + + + C_USE_DOUT_RST + 1 + + + C_USE_ECC + 0 + + + C_USE_EMBEDDED_REG + 1 + + + C_USE_PIPELINE_REG + 0 + + + C_POWER_SAVING_MODE + 0 + + + C_USE_FIFO16_FLAGS + 0 + + + C_USE_FWFT_DATA_COUNT + 0 + + + C_VALID_LOW + 0 + + + C_WR_ACK_LOW + 0 + + + C_WR_DATA_COUNT_WIDTH + 9 + + + C_WR_DEPTH + 512 + + + C_WR_FREQ + 150 + + + C_WR_PNTR_WIDTH + 9 + + + C_WR_RESPONSE_LATENCY + 1 + + + C_MSGON_VAL + 1 + + + C_ENABLE_RST_SYNC + 1 + + + C_EN_SAFETY_CKT + 0 + + + C_ERROR_INJECTION_TYPE + 0 + + + C_SYNCHRONIZER_STAGE + 2 + + + C_INTERFACE_TYPE + 0 + + + C_AXI_TYPE + 1 + + + C_HAS_AXI_WR_CHANNEL + 1 + + + C_HAS_AXI_RD_CHANNEL + 1 + + + C_HAS_SLAVE_CE + 0 + + + C_HAS_MASTER_CE + 0 + + + C_ADD_NGC_CONSTRAINT + 0 + + + C_USE_COMMON_OVERFLOW + 0 + + + C_USE_COMMON_UNDERFLOW + 0 + + + C_USE_DEFAULT_SETTINGS + 0 + + + C_AXI_ID_WIDTH + 1 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 64 + + + C_AXI_LEN_WIDTH + 8 + + + C_AXI_LOCK_WIDTH + 1 + + + C_HAS_AXI_ID + 0 + + + C_HAS_AXI_AWUSER + 0 + + + C_HAS_AXI_WUSER + 0 + + + C_HAS_AXI_BUSER + 0 + + + C_HAS_AXI_ARUSER + 0 + + + C_HAS_AXI_RUSER + 0 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_HAS_AXIS_TDATA + 1 + + + C_HAS_AXIS_TID + 0 + + + C_HAS_AXIS_TDEST + 0 + + + C_HAS_AXIS_TUSER + 1 + + + C_HAS_AXIS_TREADY + 1 + + + C_HAS_AXIS_TLAST + 0 + + + C_HAS_AXIS_TSTRB + 0 + + + C_HAS_AXIS_TKEEP + 0 + + + C_AXIS_TDATA_WIDTH + 8 + + + C_AXIS_TID_WIDTH + 1 + + + C_AXIS_TDEST_WIDTH + 1 + + + C_AXIS_TUSER_WIDTH + 4 + + + C_AXIS_TSTRB_WIDTH + 1 + + + C_AXIS_TKEEP_WIDTH + 1 + + + C_WACH_TYPE + 0 + + + C_WDCH_TYPE + 0 + + + C_WRCH_TYPE + 0 + + + C_RACH_TYPE + 0 + + + C_RDCH_TYPE + 0 + + + C_AXIS_TYPE + 0 + + + C_IMPLEMENTATION_TYPE_WACH + 1 + + + C_IMPLEMENTATION_TYPE_WDCH + 1 + + + C_IMPLEMENTATION_TYPE_WRCH + 1 + + + C_IMPLEMENTATION_TYPE_RACH + 1 + + + C_IMPLEMENTATION_TYPE_RDCH + 1 + + + C_IMPLEMENTATION_TYPE_AXIS + 1 + + + C_APPLICATION_TYPE_WACH + 0 + + + C_APPLICATION_TYPE_WDCH + 0 + + + C_APPLICATION_TYPE_WRCH + 0 + + + C_APPLICATION_TYPE_RACH + 0 + + + C_APPLICATION_TYPE_RDCH + 0 + + + C_APPLICATION_TYPE_AXIS + 0 + + + C_PRIM_FIFO_TYPE_WACH + 512x36 + + + C_PRIM_FIFO_TYPE_WDCH + 512x72 + + + C_PRIM_FIFO_TYPE_WRCH + 512x36 + + + C_PRIM_FIFO_TYPE_RACH + 512x36 + + + C_PRIM_FIFO_TYPE_RDCH + 512x72 + + + C_PRIM_FIFO_TYPE_AXIS + 1kx18 + + + C_USE_ECC_WACH + 0 + + + C_USE_ECC_WDCH + 0 + + + C_USE_ECC_WRCH + 0 + + + C_USE_ECC_RACH + 0 + + + C_USE_ECC_RDCH + 0 + + + C_USE_ECC_AXIS + 0 + + + C_ERROR_INJECTION_TYPE_WACH + 0 + + + C_ERROR_INJECTION_TYPE_WDCH + 0 + + + C_ERROR_INJECTION_TYPE_WRCH + 0 + + + C_ERROR_INJECTION_TYPE_RACH + 0 + + + C_ERROR_INJECTION_TYPE_RDCH + 0 + + + C_ERROR_INJECTION_TYPE_AXIS + 0 + + + C_DIN_WIDTH_WACH + 1 + + + C_DIN_WIDTH_WDCH + 64 + + + C_DIN_WIDTH_WRCH + 2 + + + C_DIN_WIDTH_RACH + 32 + + + C_DIN_WIDTH_RDCH + 64 + + + C_DIN_WIDTH_AXIS + 1 + + + C_WR_DEPTH_WACH + 16 + + + C_WR_DEPTH_WDCH + 1024 + + + C_WR_DEPTH_WRCH + 16 + + + C_WR_DEPTH_RACH + 16 + + + C_WR_DEPTH_RDCH + 1024 + + + C_WR_DEPTH_AXIS + 1024 + + + C_WR_PNTR_WIDTH_WACH + 4 + + + C_WR_PNTR_WIDTH_WDCH + 10 + + + C_WR_PNTR_WIDTH_WRCH + 4 + + + C_WR_PNTR_WIDTH_RACH + 4 + + + C_WR_PNTR_WIDTH_RDCH + 10 + + + C_WR_PNTR_WIDTH_AXIS + 10 + + + C_HAS_DATA_COUNTS_WACH + 0 + + + C_HAS_DATA_COUNTS_WDCH + 0 + + + C_HAS_DATA_COUNTS_WRCH + 0 + + + C_HAS_DATA_COUNTS_RACH + 0 + + + C_HAS_DATA_COUNTS_RDCH + 0 + + + C_HAS_DATA_COUNTS_AXIS + 0 + + + C_HAS_PROG_FLAGS_WACH + 0 + + + C_HAS_PROG_FLAGS_WDCH + 0 + + + C_HAS_PROG_FLAGS_WRCH + 0 + + + C_HAS_PROG_FLAGS_RACH + 0 + + + C_HAS_PROG_FLAGS_RDCH + 0 + + + C_HAS_PROG_FLAGS_AXIS + 0 + + + C_PROG_FULL_TYPE_WACH + 0 + + + C_PROG_FULL_TYPE_WDCH + 0 + + + C_PROG_FULL_TYPE_WRCH + 0 + + + C_PROG_FULL_TYPE_RACH + 0 + + + C_PROG_FULL_TYPE_RDCH + 0 + + + C_PROG_FULL_TYPE_AXIS + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WRCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_165ed04b + 64 + + + choice_list_4163f9c5 + 128 + 256 + 512 + 1024 + + + choice_list_62eb4a48 + 512 + 1024 + 2048 + 4096 + 8192 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_19452de4 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_40558afa + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + choice_pairs_ef3e87e1 + Embedded_Reg + + + choice_pairs_f78383bc + Synchronous_Reset + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + wrdata_fifo + + + + true + + + + + + Fifo_Implementation + Independent_Clocks_Builtin_FIFO + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + true + + + + true + + + + + + Input_Data_Width + 1024 + + + + true + + + + + + Input_Depth + 512 + + + + true + + + + + + Output_Data_Width + 512 + + + + true + + + + + + Output_Depth + 1024 + + + + false + + + + + + Enable_ECC + false + + + + false + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + false + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + false + + + + + + Full_Flags_Reset_Value + 0 + + + + false + + + + + + Use_Dout_Reset + true + + + + false + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + true + + + + + + Almost_Full_Flag + false + + + + false + + + + + + Almost_Empty_Flag + false + + + + false + + + + + + Valid_Flag + false + + + + true + + + + + + Valid_Sense + Active_High + + + + false + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + false + + + + false + + + + + + Data_Count_Width + 9 + + + + false + + + + + + Write_Data_Count + false + + + + false + + + + + + Write_Data_Count_Width + 9 + + + + false + + + + + + Read_Data_Count + false + + + + false + + + + + + Read_Data_Count_Width + 10 + + + + false + + + + + + Disable_Timing_Violations + false + + + + false + + + + + + Read_Clock_Frequency + 300 + + + + true + + + + + + Write_Clock_Frequency + 150 + + + + true + + + + + + Programmable_Full_Type + No_Programmable_Full_Threshold + + + + true + + + + + + Full_Threshold_Assert_Value + 510 + + + + false + + + + + + Full_Threshold_Negate_Value + 509 + + + + false + + + + + + Programmable_Empty_Type + No_Programmable_Empty_Threshold + + + + true + + + + + + Empty_Threshold_Assert_Value + 2 + + + + false + + + + + + Empty_Threshold_Negate_Value + 3 + + + + false + + + + + + PROTOCOL + AXI4 + + + + false + + + + + + Clock_Type_AXI + Common_Clock + + + + true + + + + + + HAS_ACLKEN + false + + + + false + + + + + + Clock_Enable_Type + Slave_Interface_Clock_Enable + + + + false + + + + + + READ_WRITE_MODE + READ_WRITE + + + + true + + + + + + ID_WIDTH + 0 + + + + false + + + + + + ADDRESS_WIDTH + 32 + + + + false + + + + + + DATA_WIDTH + 64 + + + + false + + + + + + AWUSER_Width + 0 + + + + false + + + + + + WUSER_Width + 0 + + + + false + + + + + + BUSER_Width + 0 + + + + false + + + + + + ARUSER_Width + 0 + + + + false + + + + + + RUSER_Width + 0 + + + + false + + + + + + TDATA_NUM_BYTES + 1 + + + + true + + + + + + TID_WIDTH + 0 + + + + false + + + + + + TDEST_WIDTH + 0 + + + + false + + + + + + TUSER_WIDTH + 4 + + + + false + + + + + + Enable_TREADY + true + + + + false + + + + + + Enable_TLAST + false + + + + true + + + + + + HAS_TSTRB + false + + + + false + + + + + + TSTRB_WIDTH + 1 + + + + false + + + + + + HAS_TKEEP + false + + + + false + + + + + + TKEEP_WIDTH + 1 + + + + false + + + + + + wach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wach + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wach + false + + + + false + + + + + + Inject_Sbit_Error_wach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wach + false + + + + false + + + + + + Input_Depth_wach + 16 + + + + true + + + + + + Enable_Data_Counts_wach + false + + + + false + + + + + + Programmable_Full_Type_wach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wdch + false + + + + false + + + + + + Inject_Sbit_Error_wdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wdch + false + + + + false + + + + + + Input_Depth_wdch + 1024 + + + + true + + + + + + Enable_Data_Counts_wdch + false + + + + false + + + + + + Programmable_Full_Type_wdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wrch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wrch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wrch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wrch + false + + + + false + + + + + + Inject_Sbit_Error_wrch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wrch + false + + + + false + + + + + + Input_Depth_wrch + 16 + + + + true + + + + + + Enable_Data_Counts_wrch + false + + + + false + + + + + + Programmable_Full_Type_wrch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wrch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wrch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wrch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rach + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rach + false + + + + false + + + + + + Inject_Sbit_Error_rach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rach + false + + + + false + + + + + + Input_Depth_rach + 16 + + + + true + + + + + + Enable_Data_Counts_rach + false + + + + false + + + + + + Programmable_Full_Type_rach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rdch + false + + + + false + + + + + + Inject_Sbit_Error_rdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rdch + false + + + + false + + + + + + Input_Depth_rdch + 1024 + + + + true + + + + + + Enable_Data_Counts_rdch + false + + + + false + + + + + + Programmable_Full_Type_rdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + axis_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_axis + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_axis + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_axis + false + + + + false + + + + + + Inject_Sbit_Error_axis + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_axis + Double Bit Error Injection + false + + + + false + + + + + + Input_Depth_axis + 1024 + + + + true + + + + + + Enable_Data_Counts_axis + false + + + + false + + + + + + Programmable_Full_Type_axis + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_axis + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_axis + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_axis + Empty Threshold Assert Value + 1022 + + + + false + + + + + + Register_Slice_Mode_wach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wrch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_axis + Register Slice Options + Fully_Registered + + + + true + + + + + + Underflow_Flag_AXI + Underflow Flag + false + + + + false + + + + + + Underflow_Sense_AXI + Underflow (Read Error) + Active_High + + + + false + + + + + + Overflow_Flag_AXI + Overflow Flag + false + + + + false + + + + + + Overflow_Sense_AXI + Overflow (Write Error) + Active_High + + + + false + + + + + + Disable_Timing_Violations_AXI + false + + + + true + + + + + + Add_NGC_Constraint_AXI + false + + + + true + + + + + + Enable_Common_Underflow + false + + + + true + + + + + + Enable_Common_Overflow + false + + + + true + + + + + + enable_read_pointer_increment_by2 + false + + + + true + + + + + + Use_Embedded_Registers_axis + false + + + + false + + + + + + enable_low_latency + false + + + + false + + + + + + use_dout_register + false + + + + false + + + + + + Master_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Slave_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Output_Register_Type + Embedded_Reg + + + + true + + + + + + Enable_Safety_Circuit + false + + + + false + + + + + + Enable_ECC_Type + Hard_ECC + + + + false + + + + + + C_SELECT_XPM + 0 + + + + + FIFO Generator + + XPM_MEMORY + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xci b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xci new file mode 100644 index 0000000..6440e75 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xci @@ -0,0 +1,1433 @@ + + + xilinx.com + xci + unknown + 1.0 + + + xdma_pcie4c_ip_gt + + + "000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" + 2 + 2500.0 + 0 + 0 + 100 + 67 + 3 + 1 + 0 + 2 + 1 + 0 + 1 + 1 + 1 + 1 + 500 + 1 + 0 + 0 + 0 + 0 + 1 + "00000000" + "00000000" + 1 + 4 + 0 + "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + "00000000" + 1 + "00000001" + 1 + 1 + 5000 + "00000000000000000000000000000000000000000000000000000000000000000000000000011100" + 1 + "1010000011" + 1 + "0101111100" + 1 + 1 + 20 + 8 + 111 + 1 + 400.0000000 + 1 + 1 + 0x000000000000000000000000000000000000000000000000 + 100 + 2 + 0 + 0 + 1 + 1 + 0 + 16 + 400.0000000 + 400.0000000 + 0 + 257.8125 + 1 + 8 + 2 + 0 + 0 + 1 + 400 + 0 + 0 + 0 + 1 + 1 + 20 + 8 + 111 + 1 + 400.0000000 + 4 + 1 + 100 + 0 + 0 + 1 + 1 + 0 + 16 + 400.0000000 + 400.0000000 + 1 + X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 + xdma_pcie4c_ip_gt + 0 + 0 + txpdelecidlemode_in txprgdivresetdone_out rcalenb_in txpisopd_in rxratemode_in dmonfiforeset_in dmonitorclk_in dmonitorout_out txdlysresetdone_out rxdlysresetdone_out rxphaligndone_out rxsyncdone_out eyescanreset_in txdiffctrl_in rxtermination_in cpllpd_in drpaddr_common_in drpclk_common_in drpdi_common_in drpen_common_in drpwe_common_in loopback_in pcieeqrxeqadaptdone_in pcierstidle_in pciersttxsyncstart_in pcieuserratedone_in qpll0pd_in qpll1pd_in rxcdrreset_in rxdfelpmreset_in rxlpmen_in rxpc +sreset_in rxpd_in rxpmareset_in rxpolarity_in rxprbscntreset_in rxprbssel_in rxrate_in txdeemph_in txdetectrx_in txelecidle_in txmaincursor_in txmargin_in txpcsreset_in txpd_in txpmareset_in txpostcursor_in txprbsforceerr_in txprbssel_in txprecursor_in txrate_in txswing_in bufgtce_out bufgtcemask_out bufgtdiv_out bufgtreset_out bufgtrstmask_out drpdo_common_out drprdy_common_out gtpowergood_out pcierategen3_out pcierateidle_out pcierateqpllpd_out pcierateqpllreset_out pciesynctxsyncdone_out pcie +usergen3rdy_out pcieuserphystatusrst_out pcieuserratestart_out phystatus_out rxelecidle_out rxoutclkfabric_out rxoutclkpcs_out rxprbserr_out rxprbslocked_out rxrecclkout_out rxstatus_out rxvalid_out txoutclkfabric_out txoutclkpcs_out qpll1freqlock_in qpll0freqlock_in cpllfreqlock_in qpll0lock_out qpll1lock_out drpclk_in cpllreset_in qpll1outclk_out qpll1outrefclk_out qpll0outclk_out qpll0outrefclk_out pcierateqpll0_in pcierateqpll1_in gtrefclk00_in gtrefclk01_in qpll0reset_in qpll1reset_in drpwe +_in drpaddr_in drpen_in drprst_in drprdy_out drpdi_in drpdo_out rxcdrhold_in rxdfeagchold_in rxdfecfokhold_in rxdfelfhold_in rxdfekhhold_in rxdfetap2hold_in rxdfetap3hold_in rxdfetap4hold_in rxdfetap5hold_in rxdfetap6hold_in rxdfetap7hold_in rxdfetap8hold_in rxdfetap9hold_in rxdfetap10hold_in rxdfetap11hold_in rxdfetap12hold_in rxdfetap13hold_in rxdfetap14hold_in rxdfetap15hold_in rxdfeuthold_in rxdfevphold_in rxoshold_in rxlpmgchold_in rxlpmhfhold_in rxlpmlfhold_in rxlpmoshold_in rxratedone_out + rxcdrfreqreset_in resetovrd_in txoutclksel_in cplllock_out gtrefclk0_in + 100 + BOTH + 0 + GTY + 1 + 15 + 96 + 5 + gtye4 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + -1 + -1 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + 1 + 1 + 1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + 1 + -1 + -1 + -1 + 1 + -1 + -1 + 1 + -1 + -1 + -1 + -1 + -1 + 1 + -1 + 1 + -1 + -1 + -1 + -1 + -1 + 1 + 1 + 1 + 1 + 0 + 0 + -1 + -1 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 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xcu50 + fsvh2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 9 + TRUE + . + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xml b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xml new file mode 100644 index 0000000..3936c93 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4c_ip_gt.xml @@ -0,0 +1,22837 @@ + + + xilinx.com + customized_ip + xdma_pcie4c_ip_gt + 1.0 + + + + xilinx_elaborateports + Elaborate Ports + :vivado.xilinx.com:elaborate.ports + gtwizard_ultrascale_v1_7_9_gtwizard_ultrascale + + + outputProductCRC + 9:9a660188 + + + + + + + gtwiz_userclk_tx_reset_in + + in + + 0 + 0 + + + + wire + xilinx_elaborateports + + + + 0 + + + + + + required + true + + + + + + gtwiz_userclk_tx_active_in + + in + + 0 + 0 + + + + wire + xilinx_elaborateports + + + + 0 + + + + + + required + true + + + + + + gtwiz_userclk_tx_srcclk_out + + out + + 0 + 0 + + + + wire + xilinx_elaborateports + + + + 0 + + + + + + illegal + false + + + + + + gtwiz_userclk_tx_usrclk_out + + out + + 0 + 0 + + + + wire + xilinx_elaborateports + + + + 0 + + + + + + illegal + false + + + + + + gtwiz_userclk_tx_usrclk2_out + + out + + 0 + 0 + + + + wire + xilinx_elaborateports + + + + 0 + + + + + + illegal + false + + + + + + gtwiz_userclk_tx_active_out + + out + + 0 + 0 + + + + wire + xilinx_elaborateports + + + + 0 + + + + + + illegal + false + + + + + + gtwiz_userclk_rx_reset_in + + in + + 0 + 0 + + + + wire + xilinx_elaborateports + + + + 0 + + + + + + illegal + false + + + + + + gtwiz_userclk_rx_active_in + + in + + 0 + 0 + + + + wire + xilinx_elaborateports + + + + 0 + + + + + + required + true + + + + + + gtwiz_userclk_rx_srcclk_out + + out + + 0 + 0 + + + + wire + xilinx_elaborateports + + + + 0 + + + + + + illegal + false + + + + + + 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GTY-HDMI + GTY-HD_SDI + GTY-HMC_12_5G + GTY-Interlaken_10G + GTY-Interlaken_12_5G + GTY-Interlaken_25G + GTY-JESD204 + GTY-JESD204B_highloss + GTY-JESD204B_lowloss + GTY-OTL4_10 + GTY-OTU2 + GTY-OTU2e + GTY-OTU4 + GTY-QSGMII + GTY-RXAUI + GTY-SATA + GTY-SRIO_Gen2 + GTY-VbyOne + GTY-XAUI + GTY-XLAUI + + + choice_pairs_7b0c3758 + RX + BOTH + TX + + + choice_pairs_85f99b7f + K28.1 + K28.5 + NONE + + + choice_pairs_8846c8f0 + RAW + 8B10B + 64B66B + 64B66B_CAUI + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_88c85933 + 8B10B + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + RAW + 64B66B + 64B66B_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_93c2d4ee + CORE + EXAMPLE_DESIGN + + + choice_pairs_9c19f015 + 1 + 2 + + + choice_pairs_a537ddda + 0 + 1 + + + choice_pairs_aa541099 + AUTO + DFE + LPM + + + choice_pairs_ae574462 + OFF + PCS + PMA + AUTO + + + choice_pairs_b0974ef0 + 1 + 2 + 0 + + + choice_pairs_d4feb97d + DISABLE + ENABLE + + + choice_pairs_f05b8192 + CHANNEL + NAME + + + The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. + + + GT_TYPE + Transceiver type + For devices which contain more than one serial transceiver type, select the type of transceiver to configure + GTY + + + INTERNAL_GT_PRIM_TYPE + gtye4 + + + + false + + + + + + GT_REV + Transceiver revision + Select the serial transceiver silicon revision + 0 + + + GT_DIRECTION + Transmit and/or Receive direction + Enable transmit and/or receive + BOTH + + + RX_ENABLE + Enabled + Enable the receiver for use + true + + + + false + + + + + + TX_ENABLE + Enabled + Enable the transmitter for use + true + + + + false + + + + + + CHANNEL_ENABLE + Enable channel + Indicate whether this transceiver channel is instantiated and enabled for use + X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 + + + TX_MASTER_CHANNEL + Master TX channel + Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) + X1Y15 + + + RX_MASTER_CHANNEL + Master RX channel + Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) + X1Y15 + + + INTERNAL_TOTAL_NUM_CHANNELS + Total number of channels + 8 + + + + false + + + + + + INTERNAL_TOTAL_NUM_COMMONS + Total number of commons required + 2 + + + + false + + + + + + LOCATE_COMMON + Include transceiver COMMON in the + If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. + CORE + + + INTERNAL_NUM_COMMONS_CORE + Number of commons in core + 2 + + + + false + + + + + + INTERNAL_NUM_COMMONS_EXAMPLE + Number of commons in example + 0 + + + + false + + + + + + INTERNAL_TX_USRCLK_FREQUENCY + 400.0000000 + + + + false + + + + + + INTERNAL_RX_USRCLK_FREQUENCY + 400.0000000 + + + + false + + + + + + RX_PPM_OFFSET + PPM offset between receiver and transmitter + Specify the PPM offset between received data and transmitted data + 0 + + + OOB_ENABLE + Enable Out of Band signaling (OOB)/Electrical Idle + Enable or disable Out of Band signaling (OOB)/Electrical Idle + false + + + + false + + + + + + RX_SSC_PPM + Spread spectrum clocking + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Insertion loss at Nyquist (dB) + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 15 + + + PCIE_CORECLK_FREQ + 500 + + + PCIE_USERCLK_FREQ + 250 + + + TX_LINE_RATE + Line rate (Gb/s) + Enter the transmitter line rate in Gb/s + 8 + + + TX_PLL_TYPE + PLL type + Select the transmitter PLL type + QPLL1 + + + TX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type + 100 + + + TX_DATA_ENCODING + Encoding + Select the encoding format for data transmission, or choose 'Raw' for no data encoding + 8B10B + + + TX_USER_DATA_WIDTH + User data width + Select the width at which the user logic will provide parallel data to the serial transceiver for transmission + 16 + + + TX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal transmitter data path + 20 + + + TX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the transmitter buffer + 0 + + + TX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection + 0 + + + TX_OUTCLK_SOURCE + TXOUTCLK source + Select the source of TXOUTCLK + TXPROGDIVCLK + + + TX_DIFF_SWING_EMPH_MODE + Differential swing and emphasis mode + Select the transmitter differential swing and emphasis mode for your application + PCIE_GEN1_GEN2 + + + RX_LINE_RATE + Line rate (Gb/s) + Enter the receiver line rate in Gb/s + 8 + + + RX_PLL_TYPE + PLL type + Select the receiver PLL type + QPLL1 + + + RX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type + 100 + + + RX_DATA_DECODING + Decoding + Select the decoding format for data reception, or choose 'Raw' for no data decoding + 8B10B + + + RX_USER_DATA_WIDTH + User data width + Select the width at which the serial transceiver will provide received parallel data to the user logic + 16 + + + RX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal receiver data path + 20 + + + RX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the receiver elastic buffer + 1 + + + RX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection + 0 + + + RX_EQ_MODE + Equalization mode + Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. + DFE + + + RX_JTOL_FC + Mask corner frequency (MHz) + Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. + 1 + + + RX_JTOL_LF_SLOPE + Mask low frequency slope (dB/decade) + Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. + -20 + + + RX_OUTCLK_SOURCE + RXOUTCLK source + Select the source of RXOUTCLK + RXOUTCLKPMA + + + SIM_CPLL_CAL_BYPASS + 1 + + + PCIE_ENABLE + true + + + RX_TERMINATION + Termination + Select the receiver termination + PROGRAMMABLE + + + RX_TERMINATION_PROG_VALUE + Programmable termination voltage (mV) + Select the termination voltage (in mV) when in programmable mode + 800 + + + RX_COUPLING + Link coupling + Select the link coupling + AC + + + RX_BUFFER_BYPASS_MODE + Receiver elastic buffer bypass mode + Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode + MULTI + + + + false + + + + + + RX_BUFFER_RESET_ON_CB_CHANGE + Reset receiver elastic buffer on channel bonding change + Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL + ENABLE + + + + false + + + + + + RX_BUFFER_RESET_ON_COMMAALIGN + Reset receiver elastic buffer on comma alignment + Control whether the receiver elastic buffer is reset on comma alignment + DISABLE + + + RX_BUFFER_RESET_ON_RATE_CHANGE + Reset receiver elastic buffer on rate change + Control whether the receiver elastic buffer is reset on rate change + ENABLE + + + TX_BUFFER_RESET_ON_RATE_CHANGE + Reset transmitter buffer on rate change + Control whether the transmitter buffer is reset on rate change + ENABLE + + + + false + + + + + + RESET_SEQUENCE_INTERVAL + Reset sequence time interval (ns) + Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval + 0 + + + RX_COMMA_PRESET + Comma value preset + K28.5 + + + RX_COMMA_VALID_ONLY + Valid comma values for 8B/10B decoding + Select the range of comma characters decoded by the 8B/10B decoder + 0 + + + RX_COMMA_P_ENABLE + Detect plus comma + Indicate whether or not the specified bit pattern is detected as a plus comma + true + + + RX_COMMA_M_ENABLE + Detect minus comma + Indicate whether or not the specified bit pattern is detected as a minus comma + true + + + RX_COMMA_DOUBLE_ENABLE + Detect combined plus/minus (double-length) comma + Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence + false + + + RX_COMMA_P_VAL + Plus comma value + Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received + 0101111100 + + + RX_COMMA_M_VAL + Minus comma value + Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received + 1010000011 + + + RX_COMMA_MASK + Mask + Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" + 1111111111 + + + RX_COMMA_ALIGN_WORD + Alignment boundary + Select which data byte boundaries are allowed for comma alignment + 1 + + + RX_COMMA_SHOW_REALIGN_ENABLE + Show realign comma + Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency + true + + + RX_SLIDE_MODE + Manual alignment (RXSLIDE) mode + Select whether to enable manual alignment, and in what mode if enabled + PMA + + + RX_CB_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable channel bonding, and how many sequences to use if enabled + 0 + + + RX_CB_LEN_SEQ + Length of each sequence + Select the number of characters in each channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_SKEW + Sequence maximum skew + Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_LEVEL + Maximum channel bonding level to be used + Select the maximum channel bonding level that will be used in the system channel bonding topology + 4 + + + + false + + + + + + RX_CB_MASK + 00000000 + + + + false + + + + + + RX_CB_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + + + + false + + + + + + RX_CB_K + 00000000 + + + + false + + + + + + RX_CB_DISP + 00000000 + + + + false + + + + + + RX_CB_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable clock correction, and how many sequences to use if enabled + 1 + + + RX_CC_LEN_SEQ + Length of each sequence + Select the number of characters in each channel clock correction sequence + 1 + + + RX_CC_PERIODICITY + Periodicity of the sequence (in bytes) + Specify the separation between clock correction sequences, in bytes + 5000 + + + RX_CC_KEEP_IDLE + Keep idle + Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received + ENABLE + + + RX_CC_PRECEDENCE + Precedence + Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time + ENABLE + + + + false + + + + + + RX_CC_REPEAT_WAIT + Minimum repetition + Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction + 0 + + + RX_CC_MASK + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + 00000000 + + + + false + + + + + + RX_CC_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000011100 + + + RX_CC_K + 00000001 + + + + false + + + + + + RX_CC_DISP + 00000000 + + + + false + + + + + + RX_CC_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_0 + Value + Specify the value for this clock correction sequence and pattern + 00011100 + + + RX_CC_K_0_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_1 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_0 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_1 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + ENABLE_OPTIONAL_PORTS + Enable optional ports + Indicate whether a port should be included + txpdelecidlemode_in txprgdivresetdone_out rcalenb_in txpisopd_in rxratemode_in dmonfiforeset_in dmonitorclk_in dmonitorout_out txdlysresetdone_out rxdlysresetdone_out rxphaligndone_out rxsyncdone_out eyescanreset_in txdiffctrl_in rxtermination_in cpllpd_in drpaddr_common_in drpclk_common_in drpdi_common_in drpen_common_in drpwe_common_in loopback_in pcieeqrxeqadaptdone_in pcierstidle_in pciersttxsyncstart_in pcieuserratedone_in qpll0pd_in qpll1pd_in rxcdrreset_in rxdfelpmreset_in rxlpmen_in rxpc +sreset_in rxpd_in rxpmareset_in rxpolarity_in rxprbscntreset_in rxprbssel_in rxrate_in txdeemph_in txdetectrx_in txelecidle_in txmaincursor_in txmargin_in txpcsreset_in txpd_in txpmareset_in txpostcursor_in txprbsforceerr_in txprbssel_in txprecursor_in txrate_in txswing_in bufgtce_out bufgtcemask_out bufgtdiv_out bufgtreset_out bufgtrstmask_out drpdo_common_out drprdy_common_out gtpowergood_out pcierategen3_out pcierateidle_out pcierateqpllpd_out pcierateqpllreset_out pciesynctxsyncdone_out pcie +usergen3rdy_out pcieuserphystatusrst_out pcieuserratestart_out phystatus_out rxelecidle_out rxoutclkfabric_out rxoutclkpcs_out rxprbserr_out rxprbslocked_out rxrecclkout_out rxstatus_out rxvalid_out txoutclkfabric_out txoutclkpcs_out qpll1freqlock_in qpll0freqlock_in cpllfreqlock_in qpll0lock_out qpll1lock_out drpclk_in cpllreset_in qpll1outclk_out qpll1outrefclk_out qpll0outclk_out qpll0outrefclk_out pcierateqpll0_in pcierateqpll1_in gtrefclk00_in gtrefclk01_in qpll0reset_in qpll1reset_in drpwe +_in drpaddr_in drpen_in drprst_in drprdy_out drpdi_in drpdo_out rxcdrhold_in rxdfeagchold_in rxdfecfokhold_in rxdfelfhold_in rxdfekhhold_in rxdfetap2hold_in rxdfetap3hold_in rxdfetap4hold_in rxdfetap5hold_in rxdfetap6hold_in rxdfetap7hold_in rxdfetap8hold_in rxdfetap9hold_in rxdfetap10hold_in rxdfetap11hold_in rxdfetap12hold_in rxdfetap13hold_in rxdfetap14hold_in rxdfetap15hold_in rxdfeuthold_in rxdfevphold_in rxoshold_in rxlpmgchold_in rxlpmhfhold_in rxlpmlfhold_in rxlpmoshold_in rxratedone_out + rxcdrfreqreset_in resetovrd_in txoutclksel_in cplllock_out gtrefclk0_in + + + RX_REFCLK_SOURCE + Receiver reference clock source + Select a reference clock input to drive the PLL chosen for receiver operation + + + + TX_REFCLK_SOURCE + Transmitter reference clock source + Select a reference clock input to drive the PLL chosen for transmitter operation + + + + RX_RECCLK_OUTPUT + Drive recovered clock out of device + Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use + + + + LOCATE_RESET_CONTROLLER + Include reset controller in the + Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + LOCATE_TX_BUFFER_BYPASS_CONTROLLER + Include transmitter buffer bypass controller in the + If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + LOCATE_RX_BUFFER_BYPASS_CONTROLLER + Include receiver elastic buffer bypass controller in the + If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_IN_SYSTEM_IBERT_CORE + Include In-System IBERT core + Indicate whether or not the In-System IBERT core should be instantiated in the example design. + NONE + + + LOCATE_TX_USER_CLOCKING + Include simple transmitter user clocking network in the + Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_RX_USER_CLOCKING + Include simple receiver user clocking network in the + Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_USER_DATA_WIDTH_SIZING + Include user data width sizing in the + Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + ORGANIZE_PORTS_BY + In the example design, organize ports across multiple channels by + If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) + NAME + + + PRESET + Transceiver configuration preset + You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard + None + + + INTERNAL_PRESET + Transceiver configuration preset + None + + + INTERNAL_PORT_USAGE_UPDATED + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLEMENT_UPDATED + 23 + + + + false + + + + + + INTERNAL_CHANNEL_SITES_UPDATED + 5 + + + + false + + + + + + INTERNAL_CHANNEL_COLUMN_LOC_MAX + 96 + + + + false + + + + + + INTERNAL_RX_COMMA_PRESET_UPDATE + 8 + + + + false + + + + + + INTERNAL_UPDATE_IP_SYMBOL_drpclk_in + true + + + + false + + + + + + SECONDARY_QPLL_ENABLE + Enable secondary QPLL + Enable and configure the QPLL which is not used in this core configuration + false + + + SECONDARY_QPLL_LINE_RATE + Line rate of second core (Gb/s) + Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL + 10.3125 + + + + false + + + + + + SECONDARY_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection + 0 + + + + false + + + + + + SECONDARY_QPLL_REFCLK_FREQUENCY + Actual Reference clock frequency (MHz) + Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate + 257.8125 + + + + false + + + + + + TXPROGDIV_FREQ_ENABLE + Enable selectable TXOUTCLK frequency + Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency + false + + + TXPROGDIV_FREQ_SOURCE + Programmable divider clock source + Select which PLL source is used to generate the selectable TXOUTCLK frequency + QPLL1 + + + + false + + + + + + TXPROGDIV_FREQ_VAL + TXOUTCLK frequency (MHz) + Select the TXOUTCLK frequency to be generated by the TX programmable divider + 400 + + + + false + + + + + + SATA_TX_BURST_LEN + TX COM sequence burst length + Select the number of bursts that make up a SATA COM sequence + 15 + + + FREERUN_FREQUENCY + Free-running and DRP clock frequency (MHz) + Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface + 100 + + + INCLUDE_CPLL_CAL + 1 + + + USER_GTPOWERGOOD_DELAY_EN + Select 1 to enable powergood delay circuit + 1 + + + DISABLE_LOC_XDC + Select to disable generation of LOC constraints in xdc + 0 + + + ENABLE_COMMON_USRCLK + 0 + + + USB_ENABLE + false + + + PCIE_64BIT + false + + + PCIE_GEN4_EIOS + false + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGBYPASSB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGMONITORENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGPDB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK01_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0PD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0RESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1PD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1RESET_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD2_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD3_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD4_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RCALENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0DATA_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0RESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0WIDTH_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1DATA_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1RESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1WIDTH_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONGPI_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONPOWERUP_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONRESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBDO_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBDRDY_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBENABLE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBGPI_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBINTR_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBIOLMBRST_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMBRST_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMREGEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMTCK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMTDI_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT + 0 + + + + false + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4c_ip.xml b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4c_ip.xml new file mode 100644 index 0000000..2549a03 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4c_ip.xml @@ -0,0 +1,31789 @@ + + + xilinx.com + customized_ip + xdma_pcie4c_ip + 1.0 + + + m_axis_cq + m_axis_cq + The Completer Request interface is used to transmit Completion TLP's to the Client Application + + + + + + + TDATA + + + m_axis_cq_tdata + + + + + TKEEP + + + m_axis_cq_tkeep + + + + + TLAST + + + m_axis_cq_tlast + + + + + TREADY + + + m_axis_cq_tready + + + + + TUSER + + + m_axis_cq_tuser + + + + + TVALID + + + m_axis_cq_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 88 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + s_axis_cc + s_axis_cc + The Completer Completion Interface is used to transmit Completion TLP's + + + + + + + TDATA + + + s_axis_cc_tdata + + + + + TKEEP + + + s_axis_cc_tkeep + + + + + TLAST + + + s_axis_cc_tlast + + + + + TREADY + + + s_axis_cc_tready + + + + + TUSER + + + s_axis_cc_tuser + + + + + TVALID + + + s_axis_cc_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 33 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + s_axis_rq + s_axis_rq + The Requestor Request interface received requests TLP's from the Client Application + + + + + + + TDATA + + + s_axis_rq_tdata + + + + + TKEEP + + + s_axis_rq_tkeep + + + + + TLAST + + + s_axis_rq_tlast + + + + + TREADY + + + s_axis_rq_tready + + + + + TUSER + + + s_axis_rq_tuser + + + + + TVALID + + + s_axis_rq_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 62 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + m_axis_rc + m_axis_rc + The Requestor Completer interface transmits completions to the client application + + + + + + + TDATA + + + m_axis_rc_tdata + + + + + TKEEP + + + m_axis_rc_tkeep + + + + + TLAST + + + m_axis_rc_tlast + + + + + TREADY + + + m_axis_rc_tready + + + + + TUSER + + + m_axis_rc_tuser + + + + + TVALID + + + m_axis_rc_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 75 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + cxs_tx + + + + + + + ACTIVE_ACK + + + cxs0_active_ack_tx + + + + + ACTIVE_REQ + + + cxs0_active_req_tx + + + + + CNTL + + + cxs0_cntl_tx + + + + + CNTL_CHK + + + cxs0_cntl_chk_tx + + + + + CRDGNT + + + cxs0_crdgnt_tx + + + + + CRDGNT_CHK + + + cxs0_crdgnt_chk_tx + + + + + CRDRTN + + + cxs0_crdrtn_tx + + + + + CRDRTN_CHK + + + cxs0_crdrtn_chk_tx + + + + + DATA + + + cxs0_data_tx + + + + + DATA_CHK + + + cxs0_data_chk_tx + + + + + DEACT_HINT + + + cxs0_deact_hint_tx + + + + + VALID + + + cxs0_valid_tx + + + + + VALID_CHK + + + cxs0_valid_chk_tx + + + + + + DATA_FLIT_WIDTH + 256 + + + MAX_PKT_PER_FLIT + 2 + + + DATACHECK + NONE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + + false + + + + + + cxs_rx + + + + + + + ACTIVE_ACK + + + cxs0_active_ack_rx + + + + + ACTIVE_REQ + + + cxs0_active_req_rx + + + + + CNTL + + + cxs0_cntl_rx + + + + + CNTL_CHK + + + cxs0_cntl_chk_rx + + + + + CRDGNT + + + cxs0_crdgnt_rx + + + + + CRDGNT_CHK + + + cxs0_crdgnt_chk_rx + + + + + CRDRTN + + + cxs0_crdrtn_rx + + + + + CRDRTN_CHK + + + cxs0_crdrtn_chk_rx + + + + + DATA + + + cxs0_data_rx + + + + + DATA_CHK + + + cxs0_data_chk_rx + + + + + DEACT_HINT + + + cxs0_deact_hint_rx + + + + + VALID + + + cxs0_valid_rx + + + + + VALID_CHK + + + cxs0_valid_chk_rx + + + + + + DATA_FLIT_WIDTH + 256 + + + MAX_PKT_PER_FLIT + 2 + + + DATACHECK + NONE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + + false + + + + + + CLK.s_aclk + CLK.s_aclk + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + S_AXI_DVSEC + + + FREQ_HZ + 250000000 + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + RST.s_aresetn + RST.s_aresetn + + + + + + + RST + + + s_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + S_AXI_DVSEC + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARBURST + + + s_axi_arburst + + + + + ARCACHE + + + s_axi_arcache + + + + + ARID + + + s_axi_arid + + + + + ARLEN + + + s_axi_arlen + + + + + ARLOCK + + + s_axi_arlock + + + + + ARPROT + + + s_axi_arprot + + + + + ARQOS + + + s_axi_arqos + + + + + ARREADY + + + s_axi_arready + + + + + ARSIZE + + + s_axi_arsize + + + + + ARUSER + + + s_axi_aruser + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWBURST + + + s_axi_awburst + + + + + AWCACHE + + + s_axi_awcache + + + + + AWID + + + s_axi_awid + + + + + AWLEN + + + s_axi_awlen + + + + + AWLOCK + + + s_axi_awlock + + + + + AWPROT + + + s_axi_awprot + + + + + AWQOS + + + s_axi_awqos + + + + + AWREADY + + + s_axi_awready + + + + + AWSIZE + + + s_axi_awsize + + + + + AWUSER + + + s_axi_awuser + + + + + AWVALID + + + s_axi_awvalid + + + + + BID + + + s_axi_bid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RID + + + s_axi_rid + + + + + RLAST + + + s_axi_rlast + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WLAST + + + s_axi_wlast + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 1 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 0 + + + none + + + + + HAS_BRESP + 0 + + + none + + + + + HAS_RRESP + 0 + + + none + + + + + SUPPORTS_NARROW_BURST + 0 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + RST.sys_rst + RST.sys_rst + sys_rst interface + + + + + + + RST + + + sys_reset + + + + + + BOARD.ASSOCIATED_PARAM + SYS_RST_N_BOARD_INTERFACE + + + + required + + + + + + TYPE + PCIE_PERST + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + pcie4_mgt + pcie_7x_mgt + PCIExpress Serial Link Interface + + + + + + + rxn + + + pci_exp_rxn + + + + + rxp + + + pci_exp_rxp + + + + + txn + + + pci_exp_txn + + + + + txp + + + pci_exp_txp + + + + + + BOARD.ASSOCIATED_PARAM + PCIE_BOARD_INTERFACE + + + + required + + + + + + + + + true + + + + + + pcie4_cfg_fc + pcie_cfg_fc + Configuration Flow Control INTERFACE + + + + + + + CPLD + + + cfg_fc_cpld + + + + + CPLH + + + cfg_fc_cplh + + + + + NPD + + + cfg_fc_npd + + + + + NPH + + + cfg_fc_nph + + + + + PD + + + cfg_fc_pd + + + + + PH + + + cfg_fc_ph + + + + + SEL + + + cfg_fc_sel + + + + + + + true + + + + + + pcie4_cfg_mgmt + pcie4_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr + + + + + BYTE_EN + + + cfg_mgmt_byte_enable + + + + + DEBUG_ACCESS + + + cfg_mgmt_debug_access + + + + + FUNCTION_NUMBER + + + cfg_mgmt_function_number + + + + + READ_DATA + + + cfg_mgmt_read_data + + + + + READ_EN + + + cfg_mgmt_read + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done + + + + + WRITE_DATA + + + cfg_mgmt_write_data + + + + + WRITE_EN + + + cfg_mgmt_write + + + + + + + true + + + + + + pcie4_cfg_mgmt_if + pcie4_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr + + + + + BYTE_EN + + + cfg_mgmt_byte_enable + + + + + DEBUG_ACCESS + + + cfg_mgmt_debug_access + + + + + FUNCTION_NUMBER + + + cfg_mgmt_function_number + + + + + READ_DATA + + + cfg_mgmt_read_data + + + + + READ_EN + + + cfg_mgmt_read + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done + + + + + WRITE_DATA + + + cfg_mgmt_write_data + + + + + WRITE_EN + + + cfg_mgmt_write + + + + + + + false + + + + + + pcie4_cfg_pm + pcie4_cfg_pm + PCIE4 Power Management Interface + + + + + + + pm_aspm_l1entry_reject + + + cfg_pm_aspm_l1_entry_reject + + + + + pm_aspm_tx_l0s_entry_disable + + + cfg_pm_aspm_tx_l0s_entry_disable + + + + + + + true + + + + + + pcie4_cfg_msi + pcie4_cfg_msi + PCIE MSI interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr + + + + + data + + + cfg_interrupt_msi_data + + + + + enable + + + cfg_interrupt_msi_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msi_int + + + + + mask_update + + + cfg_interrupt_msi_mask_update + + + + + mmenable + + + cfg_interrupt_msi_mmenable + + + + + pending_status + + + cfg_interrupt_msi_pending_status + + + + + pending_status_data_enable + + + cfg_interrupt_msi_pending_status_data_enable + + + + + pending_status_function_num + + + cfg_interrupt_msi_pending_status_function_num + + + + + select + + + cfg_interrupt_msi_select + + + + + sent + + + cfg_interrupt_msi_sent + + + + + tph_present + + + cfg_interrupt_msi_tph_present + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag + + + + + tph_type + + + cfg_interrupt_msi_tph_type + + + + + + + true + + + + + + pcie4_cfg_msix_internal + pcie4_cfg_msix_internal + PCIE MSIx Int Interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr + + + + + enable + + + cfg_interrupt_msix_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + mint_vector + + + cfg_interrupt_msi_int + + + + + sent + + + cfg_interrupt_msi_sent + + + + + tph_present + + + cfg_interrupt_msi_tph_present + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag + + + + + tph_type + + + cfg_interrupt_msi_tph_type + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_msix_internal_if + pcie4_cfg_msix_internal + PCIE MSIx Int Interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr + + + + + enable + + + cfg_interrupt_msix_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + mint_vector + + + cfg_interrupt_msi_int + + + + + sent + + + cfg_interrupt_msi_sent + + + + + tph_present + + + cfg_interrupt_msi_tph_present + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag + + + + + tph_type + + + cfg_interrupt_msi_tph_type + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_external_msix + pcie4_cfg_external_msix_without_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address + + + + + data + + + cfg_interrupt_msix_data + + + + + enable + + + cfg_interrupt_msix_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + sent + + + cfg_interrupt_msi_sent + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_external_msix_without_msi_if + pcie4_cfg_external_msix_without_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address + + + + + data + + + cfg_interrupt_msix_data + + + + + enable + + + cfg_interrupt_msix_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + sent + + + cfg_interrupt_msi_sent + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_msix_external + pcie4_cfg_external_msix_with_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address + + + + + data + + + cfg_interrupt_msix_data + + + + + enable + + + cfg_interrupt_msix_enable + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_external_msix_with_msi_if + pcie4_cfg_external_msix_with_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address + + + + + data + + + cfg_interrupt_msix_data + + + + + enable + + + cfg_interrupt_msix_enable + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_interrupt + pcie4_cfg_interrupt + PCIE Legacy Interrupt + + + + + + + INTx_VECTOR + + + cfg_interrupt_int + + + + + PENDING + + + cfg_interrupt_pending + + + + + SENT + + + cfg_interrupt_sent + + + + + + pcie4_cfg_ext + pcie4_cfg_ext + Configuration Extend Interface + + + + + + + function_number + + + cfg_ext_function_number + + + + + read_data + + + cfg_ext_read_data + + + + + read_data_valid + + + cfg_ext_read_data_valid + + + + + read_received + + + cfg_ext_read_received + + + + + register_number + + + cfg_ext_register_number + + + + + write_byte_enable + + + cfg_ext_write_byte_enable + + + + + write_data + + + cfg_ext_write_data + + + + + write_received + + + cfg_ext_write_received + + + + + + + false + + + + + + pcie4_rbar + pcie4_rbar + Resizable bar Interface + + + + + + + bar_size + + + rbar_bar_size + + + + + function_number + + + rbar_function_number + + + + + write_enable_bar0 + + + rbar_write_enable_bar0 + + + + + write_enable_bar1 + + + rbar_write_enable_bar1 + + + + + write_enable_bar2 + + + rbar_write_enable_bar2 + + + + + write_enable_bar3 + + + rbar_write_enable_bar3 + + + + + write_enable_bar4 + + + rbar_write_enable_bar4 + + + + + write_enable_bar5 + + + rbar_write_enable_bar5 + + + + + + + false + + + + + + pcie4_cfg_mesg_tx + pcie4_cfg_mesg_tx + Configuration Transmit Message Interface + + + + + + + TRANSMIT + + + cfg_msg_transmit + + + + + TRANSMIT_DATA + + + cfg_msg_transmit_data + + + + + TRANSMIT_DONE + + + cfg_msg_transmit_done + + + + + TRANSMIT_TYPE + + + cfg_msg_transmit_type + + + + + + + true + + + + + + pcie4_cfg_mesg_rcvd + pcie4_cfg_mesg_rcvd + Configuration Received Message Interface + + + + + + + recd + + + cfg_msg_received + + + + + recd_data + + + cfg_msg_received_data + + + + + recd_type + + + cfg_msg_received_type + + + + + + + true + + + + + + pcie4_cfg_control + pcie4_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + bus_number + + + cfg_bus_number + + + + + config_space_enable + + + cfg_config_space_enable + + + + + ds_bus_number + + + cfg_ds_bus_number + + + + + ds_device_number + + + cfg_ds_device_number + + + + + ds_port_number + + + cfg_ds_port_number + + + + + dsn + + + cfg_dsn + + + + + err_cor_in + + + cfg_err_cor_in + + + + + err_uncor_in + + + cfg_err_uncor_in + + + + + flr_done + + + cfg_flr_done + + + + + flr_in_process + + + cfg_flr_in_process + + + + + hot_reset_in + + + cfg_hot_reset_in + + + + + hot_reset_out + + + cfg_hot_reset_out + + + + + link_training_enable + + + cfg_link_training_enable + + + + + power_state_change_ack + + + cfg_power_state_change_ack + + + + + power_state_change_interrupt + + + cfg_power_state_change_interrupt + + + + + req_pm_transition_l23_ready + + + cfg_req_pm_transition_l23_ready + + + + + vf_flr_done + + + cfg_vf_flr_done + + + + + vf_flr_func_num + + + cfg_vf_flr_func_num + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process + + + + + + + true + + + + + + pcie4_cfg_control_if + pcie4_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + bus_number + + + cfg_bus_number + + + + + config_space_enable + + + cfg_config_space_enable + + + + + ds_bus_number + + + cfg_ds_bus_number + + + + + ds_device_number + + + cfg_ds_device_number + + + + + ds_function_number + + + cfg_ds_function_number + + + + + ds_port_number + + + cfg_ds_port_number + + + + + dsn + + + cfg_dsn + + + + + err_cor_in + + + cfg_err_cor_in + + + + + err_uncor_in + + + cfg_err_uncor_in + + + + + flr_done + + + cfg_flr_done + + + + + flr_in_process + + + cfg_flr_in_process + + + + + hot_reset_in + + + cfg_hot_reset_in + + + + + hot_reset_out + + + cfg_hot_reset_out + + + + + link_training_enable + + + cfg_link_training_enable + + + + + pm_aspm_l1entry_reject + + + cfg_pm_aspm_l1_entry_reject + + + + + pm_aspm_tx_l0s_entry_disable + + + cfg_pm_aspm_tx_l0s_entry_disable + + + + + power_state_change_ack + + + cfg_power_state_change_ack + + + + + power_state_change_interrupt + + + cfg_power_state_change_interrupt + + + + + rbar_function_number + + + rbar_function_number + + + + + rbar_size + + + rbar_bar_size + + + + + req_pm_transition_l23_ready + + + cfg_req_pm_transition_l23_ready + + + + + vf_flr_done + + + cfg_vf_flr_done + + + + + vf_flr_func_num + + + cfg_vf_flr_func_num + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process + + + + + write_enable_rbar0 + + + rbar_write_enable_bar0 + + + + + write_enable_rbar1 + + + rbar_write_enable_bar1 + + + + + write_enable_rbar2 + + + rbar_write_enable_bar2 + + + + + write_enable_rbar3 + + + rbar_write_enable_bar3 + + + + + write_enable_rbar4 + + + rbar_write_enable_bar4 + + + + + write_enable_rbar5 + + + rbar_write_enable_bar5 + + + + + + + false + + + + + + pcie4_pcie_id + pcie4_pcie_id + PCIE 4 PCIE ID interface + + + + + + + subsys_vend_id + + + cfg_subsys_vend_id + + + + + vend_id + + + cfg_vend_id + + + + + + + false + + + + + + pcie4_pcie_id_pf0 + pcie4_pcie_id_pf0 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf0 + + + cfg_dev_id_pf0 + + + + + rev_id_pf0 + + + cfg_rev_id_pf0 + + + + + subsys_id_pf0 + + + cfg_subsys_id_pf0 + + + + + + + false + + + + + + pcie4_pcie_id_pf1 + pcie4_pcie_id_pf1 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf1 + + + cfg_dev_id_pf1 + + + + + rev_id_pf1 + + + cfg_rev_id_pf1 + + + + + subsys_id_pf1 + + + cfg_subsys_id_pf1 + + + + + + + false + + + + + + pcie4_pcie_id_pf2 + pcie4_pcie_id_pf2 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf2 + + + cfg_dev_id_pf2 + + + + + rev_id_pf2 + + + cfg_rev_id_pf2 + + + + + subsys_id_pf2 + + + cfg_subsys_id_pf2 + + + + + + + false + + + + + + pcie4_pcie_id_pf3 + pcie4_pcie_id_pf3 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf3 + + + cfg_dev_id_pf3 + + + + + rev_id_pf3 + + + cfg_rev_id_pf3 + + + + + subsys_id_pf3 + + + cfg_subsys_id_pf3 + + + + + + + false + + + + + + pcie4_cfg_status + pcie4_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req + + + + + cq_np_req_count + + + pcie_cq_np_req_count + + + + + current_speed + + + cfg_current_speed + + + + + err_cor_out + + + cfg_err_cor_out + + + + + err_fatal_out + + + cfg_err_fatal_out + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out + + + + + function_power_state + + + cfg_function_power_state + + + + + function_status + + + cfg_function_status + + + + + link_power_state + + + cfg_link_power_state + + + + + local_error_out + + + cfg_local_error_out + + + + + local_error_valid + + + cfg_local_error_valid + + + + + ltssm_state + + + cfg_ltssm_state + + + + + max_payload + + + cfg_max_payload + + + + + max_read_req + + + cfg_max_read_req + + + + + negotiated_width + + + cfg_negotiated_width + + + + + obff_enable + + + cfg_obff_enable + + + + + phy_link_down + + + cfg_phy_link_down + + + + + phy_link_status + + + cfg_phy_link_status + + + + + pl_status_change + + + cfg_pl_status_change + + + + + rcb_status + + + cfg_rcb_status + + + + + rq_seq_num0 + + + pcie_rq_seq_num0 + + + + + rq_seq_num1 + + + pcie_rq_seq_num1 + + + + + rq_seq_num_vld0 + + + pcie_rq_seq_num_vld0 + + + + + rq_seq_num_vld1 + + + pcie_rq_seq_num_vld1 + + + + + rq_tag0 + + + pcie_rq_tag0 + + + + + rq_tag1 + + + pcie_rq_tag1 + + + + + rq_tag_av + + + pcie_rq_tag_av + + + + + rq_tag_vld0 + + + pcie_rq_tag_vld0 + + + + + rq_tag_vld1 + + + pcie_rq_tag_vld1 + + + + + rx_pm_state + + + cfg_rx_pm_state + + + + + tph_requester_enable + + + cfg_tph_requester_enable + + + + + tph_st_mode + + + cfg_tph_st_mode + + + + + tx_pm_state + + + cfg_tx_pm_state + + + + + vf_power_state + + + cfg_vf_power_state + + + + + vf_status + + + cfg_vf_status + + + + + vf_tph_requester_enable + + + cfg_vf_tph_requester_enable + + + + + vf_tph_st_mode + + + cfg_vf_tph_st_mode + + + + + + + true + + + + + + pcie4_cfg_status_if + pcie4_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req + + + + + cq_np_req_count + + + pcie_cq_np_req_count + + + + + current_speed + + + cfg_current_speed + + + + + err_cor_out + + + cfg_err_cor_out + + + + + err_fatal_out + + + cfg_err_fatal_out + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out + + + + + function_power_state + + + cfg_function_power_state + + + + + function_status + + + cfg_function_status + + + + + link_power_state + + + cfg_link_power_state + + + + + local_error_out + + + cfg_local_error_out + + + + + local_error_valid + + + cfg_local_error_valid + + + + + ltssm_state + + + cfg_ltssm_state + + + + + max_payload + + + cfg_max_payload + + + + + max_read_req + + + cfg_max_read_req + + + + + negotiated_width + + + cfg_negotiated_width + + + + + obff_enable + + + cfg_obff_enable + + + + + phy_link_down + + + cfg_phy_link_down + + + + + phy_link_status + + + cfg_phy_link_status + + + + + pl_status_change + + + cfg_pl_status_change + + + + + rcb_status + + + cfg_rcb_status + + + + + rq_seq_num0 + + + pcie_rq_seq_num0 + + + + + rq_seq_num1 + + + pcie_rq_seq_num1 + + + + + rq_seq_num_vld0 + + + pcie_rq_seq_num_vld0 + + + + + rq_seq_num_vld1 + + + pcie_rq_seq_num_vld1 + + + + + rq_tag0 + + + pcie_rq_tag0 + + + + + rq_tag1 + + + pcie_rq_tag1 + + + + + rq_tag_av + + + pcie_rq_tag_av + + + + + rq_tag_vld0 + + + pcie_rq_tag_vld0 + + + + + rq_tag_vld1 + + + pcie_rq_tag_vld1 + + + + + rx_pm_state + + + cfg_rx_pm_state + + + + + tph_requester_enable + + + cfg_tph_requester_enable + + + + + tph_st_mode + + + cfg_tph_st_mode + + + + + tx_pm_state + + + cfg_tx_pm_state + + + + + vf_power_state + + + cfg_vf_power_state + + + + + vf_status + + + cfg_vf_status + + + + + vf_tph_requester_enable + + + cfg_vf_tph_requester_enable + + + + + vf_tph_st_mode + + + cfg_vf_tph_st_mode + + + + + + + false + + + + + + pcie4_transmit_fc + pcie4_transmit_fc + Transmit Flow Control Interfce + + + + + + + npd_av + + + pcie_tfc_npd_av + + + + + nph_av + + + pcie_tfc_nph_av + + + + + + + true + + + + + + pcie4_drp + pcie4_drp + PCIE DRP Interface + + + + + + + DADDR + + + drp_addr + + + + + DEN + + + drp_en + + + + + DI + + + drp_di + + + + + DO + + + drp_do + + + + + DRDY + + + drp_rdy + + + + + DWE + + + drp_we + + + + + + + false + + + + + + pcie4_drp_if + pcie4_drp + PCIE DRP Interface + + + + + + + DADDR + + + drp_addr + + + + + DEN + + + drp_en + + + + + DI + + + drp_di + + + + + DO + + + drp_do + + + + + DRDY + + + drp_rdy + + + + + DWE + + + drp_we + + + + + + + false + + + + + + CLK.sys_clk + CLK.sys_clk + sys_clk interface + + + + + + + CLK + + + sys_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.sys_clk_gt + CLK.sys_clk_gt + sys_clk_gt interface + + + + + + + CLK + + + sys_clk_gt + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.user_clk + CLK.user_clk + user_clk interface + + + + + + + CLK + + + user_clk + + + + + + ASSOCIATED_BUSIF + m_axis_cq:s_axis_cc:s_axis_rq:m_axis_rc:cxs_rx:cxs_tx + + + FREQ_HZ + 125000000 + + + ASSOCIATED_RESET + user_reset + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.mcap_clk + CLK.mcap_clk + mcap_clk interface + + + + + + + CLK + + + mcap_clk + + + + + + FREQ_HZ + 125000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + CLK.core_clk + CLK.core_clk + core_clk interface + + + + + + + CLK + + + core_clk + + + + + + FREQ_HZ + 500000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + CLK.gt_drp_clk + CLK.gt_drp_clk + gt_drp_clk interface + + + + + + + CLK + + + gt_drp_clk + + + + + + FREQ_HZ + 125000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + RST.user_reset + RST.user_reset + user_reset interface + + + + + + + RST + + + user_reset + + + + + + POLARITY + ACTIVE_HIGH + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + pcie4_pl + pcie4_pl + Physical Layer Interface + + + + + + + eq_in_progress + + + pl_eq_in_progress + + + + + eq_mismatch + + + pl_eq_mismatch + + + + + eq_phase + + + pl_eq_phase + + + + + gen2_upstream_prefer_deemph + + + pl_gen2_upstream_prefer_deemph + + + + + redo_eq + + + pl_redo_eq + + + + + redo_eq_pending + + + pl_redo_eq_pending + + + + + redo_eq_speed + + + pl_redo_eq_speed + + + + + + + false + + + + + + configure + configure + + + + + + + req_data + + + conf_req_data + + + + + req_ready + + + conf_req_ready + + + + + req_reg_num + + + conf_req_reg_num + + + + + req_type + + + conf_req_type + + + + + req_valid + + + conf_req_valid + + + + + resp_rdata + + + conf_resp_rdata + + + + + resp_valid + + + conf_resp_valid + + + + + + + false + + + + + + cap + cap + + + + + + + GNT + + + cap_gnt + + + + + REL + + + cap_rel + + + + + REQ + + + cap_req + + + + + + + false + + + + + + pcie4_ext_pipe_rp + pcie4_ext_pipe_rp + PCIE4 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_in + + + + + COMMANDS_OUT + + + common_commands_out + + + + + RX_0 + + + pipe_rx_0_sigs + + + + + RX_1 + + + pipe_rx_1_sigs + + + + + RX_2 + + + pipe_rx_2_sigs + + + + + RX_3 + + + pipe_rx_3_sigs + + + + + RX_4 + + + pipe_rx_4_sigs + + + + + RX_5 + + + pipe_rx_5_sigs + + + + + RX_6 + + + pipe_rx_6_sigs + + + + + RX_7 + + + pipe_rx_7_sigs + + + + + RX_8 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AXIS_CCIX_TX_TUSER_WIDTH + CCIX Tx User Width + 47 + + + ARI_CAP_ENABLE + Ari Cap Enable + FALSE + + + PF0_ARI_CAP_NEXT_FUNC + Pf0 ARI Cap Next Func + 0x00 + + + PF1_ARI_CAP_NEXT_FUNC + Pf1 ARI Cap Next Func + 0x00 + + + PF2_ARI_CAP_NEXT_FUNC + Pf2 ARI Cap Next Func + 0x00 + + + PF3_ARI_CAP_NEXT_FUNC + Pf3 ARI Cap Next Func + 0x00 + + + AXISTEN_IF_CC_ALIGNMENT_MODE + Axisten If Cc Alignment Mode + 0x1 + + + AXISTEN_IF_CQ_ALIGNMENT_MODE + Axisten If Cq Alignment Mode + 0x1 + + + AXISTEN_IF_RC_ALIGNMENT_MODE + Axisten If Rc Alignment Mode + 0x0 + + + AXISTEN_IF_RQ_ALIGNMENT_MODE + Axisten If Rq Alignment Mode + 0x0 + + + AXISTEN_IF_EXT_512_CQ_STRADDLE + Axisten If CQ Straddle + FALSE + + + AXISTEN_IF_EXT_512_CC_STRADDLE + Axisten If CC Straddle + FALSE + + + AXISTEN_IF_EXT_512_RQ_STRADDLE + Axisten If RQ Straddle + FALSE + + + AXISTEN_IF_EXT_512_RC_STRADDLE + Axisten If RC Straddle + FALSE + + + AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE + Axisten If 512 4TLP/2TLP Rc Straddle + FALSE + + + AXISTEN_IF_RC_STRADDLE + Axisten If Rc Straddle + TRUE + + + PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE + Pf0 Aer Cap Ecrc Gen and Check Capable + FALSE + + + PF0_AER_CAP_NEXTPTR + Pf0 Aer Cap Nextptr + 0x1C0 + + + PF0_PCIE_CAP_NEXTPTR + pcie Nextptr + 0x000 + + + PF1_PCIE_CAP_NEXTPTR + pcie Nextptr + 0x000 + + + PF2_PCIE_CAP_NEXTPTR + pcie Nextptr + 0x000 + + + PF3_PCIE_CAP_NEXTPTR + pcie Nextptr + 0x000 + + + VF0_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR + vf0 ext space Nextptr + 0x000 + + + VF1_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR + vf1/ ext space Nextptr + 0x000 + + + VF2_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR + vf2 ext space Nextptr + 0x000 + + + VF3_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR + vf3 ext space Nextptr + 0x000 + + + PF0_ARI_CAP_NEXTPTR + Pf0 Ari Cap Nextptr + 0x1C0 + + + PF0_BAR0_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x009 + + + PF0_BAR0_CONTROL + Pf0 Bar0 Control + 0x4 + + + PF0_BAR1_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x000 + + + PF0_BAR1_CONTROL + Pf0 Bar1 Control + 0x0 + + + PF0_BAR2_APERTURE_SIZE + Pf0 Bar2 Aperture Size + 0x000 + + + PF0_BAR2_CONTROL + Pf0 Bar2 Control + 0x0 + + + PF0_BAR3_APERTURE_SIZE + Pf0 Bar3 Aperture Size + 0x000 + + + PF0_BAR3_CONTROL + Pf0 Bar3 Control + 0x0 + + + PF0_BAR4_APERTURE_SIZE + Pf0 Bar4 Aperture Size + 0x000 + + + PF0_BAR4_CONTROL + Pf0 Bar4 Control + 0x0 + + + PF0_BAR5_APERTURE_SIZE + Pf0 Bar5 Aperture Size + 0x000 + + + PF0_BAR5_CONTROL + Pf0 Bar5 Control + 0x0 + + + PF0_CAPABILITY_POINTER + Pf0 Capability Pointer + 0x40 + + + PF0_CLASS_CODE + Pf0 Class Code + 0x070001 + + + PF0_VENDOR_ID + Pf0 Vendor Id + 0x10EE + + + PF0_DEVICE_ID + Pf0 Device Id + 0x9038 + + + PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 128b Cas Atomic Completer Support + FALSE + + + PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 32b Atomic Completer Support + FALSE + + + PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 64b Atomic Completer Support + FALSE + + + PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT + Pf0 Dev Cap2 Tph Completer Support + FALSE + + + PF0_DEV_CAP_EXT_TAG_SUPPORTED + Pf0 Dev Cap Ext Tag Supported + TRUE + + + PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE + Pf0 Dev Cap Function Level Reset Capable + FALSE + + + PF0_DEV_CAP_MAX_PAYLOAD_SIZE + Pf0 Dev Cap Max Payload Size + 0x3 + + + DSN_CAP_ENABLE + Dsn Cap Enable + FALSE + + + PF0_VC_CAP_ENABLE + Vc Cap Enable + TRUE + + + PF0_DSN_CAP_NEXTPTR + Pf0 Dsn Cap Nextptr + 0x1C0 + + + PF0_EXPANSION_ROM_APERTURE_SIZE + Pf0 Expansion Rom Aperture Size + 0x000 + + + PF0_EXPANSION_ROM_ENABLE + Pf0 Expansion Rom Enable + FALSE + + + PF0_INTERRUPT_PIN + Pf0 Interrupt Pin + 0x1 + + + PF0_LINK_STATUS_SLOT_CLOCK_CONFIG + Pf0 Link Status Slot Clock Config + TRUE + + + PF0_MSIX_CAP_NEXTPTR + Pf0 Msix Cap Nextptr + 0x70 + + + PF0_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + PF0_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + PF0_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + PF0_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + PF0_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + PF0_MSI_CAP_MULTIMSGCAP + Pf0 Msi Cap Multimsgcap + 0 + + + PF0_MSI_CAP_NEXTPTR + Pf0 Msi Cap Nextptr + 0x70 + + + PF0_PM_CAP_NEXTPTR + Pf0 Pm Cap Nextptr + 0x48 + + + PF0_PM_CAP_PMESUPPORT_D0 + Pf0 Pm Cap Pmesupport D0 + FALSE + + + PF0_PM_CAP_PMESUPPORT_D1 + Pf0 Pm Cap Pmesupport D1 + FALSE + + + PF0_PM_CAP_PMESUPPORT_D3HOT + Pf0 Pm Cap Pmesupport D3hot + FALSE + + + PF0_PM_CAP_SUPP_D1_STATE + Pf0 Pm Cap Supp D1 State + FALSE + + + PF0_REVISION_ID + Pf0 Revision Id + 0x00 + + + PF0_SRIOV_BAR0_APERTURE_SIZE + Pf0 Sriov Bar0 Aperture Size + 0x00 + + + PF0_SRIOV_BAR0_CONTROL + Pf0 Sriov Bar0 Control + 0x0 + + + PF0_SRIOV_BAR1_APERTURE_SIZE + Pf0 Sriov Bar1 Aperture Size + 0x00 + + + PF0_SRIOV_BAR1_CONTROL + Pf0 Sriov Bar1 Control + 0x0 + + + PF0_SRIOV_BAR2_APERTURE_SIZE + Pf0 Sriov Bar2 Aperture Size + 0x00 + + + PF0_SRIOV_BAR2_CONTROL + Pf0 Sriov Bar2 Control + 0x0 + + + PF0_SRIOV_BAR3_APERTURE_SIZE + Pf0 Sriov Bar3 Aperture Size + 0x00 + + + PF0_SRIOV_BAR3_CONTROL + Pf0 Sriov Bar3 Control + 0x0 + + + PF0_SRIOV_BAR4_APERTURE_SIZE + Pf0 Sriov Bar4 Aperture Size + 0x00 + + + PF0_SRIOV_BAR4_CONTROL + Pf0 Sriov Bar4 Control + 0x0 + + + PF0_SRIOV_BAR5_APERTURE_SIZE + Pf0 Sriov Bar5 Aperture Size + 0x00 + + + PF0_SRIOV_BAR5_CONTROL + Pf0 Sriov Bar5 Control + 0x0 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0x0000 + + + PF0_SRIOV_CAP_NEXTPTR + Pf0 Sriov Cap Nextptr + 0x1F0 + + + PF0_SRIOV_CAP_TOTAL_VF + Pf0 Sriov Cap Total Vf + 0x0000 + + + PF0_SRIOV_CAP_VER + Pf0 Sriov Cap Ver + 0x1 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 0x0000 + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0x0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 0x00000553 + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0x0000 + + + PF0_SUBSYSTEM_VENDOR_ID + Pf0 Subsystem Vendor Id + 0x10EE + + + PF0_SUBSYSTEM_ID + Pf0 Subsystem Id + 0x0007 + + + PF0_TPHR_CAP_ENABLE + Pf0 Tphr Cap Enable + FALSE + + + PF0_TPHR_CAP_NEXTPTR + Pf0 Tphr Cap Nextptr + 0x000 + + + PF0_TPHR_CAP_ST_MODE_SEL + Pf0 Tphr Cap St Mode Sel + 0x0 + + + PF0_TPHR_CAP_ST_TABLE_LOC + Pf0 Tphr Cap St Table Loc + 0x0 + + + PF0_TPHR_CAP_ST_TABLE_SIZE + Pf0 Tphr Cap St Table Size + 0x000 + + + PF0_TPHR_CAP_VER + Pf0 Tphr Cap Ver + 0x1 + + + PF1_TPHR_CAP_ST_MODE_SEL + Pf1 Tphr Cap St Mode Sel + 0x0 + + + PF2_TPHR_CAP_ST_MODE_SEL + Pf2 Tphr Cap St Mode Sel + 0x0 + + + PF3_TPHR_CAP_ST_MODE_SEL + Pf3 Tphr Cap St Mode Sel + 0x0 + + + PF0_TPHR_CAP_DEV_SPECIFIC_MODE + Pf0 Tphr Cap Dev Specific Mode + TRUE + + + PF0_TPHR_CAP_INT_VEC_MODE + Pf0 Tphr Cap Int Vec Mode + FALSE + + + PF0_SECONDARY_PCIE_CAP_NEXTPTR + Secondary Pcie Extended Capability Nextptr + 0x1F0 + + + MCAP_CAP_NEXTPTR + MCAP Cap Nextptr + 0x000 + + + PF0_VC_CAP_NEXTPTR + Pf0 Vc Cap Nextptr + 0x000 + + + SPARE_WORD1 + Secondary Pcie Extended Capability Nextptr + 0x00000000 + + + PF1_AER_CAP_NEXTPTR + Pf1 Aer Cap Nextptr + 0x000 + + + PF1_ARI_CAP_NEXTPTR + Pf1 Ari Cap Nextptr + 0x000 + + + PF1_BAR0_APERTURE_SIZE + Pf1 Bar0 Aperture Size + 0x009 + + + PF1_BAR0_CONTROL + Pf1 Bar0 Control + 0x4 + + + PF1_BAR1_APERTURE_SIZE + Pf1 Bar1 Aperture Size + 0x000 + + + PF1_BAR1_CONTROL + Pf1 Bar1 Control + 0x0 + + + PF1_BAR2_APERTURE_SIZE + Pf1 Bar2 Aperture Size + 0x000 + + + PF1_BAR2_CONTROL + Pf1 Bar2 Control + 0x0 + + + PF1_BAR3_APERTURE_SIZE + Pf1 Bar3 Aperture Size + 0x000 + + + PF1_BAR3_CONTROL + Pf1 Bar3 Control + 0x0 + + + PF1_BAR4_APERTURE_SIZE + Pf1 Bar4 Aperture Size + 0x000 + + + PF1_BAR4_CONTROL + Pf1 Bar4 Control + 0x0 + + + PF1_BAR5_APERTURE_SIZE + Pf1 Bar5 Aperture Size + 0x000 + + + PF1_BAR5_CONTROL + Pf1 Bar5 Control + 0x0 + + + PF1_CAPABILITY_POINTER + Pf1 Capability Pointer + 0x40 + + + PF1_CLASS_CODE + Pf1 Class Code + 0x058000 + + + PF1_DEVICE_ID + Pf1 Device Id + 0x9011 + + + PF1_DEV_CAP_MAX_PAYLOAD_SIZE + Pf1 Dev Cap Max Payload Size + 0x3 + + + PF1_DSN_CAP_NEXTPTR + Pf1 Dsn Cap Nextptr + 0x000 + + + PF1_EXPANSION_ROM_APERTURE_SIZE + Pf1 Expansion Rom Aperture Size + 0x000 + + + PF1_EXPANSION_ROM_ENABLE + Pf1 Expansion Rom Enable + FALSE + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + 0x0 + + + PF1_MSIX_CAP_NEXTPTR + Pf1 Msix Cap Nextptr + 0x70 + + + PF1_MSIX_CAP_PBA_BIR + Pf1 Msix Cap Pba Bir + 0 + + + PF1_MSIX_CAP_PBA_OFFSET + Pf1 Msix Cap Pba Offset + 0x00000000 + + + PF1_MSIX_CAP_TABLE_BIR + Pf1 Msix Cap Table Bir + 0 + + + PF1_MSIX_CAP_TABLE_OFFSET + Pf1 Msix Cap Table Offset + 0x00000000 + + + PF1_MSIX_CAP_TABLE_SIZE + Pf1 Msix Cap Table Size + 0x000 + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 0 + + + PF1_MSI_CAP_NEXTPTR + Pf1 Msi Cap Nextptr + 0x70 + + + PF1_PM_CAP_NEXTPTR + Pf1 Pm Cap Nextptr + 0x70 + + + PF1_REVISION_ID + Pf1 Revision Id + 0x00 + + + PF1_SRIOV_BAR0_APERTURE_SIZE + Pf1 Sriov Bar0 Aperture Size + 0x00 + + + PF1_SRIOV_BAR0_CONTROL + Pf1 Sriov Bar0 Control + 0x0 + + + PF1_SRIOV_BAR1_APERTURE_SIZE + Pf1 Sriov Bar1 Aperture Size + 0x00 + + + PF1_SRIOV_BAR1_CONTROL + Pf1 Sriov Bar1 Control + 0x0 + + + PF1_SRIOV_BAR2_APERTURE_SIZE + Pf1 Sriov Bar2 Aperture Size + 0x00 + + + PF1_SRIOV_BAR2_CONTROL + Pf1 Sriov Bar2 Control + 0x0 + + + PF1_SRIOV_BAR3_APERTURE_SIZE + Pf1 Sriov Bar3 Aperture Size + 0x00 + + + PF1_SRIOV_BAR3_CONTROL + Pf1 Sriov Bar3 Control + 0x0 + + + PF1_SRIOV_BAR4_APERTURE_SIZE + Pf1 Sriov Bar4 Aperture Size + 0x00 + + + PF1_SRIOV_BAR4_CONTROL + Pf1 Sriov Bar4 Control + 0x0 + + + PF1_SRIOV_BAR5_APERTURE_SIZE + Pf1 Sriov Bar5 Aperture Size + 0x00 + + + PF1_SRIOV_BAR5_CONTROL + Pf1 Sriov Bar5 Control + 0x0 + + + PF1_SRIOV_CAP_INITIAL_VF + Pf1 Sriov Cap Initial Vf + 0x0000 + + + PF1_SRIOV_CAP_NEXTPTR + Pf1 Sriov Cap Nextptr + 0x000 + + + PF1_SRIOV_CAP_TOTAL_VF + Pf1 Sriov Cap Total Vf + 0x0000 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 0x1 + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + 0x0000 + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0x0001 + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 0x00000553 + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0x0000 + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0x0007 + + + PF1_TPHR_CAP_NEXTPTR + Pf1 Tphr Cap Nextptr + 0x000 + + + PF2_AER_CAP_NEXTPTR + Pf2 Aer Cap Nextptr + 0x000 + + + PF2_ARI_CAP_NEXTPTR + Pf2 Ari Cap Nextptr + 0x000 + + + PF2_BAR0_APERTURE_SIZE + Pf2 Bar0 Aperture Size + 0x009 + + + PF2_BAR0_CONTROL + Pf2 Bar0 Control + 0x4 + + + PF2_BAR1_APERTURE_SIZE + Pf2 Bar1 Aperture Size + 0x000 + + + PF2_BAR1_CONTROL + Pf2 Bar1 Control + 0x0 + + + PF2_BAR2_APERTURE_SIZE + Pf2 Bar2 Aperture Size + 0x000 + + + PF2_BAR2_CONTROL + Pf2 Bar2 Control + 0x0 + + + PF2_BAR3_APERTURE_SIZE + Pf2 Bar3 Aperture Size + 0x000 + + + PF2_BAR3_CONTROL + Pf2 Bar3 Control + 0x0 + + + PF2_BAR4_APERTURE_SIZE + Pf2 Bar4 Aperture Size + 0x000 + + + PF2_BAR4_CONTROL + Pf2 Bar4 Control + 0x0 + + + PF2_BAR5_APERTURE_SIZE + Pf2 Bar5 Aperture Size + 0x000 + + + PF2_BAR5_CONTROL + Pf2 Bar5 Control + 0x0 + + + PF2_CAPABILITY_POINTER + Pf2 Capability Pointer + 0x40 + + + PF2_CLASS_CODE + Pf2 Class Code + 0x058000 + + + PF2_DEVICE_ID + Pf2 Device Id + 0x9438 + + + PF2_DEV_CAP_MAX_PAYLOAD_SIZE + Pf2 Dev Cap Max Payload Size + 0x3 + + + PF2_DSN_CAP_NEXTPTR + Pf2 Dsn Cap Nextptr + 0x000 + + + PF2_EXPANSION_ROM_APERTURE_SIZE + Pf2 Expansion Rom Aperture Size + 0x000 + + + PF2_EXPANSION_ROM_ENABLE + Pf2 Expansion Rom Enable + FALSE + + + PF2_INTERRUPT_PIN + Pf2 Interrupt Pin + 0x0 + + + PF2_MSIX_CAP_NEXTPTR + Pf2 Msix Cap Nextptr + 0x70 + + + PF2_MSIX_CAP_PBA_BIR + Pf2 Msix Cap Pba Bir + 0 + + + PF2_MSIX_CAP_PBA_OFFSET + Pf2 Msix Cap Pba Offset + 0x00000000 + + + PF2_MSIX_CAP_TABLE_BIR + Pf2 Msix Cap Table Bir + 0 + + + PF2_MSIX_CAP_TABLE_OFFSET + Pf2 Msix Cap Table Offset + 0x00000000 + + + PF2_MSIX_CAP_TABLE_SIZE + Pf2 Msix Cap Table Size + 0x000 + + + PF2_MSI_CAP_MULTIMSGCAP + Pf2 Msi Cap Multimsgcap + 0 + + + PF2_MSI_CAP_NEXTPTR + Pf2 Msi Cap Nextptr + 0x70 + + + PF2_PM_CAP_NEXTPTR + Pf2 Pm Cap Nextptr + 0x70 + + + PF2_REVISION_ID + Pf2 Revision Id + 0x00 + + + PF2_SRIOV_BAR0_APERTURE_SIZE + Pf2 Sriov Bar0 Aperture Size + 0x00 + + + PF2_SRIOV_BAR0_CONTROL + Pf2 Sriov Bar0 Control + 0x0 + + + PF2_SRIOV_BAR1_APERTURE_SIZE + Pf2 Sriov Bar1 Aperture Size + 0x00 + + + PF2_SRIOV_BAR1_CONTROL + Pf2 Sriov Bar1 Control + 0x0 + + + PF2_SRIOV_BAR2_APERTURE_SIZE + Pf2 Sriov Bar2 Aperture Size + 0x00 + + + PF2_SRIOV_BAR2_CONTROL + Pf2 Sriov Bar2 Control + 0x0 + + + PF2_SRIOV_BAR3_APERTURE_SIZE + Pf2 Sriov Bar3 Aperture Size + 0x00 + + + PF2_SRIOV_BAR3_CONTROL + Pf2 Sriov Bar3 Control + 0x0 + + + PF2_SRIOV_BAR4_APERTURE_SIZE + Pf2 Sriov Bar4 Aperture Size + 0x00 + + + PF2_SRIOV_BAR4_CONTROL + Pf2 Sriov Bar4 Control + 0x0 + + + PF2_SRIOV_BAR5_APERTURE_SIZE + Pf2 Sriov Bar5 Aperture Size + 0x00 + + + PF2_SRIOV_BAR5_CONTROL + Pf2 Sriov Bar5 Control + 0x0 + + + PF2_SRIOV_CAP_INITIAL_VF + Pf2 Sriov Cap Initial Vf + 0x0000 + + + PF2_SRIOV_CAP_NEXTPTR + Pf2 Sriov Cap Nextptr + 0x000 + + + PF2_SRIOV_CAP_TOTAL_VF + Pf2 Sriov Cap Total Vf + 0x0000 + + + PF2_SRIOV_CAP_VER + Pf2 Sriov Cap Ver + 0x1 + + + PF2_SRIOV_FIRST_VF_OFFSET + Pf2 Sriov First Vf Offset + 0x0000 + + + PF2_SRIOV_FUNC_DEP_LINK + Pf2 Sriov Func Dep Link + 0x0002 + + + PF2_SRIOV_SUPPORTED_PAGE_SIZE + Pf2 Sriov Supported Page Size + 0x00000553 + + + PF2_SRIOV_VF_DEVICE_ID + Pf2 Sriov Vf Device Id + 0x0000 + + + PF2_SUBSYSTEM_ID + Pf2 Subsystem Id + 0x0007 + + + PF2_TPHR_CAP_NEXTPTR + Pf2 Tphr Cap Nextptr + 0x000 + + + PF3_AER_CAP_NEXTPTR + Pf3 Aer Cap Nextptr + 0x000 + + + PF3_ARI_CAP_NEXTPTR + Pf3 Ari Cap Nextptr + 0x000 + + + PF3_BAR0_APERTURE_SIZE + Pf3 Bar0 Aperture Size + 0x009 + + + PF3_BAR0_CONTROL + Pf3 Bar0 Control + 0x4 + + + PF3_BAR1_APERTURE_SIZE + Pf3 Bar1 Aperture Size + 0x000 + + + PF3_BAR1_CONTROL + Pf3 Bar1 Control + 0x0 + + + PF3_BAR2_APERTURE_SIZE + Pf3 Bar2 Aperture Size + 0x000 + + + PF3_BAR2_CONTROL + Pf3 Bar2 Control + 0x0 + + + PF3_BAR3_APERTURE_SIZE + Pf3 Bar3 Aperture Size + 0x000 + + + PF3_BAR3_CONTROL + Pf3 Bar3 Control + 0x0 + + + PF3_BAR4_APERTURE_SIZE + Pf3 Bar4 Aperture Size + 0x000 + + + PF3_BAR4_CONTROL + Pf3 Bar4 Control + 0x0 + + + PF3_BAR5_APERTURE_SIZE + Pf3 Bar5 Aperture Size + 0x000 + + + PF3_BAR5_CONTROL + Pf3 Bar5 Control + 0x0 + + + PF3_CAPABILITY_POINTER + Pf3 Capability Pointer + 0x40 + + + PF3_CLASS_CODE + Pf3 Class Code + 0x058000 + + + PF3_DEVICE_ID + Pf3 Device Id + 0x9638 + + + PF3_DEV_CAP_MAX_PAYLOAD_SIZE + Pf3 Dev Cap Max Payload Size + 0x3 + + + PF3_DSN_CAP_NEXTPTR + Pf3 Dsn Cap Nextptr + 0x000 + + + PF3_EXPANSION_ROM_APERTURE_SIZE + Pf3 Expansion Rom Aperture Size + 0x000 + + + PF3_EXPANSION_ROM_ENABLE + Pf3 Expansion Rom Enable + FALSE + + + PF3_INTERRUPT_PIN + Pf3 Interrupt Pin + 0x0 + + + PF3_MSIX_CAP_NEXTPTR + Pf3 Msix Cap Nextptr + 0x70 + + + PF3_MSIX_CAP_PBA_BIR + Pf3 Msix Cap Pba Bir + 0 + + + PF3_MSIX_CAP_PBA_OFFSET + Pf3 Msix Cap Pba Offset + 0x00000000 + + + PF3_MSIX_CAP_TABLE_BIR + Pf3 Msix Cap Table Bir + 0 + + + PF3_MSIX_CAP_TABLE_OFFSET + Pf3 Msix Cap Table Offset + 0x00000000 + + + PF3_MSIX_CAP_TABLE_SIZE + Pf3 Msix Cap Table Size + 0x000 + + + PF3_MSI_CAP_MULTIMSGCAP + Pf3 Msi Cap Multimsgcap + 0 + + + PF3_MSI_CAP_NEXTPTR + Pf3 Msi Cap Nextptr + 0x70 + + + PF3_PM_CAP_NEXTPTR + Pf3 Pm Cap Nextptr + 0x70 + + + PF3_REVISION_ID + Pf3 Revision Id + 0x00 + + + PF3_SRIOV_BAR0_APERTURE_SIZE + Pf3 Sriov Bar0 Aperture Size + 0x00 + + + PF3_SRIOV_BAR0_CONTROL + Pf3 Sriov Bar0 Control + 0x0 + + + PF3_SRIOV_BAR1_APERTURE_SIZE + Pf3 Sriov Bar1 Aperture Size + 0x00 + + + PF3_SRIOV_BAR1_CONTROL + Pf3 Sriov Bar1 Control + 0x0 + + + PF3_SRIOV_BAR2_APERTURE_SIZE + Pf3 Sriov Bar2 Aperture Size + 0x00 + + + PF3_SRIOV_BAR2_CONTROL + Pf3 Sriov Bar2 Control + 0x0 + + + PF3_SRIOV_BAR3_APERTURE_SIZE + Pf3 Sriov Bar3 Aperture Size + 0x00 + + + PF3_SRIOV_BAR3_CONTROL + Pf3 Sriov Bar3 Control + 0x0 + + + PF3_SRIOV_BAR4_APERTURE_SIZE + Pf3 Sriov Bar4 Aperture Size + 0x00 + + + PF3_SRIOV_BAR4_CONTROL + Pf3 Sriov Bar4 Control + 0x0 + + + PF3_SRIOV_BAR5_APERTURE_SIZE + Pf3 Sriov Bar5 Aperture Size + 0x00 + + + PF3_SRIOV_BAR5_CONTROL + Pf3 Sriov Bar5 Control + 0x0 + + + PF3_SRIOV_CAP_INITIAL_VF + Pf3 Sriov Cap Initial Vf + 0x0000 + + + PF3_SRIOV_CAP_NEXTPTR + Pf3 Sriov Cap Nextptr + 0x000 + + + PF3_SRIOV_CAP_TOTAL_VF + Pf3 Sriov Cap Total Vf + 0x0000 + + + PF3_SRIOV_CAP_VER + Pf3 Sriov Cap Ver + 0x1 + + + PF3_SRIOV_FIRST_VF_OFFSET + Pf3 Sriov First Vf Offset + 0x0000 + + + PF3_SRIOV_FUNC_DEP_LINK + Pf3 Sriov Func Dep Link + 0x0003 + + + PF3_SRIOV_SUPPORTED_PAGE_SIZE + Pf3 Sriov Supported Page Size + 0x00000553 + + + PF3_SRIOV_VF_DEVICE_ID + Pf3 Sriov Vf Device Id + 0x0000 + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0x0007 + + + PF3_TPHR_CAP_NEXTPTR + Pf3 Tphr Cap Nextptr + 0x000 + + + PL_UPSTREAM_FACING + Pl Upstream Facing + TRUE + + + PL_DISABLE_LANE_REVERSAL + Pl Disable Lane Reversal + TRUE + + + PF0_MSI_CAP_PERVECMASKCAP + en pf0 msi per vec masking + FALSE + + + PF1_MSI_CAP_PERVECMASKCAP + en pf1 msi per vec masking + FALSE + + + PF2_MSI_CAP_PERVECMASKCAP + en pf2 msi per vec masking + FALSE + + + PF3_MSI_CAP_PERVECMASKCAP + en pf3 msi per vec masking + FALSE + + + SRIOV_CAP_ENABLE + Sriov Cap Enable + 0x1 + + + TL_CREDITS_CD + Tl Credits Cd + 0x000 + + + TL_CREDITS_CH + Tl Credits Ch + 0x00 + + + TL_CREDITS_NPD + Tl Credits Npd + 0x004 + + + TL_CREDITS_NPH + Tl Credits Nph + 0x20 + + + TL_CREDITS_PD + Tl Credits Pd + 0x3E0 + + + TL_CREDITS_PH + Tl Credits Ph + 0x20 + + + EXTENDED_CFG_EXTEND_INTERFACE_ENABLE + Tl Extended Cfg Extend Interface Enable + FALSE + + + EXT_XVC_VSEC_ENABLE + Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design + FALSE + + + LEGACY_CFG_EXTEND_INTERFACE_ENABLE + FALSE + + + ACS_EXT_CAP_ENABLE + FALSE + + + ACS_CAP_NEXTPTR + 0x000 + + + PDVSEC_NEXTPTR + 0x000 + + + TL_LEGACY_MODE_ENABLE + Tl Legacy Mode Enable + FALSE + + + TL_PF_ENABLE_REG + 0 + + + VF0_CAPABILITY_POINTER + Vf0 Capability Pointer + 0x70 + + + TL_COMPLETION_RAM_SIZE + Completion Space + 0x2 + + + gen_x0y0_xdc + Generate X0Y0 XDC + 0 + + + gen_x0y1_xdc + Generate X0Y1 XDC + 0 + + + gen_x0y2_xdc + Generate X0Y2 XDC + 0 + + + gen_x0y3_xdc + Generate X0Y3 XDC + 0 + + + gen_x0y4_xdc + Generate X0Y4 XDC + 0 + + + gen_x0y5_xdc + Generate X0Y5 XDC + 0 + + + gen_x0y6_xdc + Generate X0Y6 XDC + 0 + + + gen_x0y7_xdc + Generate X0Y7 XDC + 0 + + + gen_x1y0_xdc + Generate X1Y0 XDC + 0 + + + gen_x1y1_xdc + Generate X1Y1 XDC + 0 + + + gen_x1y2_xdc + Generate X1Y2 XDC + 0 + + + gen_x1y3_xdc + Generate X1Y3 XDC + 0 + + + gen_x1y4_xdc + Generate X1Y4 XDC + 0 + + + gen_x1y5_xdc + Generate X1Y5 XDC + 0 + + + xlnx_ref_board + Xlnx Ref Board + AU50 + + + pcie_blk_locn + Pcie Blk Locn + 6 + + + PIPE_SIM + FALSE + + + AXISTEN_IF_ENABLE_CLIENT_TAG + TRUE + + + PCIE_FAST_CONFIG + PCIE FAST CONFIG + NONE + + + EXT_STARTUP_PRIMITIVE + EXT STARTUP PRIMITIVE + FALSE + + + PL_INTERFACE + PL INTERFACE + FALSE + + + PCIE_CONFIGURATION + PCIE CONFIGURATION + FALSE + + + CFG_STATUS_IF + TRUE + + + TX_FC_IF + TRUE + + + CFG_EXT_IF + FALSE + + + CFG_FC_IF + TRUE + + + PER_FUNC_STATUS_IF + TRUE + + + CFG_MGMT_IF + TRUE + + + RCV_MSG_IF + TRUE + + + CFG_TX_MSG_IF + TRUE + + + CFG_CTL_IF + TRUE + + + CFG_PM_IF + TRUE + + + PCIE_ID_IF + FALSE + + + MSI_EN + TRUE + + + MSIX_EN + FALSE + + + PCIE4_DRP + FALSE + + + DIS_GT_WIZARD + FALSE + + + BMD_PIO_MODE + FALSE + + + SRIOV_EXD_MODE + FALSE + + + DBG_CHECKER + FALSE + + + ENABLE_IBERT + FALSE + + + GEN4_EIEOS_0S7 + TRUE + + + ENABLE_JTAG_DBG + FALSE + + + ENABLE_LTSSM_DBG + FALSE + + + TWO_PORT_SWITCH + FALSE + + + TWO_PORT_CONFIG + X8G3 + + + TRANSCEIVER_CTRL_STATUS_PORTS + FALSE + + + SHARED_LOGIC + 1 + + + GTWIZ_IN_CORE + 1 + + + GTCOM_IN_CORE + 2 + + + AXISTEN_IF_RX_PARITY_EN + FALSE + + + AXISTEN_IF_TX_PARITY_EN + FALSE + + + AXISTEN_IF_MSIX_RX_PARITY_EN + FALSE + + + LL_TX_TLP_PARITY_CHK + FALSE + + + LL_RX_TLP_PARITY_GEN + FALSE + + + TL2CFG_IF_PARITY_CHK + FALSE + + + AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE + FALSE + + + DEDICATE_PERST + FALSE + + + SYS_RESET_POLARITY + 0 + + + MCAP_ENABLEMENT + NONE + + + MCAP_FPGA_BITSTREAM_VERSION + MCAP Bitstream Version Register Value + 0x00000000 + + + EXT_CH_GT_DRP + FALSE + + + EN_GT_SELECTION + FALSE + + + SELECT_QUAD + GTY_Quad_227 + + + silicon_revision + Silicon Revision + Beta + + + DEV_PORT_TYPE + 0 + + + VFG0_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG0_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG0_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG0_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG0_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + VFG1_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG1_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG1_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG1_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG1_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + VFG2_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG2_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG2_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG2_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG2_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + VFG3_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG3_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG3_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG3_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG3_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + EN_PARITY + FALSE + + + INS_LOSS_PROFILE + ADD-IN_CARD + + + MSI_X_OPTIONS + None + + + COMPLETER_MODEL + FALSE + + + DBG_DESCRAMBLE_EN + FALSE + + + PIPE_DEBUG_EN + FALSE + + + MSI_INT + MSI Ints + 32 + + + VU9P_BOARD + FALSE + + + PHY_LP_TXPRESET + 4 + + + IS_BOARD_PROJECT + Is Board Flow Enabled + 1 + + + GT_DRP_CLK_SRC + GT DRP Clk Source + 0 + + + FREE_RUN_FREQ + Free Run Freq + 1 + + + PM_ENABLE_L23_ENTRY + FALSE + + + AWS_MODE_VALUE + aws mode value + 0 + + + AXISTEN_IF_CCIX_RX_CREDIT_LIMIT + Ccix Rx Credit Limit + 0x08 + + + AXISTEN_IF_CCIX_TX_CREDIT_LIMIT + Ccix Tx Credit Limit + 0x08 + + + AXISTEN_IF_CCIX_TX_REGISTERED_TREADY + Ccix Tx Tready Registered + FALSE + + + CCIX_DIRECT_ATTACH_MODE + Ccix Direct Attach Mode + FALSE + + + CCIX_ENABLE + Ccix Enable + FALSE + + + THREE_PORT_SWITCH + FALSE + + + CCIX_DVSEC + Ccix Dvsec Enable + FALSE + + + CCIX_VENDOR_ID + Pf0 Vendor Id + 0x1E2C + + + PF0_ATS_CAP_INV_QUEUE_DEPTH + Pf0 Ats Cap Inv Queue Depth + 0x00 + + + PF0_ATS_CAP_NEXTPTR + Pf0 Ats Cap Next Ptr + 0x000 + + + PF0_ATS_CAP_ON + Pf0 Ats Cap On + FALSE + + + PF0_PRI_CAP_NEXTPTR + Pf0 Pri Cap Next Ptr + 0x000 + + + PF0_PRI_CAP_ON + Pf0 Pri Cap On + FALSE + + + PF0_PRI_OST_PR_CAPACITY + Pf0 Pri Ost Pr Capacity + 0x00000000 + + + PF0_VC_ARB_CAPABILITY + Pf0 Vc Arb Capability + 0x0 + + + PF0_VC_ARB_TBL_OFFSET + Pf0 Vc Arb Tbl Offset + 0x31 + + + PF0_VC_EXTENDED_COUNT + Pf0 Vc Extended Count + FALSE + + + PF0_VC_LOW_PRIORITY_EXTENDED_COUNT + Pf0 Vc Low Priority Extended Count + FALSE + + + PF1_ATS_CAP_INV_QUEUE_DEPTH + Pf1 Ats Cap Inv Queue Depth + 0x00 + + + PF1_ATS_CAP_NEXTPTR + Pf1 Ats Cap Next Ptr + 0x000 + + + PF1_ATS_CAP_ON + Pf1 Ats Cap On + FALSE + + + PF1_PRI_CAP_NEXTPTR + Pf1 Pri Cap Next Ptr + 0x000 + + + PF1_PRI_CAP_ON + Pf1 Pri Cap ON + FALSE + + + PF1_PRI_OST_PR_CAPACITY + Pf1 Pri Ost Pr Capacity + 0x00000000 + + + PF2_ATS_CAP_INV_QUEUE_DEPTH + Pf2 Ats Cap Inv Queue Depth + 0x00 + + + PF2_ATS_CAP_NEXTPTR + Pf2 Ats Cap Next Ptr + 0x000 + + + PF2_ATS_CAP_ON + Pf2 Ats Cap On + FALSE + + + PF2_PRI_CAP_NEXTPTR + Pf2 Pri Cap Next Ptr + 0x000 + + + PF2_PRI_CAP_ON + Pf2 Pri Cap On + FALSE + + + PF2_PRI_OST_PR_CAPACITY + Pf2 Pri Ost Pr Capacity + 0x00000000 + + + PF3_ATS_CAP_INV_QUEUE_DEPTH + Pf3 Ats Cap Inv Queue Depth + 0x00 + + + PF3_ATS_CAP_NEXTPTR + Pf3 Ats Cap Next Ptr + 0x000 + + + PF3_ATS_CAP_ON + Pf3 Ats Cap On + FALSE + + + PF3_PRI_CAP_NEXTPTR + Pf3 Pri Cap Next Ptr + 0x000 + + + PF3_PRI_CAP_ON + Pf3 Pri Cap On + FALSE + + + PF3_PRI_OST_PR_CAPACITY + Pf3 Pri Ost Pr Capacity + 0x00000000 + + + PL_CTRL_SKP_GEN_ENABLE + Pl Ctrl Skp Gen Enable + FALSE + + + PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE + Pl Ctrl Skp Parity And Crc Check Disable + TRUE + + + PL_USER_SPARE2 + Pl User Spare2 + 0x0000 + + + TL_CREDITS_CD_VC1 + Tl Credits Cd Vc1 + 0x000 + + + TL_CREDITS_CH_VC1 + Tl Credits Ch Vc1 + 0x00 + + + TL_CREDITS_NPD_VC1 + Tl Credits Npd Vc1 + 0x000 + + + TL_CREDITS_NPH_VC1 + Tl Credits Nph Vc1 + 0x01 + + + TL_CREDITS_PD_VC1 + Tl Credits Pd Vc1 + 0x1C0 + + + TL_CREDITS_PH_VC1 + Tl Credits Ph Vc1 + 0x40 + + + TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1 + Tl Fc update Min Interval Time Vc1 + 0x02 + + + TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1 + Tl Fc Update Min Internal Tlp Count Vc1 + 0x04 + + + TL_FEATURE_ENABLE_FC_SCALING + Tl Feature Enable Fc Scaling + FALSE + + + VFG0_ATS_CAP_INV_QUEUE_DEPTH + Vfg0 Ats Cap Inv Queue Depth + 0x00 + + + VFG0_ATS_CAP_NEXTPTR + Vfg0 Ats Cap Next Ptr + 0x000 + + + VFG0_ATS_CAP_ON + Vfg0 Ats Cap On + FALSE + + + VFG1_ATS_CAP_INV_QUEUE_DEPTH + Vfg1 Ats Cap Inv Queue Depth + 0x00 + + + VFG1_ATS_CAP_NEXTPTR + Vfg1 Ats Cap Next Ptr + 0x000 + + + VFG1_ATS_CAP_ON + Vfg1 Ats Cap On + FALSE + + + VFG2_ATS_CAP_INV_QUEUE_DEPTH + Vfg2 Ats Cap Inv Queue Depth + 0x00 + + + VFG2_ATS_CAP_NEXTPTR + Vfg2 Ats Cap Next Ptr + 0x000 + + + VFG2_ATS_CAP_ON + Vfg2 Ats Cap On + FALSE + + + VFG3_ATS_CAP_INV_QUEUE_DEPTH + Vfg3 Ats Cap Inv Queue Depth + 0x00 + + + VFG3_ATS_CAP_NEXTPTR + Vfg3 Ats Cap Next Ptr + 0x000 + + + VFG3_ATS_CAP_ON + Vfg3 Ats Cap On + FALSE + + + EXT_SYS_CLK_BUFG + FALSE + + + AXISTEN_IF_ENABLE_MSG_ROUTE + 0x20000 + + + GT_TYPE + GTY + + + TX_RX_MASTER_CHANNEL + X1Y15 + + + X1_CH_EN + X1Y15 + + + X2_CH_EN + X1Y15 X1Y14 + + + X4_CH_EN + X1Y15 X1Y14 X1Y13 X1Y12 + + + X8_CH_EN + X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 + + + XS_CH_EN + X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 X1Y7 X1Y6 X1Y5 X1Y4 X1Y3 X1Y2 X1Y1 X1Y0 + + + ENABLE_MORE + FALSE + + + DISABLE_BRAM_PIPELINE + FALSE + + + DISABLE_EQ_SYNCHRONIZER + FALSE + + + ENABLE_AUTO_RXEQ + FALSE + + + ENABLE_MULTIPF_AER + multi pf aer fix + FALSE + + + RBAR_ENABLE + FALSE + + + PF0_RBAR_CAP_BAR0_UPPER + PF0 Resizable BAR0 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR0_LOWER + PF0 Resizable BAR0 Capability lower 32 bits + 0x0000fff0 + + + PF0_RBAR_CAP_BAR1_UPPER + PF0 Resizable BAR1 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR1_LOWER + PF0 Resizable BAR1 Capability lower 32 bits + 0x00000000 + + + PF0_RBAR_CAP_BAR2_UPPER + PF0 Resizable BAR2 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR2_LOWER + PF0 Resizable BAR2 Capability lower 32 bits + 0x00000000 + + + PF0_RBAR_CAP_BAR3_UPPER + PF0 Resizable BAR3 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR3_LOWER + PF0 Resizable BAR3 Capability lower 32 bits + 0x00000000 + + + PF0_RBAR_CAP_BAR4_UPPER + PF0 Resizable BAR4 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR4_LOWER + PF0 Resizable BAR4 Capability lower 32 bits + 0x00000000 + + + PF0_RBAR_CAP_BAR5_UPPER + PF0 Resizable BAR5 Capability upper 16 bits + 0x0000 + + + PF0_RBAR_CAP_BAR5_LOWER + PF0 Resizable BAR5 Capability lower 32 bits + 0x00000000 + + + PF1_RBAR_CAP_BAR0_UPPER + PF1 Resizable BAR0 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR0_LOWER + PF1 Resizable BAR0 Capability lower 32 bits + 0x0000fff0 + + + PF1_RBAR_CAP_BAR1_UPPER + PF1 Resizable BAR1 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR1_LOWER + PF1 Resizable BAR1 Capability lower 32 bits + 0x00000000 + + + PF1_RBAR_CAP_BAR2_UPPER + PF1 Resizable BAR2 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR2_LOWER + PF1 Resizable BAR2 Capability lower 32 bits + 0x00000000 + + + PF1_RBAR_CAP_BAR3_UPPER + PF1 Resizable BAR3 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR3_LOWER + PF1 Resizable BAR3 Capability lower 32 bits + 0x00000000 + + + PF1_RBAR_CAP_BAR4_UPPER + PF1 Resizable BAR4 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR4_LOWER + PF1 Resizable BAR4 Capability lower 32 bits + 0x00000000 + + + PF1_RBAR_CAP_BAR5_UPPER + PF1 Resizable BAR5 Capability upper 16 bits + 0x0000 + + + PF1_RBAR_CAP_BAR5_LOWER + PF1 Resizable BAR5 Capability lower 32 bits + 0x00000000 + + + PF2_RBAR_CAP_BAR0_UPPER + PF2 Resizable BAR0 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR0_LOWER + PF2 Resizable BAR0 Capability lower 32 bits + 0x0000fff0 + + + PF2_RBAR_CAP_BAR1_UPPER + PF2 Resizable BAR1 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR1_LOWER + PF2 Resizable BAR1 Capability lower 32 bits + 0x00000000 + + + PF2_RBAR_CAP_BAR2_UPPER + PF2 Resizable BAR2 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR2_LOWER + PF2 Resizable BAR2 Capability lower 32 bits + 0x00000000 + + + PF2_RBAR_CAP_BAR3_UPPER + PF2 Resizable BAR3 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR3_LOWER + PF2 Resizable BAR3 Capability lower 32 bits + 0x00000000 + + + PF2_RBAR_CAP_BAR4_UPPER + PF2 Resizable BAR4 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR4_LOWER + PF2 Resizable BAR4 Capability lower 32 bits + 0x00000000 + + + PF2_RBAR_CAP_BAR5_UPPER + PF2 Resizable BAR5 Capability upper 16 bits + 0x0000 + + + PF2_RBAR_CAP_BAR5_LOWER + PF2 Resizable BAR5 Capability lower 32 bits + 0x00000000 + + + PF3_RBAR_CAP_BAR0_UPPER + PF3 Resizable BAR0 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR0_LOWER + PF3 Resizable BAR0 Capability lower 32 bits + 0x0000fff0 + + + PF3_RBAR_CAP_BAR1_UPPER + PF3 Resizable BAR1 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR1_LOWER + PF3 Resizable BAR1 Capability lower 32 bits + 0x00000000 + + + PF3_RBAR_CAP_BAR2_UPPER + PF3 Resizable BAR2 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR2_LOWER + PF3 Resizable BAR2 Capability lower 32 bits + 0x00000000 + + + PF3_RBAR_CAP_BAR3_UPPER + PF3 Resizable BAR3 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR3_LOWER + PF3 Resizable BAR3 Capability lower 32 bits + 0x00000000 + + + PF3_RBAR_CAP_BAR4_UPPER + PF3 Resizable BAR4 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR4_LOWER + PF3 Resizable BAR4 Capability lower 32 bits + 0x00000000 + + + PF3_RBAR_CAP_BAR5_UPPER + PF3 Resizable BAR5 Capability upper 16 bits + 0x0000 + + + PF3_RBAR_CAP_BAR5_LOWER + PF3 Resizable BAR5 Capability lower 32 bits + 0x00000000 + + + RBAR_CAP_NEXTPTR + 0x000 + + + PF0_RBAR_NUM_BAR + 0x1 + + + PF1_RBAR_NUM_BAR + 0x1 + + + PF2_RBAR_NUM_BAR + 0x1 + + + PF3_RBAR_NUM_BAR + 0x1 + + + PF0_RBAR_BAR_INDEX_0 + 0x0 + + + PF0_RBAR_BAR_INDEX_1 + 0x7 + + + PF0_RBAR_BAR_INDEX_2 + 0x7 + + + PF0_RBAR_BAR_INDEX_3 + 0x7 + + + PF0_RBAR_BAR_INDEX_4 + 0x7 + + + PF0_RBAR_BAR_INDEX_5 + 0x7 + + + PF1_RBAR_BAR_INDEX_0 + 0x0 + + + PF1_RBAR_BAR_INDEX_1 + 0x7 + + + PF1_RBAR_BAR_INDEX_2 + 0x7 + + + PF1_RBAR_BAR_INDEX_3 + 0x7 + + + PF1_RBAR_BAR_INDEX_4 + 0x7 + + + PF1_RBAR_BAR_INDEX_5 + 0x7 + + + PF2_RBAR_BAR_INDEX_0 + 0x0 + + + PF2_RBAR_BAR_INDEX_1 + 0x7 + + + PF2_RBAR_BAR_INDEX_2 + 0x7 + + + PF2_RBAR_BAR_INDEX_3 + 0x7 + + + PF2_RBAR_BAR_INDEX_4 + 0x7 + + + PF2_RBAR_BAR_INDEX_5 + 0x7 + + + PF3_RBAR_BAR_INDEX_0 + 0x0 + + + PF3_RBAR_BAR_INDEX_1 + 0x7 + + + PF3_RBAR_BAR_INDEX_2 + 0x7 + + + PF3_RBAR_BAR_INDEX_3 + 0x7 + + + PF3_RBAR_BAR_INDEX_4 + 0x7 + + + PF3_RBAR_BAR_INDEX_5 + 0x7 + + + USE_STANDARD_INTERFACES + Use standard interfaces + FALSE + + + DMA_2RP + FALSE + + + SRIOV_ACTIVE_VFS + 252 + + + QDMA_TPH_MSIX_BRAMS_DIS + FALSE + + + MASTER_GT_QUAD_INX + 3 + + + MASTER_GT_CONTAINER + 27 + + + ENABLE_MSIX_32VEC + FALSE + + + BROADCOM_SBR_WA + FALSE + + + + + + choice_list_002f5e3f + PCI_Express_Endpoint_device + Legacy_PCI_Express_Endpoint_device + Root_Port_of_PCI_Express_Root_Complex + + + choice_list_0cee66fe + 1 + 4 + 64 + + + choice_list_0f93492c + Chip-to-Chip + Add-in_Card + Backplane + + + choice_list_165ed04b + 64 + + + choice_list_1e9fb93b + X1 + X2 + X4 + X8 + X16 + + + choice_list_24b724fb + Basic + Advanced + + + choice_list_34d65ff4 + 128 + + + choice_list_35d06715 + 2 + + + choice_list_38306dd1 + SOFT + HARD + + + choice_list_3ca2cbc7 + BAR_0 + + + choice_list_3d9ff82c + 500 + 250 + + + choice_list_52d29139 + Bytes + Kilobytes + Megabytes + Gigabytes + + + choice_list_5590a31b + X1Y15 + + + choice_list_589df8e9 + RAM + Other_memory_controller + Flash + + + choice_list_5e2921cd + Kilobytes + + + choice_list_5e45706a + 1_vector + 2_vectors + 4_vectors + 8_vectors + 16_vectors + 32_vectors + + + choice_list_61bc5fcf + 0 + 4 + 7 + 8 + 12 + 16 + 20 + 24 + 28 + 32 + 36 + 40 + 44 + 48 + 52 + 56 + 60 + 64 + 68 + 72 + 76 + 80 + 84 + 88 + 92 + 96 + 100 + 104 + 108 + 112 + 116 + 120 + 124 + 128 + 132 + 136 + 140 + 144 + 148 + 152 + 156 + 160 + 164 + 168 + 172 + 176 + 180 + 184 + 188 + 192 + 196 + 200 + 204 + 208 + 212 + 216 + 220 + 224 + 228 + 232 + 236 + 240 + 244 + 248 + 252 + + + choice_list_635d42ef + X1Y15 X1Y14 + + + choice_list_6b979ebc + 250 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_6e6f488f + X1Y15 X1Y14 X1Y13 X1Y12 + + + choice_list_6eff49bd + ACTIVE_LOW + ACTIVE_HIGH + + + choice_list_75aee2a8 + X8G3 + X16G3 + + + choice_list_7a7dde49 + true + false + + + choice_list_7d45a81a + 128_bytes + 256_bytes + 512_bytes + 1024_bytes + + + choice_list_7e60966b + 2.5_GT/s + 5.0_GT/s + 8.0_GT/s + 16.0_GT/s + + + choice_list_8061eec5 + None + Tandem_PROM + Tandem_PCIe + Tandem_PCIe_with_Field_Updates + DFX_over_PCIe + + + choice_list_81a1639d + DWORD_Aligned + Address_Aligned + + + choice_list_847d868a + 1 + 2 + 3 + 4 + 5 + 6 + + + choice_list_88156f2e + QPLL1 + QPLL0 + + + choice_list_8b5e4915 + 4 + 5 + + + choice_list_909966b7 + X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 + + + choice_list_914704bd + 100_MHz + 125_MHz + + + choice_list_97bc19ec + 256_bit + + + choice_list_98ff8152 + GTY + + + choice_list_9aec9108 + Internal + External + + + choice_list_a30da595 + Custom + pcie_perstn + + + choice_list_a44ca313 + Custom + pci_express_x1 + pci_express_x16 + pci_express_x2 + pci_express_x4 + pci_express_x8 + + + choice_list_aa031417 + 1 + 2 + 3 + 4 + + + choice_list_abc20383 + GTY_Quad_227 + GTY_Quad_226 + GTY_Quad_225 + GTY_Quad_224 + + + choice_list_b41755a5 + X1Y0 + X0Y1 + X0Y0 + X1Y1 + + + choice_list_bdd7203f + True + False + + + choice_list_bea500ca + None + MSI-X_External + MSI-X_Internal + MSI-X_AXI4-Stream + + + choice_list_c15e8c67 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_c3d223d9 + Memory + + + choice_list_c8a15465 + X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 X1Y7 X1Y6 X1Y5 X1Y4 X1Y3 X1Y2 X1Y1 X1Y0 + + + choice_list_ca005b72 + No_ASPM + L1_Supported + + + choice_list_d123c74c + Bytes + Kilobytes + Megabytes + + + choice_list_d53faa96 + 100_MHz + 125_MHz + 250_MHz + + + choice_list_d85ad257 + 0 + + + choice_list_d992adf6 + Generic_XT_compatible_serial_controller + 16450_compatible_serial_controller + Parallel_port + IEEE_1284_controller + Multiport_serial_controller + 16650_compatible_serial_controller + IEEE_1284_target_device + Hayes_compatible_modem_with_16550_compatible_interface + ECP_1.X_compliant_parallel_port + 16850_compatible_serial_controller + Hayes_compatible_modem_with_16750_compatible_interface + Smart_Card + Bi_directional_parallel_port + Other_communications_device + GPIB(IEEE_488.1/2)_controller + 16550_compatible_serial_controller + Hayes_compatible_modem_with_16450_compatible_interface + 16750_compatible_serial_controller + Hayes_compatible_modem_with_16650_compatible_interface + Generic_modem + 16950_compatible_serial_controller + + + choice_list_dff1a45d + Wireless_controller + Satellite_communication_controllers + Data_acquisition_and_signal_processing_controllers + Processing_accelerators + Intelligent_I/O_controllers + Docking_stations + Device_was_built_before_Class_Code_definitions_were_finalized + Memory_controller + Simple_communication_controllers + Serial_bus_controllers + Encryption/Decryption_controllers + Display_controller + Multimedia_device + Input_devices + Mass_storage_controller + Processors + Device_does_not_fit_in_any_defined_classes + Bridge_device + Network_controller + Base_system_peripherals + + + choice_list_e7c484ae + TRUE + FALSE + + + choice_list_e9cf6440 + Disabled + 32bit_Enabled + 64bit_Enabled + + + choice_list_eaa1f22e + AU50 + + + choice_list_ec64e624 + N/A + + + choice_list_ed82972e + sample_smoke_test0 + sample_smoke_test1 + pio_writeReadBack_test0 + + + choice_list_f1174048 + NONE + INTA + INTB + INTC + INTD + + + choice_list_f149a468 + Extreme + Good + + + choice_list_fc3456a9 + Disabled + Enabled + + + choice_pairs_3c87fcdb + 1 + 0 + + + choice_pairs_53749dec + 1 + 0 + + + choice_pairs_6f00a734 + 0 + 1 + 2 + + + + + xilinx_elaboratesubcores_view_fileset + + ip_0/xdma_pcie4c_ip_gt.xci + xci + + + ip_0/xdma_pcie4c_ip_gt.xml + xml + + + + The Xilinx UltraScale+ PCI Express Integrated Block (1-lane, 2-lane, 4-lane, 8-lane and 16-lane) in conjunction with flexible Ultra series architectural features such as integrated GTs (Gigabit Transceivers) and BRAM (Block RAMs) are used to implement a PCI Express Base Specification v3.1 compliant PCI Express Endpoint. + + + device_port_type + Device Port Type + PCI_Express_Endpoint_device + + + xlnx_ref_board + Xlnx Ref Board + AU50 + + + + true + + + + + + testname + test + sample_smoke_test0 + + + PL_LINK_CAP_MAX_LINK_SPEED + Pl Link Cap Max Link Speed + 8.0_GT/s + + + PL_LINK_CAP_MAX_LINK_WIDTH + Pl Link Cap Max Link Width + The Xilinx Ultrascale Series Gen3 Integrated Block for PCI Expressification v3.0 compliant PCI Express Endpoint. + X8 + + + REF_CLK_FREQ + Ref Clk Freq + 100_MHz + + + AXISTEN_IF_EXT_512_CQ_STRADDLE + Axisten If Rc Straddle + false + + + + false + + + + + + AXISTEN_IF_EXT_512_CC_STRADDLE + Axisten If Rc Straddle + false + + + AXISTEN_IF_EXT_512_RQ_STRADDLE + Axisten If Rc Straddle + false + + + + false + + + + + + AXISTEN_IF_EXT_512_RC_STRADDLE + Axisten If Rc Straddle + true + + + AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE + Axisten If 512 4TLP/2TLP Rc Straddle + false + + + + false + + + + + + AXISTEN_IF_RC_STRADDLE + Axisten If Rc Straddle + true + + + axisten_if_enable_client_tag + Enable Client Tag + true + + + PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE + Pf0 Aer Cap Ecrc Gen and Check Capable + false + + + type1_membase_memlimit_enable + Type1 Config MemBase and MemLimit + Enabled + + + type1_prefetchable_membase_memlimit + Type1 Config Prefetchable MemBase and MemLimit + 64bit_Enabled + + + PF0_CLASS_CODE + Pf0 Class Code + 070001 + + + + false + + + + + + PF0_DEVICE_ID + Pf0 Device Id + 9038 + + + PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 128b Cas Atomic Completer Support + false + + + PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 32b Atomic Completer Support + false + + + PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 64b Atomic Completer Support + false + + + PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT + Pf0 Dev Cap2 Tph Completer Support + false + + + PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE + Pf0 Dev Cap Function Level Reset Capable + false + + + PF0_INTERRUPT_PIN + Pf0 Interrupt Pin + INTA + + + PF0_LINK_STATUS_SLOT_CLOCK_CONFIG + Pf0 Link Status Slot Clock Config + true + + + PF0_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF0_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 000 + + + + false + + + + + + PF0_MSI_CAP_MULTIMSGCAP + Pf0 Msi Cap Multimsgcap + 1_vector + + + PF0_PM_CAP_PMESUPPORT_D1 + Pf0 Pm Cap Pmesupport D1 + false + + + PF0_PM_CAP_PMESUPPORT_D3HOT + Pf0 Pm Cap Pmesupport D3hot + false + + + PF0_PM_CAP_SUPP_D1_STATE + Pf0 Pm Cap Supp D1 State + false + + + PF0_REVISION_ID + Pf0 Revision Id + 00 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 4 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 0 + + + + false + + + + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0000 + + + PF0_SUBSYSTEM_ID + Pf0 Subsystem Id + 0007 + + + PF1_CLASS_CODE + Pf1 Class Code + 058000 + + + PF1_DEVICE_ID + Pf1 Device Id + 9011 + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + NONE + + + PF1_MSIX_CAP_PBA_BIR + Pf1 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_BIR + Pf1 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_SIZE + Pf1 Msix Cap Table Size + 000 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_OFFSET + Pf1 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF1_MSIX_CAP_PBA_OFFSET + Pf1 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 1_vector + + + PF1_REVISION_ID + Pf1 Revision Id + 00 + + + PF1_SRIOV_CAP_INITIAL_VF + Pf1 Sriov Cap Initial Vf + 0 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 1 + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + 0 + + + + false + + + + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0001 + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0000 + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0007 + + + PF2_CLASS_CODE + Pf2 Class Code + 058000 + + + PF2_DEVICE_ID + Pf2 Device Id + 9438 + + + PF2_INTERRUPT_PIN + Pf2 Interrupt Pin + NONE + + + PF2_MSIX_CAP_PBA_BIR + Pf2 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_BIR + Pf2 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_SIZE + Pf2 Msix Cap Table Size + 000 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_OFFSET + Pf2 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF2_MSIX_CAP_PBA_OFFSET + Pf2 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF2_MSI_CAP_MULTIMSGCAP + Pf2 Msi Cap Multimsgcap + 1_vector + + + PF2_REVISION_ID + Pf2 Revision Id + 00 + + + PF2_SRIOV_CAP_INITIAL_VF + Pf2 Sriov Cap Initial Vf + 0 + + + PF2_SRIOV_CAP_VER + Pf2 Sriov Cap Ver + 1 + + + PF2_SRIOV_FIRST_VF_OFFSET + Pf2 Sriov First Vf Offset + 0 + + + + false + + + + + + PF2_SRIOV_FUNC_DEP_LINK + Pf2 Sriov Func Dep Link + 0002 + + + PF2_SRIOV_SUPPORTED_PAGE_SIZE + Pf2 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF2_SRIOV_VF_DEVICE_ID + Pf2 Sriov Vf Device Id + 0000 + + + PF2_SUBSYSTEM_ID + Pf2 Subsystem Id + 0007 + + + PF3_CLASS_CODE + Pf3 Class Code + 058000 + + + PF3_DEVICE_ID + Pf3 Device Id + 9638 + + + PF3_INTERRUPT_PIN + Pf3 Interrupt Pin + NONE + + + PF3_MSIX_CAP_PBA_BIR + Pf3 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_BIR + Pf3 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_SIZE + Pf3 Msix Cap Table Size + 000 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_OFFSET + Pf3 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF3_MSIX_CAP_PBA_OFFSET + Pf3 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF3_MSI_CAP_MULTIMSGCAP + Pf3 Msi Cap Multimsgcap + 1_vector + + + PF3_REVISION_ID + Pf3 Revision Id + 00 + + + PF3_SRIOV_CAP_INITIAL_VF + Pf3 Sriov Cap Initial Vf + 0 + + + PF3_SRIOV_CAP_VER + Pf3 Sriov Cap Ver + 1 + + + PF3_SRIOV_FIRST_VF_OFFSET + Pf3 Sriov First Vf Offset + 0 + + + + false + + + + + + PF3_SRIOV_FUNC_DEP_LINK + Pf3 Sriov Func Dep Link + 0003 + + + PF3_SRIOV_SUPPORTED_PAGE_SIZE + Pf3 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF3_SRIOV_VF_DEVICE_ID + Pf3 Sriov Vf Device Id + 0000 + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0007 + + + TL_PF_ENABLE_REG + 1 + + + SRIOV_CAP_ENABLE + Sriov Cap Enable + false + + + Component_Name + xdma_pcie4c_ip + + + PF0_Use_Class_Code_Lookup_Assistant + false + + + PF1_Use_Class_Code_Lookup_Assistant + false + + + PF2_Use_Class_Code_Lookup_Assistant + false + + + PF3_Use_Class_Code_Lookup_Assistant + false + + + PF0_PM_CAP_PMESUPPORT_D0 + Pf0 Pm Cap Pmesupport D0 + false + + + PF0_SUBSYSTEM_VENDOR_ID + Pf0 Subsystem Vendor Id + 10EE + + + PF1_SUBSYSTEM_VENDOR_ID + Pf1 Subsystem Vendor Id + 10EE + + + PF2_SUBSYSTEM_VENDOR_ID + Pf2 Subsystem Vendor Id + 10EE + + + PF3_SUBSYSTEM_VENDOR_ID + Pf3 Subsystem Vendor Id + 10EE + + + pf1_sriov_bar5_scale + Pf1 Sriov Bar5 Scale + Kilobytes + + + + false + + + + + + pf2_sriov_bar5_scale + Pf2 Sriov Bar5 Scale + Kilobytes + + + + false + + + + + + pf3_sriov_bar5_scale + Pf3 Sriov Bar5 Scale + Kilobytes + + + + false + + + + + + pf0_class_code_sub + Pf0 Class Code Sub + 00 + + + pf1_sriov_bar4_type + Pf1 Sriov Bar4 Type + N/A + + + + false + + + + + + pf2_sriov_bar4_type + Pf2 Sriov Bar4 Type + N/A + + + + false + + + + + + pf3_sriov_bar4_type + Pf3 Sriov Bar4 Type + N/A + + + + false + + + + + + pf0_vc_cap_enabled + Pf0 Vc Cap Enabled + true + + + pf1_sriov_bar5_type + Pf1 Sriov Bar5 Type + N/A + + + + false + + + + + + pf2_sriov_bar5_type + Pf2 Sriov Bar5 Type + N/A + + + + false + + + + + + pf3_sriov_bar5_type + Pf3 Sriov Bar5 Type + N/A + + + + false + + + + + + pf1_sriov_bar0_enabled + Pf1 Sriov Bar0 Enabled + true + + + + false + + + + + + pf2_sriov_bar0_enabled + Pf2 Sriov Bar0 Enabled + true + + + + false + + + + + + pf3_sriov_bar0_enabled + Pf3 Sriov Bar0 Enabled + true + + + + false + + + + + + pf0_sriov_bar5_enabled + Pf0 Sriov Bar5 Enabled + false + + + pf2_sriov_bar5_enabled + Pf2 Sriov Bar5 Enabled + false + + + + false + + + + + + pf3_sriov_bar5_enabled + Pf3 Sriov Bar5 Enabled + false + + + + false + + + + + + pcie_blk_locn + Pcie Blk Locn + X1Y0 + + + pf0_sriov_bar1_64bit + Pf0 Sriov Bar1 64bit + false + + + + false + + + + + + pf1_class_code_base + Pf1 Class Code Base + 05 + + + pf2_class_code_base + Pf2 Class Code Base + 05 + + + pf3_class_code_base + Pf3 Class Code Base + 05 + + + pf1_sriov_bar3_prefetchable + Pf1 Sriov Bar3 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar3_prefetchable + Pf2 Sriov Bar3 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar3_prefetchable + Pf3 Sriov Bar3 Prefetchable + false + + + + false + + + + + + pf1_sriov_bar0_64bit + Pf1 Sriov Bar0 64bit + false + + + + false + + + + + + pf2_sriov_bar0_64bit + Pf2 Sriov Bar0 64bit + false + + + + false + + + + + + pf3_sriov_bar0_64bit + Pf3 Sriov Bar0 64bit + false + + + + false + + + + + + pf1_bar3_type + Pf1 Bar3 Type + N/A + + + + false + + + + + + pf2_bar3_type + Pf2 Bar3 Type + N/A + + + + false + + + + + + pf3_bar3_type + Pf3 Bar3 Type + N/A + + + + false + + + + + + pf2_bar2_enabled + Pf2 Bar2 Enabled + false + + + + false + + + + + + pf3_bar2_enabled + Pf3 Bar2 Enabled + false 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Pf2 Bar4 Type + N/A + + + + false + + + + + + pf3_bar2_type + Pf3 Bar2 Type + N/A + + + + false + + + + + + pf3_bar2_64bit + Pf3 Bar2 64bit + false + + + + false + + + + + + pf3_bar2_prefetchable + Pf3 Bar2 Prefetchable + false + + + + false + + + + + + pf3_bar2_scale + Pf3 Bar2 Scale + Kilobytes + + + + false + + + + + + pf3_bar2_size + Pf3 Bar2 Size + 128 + + + + false + + + + + + pf3_bar4_type + Pf3 Bar4 Type + N/A + + + + false + + + + + + pf0_base_class_menu + Pf0 Base Class Menu + Simple_communication_controllers + + + pf0_sub_class_interface_menu + Pf0 Sub Class Interface Menu + 16450_compatible_serial_controller + + + pf1_sriov_bar0_scale + Pf1 Sriov Bar0 Scale + Kilobytes + + + + false + + + + + + pf1_expansion_rom_enabled + Pf1 Expansion Rom Enabled + false + + + + false + + + + + + pf0_sriov_bar0_enabled + Pf0 Sriov Bar0 Enabled + true + + + pf1_sriov_bar0_prefetchable + Pf1 Sriov Bar0 Prefetchable + false + + + + false + + + + + + pf1_bar5_type + Pf1 Bar5 Type + N/A + + + + false + + + + + + pf0_sriov_bar5_prefetchable + Pf0 Sriov Bar5 Prefetchable + false + + + pf1_sriov_bar1_enabled + Pf1 Sriov Bar1 Enabled + false + + + + false + + + + + + pf1_class_code_interface + Pf1 Class Code Interface + 00 + + + pf0_sriov_bar2_64bit + Pf0 Sriov Bar2 64bit + false + + + + false + + + + + + pf1_msix_enabled + Pf1 Msix Enabled + false + + + pf1_bar5_prefetchable + Pf1 Bar5 Prefetchable + false + + + pf1_sriov_bar1_64bit + Pf1 Sriov Bar1 64bit + false + + + + false + + + + + + pf1_bar3_64bit + Pf1 Bar3 64bit + false + + + + false + + + + + + pf0_sriov_bar2_prefetchable + Pf0 Sriov Bar2 Prefetchable + false + + + + false + + + + + + pf1_bar3_enabled + Pf1 Bar3 Enabled + false + + + + false + + + + + + pf0_sriov_bar2_scale + Pf0 Sriov Bar2 Scale + Kilobytes + + + + false + + + + + + pf1_sriov_bar1_scale + Pf1 Sriov Bar1 Scale + Kilobytes + + + + false + + + + + + pf1_bar3_scale + Pf1 Bar3 Scale + Kilobytes + + + + false + + + + + + pf0_sriov_bar1_enabled + Pf0 Sriov Bar1 Enabled + false + + + AXISTEN_IF_RQ_ALIGNMENT_MODE + DWORD_Aligned + + + AXISTEN_IF_CQ_ALIGNMENT_MODE + Address_Aligned + + + alignment_mode_256b + Alignment Mode + DWORD_Aligned + + + pf1_sriov_bar4_prefetchable + Pf1 Sriov Bar4 Prefetchable + false + + + + false + + + + + + pf1_sriov_bar2_enabled + Pf1 Sriov Bar2 Enabled + false + + + + false + + + + + + pf0_sriov_bar3_64bit + Pf0 Sriov Bar3 64bit + false + + + + false + + + + + + pf0_sriov_bar0_size + Pf0 Sriov Bar0 Size + 2 + + + pf1_sriov_bar2_64bit + Pf1 Sriov Bar2 64bit + false + + + + false + + + + + + pf1_bar4_64bit + Pf1 Bar4 64bit + false + + + + false + + + + + + pf0_sriov_bar1_size + Pf0 Sriov Bar1 Size + 2 + + + + false + + + + + + pf0_bar0_enabled + Pf0 Bar0 Enabled + true + + + pf0_bar0_type + Pf0 Bar0 Type + Memory + + + pf0_bar0_64bit + Pf0 Bar0 64bit + false + + + pf0_bar0_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar0_scale + Pf0 Bar0 Scale + Kilobytes + + + pf0_bar0_size + Pf0 Bar0 Size + 64 + + + pf0_bar1_enabled + Pf0 Bar1 Enabled + false + + + pf0_bar1_type + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf0_bar1_64bit + Pf0 Bar1 64bit + false + + + + false + + + + + + pf0_bar1_prefetchable + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf0_bar1_scale + Pf0 Bar1 Scale + Kilobytes + + + + false + + + + + + pf0_bar1_size + Pf0 Bar1 Size + 128 + + + + false + + + + + + pf0_bar2_enabled + Pf0 Bar2 Enabled + false + + + pf0_bar2_type + Pf0 Bar2 Type + N/A + + + + false + + + + + + pf0_bar2_64bit + Pf0 Bar2 64bit + false + + + + false + + + + + + pf0_bar2_prefetchable + Pf0 Bar2 Prefetchable + false + + + + false + + + + + + pf0_bar2_scale + Pf0 Bar2 Scale + Kilobytes + + + + false + + + + + + pf0_bar2_size + Pf0 Bar2 Size + 128 + + + + false + + + + + + pf0_bar3_enabled + Pf0 Bar3 Enabled + false + + + pf0_bar3_type + Pf0 Bar3 Type + N/A + + + + false + + + + + + pf0_bar3_64bit + Pf0 Bar3 64bit + false + + + + false + + + + + + pf0_bar3_prefetchable + Pf0 Bar3 Prefetchable + false + + + + false + + + + + + pf0_bar3_scale + Pf0 Bar3 Scale + Kilobytes + + + + false + + + + + + pf0_bar3_size + Pf0 Bar3 Size + 128 + + + + false + + + + + + pf0_bar4_enabled + Pf0 Bar4 Enabled + false + + + pf0_bar4_type + Pf0 Bar4 Type + N/A + + + + false + + + + + + pf0_bar4_64bit + Pf0 Bar4 64bit + false + + + + false + + + + + + pf0_bar4_prefetchable + Pf0 Bar4 Prefetchable + false + + + + false + + + + + + pf0_bar4_scale + Pf0 Bar4 Scale + Kilobytes + + + + false + + + + + + pf0_bar4_size + Pf0 Bar4 Size + 128 + + + + false + + + + + + pf0_bar5_enabled + Pf0 Bar5 Enabled + false + + + pf0_bar5_type + Pf0 Bar5 Type + N/A + + + + false + + + + + + pf0_bar5_prefetchable + Pf0 Bar5 Prefetchable + false + + + pf0_bar5_scale + Pf0 Bar5 Scale + Kilobytes + + + + false + + + + + + pf0_bar5_size + Pf0 Bar5 Size + 128 + + + + false + + + + + + pf0_sriov_bar3_scale + Pf0 Sriov Bar3 Scale + Kilobytes + + + + false + + + + + + pf1_bar4_enabled + Pf1 Bar4 Enabled + false + + + + false + + + + + + pf1_sriov_bar1_prefetchable + Pf1 Sriov Bar1 Prefetchable + false + + + + false + + + + + + pf0_sriov_bar2_size + Pf0 Sriov Bar2 Size + 2 + + + + false + + + + + + pf1_sriov_bar2_scale + Pf1 Sriov Bar2 Scale + Kilobytes + + + + false + + + + + + pf1_bar4_scale + Pf1 Bar4 Scale + Kilobytes + + + + false + + + + + + pf0_sriov_bar3_size + Pf0 Sriov Bar3 Size + 2 + + + + false + + + + + + pf0_sriov_bar2_enabled + Pf0 Sriov Bar2 Enabled + false + + + pf0_dev_cap_max_payload + Pf0 Dev Cap Max Payload + 1024_bytes + + + gen_x0y0 + Gen X0y0 + true + + + gen_x0y1 + Gen X0y1 + false + + + gen_x0y2 + Gen X0y2 + false + + + gen_x0y3 + Gen X0y3 + false + + + gen_x0y4 + Gen X0y4 + false + + + gen_x0y5 + Gen X0y5 + false + + + gen_x0y6 + Gen X0y6 + false + + + gen_x0y7 + Gen X0y7 + false + + + gen_x1y0 + Gen X1y0 + false + + + gen_x1y1 + Gen X1y1 + false + + + gen_x1y2 + Gen X1y2 + false + + + gen_x1y3 + Gen X1y3 + false + + + gen_x1y4 + Gen X1y4 + false + + + gen_x1y5 + Gen X1y5 + false + + + pf0_sriov_bar4_size + Pf0 Sriov Bar4 Size + 2 + + + + false + + + + + + pf1_expansion_rom_scale + Pf1 Expansion Rom Scale + Kilobytes + + + + false + + + + + + pf1_expansion_rom_size + Pf1 Expansion Rom Size + 2 + + + + false + + + + + + pf1_sriov_bar3_enabled + Pf1 Sriov Bar3 Enabled + false + + + + false + + + + + + pf0_sriov_bar4_64bit + Pf0 Sriov Bar4 64bit + false + + + + false + + + + + + pf0_sriov_bar5_size + Pf0 Sriov Bar5 Size + 2 + + + + false + + + + + + pf0_sriov_bar3_prefetchable + Pf0 Sriov Bar3 Prefetchable + false + + + + false + + + + + + pf1_sriov_bar3_64bit + Pf1 Sriov Bar3 64bit + false + + + + false + + + + + + pf0_expansion_rom_enabled + Pf0 Expansion Rom Enabled + false + + + pf0_sriov_bar4_scale + Pf0 Sriov Bar4 Scale + Kilobytes + + + + false + + + + + + pf1_base_class_menu + Pf1 Base Class Menu + Memory_controller + + + pf1_sub_class_interface_menu + Pf1 Sub Class Interface Menu + Other_memory_controller + + + pf0_sriov_bar0_type + Pf0 Sriov Bar0 Type + Memory + + + pf1_bar5_enabled + Pf1 Bar5 Enabled + false + + + + false + + + + + + pf1_bar3_prefetchable + Pf1 Bar3 Prefetchable + false + + + + false + + + + + + pf1_sriov_bar0_size + Pf1 Sriov Bar0 Size + 2 + + + + false + + + + + + pf1_sriov_bar3_scale + Pf1 Sriov Bar3 Scale + Kilobytes + + + + false + + + + + + pf1_bar5_scale + Pf1 Bar5 Scale + Kilobytes + + + + false + + + + + + pf1_class_code_sub + Pf1 Class Code Sub + 80 + + + extended_tag_field + Extended Tag Field + true + + + pf0_sriov_bar1_type + Pf0 Sriov Bar1 Type + N/A + + + + false + + + + + + pf0_sriov_bar0_prefetchable + Pf0 Sriov Bar0 Prefetchable + false + + + + false + + + + + + pf0_expansion_rom_scale + Pf0 Expansion Rom Scale + Kilobytes + + + + false + + + + + + pf0_expansion_rom_size + Pf0 Expansion Rom Size + 2 + + + + false + + + + + + pf1_sriov_bar1_size + Pf1 Sriov Bar1 Size + 2 + + + + false + + + + + + pf0_sriov_bar3_enabled + Pf0 Sriov Bar3 Enabled + false + + + pf1_sriov_bar5_prefetchable + Pf1 Sriov Bar5 Prefetchable + false + + + pf0_sriov_bar2_type + Pf0 Sriov Bar2 Type + N/A + + + + false + + + + + + vendor_id + Vendor Id + 10EE + + + pf1_vendor_id + Vendor Id + 10EE + + + pf2_vendor_id + Vendor Id + 10EE + + + pf3_vendor_id + Vendor Id + 10EE + + + pf0_tphr_enable + Pf0 Tphr Enable + false + + + pf1_sriov_bar2_size + Pf1 Sriov Bar2 Size + 2 + + + + false + + + + + + pf0_sriov_bar3_type + Pf0 Sriov Bar3 Type + N/A + + + + false + + + + + + pf1_sriov_bar3_size + Pf1 Sriov Bar3 Size + 2 + + + + false + + + + + + pf1_bar0_enabled + Pf1 Bar0 Enabled + true + + + + false + + + + + + pf1_bar0_type + Pf1 Bar0 Type + Memory + + + + false + + + + + + pf1_bar0_64bit + Pf1 Bar0 64bit + false + + + + false + + + + + + pf1_bar0_prefetchable + Pf1 Bar0 Prefetchable + false + + + + false + + + + + + pf1_bar0_scale + Pf1 Bar0 Scale + Kilobytes + + + + false + + + + + + pf1_bar0_size + Pf1 Bar0 Size + 64 + + + + false + + + + + + pf1_bar1_enabled + Pf1 Bar1 Enabled + false + + + + false + + + + + + pf1_bar1_type + Pf1 Bar1 Type + N/A + + + + false + + + + + + pf1_bar1_64bit + Pf1 Bar1 64bit + false + + + + false + + + + + + pf1_bar1_prefetchable + Pf1 Bar1 Prefetchable + false + + + + false + + + + + + pf1_bar1_scale + Pf1 Bar1 Scale + Kilobytes + + + + false + + + + + + pf1_bar1_size + Pf1 Bar1 Size + 128 + + + + false + + + + + + pf1_sriov_bar4_enabled + Pf1 Sriov Bar4 Enabled + false + + + + false + + + + + + pf0_sriov_bar4_type + Pf0 Sriov Bar4 Type + N/A + + + + false + + + + + + pf1_sriov_bar4_64bit + Pf1 Sriov Bar4 64bit + false + + + + false + + + + + + pf1_sriov_bar2_prefetchable + Pf1 Sriov Bar2 Prefetchable + false + + + + false + + + + + + pf0_sriov_cap_ver + Pf0 Sriov Cap Ver + 1 + + + pf1_sriov_bar4_size + Pf1 Sriov Bar4 Size + 2 + + + + false + + + + + + pf1_msi_enabled + Pf1 Msi Enabled + false + + + + false + + + + + + pf0_sriov_bar5_scale + Pf0 Sriov Bar5 Scale + Kilobytes + + + + false + + + + + + pf0_sriov_bar5_type + Pf0 Sriov Bar5 Type + N/A + + + + false + + + + + + ext_pcie_cfg_space_enabled + Ext Pcie Cfg Space Enabled + false + + + legacy_ext_pcie_cfg_space_enabled + Legacy Ext Pcie Cfg Space Enabled + false + + + ext_xvc_vsec_enable + Enable to add the PCIe XVC-VSEC to the Examlpe Design + false + + + + false + + + + + + acs_ext_cap_enable + ACS Ext Capability + false + + + pf1_sriov_bar4_scale + Pf1 Sriov Bar4 Scale + Kilobytes + + + + false + + + + + + pf1_sriov_bar5_size + Pf1 Sriov Bar5 Size + 2 + + + + false + + + + + + pf0_ari_enabled + Pf0 Ari Enabled + false + + + perf_level + Perf Level + Extreme + + + pf0_class_code_base + Pf0 Class Code Base + 07 + + + axisten_if_width + Axisten If Width + 256_bit + + + pf0_sriov_bar4_enabled + Pf0 Sriov Bar4 Enabled + false + + + pf1_sriov_bar0_type + Pf1 Sriov Bar0 Type + Memory + + + + false + + + + + + pf1_bar3_size + Pf1 Bar3 Size + 128 + + + + false + + + + + + pf0_sriov_bar4_prefetchable + Pf0 Sriov Bar4 Prefetchable + false + + + + false + + + + + + pf0_aer_enabled + Pf0 Aer Enabled + true + + + pf0_dsn_enabled + Pf0 Dsn Enabled + false + + + pf1_sriov_bar1_type + Pf1 Sriov Bar1 Type + N/A + + + + false + + + + + + pf0_sriov_bar0_64bit + Pf0 Sriov Bar0 64bit + false + + + pf1_bar4_size + Pf1 Bar4 Size + 128 + + + + false + + + + + + pf0_msi_enabled + Pf0 Msi Enabled + true + + + pf1_sriov_bar5_enabled + Pf1 Sriov Bar5 Enabled + false + + + + false + + + + + + pf1_sriov_bar2_type + Pf1 Sriov Bar2 Type + N/A + + + + false + + + + + + pf0_msix_enabled + Pf0 Msix Enabled + false + + + pf1_bar5_size + Pf1 Bar5 Size + 128 + + + + false + + + + + + pf1_bar4_prefetchable + Pf1 Bar4 Prefetchable + false + + + + false + + + + + + pf0_sriov_bar0_scale + Pf0 Sriov Bar0 Scale + Kilobytes + + + pf0_sriov_bar1_prefetchable + Pf0 Sriov Bar1 Prefetchable + false + + + + false + + + + + + pf1_sriov_bar3_type + Pf1 Sriov Bar3 Type + N/A + + + + false + + + + + + pf2_sriov_bar0_scale + Pf2 Sriov Bar0 Scale + Kilobytes + + + + false + + + + + + pf2_expansion_rom_enabled + Pf2 Expansion Rom Enabled + false + + + + false + + + + + + pf2_sriov_bar0_prefetchable + Pf2 Sriov Bar0 Prefetchable + false + + + + false + + + + + + pf2_bar5_type + Pf2 Bar5 Type + N/A + + + + false + + + + + + pf2_sriov_bar1_enabled + Pf2 Sriov Bar1 Enabled + false + + + + false + + + + + + pf2_class_code_interface + Pf2 Class Code Interface + 00 + + + pf2_msix_enabled + Pf2 Msix Enabled + false + + + pf2_bar5_prefetchable + Pf2 Bar5 Prefetchable + false + + + pf2_sriov_bar1_64bit + Pf2 Sriov Bar1 64bit + false + + + + false + + + + + + pf2_bar3_64bit + Pf2 Bar3 64bit + false + + + + false + + + + + + pf2_bar3_enabled + Pf2 Bar3 Enabled + false + + + + false + + + + + + pf2_sriov_bar1_scale + Pf2 Sriov Bar1 Scale + Kilobytes + + + + false + + + + + + pf2_bar3_scale + Pf2 Bar3 Scale + Kilobytes + + + + false + + + + + + pf2_sriov_bar4_prefetchable + Pf2 Sriov Bar4 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar2_enabled + Pf2 Sriov Bar2 Enabled + false + + + + false + + + + + + pf2_sriov_bar2_64bit + Pf2 Sriov Bar2 64bit + false + + + + false + + + + + + pf2_bar4_64bit + Pf2 Bar4 64bit + false + + + + false + + + + + + pf2_bar4_enabled + Pf2 Bar4 Enabled + false + + + + false + + + + + + pf2_sriov_bar1_prefetchable + Pf2 Sriov Bar1 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar2_scale + Pf2 Sriov Bar2 Scale + Kilobytes + + + + false + + + + + + pf2_bar4_scale + Pf2 Bar4 Scale + Kilobytes + + + + false + + + + + + pf2_expansion_rom_scale + Pf2 Expansion Rom Scale + Kilobytes + + + + false + + + + + + pf2_expansion_rom_size + Pf2 Expansion Rom Size + 2 + + + + false + + + + + + pf2_sriov_bar3_enabled + Pf2 Sriov Bar3 Enabled + false + + + + false + + + + + + pf2_sriov_bar3_64bit + Pf2 Sriov Bar3 64bit + false + + + + false + + + + + + pf2_base_class_menu + Pf2 Base Class Menu + Memory_controller + + + pf2_sub_class_interface_menu + Pf2 Sub Class Interface Menu + Other_memory_controller + + + pf2_bar5_enabled + Pf2 Bar5 Enabled + false + + + + false + + + + + + pf2_bar3_prefetchable + Pf2 Bar3 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar0_size + Pf2 Sriov Bar0 Size + 2 + + + + false + + + + + + pf2_sriov_bar3_scale + Pf2 Sriov Bar3 Scale + Kilobytes + + + + false + + + + + + pf2_bar5_scale + Pf2 Bar5 Scale + Kilobytes + + + + false + + + + + + pf2_class_code_sub + Pf2 Class Code Sub + 80 + + + pf2_sriov_bar1_size + Pf2 Sriov Bar1 Size + 2 + + + + false + + + + + + pf2_sriov_bar5_prefetchable + Pf2 Sriov Bar5 Prefetchable + false + + + pf2_sriov_bar2_size + Pf2 Sriov Bar2 Size + 2 + + + + false + + + + + + pf2_sriov_bar3_size + Pf2 Sriov Bar3 Size + 2 + + + + false + + + + + + pf2_bar0_enabled + Pf2 Bar0 Enabled + true + + + + false + + + + + + pf2_bar0_type + Pf2 Bar0 Type + Memory + + + + false + + + + + + pf2_bar0_64bit + Pf2 Bar0 64bit + false + + + + false + + + + + + pf2_bar0_prefetchable + Pf2 Bar0 Prefetchable + false + + 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Kilobytes + + + + false + + + + + + pf2_sriov_bar5_size + Pf2 Sriov Bar5 Size + 2 + + + + false + + + + + + pf2_sriov_bar0_type + Pf2 Sriov Bar0 Type + Memory + + + + false + + + + + + pf2_bar3_size + Pf2 Bar3 Size + 128 + + + + false + + + + + + pf2_sriov_bar1_type + Pf2 Sriov Bar1 Type + N/A + + + + false + + + + + + pf2_bar4_size + Pf2 Bar4 Size + 128 + + + + false + + + + + + pf2_sriov_bar2_type + Pf2 Sriov Bar2 Type + N/A + + + + false + + + + + + pf2_bar5_size + Pf2 Bar5 Size + 128 + + + + false + + + + + + pf2_bar4_prefetchable + Pf2 Bar4 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar3_type + Pf2 Sriov Bar3 Type + N/A + + + + false + + + + + + pf3_sriov_bar0_scale + Pf3 Sriov Bar0 Scale + Kilobytes + + + + false + + + + + + pf3_expansion_rom_enabled + Pf3 Expansion Rom Enabled + false + + + + false + + + + + + pf3_sriov_bar0_prefetchable + Pf3 Sriov Bar0 Prefetchable + false + + + + false + + + + + + pf3_bar5_type + Pf3 Bar5 Type + N/A + + + + false + + + + + + pf3_sriov_bar1_enabled + Pf3 Sriov Bar1 Enabled + false + + + + false + + + + + + pf3_class_code_interface + Pf3 Class Code Interface + 00 + + + pf3_msix_enabled + Pf3 Msix Enabled + false + + + pf3_bar5_prefetchable + Pf3 Bar5 Prefetchable + false + + + pf3_sriov_bar1_64bit + Pf3 Sriov Bar1 64bit + false + + + + false + + + + + + pf3_bar3_64bit + Pf3 Bar3 64bit + false + + + + false + + + + + + pf3_bar3_enabled + Pf3 Bar3 Enabled + false + + + + false + + + + + + pf3_sriov_bar1_scale + Pf3 Sriov Bar1 Scale + Kilobytes + + + + false + + + + + + pf3_bar3_scale + Pf3 Bar3 Scale + Kilobytes + + + + false + + + + + + pf3_sriov_bar4_prefetchable + Pf3 Sriov Bar4 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar2_enabled + Pf3 Sriov Bar2 Enabled + false + + + + false + + + + + + pf3_sriov_bar2_64bit + Pf3 Sriov Bar2 64bit + false + + + + false + + + + + + pf3_bar4_64bit + Pf3 Bar4 64bit + false + + + + false + + + + + + pf3_bar4_enabled + Pf3 Bar4 Enabled + false + + + + false + + + + + + pf3_sriov_bar1_prefetchable + Pf3 Sriov Bar1 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar2_scale + Pf3 Sriov Bar2 Scale + Kilobytes + + + + false + + + + + + pf3_bar4_scale + Pf3 Bar4 Scale + Kilobytes + + + + false + + + + + + pf3_expansion_rom_scale + Pf3 Expansion Rom Scale + Kilobytes + + + + false + + + + + + pf3_expansion_rom_size + Pf3 Expansion Rom Size + 2 + + + + false + + + + + + pf3_sriov_bar3_enabled + Pf3 Sriov Bar3 Enabled + false + + + + false + + + + + + pf3_sriov_bar3_64bit + Pf3 Sriov Bar3 64bit + false + + + + false + + + + + + pf3_base_class_menu + Pf3 Base Class Menu + Memory_controller + + + pf3_sub_class_interface_menu + Pf3 Sub Class Interface Menu + Other_memory_controller + + + pf3_bar5_enabled + Pf3 Bar5 Enabled + false + + + + false + + + + + + pf3_bar3_prefetchable + Pf3 Bar3 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar0_size + Pf3 Sriov Bar0 Size + 2 + + + + false + + + + + + pf3_sriov_bar3_scale + Pf3 Sriov Bar3 Scale + Kilobytes + + + + false + + + + + + pf3_bar5_scale + Pf3 Bar5 Scale + Kilobytes + + + + false + + + + + + pf3_class_code_sub + Pf3 Class Code Sub + 80 + + + pf3_sriov_bar1_size + Pf3 Sriov Bar1 Size + 2 + + + + false + + + + + + pf3_sriov_bar5_prefetchable + Pf3 Sriov Bar5 Prefetchable + false + + + pf3_sriov_bar2_size + Pf3 Sriov Bar2 Size + 2 + + + + false + + + + + + pf3_sriov_bar3_size + Pf3 Sriov Bar3 Size + 2 + + + + false + + + + + + pf3_bar0_enabled + Pf3 Bar0 Enabled + true + + + + false + + + + + + pf3_bar0_type + Pf3 Bar0 Type + Memory + + + + false + + + + + + pf3_bar0_64bit + Pf3 Bar0 64bit + false + + + + false + + + + + + pf3_bar0_prefetchable + Pf3 Bar0 Prefetchable + false + + + + false + + + + + + pf3_bar0_scale + Pf3 Bar0 Scale + Kilobytes + + + + false + + + + + + pf3_bar0_size + Pf3 Bar0 Size + 64 + + + + false + + + + + + pf3_bar1_enabled + Pf3 Bar1 Enabled + false + + + + false + + + + + + pf3_bar1_type + Pf3 Bar1 Type + N/A + + + + false + + + + + + pf3_bar1_64bit + Pf3 Bar1 64bit + false + + + + false + + + + + + pf3_bar1_prefetchable + Pf3 Bar1 Prefetchable + false + + + + false + + + + + + pf3_bar1_scale + Pf3 Bar1 Scale + Kilobytes + + + + false + + + + + + pf3_bar1_size + Pf3 Bar1 Size + 128 + + + + false + + + + + + pf3_sriov_bar4_enabled + Pf3 Sriov Bar4 Enabled + false + + + + false + + + + + + pf3_sriov_bar4_64bit + Pf3 Sriov Bar4 64bit + false + + + + false + + + + + + pf3_sriov_bar2_prefetchable + Pf3 Sriov Bar2 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar4_size + Pf3 Sriov Bar4 Size + 2 + + + + false + + + + + + pf3_msi_enabled + Pf3 Msi Enabled + false + + + + false + + + + + + pf3_sriov_bar4_scale + Pf3 Sriov Bar4 Scale + Kilobytes + + + + false + + + + + + pf3_sriov_bar5_size + Pf3 Sriov Bar5 Size + 2 + + + + false + + + + + + pf3_sriov_bar0_type + Pf3 Sriov Bar0 Type + Memory + + + + false + + + + + + pf3_bar3_size + Pf3 Bar3 Size + 128 + + + + false + + + + + + pf3_sriov_bar1_type + Pf3 Sriov Bar1 Type + N/A + + + + false + + + + + + pf3_bar4_size + Pf3 Bar4 Size + 128 + + + + false + + + + + + pf3_sriov_bar2_type + Pf3 Sriov Bar2 Type + N/A + + + + false + + + + + + pf3_bar5_size + Pf3 Bar5 Size + 128 + + + + false + + + + + + pf3_bar4_prefetchable + Pf3 Bar4 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar3_type + Pf3 Sriov Bar3 Type + N/A + + + + false + + + + + + mode_selection + Mode + Advanced + + + pipe_sim + false + + + en_ext_clk + false + + + en_msi_per_vec_masking + false + + + coreclk_freq + CORE CLOCK FREQ + 500 + + + + true + + + + + + plltype + PLL TYPE + QPLL1 + + + axisten_freq + AXISTEN IF FREQ + 250 + + + aspm_support + ASPM Support + No_ASPM + + + SRIOV_CAP_ENABLE_EXT + SRIOV Cap Enable + false + + + cfg_fc_if + true + + + cfg_ext_if + false + + + cfg_status_if + true + + + per_func_status_if + true + + + cfg_mgmt_if + true + + + rcv_msg_if + true + + + + true + + + + + + cfg_tx_msg_if + true + + + cfg_ctl_if + true + + + tx_fc_if + true + + + en_pcie_drp + false + + + en_parity + false + + + en_pl_ifc + false + + + en_pcie_conf + false + + + dis_gt_wizard + false + + + bmd_pio_mode + false + + + sriov_exd_mode + false + + + dbg_checker + false + + + + false + + + + + + enable_ibert + false + + + two_port_switch + false + + + two_port_config + X8G3 + + + RX_PPM_OFFSET + Specify the PPM offset between received data and transmitted data + 0 + + + RX_SSC_PPM + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 15 + + + ins_loss_profile + Add-in_Card + + + + true + + + + + + enable_gen4 + true + + + en_transceiver_status_ports + false + + + + true + + + + + + Shared_Logic + 1 + + + gtwiz_in_core + 1 + + + gtcom_in_core + 2 + + + dedicate_perst + false + + + sys_reset_polarity + ACTIVE_LOW + + + mcap_enablement + MCAP Enable + None + + + mcap_fpga_bitstream_version + MCAP Bitstream Version Register Value + 00000000 + + + + false + + + + + + enable_code + 0000 + + + en_ext_ch_gt_drp + false + + + ext_startup_primitive + false + + + en_gt_selection + false + + + select_quad + GTY_Quad_227 + + + + false + + + + + + copy_pf0 + true + + + copy_sriov_pf0 + true + + + cfg_pm_if + true + + + pcie_id_if + FALSE + + + PL_DISABLE_LANE_REVERSAL + true + + + MSI_X_OPTIONS + None + + + completer_model + false + + + en_dbg_descramble + false + + + enable_jtag_dbg + false + + + + true + + + + + + enable_ltssm_dbg + false + + + + true + + + + + + tl_credits_cd + 15 + + + tl_credits_ch + 15 + + + set_finite_credit + false + + + gen4_eieos_0s7 + true + + + vu9p_board + false + + + PHY_LP_TXPRESET + 4 + + + SYS_RST_N_BOARD_INTERFACE + Custom + + + PCIE_BOARD_INTERFACE + Custom + + + gt_drp_clk_src + GT DRP Clk Source + Internal + + + free_run_freq + Free Run Freq + 100_MHz + + + en_l23_entry + false + + + aws_mode_value + aws mode value + 0 + + + enable_ccix + FALSE + + + enable_dvsec + FALSE + + + X1_CH_EN + X1Y15 + + + X2_CH_EN + X1Y15 X1Y14 + + + X4_CH_EN + X1Y15 X1Y14 X1Y13 X1Y12 + + + X8_CH_EN + X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 + + + XS_CH_EN + X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 X1Y7 X1Y6 X1Y5 X1Y4 X1Y3 X1Y2 X1Y1 X1Y0 + + + GT_TYPE + GTY + + + TX_RX_MASTER_CHANNEL + X1Y15 + + + ext_sys_clk_bufg + false + + + axisten_if_enable_msg_route + 20000 + + + + true + + + + + + enable_more_clk + false + + + disable_bram_pipeline + false + + + disable_eq_synchronizer + false + + + axisten_if_enable_msg_route_override + true + + + enable_auto_rxeq + False + + + pf0_ats_enabled + Pf0 Ats Enabled + false + + + three_port_switch + Three Port Switch Enable + false + + + pf0_pri_enabled + Pf0 Pri Enabled + false + + + gen_pipe_debug + false + + + enable_mark_debug + false + + + enable_multipf_aer + false + + + master_cal_only + false + + + rbar_enable + false + + + pf0_rbar_num + Number of Resizable BARs for PF0 + 1 + + + pf1_rbar_num + Number of Resizable BARs for PF1 + 1 + + + pf2_rbar_num + Number of Resizable BARs for PF2 + 1 + + + pf3_rbar_num + Number of Resizable BARs for PF3 + 1 + + + pf0_bar0_index + PF0 BAR0 index + 0 + + + pf0_bar1_index + PF0 BAR1 index + 7 + + + pf0_bar2_index + PF0 BAR2 index + 7 + + + pf0_bar3_index + PF0 BAR3 index + 7 + + + pf0_bar4_index + PF0 BAR4 index + 7 + + + pf0_bar5_index + PF0 BAR5 index + 7 + + + pf1_bar0_index + PF0 BAR0 index + 0 + + + pf1_bar1_index + PF1 BAR1 index + 7 + + + pf1_bar2_index + PF1 BAR2 index + 7 + + + pf1_bar3_index + PF1 BAR3 index + 7 + + + pf1_bar4_index + PF1 BAR4 index + 7 + + + pf1_bar5_index + PF1 BAR5 index + 7 + + + pf2_bar0_index + PF2 BAR0 index + 0 + + + pf2_bar1_index + PF2 BAR1 index + 7 + + + pf2_bar2_index + PF2 BAR2 index + 7 + + + pf2_bar3_index + PF2 BAR3 index + 7 + + + pf2_bar4_index + PF2 BAR4 index + 7 + + + pf2_bar5_index + PF2 BAR5 index + 7 + + + pf3_bar0_index + PF3 BAR0 index + 0 + + + pf3_bar1_index + PF3 BAR1 index + 7 + + + pf3_bar2_index + PF3 BAR2 index + 7 + + + pf3_bar3_index + PF3 BAR3 index + 7 + + + pf3_bar4_index + PF3 BAR4 index + 7 + + + pf3_bar5_index + PF3 BAR5 index + 7 + + + pf0_rbar_cap_bar0 + PF0 RBAR CAP BAR0 + 0x00000000fff0 + + + pf0_rbar_cap_bar1 + PF0 RBAR CAP BAR1 + 0x000000000000 + + + pf0_rbar_cap_bar2 + PF0 RBAR CAP BAR2 + 0x000000000000 + + + pf0_rbar_cap_bar3 + PF0 RBAR CAP BAR3 + 0x000000000000 + + + pf0_rbar_cap_bar4 + PF0 RBAR CAP BAR4 + 0x000000000000 + + + pf0_rbar_cap_bar5 + PF0 RBAR CAP BAR5 + 0x000000000000 + + + pf1_rbar_cap_bar0 + PF1 RBAR CAP BAR0 + 0x00000000fff0 + + + pf1_rbar_cap_bar1 + PF1 RBAR CAP BAR1 + 0x000000000000 + + + pf1_rbar_cap_bar2 + PF1 RBAR CAP BAR2 + 0x000000000000 + + + pf1_rbar_cap_bar3 + PF1 RBAR CAP BAR3 + 0x000000000000 + + + pf1_rbar_cap_bar4 + PF1 RBAR CAP BAR4 + 0x000000000000 + + + pf1_rbar_cap_bar5 + PF1 RBAR CAP BAR5 + 0x000000000000 + + + pf2_rbar_cap_bar0 + PF2 RBAR CAP BAR0 + 0x00000000fff0 + + + pf2_rbar_cap_bar1 + PF2 RBAR CAP BAR1 + 0x000000000000 + + + pf2_rbar_cap_bar2 + PF2 RBAR CAP BAR2 + 0x000000000000 + + + pf2_rbar_cap_bar3 + PF2 RBAR CAP BAR3 + 0x000000000000 + + + pf2_rbar_cap_bar4 + PF2 RBAR CAP BAR4 + 0x000000000000 + + + pf2_rbar_cap_bar5 + PF2 RBAR CAP BAR5 + 0x000000000000 + + + pf3_rbar_cap_bar0 + PF3 RBAR CAP BAR0 + 0x00000000fff0 + + + pf3_rbar_cap_bar1 + PF3 RBAR CAP BAR1 + 0x000000000000 + + + pf3_rbar_cap_bar2 + PF3 RBAR CAP BAR2 + 0x000000000000 + + + pf3_rbar_cap_bar3 + PF3 RBAR CAP BAR3 + 0x000000000000 + + + pf3_rbar_cap_bar4 + PF3 RBAR CAP BAR4 + 0x000000000000 + + + pf3_rbar_cap_bar5 + PF3 RBAR CAP BAR5 + 0x000000000000 + + + enable_multi_pcie + false + + + msix_type + MSI-X Type + HARD + + + VFG0_MSIX_CAP_PBA_OFFSET + vfg0 Msix Cap Pba Offset + 00000000 + + + VFG1_MSIX_CAP_PBA_OFFSET + vfg1 Msix Cap Pba Offset + 00000000 + + + VFG2_MSIX_CAP_PBA_OFFSET + vfg2 Msix Cap Pba Offset + 00000000 + + + VFG3_MSIX_CAP_PBA_OFFSET + vfg3 Msix Cap Pba Offset + 00000000 + + + VFG0_MSIX_CAP_TABLE_OFFSET + vfg0 Msix Cap table Offset + 00000000 + + + VFG1_MSIX_CAP_TABLE_OFFSET + vfg1 Msix Cap table Offset + 00000000 + + + VFG2_MSIX_CAP_TABLE_OFFSET + vfg2 Msix Cap table Offset + 00000000 + + + VFG3_MSIX_CAP_TABLE_OFFSET + vfg3 Msix Cap table Offset + 00000000 + + + VFG0_MSIX_CAP_TABLE_SIZE + vfg0 Msix Cap Table Size + 0 + + + VFG1_MSIX_CAP_TABLE_SIZE + vfg1 Msix Cap Table Size + 0 + + + VFG2_MSIX_CAP_TABLE_SIZE + vfg2 Msix Cap Table Size + 0 + + + VFG3_MSIX_CAP_TABLE_SIZE + vfg3 Msix Cap Table Size + 0 + + + disable_gt_loc + Disable GT loc constraint delivery + false + + + use_standard_interfaces + use standard interfaces for IPI design + false + + + dma_2rp + Truncate ports for 2RP DMA design + false + + + disable_user_clock_root + true + + + qdma_tph_msix_brams_dis + false + + + double_quad + false + + + enable_epyc_chipset_fix + false + + + MASTER_GT + GTHE4_CHANNEL_X49Y99 + + + enable_msix_32vec + false + + + broadcom_sbr_wa + false + + + user_interface_signals + false + + + link_training_signals + false + + + transmit_fc_interface + false + + + config_fc_interface + false + + + config_status_interface + false + + + config_mgmt_interface + false + + + rx_mesg_interface + false + + + config_tx_mesg_interface + false + + + config_interface + false + + + + false + + + + + + config_ctrl_interface + false + + + config_pwr_mgmt_interface + false + + + interrupt_interface + false + + + descrambler_pipe_debug_signals + false + + + + false + + + + + + descrambler_user_interface_signals + false + + + exdes_simulation_tab + false + + + tl_tx_mux_strict_priority + false + + + + + UltraScale+ Integrated Block (PCIE4C) for PCI Express + + XPM_CDC + XPM_FIFO + XPM_MEMORY + + 10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_eab86dfe + READ_FIRST + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + xdma_v4_1_8_blk_mem_64_reg_be + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Simple_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + true + + + + + + ECC + false + + + + true + + + + + + softecc + false + + + + true + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + 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C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 2.618 mW + + + + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f92be8b1 + 18 + 36 + 72 + 144 + 288 + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_eab86dfe + READ_FIRST + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + xdma_v4_1_8_blk_mem_64_noreg_be + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Simple_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + true + + + + + + ECC + false + + + + true + + + + + + softecc + false + + + + true + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + 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+ + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + M_AXIS_H2C_3 + M_AXIS_H2C_3 + + + + + + + TDATA + + + m_axis_h2c_tdata_3 + + + + + TKEEP + + + m_axis_h2c_tkeep_3 + + + + + TLAST + + + m_axis_h2c_tlast_3 + + + + + TREADY + + + m_axis_h2c_tready_3 + + + + + TUSER + + + m_axis_h2c_tuser_3 + + + + + TVALID + + + m_axis_h2c_tvalid_3 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + m_axis_cq + m_axis_cq + The Completer Request interface is used to transmit Completion TLP's to the Client Application + + + + + + + TDATA + + + m_axis_cq_tdata_sd + + + + + TKEEP + + + m_axis_cq_tkeep_sd + + + + + TLAST + + + m_axis_cq_tlast_sd + + + + + TREADY + + + m_axis_cq_tready_sd + + + + + TUSER + + + m_axis_cq_tuser_sd + + + + + TVALID + + + m_axis_cq_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axis_cc + s_axis_cc + The Completer Completion Interface is used to transmit Completion TLP's + + + + + + + TDATA + + + s_axis_cc_tdata_sd + + + + + TKEEP + + + s_axis_cc_tkeep_sd + + + + + TLAST + + + s_axis_cc_tlast_sd + + + + + TREADY + + + s_axis_cc_tready_sd + + + + + TUSER + + + s_axis_cc_tuser_sd + + + + + TVALID + + + s_axis_cc_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axis_rq + s_axis_rq + The Requestor Request interface received requests TLP's from the Client Application + + + + + + + TDATA + + + s_axis_rq_tdata_sd + + + + + TKEEP + + + s_axis_rq_tkeep_sd + + + + + TLAST + + + s_axis_rq_tlast_sd + + + + + TREADY + + + s_axis_rq_tready_sd + + + + + TUSER + + + s_axis_rq_tuser_sd + + + + + TVALID + + + s_axis_rq_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + m_axis_rc + m_axis_rc + The Requestor Completer interface transmits completions to the client application + + + + + + + TDATA + + + m_axis_rc_tdata_sd + + + + + TKEEP + + + m_axis_rc_tkeep_sd + + + + + TLAST + + + m_axis_rc_tlast_sd + + + + + TREADY + + + m_axis_rc_tready_sd + + + + + TUSER + + + m_axis_rc_tuser_sd + + + + + TVALID + + + m_axis_rc_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + pcie4_cfg_mesg_tx + pcie4_cfg_mesg_tx + Configuration Transmit Message Interface + + + + + + + TRANSMIT + + + cfg_msg_transmit_sd + + + + + TRANSMIT_DATA + + + cfg_msg_transmit_data_sd + + + + + TRANSMIT_DONE + + + cfg_msg_transmit_done_sd + + + + + TRANSMIT_TYPE + + + cfg_msg_transmit_type_sd + + + + + + + false + + + + + + pcie4_cfg_mesg_rcvd + pcie4_cfg_mesg_rcvd + Configuration Received Message Interface + + + + + + + recd + + + cfg_msg_received_sd + + + + + recd_data + + + cfg_msg_received_data_sd + + + + + recd_type + + + cfg_msg_received_type_sd + + + + + + + false + + + + + + pcie4_cfg_status + pcie4_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req_sd + + + + + cq_np_req_count + + + pcie_cq_np_req_count_sd + + + + + current_speed + + + cfg_current_speed_sd + + + + + err_cor_out + + + cfg_err_cor_out_sd + + + + + err_fatal_out + + + cfg_err_fatal_out_sd + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out_sd + + + + + function_status + + + cfg_function_status_sd + + + + + local_error_out + + + cfg_local_error_out_sd + + + + + ltssm_state + + + cfg_ltssm_state_sd + + + + + max_payload + + + cfg_max_payload_sd + + + + + max_read_req + + + cfg_max_read_req_sd + + + + + negotiated_width + + + cfg_negotiated_width_sd + + + + + phy_link_down + + + cfg_phy_link_down_sd + + + + + phy_link_status + + + cfg_phy_link_status_sd + + + + + pl_status_change + + + cfg_pl_status_change_sd + + + + + rq_seq_num0 + + + pcie_rq_seq_num0_sd + + + + + rq_seq_num1 + + + pcie_rq_seq_num1_sd + + + + + rq_seq_num_vld0 + + + pcie_rq_seq_num_vld0_sd + + + + + rq_seq_num_vld1 + + + pcie_rq_seq_num_vld1_sd + + + + + tfc_npd_av + + + pcie_tfc_npd_av_sd + + + + + tfc_nph_av + + + pcie_tfc_nph_av_sd + + + + + + + false + + + + + + pcie4_cfg_status_if + pcie4_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req_sd + + + + + cq_np_req_count + + + pcie_cq_np_req_count_sd + + + + + current_speed + + + cfg_current_speed_sd + + + + + err_cor_out + + + cfg_err_cor_out_sd + + + + + err_fatal_out + + + cfg_err_fatal_out_sd + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out_sd + + + + + function_status + + + cfg_function_status_sd + + + + + local_error_out + + + cfg_local_error_out_sd + + + + + ltssm_state + + + cfg_ltssm_state_sd + + + + + max_payload + + + cfg_max_payload_sd + + + + + max_read_req + + + cfg_max_read_req_sd + + + + + negotiated_width + + + cfg_negotiated_width_sd + + + + + phy_link_down + + + cfg_phy_link_down_sd + + + + + phy_link_status + + + cfg_phy_link_status_sd + + + + + pl_status_change + + + cfg_pl_status_change_sd + + + + + rq_seq_num0 + + + pcie_rq_seq_num0_sd + + + + + rq_seq_num1 + + + pcie_rq_seq_num1_sd + + + + + rq_seq_num_vld0 + + + pcie_rq_seq_num_vld0_sd + + + + + rq_seq_num_vld1 + + + pcie_rq_seq_num_vld1_sd + + + + + + + false + + + + + + pcie4_transmit_fc_if + pcie4_transmit_fc + Transmit Flow Control Interfce + + + + + + + npd_av + + + pcie_tfc_npd_av_sd + + + + + nph_av + + + pcie_tfc_nph_av_sd + + + + + + + false + + + + + + pcie4_rbar + pcie4_rbar + Resizable bar Interface + + + + + + + bar_size + + + rbar_bar_size_sd + + + + + function_number + + + rbar_function_number_sd + + + + + write_enable_bar0 + + + rbar_write_enable_bar0_sd + + + + + write_enable_bar1 + + + rbar_write_enable_bar1_sd + + + + + write_enable_bar2 + + + rbar_write_enable_bar2_sd + + + + + write_enable_bar3 + + + rbar_write_enable_bar3_sd + + + + + write_enable_bar4 + + + rbar_write_enable_bar4_sd + + + + + write_enable_bar5 + + + rbar_write_enable_bar5_sd + + + + + + + false + + + + + + pcie4_cfg_control + pcie4_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + ds_bus_number + + + cfg_ds_bus_number_sd + + + + + ds_device_number + + + cfg_ds_device_number_sd + + + + + ds_function_number + + + cfg_ds_function_number_sd + + + + + ds_port_number + + + cfg_ds_port_number_sd + + + + + dsn + + + cfg_dsn_sd + + + + + err_cor_in + + + cfg_err_cor_in_sd + + + + + err_uncor_in + + + cfg_err_uncor_in_sd + + + + + flr_done + + + cfg_flr_done_sd + + + + + flr_in_process + + + cfg_flr_in_process_sd + + + + + hot_reset_out + + + cfg_hot_reset_out_sd + + + + + link_training_enable + + + cfg_link_training_enable_sd + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process_sd + + + + + + + false + + + + + + pcie4_cfg_control_if + pcie4_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + ds_bus_number + + + cfg_ds_bus_number_sd + + + + + ds_device_number + + + cfg_ds_device_number_sd + + + + + ds_function_number + + + cfg_ds_function_number_sd + + + + + ds_port_number + + + cfg_ds_port_number_sd + + + + + dsn + + + cfg_dsn_sd + + + + + err_cor_in + + + cfg_err_cor_in_sd + + + + + err_uncor_in + + + cfg_err_uncor_in_sd + + + + + flr_done + + + cfg_flr_done_sd + + + + + flr_in_process + + + cfg_flr_in_process_sd + + + + + hot_reset_out + + + cfg_hot_reset_out_sd + + + + + link_training_enable + + + cfg_link_training_enable_sd + + + + + rbar_function_number + + + rbar_function_number_sd + + + + + rbar_size + + + rbar_bar_size_sd + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process_sd + + + + + write_enable_rbar0 + + + rbar_write_enable_bar0_sd + + + + + write_enable_rbar1 + + + rbar_write_enable_bar1_sd + + + + + write_enable_rbar2 + + + rbar_write_enable_bar2_sd + + + + + write_enable_rbar3 + + + rbar_write_enable_bar3_sd + + + + + write_enable_rbar4 + + + rbar_write_enable_bar4_sd + + + + + write_enable_rbar5 + + + rbar_write_enable_bar5_sd + + + + + + + false + + + + + + pcie4_cfg_fc + pcie_cfg_fc + Configuration Flow Control INTERFACE + + + + + + + NPH + + + cfg_fc_nph_sd + + + + + SEL + + + cfg_fc_sel_sd + + + + + + + false + + + + + + pcie4_cfg_msi + pcie4_cfg_msi + PCIE MSI interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr_sd + + + + + data + + + cfg_interrupt_msi_data_sd + + + + + enable + + + cfg_interrupt_msi_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msi_int_sd + + + + + mask_update + + + cfg_interrupt_msi_mask_update_sd + + + + + pending_status + + + cfg_interrupt_msi_pending_status_sd + + + + + pending_status_data_enable + + + cfg_interrupt_msi_pending_status_data_enable_sd + + + + + pending_status_function_num + + + cfg_interrupt_msi_pending_status_function_num_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + tph_present + + + cfg_interrupt_msi_tph_present_sd + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag_sd + + + + + tph_type + + + cfg_interrupt_msi_tph_type_sd + + + + + + + false + + + + + + pcie4_cfg_msix_external + pcie4_cfg_msix_external + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_external_msix_with_msi_if + pcie4_cfg_external_msix_with_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_external_msix + pcie4_cfg_external_msix + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_msix_internal + pcie4_cfg_msix_internal + PCIE MSIx Int Interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + mint_vector + + + cfg_interrupt_msi_int_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + tph_present + + + cfg_interrupt_msi_tph_present_sd + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag_sd + + + + + tph_type + + + cfg_interrupt_msi_tph_type_sd + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending_sd + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_msix_internal_if + pcie4_cfg_msix_internal + PCIE MSIx Int Interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + mint_vector + + + cfg_interrupt_msi_int_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + tph_present + + + cfg_interrupt_msi_tph_present_sd + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag_sd + + + + + tph_type + + + cfg_interrupt_msi_tph_type_sd + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending_sd + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_external_msix_without_msi_if + pcie4_cfg_external_msix_without_msi + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_interrupt + pcie4_cfg_interrupt + PCIE Legacy Interrupt + + + + + + + INTx_VECTOR + + + cfg_interrupt_int_sd + + + + + PENDING + + + cfg_interrupt_pending_sd + + + + + SENT + + + cfg_interrupt_sent_sd + + + + + + + false + + + + + + pcie_cfg_mgmt_sd + pcie4_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr_sd + + + + + BYTE_EN + + + cfg_mgmt_byte_enable_sd + + + + + DEBUG_ACCESS + + + cfg_mgmt_type1_cfg_reg_access_sd + + + + + FUNCTION_NUMBER + + + cfg_mgmt_function_number_sd + + + + + READ_DATA + + + cfg_mgmt_read_data_sd + + + + + READ_EN + + + cfg_mgmt_read_sd + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done_sd + + + + + WRITE_DATA + + + cfg_mgmt_write_data_sd + + + + + WRITE_EN + + + cfg_mgmt_write_sd + + + + + + + false + + + + + + pcie_cfg_mgmt_if + pcie4_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr_sd + + + + + BYTE_EN + + + cfg_mgmt_byte_enable_sd + + + + + DEBUG_ACCESS + + + cfg_mgmt_type1_cfg_reg_access_sd + + + + + FUNCTION_NUMBER + + + cfg_mgmt_function_number_sd + + + + + READ_DATA + + + cfg_mgmt_read_data_sd + + + + + READ_EN + + + cfg_mgmt_read_sd + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done_sd + + + + + WRITE_DATA + + + cfg_mgmt_write_data_sd + + + + + WRITE_EN + + + cfg_mgmt_write_sd + + + + + + + false + + + + + + pcie_cfg_mgmt + pcie_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr + + + + + BYTE_EN + + + cfg_mgmt_byte_enable + + + + + READ_DATA + + + cfg_mgmt_read_data + + + + + READ_EN + + + cfg_mgmt_read + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done + + + + + TYPE1_CFG_REG_ACCESS + + + cfg_mgmt_type1_cfg_reg_access + + + + + WRITE_DATA + + + cfg_mgmt_write_data + + + + + WRITE_EN + + + cfg_mgmt_write + + + + + + + true + + + + + + pcie_mgt + pcie_7x_mgt + + + + + + + rxn + + + pci_exp_rxn + + + + + rxp + + + pci_exp_rxp + + + + + txn + + + pci_exp_txn + + + + + txp + + + pci_exp_txp + + + + + + BOARD.ASSOCIATED_PARAM + PCIE_BOARD_INTERFACE + + + + required + + + + + + + + + true + + + + + + drp + drp + DRP interface + + + + + + + DADDR + + + drp_addr + + + + + DEN + + + drp_en + + + + + DI + + + drp_di + + + + + DO + + + drp_do + + + + + DRDY + + + drp_rdy + + + + + DWE + + + drp_we + + + + + + + false + + + + + + pcie_debug_ports + pcie_debug_ports + PCIe Debug Interface + + + + + + + cfg_current_speed + + + cfg_current_speed_o + + + + + cfg_err_cor + + + cfg_err_cor_o + + + + + cfg_err_fatal + + + cfg_err_fatal_o + + + + + cfg_err_nonfatal + + + cfg_err_nonfatal_o + + + + + cfg_local_error + + + cfg_local_error_o + + + + + cfg_local_error_valid + + + cfg_local_error_valid_o + + + + + cfg_ltssm_state + + + cfg_ltssm_state_o + + + + + cfg_negotiated_width + + + cfg_negotiated_width_o + + + + + + + false + + + + + + pcie4_pcie_id + pcie4_pcie_id + PCIE 4 PCIE ID interface + + + + + + + subsys_vend_id + + + cfg_subsys_vend_id + + + + + vend_id + + + cfg_vend_id + + + + + + + false + + + + + + pcie4_pcie_id_pf0 + pcie4_pcie_id_pf0 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf0 + + + cfg_dev_id_pf0 + + + + + rev_id_pf0 + + + cfg_rev_id_pf0 + + + + + subsys_id_pf0 + + + cfg_subsys_id_pf0 + + + + + + + false + + + + + + pcie4_pcie_id_pf1 + pcie4_pcie_id_pf1 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf1 + + + cfg_dev_id_pf1 + + + + + rev_id_pf1 + + + cfg_rev_id_pf1 + + + + + subsys_id_pf1 + + + cfg_subsys_id_pf1 + + + + + + + false + + + + + + pcie4_pcie_id_pf2 + pcie4_pcie_id_pf2 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf2 + + + cfg_dev_id_pf2 + + + + + rev_id_pf2 + + + cfg_rev_id_pf2 + + + + + subsys_id_pf2 + + + cfg_subsys_id_pf2 + + + + + + + false + + + + + + pcie4_pcie_id_pf3 + pcie4_pcie_id_pf3 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf3 + + + cfg_dev_id_pf3 + + + + + rev_id_pf3 + + + cfg_rev_id_pf3 + + + + + subsys_id_pf3 + + + cfg_subsys_id_pf3 + + + + + + + false + + + + + + pcie3_7x_transceiver_debug + pcie3_7x_transceiver_debug + Transceiver Debug Interface of pcie3_7x + + + + + + + cpll_lock + + + pipe_cpll_lock + + + + + debug + + + pipe_debug + + + + + debug_0 + + + pipe_debug_0 + + + + + debug_1 + + + pipe_debug_1 + + + + + debug_2 + + + pipe_debug_2 + + + + + debug_3 + + + pipe_debug_3 + + + + + debug_4 + + + pipe_debug_4 + + + + + debug_5 + + + pipe_debug_5 + + + + + debug_6 + + + pipe_debug_6 + + + + + debug_7 + + + pipe_debug_7 + + + + + debug_8 + + + pipe_debug_8 + + + + + debug_9 + + + pipe_debug_9 + + + + + dmonitorout + + + pipe_dmonitorout + + + + + drp_fsm + + + pipe_drp_fsm + + + + + eyescandataerror + + + pipe_eyescandataerror + + + + + gt_ch_drp_rdy + + + gt_ch_drp_rdy + + + + + loopback + + + pipe_loopback + + + + + qpll_lock + + + pipe_qpll_lock + + + + + qrst_fsm + + + pipe_qrst_fsm + + + + + qrst_idle + + + pipe_qrst_idle + + + + + rate_fsm + + + pipe_rate_fsm + + + + + rate_idle + + + pipe_rate_idle + + + + + rst_fsm + + + pipe_rst_fsm + + + + + rst_idle + + + pipe_rst_idle + + + + + rxbufstatus + + + pipe_rxbufstatus + + + + + rxcommadet + + + pipe_rxcommadet + + + + + rxdisperr + + + pipe_rxdisperr + + + + + rxdlysresetdone + + + pipe_rxdlysresetdone + + + + + rxnotintable + + + pipe_rxnotintable + + + + + rxphaligndone + + + pipe_rxphaligndone + + + + + rxpmaresetdone + + + pipe_rxpmaresetdone + + + + + rxprbscntreset + + + pipe_rxprbscntreset + + + + + rxprbserr + + + pipe_rxprbserr + + + + + rxprbssel + + + pipe_rxprbssel + + + + + rxstatus + + + pipe_rxstatus + + + + + rxsyncdone + + + pipe_rxsyncdone + + + + + sync_fsm_rx + + + pipe_sync_fsm_rx + + + + + sync_fsm_tx + + + pipe_sync_fsm_tx + + + + + txdlysresetdone + + + pipe_txdlysresetdone + + + + + txinhibit + + + pipe_txinhibit + + + + + txphaligndone + + + pipe_txphaligndone + + + + + txphinitdone + + + pipe_txphinitdone + + + + + txprbsforceerr + + + pipe_txprbsforceerr + + + + + txprbssel + + + pipe_txprbssel + + + + + + + false + + + + + + pcie3_us_transceiver_debug + pcie3_us_transceiver_debug + Transceiver Debug Interface of pcie3_us + + + + + + + bufgtdiv + + + gt_bufgtdiv + + + + + cpll_lock + + + gt_cplllock + + + + + dmonfiforeset + + + gt_dmonfiforeset + + + + + dmonitorclk + + + gt_dmonitorclk + + + + + dmonitorout + + + gt_dmonitorout + + + + + eyescandataerror + + + gt_eyescandataerror + + + + + gtpowergood + + + gt_gtpowergood + + + + + loopback + + + gt_loopback + + + + + pcieuserratedone + + + gt_pcieuserratedone + + + + + pcieuserratestart + + + gt_pcieuserratestart + + + + + phystatus + + + gt_phystatus + + + + + prst_n + + + phy_prst_n + + + + + qpll_lock + + + gt_qpll1lock + + + + + rate_idle + + + gt_pcierateidle + + + + + rrst_n + + + phy_rrst_n + + + + + rst_fsm + + + phy_rst_fsm + + + + + rst_idle + + + phy_rst_idle + + + + + rxbufstatus + + + gt_rxbufstatus + + + + + rxcdrlock + + + gt_rxcdrlock + + + + + rxcommadet + + + gt_rxcommadet + + + + + rxdlysresetdone + + + gt_rxdlysresetdone + + + + + rxeq_fsm + + + phy_rxeq_fsm + + + + + rxoutclk + + + gt_rxoutclk + + + + + rxphaligndone + + + gt_rxphaligndone + + + + + rxpmaresetdone + + + gt_rxpmaresetdone + + + + + rxprbscntreset + + + gt_rxprbscntreset + + + + + rxprbserr + + + gt_rxprbserr + + + + + rxprbssel + + + gt_rxprbssel + + + + + rxrecclkout + + + gt_rxrecclkout + + + + + rxresetdone + + + gt_rxresetdone + + + + + rxstatus + + + gt_rxstatus + + + + + rxsyncdone + + + gt_rxsyncdone + + + + + rxvalid + + + gt_rxvalid + + + + + txdlysresetdone + + + gt_txdlysresetdone + + + + + txelecidle + + + gt_txelecidle + + + + + txeq_ctrl + + + phy_txeq_ctrl + + + + + txeq_fsm + + + phy_txeq_fsm + + + + + txeq_preset + + + phy_txeq_preset + + + + + txinhibit + + + gt_txinhibit + + + + + txphaligndone + + + gt_txphaligndone + + + + + txphinitdone + + + gt_txphinitdone + + + + + txprbsforceerr + + + gt_txprbsforceerr + + + + + txprbssel + + + gt_txprbssel + + + + + txresetdone + + + gt_txresetdone + + + + + + + false + + + + + + pcie4_us_plus_transceiver_debug + pcie4_us_plus_transceiver_debug + Transceiver Debug Interface of pcie4_us_plus + + + + + + + bufgtdiv + + + gt_bufgtdiv + + + + + cpll_lock + + + gt_cplllock + + + + + dmonfiforeset + + + gt_dmonfiforeset + + + + + dmonitorclk + + + gt_dmonitorclk + + + + + dmonitorout + + + gt_dmonitorout + + + + + eyescandataerror + + + gt_eyescandataerror + + + + + gen34_eios_det + + + gt_gen34_eios_det + + + + + gtpowergood + + + gt_gtpowergood + + + + + loopback + + + gt_loopback + + + + + pcieuserratedone + + + gt_pcieuserratedone + + + + + pcieuserratestart + + + gt_pcieuserratestart + + + + + phystatus + + + gt_phystatus + + + + + prst_n + + + phy_prst_n + + + + + qpll0_lock + + + gt_qpll0lock + + + + + qpll1_lock + + + gt_qpll1lock + + + + + rate_idle + + + gt_pcierateidle + + + + + rrst_n + + + phy_rrst_n + + + + + rst_fsm + + + phy_rst_fsm + + + + + rst_idle + + + phy_rst_idle + + + + + rxbufreset + + + gt_rxbufreset + + + + + rxbufstatus + + + gt_rxbufstatus + + + + + rxcdrlock + + + gt_rxcdrlock + + + + + rxcdrreset + + + gt_rxcdrreset + + + + + rxcommadet + + + gt_rxcommadet + + + + + rxdfelpmreset + + + gt_rxdfelpmreset + + + + + rxdlysresetdone + + + gt_rxdlysresetdone + + + + + rxeq_fsm + + + phy_rxeq_fsm + + + + + rxoutclk + + + gt_rxoutclk + + + + + rxoutclkfabric + + + gt_rxoutclkfabric + + + + + rxoutclkpcs + + + gt_rxoutclkpcs + + + + + rxpcsreset + + + gt_rxpcsreset + + + + + rxphaligndone + + + gt_rxphaligndone + + + + + rxpmareset + + + gt_rxpmareset + + + + + rxpmaresetdone + + + gt_rxpmaresetdone + + + + + rxprbscntreset + + + gt_rxprbscntreset + + + + + rxprbserr + + + gt_rxprbserr + + + + + rxprbslocked + + + gt_rxprbslocked + + + + + rxprbssel + + + gt_rxprbssel + + + + + rxrecclkout + + + gt_rxrecclkout + + + + + rxresetdone + + + gt_rxresetdone + + + + + rxstatus + + + gt_rxstatus + + + + + rxsyncdone + + + gt_rxsyncdone + + + + + rxvalid + + + gt_rxvalid + + + + + txdlysresetdone + + + gt_txdlysresetdone + + + + + txelecidle + + + gt_txelecidle + + + + + txeq_ctrl + + + phy_txeq_ctrl + + + + + txeq_fsm + + + phy_txeq_fsm + + + + + txeq_preset + + + phy_txeq_preset + + + + + txinhibit + + + gt_txinhibit + + + + + txoutclk + + + gt_txoutclk + + + + + txoutclkfabric + + + gt_txoutclkfabric + + + + + txoutclkpcs + + + gt_txoutclkpcs + + + + + txpcsreset + + + gt_txpcsreset + + + + + txphaligndone + + + gt_txphaligndone + + + + + txphinitdone + + + gt_txphinitdone + + + + + txpmareset + + + gt_txpmareset + + + + + txpmaresetdone + + + gt_txpmaresetdone + + + + + txprbsforceerr + + + gt_txprbsforceerr + + + + + txprbssel + + + gt_txprbssel + + + + + txprogdivresetdone + + + gt_txprogdivresetdone + + + + + txresetdone + + + gt_txresetdone + + + + + txsyncdone + + + gt_txsyncdone + + + + + + + false + + + + + + pcie3_us_gt_if + pcie3_us_gt_if + GT Interface + + + + + + + bufgtce_out + + + bufgtce_us_out + + + + + bufgtcemask_out + + + bufgtcemask_us_out + + + + + bufgtdiv_out + + + bufgtdiv_us_out + + + + + bufgtreset_out + + + bufgtreset_us_out + + + + + bufgtrstmask_out + + + bufgtrstmask_us_out + + + + + cplllock_out + + + cplllock_us_out + + + + + cpllpd_in + + + cpllpd_us_in + + + + + cpllreset_in + + + cpllreset_us_in + + + + + dmonfiforeset_in + + + dmonfiforeset_us_in + + + + + dmonitorclk_in + + + dmonitorclk_us_in + + + + + dmonitorout_out + + + dmonitorout_us_out + + + + + drpaddr_in + + + drpaddr_us_in + + + + + drpclk_in + + + drpclk_us_in + + + + + drpdi_in + + + drpdi_us_in + + + + + drpdo_out + + + drpdo_us_out + + + + + drpen_in + + + drpen_us_in + + + + + drprdy_out + + + drprdy_us_out + + + + + drpwe_in + + + drpwe_us_in + + + + + eyescandataerror_out + + + eyescandataerror_us_out + + + + + eyescanreset_in + + + eyescanreset_us_in + + + + + gthrxn_in + + + gthrxn_us_in + + + + + gthrxp_in + + + gthrxp_us_in + + + + + gthtxn_out + + + gthtxn_us_out + + + + + gthtxp_out + + + gthtxp_us_out + + + + + gtpowergood_out + + + gtpowergood_us_out + + + + + gtrefclk0_in + + + gtrefclk0_us_in + + + + + gtrefclk01_in + + + gtrefclk01_us_in + + + + + gtrxreset_in + + + gtrxreset_us_in + + + + + gttxreset_in + + + gttxreset_us_in + + + + + gtwiz_reset_rx_done_in + + + gtwiz_reset_rx_done_us_in + + + + + gtwiz_reset_tx_done_in + + + gtwiz_reset_tx_done_us_in + + + + + gtwiz_userclk_rx_active_in + + + gtwiz_userclk_rx_active_us_in + + + + + gtwiz_userclk_tx_active_in + + + gtwiz_userclk_tx_active_us_in + + + + + gtwiz_userclk_tx_reset_in + + + gtwiz_userclk_tx_reset_us_in + + + + + loopback_in + + + loopback_us_in + + + + + pcieeqrxeqadaptdone_in + + + pcieeqrxeqadaptdone_us_in + + + + + pcierategen3_out + + + pcierategen3_us_out + + + + + pcierateidle_out + + + pcierateidle_us_out + + + + + pcierateqpllpd_out + + + pcierateqpllpd_us_out + + + + + pcierateqpllreset_out + + + pcierateqpllreset_us_out + + + + + pcierstidle_in + + + pcierstidle_us_in + + + + + pciersttxsyncstart_in + + + pciersttxsyncstart_us_in + + + + + pciesynctxsyncdone_out + + + pciesynctxsyncdone_us_out + + + + + pcieusergen3rdy_out + + + pcieusergen3rdy_us_out + + + + + pcieuserphystatusrst_out + + + pcieuserphystatusrst_us_out + + + + + pcieuserratedone_in + + + pcieuserratedone_us_in + + + + + pcieuserratestart_out + + + pcieuserratestart_us_out + + + + + pcsrsvdin_in + + + pcsrsvdin_us_in + + + + + pcsrsvdout_out + + + pcsrsvdout_us_out + + + + + phystatus_out + + + phystatus_us_out + + + + + qpll0clk_in + + + qpll0clk_us_in + + + + + qpll0refclk_in + + + qpll0refclk_us_in + + + + + qpll1clk_in + + + qpll1clk_us_in + + + + + qpll1lock_out + + + qpll1lock_us_out + + + + + qpll1outclk_out + + + qpll1outclk_us_out + + + + + qpll1outrefclk_out + + + qpll1outrefclk_us_out + + + + + qpll1pd_in + + + qpll1pd_us_in + + + + + qpll1refclk_in + + + qpll1refclk_us_in + + + + + qpll1reset_in + + + qpll1reset_us_in + + + + + qpllrsvd2_in + + + qpllrsvd2_us_in + + + + + qpllrsvd3_in + + + qpllrsvd3_us_in + + + + + rx8b10ben_in + + + rx8b10ben_us_in + + + + + rxbufreset_in + + + rxbufreset_us_in + + + + + rxbufstatus_out + + + rxbufstatus_us_out + + + + + rxbyteisaligned_out + + + rxbyteisaligned_us_out + + + + + rxbyterealign_out + + + rxbyterealign_us_out + + + + + rxcdrhold_in + + + rxcdrhold_us_in + + + + + rxcdrlock_out + + + rxcdrlock_us_out + + + + + rxclkcorcnt_out + + + rxclkcorcnt_us_out + + + + + rxcommadet_out + + + rxcommadet_us_out + + + + + rxcommadeten_in + + + rxcommadeten_us_in + + + + + rxctrl0_out + + + rxctrl0_us_out + + + + + rxctrl1_out + + + rxctrl1_us_out + + + + + rxctrl2_out + + + rxctrl2_us_out + + + + + rxctrl3_out + + + rxctrl3_us_out + + + + + rxdata_out + + + rxdata_us_out + + + + + rxdfeagchold_in + + + rxdfeagchold_us_in + + + + + rxdfecfokhold_in + + + rxdfecfokhold_us_in + + + + + rxdfekhhold_in + + + rxdfekhhold_us_in + + + + + rxdfelfhold_in + + + rxdfelfhold_us_in + + + + + rxdfetap2hold_in + + + rxdfetap2hold_us_in + + + + + rxdfetap3hold_in + + + rxdfetap3hold_us_in + + + + + rxdfetap4hold_in + + + rxdfetap4hold_us_in + + + + + rxdfetap5hold_in + + + rxdfetap5hold_us_in + + + + + rxdfetap6hold_in + + + rxdfetap6hold_us_in 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rxoshold_in + + + rxoshold_us_in + + + + + rxoutclk_out + + + rxoutclk_us_out + + + + + rxpcommaalignen_in + + + rxpcommaalignen_us_in + + + + + rxpd_in + + + rxpd_us_in + + + + + rxphaligndone_out + + + rxphaligndone_us_out + + + + + rxpmaresetdone_out + + + rxpmaresetdone_us_out + + + + + rxpolarity_in + + + rxpolarity_us_in + + + + + rxprbscntreset_in + + + rxprbscntreset_us_in + + + + + rxprbserr_out + + + rxprbserr_us_out + + + + + rxprbslocked_out + + + rxprbslocked_us_out + + + + + rxprbssel_in + + + rxprbssel_us_in + + + + + rxprgdivresetdone_out + + + rxprgdivresetdone_us_out + + + + + rxprogdivreset_in + + + rxprogdivreset_us_in + + + + + rxrate_in + + + rxrate_us_in + + + + + rxratedone_out + + + rxratedone_us_out + + + + + rxratemode_in + + + rxratemode_us_in + + + + + rxresetdone_out + + + rxresetdone_us_out + + + + + rxslide_in + + + rxslide_us_in + + + + + rxstatus_out + + + rxstatus_us_out + + + + + rxsyncdone_out + + + rxsyncdone_us_out + + + + + rxuserrdy_in + + + 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rxoutclk_usp_out + + + + + rxoutclkfabric_out + + + rxoutclkfabric_usp_out + + + + + rxoutclkpcs_out + + + rxoutclkpcs_usp_out + + + + + rxpcommaalignen_in + + + rxpcommaalignen_usp_in + + + + + rxpcsreset_in + + + rxpcsreset_usp_in + + + + + rxpd_in + + + rxpd_usp_in + + + + + rxphaligndone_out + + + rxphaligndone_usp_out + + + + + rxpmareset_in + + + rxpmareset_usp_in + + + + + rxpmaresetdone_out + + + rxpmaresetdone_usp_out + + + + + rxpolarity_in + + + rxpolarity_usp_in + + + + + rxprbscntreset_in + + + rxprbscntreset_usp_in + + + + + rxprbserr_out + + + rxprbserr_usp_out + + + + + rxprbslocked_out + + + rxprbslocked_usp_out + + + + + rxprbssel_in + + + rxprbssel_usp_in + + + + + rxprogdivreset_in + + + rxprogdivreset_usp_in + + + + + rxrate_in + + + rxrate_usp_in + + + + + rxratedone_out + + + rxratedone_usp_out + + + + + rxratemode_in + + + rxratemode_usp_in + + + + + rxrecclkout_out + + + rxrecclkout_usp_out + + + + + rxresetdone_out + + + rxresetdone_usp_out + + + + + rxslide_in + + + rxslide_usp_in + + + + + rxstatus_out + + + rxstatus_usp_out + + + + + rxsyncdone_out + + + rxsyncdone_usp_out + + + + + rxtermination_in + + + rxtermination_usp_in + + + + + rxuserrdy_in + + + rxuserrdy_usp_in + + + + + rxusrclk2_in + + + rxusrclk2_usp_in + + + + + rxusrclk_in + + + rxusrclk_usp_in + + + + + rxvalid_out + + + rxvalid_usp_out + + + + + tx8b10ben_in + + + tx8b10ben_usp_in + + + + + txctrl0_in + + + txctrl0_usp_in + + + + + txctrl1_in + + + txctrl1_usp_in + + + + + txctrl2_in + + + txctrl2_usp_in + + + + + txdata_in + + + txdata_usp_in + + + + + txdeemph_in + + + txdeemph_usp_in + + + + + txdetectrx_in + + + txdetectrx_usp_in + + + + + txdiffctrl_in + + + txdiffctrl_usp_in + + + + + txdlybypass_in + + + txdlybypass_usp_in + + + + + txdlyen_in + + + txdlyen_usp_in + + + + + txdlyhold_in + + + txdlyhold_usp_in + + + + + txdlyovrden_in + + + txdlyovrden_usp_in + + + + + txdlysreset_in + + + txdlysreset_usp_in + + + + + txdlysresetdone_out + + + txdlysresetdone_usp_out + + + + + txdlyupdown_in + + + txdlyupdown_usp_in + + + + + txelecidle_in + + + txelecidle_usp_in + + + + + txmaincursor_in + + + txmaincursor_usp_in + + + + + txmargin_in + + + txmargin_usp_in + + + + + txoutclk_out + + + txoutclk_usp_out + + + + + txoutclkfabric_out + + + txoutclkfabric_usp_out + + + + + txoutclkpcs_out + + + txoutclkpcs_usp_out + + + + + txoutclksel_in + + + txoutclksel_usp_in + + + + + txpcsreset_in + + + txpcsreset_usp_in + + + + + txpd_in + + + txpd_usp_in + + + + + txpdelecidlemode_in + + + txpdelecidlemode_usp_in + + + + + txphalign_in + + + txphalign_usp_in + + + + + txphaligndone_out + + + txphaligndone_usp_out + + + + + txphalignen_in + + + txphalignen_usp_in + + + + + txphdlypd_in + + + txphdlypd_usp_in + + + + + txphdlyreset_in + + + txphdlyreset_usp_in + + + + + txphdlytstclk_in + + + txphdlytstclk_usp_in + + + + + txphinit_in + + + txphinit_usp_in + + + + + txphinitdone_out + + + txphinitdone_usp_out + + + + + txphovrden_in + + + txphovrden_usp_in + + + + + txpisopd_in + + + txpisopd_usp_in + + + + + txpmareset_in + + + txpmareset_usp_in + + + + + txpmaresetdone_out + + + txpmaresetdone_usp_out + + + + + txpostcursor_in + + + txpostcursor_usp_in + + + + + txprbsforceerr_in + + + txprbsforceerr_usp_in + + + + + txprbssel_in + + + txprbssel_usp_in + + + + + txprecursor_in + + + txprecursor_usp_in + + + + + txprgdivresetdone_out + + + txprgdivresetdone_usp_out + + + + + txprogdivreset_in + + + txprogdivreset_usp_in + + + + + txrate_in + + + txrate_usp_in + + + + + txresetdone_out + + + txresetdone_usp_out + + + + + txswing_in + + + txswing_usp_in + + + + + txsyncallin_in + + + txsyncallin_usp_in + + + + + txsyncdone_out + + + txsyncdone_usp_out + + + + + txsyncin_in + + + txsyncin_usp_in + + + + + txsyncmode_in + + + txsyncmode_usp_in + + + + + txsyncout_out + + + txsyncout_usp_out + + + + + txuserrdy_in + + + txuserrdy_usp_in + + + + + txusrclk2_in + + + txusrclk2_usp_in + + + + + txusrclk_in + + + txusrclk_usp_in + + + + + + + false + + + + + + pcie_ext_ch_gt + pcie_ext_ch_gt + GT DRP interface + + + + + + + DADDR + + + ext_ch_gt_drpaddr + + + + + DEN + + + ext_ch_gt_drpen + + + + + DI + + + ext_ch_gt_drpdi + + + + + DO + + + ext_ch_gt_drpdo + + + + + DRDY + + + ext_ch_gt_drprdy + + + + + DWE + + + ext_ch_gt_drpwe + + + + + + + false + + + + + + pcie_cfg_ext + pcie4_cfg_ext + Configuration Extend Interface + + + + + + + function_number + + + cfg_ext_function_number + + + + + read_data + + + cfg_ext_read_data + + + + + read_data_valid + + + cfg_ext_read_data_valid + + + + + read_received + + + cfg_ext_read_received + + + + + register_number + + + cfg_ext_register_number + + + + + write_byte_enable + + + cfg_ext_write_byte_enable + + + + + write_data + + + cfg_ext_write_data + + + + + write_received + + + cfg_ext_write_received + + + + + + + false + + + + + + CLK.ext_ch_gt_drpclk + + + + + + + CLK + + + ext_ch_gt_drpclk + + + + + + ASSOCIATED_BUSIF + pcie_ext_ch_gt + + + FREQ_HZ + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + pcie_ext_pipe_rp_usp + pcie3_ext_pipe_rp_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_in + + + + + COMMANDS_OUT + + + common_commands_out + + + + + RX_0 + + + pipe_rx_0_sigs + + + + + RX_1 + + + pipe_rx_1_sigs + + + + + RX_2 + + + pipe_rx_2_sigs + + + + + RX_3 + + + pipe_rx_3_sigs + + + + + RX_4 + + + pipe_rx_4_sigs + + + + + RX_5 + + + pipe_rx_5_sigs + + + + + RX_6 + + + pipe_rx_6_sigs + + + + + RX_7 + + + pipe_rx_7_sigs + + + + + RX_8 + + + pipe_rx_8_sigs + + + + + RX_9 + + + pipe_rx_9_sigs + + + + + RX_10 + + + pipe_rx_10_sigs + + + + + RX_11 + + + pipe_rx_11_sigs + + + + + RX_12 + + + pipe_rx_12_sigs + + + + + RX_13 + + + pipe_rx_13_sigs + + + + + RX_14 + + + pipe_rx_14_sigs + + + + + RX_15 + + + pipe_rx_15_sigs + + + + + TX_0 + + + pipe_tx_0_sigs + + + + + TX_1 + + + pipe_tx_1_sigs + + + + + TX_2 + + + pipe_tx_2_sigs + + + + + TX_3 + + + pipe_tx_3_sigs + + + + + TX_4 + + + pipe_tx_4_sigs + + + + + TX_5 + + + pipe_tx_5_sigs + + + + + TX_6 + + + pipe_tx_6_sigs + + + + + TX_7 + + + pipe_tx_7_sigs + + + + + TX_8 + + + pipe_tx_8_sigs + + + + + TX_9 + + + pipe_tx_9_sigs + + + + + TX_10 + + + pipe_tx_10_sigs + + + + + TX_11 + + + pipe_tx_11_sigs + + + + + TX_12 + + + pipe_tx_12_sigs + + + + + TX_13 + + + pipe_tx_13_sigs + + + + + TX_14 + + + pipe_tx_14_sigs + + + + + TX_15 + + + pipe_tx_15_sigs + + + + + + + false + + + + + + pcie_ext_pipe_ep_usp + pcie3_ext_pipe_ep_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + RX_8 + + + pipe_tx_8_sigs + + + + + RX_9 + + + pipe_tx_9_sigs + + + + + RX_10 + + + pipe_tx_10_sigs + + + + + RX_11 + + + pipe_tx_11_sigs + + + + + RX_12 + + + pipe_tx_12_sigs + + + + + RX_13 + + + pipe_tx_13_sigs + + + + + RX_14 + + + pipe_tx_14_sigs + + + + + RX_15 + + + pipe_tx_15_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + TX_8 + + + pipe_rx_8_sigs + + + + + TX_9 + + + pipe_rx_9_sigs + + + + + TX_10 + + + pipe_rx_10_sigs + + + + + TX_11 + + + pipe_rx_11_sigs + + + + + TX_12 + + + pipe_rx_12_sigs + + + + + TX_13 + + + pipe_rx_13_sigs + + + + + TX_14 + + + pipe_rx_14_sigs + + + + + TX_15 + + + pipe_rx_15_sigs + + + + + + + false + + + + + + pcie_ext_pipe_ep_legacy_usp + pcie3_ext_pipe_ep_legacy_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + RX_8 + + + pipe_tx_8_sigs + + + + + RX_9 + + + pipe_tx_9_sigs + + + + + RX_10 + + + pipe_tx_10_sigs + + + + + RX_11 + + + pipe_tx_11_sigs + + + + + RX_12 + + + pipe_tx_12_sigs + + + + + RX_13 + + + pipe_tx_13_sigs + + + + + RX_14 + + + pipe_tx_14_sigs + + + + + RX_15 + + + pipe_tx_15_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + TX_8 + + + pipe_rx_8_sigs + + + + + TX_9 + + + pipe_rx_9_sigs + + + + + TX_10 + + + pipe_rx_10_sigs + + + + + TX_11 + + + pipe_rx_11_sigs + + + + + TX_12 + + + pipe_rx_12_sigs + + + + + TX_13 + + + pipe_rx_13_sigs + + + + + TX_14 + + + pipe_rx_14_sigs + + + + + TX_15 + + + pipe_rx_15_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_rp + pcie3_ext_pipe_rp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_in + + + + + COMMANDS_OUT + + + common_commands_out + + + + + RX_0 + + + pipe_rx_0_sigs + + + + + RX_1 + + + pipe_rx_1_sigs + + + + + RX_2 + + + pipe_rx_2_sigs + + + + + RX_3 + + + pipe_rx_3_sigs + + + + + RX_4 + + + pipe_rx_4_sigs + + + + + RX_5 + + + pipe_rx_5_sigs + + + + + RX_6 + + + pipe_rx_6_sigs + + + + + RX_7 + + + pipe_rx_7_sigs + + + + + TX_0 + + + pipe_tx_0_sigs + + + + + TX_1 + + + pipe_tx_1_sigs + + + + + TX_2 + + + pipe_tx_2_sigs + + + + + TX_3 + + + pipe_tx_3_sigs + + + + + TX_4 + + + pipe_tx_4_sigs + + + + + TX_5 + + + pipe_tx_5_sigs + + + + + TX_6 + + + pipe_tx_6_sigs + + + + + TX_7 + + + pipe_tx_7_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_ep + pcie3_ext_pipe_ep + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_ep_legacy + pcie3_ext_pipe_ep_legacy + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + + + false + + + + + + dsc_bypass_c2h_0 + dsc_bypass_c2h_0 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_0 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_0 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_0 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_0 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_0 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_0 + + + + + + + false + + + + + + dsc_bypass_c2h_1 + dsc_bypass_c2h_1 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_1 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_1 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_1 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_1 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_1 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_1 + + + + + + + false + + + + + + dsc_bypass_c2h_2 + dsc_bypass_c2h_2 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_2 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_2 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_2 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_2 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_2 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_2 + + + + + + + false + + + + + + dsc_bypass_c2h_3 + dsc_bypass_c2h_3 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_3 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_3 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_3 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_3 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_3 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_3 + + + + + + + false + + + + + + dsc_bypass_h2c_0 + dsc_bypass_h2c_0 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_0 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_0 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_0 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_0 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_0 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_0 + + + + + + + false + + + + + + dsc_bypass_h2c_1 + dsc_bypass_h2c_1 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_1 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_1 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_1 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_1 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_1 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_1 + + + + + + + false + + + + + + dsc_bypass_h2c_2 + dsc_bypass_h2c_2 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_2 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_2 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_2 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_2 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_2 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_2 + + + + + + + false + + + + + + dsc_bypass_h2c_3 + dsc_bypass_h2c_3 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_3 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_3 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_3 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_3 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_3 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_3 + + + + + + + false + + + + + + dma_status_ports + dma_status_ports + XDMA Status Ports Interface + + + + + + + c2h_sts0 + + + c2h_sts_0 + + + + + c2h_sts1 + + + c2h_sts_1 + + + + + c2h_sts2 + + + c2h_sts_2 + + + + + c2h_sts3 + + + c2h_sts_3 + + + + + h2c_sts0 + + + h2c_sts_0 + + + + + h2c_sts1 + + + h2c_sts_1 + + + + + h2c_sts2 + + + h2c_sts_2 + + + + + h2c_sts3 + + + h2c_sts_3 + + + + + + + false + + + + + + cap + cap + + + + + + + GNT + + + cap_gnt + + + + + REL + + + cap_rel + + + + + REQ + + + cap_req + + + + + + + false + + + + + + startup + startup + STARTUP Interface + + + + + + + cfgclk + + + startup_cfgclk + + + + + cfgmclk + + + startup_cfgmclk + + + + + di + + + startup_di + + + + + do + + + startup_do + + + + + dts + + + startup_dts + + + + + eos + + + startup_eos + + + + + fcsbo + + + startup_fcsbo + + + + + fcsbts + + + startup_fcsbts + + + + + gsr + + + startup_gsr + + + + + gts + + + startup_gts + + + + + keyclearb + + + startup_keyclearb + + + + + pack + + + startup_pack + + + + + preq + + + startup_preq + + + + + userdoneo + + + startup_usrdoneo + + + + + usrcclko + + + startup_usrcclko + + + + + usrclkts + + + startup_usrcclkts + + + + + usrdonets + + + startup_usrdonets + + + + + + + false + + + + + + atspri_s_axis_rq + atspri_s_axis_rq + The Requestor Request interface received requests TLP's from the Client Application + + + + + + + TDATA + + + atspri_s_axis_rq_tdata + + + + + TKEEP + + + atspri_s_axis_rq_tkeep + + + + + TLAST + + + atspri_s_axis_rq_tlast + + + + + TREADY + + + atspri_s_axis_rq_tready + + + + + TUSER + + + atspri_s_axis_rq_tuser + + + + + TVALID + + + atspri_s_axis_rq_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + atspri_m_axis_cq + atspri_m_axis_cq + The Completer Request interface is used to transmit Completion TLP's to the Client Application + + + + + + + TDATA + + + atspri_m_axis_cq_tdata + + + + + TKEEP + + + atspri_m_axis_cq_tkeep + + + + + TLAST + + + atspri_m_axis_cq_tlast + + + + + TREADY + + + atspri_m_axis_cq_tready + + + + + TUSER + + + atspri_m_axis_cq_tuser + + + + + TVALID + + + atspri_m_axis_cq_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + cfg_status_ats + cfg_status_ats + Configuration Status Interface For ATS + + + + + + + cfg_status_ats_en + + + cfg_status_ats_en + + + + + cfg_status_ats_stu + + + cfg_status_ats_stu + + + + + + + false + + + + + + cfg_status_pri + cfg_status_pri + Configuration Status Interface For PRI + + + + + + + cfg_status_clr_s + + + cfg_status_clr_s + + + + + cfg_status_ost_pr_alloc + + + cfg_status_ost_pr_alloc + + + + + cfg_status_pr_en + + + cfg_status_pr_en + + + + + cfg_status_pr_rf + + + cfg_status_pr_rf + + + + + cfg_status_pr_rst + + + cfg_status_pr_rst + + + + + cfg_status_pr_uprgi + + + cfg_status_pr_uprgi + + + + + cfg_status_set_rf + + + cfg_status_set_rf + + + + + cfg_status_set_s + + + cfg_status_set_s + + + + + cfg_status_set_uprgi + + + cfg_status_set_uprgi + + + + + + + false + + + + + + dma_debug_ports + XDMA Debug Ports + + + + + + + cc_tdata_out + + + m_axis_cc_tdata_out + + + + + cc_tkeep_out + + + m_axis_cc_tkeep_out + + + + + cc_tlast_out + + + m_axis_cc_tlast_out + + + + + cc_tready_out + + + m_axis_cc_tready_out + + + + + cc_tuser_out + + + m_axis_cc_tuser_out + + + + + cc_tvalid_out + + + m_axis_cc_tvalid_out + + + + + cq_tdata_out + + + s_axis_cq_tdata_out + + + + + cq_tkeep_out + + + s_axis_cq_tkeep_out + + + + + cq_tlast_out + + + s_axis_cq_tlast_out + + + + + cq_tready_out + + + s_axis_cq_tready_out + + + + + cq_tuser_out + + + s_axis_cq_tuser_out + + + + + cq_tvalid_out + + + s_axis_cq_tvalid_out + + + + + rc_tdata_out + + + s_axis_rc_tdata_out + + + + + rc_tkeep_out + + + s_axis_rc_tkeep_out + + + + + rc_tlast_out + + + s_axis_rc_tlast_out + + + + + rc_tready_out + + + s_axis_rc_tready_out + + + + + rc_tuser_out + + + s_axis_rc_tuser_out + + + + + rc_tvalid_out + + + s_axis_rc_tvalid_out + + + + + rq_tdata_out + + + m_axis_rq_tdata_out + + + + + rq_tkeep_out + + + m_axis_rq_tkeep_out + + + + + rq_tlast_out + + + m_axis_rq_tlast_out + + + + + rq_tready_out + + + m_axis_rq_tready_out + + + + + rq_tuser_out + + + m_axis_rq_tuser_out + + + + + rq_tvalid_out + + + m_axis_rq_tvalid_out + + + + + + + false + + + + + + pcie3_us_ext_shared_logic + pcie3_us_ext_shared_logic + PCIE3 Ultrascale External Shared Logic Interface + + + + + + + exts_qpll1lock_out + + + ext_qpll1lock_out + + + + + exts_qpll1outclk_out + + + ext_qpll1outclk_out + + + + + exts_qpll1outrefclk_out + + + ext_qpll1outrefclk_out + + + + + exts_qpll1pd + + + ext_qpll1pd + + + + + exts_qpll1rate + + + ext_qpll1rate + + + + + exts_qpll1refclk + + + ext_qpll1refclk + + + + + exts_qpll1reset + + + ext_qpll1reset + + + + + + + false + + + + + + pcie3_us_int_shared_logic + pcie3_us_int_shared_logic + PCIE3 Ultrascale Internal Shared Logic Interface + + + + + + + ints_qpll1lock_out + + + int_qpll1lock_out + + + + + ints_qpll1outclk_out + + + int_qpll1outclk_out + + + + + ints_qpll1outrefclk_out + + + int_qpll1outrefclk_out + + + + + + + false + + + + + + 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PL_UPSTREAM_FACING + Pl Upstream Facing + true + + + TL_LEGACY_MODE_ENABLE + Tl Legacy Mode Enable + false + + + PCIE_BLK_LOCN + 6 + + + PL_LINK_CAP_MAX_LINK_WIDTH + Pl Link Cap Max Link Width + 8 + + + PL_LINK_CAP_MAX_LINK_SPEED + Pl Link Cap Max Link Speed + 4 + + + REF_CLK_FREQ + Ref Clk Freq + 0 + + + DRP_CLK_SEL + DRP CLK SEL + 0 + + + FREE_RUN_FREQ + Ref Clk Freq + 0 + + + AXI_ADDR_WIDTH + AXI Address width + 64 + + + AXI_DATA_WIDTH + AXI data width + 256 + + + CORE_CLK_FREQ + Core Clk Freq + 2 + + + PLL_TYPE + PLL Type + 2 + + + USER_CLK_FREQ + User Clk Freq + 2 + + + SILICON_REV + Silicon Revision + Pre-Production + + + PIPE_SIM + Enable External PIPE Interface + false + + + EXT_CH_GT_DRP + false + + + PCIE3_DRP + false + + + DEDICATE_PERST + false + + + SYS_RESET_POLARITY + 0 + + + MCAP_ENABLEMENT + NONE + + + EXT_STARTUP_PRIMITIVE + EXT STARTUP PRIMITIVE + false + + + PF0_VENDOR_ID + pf0 Vendor Id + 0x10EE + + + PF0_DEVICE_ID + Pf0 Device Id + 0x9038 + + + PF0_REVISION_ID + Pf0 Revision Id + 0x00 + + + PF0_SUBSYSTEM_VENDOR_ID + Pf0 Subsystem Vendor Id + 0x10EE + + + PF0_SUBSYSTEM_ID + Pf0 Subsystem Id + 0x0007 + + + PF0_CLASS_CODE + Pf0 Class Code + 0x070001 + + + PF1_VENDOR_ID + pf1 Vendor Id + 0x10EE + + + PF1_DEVICE_ID + Pf1 Device Id + 0x9111 + + + PF1_REVISION_ID + Pf1 Revision Id + 0x00 + + + PF1_SUBSYSTEM_VENDOR_ID + Pf1 Subsystem Vendor Id + 0x10EE + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0x0007 + + + PF1_CLASS_CODE + Pf1 Class Code + 0x070001 + + + PF2_DEVICE_ID + Pf2 Device Id + 0x9211 + + + PF2_REVISION_ID + Pf2 Revision Id + 0x00 + + + PF2_SUBSYSTEM_ID + Pf3 Subsystem Id + 0x0007 + + + PF3_DEVICE_ID + Pf3 Device Id + 0x9311 + + + PF3_REVISION_ID + Pf3 Revision Id + 0x00 + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0x0007 + + + AXILITE_MASTER_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x0D + + + AXILITE_MASTER_CONTROL + Pf0 Bar0 Control + 0x0 + + + XDMA_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x09 + + + XDMA_CONTROL + Pf0 Bar1 Control + 0x4 + + + AXIST_BYPASS_APERTURE_SIZE + Pf0 Bar2 Aperture Size + 0x0D + + + AXIST_BYPASS_CONTROL + Pf0 Bar2 Control + 0x0 + + + PF0_INTERRUPT_PIN + pf1 Interrupt Pin + 0x1 + + + PF0_MSI_CAP_MULTIMSGCAP + pf0 Msi Cap Multimsgcap + 0 + + + C_COMP_TIMEOUT + c_comp_timeout + 1 + + + C_TIMEOUT0_SEL + 0xE + + + C_TIMEOUT1_SEL + 0xF + + + C_TIMEOUT_MULT + 0x3 + + + C_OLD_BRIDGE_TIMEOUT + 0 + + + SHARED_LOGIC + 1 + + + SHARED_LOGIC_CLK + false + + + SHARED_LOGIC_BOTH + false + + + SHARED_LOGIC_GTC + false + + + SHARED_LOGIC_GTC_7XG2 + false + + + SHARED_LOGIC_CLK_7XG2 + false + + + SHARED_LOGIC_BOTH_7XG2 + false + + + EN_TRANSCEIVER_STATUS_PORTS + false + + + IS_BOARD_PROJECT + Is Board Flow Enabled + 1 + + + EN_GT_SELECTION + FALSE + + + SELECT_QUAD + GTY_Quad_227 + + + ULTRASCALE + FALSE + + + ULTRASCALE_PLUS + TRUE + + + V7_GEN3 + FALSE + + + MSI_ENABLED + TRUE + + + DEV_PORT_TYPE + 0 + + + XDMA_AXI_INTF_MM + 0 + + + XDMA_PCIE_64BIT_EN + xdma_pcie_64bit_en + + + XDMA_AXILITE_MASTER + FALSE + + + XDMA_AXIST_BYPASS + FALSE + + + XDMA_RNUM_CHNL + 1 + + + XDMA_WNUM_CHNL + 1 + + + XDMA_AXILITE_SLAVE + FALSE + + + XDMA_NUM_USR_IRQ + 1 + + + XDMA_RNUM_RIDS + 32 + + + XDMA_WNUM_RIDS + 16 + + + C_M_AXI_ID_WIDTH + 4 + + + C_AXIBAR_NUM + 1 + + + C_FAMILY + virtexuplusHBM + + + XDMA_NUM_PCIE_TAG + 256 + + + EN_AXI_MASTER_IF + Enable AXI Master IF + TRUE + + + EN_WCHNL_0 + TRUE + + + EN_WCHNL_1 + FALSE + + + EN_WCHNL_2 + FALSE + + + EN_WCHNL_3 + FALSE + + + EN_WCHNL_4 + FALSE + + + EN_WCHNL_5 + FALSE + + + EN_WCHNL_6 + FALSE + + + EN_WCHNL_7 + FALSE + + + EN_RCHNL_0 + TRUE + + + EN_RCHNL_1 + FALSE + + + EN_RCHNL_2 + FALSE + + + EN_RCHNL_3 + FALSE + + + EN_RCHNL_4 + FALSE + + + EN_RCHNL_5 + FALSE + + + EN_RCHNL_6 + FALSE + + + EN_RCHNL_7 + FALSE + + + XDMA_DSC_BYPASS + FALSE + + + C_METERING_ON + 1 + + + RX_DETECT + Receiver Detect + 0 + + + C_ATS_ENABLE + ATS Extended Capability Enable + FALSE + + + C_ATS_CAP_NEXTPTR + 0x000 + + + C_PR_CAP_NEXTPTR + 0x000 + + + C_PRI_ENABLE + Page Request Extended Capability Enable + FALSE + + + DSC_BYPASS_RD + 0 + + + DSC_BYPASS_WR + 0 + + + XDMA_STS_PORTS + FALSE + + + MSIX_ENABLED + FALSE + + + WR_CH0_ENABLED + FALSE + + + WR_CH1_ENABLED + FALSE + + + WR_CH2_ENABLED + FALSE + + + WR_CH3_ENABLED + FALSE + + + RD_CH0_ENABLED + FALSE + + + RD_CH1_ENABLED + FALSE + + + RD_CH2_ENABLED + FALSE + + + RD_CH3_ENABLED + FALSE + + + CFG_MGMT_IF + TRUE + + + RQ_SEQ_NUM_IGNORE + 0 + + + CFG_EXT_IF + FALSE + + + LEGACY_CFG_EXT_IF + FALSE + + + C_PARITY_CHECK + 0 + + + C_PARITY_GEN + 0 + + + C_PARITY_PROP + 0 + + + C_ECC_ENABLE + 0 + + + EN_DEBUG_PORTS + FALSE + + + VU9P_BOARD + FALSE + + + ENABLE_JTAG_DBG + FALSE + + + ENABLE_LTSSM_DBG + FALSE + + + ENABLE_IBERT + false + + + MM_SLAVE_EN + 0 + + + DMA_EN + 1 + + + C_AXIBAR_0 + 0x0000000000000000 + + + C_AXIBAR_1 + 0x0000000000000000 + + + C_AXIBAR_2 + 0x0000000000000000 + + + C_AXIBAR_3 + 0x0000000000000000 + + + C_AXIBAR_4 + 0x0000000000000000 + + + C_AXIBAR_5 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_0 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_1 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_2 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_3 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_4 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_5 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_0 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_1 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_2 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_3 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_4 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_5 + 0x0000000000000000 + + + EN_AXI_SLAVE_IF + Enable AXI Slave IF + TRUE + + + C_INCLUDE_BAROFFSET_REG + 1 + + + C_BASEADDR + 0x00001000 + + + C_HIGHADDR + 0x00001FFF + + + C_S_AXI_ID_WIDTH + 4 + + + C_S_AXI_NUM_READ + AXI Address width + 8 + + + C_M_AXI_NUM_READ + AXI Address width + 8 + + + C_M_AXI_NUM_READQ + AXI Address width + 2 + + + C_S_AXI_NUM_WRITE + AXI Address width + 8 + + + C_M_AXI_NUM_WRITE + AXI Address width + 16 + + + C_M_AXI_NUM_WRITE_SCALE + AXI Address width + 1 + + + MSIX_IMPL_EXT + FALSE + + + AXI_ACLK_LOOPBACK + FALSE + + + PF0_BAR0_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x0A + + + PF0_BAR0_CONTROL + Pf0 Bar0 Control + 0x4 + + + PF0_BAR1_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x05 + + + PF0_BAR1_CONTROL + Pf0 Bar1 Control + 0x0 + + + PF0_BAR2_APERTURE_SIZE + Pf0 Bar2 Aperture Size + 0x05 + + + PF0_BAR2_CONTROL + Pf0 Bar2 Control + 0x0 + + + PF0_BAR3_APERTURE_SIZE + Pf0 Bar3 Aperture Size + 0x05 + + + PF0_BAR3_CONTROL + Pf0 Bar3 Control + 0x0 + + + PF0_BAR4_APERTURE_SIZE + Pf0 Bar4 Aperture Size + 0x05 + + + PF0_BAR4_CONTROL + Pf0 Bar4 Control + 0x0 + + + PF0_BAR5_APERTURE_SIZE + Pf0 Bar5 Aperture Size + 0x05 + + + PF0_BAR5_CONTROL + Pf0 Bar5 Control + 0x0 + + + PF0_EXPANSION_ROM_APERTURE_SIZE + Pf0 Expansion Rom Aperture Size + 0x000 + + + PF0_EXPANSION_ROM_ENABLE + Pf0 Expansion Rom Enable + FALSE + + + PCIEBAR_NUM + 6 + + + C_PCIEBAR2AXIBAR_0 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_1 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_2 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_3 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_4 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_5 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_6 + 0x0000000000000000 + + + BARLITE1 + 0 + + + BARLITE2 + 7 + + + VCU118_BOARD + FALSE + + + SPLIT_DMA + FALSE + + + USE_STANDARD_INTERFACES + FALSE + + + DMA_2RP + FALSE + + + SRIOV_ACTIVE_VFS + 252 + + + PIPE_LINE_STAGE + 2 + + + AXIS_PIPE_LINE_STAGE + 0 + + + MULT_PF_DES + FALSE + + + PF_SWAP + FALSE + + + PF0_MSIX_TAR_ID + PF0 MSIX target ID + 0x08 + + + PF1_MSIX_TAR_ID + PF1 MSIX target ID + 0x09 + + + RUNBIT_FIX + FALSE + + + USRINT_EXPN + FALSE + + + xlnx_ref_board + AU50 + + + GTWIZ_IN_CORE + 1 + + + GTCOM_IN_CORE + 2 + + + INS_LOSS_PROFILE + Add-in_Card + + + FUNC_MODE + 1 + + + PF1_ENABLED + 0 + + + DMA_RESET_SOURCE_SEL + 0 + + + PF1_BAR0_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x12 + + + PF1_BAR0_CONTROL + Pf0 Bar0 Control + 0x4 + + + PF1_BAR1_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x0A + + + PF1_BAR1_CONTROL + Pf0 Bar1 Control + 0x0 + + + PF1_BAR2_APERTURE_SIZE + Pf0 Bar2 Aperture Size + 0x0A + + + PF1_BAR2_CONTROL + Pf0 Bar2 Control + 0x6 + + + PF1_BAR3_APERTURE_SIZE + Pf0 Bar3 Aperture Size + 0x0A + + + PF1_BAR3_CONTROL + Pf0 Bar3 Control + 0x0 + + + PF1_BAR4_APERTURE_SIZE + Pf0 Bar4 Aperture Size + 0x0A + + + PF1_BAR4_CONTROL + Pf0 Bar4 Control + 0x6 + + + PF1_BAR5_APERTURE_SIZE + Pf0 Bar5 Aperture Size + 0x0A + + + PF1_BAR5_CONTROL + Pf0 Bar5 Control + 0x0 + + + PF1_EXPANSION_ROM_APERTURE_SIZE + Pf1 Expansion Rom Aperture Size + 0x000 + + + PF1_EXPANSION_ROM_ENABLE + Pf1 Expansion Rom Enable + FALSE + + + PF1_PCIEBAR2AXIBAR_0 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_1 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_2 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_3 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_4 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_5 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_6 + 0x0000000000000000 + + + C_MSIX_INT_TABLE_EN + 0 + + + VU9P_TUL_EX + VU9P TUL board + FALSE + + + PCIE_BLK_TYPE + 1 + + + CCIX_ENABLE + Ccix Enable + FALSE + + + CCIX_DVSEC + Ccix Dvsec Enable + FALSE + + + EXT_SYS_CLK_BUFG + FALSE + + + C_NUM_OF_SC + 1 + + + USR_IRQ_EXDES + FALSE + + + AXI_VIP_IN_EXDES + FALSE + + + PIPE_DEBUG_EN + FALSE + + + XDMA_NON_INCREMENTAL_EXDES + FALSE + + + XDMA_ST_INFINITE_DESC_EXDES + FALSE + + + EXT_XVC_VSEC_ENABLE + Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design + FALSE + + + ACS_EXT_CAP_ENABLE + FALSE + + + EN_PCIE_DEBUG_PORTS + FALSE + + + MULTQ_EN + 0 + + + DMA_MM + 0 + + + DMA_ST + 1 + + + C_PCIE_PFS_SUPPORTED + 0 + + + C_SRIOV_EN + 0 + + + BARLITE_EXT_PF0 + 0x00 + + + BARLITE_EXT_PF1 + 0x00 + + + BARLITE_EXT_PF2 + 0x00 + + + BARLITE_EXT_PF3 + 0x00 + + + BARLITE_INT_PF0 + 0x01 + + + BARLITE_INT_PF1 + 0x00 + + + BARLITE_INT_PF2 + 0x00 + + + BARLITE_INT_PF3 + 0x00 + + + NUM_VFS_PF0 + 0 + + + NUM_VFS_PF1 + 0 + + + NUM_VFS_PF2 + 0 + + + NUM_VFS_PF3 + 0 + + + FIRSTVF_OFFSET_PF0 + 0 + + + FIRSTVF_OFFSET_PF1 + 0 + + + FIRSTVF_OFFSET_PF2 + 0 + + + FIRSTVF_OFFSET_PF3 + 0 + + + VF_BARLITE_EXT_PF0 + 0x00 + + + VF_BARLITE_EXT_PF1 + 0x00 + + + VF_BARLITE_EXT_PF2 + 0x00 + + + VF_BARLITE_EXT_PF3 + 0x00 + + + VF_BARLITE_INT_PF0 + 0x01 + + + VF_BARLITE_INT_PF1 + 0x01 + + + VF_BARLITE_INT_PF2 + 0x01 + + + VF_BARLITE_INT_PF3 + 0x01 + + + C_C2H_NUM_CHNL + 1 + + + C_H2C_NUM_CHNL + 1 + + + H2C_XDMA_CHNL + 0x0F + + + C2H_XDMA_CHNL + 0x0F + + + AXISTEN_IF_ENABLE_MSG_ROUTE + 0x00000 + + + ENABLE_MORE + FALSE + + + DISABLE_BRAM_PIPELINE + FALSE + + + DISABLE_EQ_SYNCHRONIZER + FALSE + + + C_ENABLE_RESOURCE_REDUCTION + FALSE + + + GEN4_EIEOS_0S7 + TRUE + + + C_S_AXI_SUPPORTS_NARROW_BURST + 0 + + + ENABLE_ATS_SWITCH + ATS Switch Enable + FALSE + + + C_ATS_SWITCH_UNIQUE_BDF + 1 + + + C_LAST_CORE_CAP_ADDR + 0x100 + + + C_VSEC_CAP_ADDR + 0x128 + + + SOFT_RESET_EN + FALSE + + + INTERRUPT_OUT_WIDTH + 1 + + + C_MSI_RX_PIN_EN + 0 + + + C_MSIX_RX_PIN_EN + 1 + + + C_INTX_RX_PIN_EN + 1 + + + MSIX_RX_DECODE_EN + FALSE + + + PCIE_ID_IF + FALSE + + + TL_PF_ENABLE_REG + 0 + + + AXSIZE_BYTE_ACCESS_EN + FALSE + + + SPLIT_DMA_SINGLE_PF + FALSE + + + RBAR_ENABLE + FALSE + + + C_SMMU_EN + 0 + + + C_M_AXI_AWUSER_WIDTH + 8 + + + C_M_AXI_ARUSER_WIDTH + 8 + + + C_SLAVE_READ_64OS_EN + 0 + + + FLR_ENABLE + FLR Enable + FALSE + + + SHELL_BRIDGE + 0 + + + MSIX_PCIE_INTERNAL + 0 + + + + + + choice_list_03bd623c + BAR_0 + BAR_1 + BAR_3:2 + BAR_5:4 + + + choice_list_08bf412c + 128 + 256 + 512 + + + choice_list_0be33969 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + + + choice_list_0d378f84 + Simple_communication_controllers + Device_was_built_before_Class_Code_definitions_were_finalized + Mass_storage_controller + Network_controller + Display_controller + Multimedia_device + Memory_controller + Base_system_peripherals + Input_devices + Docking_stations + Processors + Serial_bus_controllers + Wireless_controller + Intelligent_I/O_controllers + Satellite_communication_controllers + Processing_accelerators + + + choice_list_0f93492c + Chip-to-Chip + Add-in_Card + Backplane + + + choice_list_110bd32e + 2 + 4 + + + choice_list_1cfc6134 + 1 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_1e9fb93b + X1 + X2 + X4 + X8 + X16 + + + choice_list_24b724fb + Basic + Advanced + + + choice_list_2dba17cd + None + Check_Parity + Propagate_Parity + + + choice_list_34d65ff4 + 128 + + + choice_list_35d06715 + 2 + + + choice_list_38306dd1 + SOFT + HARD + + + choice_list_3ca2cbc7 + BAR_0 + + + choice_list_3cee6ea1 + 16450_compatible_serial_controller + 16550_compatible_serial_controller + 16650_compatible_serial_controller + 16750_compatible_serial_controller + 16850_compatible_serial_controller + 16950_compatible_serial_controller + Bi_directional_parallel_port + ECP_1.X_compliant_parallel_port + GPIB(IEEE_488.1/2)_controller + Generic_XT_compatible_serial_controller + Generic_modem + Hayes_compatible_modem_with_16450_compatible_interface + Hayes_compatible_modem_with_16550_compatible_interface + Hayes_compatible_modem_with_16650_compatible_interface + Hayes_compatible_modem_with_16750_compatible_interface + IEEE_1284_controller + IEEE_1284_target_device + Multiport_serial_controller + Other_communications_device + Parallel_port + Smart_Card + + + choice_list_4665eb01 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_list_47140c0d + 0000 + 0001 + + + choice_list_4e419c85 + Default + Falling_Edge + + + choice_list_52d29139 + Bytes + Kilobytes + Megabytes + Gigabytes + + + choice_list_57749bc8 + DMA + + + choice_list_57c4a416 + None + None + + + choice_list_589df8e9 + RAM + Other_memory_controller + Flash + + + choice_list_5e150e6c + 50us + 50ms + + + choice_list_5e2921cd + Kilobytes + + + choice_list_5e45706a + 1_vector + 2_vectors + 4_vectors + 8_vectors + 16_vectors + 32_vectors + + + choice_list_640e51e1 + DMA + AXI_Bridge + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_6a0870a7 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + 30 + 31 + + + choice_list_6b979ebc + 250 + + + choice_list_6eff49bd + ACTIVE_LOW + ACTIVE_HIGH + + + choice_list_7a7dde49 + true + false + + + choice_list_7e60966b + 2.5_GT/s + 5.0_GT/s + 8.0_GT/s + 16.0_GT/s + + + choice_list_8112d406 + 8 + 16 + 32 + + + choice_list_81ddc592 + Kilobytes + Megabytes + Gigabytes + Terabytes + Petabytes + Exabytes + + + choice_list_847d868a + 1 + 2 + 3 + 4 + 5 + 6 + + + choice_list_86c5d341 + 500 + + + choice_list_88156f2e + QPLL1 + QPLL0 + + + choice_list_8a9e69a3 + AXI_Lite_Master + DMA + + + choice_list_8aad6ae4 + 1 + 2 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_8b5e4915 + 4 + 5 + + + choice_list_914704bd + 100_MHz + 125_MHz + + + choice_list_91b49d0b + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + + + choice_list_96d6a000 + Wireless_controller + Satellite_communication_controllers + Data_acquisition_and_signal_processing_controllers + Intelligent_I/O_controllers + Docking_stations + Processing_accelerators + Device_was_built_before_Class_Code_definitions_were_finalized + Memory_controller + Simple_communication_controllers + Serial_bus_controllers + Encryption/Decryption_controllers + Display_controller + Multimedia_device + Input_devices + Mass_storage_controller + Processors + Device_does_not_fit_in_any_defined_classes + Bridge_device + Network_controller + Base_system_peripherals + + + choice_list_97bc19ec + 256_bit + + + choice_list_9aec9108 + Internal + External + + + choice_list_9e15bd51 + CONSTANT + + + choice_list_9f5580fd + Pre-Production + + + choice_list_a30da595 + Custom + pcie_perstn + + + choice_list_a44ca313 + Custom + pci_express_x1 + pci_express_x16 + pci_express_x2 + pci_express_x4 + pci_express_x8 + + + choice_list_a71f3969 + AXI_Memory_Mapped + AXI_Stream + + + choice_list_aa031417 + 1 + 2 + 3 + 4 + + + choice_list_ab8591cd + PCI_Express_Endpoint_device + PCI_Express_Endpoint_device + + + choice_list_abc20383 + GTY_Quad_227 + GTY_Quad_226 + GTY_Quad_225 + GTY_Quad_224 + + + choice_list_ae9f88f6 + 1 + + + choice_list_b0ffef10 + 0 + 1 + 2 + 3 + 4 + 5 + 7 + + + choice_list_bdd7203f + True + False + + + choice_list_bea500ca + None + MSI-X_External + MSI-X_Internal + MSI-X_AXI4-Stream + + + choice_list_c15e8c67 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_c3d223d9 + Memory + + + choice_list_c63ab5b1 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + choice_list_ca005b72 + No_ASPM + L1_Supported + + + choice_list_ca108395 + 2 + 4 + 8 + 16 + 32 + + + choice_list_d123c74c + Bytes + Kilobytes + Megabytes + + + choice_list_d1e1a340 + Kilobytes + Megabytes + Gigabytes + + + choice_list_d291617b + PCIE4C_X1Y0 + PCIE4C_X0Y1 + PCIE4C_X0Y0 + PCIE4C_X1Y1 + + + choice_list_d53faa96 + 100_MHz + 125_MHz + 250_MHz + + + choice_list_d85ad257 + 0 + + + choice_list_df7cde9e + RAM + Flash + Other_memory_controller + + + choice_list_dff1a45d + Wireless_controller + Satellite_communication_controllers + Data_acquisition_and_signal_processing_controllers + Processing_accelerators + Intelligent_I/O_controllers + Docking_stations + Device_was_built_before_Class_Code_definitions_were_finalized + Memory_controller + Simple_communication_controllers + Serial_bus_controllers + Encryption/Decryption_controllers + Display_controller + Multimedia_device + Input_devices + Mass_storage_controller + Processors + Device_does_not_fit_in_any_defined_classes + Bridge_device + Network_controller + Base_system_peripherals + + + choice_list_e7c484ae + TRUE + FALSE + + + choice_list_e7f13338 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_e9cf6440 + Disabled + 32bit_Enabled + 64bit_Enabled + + + choice_list_eaa1f22e + AU50 + + + choice_list_ec64e624 + N/A + + + choice_list_f1174048 + NONE + INTA + INTB + INTC + INTD + + + choice_list_f94ec5c4 + 4 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_fab783d7 + User_Reset + Phy_Ready + + + choice_list_fc3456a9 + Disabled + Enabled + + + choice_list_fde36331 + Kilobytes + Megabytes + + + choice_list_fe1fb7c4 + 0 + 4 + 8 + 12 + 16 + + + choice_pairs_3c87fcdb + 1 + 0 + + + choice_pairs_53749dec + 1 + 0 + + + choice_pairs_6f00a734 + 0 + 1 + 2 + + + + + xilinx_elaboratesubcores_view_fileset + + ip_0/xdma_pcie4c_ip.xci + xci + + + ip_0/xdma_pcie4c_ip.xml + xml + + + ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci + xci + + + ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xml + xml + + + ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci + xci + + + ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xml + xml + + + + The Xilinx PCI Express DMA + + + Component_Name + xdma + + + functional_mode + Functional Mode + DMA + + + + true + + + + + + mode_selection + Mode + Basic + + + + true + + + + + + device_port_type + Device Port Type + PCI_Express_Endpoint_device + + + + false + + + + + + pcie_blk_locn + Pcie Blk Locn + PCIE4C_X1Y0 + + + + true + + + + + + pl_link_cap_max_link_width + Pl Link Cap Max Link Width + X8 + + + + true + + + + + + pl_link_cap_max_link_speed + Pl Link Cap Max Link Speed + 8.0_GT/s + + + + true + + + + + + ref_clk_freq + 100_MHz + + + + true + + + + + + drp_clk_sel + Internal + + + + true + + + + + + free_run_freq + 100_MHz + + + + true + + + + + + axi_addr_width + AXI Address width + 64 + + + + false + + + + + + axi_data_width + AXI Data width + 256_bit + + + + true + + + + + + axisten_freq + AXIsten if freq + 250 + + + + true + + + + + + en_axi_slave_if + Enable AXI Slave Interface + true + + + + true + + + + + + en_axi_master_if + Enable AXI Master Interface + true + + + + true + + + + + + pipe_sim + false + + + + true + + + + + + en_ext_ch_gt_drp + false + + + + true + + + + + + en_pcie_drp + false + + + + true + + + + + + dedicate_perst + false + + + + false + + + + + + sys_reset_polarity + ACTIVE_LOW + + + + true + + + + + + mcap_enablement + MCAP Enable + None + + + + false + + + + + + mcap_fpga_bitstream_version + MCAP Bitstream Version Register Value + 00000000 + + + + false + + + + + + ext_startup_primitive + false + + + + false + + + + + + enable_code + 0000 + + + vendor_id + Vendor Id + 10EE + + + + true + + + + + + pf0_device_id + PF0 Device Id + 9038 + + + + true + + + + + + pf0_revision_id + PF0 Revision Id + 00 + + + + true + + + + + + pf0_subsystem_vendor_id + PF0 Subsystem Vendor Id + 10EE + + + + true + + + + + + pf0_subsystem_id + PF0 Subsystem Id + 0007 + + + + true + + + + + + pf0_Use_Class_Code_Lookup_Assistant + false + + + + true + + + + + + pf0_base_class_menu + Pf0 Base Class Menu + Simple_communication_controllers + + + + true + + + + + + pf0_class_code_base + Pf0 Class Code Base + 07 + + + + true + + + + + + pf0_sub_class_interface_menu + Pf0 Sub Class Interface Menu + 16450_compatible_serial_controller + + + + true + + + + + + pf0_class_code_sub + pf0 Class Code Sub + 00 + + + + true + + + + + + pf0_class_code_interface + pf0 Class Code Interface + 01 + + + + true + + + + + + pf0_class_code + pf0 Class Code + 070001 + + + + false + + + + + + axilite_master_en + false + + + + true + + + + + + axilite_master_size + 1 + + + + false + + + + + + axilite_master_scale + Megabytes + + + + false + + + + + + xdma_en + true + + + + false + + + + + + xdma_size + 64 + + + + false + + + + + + xdma_scale + Kilobytes + + + + false + + + + + + axist_bypass_en + false + + + + true + + + + + + axist_bypass_size + 1 + + + + false + + + + + + axist_bypass_scale + Megabytes + + + + false + + + + + + pciebar2axibar_axil_master + 0x00000000 + + + + false + + + + + + pciebar2axibar_xdma + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_axist_bypass + 0x0000000000000000 + + + + false + + + + + + pf0_interrupt_pin + pf0 Interrupt Pin + INTA + + + + true + + + + + + pf0_msi_enabled + pf0 Msi Enabled + true + + + + true + + + + + + pf0_msi_cap_multimsgcap + pf0 Msi Cap Multimsgcap + 1_vector + + + + true + + + + + + comp_timeout + 50ms + + + + true + + + + + + timeout0_sel + 14 + + + + true + + + + + + timeout1_sel + 15 + + + + true + + + + + + timeout_mult + 3 + + + + true + + + + + + old_bridge_timeout + false + + + Shared_Logic + 1 + + + + true + + + + + + Shared_Logic_Clk + false + + + Shared_Logic_Both + false + + + Shared_Logic_Gtc + false + + + Shared_Logic_Gtc_7xG2 + false + + + Shared_Logic_Clk_7xG2 + false + + + Shared_Logic_Both_7xG2 + false + + + en_transceiver_status_ports + false + + + + true + + + + + + xdma_rnum_chnl + 1 + + + + true + + + + + + xdma_wnum_chnl + 1 + + + + true + + + + + + xdma_axilite_slave + false + + + + true + + + + + + xdma_num_usr_irq + 1 + + + + true + + + + + + xdma_rnum_rids + 32 + + + xdma_wnum_rids + 16 + + + SYS_RST_N_BOARD_INTERFACE + Custom + + + PCIE_BOARD_INTERFACE + Custom + + + en_gt_selection + false + + + select_quad + GTY_Quad_227 + + + + false + + + + + + RX_PPM_OFFSET + Specify the PPM offset between received data and transmitted data + 0 + + + RX_SSC_PPM + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 15 + + + PHY_LP_TXPRESET + Phy Lp Txpreset + 4 + + + coreclk_freq + CORE CLOCK FREQ + 500 + + + + false + + + + + + plltype + PLL TYPE + QPLL1 + + + xdma_axi_intf_mm + XDMA Interface + AXI_Stream + + + + true + + + + + + xdma_pcie_64bit_en + false + + + silicon_rev + Pre-Production + + + xdma_dsc_bypass + false + + + performance + false + + + pcie_extended_tag + true + + + rx_detect + Receiver Detect + Default + + + pf0_link_status_slot_clock_config + Pf0 Link Status Slot Clock Config + true + + + dsc_bypass_rd + 0000 + + + dsc_bypass_wr + 0000 + + + xdma_sts_ports + false + + + pf0_msix_enabled + Pf0 Msix Enabled + false + + + pf0_msix_cap_table_size + Pf0 Msix Cap Table Size + 000 + + + + false + + + + + + pf0_msix_cap_table_offset + Pf0 Msix Cap Table Offset + 00000000 + + + + false + + + + + + pf0_msix_cap_table_bir + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + pf0_msix_cap_pba_offset + Pf0 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + pf0_msix_cap_pba_bir + Pf0 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + pf1_msix_enabled + Pf1 Msix Enabled + false + + + pf1_msix_cap_table_size + Pf1 Msix Cap Table Size + 01F + + + pf1_msix_cap_table_offset + Pf1 Msix Cap Table Offset + 00009000 + + + pf1_msix_cap_table_bir + Pf1 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + pf1_msix_cap_pba_offset + Pf1 Msix Cap Pba Offset + 00009FE0 + + + pf1_msix_cap_pba_bir + Pf1 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + cfg_mgmt_if + true + + + + true + + + + + + ins_loss_profile + Add-in_Card + + + axil_master_64bit_en + false + + + + false + + + + + + axi_bypass_64bit_en + false + + + + false + + + + + + axil_master_prefetchable + false + + + + false + + + + + + xdma_pcie_prefetchable + false + + + + false + + + + + + axi_bypass_prefetchable + false + + + + false + + + + + + cfg_ext_if + false + + + legacy_cfg_ext_if + false + + + + false + + + + + + parity_settings + None + + + + true + + + + + + ecc_en + false + + + + true + + + + + + en_debug_ports + false + + + axi_id_width + 4 + + + + true + + + + + + vu9p_board + false + + + type1_membase_memlimit_enable + Type1 Config MemBase and MemLimit + Disabled + + + + false + + + + + + type1_prefetchable_membase_memlimit + Type1 Config Prefetchable MemBase and MemLimit + Disabled + + + + false + + + + + + enable_jtag_dbg + false + + + + true + + + + + + enable_ltssm_dbg + false + + + + true + + + + + + enable_ibert + false + + + + true + + + + + + axibar_num + 1 + + + + true + + + + + + axibar_0 + 0x0000000000000000 + + + + true + + + + + + axibar_1 + 0x0000000000000000 + + + + false + + + + + + axibar_2 + 0x0000000000000000 + + + + false + + + + + + axibar_3 + 0x0000000000000000 + + + + false + + + + + + axibar_4 + 0x0000000000000000 + + + + false + + + + + + axibar_5 + 0x0000000000000000 + + + + false + + + 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Master outstanding write Transactions Selection + 8 + + + + true + + + + + + c_m_axi_num_read + AXI Master outstanding read Transactions Selection + 8 + + + + false + + + + + + c_m_axi_num_readq + AXI Master outstanding read Transactions Selection + 2 + + + c_s_axi_num_write + AXI Slave outstanding write Transactions Selection + 8 + + + + false + + + + + + c_s_axi_num_read + AXI Slave outstanding read Transactions Selection + 8 + + + + false + + + + + + pf0_msix_impl_locn + Pf0 Msix Implementation Location + Internal + + + + false + + + + + + axi_aclk_loopback + false + + + pf0_bar0_enabled + Pf0 Bar0 Enabled + true + + + + true + + + + + + pf0_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf0_bar0_size + Pf0 Bar0 Size + 128 + + + + true + + + + + + pf0_bar0_scale + Pf0 Bar0 Scale + Kilobytes + + + + true + + + + + + pf0_bar0_64bit + Pf0 Bar0 64bit + false + + + + true + + + + + + pf0_bar0_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar1_enabled + Pf0 Bar0 Enabled + false + + + + true + + + + + + pf0_bar1_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf0_bar1_size + Pf0 Bar0 Size + 4 + + + + false + + + + + + pf0_bar1_scale + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf0_bar1_64bit + Pf0 Bar0 64bit + false + + + + false + + + + + + pf0_bar1_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar2_enabled + Pf0 Bar0 Enabled + false + + + + false + + + + + + pf0_bar2_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf0_bar2_size + Pf0 Bar0 Size + 4 + + + + false + + + + + + pf0_bar2_scale + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf0_bar2_64bit + Pf0 Bar0 64bit + false + + + + false + + + + + + pf0_bar2_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar3_enabled + Pf0 Bar0 Enabled + false + + + + false + + + + + + pf0_bar3_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf0_bar3_size + Pf0 Bar0 Size + 4 + + + + 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Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_6 + 0x0000000000000000 + + + + false + + + + + + bar_indicator + BAR_0 + + + + false + + + + + + bar0_indicator + 1 + + + + true + + + + + + bar1_indicator + 0 + + + + true + + + + + + bar2_indicator + 0 + + + + true + + + + + + bar3_indicator + 0 + + + + true + + + + + + bar4_indicator + 0 + + + + true + + + + + + bar5_indicator + 0 + + + + true + + + + + + barlite2 + 7 + + + en_dbg_descramble + false + + + vcu118_board + false + + + tl_pf_enable_reg + NUM PF Enable + 1 + + + pf1_vendor_id + Vendor Id + 10EE + + + pf1_device_id + PF1 Device Id + 1041 + + + pf1_class_code + Pf1 Class Code + 070001 + + + + false + + + + + + PF1_REVISION_ID + Pf1 Revision Id + 00 + + + PF1_SUBSYSTEM_VENDOR_ID + Pf1 Subsystem Vendor Id + 10EE + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0007 + + + PF1_Use_Class_Code_Lookup_Assistant + false + + + + true + + + + + + pf1_base_class_menu + Pf1 Base Class Menu + Simple_communication_controllers + + + pf1_class_code_base + Pf1 Class Code Base + 07 + + + + true + + + + + + pf1_class_code_sub + Pf1 Class Code Sub + 00 + + + + true + + + + + + pf1_sub_class_interface_menu + Pf1 Sub Class Interface Menu + 16450_compatible_serial_controller + + + + true + + + + + + pf1_class_code_interface + Pf1 Class Code Interface + 01 + + + + true + + + + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + NONE + + + pf1_msi_enabled + Pf1 Msi Enabled + false + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 1_vector + + + pf1_bar0_enabled + Pf1 Bar0 Enabled + true + + + pf1_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar0_size + Pf1 Bar0 Size + 32 + + + pf1_bar0_scale + Pf1 Bar0 Scale + Megabytes + + + pf1_bar0_64bit + Pf1 Bar0 64bit + false + + + pf1_bar0_prefetchable + Pf1 Bar0 Prefetchable + false + + + pf1_bar1_enabled + Pf1 Bar1 Enabled + true + + + pf1_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar1_size + Pf1 Bar1 Size + 128 + + + pf1_bar1_scale + Pf1 Bar1 Scale + Kilobytes + + + pf1_bar1_64bit + Pf1 Bar1 64bit + false + + + pf1_bar1_prefetchable + Pf1 Bar1 Prefetchable + false + + + pf1_bar2_enabled + Pf1 Bar2 Enabled + true + + + pf1_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar2_size + Pf1 Bar2 Size + 128 + + + pf1_bar2_scale + Pf1 Bar2 Scale + Kilobytes + + + pf1_bar2_64bit + Pf1 Bar2 64bit + true + + + pf1_bar2_prefetchable + Pf1 Bar2 Prefetchable + false + + + pf1_bar3_enabled + Pf1 Bar3 Enabled + false + + + + false + + + + + + pf1_bar3_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf1_bar3_size + Pf1 Bar3 Size + 128 + + + + false + + + + + + pf1_bar3_scale + Pf1 Bar3 Scale + Kilobytes + + + + false + + + + + + pf1_bar3_64bit + Pf1 Bar3 64bit + false + + + pf1_bar3_prefetchable + Pf1 Bar3 Prefetchable + false + + + + false + + + + + + pf1_bar4_enabled + Pf1 Bar4 Enabled + true + + + pf1_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar4_size + Pf1 Bar4 Size + 128 + + + pf1_bar4_scale + Pf1 Bar4 Scale + Kilobytes + + + pf1_bar4_64bit + Pf1 Bar4 64bit + true + + + pf1_bar4_prefetchable + Pf1 Bar4 Prefetchable + false + + + pf1_bar5_enabled + Pf1 Bar5 Enabled + false + + + + false + + + + + + pf1_bar5_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf1_bar5_size + Pf1 Bar5 Size + 128 + + + + false + + + + + + pf1_bar5_scale + Pf1 Bar5 Scale + Kilobytes + + + + false + + + + + + pf1_bar5_prefetchable + Pf1 Bar5 Prefetchable + false + + + + false + + + + + + pf2_device_id + PF2 Device Id + 1040 + + + pf2_class_code + pf2 Class Code + 058000 + + + PF2_REVISION_ID + pf2 Revision Id + 00 + + + PF2_SUBSYSTEM_VENDOR_ID + pf2 Subsystem Vendor Id + 10EE + + + PF2_SUBSYSTEM_ID + pf2 Subsystem Id + 0007 + + + PF2_Use_Class_Code_Lookup_Assistant + false + + + pf2_base_class_menu + pf2 Base Class Menu + Memory_controller + + + pf2_class_code_base + pf2 Class Code Base + 05 + + + pf2_class_code_sub + pf2 Class Code Sub + 80 + + + pf2_sub_class_interface_menu + pf2 Sub Class Interface Menu + Other_memory_controller + + + pf2_class_code_interface + pf2 Class Code Interface + 00 + + + PF2_INTERRUPT_PIN + pf2 Interrupt Pin + NONE + + + pf2_msi_enabled + pf2 Msi Enabled + false + + + PF2_MSI_CAP_MULTIMSGCAP + pf2 Msi Cap Multimsgcap + 1_vector + + + pf2_bar0_enabled + pf2 Bar0 Enabled + true + + + pf2_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar0_size + pf2 Bar0 Size + 128 + + + pf2_bar0_scale + pf2 Bar0 Scale + Kilobytes + + + pf2_bar0_64bit + pf2 Bar0 64bit + false + + + pf2_bar0_prefetchable + pf2 Bar0 Prefetchable + false + + + pf2_bar1_enabled + pf2 Bar1 Enabled + true + + + pf2_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar1_size + pf2 Bar1 Size + 128 + + + pf2_bar1_scale + pf2 Bar1 Scale + Kilobytes + + + pf2_bar1_64bit + pf2 Bar1 64bit + false + + + pf2_bar1_prefetchable + pf2 Bar1 Prefetchable + false + + + pf2_bar2_enabled + pf2 Bar2 Enabled + true + + + pf2_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar2_size + pf2 Bar2 Size + 128 + + + pf2_bar2_scale + pf2 Bar2 Scale + Kilobytes + + + pf2_bar2_64bit + pf2 Bar2 64bit + false + + + pf2_bar2_prefetchable + pf2 Bar2 Prefetchable + false + + + pf2_bar3_enabled + pf2 Bar3 Enabled + true + + + pf2_bar3_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar3_size + pf2 Bar3 Size + 128 + + + pf2_bar3_scale + pf2 Bar3 Scale + Kilobytes + + + pf2_bar3_64bit + pf2 Bar3 64bit + false + + + pf2_bar3_prefetchable + pf2 Bar3 Prefetchable + false + + + pf2_bar4_enabled + pf2 Bar4 Enabled + true + + + pf2_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar4_size + pf2 Bar4 Size + 128 + + + pf2_bar4_scale + pf2 Bar4 Scale + Kilobytes + + + pf2_bar4_64bit + pf2 Bar4 64bit + false + + + pf2_bar4_prefetchable + pf2 Bar4 Prefetchable + false + + + pf2_bar5_enabled + pf2 Bar5 Enabled + true + + + pf2_bar5_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar5_size + pf2 Bar5 Size + 128 + + + pf2_bar5_scale + pf2 Bar5 Scale + Kilobytes + + + pf2_bar5_prefetchable + pf2 Bar5 Prefetchable + false + + + pf3_device_id + PF3 Device Id + 1039 + + + pf3_class_code + Pf3 Class Code + 058000 + + + PF3_REVISION_ID + Pf3 Revision Id + 00 + + + PF3_SUBSYSTEM_VENDOR_ID + Pf3 Subsystem Vendor Id + 10EE + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0007 + + + PF3_Use_Class_Code_Lookup_Assistant + false + + + pf3_base_class_menu + Pf3 Base Class Menu + Memory_controller + + + pf3_class_code_base + Pf3 Class Code Base + 05 + + + pf3_class_code_sub + Pf3 Class Code Sub + 80 + + + pf3_sub_class_interface_menu + Pf3 Sub Class Interface Menu + Other_memory_controller + + + pf3_class_code_interface + Pf3 Class Code Interface + 00 + + + PF3_INTERRUPT_PIN + Pf3 Interrupt Pin + NONE + + + pf3_msi_enabled + Pf3 Msi Enabled + false + + + PF3_MSI_CAP_MULTIMSGCAP + Pf3 Msi Cap Multimsgcap + 1_vector + + + pf3_bar0_enabled + Pf3 Bar0 Enabled + true + + + pf3_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar0_size + Pf3 Bar0 Size + 128 + + + pf3_bar0_scale + Pf3 Bar0 Scale + Kilobytes + + + pf3_bar0_64bit + Pf3 Bar0 64bit + false + + + pf3_bar0_prefetchable + Pf3 Bar0 Prefetchable + false + + + pf3_bar1_enabled + Pf3 Bar1 Enabled + true + + + pf3_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar1_size + Pf3 Bar1 Size + 128 + + + pf3_bar1_scale + Pf3 Bar1 Scale + Kilobytes + + + pf3_bar1_64bit + Pf3 Bar1 64bit + false + + + pf3_bar1_prefetchable + Pf3 Bar1 Prefetchable + false + + + pf3_bar2_enabled + Pf3 Bar2 Enabled + true + + + pf3_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar2_size + Pf3 Bar2 Size + 128 + + + pf3_bar2_scale + Pf3 Bar2 Scale + Kilobytes + + + pf3_bar2_64bit + Pf3 Bar2 64bit + false + + + pf3_bar2_prefetchable + Pf3 Bar2 Prefetchable + false + + + pf3_bar3_enabled + Pf3 Bar3 Enabled + true + + + pf3_bar3_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar3_size + Pf3 Bar3 Size + 128 + + + pf3_bar3_scale + Pf3 Bar3 Scale + Kilobytes + + + pf3_bar3_64bit + Pf3 Bar3 64bit + false + + + pf3_bar3_prefetchable + Pf3 Bar3 Prefetchable + false + + + pf3_bar4_enabled + Pf3 Bar4 Enabled + true + + + pf3_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar4_size + Pf3 Bar4 Size + 128 + + + pf3_bar4_scale + Pf3 Bar4 Scale + Kilobytes + + + pf3_bar4_64bit + Pf3 Bar4 64bit + false + + + pf3_bar4_prefetchable + Pf3 Bar4 Prefetchable + false + + + pf3_bar5_enabled + Pf3 Bar5 Enabled + true + + + pf3_bar5_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar5_size + Pf3 Bar5 Size + 128 + + + pf3_bar5_scale + Pf3 Bar5 Scale + Kilobytes + + + pf3_bar5_prefetchable + Pf3 Bar5 Prefetchable + false + + + split_dma + false + + + split_dma_single_pf + false + + + mult_pf_des + false + + + pf_swap + false + + + prog_usr_irq_vec_map + false + + + rcfg_nph_fix_en + false + + + post_synth_sim_en + false + + + user_pf_two_axilite_bar_en + false + + + two_bypass_bar + false + + + xlnx_ref_board + Xlnx Ref Board + AU50 + + + + true + + + + + + en_l23_entry + false + + + pf1_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf1_pciebar2axibar_2 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf1_pciebar2axibar_4 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + pf1_pciebar2axibar_6 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf2_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf3_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + gtwiz_in_core_us + 1 + + + gtwiz_in_core_usp + 1 + + + dma_reset_source_sel + User_Reset + + + en_dma_and_bridge + false + + + en_coreclk_es1 + false + + + pipe_line_stage + number of Pipe Line Stages + 2 + + + + false + + + + + + axis_pipe_line_stage + number of Pipe Line Stages on PCIe axis interface + 0 + + + + false + + + + + + vu9p_tul_ex + false + + + vcu1525_ddr_ex + false + + + en_bridge + false + + + enable_ccix + FALSE + + + enable_dvsec + FALSE + + + ext_sys_clk_bufg + false + + + usr_irq_exdes + false + + + axi_vip_in_exdes + false + + + xdma_non_incremental_exdes + false + + + xdma_st_infinite_desc_exdes + false + + + gtcom_in_core_usp + 2 + + + en_mqdma + false + + + SRIOV_CAP_ENABLE + false + + + + false + + + + + + ext_xvc_vsec_enable + Enable to add the PCIe XVC-VSEC to the Examlpe Design + false + + + + false + + + + + + acs_ext_cap_enable + ACS Ext Capability + false + + + pf0_bar0_enabled_mqdma + Pf0 Bar1 Enabled + true + + + pf0_bar0_type_mqdma + Pf0 Bar0 Type + DMA + + + pf0_bar0_64bit_mqdma + Pf0 Bar0 64bit + false + + + pf0_bar0_prefetchable_mqdma + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar0_scale_mqdma + Pf0 Bar0 Scale + Kilobytes + + + pf0_bar0_size_mqdma + Pf0 Bar0 Size + 128 + + + pf0_bar1_enabled_mqdma + Pf0 Bar1 Enabled + false + + + pf0_bar1_type_mqdma + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf0_bar1_64bit_mqdma + Pf0 Bar1 64bit + false + + + + false + + + + + + pf0_bar1_prefetchable_mqdma + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf0_bar1_scale_mqdma + Pf0 Bar1 Scale + Kilobytes + + + + false + + + + + + pf0_bar1_size_mqdma + Pf0 Bar1 Size + 128 + + + + false + + + + + + pf0_bar2_enabled_mqdma + Pf0 Bar2 Enabled + false + + + pf0_bar2_type_mqdma + Pf0 Bar2 Type + N/A + + + + false + + + + + + pf0_bar2_64bit_mqdma + Pf0 Bar2 64bit + false + + + + false + + + + + + pf0_bar2_prefetchable_mqdma + Pf0 Bar2 Prefetchable + false + + + + false + + + + + + pf0_bar2_scale_mqdma + Pf0 Bar2 Scale + Kilobytes + + + + false + + + + + + pf0_bar2_size_mqdma + Pf0 Bar2 Size + 128 + + + + false + + + + + + pf0_bar3_enabled_mqdma + Pf0 Bar3 Enabled + false + + + pf0_bar3_type_mqdma + Pf0 Bar3 Type + N/A + + + + false + + + + + + pf0_bar3_64bit_mqdma + Pf0 Bar3 64bit + false + + + + false + + + + + + pf0_bar3_prefetchable_mqdma + Pf0 Bar3 Prefetchable + false + + + + false + + + + + + pf0_bar3_scale_mqdma + Pf0 Bar3 Scale + Kilobytes + + + + false + + + + + + pf0_bar3_size_mqdma + Pf0 Bar3 Size + 128 + + + + false + + + + + + pf0_bar4_enabled_mqdma + Pf0 Bar4 Enabled + false + + + pf0_bar4_type_mqdma + Pf0 Bar4 Type + N/A + + + + false + + + + + + pf0_bar4_64bit_mqdma + Pf0 Bar4 64bit + false + + + + false + + + + + + pf0_bar4_prefetchable_mqdma + Pf0 Bar4 Prefetchable + false + + + + false + + + + + + pf0_bar4_scale_mqdma + Pf0 Bar4 Scale + Kilobytes + + + + false + + + + + + pf0_bar4_size_mqdma + Pf0 Bar4 Size + 128 + + + + false + + + + + + pf0_bar5_enabled_mqdma + Pf0 Bar5 Enabled + false + + + pf0_bar5_type_mqdma + Pf0 Bar5 Type + N/A + + + + false + + + + + + pf0_bar5_prefetchable_mqdma + Pf0 Bar5 Prefetchable + false + + + pf0_bar5_scale_mqdma + Pf0 Bar5 Scale + Kilobytes + + + + false + + + + + + pf0_bar5_size_mqdma + Pf0 Bar5 Size + 128 + + + + false + + + + + + pf1_bar0_enabled_mqdma + Pf0 Bar0 Enabled + true + + + + false + + + + + + pf1_bar0_type_mqdma + Pf0 Bar0 Type + DMA + + + + false + + + + + + pf1_bar0_64bit_mqdma + Pf0 Bar0 64bit + false + + + + false + + + + + + pf1_bar0_prefetchable_mqdma + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf1_bar0_scale_mqdma + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf1_bar0_size_mqdma + Pf0 Bar0 Size + 128 + + + + false + + + + + + pf1_bar1_enabled_mqdma + Pf0 Bar1 Enabled + false + + + + false + + + + + + pf1_bar1_type_mqdma + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf1_bar1_64bit_mqdma + Pf0 Bar1 64bit + false + + + + false + + + + + + pf1_bar1_prefetchable_mqdma + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf1_bar1_scale_mqdma + Pf0 Bar1 Scale + Kilobytes + + + + false + + + + + + pf1_bar1_size_mqdma + Pf0 Bar1 Size + 128 + + + + false + + + + + + pf1_bar2_enabled_mqdma + Pf0 Bar2 Enabled + false + + + + false + + + + + + pf1_bar2_type_mqdma + Pf0 Bar2 Type + N/A + + + + false + + + + + + pf1_bar2_64bit_mqdma + Pf0 Bar2 64bit + false + + + + false + + + + + + pf1_bar2_prefetchable_mqdma + Pf0 Bar2 Prefetchable + false + + + + false + + + + + + pf1_bar2_scale_mqdma + Pf0 Bar2 Scale + Kilobytes + + + + false + + + + + + pf1_bar2_size_mqdma + Pf0 Bar2 Size + 128 + + + + false + + + + + + pf1_bar3_enabled_mqdma + Pf0 Bar3 Enabled + false + + + + false + + + + + + pf1_bar3_type_mqdma + Pf0 Bar3 Type + N/A + + + + false + + + + + + pf1_bar3_64bit_mqdma + Pf0 Bar3 64bit + false + + + + false + + + + + + pf1_bar3_prefetchable_mqdma + Pf0 Bar3 Prefetchable + false + + + + false + + + + + + pf1_bar3_scale_mqdma + Pf0 Bar3 Scale + Kilobytes + + + + false + + + + + + pf1_bar3_size_mqdma + Pf0 Bar3 Size + 128 + + + + false + + + + + + pf1_bar4_enabled_mqdma + Pf0 Bar4 Enabled + false + + + + false + + + + + + pf1_bar4_type_mqdma + Pf0 Bar4 Type + N/A + + + + false + + + + + + pf1_bar4_64bit_mqdma + Pf0 Bar4 64bit + false + + + + false + + + + + + pf1_bar4_prefetchable_mqdma + Pf0 Bar4 Prefetchable + false + + + + false + + + + + + pf1_bar4_scale_mqdma + Pf0 Bar4 Scale + Kilobytes + + + + false + + + + + + pf1_bar4_size_mqdma + Pf0 Bar4 Size + 128 + + + + false + + + + + + pf1_bar5_enabled_mqdma + Pf0 Bar5 Enabled + false + + + + false + + + + + + pf1_bar5_type_mqdma + Pf0 Bar5 Type + N/A + + + + false + + + + + + pf1_bar5_prefetchable_mqdma + Pf0 Bar5 Prefetchable + false + + + pf1_bar5_scale_mqdma + Pf0 Bar5 Scale + Kilobytes + + + + false + + + + + + pf1_bar5_size_mqdma + Pf0 Bar5 Size + 128 + + + + false + + + + + + pf2_bar0_enabled_mqdma + Pf0 Bar0 Enabled + true + + + + false + + + + + + pf2_bar0_type_mqdma + Pf0 Bar0 Type + DMA + + + + false + + + + + + pf2_bar0_64bit_mqdma + Pf0 Bar0 64bit + false + + + + false + + + + + + pf2_bar0_prefetchable_mqdma + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf2_bar0_scale_mqdma + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf2_bar0_size_mqdma + Pf0 Bar0 Size + 128 + + + + false + + + + + + pf2_bar1_enabled_mqdma + Pf0 Bar1 Enabled + false + + + + false + + + + + + pf2_bar1_type_mqdma + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf2_bar1_64bit_mqdma + Pf0 Bar1 64bit + false + + + + false + + + + + + pf2_bar1_prefetchable_mqdma + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf2_bar1_scale_mqdma + Pf0 Bar1 Scale + Kilobytes + + + + false + + + + + + pf2_bar1_size_mqdma + Pf0 Bar1 Size + 128 + + + + false + + + + + + pf2_bar2_enabled_mqdma + Pf0 Bar2 Enabled + false + + + + false + + + + + + pf2_bar2_type_mqdma + Pf0 Bar2 Type + N/A + + + + false + + + + + + pf2_bar2_64bit_mqdma + Pf0 Bar2 64bit + false + + + + false + + + + + + pf2_bar2_prefetchable_mqdma + Pf0 Bar2 Prefetchable + false + + + + false + + + + + + pf2_bar2_scale_mqdma + Pf0 Bar2 Scale + Kilobytes + + + + false + + + + + + pf2_bar2_size_mqdma + Pf0 Bar2 Size + 128 + + + + false + + + + + + pf2_bar3_enabled_mqdma + Pf0 Bar3 Enabled + false + + + + false + + + + + + pf2_bar3_type_mqdma + Pf0 Bar3 Type + N/A + + + + false + + + + + + pf2_bar3_64bit_mqdma + Pf0 Bar3 64bit + false + + + + false + + + + + + pf2_bar3_prefetchable_mqdma + Pf0 Bar3 Prefetchable + false + + + + false + + + + + + pf2_bar3_scale_mqdma + Pf0 Bar3 Scale + Kilobytes + + + + false + + + + + + pf2_bar3_size_mqdma + Pf0 Bar3 Size + 128 + + + + false + + + + + + pf2_bar4_enabled_mqdma + Pf0 Bar4 Enabled + false + + + + false + + + + + + pf2_bar4_type_mqdma + Pf0 Bar4 Type + N/A + + + + false + + + + + + pf2_bar4_64bit_mqdma + Pf0 Bar4 64bit + false + + + + false + + + + + + pf2_bar4_prefetchable_mqdma + Pf0 Bar4 Prefetchable + false + + + + false + + + + + + pf2_bar4_scale_mqdma + Pf0 Bar4 Scale + Kilobytes + + + + false + + + + + + pf2_bar4_size_mqdma + Pf0 Bar4 Size + 128 + + + + false + + + + + + pf2_bar5_enabled_mqdma + Pf0 Bar5 Enabled + false + + + + false + + + + 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Subsystem Vendor Id + 10EE + + + PF2_SUBSYSTEM_VENDOR_ID_mqdma + Pf2 Subsystem Vendor Id + 10EE + + + PF3_SUBSYSTEM_VENDOR_ID_mqdma + Pf3 Subsystem Vendor Id + 10EE + + + PF0_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF1_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF2_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF3_SUBSYSTEM_ID_mqdma + Pf3 Subsystem Id + 0007 + + + pf0_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf1_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf2_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf3_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf0_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf0_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf0_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf0_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf0_class_code_interface_mqdma + Pf1 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pf2_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf2_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + pf3_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf3_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf3_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf3_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf3_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf3_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 1 + + + pf0_sriov_cap_ver + Pf0 Sriov Cap Ver + 1 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0000 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 0 + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 00000553 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 1 + + + + false + + + + + + PF1_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + 0 + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0001 + + + + false + + + + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 00000553 + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0000 + + + + false + + + + + + PF2_SRIOV_CAP_VER + Pf2 Sriov Cap Ver + 1 + + + + false + + + + + + PF2_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF2_SRIOV_FIRST_VF_OFFSET + Pf2 Sriov First Vf Offset + 0 + + + PF2_SRIOV_FUNC_DEP_LINK + Pf2 Sriov Func Dep Link + 0002 + + + + false + + + + + + PF2_SRIOV_SUPPORTED_PAGE_SIZE + Pf2 Sriov Supported Page Size + 00000553 + + + PF2_SRIOV_VF_DEVICE_ID + Pf2 Sriov Vf Device Id + 0000 + + + + false + + + + + + PF3_SRIOV_CAP_INITIAL_VF + Pf3 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF3_SRIOV_CAP_VER + Pf3 Sriov Cap Ver + 1 + + + + false + + + + + + PF3_SRIOV_FIRST_VF_OFFSET + Pf3 Sriov First Vf Offset + 0 + + + PF3_SRIOV_FUNC_DEP_LINK + Pf3 Sriov Func Dep Link + 0003 + + + + false + + + + + + PF3_SRIOV_SUPPORTED_PAGE_SIZE + Pf3 Sriov Supported Page Size + 00000553 + + + PF3_SRIOV_VF_DEVICE_ID + Pf3 Sriov Vf Device Id + 0000 + + + + false + + + + + + pf0_ari_enabled + Pf0 Ari Enabled + false + + + pf0_msix_enabled_mqdma + Pf0 Msix Enabled + false + + + pf1_msix_enabled_mqdma + Pf1 Msix Enabled + false + + + pf2_msix_enabled_mqdma + Pf2 Msix Enabled + false + + + pf3_msix_enabled_mqdma + Pf3 Msix Enabled + false + + + PF0_MSIX_CAP_TABLE_SIZE_mqdma + Pf0 Msix Cap Table Size + 000 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_SIZE_mqdma + Pf1 Msix Cap Table Size + 000 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_SIZE_mqdma + Pf2 Msix Cap Table Size + 000 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_SIZE_mqdma + Pf3 Msix Cap Table Size + 000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_OFFSET_mqdma + Pf0 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_OFFSET_mqdma + Pf1 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_OFFSET_mqdma + Pf2 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_OFFSET_mqdma + Pf3 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF0_MSIX_CAP_PBA_OFFSET_mqdma + Pf0 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF1_MSIX_CAP_PBA_OFFSET_mqdma + Pf1 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF2_MSIX_CAP_PBA_OFFSET_mqdma + Pf2 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF3_MSIX_CAP_PBA_OFFSET_mqdma + Pf3 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_PBA_BIR_mqdma + Pf0 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_PBA_BIR_mqdma + Pf1 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_PBA_BIR_mqdma + Pf2 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_PBA_BIR_mqdma + Pf3 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + MSI_X_OPTIONS + None + + + + false + + + + + + dsc_bypass_rd_out + 0000 + + + dsc_bypass_wr_out + 0000 + + + num_queues + 1 + + + enable_auto_rxeq + False + + + enable_pcie_debug + False + + + axisten_if_enable_msg_route + 27FFF + + + en_axi_mm_mqdma + true + + + + true + + + + + + en_axi_st_mqdma + false + + + + true + + + + + + enable_more_clk + false + + + tl_credits_cd + 15 + + + tl_credits_ch + 15 + + + set_finite_credit + false + + + disable_bram_pipeline + false + + + disable_eq_synchronizer + false + + + enable_resource_reduction + false + + + c_ats_enable + ATS Extended Capability Enable + false + + + c_pri_enable + Page Request Extended Capability Enable + false + + + usplus_es1_seqnum_bypass + false + + + bridge_registers_offset_enable + false + + + enable_gen4 + true + + + local_test + false + + + gen4_eieos_0s7 + true + + + c_s_axi_supports_narrow_burst + false + + + enable_ats_switch + FALSE + + + c_ats_switch_unique_bdf + 1 + + + ctrl_skip_mask + true + + + pf0_ats_enabled + Pf0 Ats Enabled + false + + + pf0_pri_enabled + Pf0 Pri Enabled + false + + + aspm_support + ASPM Support + No_ASPM + + + pf0_aer_cap_ecrc_gen_and_check_capable + false + + + gen_pipe_debug + false + + + soft_reset_en + DMA Bridge Reset + false + + + msi_rx_pin_en + FALSE + + + msix_rx_pin_en + TRUE + + + msix_rx_decode_en + FALSE + + + + false + + + + + + intx_rx_pin_en + true + + + msix_type + MSI-X Type + HARD + + + runbit_fix + false + + + axsize_byte_access_en + false + + + enable_lane_reversal + false + + + enable_mark_debug + false + + + master_cal_only + false + + + enable_multi_pcie + false + + + rbar_enable + false + + + pf0_rbar_num + Number of Resizable BARs for PF0 + 1 + + + pf1_rbar_num + Number of Resizable BARs for PF1 + 1 + + + pf2_rbar_num + Number of Resizable BARs for PF2 + 1 + + + pf3_rbar_num + Number of Resizable BARs for PF3 + 1 + + + pf0_bar0_index + PF0 BAR0 index + 0 + + + pf0_bar1_index + PF0 BAR1 index + 7 + + + pf0_bar2_index + PF0 BAR2 index + 7 + + + pf0_bar3_index + PF0 BAR3 index + 7 + + + pf0_bar4_index + PF0 BAR4 index + 7 + + + pf0_bar5_index + PF0 BAR5 index + 7 + + + pf1_bar0_index + PF0 BAR0 index + 0 + + + pf1_bar1_index + PF1 BAR1 index + 7 + + + pf1_bar2_index + PF1 BAR2 index + 7 + + + pf1_bar3_index + PF1 BAR3 index + 7 + + + pf1_bar4_index + PF1 BAR4 index + 7 + + + pf1_bar5_index + PF1 BAR5 index + 7 + + + pf2_bar0_index + PF2 BAR0 index + 0 + + + pf2_bar1_index + PF2 BAR1 index + 7 + + + pf2_bar2_index + PF2 BAR2 index + 7 + + + pf2_bar3_index + PF2 BAR3 index + 7 + + + pf2_bar4_index + PF2 BAR4 index + 7 + + + pf2_bar5_index + PF2 BAR5 index + 7 + + + pf3_bar0_index + PF3 BAR0 index + 0 + + + pf3_bar1_index + PF3 BAR1 index + 7 + + + pf3_bar2_index + PF3 BAR2 index + 7 + + + pf3_bar3_index + PF3 BAR3 index + 7 + + + pf3_bar4_index + PF3 BAR4 index + 7 + + + pf3_bar5_index + PF3 BAR5 index + 7 + + + pf0_rbar_cap_bar0 + PF0 RBAR CAP BAR0 + 0x00000000fff0 + + + pf0_rbar_cap_bar1 + PF0 RBAR CAP BAR1 + 0x000000000000 + + + pf0_rbar_cap_bar2 + PF0 RBAR CAP BAR2 + 0x000000000000 + + + pf0_rbar_cap_bar3 + PF0 RBAR CAP BAR3 + 0x000000000000 + + + pf0_rbar_cap_bar4 + PF0 RBAR CAP BAR4 + 0x000000000000 + + + pf0_rbar_cap_bar5 + PF0 RBAR CAP BAR5 + 0x000000000000 + + + pf1_rbar_cap_bar0 + PF1 RBAR CAP BAR0 + 0x00000000fff0 + + + pf1_rbar_cap_bar1 + PF1 RBAR CAP BAR1 + 0x000000000000 + + + pf1_rbar_cap_bar2 + PF1 RBAR CAP BAR2 + 0x000000000000 + + + pf1_rbar_cap_bar3 + PF1 RBAR CAP BAR3 + 0x000000000000 + + + pf1_rbar_cap_bar4 + PF1 RBAR CAP BAR4 + 0x000000000000 + + + pf1_rbar_cap_bar5 + PF1 RBAR CAP BAR5 + 0x000000000000 + + + pf2_rbar_cap_bar0 + PF2 RBAR CAP BAR0 + 0x00000000fff0 + + + pf2_rbar_cap_bar1 + PF2 RBAR CAP BAR1 + 0x000000000000 + + + pf2_rbar_cap_bar2 + PF2 RBAR CAP BAR2 + 0x000000000000 + + + pf2_rbar_cap_bar3 + PF2 RBAR CAP BAR3 + 0x000000000000 + + + pf2_rbar_cap_bar4 + PF2 RBAR CAP BAR4 + 0x000000000000 + + + pf2_rbar_cap_bar5 + PF2 RBAR CAP BAR5 + 0x000000000000 + + + pf3_rbar_cap_bar0 + PF3 RBAR CAP BAR0 + 0x00000000fff0 + + + pf3_rbar_cap_bar1 + PF3 RBAR CAP BAR1 + 0x000000000000 + + + pf3_rbar_cap_bar2 + PF3 RBAR CAP BAR2 + 0x000000000000 + + + pf3_rbar_cap_bar3 + PF3 RBAR CAP BAR3 + 0x000000000000 + + + pf3_rbar_cap_bar4 + PF3 RBAR CAP BAR4 + 0x000000000000 + + + pf3_rbar_cap_bar5 + PF3 RBAR CAP BAR5 + 0x000000000000 + + + mpsoc_pl_rp_enable + false + + + c_smmu_en + 0 + + + enable_slave_read_64os + false + + + m_axib_num_write_scale + 1 + + + disable_gt_loc + Disable GT loc constraint delivery + false + + + use_standard_interfaces + use standard interfaces for IPI design + false + + + dma_2rp + Truncate ports for 2RP DMA design + false + + + disable_user_clock_root + true + + + flr_enable + false + + + enable_epyc_chipset_fix + false + + + usrint_expn + false + + + shell_bridge + false + + + msix_pcie_internal + false + + + broadcom_sbr_wa + false + + + tl_tx_mux_strict_priority + false + + + + + DMA/Bridge Subsystem for PCI Express + + XPM_CDC + XPM_MEMORY + XPM_FIFO + + 8 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci new file mode 100644 index 0000000..70fab9d --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci @@ -0,0 +1,318 @@ + + + xilinx.com + xci + unknown + 1.0 + + + zq_calib_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.000 + 0 + 7 + 7 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 5.931282 mW + virtexuplusHBM + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zq_calib_mem.mem + zq_calib_mem.mif + 0 + 1 + 0 + 0 + 1 + 128 + 128 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 128 + 128 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + virtexuplusHBM + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../coe/zq.coe + ALL + zq_calib_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 128 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + virtexuplusHBM + xilinx.com:au50:part0:1.3 + + xcu50 + fsvh2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml new file mode 100644 index 0000000..8f7e139 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml @@ -0,0 +1,4181 @@ + + + xilinx.com + customized_ip + zq_calib_mem + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + AXI_SLAVE_S_AXI + AXI_SLAVE + AXI_SLAVE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARBURST + + + s_axi_arburst + + + + + ARID + + + s_axi_arid + + + + + ARLEN + + + s_axi_arlen + + + + + ARREADY + + + s_axi_arready + + + + + ARSIZE + + + s_axi_arsize + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWBURST + + + s_axi_awburst + + + + + AWID + + + s_axi_awid + + + + + AWLEN + + + s_axi_awlen + + + + + AWREADY + + + s_axi_awready + + + + + AWSIZE + + + s_axi_awsize + + + + + AWVALID + + + s_axi_awvalid + + + + + BID + + + s_axi_bid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RID + + + s_axi_rid + + + + + RLAST + + + s_axi_rlast + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WLAST + + + s_axi_wlast + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 1 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 0 + + + none + + + + + HAS_BRESP + 0 + + + none + + + + + HAS_RRESP + 0 + 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It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + zq_calib_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + false + + + + + + RD_ADDR_CHNG_B + false + + + + false + + + + + + Use_Error_Injection_Pins + false + + + + false + + + + + + Error_Injection_Type + Single_Bit_Error_Injection + + + + false + + + + + + Use_Byte_Write_Enable + false + + + + true + + + + + + Byte_Size + 9 + + + + false + + + + + + Algorithm + Minimum_Area + + + + true + + + + + + Primitive + 8kx2 + + + + false + + + + + + Assume_Synchronous_Clk + false + + + + false + + + + + + Write_Width_A + 64 + + + + true + + + + + + Write_Depth_A + 128 + + + + true + + + + + + Read_Width_A + 64 + + + + true + + + + + + Operating_Mode_A + WRITE_FIRST + + + + true + + + + + + Enable_A + Use_ENA_Pin + + + + true + + + + + + Write_Width_B + 64 + + + + false + + + + + + Read_Width_B + 64 + + + + false + + + + + + Operating_Mode_B + WRITE_FIRST + + + + false + + + + + + Enable_B + Always_Enabled + + + + false + + + + + + Register_PortA_Output_of_Memory_Primitives + false + + + + true + + + + + + Register_PortA_Output_of_Memory_Core + false + + + + true + + + + + + Use_REGCEA_Pin + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Primitives + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Core + false + + + + false + + + + + + Use_REGCEB_Pin + false + + + + false + + + + + + register_porta_input_of_softecc + false + + + + false + + + + + + register_portb_output_of_softecc + false + + + + false + + + + + + Pipeline_Stages + 0 + + + + false + + + + + + Load_Init_File + true + + + + true + + + + + + Coe_File + ../../../../coe/zq.coe + + + + true + + + + + + Fill_Remaining_Memory_Locations + false + + + + true + + + + + + Remaining_Memory_Locations + 0 + + + + false + + + + + + Use_RSTA_Pin + false + + + + true + + + + + + Reset_Memory_Latch_A + false + + + + false + + + + + + Reset_Priority_A + CE + + + + false + + + + + + Output_Reset_Value_A + 0 + + + + false + + + + + + Use_RSTB_Pin + false + + + + false + + + + + + Reset_Memory_Latch_B + false + + + + false + + + + + + Reset_Priority_B + CE + + + + false + + + + + + Output_Reset_Value_B + 0 + + + + false + + + + + + Reset_Type + SYNC + + + + false + + + + + + Additional_Inputs_for_Power_Estimation + false + + + + true + + + + + + Port_A_Clock + 100 + + + + true + + + + + + Port_A_Write_Rate + 50 + + + + true + + + + + + Port_B_Clock + 0 + + + + true + + + + + + Port_B_Write_Rate + 0 + + + + true + + + + + + Port_A_Enable_Rate + 100 + + + + true + + + + + + Port_B_Enable_Rate + 0 + + + + true + + + + + + Collision_Warnings + ALL + + + + true + + + + + + Disable_Collision_Warnings + false + + + + true + + + + + + Disable_Out_of_Range_Warnings + false + + + + true + + + + + + use_bram_block + Stand_Alone + + + + true + + + + + + MEM_FILE + no_mem_loaded + + + + true + + + + + + CTRL_ECC_ALGO + NONE + + + + true + + + + + + EN_SAFETY_CKT + false + + + + false + + + + + + READ_LATENCY_A + 1 + + + + false + + + + + + READ_LATENCY_B + 1 + + + + false + + + + + + + + Block Memory Generator + + XPM_MEMORY + + 4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + -- cgit v1.2.3