From 7721980589f4c7fa811689e815a77d63f2556497 Mon Sep 17 00:00:00 2001 From: Ataberk Date: Thu, 2 May 2024 17:22:05 +0200 Subject: Add sources for U50 HBM2 --- projects/U50-HBM/verilog/project.vh | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 projects/U50-HBM/verilog/project.vh (limited to 'projects/U50-HBM/verilog/project.vh') diff --git a/projects/U50-HBM/verilog/project.vh b/projects/U50-HBM/verilog/project.vh new file mode 100644 index 0000000..607ddb5 --- /dev/null +++ b/projects/U50-HBM/verilog/project.vh @@ -0,0 +1,27 @@ +`define XUPVVH_HBM +`define HBM_BENDER + +// Row Commands +`define RNOP 0 +`define ACTT 1 +`define PREE 2 +`define PREA 3 +`define REFSB 4 +`define REFF 5 +`define PDE 6 +`define SREE 7 +`define PDX_SRX 8 +// Column Commands +`define CNOP 9 +`define RD 10 +`define RDA 11 +`define WR 12 +`define WRA 13 +//`define MRS 14 + +`define ROW_ADDR_WIDTH 14 +`define COL_ADDR_WIDTH 5 +`define BA_ADDR_WIDTH 4 +`define CMD_TYPE_WIDTH 4 +`define PC_WIDTH 1 +`define WR_DATA_WIDTH 256 \ No newline at end of file -- cgit v1.2.3