From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../ip/xdma/ip_0/ip_0/xdma_pcie3_ip_gt.xci | 1429 ++ .../ip/xdma/ip_0/ip_0/xdma_pcie3_ip_gt.xml | 22908 +++++++++++++++++++ .../sources_1/ip/xdma/ip_0/xdma_pcie3_ip.xci | 903 + .../sources_1/ip/xdma/ip_0/xdma_pcie3_ip.xml | 19273 ++++++++++++++++ 4 files changed, 44513 insertions(+) create mode 100644 projects/VU095/VU095.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie3_ip_gt.xci create mode 100644 projects/VU095/VU095.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie3_ip_gt.xml create mode 100644 projects/VU095/VU095.srcs/sources_1/ip/xdma/ip_0/xdma_pcie3_ip.xci create mode 100644 projects/VU095/VU095.srcs/sources_1/ip/xdma/ip_0/xdma_pcie3_ip.xml (limited to 'projects/VU095/VU095.srcs/sources_1/ip/xdma/ip_0') diff --git a/projects/VU095/VU095.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie3_ip_gt.xci b/projects/VU095/VU095.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie3_ip_gt.xci new file mode 100644 index 0000000..3ac6431 --- /dev/null +++ b/projects/VU095/VU095.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie3_ip_gt.xci @@ -0,0 +1,1429 @@ + + + xilinx.com + xci + unknown + 1.0 + + + xdma_pcie3_ip_gt + + + "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111" + 2 + 2000.0 + 0 + 0 + 100 + 18 + 0 + 2 + 0 + 2 + 1 + 0 + 1 + 1 + 1 + 1 + 500 + 1 + 0 + 0 + 0 + 0 + 1 + "00000000" + "00000000" + 1 + 4 + 0 + "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + "00000000" + 1 + "00000001" + 1 + 1 + 5000 + "00000000000000000000000000000000000000000000000000000000000000000000000000011100" + 1 + "1010000011" + 1 + "0101111100" + 1 + 1 + 20 + 8 + 7 + 1 + 400.0000000 + 1 + 1 + 0x000000000000000000000000000000000000000000000000 + 100 + 2 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GTH-Bandwidth_Engine + GTH-CAUI_10 + GTH-CEI_11G_SR + GTH-CPRI_10G + GTH-CPRI_10_1G + GTH-CPRI_3G + GTH-CPRI_6G + GTH-DisplayPort_1_62G + GTH-DisplayPort_2_7G + GTH-DisplayPort_5_4G + GTH-Gigabit_Ethernet + GTH-HDMI + GTH-HD_SDI + GTH-HMC_12_5G + GTH-Interlaken_10G + GTH-Interlaken_12_5G + GTH-Interlaken_6_25G + GTH-JESD204 + GTH-JESD204_3_125G + GTH-JESD204_6_375G + GTH-OTL4_10 + GTH-OTU2 + GTH-OTU2e + GTH-QSGMII + GTH-RXAUI + GTH-SATA + GTH-SRIO_Gen2 + GTH-XAUI + GTH-XLAUI + GTY-10GBASE-KR + GTY-10GBASE-R + GTY-12G_SDI + GTY-1G_10G_25G_switchable + GTY-3G_SDI + GTY-Aurora_64B66B + GTY-Aurora_8B10B + GTY-Bandwidth_Engine + GTY-CAUI_10 + GTY-CAUI_10_raw + GTY-CAUI_4 + GTY-CEI_11G_SR + GTY-CPRI_10G + GTY-CPRI_10_1G + GTY-CPRI_3G + GTY-CPRI_6G + GTY-DisplayPort_1_62G + GTY-DisplayPort_2_7G + GTY-DisplayPort_5_4G + GTY-Gigabit_Ethernet + GTY-HDMI + GTY-HD_SDI + GTY-HMC_12_5G + GTY-Interlaken_10G + GTY-Interlaken_12_5G + GTY-Interlaken_25G + GTY-JESD204 + GTY-OTL4_10 + GTY-OTU2 + GTY-OTU2e + GTY-OTU4 + GTY-RXAUI + GTY-SRIO_Gen2 + GTY-XAUI + + + choice_pairs_40d02874 + 10GBASE_KR + CUSTOM + PCIE_GEN1_GEN2 + PCIE_GEN3 + QPI + + + choice_pairs_4e550952 + NONE + EXAMPLE_DESIGN + + + choice_pairs_7b0c3758 + RX + BOTH + TX + + + choice_pairs_85f99b7f + K28.1 + K28.5 + NONE + + + choice_pairs_8846c8f0 + RAW + 8B10B + 64B66B + 64B66B_CAUI + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_88c85933 + 8B10B + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + RAW + 64B66B + 64B66B_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_93c2d4ee + CORE + EXAMPLE_DESIGN + + + choice_pairs_9c19f015 + 1 + 2 + + + choice_pairs_a537ddda + 0 + 1 + + + choice_pairs_aa541099 + AUTO + DFE + LPM + + + choice_pairs_ae574462 + OFF + PCS + PMA + AUTO + + + choice_pairs_b0974ef0 + 1 + 2 + 0 + + + choice_pairs_d4feb97d + DISABLE + ENABLE + + + choice_pairs_f05b8192 + CHANNEL + NAME + + + The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. + + + GT_TYPE + Transceiver type + For devices which contain more than one serial transceiver type, select the type of transceiver to configure + GTH + + + INTERNAL_GT_PRIM_TYPE + gthe3 + + + + false + + + + + + GT_REV + Transceiver revision + Select the serial transceiver silicon revision + 0 + + + GT_DIRECTION + Transmit and/or Receive direction + Enable transmit and/or receive + BOTH + + + RX_ENABLE + Enabled + Enable the receiver for use + true + + + + false + + + + + + TX_ENABLE + Enabled + Enable the transmitter for use + true + + + + false + + + + + + CHANNEL_ENABLE + Enable channel + Indicate whether this transceiver channel is instantiated and enabled for use + X0Y7 X0Y6 X0Y5 X0Y4 X0Y3 X0Y2 X0Y1 X0Y0 + + + TX_MASTER_CHANNEL + Master TX channel + Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) + X0Y7 + + + RX_MASTER_CHANNEL + Master RX channel + Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) + X0Y7 + + + INTERNAL_TOTAL_NUM_CHANNELS + Total number of channels + 8 + + + + false + + + + + + INTERNAL_TOTAL_NUM_COMMONS + Total number of commons required + 2 + + + + false + + + + + + LOCATE_COMMON + Include transceiver COMMON in the + If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. + CORE + + + INTERNAL_NUM_COMMONS_CORE + Number of commons in core + 2 + + + + false + + + + + + INTERNAL_NUM_COMMONS_EXAMPLE + Number of commons in example + 0 + + + + false + + + + + + INTERNAL_TX_USRCLK_FREQUENCY + 400.0000000 + + + + false + + + + + + INTERNAL_RX_USRCLK_FREQUENCY + 400.0000000 + + + + false + + + + + + RX_PPM_OFFSET + PPM offset between receiver and transmitter + Specify the PPM offset between received data and transmitted data + 0 + + + OOB_ENABLE + Enable Out of Band signaling (OOB)/Electrical Idle + Enable or disable Out of Band signaling (OOB)/Electrical Idle + false + + + + false + + + + + + RX_SSC_PPM + Spread spectrum clocking + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Insertion loss at Nyquist (dB) + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 15 + + + PCIE_CORECLK_FREQ + 500 + + + PCIE_USERCLK_FREQ + 250 + + + TX_LINE_RATE + Line rate (Gb/s) + Enter the transmitter line rate in Gb/s + 8 + + + TX_PLL_TYPE + PLL type + Select the transmitter PLL type + QPLL1 + + + TX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type + 100 + + + TX_DATA_ENCODING + Encoding + Select the encoding format for data transmission, or choose 'Raw' for no data encoding + 8B10B + + + TX_USER_DATA_WIDTH + User data width + Select the width at which the user logic will provide parallel data to the serial transceiver for transmission + 16 + + + TX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal transmitter data path + 20 + + + TX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the transmitter buffer + 0 + + + TX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection + 0 + + + + false + + + + + + TX_OUTCLK_SOURCE + TXOUTCLK source + Select the source of TXOUTCLK + TXPROGDIVCLK + + + TX_DIFF_SWING_EMPH_MODE + Differential swing and emphasis mode + Select the transmitter differential swing and emphasis mode for your application + PCIE_GEN1_GEN2 + + + RX_LINE_RATE + Line rate (Gb/s) + Enter the receiver line rate in Gb/s + 8 + + + RX_PLL_TYPE + PLL type + Select the receiver PLL type + QPLL1 + + + RX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type + 100 + + + RX_DATA_DECODING + Decoding + Select the decoding format for data reception, or choose 'Raw' for no data decoding + 8B10B + + + RX_USER_DATA_WIDTH + User data width + Select the width at which the serial transceiver will provide received parallel data to the user logic + 16 + + + RX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal receiver data path + 20 + + + RX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the receiver elastic buffer + 1 + + + RX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection + 0 + + + + false + + + + + + RX_EQ_MODE + Equalization mode + Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. + DFE + + + RX_JTOL_FC + Mask corner frequency (MHz) + Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. + 1 + + + RX_JTOL_LF_SLOPE + Mask low frequency slope (dB/decade) + Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. + -20 + + + RX_OUTCLK_SOURCE + RXOUTCLK source + Select the source of RXOUTCLK + RXOUTCLKPMA + + + SIM_CPLL_CAL_BYPASS + 1 + + + PCIE_ENABLE + true + + + RX_TERMINATION + Termination + Select the receiver termination + PROGRAMMABLE + + + RX_TERMINATION_PROG_VALUE + Programmable termination voltage (mV) + Select the termination voltage (in mV) when in programmable mode + 800 + + + RX_COUPLING + Link coupling + Select the link coupling + AC + + + RX_BUFFER_BYPASS_MODE + Receiver elastic buffer bypass mode + Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode + MULTI + + + + false + + + + + + RX_BUFFER_RESET_ON_CB_CHANGE + Reset receiver elastic buffer on channel bonding change + Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL + ENABLE + + + + false + + + + + + RX_BUFFER_RESET_ON_COMMAALIGN + Reset receiver elastic buffer on comma alignment + Control whether the receiver elastic buffer is reset on comma alignment + DISABLE + + + RX_BUFFER_RESET_ON_RATE_CHANGE + Reset receiver elastic buffer on rate change + Control whether the receiver elastic buffer is reset on rate change + ENABLE + + + TX_BUFFER_RESET_ON_RATE_CHANGE + Reset transmitter buffer on rate change + Control whether the transmitter buffer is reset on rate change + ENABLE + + + + false + + + + + + RESET_SEQUENCE_INTERVAL + Reset sequence time interval (ns) + Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval + 0 + + + RX_COMMA_PRESET + Comma value preset + K28.5 + + + RX_COMMA_VALID_ONLY + Valid comma values for 8B/10B decoding + Select the range of comma characters decoded by the 8B/10B decoder + 0 + + + RX_COMMA_P_ENABLE + Detect plus comma + Indicate whether or not the specified bit pattern is detected as a plus comma + true + + + RX_COMMA_M_ENABLE + Detect minus comma + Indicate whether or not the specified bit pattern is detected as a minus comma + true + + + RX_COMMA_DOUBLE_ENABLE + Detect combined plus/minus (double-length) comma + Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence + false + + + RX_COMMA_P_VAL + Plus comma value + Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received + 0101111100 + + + RX_COMMA_M_VAL + Minus comma value + Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received + 1010000011 + + + RX_COMMA_MASK + Mask + Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" + 1111111111 + + + RX_COMMA_ALIGN_WORD + Alignment boundary + Select which data byte boundaries are allowed for comma alignment + 1 + + + RX_COMMA_SHOW_REALIGN_ENABLE + Show realign comma + Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency + true + + + RX_SLIDE_MODE + Manual alignment (RXSLIDE) mode + Select whether to enable manual alignment, and in what mode if enabled + PMA + + + RX_CB_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable channel bonding, and how many sequences to use if enabled + 0 + + + RX_CB_LEN_SEQ + Length of each sequence + Select the number of characters in each channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_SKEW + Sequence maximum skew + Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_LEVEL + Maximum channel bonding level to be used + Select the maximum channel bonding level that will be used in the system channel bonding topology + 4 + + + + false + + + + + + RX_CB_MASK + 00000000 + + + + false + + + + + + RX_CB_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + + + + false + + + + + + RX_CB_K + 00000000 + + + + false + + + + + + RX_CB_DISP + 00000000 + + + + false + + + + + + RX_CB_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable clock correction, and how many sequences to use if enabled + 1 + + + RX_CC_LEN_SEQ + Length of each sequence + Select the number of characters in each channel clock correction sequence + 1 + + + RX_CC_PERIODICITY + Periodicity of the sequence (in bytes) + Specify the separation between clock correction sequences, in bytes + 5000 + + + RX_CC_KEEP_IDLE + Keep idle + Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received + ENABLE + + + RX_CC_PRECEDENCE + Precedence + Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time + ENABLE + + + + false + + + + + + RX_CC_REPEAT_WAIT + Minimum repetition + Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction + 0 + + + RX_CC_MASK + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + 00000000 + + + + false + + + + + + RX_CC_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000011100 + + + RX_CC_K + 00000001 + + + + false + + + + + + RX_CC_DISP + 00000000 + + + + false + + + + + + RX_CC_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_0 + Value + Specify the value for this clock correction sequence and pattern + 00011100 + + + RX_CC_K_0_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_1 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_0 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_1 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + ENABLE_OPTIONAL_PORTS + Enable optional ports + Indicate whether a port should be included + rxratemode_in rxratedone_out eyescanreset_in txdiffctrl_in drpdo_out drprdy_out drpaddr_in drpdi_in drpen_in drpwe_in cpllreset_in txoutclksel_in txresetdone_out rxpmaresetdone_out rxresetdone_out rxbufstatus_out txphaligndone_out txphinitdone_out txdlysresetdone_out rxphaligndone_out rxdlysresetdone_out rxsyncdone_out cplllock_out qpll1lock_out eyescandataerror_out loopback_in txinhibit_in txprbsforceerr_in txprbssel_in rxprbssel_in rxprbserr_out rxprbscntreset_in dmonfiforeset_in dmonitorclk_i +n dmonitorout_out rxcommadet_out rxstatus_out qpll1pd_in qpllrsvd2_in qpllrsvd3_in rxbufreset_in rxclkcorcnt_out cpllpd_in pcieeqrxeqadaptdone_in pcierstidle_in pciersttxsyncstart_in pcieuserratedone_in pcsrsvdin_in rxlpmen_in rxpd_in rxpolarity_in rxrate_in rxcdrhold_in txdeemph_in txdetectrx_in txelecidle_in txmaincursor_in txmargin_in txpd_in txpostcursor_in txprecursor_in txrate_in txswing_in bufgtce_out bufgtcemask_out bufgtdiv_out bufgtreset_out bufgtrstmask_out + gtpowergood_out pcierategen3_out pcierateidle_out pcierateqpllpd_out pcierateqpllreset_out pciesynctxsyncdone_out pcieusergen3rdy_out pcieuserphystatusrst_out pcieuserratestart_out pcsrsvdout_out phystatus_out rxelecidle_out rxprbslocked_out rxprgdivresetdone_out txprgdivresetdone_out rxvalid_out rxdfeagchold_in rxdfelfhold_in rxdfetap2hold_in rxdfetap3hold_in rxdfetap4hold_in rxdfetap5hold_in rxdfetap6hold_in rxdfetap7hold_in rxdfetap8hold_in rxdfetap9hold_in rxdfetap10hold_in rx +dfetap11hold_in rxdfetap12hold_in rxdfetap13hold_in rxdfetap14hold_in rxdfetap15hold_in rxdfeuthold_in rxdfevphold_in rxoshold_in rxlpmgchold_in rxlpmhfhold_in rxlpmlfhold_in rxlpmoshold_in + + + RX_REFCLK_SOURCE + Receiver reference clock source + Select a reference clock input to drive the PLL chosen for receiver operation + + + + TX_REFCLK_SOURCE + Transmitter reference clock source + Select a reference clock input to drive the PLL chosen for transmitter operation + + + + RX_RECCLK_OUTPUT + Drive recovered clock out of device + Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use + + + + LOCATE_RESET_CONTROLLER + Include reset controller in the + Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + LOCATE_TX_BUFFER_BYPASS_CONTROLLER + Include transmitter buffer bypass controller in the + If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + LOCATE_RX_BUFFER_BYPASS_CONTROLLER + Include receiver elastic buffer bypass controller in the + If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_IN_SYSTEM_IBERT_CORE + Include In-System IBERT core + Indicate whether or not the In-System IBERT core should be instantiated in the example design. + NONE + + + LOCATE_TX_USER_CLOCKING + Include simple transmitter user clocking network in the + Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_RX_USER_CLOCKING + Include simple receiver user clocking network in the + Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_USER_DATA_WIDTH_SIZING + Include user data width sizing in the + Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + ORGANIZE_PORTS_BY + In the example design, organize ports across multiple channels by + If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) + NAME + + + PRESET + Transceiver configuration preset + You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard + None + + + INTERNAL_PRESET + Transceiver configuration preset + None + + + INTERNAL_PORT_USAGE_UPDATED + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLEMENT_UPDATED + 24 + + + + false + + + + + + INTERNAL_CHANNEL_SITES_UPDATED + 5 + + + + false + + + + + + INTERNAL_CHANNEL_COLUMN_LOC_MAX + 96 + + + + false + + + + + + INTERNAL_RX_COMMA_PRESET_UPDATE + 8 + + + + false + + + + + + INTERNAL_UPDATE_IP_SYMBOL_drpclk_in + true + + + + false + + + + + + SECONDARY_QPLL_ENABLE + Enable secondary QPLL + Enable and configure the QPLL which is not used in this core configuration + false + + + SECONDARY_QPLL_LINE_RATE + Line rate of second core (Gb/s) + Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL + 10.3125 + + + + false + + + + + + SECONDARY_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection + 0 + + + + false + + + + + + SECONDARY_QPLL_REFCLK_FREQUENCY + Actual Reference clock frequency (MHz) + Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate + 257.8125 + + + + false + + + + + + TXPROGDIV_FREQ_ENABLE + Enable selectable TXOUTCLK frequency + Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency + true + + + TXPROGDIV_FREQ_SOURCE + Programmable divider clock source + Select which PLL source is used to generate the selectable TXOUTCLK frequency + CPLL + + + TXPROGDIV_FREQ_VAL + TXOUTCLK frequency (MHz) + Select the TXOUTCLK frequency to be generated by the TX programmable divider + 400 + + + SATA_TX_BURST_LEN + TX COM sequence burst length + Select the number of bursts that make up a SATA COM sequence + 15 + + + FREERUN_FREQUENCY + Free-running and DRP clock frequency (MHz) + Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface + 100 + + + INCLUDE_CPLL_CAL + 2 + + + USER_GTPOWERGOOD_DELAY_EN + Select 1 to enable powergood delay circuit + 1 + + + DISABLE_LOC_XDC + Select to disable generation of LOC constraints in xdc + 0 + + + ENABLE_COMMON_USRCLK + 0 + + + USB_ENABLE + false + + + PCIE_64BIT + false + + + PCIE_GEN4_EIOS + false + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGBYPASSB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGMONITORENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGPDB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK01_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0PD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0RESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1PD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1RESET_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD2_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD3_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD4_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RCALENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0DATA_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0WIDTH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1DATA_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1WIDTH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONGPI_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONPOWERUP_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONRESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBDO_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBDRDY_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBENABLE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBGPI_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBINTR_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBIOLMBRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMBRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMREGEN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMTCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMTDI_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT + 0 + + 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+ + + + + INTERNAL_PORT_ENABLED_CDRSTEPSX_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CFGRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLFREQLOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLPD_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DMONFIFORESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DMONITORCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPADDR_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDI_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANMODE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_FREQOS_IN + -1 + + + + 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+ + m_axis_rc + m_axis_rc + The Requestor Completer interface transmits completions to the client application + + + + + + + TDATA + + + m_axis_rc_tdata + + + + + TKEEP + + + m_axis_rc_tkeep + + + + + TLAST + + + m_axis_rc_tlast + + + + + TREADY + + + m_axis_rc_tready + + + + + TUSER + + + m_axis_rc_tuser + + + + + TVALID + + + m_axis_rc_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 75 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + pcie_7x_mgt + pcie_7x_mgt + PCIExpress Serial Link Interface + + + + + + + rxn + + + pci_exp_rxn + + + + + rxp + + + pci_exp_rxp + + + + + txn + + + pci_exp_txn + + + + + txp + + + pci_exp_txp + + + + + + pcie_cfg_fc + pcie_cfg_fc + Configuration Flow Control INTERFACE + + + + + + + CPLD + + + cfg_fc_cpld + + + + + CPLH + + + cfg_fc_cplh + + + + + NPD + + + cfg_fc_npd + + + + + NPH + + + cfg_fc_nph + + + + + PD + + + cfg_fc_pd + + + + + PH + + + cfg_fc_ph + + + + + SEL + + + cfg_fc_sel + + + + + + + true + + + + + + pcie_cfg_mgmt + pcie_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr + + + + + BYTE_EN + + + cfg_mgmt_byte_enable + + + + + READ_DATA + + + cfg_mgmt_read_data + + + + + READ_EN + + + cfg_mgmt_read + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done + + + + + TYPE1_CFG_REG_ACCESS + + + cfg_mgmt_type1_cfg_reg_access + + + + + WRITE_DATA + + + cfg_mgmt_write_data + + + + + WRITE_EN + + + cfg_mgmt_write + + + + + + + true + + + + + + pcie3_cfg_msi + pcie3_us_cfg_msi + PCIE MSI interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr + + + + + data + + + cfg_interrupt_msi_data + + + + + enable + + + cfg_interrupt_msi_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msi_int + + + + + mask_update + + + cfg_interrupt_msi_mask_update + + + + + mmenable + + + cfg_interrupt_msi_mmenable + + + + + pending_status + + + cfg_interrupt_msi_pending_status + + + + + pending_status_data_enable + + + cfg_interrupt_msi_pending_status_data_enable + + + + + pending_status_function_num + + + cfg_interrupt_msi_pending_status_function_num + + + + + select + + + cfg_interrupt_msi_select + + + + + sent + + + cfg_interrupt_msi_sent + + + + + tph_present + + + cfg_interrupt_msi_tph_present + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag + + + + + tph_type + + + cfg_interrupt_msi_tph_type + + + + + vf_enable + + + cfg_interrupt_msi_vf_enable + + + + + + + true + + + + + + pcie3_cfg_msix + pcie3_us_cfg_msix + PCIE MSIx Interrupt + + + + + + + address + + + cfg_interrupt_msix_address + + + + + data + + + cfg_interrupt_msix_data + + + + + enable + + + cfg_interrupt_msix_enable + + + + + fail + + + cfg_interrupt_msix_fail + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + sent + + + cfg_interrupt_msix_sent + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie3_cfg_interrupt + pcie3_cfg_interrupt + PCIE Legacy Interrupt + + + + + + + INTx_VECTOR + + + cfg_interrupt_int + + + + + PENDING + + + cfg_interrupt_pending + + + + + SENT + + + cfg_interrupt_sent + + + + + + pcie3_cfg_ext + pcie3_us_cfg_ext + Configuration Extend Interface + + + + + + + function_number + + + cfg_ext_function_number + + + + + read_data + + + cfg_ext_read_data + + + + + read_data_valid + + + cfg_ext_read_data_valid + + + + + read_received + + + cfg_ext_read_received + + + + + register_number + + + cfg_ext_register_number + + + + + write_byte_enable + + + cfg_ext_write_byte_enable + + + + + write_data + + + cfg_ext_write_data + + + + + write_received + + + cfg_ext_write_received + + + + + + + false + + + + + + pcie3_cfg_mesg_tx + pcie3_us_cfg_mesg_tx + Configuration Transmit Message Interface + + + + + + + TRANSMIT + + + cfg_msg_transmit + + + + + TRANSMIT_DATA + + + cfg_msg_transmit_data + + + + + TRANSMIT_DONE + + + cfg_msg_transmit_done + + + + + TRANSMIT_TYPE + + + cfg_msg_transmit_type + + + + + + + true + + + + + + pcie3_cfg_mesg_rcvd + pcie3_us_cfg_mesg_rcvd + Configuration Received Message Interface + + + + + + + recd + + + cfg_msg_received + + + + + recd_data + + + cfg_msg_received_data + + + + + recd_type + + + cfg_msg_received_type + + + + + + + true + + + + + + pcie3_cfg_control + pcie3_us_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + config_space_enable + + + cfg_config_space_enable + + + + + ds_bus_number + + + cfg_ds_bus_number + + + + + ds_device_number + + + cfg_ds_device_number + + + + + ds_function_number + + + cfg_ds_function_number + + + + + ds_port_number + + + cfg_ds_port_number + + + + + dsn + + + cfg_dsn + + + + + err_cor_in + + + cfg_err_cor_in + + + + + err_uncor_in + + + cfg_err_uncor_in + + + + + flr_done + + + cfg_flr_done + + + + + flr_in_process + + + cfg_flr_in_process + + + + + hot_reset_in + + + cfg_hot_reset_in + + + + + hot_reset_out + + + cfg_hot_reset_out + + + + + link_training_enable + + + cfg_link_training_enable + + + + + local_error + + + cfg_local_error + + + + + per_function_number + + + cfg_per_function_number + + + + + per_function_output_request + + + cfg_per_function_output_request + + + + + per_function_update_done + + + cfg_per_function_update_done + + + + + power_state_change_ack + + + cfg_power_state_change_ack + + + + + power_state_change_interrupt + + + cfg_power_state_change_interrupt + + + + + req_pm_transition_l23_ready + + + cfg_req_pm_transition_l23_ready + + + + + subsys_vend_id + + + cfg_subsys_vend_id + + + + + vf_flr_done + + + cfg_vf_flr_done + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process + + + + + + + true + + + + + + pcie3_per_func_status + pcie3_us_per_func_status + Per Function Status Interface + + + + + + + STATUS_CONTROL + + + cfg_per_func_status_control + + + + + STATUS_DATA + + + cfg_per_func_status_data + + + + + + + true + + + + + + pcie3_user_tph + pcie3_us_user_tph + PCIE TPH Interface + + + + + + + function_num + + + user_tph_function_num + + + + + stt_address + + + user_tph_stt_address + + + + + stt_read_data + + + user_tph_stt_read_data + + + + + stt_read_data_valid + + + user_tph_stt_read_data_valid + + + + + stt_read_enable + + + user_tph_stt_read_enable + + + + + + + false + + + + + + pcie3_cfg_status + pcie3_us_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req + + + + + cq_np_req_count + + + pcie_cq_np_req_count + + + + + current_speed + + + cfg_current_speed + + + + + dpa_substate_change + + + cfg_dpa_substate_change + + + + + err_cor_out + + + cfg_err_cor_out + + + + + err_fatal_out + + + cfg_err_fatal_out + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out + + + + + function_power_state + + + cfg_function_power_state + + + + + function_status + + + cfg_function_status + + + + + link_power_state + + + cfg_link_power_state + + + + + ltr_enable + + + cfg_ltr_enable + + + + + ltssm_state + + + cfg_ltssm_state + + + + + max_payload + + + cfg_max_payload + + + + + max_read_req + + + cfg_max_read_req + + + + + negotiated_width + + + cfg_negotiated_width + + + + + obff_enable + + + cfg_obff_enable + + + + + phy_link_down + + + cfg_phy_link_down + + + + + phy_link_status + + + cfg_phy_link_status + + + + + pl_status_change + + + cfg_pl_status_change + + + + + rcb_status + + + cfg_rcb_status + + + + + rq_seq_num + + + pcie_rq_seq_num + + + + + rq_seq_num_vld + + + pcie_rq_seq_num_vld + + + + + rq_tag + + + pcie_rq_tag + + + + + rq_tag_av + + + pcie_rq_tag_av + + + + + rq_tag_vld + + + pcie_rq_tag_vld + + + + + tfc_npd_av + + + pcie_tfc_npd_av + + + + + tfc_nph_av + + + pcie_tfc_nph_av + + + + + tph_requester_enable + + + cfg_tph_requester_enable + + + + + tph_st_mode + + + cfg_tph_st_mode + + + + + vf_power_state + + + cfg_vf_power_state + + + + + vf_status + + + cfg_vf_status + + + + + vf_tph_requester_enable + + + cfg_vf_tph_requester_enable + + + + + vf_tph_st_mode + + + cfg_vf_tph_st_mode + + + + + + + true + + + + + + pcie3_transmit_fc + pcie3_us_transmit_fc + Transmit Flow Control Interfce + + + + + + + npd_av + + + pcie_tfc_npd_av + + + + + nph_av + + + pcie_tfc_nph_av + + + + + + + true + + + + + + pcie3_us_drp + pcie3_us_drp + PCIE DRP Interface + + + + + + + DADDR + + + drp_addr + + + + + DEN + + + drp_en + + + + + DI + + + drp_di + + + + + DO + + + drp_do + + + + + DRDY + + + drp_rdy + + + + + DWE + + + drp_we + + + + + + + false + + + + + + CLK.sys_clk + CLK.sys_clk + sys_clk interface + + + + + + + CLK + + + sys_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + CLK.sys_clk_gt + CLK.sys_clk_gt + sys_clk_gt interface + + + + + + + CLK + + + sys_clk_gt + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + RST.sys_rst + RST.sys_rst + sys_rst interface + + + + + + + RST + + + sys_reset + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + + + CLK.user_clk + CLK.user_clk + user_clk interface + + + + + + + CLK + + + user_clk + + + + + + ASSOCIATED_BUSIF + m_axis_cq:s_axis_cc:s_axis_rq:m_axis_rc + + + FREQ_HZ + 125000000 + + + ASSOCIATED_RESET + user_reset + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.user_reset + RST.user_reset + user_reset interface + + + + + + + RST + + + user_reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + pcie3_pl + pcie3_pl + Physical Layer Interface + + + + + + + eq_in_progress + + + pl_eq_in_progress + + + + + eq_phase + + + pl_eq_phase + + + + + eq_reset_eieos_count + + + pl_eq_reset_eieos_count + + + + + gen2_upstream_prefer_deemph + + + pl_gen2_upstream_prefer_deemph + + + + + + + false + + + + + + configure + configure + + + + + + + req_data + + + conf_req_data + + + + + req_ready + + + conf_req_ready + + + + + req_reg_num + + + conf_req_reg_num + + + + + req_type + + + conf_req_type + + + + + req_valid + + + conf_req_valid + + + + + resp_rdata + + + conf_resp_rdata + + + + + resp_valid + + + conf_resp_valid + + + + + + + false + + + + + + cap + cap + + + + + + + GNT + + + cap_gnt + + + + + REL + + + cap_rel + + + + + REQ + + + cap_req + + + + + + + false + + + + + + startup + startup + STARTUP Interface + + + + + + + cfgclk + + + startup_cfgclk + + + + + cfgmclk + + + startup_cfgmclk + + + + + di + + + startup_di + + + + + do + + + startup_do + + + + + dts + + + startup_dts + + + + + eos + + + startup_eos + + + + + fcsbo + + + startup_fcsbo + + + + + fcsbts + + + startup_fcsbts + + + + + gsr + + + startup_gsr + + + + + gts + + + startup_gts + + + + + keyclearb + + + startup_keyclearb + + + + + pack + + + startup_pack + + + + + preq + + + startup_preq + + + + + userdoneo + + + startup_usrdoneo + + + + + usrcclko + + + startup_usrcclko + + + + + usrclkts + + + startup_usrcclkts + + + + + usrdonets + + + startup_usrdonets + + + + + + + false + + + + + + pcie3_ext_pipe_rp + pcie3_ext_pipe_rp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_in + + + + + COMMANDS_OUT + + + common_commands_out + + + + + RX_0 + + + pipe_rx_0_sigs + + + + + RX_1 + + + pipe_rx_1_sigs + + + + + RX_2 + + + pipe_rx_2_sigs + + + + + RX_3 + + + pipe_rx_3_sigs + + + + + RX_4 + + + pipe_rx_4_sigs + + + + + RX_5 + + + pipe_rx_5_sigs + + + + + RX_6 + + + pipe_rx_6_sigs + + + + + RX_7 + + + pipe_rx_7_sigs + + + + + TX_0 + + + pipe_tx_0_sigs + + + + + TX_1 + + + pipe_tx_1_sigs + + + + + TX_2 + + + pipe_tx_2_sigs + + + + + TX_3 + + + pipe_tx_3_sigs + + + + + TX_4 + + + pipe_tx_4_sigs + + + + + TX_5 + + + pipe_tx_5_sigs + + + + + TX_6 + + + pipe_tx_6_sigs + + + + + TX_7 + + + pipe_tx_7_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_ep + pcie3_ext_pipe_ep + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_ep_legacy + pcie3_ext_pipe_ep_legacy + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + + + false + + + + + + pcie3_us_ext_shared_logic + pcie3_us_ext_shared_logic + PCIE3 Ultrascale External Shared Logic Interface + + + + + + + exts_qpll1lock_out + + + ext_qpll1lock_out + + + + + exts_qpll1outclk_out + + + ext_qpll1outclk_out + + + + + exts_qpll1outrefclk_out + + + ext_qpll1outrefclk_out + + + + + exts_qpll1pd + + + ext_qpll1pd + + + + + exts_qpll1rate + + + ext_qpll1rate + + + + + exts_qpll1refclk + + + ext_qpll1refclk + + + + + exts_qpll1reset + + + ext_qpll1reset + + + + + + + false + + + + + + pcie3_us_int_shared_logic + pcie3_us_int_shared_logic + PCIE3 Ultrascale Internal Shared Logic Interface + + + + + + + ints_qpll1lock_out + + + int_qpll1lock_out + + + + + ints_qpll1outclk_out + + + int_qpll1outclk_out + + + + + ints_qpll1outrefclk_out + + + int_qpll1outrefclk_out + + + + + + + true + + + + + + pcie_ext_ch_gt + pcie_ext_ch_gt + channel DRP signals + + + + + + + DADDR + + + ext_ch_gt_drpaddr + + + + + DEN + + + ext_ch_gt_drpen + + + + + DI + + + ext_ch_gt_drpdi + + + + + DO + + + ext_ch_gt_drpdo + + + + + DRDY + + + ext_ch_gt_drprdy + + + + + DWE + + + ext_ch_gt_drpwe + + + + + + + false + + + + + + pcie3_us_gt_if + pcie3_us_gt_if + GT Interface + + + + + + + bufgtce_out + + + bufgtce_out + + + + + bufgtcemask_out + + + bufgtcemask_out + + + + + bufgtdiv_out + + + bufgtdiv_out + + + + + bufgtreset_out + + + bufgtreset_out + + + + + bufgtrstmask_out + + + bufgtrstmask_out + + + + + cplllock_out + + + cplllock_out + + + + + cpllpd_in + + + cpllpd_in + + + + + cpllreset_in + + + cpllreset_in + + + + + dmonfiforeset_in + + + dmonfiforeset_in + + + + + dmonitorclk_in + + + dmonitorclk_in + + + + + dmonitorout_out + + + dmonitorout_out + + + + + drpaddr_in + + + drpaddr_in + + + + + drpclk_in + + + drpclk_in + + + + + drpdi_in + + + drpdi_in + + + + + drpdo_out + + + drpdo_out + + + + + drpen_in + + + drpen_in + + + + + drprdy_out + + + drprdy_out + + + + + drpwe_in + + + drpwe_in + + + + + eyescandataerror_out + + + eyescandataerror_out + + + + + eyescanreset_in + + + eyescanreset_in + + + + + gthrxn_in + + + gthrxn_in + + + + + gthrxp_in + + + gthrxp_in + + + + + gthtxn_out + + + gthtxn_out + + + + + gthtxp_out + + + gthtxp_out + + + + + gtpowergood_out + + + gtpowergood_out + + + + + gtrefclk0_in + + + gtrefclk0_in + + + + + gtrefclk01_in + + + gtrefclk01_in + + + + + gtrxreset_in + + + gtrxreset_in + + + + + gttxreset_in + + + gttxreset_in + + + + + gtwiz_reset_rx_done_in + + + gtwiz_reset_rx_done_in + + + + + gtwiz_reset_tx_done_in + + + gtwiz_reset_tx_done_in + + + + + gtwiz_userclk_rx_active_in + + + gtwiz_userclk_rx_active_in + + + + + gtwiz_userclk_tx_active_in + + + gtwiz_userclk_tx_active_in + + + + + gtwiz_userclk_tx_reset_in + + + gtwiz_userclk_tx_reset_in + + + + + loopback_in + + + loopback_in + + + + + pcieeqrxeqadaptdone_in + + + pcieeqrxeqadaptdone_in + + + + + pcierategen3_out + + + pcierategen3_out + + + + + pcierateidle_out + + + pcierateidle_out + + + + + pcierateqpllpd_out + + + pcierateqpllpd_out + + + + + pcierateqpllreset_out + + + pcierateqpllreset_out + + + + + pcierstidle_in + + + pcierstidle_in + + + + + pciersttxsyncstart_in + + + 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PF0_ARI_CAP_NEXT_FUNC + Pf0 ARI Cap Next Func + 0x00 + + + AXISTEN_IF_CC_ALIGNMENT_MODE + Axisten If Cc Alignment Mode + TRUE + + + AXISTEN_IF_CQ_ALIGNMENT_MODE + Axisten If Cq Alignment Mode + TRUE + + + AXISTEN_IF_RC_ALIGNMENT_MODE + Axisten If Rc Alignment Mode + FALSE + + + AXISTEN_IF_RC_STRADDLE + Axisten If Rc Straddle + TRUE + + + AXISTEN_IF_RQ_ALIGNMENT_MODE + Axisten If Rq Alignment Mode + FALSE + + + AXISTEN_IF_ENABLE_MSG_ROUTE + 0x20000 + + + AXISTEN_IF_ENABLE_RX_MSG_INTFC + FALSE + + + PF0_AER_CAP_ECRC_CHECK_CAPABLE + Pf0 Aer Cap Ecrc Check Capable + FALSE + + + PF0_AER_CAP_ECRC_GEN_CAPABLE + Pf0 Aer Cap Ecrc Gen Capable + FALSE + + + PF0_AER_CAP_NEXTPTR + Pf0 Aer Cap Nextptr + 0x300 + + + PF0_ARI_CAP_NEXTPTR + Pf0 Ari Cap Nextptr + 0x000 + + + VF0_ARI_CAP_NEXTPTR + Vf0 Ari Cap Nextptr + 0x000 + + + VF1_ARI_CAP_NEXTPTR + Vf1 Ari Cap Nextptr + 0x000 + + + VF2_ARI_CAP_NEXTPTR + Vf2 Ari Cap Nextptr + 0x000 + + + VF3_ARI_CAP_NEXTPTR + Vf3 Ari Cap Nextptr + 0x000 + + + VF4_ARI_CAP_NEXTPTR + Vf4 Ari Cap Nextptr + 0x000 + + + VF5_ARI_CAP_NEXTPTR + Vf5 Ari Cap Nextptr + 0x000 + + + PF0_BAR0_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x09 + + + PF0_BAR0_CONTROL + Pf0 Bar0 Control + 0x4 + + + PF0_BAR1_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x00 + + + PF0_BAR1_CONTROL + Pf0 Bar1 Control + 0x0 + + + PF0_BAR2_APERTURE_SIZE + Pf0 Bar2 Aperture Size + 0x00 + + + PF0_BAR2_CONTROL + Pf0 Bar2 Control + 0x0 + + + PF0_BAR3_APERTURE_SIZE + Pf0 Bar3 Aperture Size + 0x00 + + + PF0_BAR3_CONTROL + Pf0 Bar3 Control + 0x0 + + + PF0_BAR4_APERTURE_SIZE + Pf0 Bar4 Aperture Size + 0x00 + + + PF0_BAR4_CONTROL + Pf0 Bar4 Control + 0x0 + + + PF0_BAR5_APERTURE_SIZE + Pf0 Bar5 Aperture Size + 0x00 + + + PF0_BAR5_CONTROL + Pf0 Bar5 Control + 0x0 + + + PF0_CAPABILITY_POINTER + Pf0 Capability Pointer + 0x80 + + + PF0_CLASS_CODE + Pf0 Class Code + 0x070001 + + + PF0_VENDOR_ID + Pf0 Vendor Id + 0x10EE + + + PF0_DEVICE_ID + Pf0 Device Id + 0x8038 + + + PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 128b Cas Atomic Completer Support + FALSE + + + PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 32b Atomic Completer Support + FALSE + + + PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 64b Atomic Completer Support + FALSE + + + PF0_DEV_CAP2_LTR_SUPPORT + Pf0 Dev Cap2 Ltr Support + FALSE + + + PF0_DEV_CAP2_OBFF_SUPPORT + Pf0 Dev Cap2 Obff Support + 0x0 + + + PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT + Pf0 Dev Cap2 Tph Completer Support + FALSE + + + PF0_DEV_CAP_EXT_TAG_SUPPORTED + Pf0 Dev Cap Ext Tag Supported + TRUE + + + PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE + Pf0 Dev Cap Function Level Reset Capable + FALSE + + + PF0_DEV_CAP_MAX_PAYLOAD_SIZE + Pf0 Dev Cap Max Payload Size + 0x2 + + + PF0_DPA_CAP_NEXTPTR + Pf0 Dpa Cap Nextptr + 0x300 + + + PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 + Pf0 DPA Cap Sub State Power Allocation0 + 0x00 + + + PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 + Pf0 DPA Cap Sub State Power Allocation1 + 0x00 + + + PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 + Pf0 DPA Cap Sub State Power Allocation2 + 0x00 + + + PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 + Pf0 DPA Cap Sub State Power Allocation3 + 0x00 + + + PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 + Pf0 DPA Cap Sub State Power Allocation4 + 0x00 + + + PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 + Pf0 DPA Cap Sub State Power Allocation5 + 0x00 + + + PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 + Pf0 DPA Cap Sub State Power Allocation6 + 0x00 + + + PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 + Pf0 DPA Cap Sub State Power Allocation7 + 0x00 + + + PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 + Pf1 DPA Cap Sub State Power Allocation0 + 0x00 + + + PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 + Pf1 DPA Cap Sub State Power Allocation1 + 0x00 + + + PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 + Pf1 DPA Cap Sub State Power Allocation2 + 0x00 + + + PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 + Pf1 DPA Cap Sub State Power Allocation3 + 0x00 + + + PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 + Pf1 DPA Cap Sub State Power Allocation4 + 0x00 + + + PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 + Pf1 DPA Cap Sub State Power Allocation5 + 0x00 + + + PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 + Pf1 DPA Cap Sub State Power Allocation6 + 0x00 + + + PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 + Pf1 DPA Cap Sub State Power Allocation7 + 0x00 + + + PF0_DSN_CAP_NEXTPTR + Pf0 Dsn Cap Nextptr + 0x300 + + + PF0_EXPANSION_ROM_APERTURE_SIZE + Pf0 Expansion Rom Aperture Size + 0x00 + + + PF0_EXPANSION_ROM_ENABLE + Pf0 Expansion Rom Enable + FALSE + + + PF0_INTERRUPT_PIN + Pf0 Interrupt Pin + 0x1 + + + PF0_LINK_STATUS_SLOT_CLOCK_CONFIG + Pf0 Link Status Slot Clock Config + TRUE + + + PF0_LTR_CAP_NEXTPTR + Pf0 Ltr Cap Nextptr + 0x300 + + + PF0_MSIX_CAP_NEXTPTR + Pf0 Msix Cap Nextptr + 0x00 + + + PF0_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + PF0_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + PF0_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + PF0_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + PF0_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + PF0_MSI_CAP_MULTIMSGCAP + Pf0 Msi Cap Multimsgcap + 0 + + + PF0_MSI_CAP_NEXTPTR + Pf0 Msi Cap Nextptr + 0xC0 + + + PF0_PB_CAP_NEXTPTR + Pf0 Pb Cap Nextptr + 0x274 + + + PF0_PM_CAP_NEXTPTR + Pf0 Pm Cap Nextptr + 0x90 + + + PF0_PM_CAP_PMESUPPORT_D0 + Pf0 Pm Cap Pmesupport D0 + FALSE + + + PF0_PM_CAP_PMESUPPORT_D1 + Pf0 Pm Cap Pmesupport D1 + FALSE + + + PF0_PM_CAP_PMESUPPORT_D3HOT + Pf0 Pm Cap Pmesupport D3hot + FALSE + + + PF0_PM_CAP_SUPP_D1_STATE + Pf0 Pm Cap Supp D1 State + FALSE + + + PF0_RBAR_CAP_ENABLE + Pf0 Rbar Cap Enable + FALSE + + + PF0_RBAR_CAP_NEXTPTR + Pf0 Rbar Cap Nextptr + 0x300 + + + PF0_RBAR_CAP_SIZE0 + Pf0 Rbar Cap Size0 + 0x00000 + + + PF0_RBAR_CAP_SIZE1 + Pf0 Rbar Cap Size1 + 0x00000 + + + PF0_RBAR_CAP_SIZE2 + Pf0 Rbar Cap Size2 + 0x00000 + + + PF1_RBAR_CAP_SIZE0 + Pf1 Rbar Cap Size0 + 0x00000 + + + PF1_RBAR_CAP_SIZE1 + Pf1 Rbar Cap Size1 + 0x00000 + + + PF1_RBAR_CAP_SIZE2 + Pf1 Rbar Cap Size2 + 0x00000 + + + PF0_REVISION_ID + Pf0 Revision Id + 0x00 + + + PF0_SRIOV_BAR0_APERTURE_SIZE + Pf0 Sriov Bar0 Aperture Size + 0x00 + + + PF0_SRIOV_BAR0_CONTROL + Pf0 Sriov Bar0 Control + 0x0 + + + PF0_SRIOV_BAR1_APERTURE_SIZE + Pf0 Sriov Bar1 Aperture Size + 0x00 + + + PF0_SRIOV_BAR1_CONTROL + Pf0 Sriov Bar1 Control + 0x0 + + + PF0_SRIOV_BAR2_APERTURE_SIZE + Pf0 Sriov Bar2 Aperture Size + 0x00 + + + PF0_SRIOV_BAR2_CONTROL + Pf0 Sriov Bar2 Control + 0x0 + + + PF0_SRIOV_BAR3_APERTURE_SIZE + Pf0 Sriov Bar3 Aperture Size + 0x00 + + + PF0_SRIOV_BAR3_CONTROL + Pf0 Sriov Bar3 Control + 0x0 + + + PF0_SRIOV_BAR4_APERTURE_SIZE + Pf0 Sriov Bar4 Aperture Size + 0x00 + + + PF0_SRIOV_BAR4_CONTROL + Pf0 Sriov Bar4 Control + 0x0 + + + PF0_SRIOV_BAR5_APERTURE_SIZE + Pf0 Sriov Bar5 Aperture Size + 0x00 + + + PF0_SRIOV_BAR5_CONTROL + Pf0 Sriov Bar5 Control + 0x0 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0x0000 + + + PF0_SRIOV_CAP_NEXTPTR + Pf0 Sriov Cap Nextptr + 0x300 + + + PF0_SRIOV_CAP_TOTAL_VF + Pf0 Sriov Cap Total Vf + 0x0000 + + + PF0_SRIOV_CAP_VER + Pf0 Sriov Cap Ver + 0x0 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 0x0000 + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0x0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 0x00000553 + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0x0000 + + + PF0_SUBSYSTEM_VENDOR_ID + Pf0 Subsystem Vendor Id + 0x10EE + + + PF0_SUBSYSTEM_ID + Pf0 Subsystem Id + 0x0007 + + + PF0_TPHR_CAP_ENABLE + Pf0 Tphr Cap Enable + FALSE + + + PF0_TPHR_CAP_NEXTPTR + Pf0 Tphr Cap Nextptr + 0x300 + + + VF0_TPHR_CAP_NEXTPTR + Vf0 Tphr Cap Nextptr + 0x000 + + + VF1_TPHR_CAP_NEXTPTR + Vf1 Tphr Cap Nextptr + 0x000 + + + VF2_TPHR_CAP_NEXTPTR + Vf2 Tphr Cap Nextptr + 0x000 + + + VF3_TPHR_CAP_NEXTPTR + Vf3 Tphr Cap Nextptr + 0x000 + + + VF4_TPHR_CAP_NEXTPTR + Vf4 Tphr Cap Nextptr + 0x000 + + + VF5_TPHR_CAP_NEXTPTR + Vf5 Tphr Cap Nextptr + 0x000 + + + PF0_TPHR_CAP_ST_MODE_SEL + Pf0 Tphr Cap St Mode Sel + 0x0 + + + PF0_TPHR_CAP_ST_TABLE_LOC + Pf0 Tphr Cap St Table Loc + 0x0 + + + PF0_TPHR_CAP_ST_TABLE_SIZE + Pf0 Tphr Cap St Table Size + 0x000 + + + PF0_TPHR_CAP_VER + Pf0 Tphr Cap Ver + 0x1 + + + PF1_TPHR_CAP_ST_MODE_SEL + Pf1 Tphr Cap St Mode Sel + 0x0 + + + PF1_TPHR_CAP_ST_TABLE_LOC + Pf1 Tphr Cap St Table Loc + 0x0 + + + PF1_TPHR_CAP_ST_TABLE_SIZE + Pf1 Tphr Cap St Table Size + 0x000 + + + PF1_TPHR_CAP_VER + Pf1 Tphr Cap Ver + 0x1 + + + VF0_TPHR_CAP_ST_MODE_SEL + Vf0 Tphr Cap St Mode Sel + 0x0 + + + VF0_TPHR_CAP_ST_TABLE_LOC + Vf0 Tphr Cap St Table Loc + 0x0 + + + VF0_TPHR_CAP_ST_TABLE_SIZE + Vf0 Tphr Cap St Table Size + 0x000 + + + VF0_TPHR_CAP_VER + Vf0 Tphr Cap Ver + 0x1 + + + VF1_TPHR_CAP_ST_MODE_SEL + Vf1 Tphr Cap St Mode Sel + 0x0 + + + VF1_TPHR_CAP_ST_TABLE_LOC + Vf1 Tphr Cap St Table Loc + 0x0 + + + VF1_TPHR_CAP_ST_TABLE_SIZE + Vf1 Tphr Cap St Table Size + 0x000 + + + VF1_TPHR_CAP_VER + Vf1 Tphr Cap Ver + 0x1 + + + VF2_TPHR_CAP_ST_MODE_SEL + Vf2 Tphr Cap St Mode Sel + 0x0 + + + VF2_TPHR_CAP_ST_TABLE_LOC + Vf2 Tphr Cap St Table Loc + 0x0 + + + VF2_TPHR_CAP_ST_TABLE_SIZE + Vf2 Tphr Cap St Table Size + 0x000 + + + VF2_TPHR_CAP_VER + Vf2 Tphr Cap Ver + 0x1 + + + VF3_TPHR_CAP_ST_MODE_SEL + Vf3 Tphr Cap St Mode Sel + 0x0 + + + VF3_TPHR_CAP_ST_TABLE_LOC + Vf3 Tphr Cap St Table Loc + 0x0 + + + VF3_TPHR_CAP_ST_TABLE_SIZE + Vf3 Tphr Cap St Table Size + 0x000 + + + VF3_TPHR_CAP_VER + Vf3 Tphr Cap Ver + 0x1 + + + VF4_TPHR_CAP_ST_MODE_SEL + Vf4 Tphr Cap St Mode Sel + 0x0 + + + VF4_TPHR_CAP_ST_TABLE_LOC + Vf4 Tphr Cap St Table Loc + 0x0 + + + VF4_TPHR_CAP_ST_TABLE_SIZE + Vf4 Tphr Cap St Table Size + 0x000 + + + VF4_TPHR_CAP_VER + Vf4 Tphr Cap Ver + 0x1 + + + VF5_TPHR_CAP_ST_MODE_SEL + Vf5 Tphr Cap St Mode Sel + 0x0 + + + VF5_TPHR_CAP_ST_TABLE_LOC + Vf5 Tphr Cap St Table Loc + 0x0 + + + VF5_TPHR_CAP_ST_TABLE_SIZE + Vf5 Tphr Cap St Table Size + 0x000 + + + VF5_TPHR_CAP_VER + Vf5 Tphr Cap Ver + 0x1 + + + PF0_TPHR_CAP_DEV_SPECIFIC_MODE + Pf0 Tphr Cap Dev Specific Mode + TRUE + + + PF0_TPHR_CAP_INT_VEC_MODE + Pf0 Tphr Cap Int Vec Mode + FALSE + + + PF1_TPHR_CAP_DEV_SPECIFIC_MODE + Pf1 Tphr Cap Dev Specific Mode + TRUE + + + PF1_TPHR_CAP_INT_VEC_MODE + Pf1 Tphr Cap Int Vec Mode + FALSE + + + VF0_TPHR_CAP_DEV_SPECIFIC_MODE + Vf0 Tphr Cap Dev Specific Mode + TRUE + + + VF0_TPHR_CAP_INT_VEC_MODE + Vf0 Tphr Cap Int Vec Mode + FALSE + + + VF1_TPHR_CAP_DEV_SPECIFIC_MODE + Vf1 Tphr Cap Dev Specific Mode + TRUE + + + VF1_TPHR_CAP_INT_VEC_MODE + Vf1 Tphr Cap Int Vec Mode + FALSE + + + VF2_TPHR_CAP_DEV_SPECIFIC_MODE + Vf2 Tphr Cap Dev Specific Mode + TRUE + + + VF2_TPHR_CAP_INT_VEC_MODE + Vf2 Tphr Cap Int Vec Mode + FALSE + + + VF3_TPHR_CAP_DEV_SPECIFIC_MODE + Vf3 Tphr Cap Dev Specific Mode + TRUE + + + VF3_TPHR_CAP_INT_VEC_MODE + Vf3 Tphr Cap Int Vec Mode + FALSE + + + VF4_TPHR_CAP_DEV_SPECIFIC_MODE + Vf4 Tphr Cap Dev Specific Mode + TRUE + + + VF4_TPHR_CAP_INT_VEC_MODE + Vf4 Tphr Cap Int Vec Mode + FALSE + + + VF5_TPHR_CAP_DEV_SPECIFIC_MODE + Vf5 Tphr Cap Dev Specific Mode + TRUE + + + VF5_TPHR_CAP_INT_VEC_MODE + Vf5 Tphr Cap Int Vec Mode + FALSE + + + PF0_SECONDARY_PCIE_CAP_NEXTPTR + Secondary Pcie Extended Capability Nextptr + 0x000 + + + MCAP_CAP_NEXTPTR + MCAP Cap Nextptr + 0x000 + + + PF0_VC_CAP_NEXTPTR + Pf0 Vc Cap Nextptr + 0x000 + + + SPARE_WORD1 + Secondary Pcie Extended Capability Nextptr + 0x00000000 + + + PF1_AER_CAP_ECRC_CHECK_CAPABLE + Pf1 Aer Cap Ecrc Check Capable + FALSE + + + PF1_AER_CAP_ECRC_GEN_CAPABLE + Pf1 Aer Cap Ecrc Gen Capable + FALSE + + + PF1_AER_CAP_NEXTPTR + Pf1 Aer Cap Nextptr + 0x000 + + + PF1_ARI_CAP_NEXTPTR + Pf1 Ari Cap Nextptr + 0x000 + + + PF1_BAR0_APERTURE_SIZE + Pf1 Bar0 Aperture Size + 0x00 + + + PF1_BAR0_CONTROL + Pf1 Bar0 Control + 0x0 + + + PF1_BAR1_APERTURE_SIZE + Pf1 Bar1 Aperture Size + 0x00 + + + PF1_BAR1_CONTROL + Pf1 Bar1 Control + 0x0 + + + PF1_BAR2_APERTURE_SIZE + Pf1 Bar2 Aperture Size + 0x00 + + + PF1_BAR2_CONTROL + Pf1 Bar2 Control + 0x0 + + + PF1_BAR3_APERTURE_SIZE + Pf1 Bar3 Aperture Size + 0x00 + + + PF1_BAR3_CONTROL + Pf1 Bar3 Control + 0x0 + + + PF1_BAR4_APERTURE_SIZE + Pf1 Bar4 Aperture Size + 0x00 + + + PF1_BAR4_CONTROL + Pf1 Bar4 Control + 0x0 + + + PF1_BAR5_APERTURE_SIZE + Pf1 Bar5 Aperture Size + 0x00 + + + PF1_BAR5_CONTROL + Pf1 Bar5 Control + 0x0 + + + PF1_CAPABILITY_POINTER + Pf1 Capability Pointer + 0x80 + + + PF1_CLASS_CODE + Pf1 Class Code + 0x058000 + + + PF1_DEVICE_ID + Pf1 Device Id + 0x8011 + + + PF1_DEV_CAP_MAX_PAYLOAD_SIZE + Pf1 Dev Cap Max Payload Size + 0x2 + + + PF1_DPA_CAP_NEXTPTR + Pf1 Dpa Cap Nextptr + 0x000 + + + PF1_DSN_CAP_NEXTPTR + Pf1 Dsn Cap Nextptr + 0x000 + + + PF1_EXPANSION_ROM_APERTURE_SIZE + Pf1 Expansion Rom Aperture Size + 0x00 + + + PF1_EXPANSION_ROM_ENABLE + Pf1 Expansion Rom Enable + FALSE + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + 0x0 + + + PF1_MSIX_CAP_NEXTPTR + Pf1 Msix Cap Nextptr + 0x00 + + + PF1_MSIX_CAP_PBA_BIR + Pf1 Msix Cap Pba Bir + 0 + + + PF1_MSIX_CAP_PBA_OFFSET + Pf1 Msix Cap Pba Offset + 0x00000000 + + + PF1_MSIX_CAP_TABLE_BIR + Pf1 Msix Cap Table Bir + 0 + + + PF1_MSIX_CAP_TABLE_OFFSET + Pf1 Msix Cap Table Offset + 0x00000000 + + + PF1_MSIX_CAP_TABLE_SIZE + Pf1 Msix Cap Table Size + 0x000 + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 0 + + + PF1_MSI_CAP_NEXTPTR + Pf1 Msi Cap Nextptr + 0x00 + + + PF1_PB_CAP_NEXTPTR + Pf1 Pb Cap Nextptr + 0x000 + + + PF1_PM_CAP_NEXTPTR + Pf1 Pm Cap Nextptr + 0x00 + + + PF1_RBAR_CAP_ENABLE + Pf1 Rbar Cap Enable + FALSE + + + PF1_RBAR_CAP_NEXTPTR + Pf1 Rbar Cap Nextptr + 0x000 + + + PF1_REVISION_ID + Pf1 Revision Id + 0x00 + + + PF1_SRIOV_BAR0_APERTURE_SIZE + Pf1 Sriov Bar0 Aperture Size + 0x00 + + + PF1_SRIOV_BAR0_CONTROL + Pf1 Sriov Bar0 Control + 0x0 + + + PF1_SRIOV_BAR1_APERTURE_SIZE + Pf1 Sriov Bar1 Aperture Size + 0x00 + + + PF1_SRIOV_BAR1_CONTROL + Pf1 Sriov Bar1 Control + 0x0 + + + PF1_SRIOV_BAR2_APERTURE_SIZE + Pf1 Sriov Bar2 Aperture Size + 0x00 + + + PF1_SRIOV_BAR2_CONTROL + Pf1 Sriov Bar2 Control + 0x0 + + + PF1_SRIOV_BAR3_APERTURE_SIZE + Pf1 Sriov Bar3 Aperture Size + 0x00 + + + PF1_SRIOV_BAR3_CONTROL + Pf1 Sriov Bar3 Control + 0x0 + + + PF1_SRIOV_BAR4_APERTURE_SIZE + Pf1 Sriov Bar4 Aperture Size + 0x00 + + + PF1_SRIOV_BAR4_CONTROL + Pf1 Sriov Bar4 Control + 0x0 + + + PF1_SRIOV_BAR5_APERTURE_SIZE + Pf1 Sriov Bar5 Aperture Size + 0x00 + + + PF1_SRIOV_BAR5_CONTROL + Pf1 Sriov Bar5 Control + 0x0 + + + PF1_SRIOV_CAP_INITIAL_VF + Pf1 Sriov Cap Initial Vf + 0x0000 + + + PF1_SRIOV_CAP_NEXTPTR + Pf1 Sriov Cap Nextptr + 0x000 + + + PF1_SRIOV_CAP_TOTAL_VF + Pf1 Sriov Cap Total Vf + 0x0000 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 0x0 + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + 0x0000 + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0x0001 + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 0x00000553 + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0x0000 + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0x0007 + + + PF1_TPHR_CAP_ENABLE + Pf1 Tphr Cap Enable + FALSE + + + PF1_TPHR_CAP_NEXTPTR + Pf1 Tphr Cap Nextptr + 0x000 + + + PL_UPSTREAM_FACING + Pl Upstream Facing + TRUE + + + en_msi_per_vec_masking + en msi per vec masking + FALSE + + + SRIOV_CAP_ENABLE + Sriov Cap Enable + FALSE + + + TL_CREDITS_CD + Tl Credits Cd + 0x000 + + + TL_CREDITS_CH + Tl Credits Ch + 0x00 + + + TL_CREDITS_NPD + Tl Credits Npd + 0x028 + + + TL_CREDITS_NPH + Tl Credits Nph + 0x20 + + + TL_CREDITS_PD + Tl Credits Pd + 0x198 + + + TL_CREDITS_PH + Tl Credits Ph + 0x20 + + + TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE + Tl Extended Cfg Extend Interface Enable + FALSE + + + ACS_EXT_CAP_ENABLE + FALSE + + + ACS_CAP_NEXTPTR + 0x000 + + + TL_LEGACY_MODE_ENABLE + Tl Legacy Mode Enable + FALSE + + + TL_PF_ENABLE_REG + Tl Pf Enable Reg + 0x0 + + + VF0_CAPABILITY_POINTER + Vf0 Capability Pointer + 0x80 + + + VF0_MSIX_CAP_PBA_BIR + Vf0 Msix Cap Pba Bir + 0 + + + VF0_MSIX_CAP_PBA_OFFSET + Vf0 Msix Cap Pba Offset + 0x00000000 + + + VF0_MSIX_CAP_TABLE_BIR + Vf0 Msix Cap Table Bir + 0 + + + VF0_MSIX_CAP_TABLE_OFFSET + Vf0 Msix Cap Table Offset + 0x00000000 + + + VF0_MSIX_CAP_TABLE_SIZE + Vf0 Msix Cap Table Size + 0x000 + + + VF0_MSI_CAP_MULTIMSGCAP + Vf0 Msi Cap Multimsgcap + 0 + + + VF0_PM_CAP_NEXTPTR + Vf0 Pm Cap Nextptr + 0x00 + + + VF1_MSIX_CAP_PBA_BIR + Vf1 Msix Cap Pba Bir + 0 + + + VF1_MSIX_CAP_PBA_OFFSET + Vf1 Msix Cap Pba Offset + 0x00000000 + + + VF1_MSIX_CAP_TABLE_BIR + Vf1 Msix Cap Table Bir + 0 + + + VF1_MSIX_CAP_TABLE_OFFSET + Vf1 Msix Cap Table Offset + 0x00000000 + + + VF1_MSIX_CAP_TABLE_SIZE + Vf1 Msix Cap Table Size + 0x000 + + + VF1_MSI_CAP_MULTIMSGCAP + Vf1 Msi Cap Multimsgcap + 0 + + + VF1_PM_CAP_NEXTPTR + Vf1 Pm Cap Nextptr + 0x00 + + + VF2_MSIX_CAP_PBA_BIR + Vf2 Msix Cap Pba Bir + 0 + + + VF2_MSIX_CAP_PBA_OFFSET + Vf2 Msix Cap Pba Offset + 0x00000000 + + + VF2_MSIX_CAP_TABLE_BIR + Vf2 Msix Cap Table Bir + 0 + + + VF2_MSIX_CAP_TABLE_OFFSET + Vf2 Msix Cap Table Offset + 0x00000000 + + + VF2_MSIX_CAP_TABLE_SIZE + Vf2 Msix Cap Table Size + 0x000 + + + VF2_MSI_CAP_MULTIMSGCAP + Vf2 Msi Cap Multimsgcap + 0 + + + VF2_PM_CAP_NEXTPTR + Vf2 Pm Cap Nextptr + 0x00 + + + VF3_MSIX_CAP_PBA_BIR + Vf3 Msix Cap Pba Bir + 0 + + + VF3_MSIX_CAP_PBA_OFFSET + Vf3 Msix Cap Pba Offset + 0x00000000 + + + VF3_MSIX_CAP_TABLE_BIR + Vf3 Msix Cap Table Bir + 0 + + + VF3_MSIX_CAP_TABLE_OFFSET + Vf3 Msix Cap Table Offset + 0x00000000 + + + VF3_MSIX_CAP_TABLE_SIZE + Vf3 Msix Cap Table Size + 0x000 + + + VF3_MSI_CAP_MULTIMSGCAP + Vf3 Msi Cap Multimsgcap + 0 + + + VF3_PM_CAP_NEXTPTR + Vf3 Pm Cap Nextptr + 0x00 + + + VF4_MSIX_CAP_PBA_BIR + Vf4 Msix Cap Pba Bir + 0 + + + VF4_MSIX_CAP_PBA_OFFSET + Vf4 Msix Cap Pba Offset + 0x00000000 + + + VF4_MSIX_CAP_TABLE_BIR + Vf4 Msix Cap Table Bir + 0 + + + VF4_MSIX_CAP_TABLE_OFFSET + Vf4 Msix Cap Table Offset + 0x00000000 + + + VF4_MSIX_CAP_TABLE_SIZE + Vf4 Msix Cap Table Size + 0x000 + + + VF4_MSI_CAP_MULTIMSGCAP + Vf4 Msi Cap Multimsgcap + 0 + + + VF4_PM_CAP_NEXTPTR + Vf4 Pm Cap Nextptr + 0x00 + + + VF5_MSIX_CAP_PBA_BIR + Vf5 Msix Cap Pba Bir + 0 + + + VF5_MSIX_CAP_PBA_OFFSET + Vf5 Msix Cap Pba Offset + 0x00000000 + + + VF5_MSIX_CAP_TABLE_BIR + Vf5 Msix Cap Table Bir + 0 + + + VF5_MSIX_CAP_TABLE_OFFSET + Vf5 Msix Cap Table Offset + 0x00000000 + + + VF5_MSIX_CAP_TABLE_SIZE + Vf5 Msix Cap Table Size + 0x000 + + + VF5_MSI_CAP_MULTIMSGCAP + Vf5 Msi Cap Multimsgcap + 0 + + + VF5_PM_CAP_NEXTPTR + Vf5 Pm Cap Nextptr + 0x00 + + + COMPLETION_SPACE + Completion Space + 16KB + + + gen_x0y0_xdc + Generate X0Y0 XDC + 1 + + + gen_x0y1_xdc + Generate X0Y1 XDC + 0 + + + gen_x0y2_xdc + Generate X0Y2 XDC + 0 + + + gen_x0y3_xdc + Generate X0Y3 XDC + 0 + + + gen_x0y4_xdc + Generate X0Y4 XDC + 0 + + + gen_x0y5_xdc + Generate X0Y5 XDC + 0 + + + xlnx_ref_board + Xlnx Ref Board + 0 + + + pcie_blk_locn + Pcie Blk Locn + 0 + + + PIPE_SIM + FALSE + + + AXISTEN_IF_ENABLE_CLIENT_TAG + TRUE + + + PCIE_USE_MODE + PCIE USE MODE + 2.0 + + + PCIE_FAST_CONFIG + PCIE FAST CONFIG + NONE + + + EXT_STARTUP_PRIMITIVE + EXT STARTUP PRIMITIVE + FALSE + + + PL_INTERFACE + PL INTERFACE + FALSE + + + PCIE_CONFIGURATION + PCIE CONFIGURATION + FALSE + + + CFG_STATUS_IF + TRUE + + + TX_FC_IF + TRUE + + + CFG_EXT_IF + FALSE + + + CFG_FC_IF + TRUE + + + PER_FUNC_STATUS_IF + TRUE + + + CFG_MGMT_IF + TRUE + + + RCV_MSG_IF + TRUE + + + CFG_TX_MSG_IF + TRUE + + + CFG_CTL_IF + TRUE + + + MSI_EN + TRUE + + + MSIX_EN + FALSE + + + PCIE3_DRP + FALSE + + + DIS_GT_WIZARD + FALSE + + + TRANSCEIVER_CTRL_STATUS_PORTS + FALSE + + + SHARED_LOGIC + 1 + + + DEDICATE_PERST + TRUE + + + SYS_RESET_POLARITY + 0 + + + MCAP_ENABLEMENT + NONE + + + PHY_LP_TXPRESET + Phy Lp Txpreset + 4 + + + EXT_CH_GT_DRP + FALSE + + + EN_GT_SELECTION + FALSE + + + SELECT_QUAD + GTH_Quad_225 + + + silicon_revision + Silicon Revision + Production + + + DEV_PORT_TYPE + 0 + + + RX_DETECT + Receiver Detect + 0 + + + ENABLE_IBERT + FALSE + + + DBG_DESCRAMBLE_EN + FALSE + + + ENABLE_JTAG_DBG + FALSE + + + AXISTEN_IF_CC_PARITY_CHK + FALSE + + + AXISTEN_IF_RQ_PARITY_CHK + FALSE + + + ENABLE_AUTO_RXEQ + FALSE + + + GTWIZ_IN_CORE + 1 + + + INS_LOSS_PROFILE + Add-in_Card + + + PM_ENABLE_L23_ENTRY + FALSE + + + BMD_PIO_MODE + FALSE + + + MULT_PF_DES + TRUE + + + ENABLE_GT_V1_5 + FALSE + + + EXT_XVC_VSEC_ENABLE + Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design + FALSE + + + + + + choice_list_24b724fb + Basic + Advanced + + + choice_list_3c2e0592 + QPLL1 + + + choice_list_52d29139 + Bytes + Kilobytes + Megabytes + Gigabytes + + + choice_list_55451da8 + X1 + X2 + X4 + X8 + + + choice_list_6b979ebc + 250 + + + choice_list_6f5507b7 + None + + + choice_list_7a7dde49 + true + false + + + choice_list_86c5d341 + 500 + + + choice_list_8b5e4915 + 4 + 5 + + + choice_list_bdd7203f + True + False + + + choice_list_be0f0e98 + X0Y0 + X0Y1 + X0Y2 + X0Y3 + + + choice_list_c15e8c67 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_c3d223d9 + Memory + + + choice_list_c63ab5b1 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + choice_list_d123c74c + Bytes + Kilobytes + Megabytes + + + choice_list_d85ad257 + 0 + + + choice_list_dd772e63 + Extreme + + + choice_list_ec64e624 + N/A + + + choice_list_f1174048 + NONE + INTA + INTB + INTC + INTD + + + choice_pairs_0b493de9 + No_ASPM + L1_Supported + + + choice_pairs_0d200523 + 00_Not_Supported + 01_MSI_only + + + choice_pairs_11ed4471 + 1_vector + 2_vectors + 4_vectors + 8_vectors + 16_vectors + 32_vectors + + + choice_pairs_12c31cff + Chip-to-Chip + Add-in_Card + Backplane + + + choice_pairs_3c87fcdb + 1 + 0 + + + choice_pairs_3f2631bf + 128_bytes + 256_bytes + 512_bytes + 1024_bytes + + + choice_pairs_3fe73c5d + BAR_0 + 0 + BAR_1 + 1 + BAR_2 + 2 + BAR_3 + 3 + BAR_4 + 4 + BAR_5 + + + choice_pairs_49d248fb + BAR_0 + + + choice_pairs_4b246358 + Wireless_controller + Satellite_communication_controllers + Data_acquisition_and_signal_processing_controllers + Intelligent_I/O_controllers + Docking_stations + Device_was_built_before_Class_Code_definitions_were_finalized + Memory_controller + Simple_communication_controllers + Serial_bus_controllers + Encryption/Decryption_controllers + Display_controller + Multimedia_device + Input_devices + Mass_storage_controller + Processors + Device_does_not_fit_in_any_defined_classes + Bridge_device + Network_controller + Base_system_peripherals + + + choice_pairs_503b93ee + None + DWORD_Aligned + Address_Aligned + + + choice_pairs_53749dec + 1 + 0 + + + choice_pairs_649e04ee + GTH_Quad_225 + GTH_Quad_224 + + + choice_pairs_7156aca5 + Default + Falling_Edge + + + choice_pairs_7ddd9aec + ACTIVE_LOW + ACTIVE_HIGH + + + choice_pairs_8b05c234 + DWORD_Aligned + Address_Aligned + + + choice_pairs_96d05a8d + 100_MHz + 125_MHz + 250_MHz + + + choice_pairs_c1620769 + 256_bit + + + choice_pairs_c98117c0 + RAM + Other_memory_controller + Flash + + + choice_pairs_d3142f18 + None + Tandem + Tandem_with_Field_Updates + PR_over_PCIe + + + choice_pairs_dc66c043 + PCI_Express_Endpoint_device + Legacy_PCI_Express_Endpoint_device + Root_Port_of_PCI_Express_Root_Complex + + + choice_pairs_dd20f238 + None + Tandem_PROM + Tandem_Pcie + + + choice_pairs_e13c2c7f + Generic_XT_compatible_serial_controller + 16450_compatible_serial_controller + Parallel_port + IEEE_1284_controller + Multiport_serial_controller + 16650_compatible_serial_controller + IEEE_1284_target_device + Hayes_compatible_modem_with_16550_compatible_interface + ECP_1.X_compliant_parallel_port + 16850_compatible_serial_controller + Hayes_compatible_modem_with_16750_compatible_interface + Smart_Card + Bi_directional_parallel_port + Other_communications_device + GPIB(IEEE_488.1/2)_controller + 16550_compatible_serial_controller + Hayes_compatible_modem_with_16450_compatible_interface + 16750_compatible_serial_controller + Hayes_compatible_modem_with_16650_compatible_interface + Generic_modem + 16950_compatible_serial_controller + + + choice_pairs_f8a795d6 + 2.5_GT/s + 5.0_GT/s + 8.0_GT/s + + + + + xilinx_elaboratesubcores_view_fileset + + ip_0/xdma_pcie3_ip_gt.xci + xci + + + ip_0/xdma_pcie3_ip_gt.xml + xml + + + + The Xilinx UltraScale Gen3 Integrated Block for PCI Express (1-lane, 2-lane, 4-lane, and 8-lane) in conjunction with flexible UltraScale architectural features such as integrated GTs (Gigabit Transceivers) and BRAM (Block RAMs) are used to implement a PCI Express Base Specification v3.1 compliant PCI Express devices. + + + device_port_type + Device Port Type + PCI_Express_Endpoint_device + + + xlnx_ref_board + Xlnx Ref Board + None + + + + true + + + + + + PL_LINK_CAP_MAX_LINK_SPEED + Pl Link Cap Max Link Speed + 8.0_GT/s + + + PL_LINK_CAP_MAX_LINK_WIDTH + Pl Link Cap Max Link Width + The Xilinx Ultrascale Series Gen3 Integrated Block for PCI Expressification v3.0 compliant PCI Express Endpoint. + X8 + + + REF_CLK_FREQ + Ref Clk Freq + 100_MHz + + + AXISTEN_IF_RC_STRADDLE + Axisten If Rc Straddle + true + + + axisten_if_enable_client_tag + Enable Client Tag + true + + + PF0_AER_CAP_ECRC_CHECK_CAPABLE + Pf0 Aer Cap Ecrc Check Capable + false + + + PF0_AER_CAP_ECRC_GEN_CAPABLE + Pf0 Aer Cap Ecrc Gen Capable + false + + + PF0_DEVICE_ID + Pf0 Device Id + 8038 + + + PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 128b Cas Atomic Completer Support + false + + + PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 32b Atomic Completer Support + false + + + PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 64b Atomic Completer Support + false + + + PF0_DEV_CAP2_OBFF_SUPPORT + Pf0 Dev Cap2 Obff Support + 00_Not_Supported + + + PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT + Pf0 Dev Cap2 Tph Completer Support + false + + + PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE + Pf0 Dev Cap Function Level Reset Capable + false + + + PF0_INTERRUPT_PIN + Pf0 Interrupt Pin + INTA + + + PF0_LINK_STATUS_SLOT_CLOCK_CONFIG + Pf0 Link Status Slot Clock Config + true + + + PF0_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + BAR_0 + + + PF0_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 00000000 + + + PF0_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + BAR_0 + + + PF0_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 00000000 + + + PF0_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 000 + + + PF0_MSI_CAP_MULTIMSGCAP + Pf0 Msi Cap Multimsgcap + 1_vector + + + PF0_PM_CAP_PMESUPPORT_D1 + Pf0 Pm Cap Pmesupport D1 + false + + + PF0_PM_CAP_PMESUPPORT_D3HOT + Pf0 Pm Cap Pmesupport D3hot + false + + + PF0_PM_CAP_SUPP_D1_STATE + Pf0 Pm Cap Supp D1 State + false + + + PF0_REVISION_ID + Pf0 Revision Id + 00 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + N/A + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 00000553 + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0000 + + + PF0_SUBSYSTEM_ID + Pf0 Subsystem Id + 0007 + + + PF1_AER_CAP_ECRC_CHECK_CAPABLE + Pf1 Aer Cap Ecrc Check Capable + false + + + PF1_AER_CAP_ECRC_GEN_CAPABLE + Pf1 Aer Cap Ecrc Gen Capable + false + + + PF1_DEVICE_ID + Pf1 Device Id + 8011 + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + NONE + + + PF1_MSIX_CAP_PBA_BIR + Pf1 Msix Cap Pba Bir + BAR_0 + + + PF1_MSIX_CAP_TABLE_BIR + Pf1 Msix Cap Table Bir + BAR_0 + + + PF1_MSIX_CAP_TABLE_SIZE + Pf1 Msix Cap Table Size + 000 + + + PF1_MSIX_CAP_TABLE_OFFSET + Pf1 Msix Cap Table Offset + 00000000 + + + PF1_MSIX_CAP_PBA_OFFSET + Pf1 Msix Cap Pba Offset + 00000000 + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 1_vector + + + PF1_REVISION_ID + Pf1 Revision Id + 00 + + + PF1_SRIOV_CAP_INITIAL_VF + Pf1 Sriov Cap Initial Vf + 0 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 0 + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + N/A + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0001 + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 00000553 + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0000 + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0007 + + + tl_pf0_enable_reg + Tl Pf0 Enable Reg + true + + + TL_PF_ENABLE_REG + Tl Pf Enable Reg + false + + + SRIOV_CAP_ENABLE + Sriov Cap Enable + false + + + VF0_MSIX_CAP_PBA_BIR + Vf0 Msix Cap Pba Bir + BAR_0 + + + VF0_MSIX_CAP_PBA_OFFSET + Vf0 Msix Cap Pba Offset + 00000000 + + + VF0_MSIX_CAP_TABLE_BIR + Vf0 Msix Cap Table Bir + BAR_0 + + + VF0_MSIX_CAP_TABLE_OFFSET + Vf0 Msix Cap Table Offset + 00000000 + + + VF0_MSIX_CAP_TABLE_SIZE + Vf0 Msix Cap Table Size + 000 + + + VF0_MSI_CAP_MULTIMSGCAP + Vf0 Msi Cap Multimsgcap + 1_vector + + + VF1_MSIX_CAP_PBA_BIR + Vf1 Msix Cap Pba Bir + BAR_0 + + + VF1_MSIX_CAP_PBA_OFFSET + Vf1 Msix Cap Pba Offset + 00000000 + + + VF1_MSIX_CAP_TABLE_BIR + Vf1 Msix Cap Table Bir + BAR_0 + + + VF1_MSIX_CAP_TABLE_OFFSET + Vf1 Msix Cap Table Offset + 00000000 + + + VF1_MSIX_CAP_TABLE_SIZE + Vf1 Msix Cap Table Size + 000 + + + VF1_MSI_CAP_MULTIMSGCAP + Vf1 Msi Cap Multimsgcap + 1_vector + + + VF2_MSIX_CAP_PBA_BIR + Vf2 Msix Cap Pba Bir + BAR_0 + + + VF2_MSIX_CAP_PBA_OFFSET + Vf2 Msix Cap Pba Offset + 00000000 + + + VF2_MSIX_CAP_TABLE_BIR + Vf2 Msix Cap Table Bir + BAR_0 + + + VF2_MSIX_CAP_TABLE_OFFSET + Vf2 Msix Cap Table Offset + 00000000 + + + VF2_MSIX_CAP_TABLE_SIZE + Vf2 Msix Cap Table Size + 000 + + + VF2_MSI_CAP_MULTIMSGCAP + Vf2 Msi Cap Multimsgcap + 1_vector + + + VF3_MSIX_CAP_PBA_BIR + Vf3 Msix Cap Pba Bir + BAR_0 + + + VF3_MSIX_CAP_PBA_OFFSET + Vf3 Msix Cap Pba Offset + 00000000 + + + VF3_MSIX_CAP_TABLE_BIR + Vf3 Msix Cap Table Bir + BAR_0 + + + VF3_MSIX_CAP_TABLE_OFFSET + Vf3 Msix Cap Table Offset + 00000000 + + + VF3_MSIX_CAP_TABLE_SIZE + Vf3 Msix Cap Table Size + 000 + + + VF3_MSI_CAP_MULTIMSGCAP + Vf3 Msi Cap Multimsgcap + 1_vector + + + VF4_MSIX_CAP_PBA_BIR + Vf4 Msix Cap Pba Bir + BAR_0 + + + VF4_MSIX_CAP_PBA_OFFSET + Vf4 Msix Cap Pba Offset + 00000000 + + + VF4_MSIX_CAP_TABLE_BIR + Vf4 Msix Cap Table Bir + BAR_0 + + + VF4_MSIX_CAP_TABLE_OFFSET + Vf4 Msix Cap Table Offset + 00000000 + + + VF4_MSIX_CAP_TABLE_SIZE + Vf4 Msix Cap Table Size + 000 + + + VF4_MSI_CAP_MULTIMSGCAP + Vf4 Msi Cap Multimsgcap + 1_vector + + + VF5_MSIX_CAP_PBA_BIR + Vf5 Msix Cap Pba Bir + BAR_0 + + + VF5_MSIX_CAP_PBA_OFFSET + Vf5 Msix Cap Pba Offset + 00000000 + + + VF5_MSIX_CAP_TABLE_BIR + Vf5 Msix Cap Table Bir + BAR_0 + + + VF5_MSIX_CAP_TABLE_OFFSET + Vf5 Msix Cap Table Offset + 00000000 + + + VF5_MSIX_CAP_TABLE_SIZE + Vf5 Msix Cap Table Size + 000 + + + VF5_MSI_CAP_MULTIMSGCAP + Vf5 Msi Cap Multimsgcap + 1_vector + + + Component_Name + xdma_pcie3_ip + + + PF0_Use_Class_Code_Lookup_Assistant + false + + + PF1_Use_Class_Code_Lookup_Assistant + false + + + PF0_PM_CAP_PMESUPPORT_D0 + Pf0 Pm Cap Pmesupport D0 + false + + + PF0_SUBSYSTEM_VENDOR_ID + Pf0 Subsystem Vendor Id + 10EE + + + pf1_sriov_bar5_scale + Pf1 Sriov Bar5 Scale + Kilobytes + + + pf1_sriov_bar4_type + Pf1 Sriov Bar4 Type + N/A + + + pf0_vc_cap_enabled + Pf0 Vc Cap Enabled + false + + + pf1_sriov_bar5_type + Pf1 Sriov Bar5 Type + N/A + + + pf1_sriov_bar0_enabled + Pf1 Sriov Bar0 Enabled + true + + + pf0_sriov_bar5_enabled + Pf0 Sriov Bar5 Enabled + false + + + pcie_blk_locn + Pcie Blk Locn + X0Y0 + + + pf0_sriov_bar1_64bit + Pf0 Sriov Bar1 64bit + false + + + pf1_sriov_bar3_prefetchable + Pf1 Sriov Bar3 Prefetchable + false + + + pf0_pb_enabled + Pf0 Pb Enabled + false + + + pf1_sriov_bar0_64bit + Pf1 Sriov Bar0 64bit + false + + + pf1_bar3_type + Pf1 Bar3 Type + N/A + + + pf1_bar2_enabled + Pf1 Bar2 Enabled + false + + + pf1_bar2_type + Pf1 Bar2 Type + N/A + + + pf1_bar2_64bit + Pf1 Bar2 64bit + false + + + pf1_bar2_prefetchable + Pf1 Bar2 Prefetchable + false + + + pf1_bar2_scale + Pf1 Bar2 Scale + Kilobytes + + + pf1_bar2_size + Pf1 Bar2 Size + 2 + + + pf0_sriov_bar1_scale + Pf0 Sriov Bar1 Scale + Kilobytes + + + pf1_bar4_type + Pf1 Bar4 Type + N/A + + + pf0_base_class_menu + Pf0 Base Class Menu + Simple_communication_controllers + + + pf0_class_code_base + Pf0 Class Code Base + 07 + + + pf0_sub_class_interface_menu + Pf0 Sub Class Interface Menu + 16450_compatible_serial_controller + + + pf0_class_code_sub + Pf0 Class Code Sub + 00 + + + pf0_class_code_interface + Pf0 Class Code Interface + 01 + + + PF0_CLASS_CODE + Pf0 Class Code + 070001 + + + pf1_base_class_menu + Pf1 Base Class Menu + Memory_controller + + + pf1_class_code_base + Pf1 Class Code Base + 05 + + + pf1_sub_class_interface_menu + Pf1 Sub Class Interface Menu + Other_memory_controller + + + pf1_class_code_sub + Pf1 Class Code Sub + 80 + + + pf1_class_code_interface + Pf1 Class Code Interface + 00 + + + PF1_CLASS_CODE + Pf1 Class Code + 058000 + + + pf1_sriov_bar0_scale + Pf1 Sriov Bar0 Scale + Kilobytes + + + pf1_expansion_rom_enabled + Pf1 Expansion Rom Enabled + false + + + pf0_sriov_bar0_enabled + Pf0 Sriov Bar0 Enabled + true + + + pf1_sriov_bar0_prefetchable + Pf1 Sriov Bar0 Prefetchable + false + + + pf1_bar5_type + Pf1 Bar5 Type + N/A + + + pf0_sriov_bar5_prefetchable + Pf0 Sriov Bar5 Prefetchable + false + + + pf1_sriov_bar1_enabled + Pf1 Sriov Bar1 Enabled + false + + + pf0_sriov_bar2_64bit + Pf0 Sriov Bar2 64bit + false + + + pf1_msix_enabled + Pf1 Msix Enabled + false + + + pf1_bar5_prefetchable + Pf1 Bar5 Prefetchable + false + + + pf0_rbar_enabled + Pf0 Rbar Enabled + false + + + pf1_pb_enabled + Pf1 Pb Enabled + false + + + pf1_sriov_bar1_64bit + Pf1 Sriov Bar1 64bit + false + + + pf1_bar3_64bit + Pf1 Bar3 64bit + false + + + pf0_sriov_bar2_prefetchable + Pf0 Sriov Bar2 Prefetchable + false + + + pf1_bar3_enabled + Pf1 Bar3 Enabled + false + + + pf0_sriov_bar2_scale + Pf0 Sriov Bar2 Scale + Kilobytes + + + pf1_sriov_bar1_scale + Pf1 Sriov Bar1 Scale + Kilobytes + + + pf1_bar3_scale + Pf1 Bar3 Scale + Kilobytes + + + pf0_sriov_bar1_enabled + Pf0 Sriov Bar1 Enabled + false + + + alignment_mode + Alignment Mode + DWORD_Aligned + + + pf1_sriov_bar4_prefetchable + Pf1 Sriov Bar4 Prefetchable + false + + + pf1_sriov_bar2_enabled + Pf1 Sriov Bar2 Enabled + false + + + pf0_sriov_bar3_64bit + Pf0 Sriov Bar3 64bit + false + + + pf0_sriov_bar0_size + Pf0 Sriov Bar0 Size + 2 + + + pf1_sriov_bar2_64bit + Pf1 Sriov Bar2 64bit + false + + + pf1_bar4_64bit + Pf1 Bar4 64bit + false + + + pf0_sriov_bar1_size + Pf0 Sriov Bar1 Size + 2 + + + pf0_bar0_enabled + Pf0 Bar0 Enabled + true + + + pf0_bar0_type + Pf0 Bar0 Type + Memory + + + pf0_bar0_64bit + Pf0 Bar0 64bit + false + + + pf0_bar0_prefetchable + Pf0 Bar0 Prefetchable + false + + + pf0_bar0_scale + Pf0 Bar0 Scale + Kilobytes + + + pf0_bar0_size + Pf0 Bar0 Size + 64 + + + pf0_bar1_enabled + Pf0 Bar1 Enabled + false + + + pf0_bar1_type + Pf0 Bar1 Type + N/A + + + pf0_bar1_64bit + Pf0 Bar1 64bit + false + + + pf0_bar1_prefetchable + Pf0 Bar1 Prefetchable + false + + + pf0_bar1_scale + Pf0 Bar1 Scale + Kilobytes + + + pf0_bar1_size + Pf0 Bar1 Size + 2 + + + pf0_bar2_enabled + Pf0 Bar2 Enabled + false + + + pf0_bar2_type + Pf0 Bar2 Type + N/A + + + pf0_bar2_64bit + Pf0 Bar2 64bit + false + + + pf0_bar2_prefetchable + Pf0 Bar2 Prefetchable + false + + + pf0_bar2_scale + Pf0 Bar2 Scale + Kilobytes + + + pf0_bar2_size + Pf0 Bar2 Size + 2 + + + pf0_bar3_enabled + Pf0 Bar3 Enabled + false + + + pf0_bar3_type + Pf0 Bar3 Type + N/A + + + pf0_bar3_64bit + Pf0 Bar3 64bit + false + + + pf0_bar3_prefetchable + Pf0 Bar3 Prefetchable + false + + + pf0_bar3_scale + Pf0 Bar3 Scale + Kilobytes + + + pf0_bar3_size + Pf0 Bar3 Size + 2 + + + pf0_bar4_enabled + Pf0 Bar4 Enabled + false + + + pf0_bar4_type + Pf0 Bar4 Type + N/A + + + pf0_bar4_64bit + Pf0 Bar4 64bit + false + + + pf0_bar4_prefetchable + Pf0 Bar4 Prefetchable + false + + + pf0_bar4_scale + Pf0 Bar4 Scale + Kilobytes + + + pf0_bar4_size + Pf0 Bar4 Size + 2 + + + pf0_bar5_enabled + Pf0 Bar5 Enabled + false + + + pf0_bar5_type + Pf0 Bar5 Type + N/A + + + pf0_bar5_prefetchable + Pf0 Bar5 Prefetchable + false + + + pf0_bar5_scale + Pf0 Bar5 Scale + Kilobytes + + + pf0_bar5_size + Pf0 Bar5 Size + 2 + + + pf0_sriov_bar3_scale + Pf0 Sriov Bar3 Scale + Kilobytes + + + pf1_bar4_enabled + Pf1 Bar4 Enabled + false + + + pf1_sriov_bar1_prefetchable + Pf1 Sriov Bar1 Prefetchable + false + + + pf0_sriov_bar2_size + Pf0 Sriov Bar2 Size + 2 + + + pf1_sriov_bar2_scale + Pf1 Sriov Bar2 Scale + Kilobytes + + + pf1_bar4_scale + Pf1 Bar4 Scale + Kilobytes + + + pf0_sriov_bar3_size + Pf0 Sriov Bar3 Size + 2 + + + pf0_sriov_bar2_enabled + Pf0 Sriov Bar2 Enabled + false + + + pf0_dev_cap_max_payload + Pf0 Dev Cap Max Payload + 512_bytes + + + gen_x0y0 + Gen X0y0 + true + + + gen_x0y1 + Gen X0y1 + false + + + gen_x0y2 + Gen X0y2 + false + + + gen_x0y3 + Gen X0y3 + false + + + gen_x0y4 + Gen X0y4 + false + + + gen_x0y5 + Gen X0y5 + false + + + pf0_sriov_bar4_size + Pf0 Sriov Bar4 Size + 2 + + + pf1_expansion_rom_scale + Pf1 Expansion Rom Scale + Kilobytes + + + pf1_expansion_rom_size + Pf1 Expansion Rom Size + 2 + + + pf1_rbar_enabled + Pf1 Rbar Enabled + false + + + pf1_tphr_enable + Pf1 Tphr Enable + false + + + pf1_sriov_bar3_enabled + Pf1 Sriov Bar3 Enabled + false + + + pf0_sriov_bar4_64bit + Pf0 Sriov Bar4 64bit + false + + + pf0_sriov_bar5_size + Pf0 Sriov Bar5 Size + 2 + + + pf0_sriov_bar3_prefetchable + Pf0 Sriov Bar3 Prefetchable + false + + + pf1_sriov_bar3_64bit + Pf1 Sriov Bar3 64bit + false + + + pf0_expansion_rom_enabled + Pf0 Expansion Rom Enabled + false + + + pf0_sriov_bar4_scale + Pf0 Sriov Bar4 Scale + Kilobytes + + + pf0_sriov_bar0_type + Pf0 Sriov Bar0 Type + Memory + + + pf1_bar5_enabled + Pf1 Bar5 Enabled + false + + + pf1_bar3_prefetchable + Pf1 Bar3 Prefetchable + false + + + pf1_sriov_bar0_size + Pf1 Sriov Bar0 Size + 2 + + + pf1_sriov_bar3_scale + Pf1 Sriov Bar3 Scale + Kilobytes + + + pf1_bar5_scale + Pf1 Bar5 Scale + Kilobytes + + + extended_tag_field + Extended Tag Field + true + + + pf0_sriov_bar1_type + Pf0 Sriov Bar1 Type + N/A + + + pf0_sriov_bar0_prefetchable + Pf0 Sriov Bar0 Prefetchable + false + + + pf0_expansion_rom_scale + Pf0 Expansion Rom Scale + Kilobytes + + + pf0_expansion_rom_size + Pf0 Expansion Rom Size + 2 + + + pf1_sriov_bar1_size + Pf1 Sriov Bar1 Size + 2 + + + pf1_ari_enabled + Pf1 Ari Enabled + false + + + pf0_sriov_bar3_enabled + Pf0 Sriov Bar3 Enabled + false + + + pf1_sriov_bar5_prefetchable + Pf1 Sriov Bar5 Prefetchable + false + + + pf0_sriov_bar2_type + Pf0 Sriov Bar2 Type + N/A + + + vendor_id + Vendor Id + 10EE + + + pf0_tphr_enable + Pf0 Tphr Enable + false + + + pf1_sriov_bar2_size + Pf1 Sriov Bar2 Size + 2 + + + pf0_sriov_bar3_type + Pf0 Sriov Bar3 Type + N/A + + + pf1_sriov_bar3_size + Pf1 Sriov Bar3 Size + 2 + + + pf1_bar0_enabled + Pf1 Bar0 Enabled + false + + + pf1_bar0_type + Pf1 Bar0 Type + N/A + + + pf1_bar0_64bit + Pf1 Bar0 64bit + false + + + pf1_bar0_prefetchable + Pf1 Bar0 Prefetchable + false + + + pf1_bar0_scale + Pf1 Bar0 Scale + Kilobytes + + + pf1_bar0_size + Pf1 Bar0 Size + 2 + + + pf1_bar1_enabled + Pf1 Bar1 Enabled + false + + + pf1_bar1_type + Pf1 Bar1 Type + N/A + + + pf1_bar1_64bit + Pf1 Bar1 64bit + false + + + pf1_bar1_prefetchable + Pf1 Bar1 Prefetchable + false + + + pf1_bar1_scale + Pf1 Bar1 Scale + Kilobytes + + + pf1_bar1_size + Pf1 Bar1 Size + 2 + + + pf1_sriov_bar4_enabled + Pf1 Sriov Bar4 Enabled + false + + + pf1_aer_enabled + Pf1 Aer Enabled + true + + + pf1_dsn_enabled + Pf1 Dsn Enabled + false + + + pf0_sriov_bar4_type + Pf0 Sriov Bar4 Type + N/A + + + pf1_sriov_bar4_64bit + Pf1 Sriov Bar4 64bit + false + + + pf1_sriov_bar2_prefetchable + Pf1 Sriov Bar2 Prefetchable + false + + + pf0_sriov_cap_ver + Pf0 Sriov Cap Ver + 0 + + + pf1_sriov_bar4_size + Pf1 Sriov Bar4 Size + 2 + + + pf1_msi_enabled + Pf1 Msi Enabled + true + + + pf0_sriov_bar5_scale + Pf0 Sriov Bar5 Scale + Kilobytes + + + pf1_dpa_enabled + Pf1 Dpa Enabled + false + + + pf0_sriov_bar5_type + Pf0 Sriov Bar5 Type + N/A + + + ext_pcie_cfg_space_enabled + Ext Pcie Cfg Space Enabled + false + + + pf1_sriov_bar4_scale + Pf1 Sriov Bar4 Scale + Kilobytes + + + pf1_sriov_bar5_size + Pf1 Sriov Bar5 Size + 2 + + + pf0_ari_enabled + Pf0 Ari Enabled + false + + + perf_level + Perf Level + Extreme + + + axisten_if_width + Axisten If Width + 256_bit + + + pf0_sriov_bar4_enabled + Pf0 Sriov Bar4 Enabled + false + + + pf1_sriov_bar0_type + Pf1 Sriov Bar0 Type + Memory + + + pf1_bar3_size + Pf1 Bar3 Size + 2 + + + pf0_sriov_bar4_prefetchable + Pf0 Sriov Bar4 Prefetchable + false + + + pf0_aer_enabled + Pf0 Aer Enabled + true + + + pf0_dsn_enabled + Pf0 Dsn Enabled + false + + + pf1_sriov_bar1_type + Pf1 Sriov Bar1 Type + N/A + + + pf0_sriov_bar0_64bit + Pf0 Sriov Bar0 64bit + false + + + pf1_bar4_size + Pf1 Bar4 Size + 2 + + + pf0_msi_enabled + Pf0 Msi Enabled + true + + + pf1_sriov_bar5_enabled + Pf1 Sriov Bar5 Enabled + false + + + pf0_dpa_enabled + Pf0 Dpa Enabled + false + + + pf1_sriov_bar2_type + Pf1 Sriov Bar2 Type + N/A + + + pf0_msix_enabled + Pf0 Msix Enabled + false + + + pf1_bar5_size + Pf1 Bar5 Size + 2 + + + pf1_bar4_prefetchable + Pf1 Bar4 Prefetchable + false + + + pf0_sriov_bar0_scale + Pf0 Sriov Bar0 Scale + Kilobytes + + + pf1_dev_cap_max_payload + Pf1 Dev Cap Max Payload + 512_bytes + + + pf0_sriov_bar1_prefetchable + Pf0 Sriov Bar1 Prefetchable + false + + + pf1_sriov_bar3_type + Pf1 Sriov Bar3 Type + N/A + + + pf0_ltr_enabled + Pf0 Ltr Enabled + false + + + mode_selection + Mode + Advanced + + + pipe_sim + false + + + en_ext_clk + false + + + en_msi_per_vec_masking + false + + + tandem_mode + Tandem Mode + None + + + coreclk_freq + CORE CLOCK FREQ + 500 + + + plltype + PLL TYPE + QPLL1 + + + axisten_freq + AXISTEN IF FREQ + 250 + + + aspm_support + ASPM Support + No_ASPM + + + SRIOV_CAP_ENABLE_EXT + SRIOV Cap Enable + false + + + axisten_if_enable_msg_route + 20000 + + + axisten_if_enable_rx_msg_intfc + false + + + cfg_fc_if + true + + + cfg_ext_if + false + + + acs_ext_cap_enable + ACS Ext Capability + false + + + cfg_status_if + true + + + per_func_status_if + true + + + cfg_mgmt_if + true + + + rcv_msg_if + true + + + cfg_tx_msg_if + true + + + cfg_ctl_if + true + + + tx_fc_if + true + + + en_pcie_drp + false + + + en_pl_ifc + false + + + en_pcie_conf + false + + + dis_gt_wizard + false + + + RX_PPM_OFFSET + Specify the PPM offset between received data and transmitted data + 0 + + + RX_SSC_PPM + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 15 + + + en_transceiver_status_ports + false + + + Shared_Logic + 1 + + + dedicate_perst + true + + + sys_reset_polarity + ACTIVE_LOW + + + mcap_enablement + MCAP Enable + None + + + PHY_LP_TXPRESET + Phy Lp Txpreset + 4 + + + RX_DETECT + Receiver Detect + Default + + + en_ext_ch_gt_drp + false + + + ext_startup_primitive + false + + + en_gt_selection + false + + + select_quad + GTH_Quad_225 + + + performance + false + + + cc_cq_alignment + CC CQ Alignment Mode + Address_Aligned + + + rc_rq_alignment + CC CQ Alignment Mode + DWORD_Aligned + + + ins_loss_profile + Add-in_Card + + + enable_ibert + false + + + en_dbg_descramble + false + + + enable_jtag_dbg + false + + + en_parity + false + + + enable_auto_rxeq + False + + + special_gui + false + + + gtwiz_in_core + 1 + + + en_l23_entry + false + + + bmd_pio_mode + false + + + mult_pf_des + true + + + enable_gt_v1_5 + false + + + ext_xvc_vsec_enable + Enable to add the PCIe XVC-VSEC to the Examlpe Design + false + + + + false + + + + + + axisten_if_enable_msg_route_override + true + + + + + UltraScale FPGA Gen3 Integrated Block for PCI Express + + XPM_CDC + + 3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + -- cgit v1.2.3