From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../VU095/VU095.srcs/sources_1/ip/xdma/xdma.xml | 56283 +++++++++++++++++++ 1 file changed, 56283 insertions(+) create mode 100644 projects/VU095/VU095.srcs/sources_1/ip/xdma/xdma.xml (limited to 'projects/VU095/VU095.srcs/sources_1/ip/xdma/xdma.xml') diff --git a/projects/VU095/VU095.srcs/sources_1/ip/xdma/xdma.xml b/projects/VU095/VU095.srcs/sources_1/ip/xdma/xdma.xml new file mode 100644 index 0000000..5dc4222 --- /dev/null +++ b/projects/VU095/VU095.srcs/sources_1/ip/xdma/xdma.xml @@ -0,0 +1,56283 @@ + + + xilinx.com + customized_ip + xdma + 1.0 + + + CLK.SYS_CLK + + + + + + + CLK + + + sys_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + + true + + + + + + CLK.sys_clk_gt + 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+ none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 0 + + + none + + + + + HAS_BRESP + 0 + + + none + + + + + HAS_RRESP + 0 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + S_AXIS_C2H_0 + S_AXIS_C2H_0 + + + + + + + TDATA + + + s_axis_c2h_tdata_0 + + + + + TKEEP + + + s_axis_c2h_tkeep_0 + + + + + TLAST + + + s_axis_c2h_tlast_0 + + + + + TREADY + + + s_axis_c2h_tready_0 + + + + + TUSER + + + s_axis_c2h_tuser_0 + + + + + TVALID + + + s_axis_c2h_tvalid_0 + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + true + + + + + + M_AXIS_H2C_0 + M_AXIS_H2C_0 + + + + + + + TDATA + + + m_axis_h2c_tdata_0 + + + + + TKEEP + + + m_axis_h2c_tkeep_0 + + + + + TLAST + + + m_axis_h2c_tlast_0 + + + + + TREADY + + + m_axis_h2c_tready_0 + + + + + TUSER + + + m_axis_h2c_tuser_0 + + + + + TVALID + + + m_axis_h2c_tvalid_0 + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + true + + + + + + S_AXIS_C2H_1 + S_AXIS_C2H_1 + + + + + + + TDATA + + + s_axis_c2h_tdata_1 + + + + + TKEEP + + + s_axis_c2h_tkeep_1 + + + + + TLAST + + + s_axis_c2h_tlast_1 + + + + + TREADY + + + s_axis_c2h_tready_1 + + + + + TUSER + + + s_axis_c2h_tuser_1 + + + + + TVALID + + + s_axis_c2h_tvalid_1 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + M_AXIS_H2C_1 + M_AXIS_H2C_1 + + + + + + + TDATA + + + m_axis_h2c_tdata_1 + + + + + TKEEP + + + m_axis_h2c_tkeep_1 + + + + + TLAST + + + m_axis_h2c_tlast_1 + + + + + TREADY + + + m_axis_h2c_tready_1 + + + + + TUSER + + + m_axis_h2c_tuser_1 + + + + + TVALID + + + m_axis_h2c_tvalid_1 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + S_AXIS_C2H_2 + S_AXIS_C2H_2 + + + + + + + TDATA + + + s_axis_c2h_tdata_2 + + + + + TKEEP + + + s_axis_c2h_tkeep_2 + + + + + TLAST + + + s_axis_c2h_tlast_2 + + + + + TREADY + + + s_axis_c2h_tready_2 + + + + + TUSER + + + s_axis_c2h_tuser_2 + + + + + TVALID + + + s_axis_c2h_tvalid_2 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + M_AXIS_H2C_2 + M_AXIS_H2C_2 + + + + + + + TDATA + + + m_axis_h2c_tdata_2 + + + + + TKEEP + + + m_axis_h2c_tkeep_2 + + + + + TLAST + + + m_axis_h2c_tlast_2 + + + + + TREADY + + + m_axis_h2c_tready_2 + + + + + TUSER + + + m_axis_h2c_tuser_2 + + + + + TVALID + + + m_axis_h2c_tvalid_2 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + S_AXIS_C2H_3 + S_AXIS_C2H_3 + + + + + + + TDATA + + + s_axis_c2h_tdata_3 + + + + + TKEEP + + + s_axis_c2h_tkeep_3 + + + + + TLAST + + + s_axis_c2h_tlast_3 + + + + + TREADY + + + s_axis_c2h_tready_3 + + + + + TUSER + + + s_axis_c2h_tuser_3 + + + + + TVALID + + + s_axis_c2h_tvalid_3 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + M_AXIS_H2C_3 + M_AXIS_H2C_3 + + + + + + + TDATA + + + m_axis_h2c_tdata_3 + + + + + TKEEP + + + m_axis_h2c_tkeep_3 + + + + + TLAST + + + m_axis_h2c_tlast_3 + + + + + TREADY + + + m_axis_h2c_tready_3 + + + + + TUSER + + + m_axis_h2c_tuser_3 + + + + + TVALID + + + m_axis_h2c_tvalid_3 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + m_axis_cq + m_axis_cq + The Completer Request interface is used to transmit Completion TLP's to the Client Application + + + + + + + TDATA + + + m_axis_cq_tdata_sd + + + + + TKEEP + + + m_axis_cq_tkeep_sd + + + + + TLAST + + + m_axis_cq_tlast_sd + + + + + TREADY + + + m_axis_cq_tready_sd + + + + + TUSER + + + m_axis_cq_tuser_sd + + + + + TVALID + + + m_axis_cq_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + s_axis_cc + s_axis_cc + The Completer Completion Interface is used to transmit Completion TLP's + + + + + + + TDATA + + + s_axis_cc_tdata_sd + + + + + TKEEP + + + s_axis_cc_tkeep_sd + + + + + TLAST + + + s_axis_cc_tlast_sd + + + + + TREADY + + + s_axis_cc_tready_sd + + + + + TUSER + + + s_axis_cc_tuser_sd + + + + + TVALID + + + s_axis_cc_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + s_axis_rq + s_axis_rq + The Requestor Request interface received requests TLP's from the Client Application + + + + + + + TDATA + + + s_axis_rq_tdata_sd + + + + + TKEEP + + + s_axis_rq_tkeep_sd + + + + + TLAST + + + s_axis_rq_tlast_sd + + + + + TREADY + + + s_axis_rq_tready_sd + + + + + TUSER + + + s_axis_rq_tuser_sd + + + + + TVALID + + + s_axis_rq_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + m_axis_rc + m_axis_rc + The Requestor Completer interface transmits completions to the client application + + + + + + + TDATA + + + m_axis_rc_tdata_sd + + + + + TKEEP + + + m_axis_rc_tkeep_sd + + + + + TLAST + + + m_axis_rc_tlast_sd + + + + + TREADY + + + m_axis_rc_tready_sd + + + + + TUSER + + + m_axis_rc_tuser_sd + + + + + TVALID + + + m_axis_rc_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + pcie4_cfg_mesg_tx + pcie4_us_cfg_mesg_tx + Configuration Transmit Message Interface + + + + + + + TRANSMIT + + + cfg_msg_transmit_sd + + + + + TRANSMIT_DATA + + + cfg_msg_transmit_data_sd + + + + + TRANSMIT_DONE + + + cfg_msg_transmit_done_sd + + + + + TRANSMIT_TYPE + + + cfg_msg_transmit_type_sd + + + + + + + false + + + + + + pcie4_cfg_mesg_rcvd + pcie4_us_cfg_mesg_rcvd + Configuration Received Message Interface + + + + + + + recd + + + cfg_msg_received_sd + + + + + recd_data + + + cfg_msg_received_data_sd + + + + + recd_type + + + cfg_msg_received_type_sd + + + + + + + false + + + + + + pcie4_cfg_status + pcie4_us_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req_sd + + + + + cq_np_req_count + + + pcie_cq_np_req_count_sd + + + + + current_speed + + + cfg_current_speed_sd + + + + + err_cor_out + + + cfg_err_cor_out_sd + + + + + err_fatal_out + + + cfg_err_fatal_out_sd + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out_sd + + + + + function_status + + + cfg_function_status_sd + + + + + local_error_out + + + cfg_local_error_out_sd + + + + + ltssm_state + + + cfg_ltssm_state_sd + + + + + max_payload + + + cfg_max_payload_sd + + + + + max_read_req + + + cfg_max_read_req_sd + + + + + negotiated_width + + + cfg_negotiated_width_sd + + + + + phy_link_down + + + cfg_phy_link_down_sd + + + + + phy_link_status + + + cfg_phy_link_status_sd + + + + + pl_status_change + + + cfg_pl_status_change_sd + + + + + rq_seq_num0 + + + pcie_rq_seq_num0_sd + + + + + rq_seq_num1 + + + pcie_rq_seq_num1_sd + + + + + rq_seq_num_vld0 + + + pcie_rq_seq_num_vld0_sd + + + + + rq_seq_num_vld1 + + + pcie_rq_seq_num_vld1_sd + + + + + tfc_npd_av + + + pcie_tfc_npd_av_sd + + + + + tfc_nph_av + + + pcie_tfc_nph_av_sd + + + + + + + false + + + + + + pcie4_cfg_control + pcie4_us_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + ds_bus_number + + + cfg_ds_bus_number_sd + + + + + ds_device_number + + + cfg_ds_device_number_sd + + + + + ds_function_number + + + cfg_ds_function_number_sd + + + + + ds_port_number + + + cfg_ds_port_number_sd + + + + + dsn + + + cfg_dsn_sd + + + + + err_cor_in + + + cfg_err_cor_in_sd + + + + + err_uncor_in + + + cfg_err_uncor_in_sd + + + + + flr_done + + + cfg_flr_done_sd + + + + + flr_in_process + + + cfg_flr_in_process_sd + + + + + hot_reset_out + + + cfg_hot_reset_out_sd + + + + + link_training_enable + + + cfg_link_training_enable_sd + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process_sd + + + + + + + false + + + + + + pcie4_cfg_fc + pcie_cfg_fc + Configuration Flow Control INTERFACE + + + + + + + NPH + + + cfg_fc_nph_sd + + + + + SEL + + + cfg_fc_sel_sd + + + + + + + false + + + + + + pcie4_cfg_msi + pcie4_us_cfg_msi + PCIE MSI interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr_sd + + + + + data + + + cfg_interrupt_msi_data_sd + + + + + enable + + + cfg_interrupt_msi_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msi_int_sd + + + + + mask_update + + + cfg_interrupt_msi_mask_update_sd + + + + + pending_status + + + cfg_interrupt_msi_pending_status_sd + + + + + pending_status_data_enable + + + cfg_interrupt_msi_pending_status_data_enable_sd + + + + + pending_status_function_num + + + cfg_interrupt_msi_pending_status_function_num_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + tph_present + + + cfg_interrupt_msi_tph_present_sd + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag_sd + + + + + tph_type + + + cfg_interrupt_msi_tph_type_sd + + + + + + + false + + + + + + pcie4_cfg_msix_external + pcie4_cfg_msix_external + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_external_msix + pcie4_cfg_external_msix + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_interrupt + pcie4_cfg_interrupt + PCIE Legacy Interrupt + + + + + + + INTx_VECTOR + + + cfg_interrupt_int_sd + + + + + PENDING + + + cfg_interrupt_pending_sd + + + + + SENT + + + cfg_interrupt_sent_sd + + + + + + + false + + + + + + pcie_cfg_mgmt + pcie_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr + + + + + BYTE_EN + + + cfg_mgmt_byte_enable + + + + + READ_DATA + + + cfg_mgmt_read_data + + + + + READ_EN + + + cfg_mgmt_read + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done + + + + + TYPE1_CFG_REG_ACCESS + + + cfg_mgmt_type1_cfg_reg_access + + + + + WRITE_DATA + + + cfg_mgmt_write_data + + + + + WRITE_EN + + + cfg_mgmt_write + + + + + + + true + + + + + + pcie_mgt + pcie_7x_mgt + + + + + + + rxn + + + pci_exp_rxn + + + + + rxp + + + pci_exp_rxp + + + + + txn + + + pci_exp_txn + + + + + txp + + + pci_exp_txp + + + + + + BOARD.ASSOCIATED_PARAM + PCIE_BOARD_INTERFACE + + + + required + + + + + + + + + true + + + + + + drp + drp + DRP interface + + + + + + + DADDR + + + drp_addr + + + + + DEN + + + drp_en + + + + + DI + + + drp_di + + + + + DO + + + drp_do + + + + + DRDY + + + drp_rdy + + + + + DWE + + + drp_we + + + + + + + false + + + + + + pcie_debug_ports + pcie_debug_ports + PCIe Debug Interface + + + + + + + cfg_current_speed + + + cfg_current_speed_o + + + + + cfg_ltssm_state + + + cfg_ltssm_state_o + + + + + cfg_negotiated_width + + + cfg_negotiated_width_o + + + + + + + false + + + + + + pcie4_pcie_id + pcie4_pcie_id + PCIE 4 PCIE ID interface + + + + + + + subsys_vend_id + + + cfg_subsys_vend_id + + + + + vend_id + + + cfg_vend_id + + + + + + + false + + + + + + pcie4_pcie_id_pf0 + pcie4_pcie_id_pf0 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf0 + + + cfg_dev_id_pf0 + + + + + rev_id_pf0 + + + cfg_rev_id_pf0 + + + + + subsys_id_pf0 + + + cfg_subsys_id_pf0 + + + + + + + false + + + + + + pcie4_pcie_id_pf1 + pcie4_pcie_id_pf1 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf1 + + + cfg_dev_id_pf1 + + + + + rev_id_pf1 + + + cfg_rev_id_pf1 + + + + + subsys_id_pf1 + + + cfg_subsys_id_pf1 + + + + + + + false + + + + + + pcie4_pcie_id_pf2 + pcie4_pcie_id_pf2 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf2 + + + cfg_dev_id_pf2 + + + + + rev_id_pf2 + + + cfg_rev_id_pf2 + + + + + subsys_id_pf2 + + + cfg_subsys_id_pf2 + + + + + + + false + + + + + + pcie4_pcie_id_pf3 + pcie4_pcie_id_pf3 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf3 + + + cfg_dev_id_pf3 + + + + + rev_id_pf3 + + + cfg_rev_id_pf3 + + + + + subsys_id_pf3 + + + cfg_subsys_id_pf3 + + + + + + + false + + + + + + pcie3_7x_transceiver_debug + pcie3_7x_transceiver_debug + Transceiver Debug Interface of pcie3_7x + + + + + + + cpll_lock + + + pipe_cpll_lock + + + + + debug + + + pipe_debug + + + + + debug_0 + + + pipe_debug_0 + + + + + debug_1 + + + pipe_debug_1 + + + + + debug_2 + + + pipe_debug_2 + + + + + debug_3 + + + pipe_debug_3 + + + + + debug_4 + + + pipe_debug_4 + + + + + debug_5 + + + pipe_debug_5 + + + + + debug_6 + + + pipe_debug_6 + + + + + debug_7 + + + pipe_debug_7 + + + + + debug_8 + + + pipe_debug_8 + + + + + debug_9 + + + pipe_debug_9 + + + + + dmonitorout + + + pipe_dmonitorout + + + + + drp_fsm + + + pipe_drp_fsm + + + + + eyescandataerror + + + pipe_eyescandataerror + + + + + gt_ch_drp_rdy + + + gt_ch_drp_rdy + + + + + loopback + + + pipe_loopback + + + + + qpll_lock + + + pipe_qpll_lock + + + + + qrst_fsm + + + pipe_qrst_fsm + + + + + qrst_idle + + + pipe_qrst_idle + + + + + rate_fsm + + + pipe_rate_fsm + + + + + rate_idle + + + pipe_rate_idle + + + + + rst_fsm + + + pipe_rst_fsm + + + + + rst_idle + + + pipe_rst_idle + + + + + rxbufstatus + + + pipe_rxbufstatus + + + + + rxcommadet + + + pipe_rxcommadet + + + + + rxdisperr + + + pipe_rxdisperr + + + + + rxdlysresetdone + + + pipe_rxdlysresetdone + + + + + rxnotintable + + + pipe_rxnotintable + + + + + rxphaligndone + + + pipe_rxphaligndone + + + + + rxpmaresetdone + + + pipe_rxpmaresetdone + + + + + rxprbscntreset + + + pipe_rxprbscntreset + + + + + rxprbserr + + + pipe_rxprbserr + + + + + rxprbssel + + + pipe_rxprbssel + + + + + rxstatus + + + pipe_rxstatus + + + + + rxsyncdone + + + pipe_rxsyncdone + + + + + sync_fsm_rx + + + pipe_sync_fsm_rx + + + + + sync_fsm_tx + + + pipe_sync_fsm_tx + + + + + txdlysresetdone + + + pipe_txdlysresetdone + + + + + txinhibit + + + pipe_txinhibit + + + + + txphaligndone + + + pipe_txphaligndone + + + + + txphinitdone + + + pipe_txphinitdone + + + + + txprbsforceerr + + + pipe_txprbsforceerr + + + + + txprbssel + + + pipe_txprbssel + + + + + + + false + + + + + + pcie3_us_transceiver_debug + pcie3_us_transceiver_debug + Transceiver Debug Interface of pcie3_us + + + + + + + bufgtdiv + + + gt_bufgtdiv + + + + + cpll_lock + + + gt_cplllock + + + + + dmonfiforeset + + + gt_dmonfiforeset + + + + + dmonitorclk + + + gt_dmonitorclk + + + + + dmonitorout + + + gt_dmonitorout + + + + + eyescandataerror + + + gt_eyescandataerror + + + + + gtpowergood + + + gt_gtpowergood + + + + + loopback + + + gt_loopback + + + + + pcieuserratedone + + + gt_pcieuserratedone + + + + + pcieuserratestart + + + gt_pcieuserratestart + + + + + phystatus + + + gt_phystatus + + + + + prst_n + + + phy_prst_n + + + + + qpll_lock + + + gt_qpll1lock + + + + + rate_idle + + + gt_pcierateidle + + + + + rrst_n + + + phy_rrst_n + + + + + rst_fsm + + + phy_rst_fsm + + + + + rst_idle + + + phy_rst_idle + + + + + rxbufstatus + + + gt_rxbufstatus + + + + + rxcdrlock + + + gt_rxcdrlock + + + + + rxcommadet + + + gt_rxcommadet + + + + + rxdlysresetdone + + + gt_rxdlysresetdone + + + + + rxeq_fsm + + + phy_rxeq_fsm + + + + + rxoutclk + + + gt_rxoutclk + + + + + rxphaligndone + + + gt_rxphaligndone + + + + + rxpmaresetdone + + + gt_rxpmaresetdone + + + + + rxprbscntreset + + + gt_rxprbscntreset + + + + + rxprbserr + + + gt_rxprbserr + + + + + rxprbssel + + + gt_rxprbssel + + + + + rxrecclkout + + + gt_rxrecclkout + + + + + rxresetdone + + + gt_rxresetdone + + + + + rxstatus + + + gt_rxstatus + + + + + rxsyncdone + + + gt_rxsyncdone + + + + + rxvalid + + + gt_rxvalid + + + + + txdlysresetdone + + + gt_txdlysresetdone + + + + + txelecidle + + + gt_txelecidle + + + + + txeq_ctrl + + + phy_txeq_ctrl + + + + + txeq_fsm + + + phy_txeq_fsm + + + + + txeq_preset + + + phy_txeq_preset + + + + + txinhibit + + + gt_txinhibit + + + + + txphaligndone + + + gt_txphaligndone + + + + + txphinitdone + + + gt_txphinitdone + + + + + txprbsforceerr + + + gt_txprbsforceerr + + + + + txprbssel + + + gt_txprbssel + + + + + txresetdone + + + gt_txresetdone + + + + + + + false + + + + + + pcie4_us_plus_transceiver_debug + pcie4_us_plus_transceiver_debug + Transceiver Debug Interface of pcie4_us_plus + + + + + + + bufgtdiv + + + gt_bufgtdiv + + + + + cpll_lock + + + gt_cplllock + + + + + dmonfiforeset + + + gt_dmonfiforeset + + + + + dmonitorclk + + + gt_dmonitorclk + + + + + dmonitorout + + + gt_dmonitorout + + + + + eyescandataerror + + + gt_eyescandataerror + + + + + gen34_eios_det + + + gt_gen34_eios_det + + + + + gtpowergood + + + gt_gtpowergood + + + + + loopback + + + gt_loopback + + + + + pcieuserratedone + + + gt_pcieuserratedone + + + + + pcieuserratestart + + + gt_pcieuserratestart + + + + + phystatus + + + gt_phystatus + + + + + prst_n + + + phy_prst_n + + + + + qpll0_lock + + + gt_qpll0lock + + + + + qpll1_lock + + + gt_qpll1lock + + + + + rate_idle + + + gt_pcierateidle + + + + + rrst_n + + + phy_rrst_n + + + + + rst_fsm + + + phy_rst_fsm + + + + + rst_idle + + + phy_rst_idle + + + + + rxbufreset + + + gt_rxbufreset + + + + + rxbufstatus + + + gt_rxbufstatus + + + + + rxcdrlock + + + gt_rxcdrlock + + + + + rxcdrreset + + + gt_rxcdrreset + + + + + rxcommadet + + + gt_rxcommadet + + + + + rxdfelpmreset + + + gt_rxdfelpmreset + + + + + rxdlysresetdone + + + gt_rxdlysresetdone + + + + + rxeq_fsm + + + phy_rxeq_fsm + + + + + rxoutclk + + + gt_rxoutclk + + + + + rxoutclkfabric + + + gt_rxoutclkfabric + + + + + rxoutclkpcs + + + gt_rxoutclkpcs + + + + + rxpcsreset + + + gt_rxpcsreset + + + + + rxphaligndone + + + gt_rxphaligndone + + + + + rxpmareset + + + gt_rxpmareset + + + + + rxpmaresetdone + + + gt_rxpmaresetdone + + + + + rxprbscntreset + + + gt_rxprbscntreset + + + + + rxprbserr + + + gt_rxprbserr + + + + + rxprbslocked + + + gt_rxprbslocked + + + + + rxprbssel + + + gt_rxprbssel + + + + + rxrecclkout + + + gt_rxrecclkout + + + + + rxresetdone + + + gt_rxresetdone + + + + + rxstatus + + + gt_rxstatus + + + + + rxsyncdone + + + gt_rxsyncdone + + + + + rxvalid + + + gt_rxvalid + + + + + txdlysresetdone + + + gt_txdlysresetdone + + + + + txelecidle + + + gt_txelecidle + + + + + txeq_ctrl + + + phy_txeq_ctrl + + + + + txeq_fsm + + + phy_txeq_fsm + + + + + txeq_preset + + + phy_txeq_preset + + + + + txinhibit + + + gt_txinhibit + + + + + txoutclk + + + gt_txoutclk + + + + + txoutclkfabric + + + gt_txoutclkfabric + + + + + txoutclkpcs + + + gt_txoutclkpcs + + + + + txpcsreset + + + gt_txpcsreset + + + + + txphaligndone + + + gt_txphaligndone + + + + + txphinitdone + + + gt_txphinitdone + + + + + txpmareset + + + gt_txpmareset + + + + + txpmaresetdone + + + gt_txpmaresetdone + + + + + txprbsforceerr + + + gt_txprbsforceerr + + + + + txprbssel + + + gt_txprbssel + + + + + txprogdivresetdone + + + gt_txprogdivresetdone + + + + + txresetdone + + + gt_txresetdone + + + + + txsyncdone + + + gt_txsyncdone + + + + + + + false + + + + + + pcie3_us_gt_if + pcie3_us_gt_if + GT Interface + + + + + + + bufgtce_out + + + bufgtce_us_out + + + + + bufgtcemask_out + + + bufgtcemask_us_out + + + + + bufgtdiv_out + + + bufgtdiv_us_out + + + + + bufgtreset_out + + + bufgtreset_us_out + + + + + bufgtrstmask_out + + + bufgtrstmask_us_out + + + + + cplllock_out + + + cplllock_us_out + + + + + cpllpd_in + + + cpllpd_us_in + + + + + cpllreset_in + + + cpllreset_us_in + + + + + dmonfiforeset_in + + + dmonfiforeset_us_in + + + + + dmonitorclk_in + + + dmonitorclk_us_in + + + + + dmonitorout_out + + + dmonitorout_us_out + + + + + drpaddr_in + + + drpaddr_us_in + + + + + drpclk_in + + + drpclk_us_in + + + + + drpdi_in + + + drpdi_us_in + + + + + drpdo_out + + + drpdo_us_out + + + + + drpen_in + + + drpen_us_in + + + + + drprdy_out + + + drprdy_us_out + + + + + drpwe_in + + + drpwe_us_in + + + + + eyescandataerror_out + + + eyescandataerror_us_out + + + + + eyescanreset_in + + + eyescanreset_us_in + + + + + gthrxn_in + + + gthrxn_us_in + + + + + gthrxp_in + + + gthrxp_us_in + + + + + gthtxn_out + + + gthtxn_us_out + + + + + gthtxp_out + + + gthtxp_us_out + + + + + gtpowergood_out + + + gtpowergood_us_out + + + + + gtrefclk0_in + + + gtrefclk0_us_in + + + + + gtrefclk01_in + + + gtrefclk01_us_in + + + + + gtrxreset_in + + + gtrxreset_us_in + + + + + gttxreset_in + + + gttxreset_us_in + + + + + gtwiz_reset_rx_done_in + + + gtwiz_reset_rx_done_us_in + + + + + gtwiz_reset_tx_done_in + + + gtwiz_reset_tx_done_us_in + + + + + gtwiz_userclk_rx_active_in + + + gtwiz_userclk_rx_active_us_in + + + + + gtwiz_userclk_tx_active_in + + + gtwiz_userclk_tx_active_us_in + + + + + gtwiz_userclk_tx_reset_in + + + gtwiz_userclk_tx_reset_us_in + + + + + loopback_in + + + loopback_us_in + + + + + pcieeqrxeqadaptdone_in + + + pcieeqrxeqadaptdone_us_in + + + + + pcierategen3_out + + + pcierategen3_us_out + + + + + pcierateidle_out + + + pcierateidle_us_out + + + + + pcierateqpllpd_out + + + pcierateqpllpd_us_out + + + + + pcierateqpllreset_out + + + pcierateqpllreset_us_out + + + + + pcierstidle_in + + + pcierstidle_us_in + + + + + pciersttxsyncstart_in + + + pciersttxsyncstart_us_in + + + + + pciesynctxsyncdone_out + + + pciesynctxsyncdone_us_out + + + + + pcieusergen3rdy_out + + + pcieusergen3rdy_us_out + + + + + pcieuserphystatusrst_out + + + pcieuserphystatusrst_us_out + + + + + pcieuserratedone_in + + + pcieuserratedone_us_in + + + + + pcieuserratestart_out + + + pcieuserratestart_us_out + + + + + pcsrsvdin_in + + + pcsrsvdin_us_in + + + + + pcsrsvdout_out + + + pcsrsvdout_us_out + + + + + phystatus_out + + + phystatus_us_out + + + + + qpll0clk_in + + + qpll0clk_us_in + + + + + qpll0refclk_in + + + qpll0refclk_us_in + + + + + qpll1clk_in + + + qpll1clk_us_in + + + + + qpll1lock_out + + + qpll1lock_us_out + + + + + qpll1outclk_out + + + qpll1outclk_us_out + + + + + qpll1outrefclk_out + + + qpll1outrefclk_us_out + + + + + qpll1pd_in + + + qpll1pd_us_in + + + + + qpll1refclk_in + + + qpll1refclk_us_in + + + + + qpll1reset_in + + + qpll1reset_us_in + + + + + qpllrsvd2_in + + + qpllrsvd2_us_in + + + + + qpllrsvd3_in + + + qpllrsvd3_us_in + + + + + rx8b10ben_in + + + rx8b10ben_us_in + + + + + rxbufreset_in + + + rxbufreset_us_in + + + + + rxbufstatus_out + + + rxbufstatus_us_out + + + + + rxbyteisaligned_out + + + rxbyteisaligned_us_out + + + + + rxbyterealign_out + + + rxbyterealign_us_out + + + + + rxcdrhold_in + + + rxcdrhold_us_in + + + + + rxcdrlock_out + + + rxcdrlock_us_out + + + + + rxclkcorcnt_out + + + rxclkcorcnt_us_out + + + + + rxcommadet_out + + + rxcommadet_us_out + + + + + rxcommadeten_in + + + rxcommadeten_us_in + + + + + rxctrl0_out + + + rxctrl0_us_out + + + + + rxctrl1_out + + + rxctrl1_us_out + + + + + rxctrl2_out + + + rxctrl2_us_out + + + + + rxctrl3_out + + + rxctrl3_us_out + + + + + rxdata_out + + + rxdata_us_out + + + + + rxdfeagchold_in + + + rxdfeagchold_us_in + + + + + rxdfecfokhold_in + + + rxdfecfokhold_us_in + + + + + rxdfekhhold_in + + + rxdfekhhold_us_in + + + + + rxdfelfhold_in + + + rxdfelfhold_us_in + + + + + rxdfetap2hold_in + + + rxdfetap2hold_us_in + + + + + rxdfetap3hold_in + + + rxdfetap3hold_us_in + + + + + rxdfetap4hold_in + + + rxdfetap4hold_us_in + + + + + rxdfetap5hold_in + + + rxdfetap5hold_us_in + + + + + rxdfetap6hold_in + + + rxdfetap6hold_us_in + + + + + rxdfetap7hold_in + + + rxdfetap7hold_us_in + + + + + rxdfetap8hold_in + + + rxdfetap8hold_us_in + + + + + rxdfetap9hold_in + + + rxdfetap9hold_us_in + + + + + rxdfetap10hold_in + + + rxdfetap10hold_us_in + + + + + rxdfetap11hold_in + + + rxdfetap11hold_us_in + + + + + rxdfetap12hold_in + + + rxdfetap12hold_us_in + + + + + rxdfetap13hold_in + + + rxdfetap13hold_us_in + + + + + rxdfetap14hold_in + + + rxdfetap14hold_us_in + + + + + rxdfetap15hold_in + + + rxdfetap15hold_us_in + + + + + rxdfeuthold_in + + + rxdfeuthold_us_in + + + + + rxdfevphold_in + + + rxdfevphold_us_in + + + + + rxdlysresetdone_out + + + rxdlysresetdone_us_out + + + + + rxelecidle_out + + + rxelecidle_us_out + + + + + rxlpmen_in + + + rxlpmen_us_in + + + + + rxlpmgchold_in + + + rxlpmgchold_us_in + + + + + rxlpmhfhold_in + + + rxlpmhfhold_us_in + + + + + rxlpmlfhold_in + + + rxlpmlfhold_us_in + + + + + rxlpmoshold_in + + + rxlpmoshold_us_in + + + + + rxmcommaalignen_in + + + rxmcommaalignen_us_in + + + + + rxoshold_in + + + rxoshold_us_in + + + + + rxoutclk_out + + + rxoutclk_us_out + + + + + rxpcommaalignen_in + + + rxpcommaalignen_us_in + + + + + rxpd_in + + + rxpd_us_in + + + + + rxphaligndone_out + + + rxphaligndone_us_out + + + + + rxpmaresetdone_out + + + rxpmaresetdone_us_out + + + + + rxpolarity_in + + + rxpolarity_us_in + + + + + rxprbscntreset_in + + + rxprbscntreset_us_in + + + + + rxprbserr_out + + + rxprbserr_us_out + + + + + rxprbslocked_out + + + rxprbslocked_us_out + + + + + rxprbssel_in + + + rxprbssel_us_in + + + + + rxprgdivresetdone_out + + + rxprgdivresetdone_us_out + + + + + rxprogdivreset_in + + + rxprogdivreset_us_in + + + + + rxrate_in + + + rxrate_us_in + + + + + rxratedone_out + + + rxratedone_us_out + + + + + rxratemode_in + + + rxratemode_us_in + + + + + rxresetdone_out + + + rxresetdone_us_out + + + + + rxslide_in + + + rxslide_us_in + + + + + rxstatus_out + + + rxstatus_us_out + + + + + rxsyncdone_out + + + rxsyncdone_us_out + + + + + rxuserrdy_in + + + rxuserrdy_us_in + + + + + rxusrclk2_in + + + rxusrclk2_us_in + + + + + rxusrclk_in + + + rxusrclk_us_in + + + + + rxvalid_out + + + rxvalid_us_out + + + + + tx8b10ben_in + + + tx8b10ben_us_in + + + + + txctrl0_in + + + txctrl0_us_in + + + + + txctrl1_in + + + txctrl1_us_in + + + + + txctrl2_in + + + txctrl2_us_in + + + + + txdata_in + + + txdata_us_in + + + + + txdeemph_in + + + txdeemph_us_in + + + + + txdetectrx_in + + + txdetectrx_us_in + + + + + txdiffctrl_in + + + txdiffctrl_us_in + + + + + txdlybypass_in + + + txdlybypass_us_in + + + + + txdlyen_in + + + txdlyen_us_in + + + + + txdlyhold_in + + + txdlyhold_us_in + + + + + txdlyovrden_in + + + txdlyovrden_us_in + + + + + txdlysreset_in + + + txdlysreset_us_in + + + + + txdlysresetdone_out + + + txdlysresetdone_us_out + + + + + txdlyupdown_in + + + txdlyupdown_us_in + + + + + txelecidle_in + + + txelecidle_us_in + + + + + txinhibit_in + + + txinhibit_us_in + + + + + txmaincursor_in + + + txmaincursor_us_in + + + + + txmargin_in + + + txmargin_us_in + + + + + txoutclk_out + + + txoutclk_us_out + + + + + txoutclksel_in + + + txoutclksel_us_in + + + + + txpd_in + + + txpd_us_in + + + + + txphalign_in + + + txphalign_us_in + + + + + txphaligndone_out + + + txphaligndone_us_out + + + + + txphalignen_in + + + txphalignen_us_in + + + + + txphdlypd_in + + + txphdlypd_us_in + + + + + txphdlyreset_in + + + txphdlyreset_us_in + + + + + txphdlytstclk_in + + + txphdlytstclk_us_in + + + + + txphinit_in + + + txphinit_us_in + + + + + txphinitdone_out + + + txphinitdone_us_out + + + + + txphovrden_in + + + txphovrden_us_in + + + + + txpmaresetdone_out + + + txpmaresetdone_us_out + + + + + txpostcursor_in + + + txpostcursor_us_in + + + + + txprbsforceerr_in + + + txprbsforceerr_us_in + + + + + txprbssel_in + + + txprbssel_us_in + + + + + txprecursor_in + + + txprecursor_us_in + + + + + txprgdivresetdone_out + + + txprgdivresetdone_us_out + + + + + txprogdivreset_in + + + txprogdivreset_us_in + + + + + txrate_in + + + txrate_us_in + + + + + txresetdone_out + + + txresetdone_us_out + + + + + txswing_in + + + txswing_us_in + + + + + txsyncallin_in + + + txsyncallin_us_in + + + + + txsyncdone_out + + + txsyncdone_us_out + + + + + txsyncin_in + + + txsyncin_us_in + + + + + txsyncmode_in + + + txsyncmode_us_in + + + + + txsyncout_out + + + txsyncout_us_out + + + + + txuserrdy_in + + + txuserrdy_us_in + + + + + txusrclk2_in + + + txusrclk2_us_in + + + + + txusrclk_in + + + txusrclk_us_in + + + + + + + false + + + + + + pcie4_gt_if + pcie4_gt_if + GT Interface + + + + + + + bufgtce_out + + + bufgtce_usp_out + + + + + bufgtcemask_out + + + bufgtcemask_usp_out + + + + + bufgtdiv_out + + + bufgtdiv_usp_out + + + + + bufgtreset_out + + + bufgtreset_usp_out + + + + + bufgtrstmask_out + + + bufgtrstmask_usp_out + + + + + cpllfreqlock_in + + + cpllfreqlock_usp_in + + + + + cplllock_out + + + cplllock_usp_out + + + + + cpllpd_in + + + cpllpd_usp_in + + + + + cpllreset_in + + + cpllreset_usp_in + + + + + dmonfiforeset_in + + + dmonfiforeset_usp_in + + + + + dmonitorclk_in + + + dmonitorclk_usp_in + + + + + dmonitorout_out + + + dmonitorout_usp_out + + + + + drpaddr_in + + + drpaddr_usp_in + + + + + drpclk_in + + + drpclk_usp_in + + + + + drpdi_in + + + drpdi_usp_in + + + + + drpdo_out + + + drpdo_usp_out + + + + + drpen_in + + + drpen_usp_in + + + + + drprdy_out + + + drprdy_usp_out + + + + + drprst_in + + + drprst_usp_in + + + + + drpwe_in + + + drpwe_usp_in + + + + + ext_phy_clk_bufg_gt_ce + + + ext_phy_clk_bufg_gt_ce + + + + + ext_phy_clk_bufg_gt_reset + + + ext_phy_clk_bufg_gt_reset + + + + + ext_phy_clk_bufgtcemask + + + ext_phy_clk_bufgtcemask + + + + + ext_phy_clk_bufgtdiv + + + ext_phy_clk_bufgtdiv + + + + + ext_phy_clk_gt_bufgtrstmask + + + ext_phy_clk_gt_bufgtrstmask + + + + + ext_phy_clk_int_clock + + + ext_phy_clk_int_clock + + + + + ext_phy_clk_pclk + + + ext_phy_clk_pclk + + + + + ext_phy_clk_pclk2_gt + + + ext_phy_clk_pclk2_gt + + + + + ext_phy_clk_phy_coreclk + + + ext_phy_clk_phy_coreclk + + + + + ext_phy_clk_phy_mcapclk + + + ext_phy_clk_phy_mcapclk + + + + + ext_phy_clk_phy_pclk2 + + + ext_phy_clk_phy_pclk2 + + + + + ext_phy_clk_phy_userclk + + + ext_phy_clk_phy_userclk + + + + + ext_phy_clk_rst_idle + + + ext_phy_clk_rst_idle + + + + + ext_phy_clk_txoutclk + + + ext_phy_clk_txoutclk + + + + + eyescanreset_in + + + eyescanreset_usp_in + + + + + gtpowergood_out + + + gtpowergood_usp_out + + + + + gtrefclk0_in + + + gtrefclk0_usp_in + + + + + gtrefclk00_in + + + gtrefclk00_usp_in + + + + + gtrefclk01_in + + + gtrefclk01_usp_in + + + + + gtrxreset_in + + + gtrxreset_usp_in + + + + + gttxreset_in + + + gttxreset_usp_in + + + + + gtwiz_reset_rx_done_in + + + gtwiz_reset_rx_done_usp_in + + + + + gtwiz_reset_tx_done_in + + + gtwiz_reset_tx_done_usp_in + + + + + gtwiz_userclk_rx_active_in + + + gtwiz_userclk_rx_active_usp_in + + + + + gtwiz_userclk_tx_active_in + + + gtwiz_userclk_tx_active_usp_in + + + + + loopback_in + + + loopback_usp_in + + + + + pcieeqrxeqadaptdone_in + + + pcieeqrxeqadaptdone_usp_in + + + + + pcierategen3_out + + + pcierategen3_usp_out + + + + + pcierateidle_out + + + pcierateidle_usp_out + + + + + pcierateqpll0_in + + + pcierateqpll0_usp_in + + + + + pcierateqpll1_in + + + pcierateqpll1_usp_in + + + + + pcierateqpllpd_out + + + pcierateqpllpd_usp_out + + + + + pcierateqpllreset_out + + + pcierateqpllreset_usp_out + + + + + pcierstidle_in + + + pcierstidle_usp_in + + + + + pciersttxsyncstart_in + + + pciersttxsyncstart_usp_in + + + + + pciesynctxsyncdone_out + + + pciesynctxsyncdone_usp_out + + + + + pcieusergen3rdy_out + + + pcieusergen3rdy_usp_out + + + + + pcieuserphystatusrst_out + + + pcieuserphystatusrst_usp_out + + + + + pcieuserratedone_in + + + pcieuserratedone_usp_in + + + + + pcieuserratestart_out + + + pcieuserratestart_usp_out + + + + + phystatus_out + + + phystatus_usp_out + + + + + qpll0freqlock_in + + + qpll0freqlock_usp_in + + + + + qpll0lock_out + + + qpll0lock_usp_out + + + + + qpll0outclk_out + + + qpll0outclk_usp_out + + + + + qpll0outrefclk_out + + + qpll0outrefclk_usp_out + + + + + qpll0pd_in + + + qpll0pd_usp_in + + + + + qpll0reset_in + + + qpll0reset_usp_in + + + + + qpll1freqlock_in + + + qpll1freqlock_usp_in + + + + + qpll1lock_out + + + qpll1lock_usp_out + + + + + qpll1outclk_out + + + qpll1outclk_usp_out + + + + + qpll1outrefclk_out + + + qpll1outrefclk_usp_out + + + + + qpll1pd_in + + + qpll1pd_usp_in + + + + + qpll1reset_in + + + qpll1reset_usp_in + + + + + rcalenb_in + + + rcalenb_usp_in + + + + + resetovrd_in + + + resetovrd_usp_in + + + + + rx8b10ben_in + + + rx8b10ben_usp_in + + + + + rxbufreset_in + + + rxbufreset_usp_in + + + + + rxbufstatus_out + + + rxbufstatus_usp_out + + + + + rxbyteisaligned_out + + + rxbyteisaligned_usp_out + + + + + rxbyterealign_out + + + rxbyterealign_usp_out + + + + + rxcdrfreqreset_in + + + rxcdrfreqreset_usp_in + + + + + rxcdrhold_in + + + rxcdrhold_usp_in + + + + + rxcdrlock_out + + + rxcdrlock_usp_out + + + + + rxcdrreset_in + + + rxcdrreset_usp_in + + + + + rxclkcorcnt_out + + + rxclkcorcnt_usp_out + + + + + rxcommadet_out + + + rxcommadet_usp_out + + + + + rxcommadeten_in + + + rxcommadeten_usp_in + + + + + rxctrl0_out + + + rxctrl0_usp_out + + + + + rxctrl1_out + + + rxctrl1_usp_out + + + + + rxctrl2_out + + + rxctrl2_usp_out + + + + + rxctrl3_out + + + rxctrl3_usp_out + + + + + rxdata_out + + + rxdata_usp_out + + + + + rxdfeagchold_in + + + rxdfeagchold_usp_in + + + + + rxdfecfokhold_in + + + rxdfecfokhold_usp_in + + + + + rxdfekhhold_in + + + rxdfekhhold_usp_in + + + + + rxdfelfhold_in + + + rxdfelfhold_usp_in + + + + + rxdfelpmreset_in + + + rxdfelpmreset_usp_in + + + + + rxdfetap2hold_in + + + rxdfetap2hold_usp_in + + + + + rxdfetap3hold_in + + + rxdfetap3hold_usp_in + + + + + rxdfetap4hold_in + + + rxdfetap4hold_usp_in + + + + + rxdfetap5hold_in + + + rxdfetap5hold_usp_in + + + + + rxdfetap6hold_in + + + rxdfetap6hold_usp_in + + + + + rxdfetap7hold_in + + + rxdfetap7hold_usp_in + + + + + rxdfetap8hold_in + + + rxdfetap8hold_usp_in + + + + + rxdfetap9hold_in + + + rxdfetap9hold_usp_in + + + + + rxdfetap10hold_in + + + rxdfetap10hold_usp_in + + + + + rxdfetap11hold_in + + + rxdfetap11hold_usp_in + + + + + rxdfetap12hold_in + + + rxdfetap12hold_usp_in + + + + + rxdfetap13hold_in + + + rxdfetap13hold_usp_in + + + + + rxdfetap14hold_in + + + rxdfetap14hold_usp_in + + + + + rxdfetap15hold_in + + + rxdfetap15hold_usp_in + + + + + rxdfeuthold_in + + + rxdfeuthold_usp_in + + + + + rxdfevphold_in + + + rxdfevphold_usp_in + + + + + rxdlysresetdone_out + + + rxdlysresetdone_usp_out + + + + + rxelecidle_out + + + rxelecidle_usp_out + + + + + rxlpmen_in + + + rxlpmen_usp_in + + + + + rxlpmgchold_in + + + rxlpmgchold_usp_in + + + + + rxlpmhfhold_in + + + rxlpmhfhold_usp_in + + + + + rxlpmlfhold_in + + + rxlpmlfhold_usp_in + + + + + rxlpmoshold_in + + + rxlpmoshold_usp_in + + + + + rxmcommaalignen_in + + + rxmcommaalignen_usp_in + + + + + rxoshold_in + + + rxoshold_usp_in + + + + + rxoutclk_out + + + rxoutclk_usp_out + + + + + rxoutclkfabric_out + + + rxoutclkfabric_usp_out + + + + + rxoutclkpcs_out + + + rxoutclkpcs_usp_out + + + + + rxpcommaalignen_in + + + rxpcommaalignen_usp_in + + + + + rxpcsreset_in + + + rxpcsreset_usp_in + + + + + rxpd_in + + + rxpd_usp_in + + + + + rxphaligndone_out + + + rxphaligndone_usp_out + + + + + rxpmareset_in + + + rxpmareset_usp_in + + + + + rxpmaresetdone_out + + + rxpmaresetdone_usp_out + + + + + rxpolarity_in + + + rxpolarity_usp_in + + + + + rxprbscntreset_in + + + rxprbscntreset_usp_in + + + + + rxprbserr_out + + + rxprbserr_usp_out + + + + + rxprbslocked_out + + + rxprbslocked_usp_out + + + + + rxprbssel_in + + + rxprbssel_usp_in + + + + + rxprogdivreset_in + + + rxprogdivreset_usp_in + + + + + rxrate_in + + + rxrate_usp_in + + + + + rxratedone_out + + + rxratedone_usp_out + + + + + rxratemode_in + + + rxratemode_usp_in + + + + + rxrecclkout_out + + + rxrecclkout_usp_out + + + + + rxresetdone_out + + + rxresetdone_usp_out + + + + + rxslide_in + + + rxslide_usp_in + + + + + rxstatus_out + + + rxstatus_usp_out + + + + + rxsyncdone_out + + + rxsyncdone_usp_out + + + + + rxtermination_in + + + rxtermination_usp_in + + + + + rxuserrdy_in + + + rxuserrdy_usp_in + + + + + rxusrclk2_in + + + rxusrclk2_usp_in + + + + + rxusrclk_in + + + rxusrclk_usp_in + + + + + rxvalid_out + + + rxvalid_usp_out + + + + + tx8b10ben_in + + + tx8b10ben_usp_in + + + + + txctrl0_in + + + txctrl0_usp_in + + + + + txctrl1_in + + + txctrl1_usp_in + + + + + txctrl2_in + + + txctrl2_usp_in + + + + + txdata_in + + + txdata_usp_in + + + + + txdeemph_in + + + txdeemph_usp_in + + + + + txdetectrx_in + + + txdetectrx_usp_in + + + + + txdiffctrl_in + + + txdiffctrl_usp_in + + + + + txdlybypass_in + + + txdlybypass_usp_in + + + + + txdlyen_in + + + txdlyen_usp_in + + + + + txdlyhold_in + + + txdlyhold_usp_in + + + + + txdlyovrden_in + + + txdlyovrden_usp_in + + + + + txdlysreset_in + + + txdlysreset_usp_in + + + + + txdlysresetdone_out + + + txdlysresetdone_usp_out + + + + + txdlyupdown_in + + + txdlyupdown_usp_in + + + + + txelecidle_in + + + txelecidle_usp_in + + + + + txmaincursor_in + + + txmaincursor_usp_in + + + + + txmargin_in + + + txmargin_usp_in + + + + + txoutclk_out + + + txoutclk_usp_out + + + + + txoutclkfabric_out + + + txoutclkfabric_usp_out + + + + + txoutclkpcs_out + + + txoutclkpcs_usp_out + + + + + txoutclksel_in + + + txoutclksel_usp_in + + + + + txpcsreset_in + + + txpcsreset_usp_in + + + + + txpd_in + + + txpd_usp_in + + + + + txphalign_in + + + txphalign_usp_in + + + + + txphaligndone_out + + + txphaligndone_usp_out + + + + + txphalignen_in + + + txphalignen_usp_in + + + + + txphdlypd_in + + + txphdlypd_usp_in + + + + + txphdlyreset_in + + + txphdlyreset_usp_in + + + + + txphdlytstclk_in + + + txphdlytstclk_usp_in + + + + + txphinit_in + + + txphinit_usp_in + + + + + txphinitdone_out + + + txphinitdone_usp_out + + + + + txphovrden_in + + + txphovrden_usp_in + + + + + txpisopd_in + + + txpisopd_usp_in + + + + + txpmareset_in + + + txpmareset_usp_in + + + + + txpmaresetdone_out + + + txpmaresetdone_usp_out + + + + + txpostcursor_in + + + txpostcursor_usp_in + + + + + txprbsforceerr_in + + + txprbsforceerr_usp_in + + + + + txprbssel_in + + + txprbssel_usp_in + + + + + txprecursor_in + + + txprecursor_usp_in + + + + + txprgdivresetdone_out + + + txprgdivresetdone_usp_out + + + + + txprogdivreset_in + + + txprogdivreset_usp_in + + + + + txrate_in + + + txrate_usp_in + + + + + txresetdone_out + + + txresetdone_usp_out + + + + + txswing_in + + + txswing_usp_in + + + + + txsyncallin_in + + + txsyncallin_usp_in + + + + + txsyncdone_out + + + txsyncdone_usp_out + + + + + txsyncin_in + + + txsyncin_usp_in + + + + + txsyncmode_in + + + txsyncmode_usp_in + + + + + txsyncout_out + + + txsyncout_usp_out + + + + + txuserrdy_in + + + txuserrdy_usp_in + + + + + txusrclk2_in + + + txusrclk2_usp_in + + + + + txusrclk_in + + + txusrclk_usp_in + + + + + + + false + + + + + + pcie_ext_ch_gt + pcie_ext_ch_gt + GT DRP interface + + + + + + + DADDR + + + ext_ch_gt_drpaddr + + + + + DEN + + + ext_ch_gt_drpen + + + + + DI + + + ext_ch_gt_drpdi + + + + + DO + + + ext_ch_gt_drpdo + + + + + DRDY + + + ext_ch_gt_drprdy + + + + + DWE + + + ext_ch_gt_drpwe + + + + + + + false + + + + + + pcie_cfg_ext + pcie4_us_cfg_ext + Configuration Extend Interface + + + + + + + function_number + + + cfg_ext_function_number + + + + + read_data + + + cfg_ext_read_data + + + + + read_data_valid + + + cfg_ext_read_data_valid + + + + + read_received + + + cfg_ext_read_received + + + + + register_number + + + cfg_ext_register_number + + + + + write_byte_enable + + + cfg_ext_write_byte_enable + + + + + write_data + + + cfg_ext_write_data + + + + + write_received + + + cfg_ext_write_received + + + + + + + false + + + + + + CLK.ext_ch_gt_drpclk + + + + + + + CLK + + + ext_ch_gt_drpclk + + + + + + ASSOCIATED_BUSIF + pcie_ext_ch_gt + + + FREQ_HZ + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + + false + + + + + + pcie_ext_pipe_rp_usp + pcie3_ext_pipe_rp_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_in + + + + + COMMANDS_OUT + + + common_commands_out + + + + + RX_0 + + + pipe_rx_0_sigs + + + + + RX_1 + + + pipe_rx_1_sigs + + + + + RX_2 + + + pipe_rx_2_sigs + + + + + RX_3 + + + pipe_rx_3_sigs + + + + + RX_4 + + + pipe_rx_4_sigs + + + + + RX_5 + + + pipe_rx_5_sigs + + + + + RX_6 + + + pipe_rx_6_sigs + + + + + RX_7 + + + pipe_rx_7_sigs + + + + + RX_8 + + + pipe_rx_8_sigs + + + + + RX_9 + + + pipe_rx_9_sigs + + + + + RX_10 + + + pipe_rx_10_sigs + + + + + RX_11 + + + pipe_rx_11_sigs + + + + + RX_12 + + + pipe_rx_12_sigs + + + + + RX_13 + + + pipe_rx_13_sigs + + + + + RX_14 + + + pipe_rx_14_sigs + + + + + RX_15 + + + pipe_rx_15_sigs + + + + + TX_0 + + + pipe_tx_0_sigs + + + + + TX_1 + + + pipe_tx_1_sigs + + + + + TX_2 + + + pipe_tx_2_sigs + + + + + TX_3 + + + pipe_tx_3_sigs + + + + + TX_4 + + + pipe_tx_4_sigs + + + + + TX_5 + + + pipe_tx_5_sigs + + + + + TX_6 + + + pipe_tx_6_sigs + + + + + TX_7 + + + pipe_tx_7_sigs + + + + + TX_8 + + + pipe_tx_8_sigs + + + + + TX_9 + + + pipe_tx_9_sigs + + + + + TX_10 + + + pipe_tx_10_sigs + + + + + TX_11 + + + pipe_tx_11_sigs + + + + + TX_12 + + + pipe_tx_12_sigs + + + + + TX_13 + + + pipe_tx_13_sigs + + + + + TX_14 + + + pipe_tx_14_sigs + + + + + TX_15 + + + pipe_tx_15_sigs + + + + + + + false + + + + + + pcie_ext_pipe_ep_usp + pcie3_ext_pipe_ep_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + RX_8 + + + pipe_tx_8_sigs + + + + + RX_9 + + + pipe_tx_9_sigs + + + + + RX_10 + + + pipe_tx_10_sigs + + + + + RX_11 + + + pipe_tx_11_sigs + + + + + RX_12 + + + pipe_tx_12_sigs + + + + + RX_13 + + + pipe_tx_13_sigs + + + + + RX_14 + + + pipe_tx_14_sigs + + + + + RX_15 + + + pipe_tx_15_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + TX_8 + + + pipe_rx_8_sigs + + + + + TX_9 + + + pipe_rx_9_sigs + + + + + TX_10 + + + pipe_rx_10_sigs + + + + + TX_11 + + + pipe_rx_11_sigs + + + + + TX_12 + + + pipe_rx_12_sigs + + + + + TX_13 + + + pipe_rx_13_sigs + + + + + TX_14 + + + pipe_rx_14_sigs + + + + + TX_15 + + + pipe_rx_15_sigs + + + + + + + false + + + + + + pcie_ext_pipe_ep_legacy_usp + pcie3_ext_pipe_ep_legacy_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + RX_8 + + + pipe_tx_8_sigs + + + + + RX_9 + + + pipe_tx_9_sigs + + + + + RX_10 + + + pipe_tx_10_sigs + + + + + RX_11 + + + pipe_tx_11_sigs + + + + + RX_12 + + + pipe_tx_12_sigs + + + + + RX_13 + + + pipe_tx_13_sigs + + + + + RX_14 + + + pipe_tx_14_sigs + + + + + RX_15 + + + pipe_tx_15_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + TX_8 + + + pipe_rx_8_sigs + + + + + TX_9 + + + pipe_rx_9_sigs + + + + + TX_10 + + + pipe_rx_10_sigs + + + + + TX_11 + + + pipe_rx_11_sigs + + + + + TX_12 + + + pipe_rx_12_sigs + + + + + TX_13 + + + pipe_rx_13_sigs + + + + + TX_14 + + + pipe_rx_14_sigs + + + + + TX_15 + + + pipe_rx_15_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_rp + pcie3_ext_pipe_rp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_in + + + + + COMMANDS_OUT + + + common_commands_out + + + + + RX_0 + + + pipe_rx_0_sigs + + + + + RX_1 + + + pipe_rx_1_sigs + + + + + RX_2 + + + pipe_rx_2_sigs + + + + + RX_3 + + + pipe_rx_3_sigs + + + + + RX_4 + + + pipe_rx_4_sigs + + + + + RX_5 + + + pipe_rx_5_sigs + + + + + RX_6 + + + pipe_rx_6_sigs + + + + + RX_7 + + + pipe_rx_7_sigs + + + + + TX_0 + + + pipe_tx_0_sigs + + + + + TX_1 + + + pipe_tx_1_sigs + + + + + TX_2 + + + pipe_tx_2_sigs + + + + + TX_3 + + + pipe_tx_3_sigs + + + + + TX_4 + + + pipe_tx_4_sigs + + + + + TX_5 + + + pipe_tx_5_sigs + + + + + TX_6 + + + pipe_tx_6_sigs + + + + + TX_7 + + + pipe_tx_7_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_ep + pcie3_ext_pipe_ep + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_ep_legacy + pcie3_ext_pipe_ep_legacy + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + + + false + + + + + + dsc_bypass_c2h_0 + dsc_bypass_c2h_0 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_0 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_0 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_0 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_0 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_0 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_0 + + + + + + + false + + + + + + dsc_bypass_c2h_1 + dsc_bypass_c2h_1 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_1 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_1 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_1 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_1 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_1 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_1 + + + + + + + false + + + + + + dsc_bypass_c2h_2 + dsc_bypass_c2h_2 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_2 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_2 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_2 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_2 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_2 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_2 + + + + + + + false + + + + + + dsc_bypass_c2h_3 + dsc_bypass_c2h_3 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_3 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_3 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_3 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_3 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_3 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_3 + + + + + + + false + + + + + + dsc_bypass_h2c_0 + dsc_bypass_h2c_0 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_0 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_0 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_0 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_0 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_0 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_0 + + + + + + + false + + + + + + dsc_bypass_h2c_1 + dsc_bypass_h2c_1 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_1 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_1 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_1 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_1 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_1 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_1 + + + + + + + false + + + + + + dsc_bypass_h2c_2 + dsc_bypass_h2c_2 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_2 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_2 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_2 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_2 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_2 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_2 + + + + + + + false + + + + + + dsc_bypass_h2c_3 + dsc_bypass_h2c_3 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_3 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_3 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_3 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_3 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_3 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_3 + + + + + + + false + + + + + + dma_status_ports + dma_status_ports + XDMA Status Ports Interface + + + + + + + c2h_sts0 + + + c2h_sts_0 + + + + + c2h_sts1 + + + c2h_sts_1 + + + + + c2h_sts2 + + + c2h_sts_2 + + + + + c2h_sts3 + + + c2h_sts_3 + + + + + h2c_sts0 + + + h2c_sts_0 + + + + + h2c_sts1 + + + h2c_sts_1 + + + + + h2c_sts2 + + + h2c_sts_2 + + + + + h2c_sts3 + + + h2c_sts_3 + + + + + + + false + + + + + + cap + cap + + + + + + + GNT + + + cap_gnt + + + + + REL + + + cap_rel + + + + + REQ + + + cap_req + + + + + + + false + + + + + + startup + startup + STARTUP Interface + + + + + + + cfgclk + + + startup_cfgclk + + + + + cfgmclk + + + startup_cfgmclk + + + + + di + + + startup_di + + + + + do + + + startup_do + + + + + dts + + + startup_dts + + + + + eos + + + startup_eos + + + + + fcsbo + + + startup_fcsbo + + + + + fcsbts + + + startup_fcsbts + + + + + gsr + + + startup_gsr + + + + + gts + + + startup_gts + + + + + keyclearb + + + startup_keyclearb + + + + + pack + + + startup_pack + + + + + preq + + + startup_preq + + + + + userdoneo + + + startup_usrdoneo + + + + + usrcclko + + + startup_usrcclko + + + + + usrclkts + + + startup_usrcclkts + + + + + usrdonets + + + startup_usrdonets + + + + + + + false + + + + + + atspri_s_axis_rq + atspri_s_axis_rq + The Requestor Request interface received requests TLP's from the Client Application + + + + + + + TDATA + + + atspri_s_axis_rq_tdata + + + + + TKEEP + + + atspri_s_axis_rq_tkeep + + + + + TLAST + + + atspri_s_axis_rq_tlast + + + + + TREADY + + + atspri_s_axis_rq_tready + + + + + TUSER + + + atspri_s_axis_rq_tuser + + + + + TVALID + + + atspri_s_axis_rq_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + atspri_m_axis_cq + atspri_m_axis_cq + The Completer Request interface is used to transmit Completion TLP's to the Client Application + + + + + + + TDATA + + + atspri_m_axis_cq_tdata + + + + + TKEEP + + + atspri_m_axis_cq_tkeep + + + + + TLAST + + + atspri_m_axis_cq_tlast + + + + + TREADY + + + atspri_m_axis_cq_tready + + + + + TUSER + + + atspri_m_axis_cq_tuser + + + + + TVALID + + + atspri_m_axis_cq_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + cfg_status_ats + cfg_status_ats + Configuration Status Interface For ATS + + + + + + + cfg_status_ats_en + + + cfg_status_ats_en + + + + + cfg_status_ats_stu + + + cfg_status_ats_stu + + + + + + + false + + + + + + cfg_status_pri + cfg_status_pri + Configuration Status Interface For PRI + + + + + + + cfg_status_clr_s + + + cfg_status_clr_s + + + + + cfg_status_ost_pr_alloc + + + cfg_status_ost_pr_alloc + + + + + cfg_status_pr_en + + + cfg_status_pr_en + + + + + cfg_status_pr_rf + + + cfg_status_pr_rf + + + + + cfg_status_pr_rst + + + cfg_status_pr_rst + + + + + cfg_status_pr_uprgi + + + cfg_status_pr_uprgi + + + + + cfg_status_set_rf + + + cfg_status_set_rf + + + + + cfg_status_set_s + + + cfg_status_set_s + + + + + cfg_status_set_uprgi + + + cfg_status_set_uprgi + + + + + + + false + + + + + + dma_debug_ports + XDMA Debug Ports + + + + + + + cc_tdata_out + + + m_axis_cc_tdata_out + + + + + cc_tkeep_out + + + m_axis_cc_tkeep_out + + + + + cc_tlast_out + + + m_axis_cc_tlast_out + + + + + cc_tready_out + + + m_axis_cc_tready_out + + + + + cc_tuser_out + + + m_axis_cc_tuser_out + + + + + cc_tvalid_out + + + m_axis_cc_tvalid_out + + + + + cq_tdata_out + + + s_axis_cq_tdata_out + + + + + cq_tkeep_out + + + s_axis_cq_tkeep_out + + + + + cq_tlast_out + + + s_axis_cq_tlast_out + + + + + cq_tready_out + + + s_axis_cq_tready_out + + + + + cq_tuser_out + + + s_axis_cq_tuser_out + + + + + cq_tvalid_out + + + s_axis_cq_tvalid_out + + + + + rc_tdata_out + + + s_axis_rc_tdata_out + + + + + rc_tkeep_out + + + s_axis_rc_tkeep_out + + + + + rc_tlast_out + + + s_axis_rc_tlast_out + + + + + rc_tready_out + + + s_axis_rc_tready_out + + + + + rc_tuser_out + + + s_axis_rc_tuser_out + + + + + rc_tvalid_out + + + s_axis_rc_tvalid_out + + + + + rq_tdata_out + + + m_axis_rq_tdata_out + + + + + rq_tkeep_out + + + m_axis_rq_tkeep_out + + + + + rq_tlast_out + + + m_axis_rq_tlast_out + + + + + rq_tready_out + + + m_axis_rq_tready_out + + + + + rq_tuser_out + + + m_axis_rq_tuser_out + + + + + rq_tvalid_out + + + m_axis_rq_tvalid_out + + + + + + + false + + + + + + pcie3_us_ext_shared_logic + pcie3_us_ext_shared_logic + PCIE3 Ultrascale External Shared Logic Interface + + + + + + + exts_qpll1lock_out + + + ext_qpll1lock_out + + + + + exts_qpll1outclk_out + + + ext_qpll1outclk_out + + + + + exts_qpll1outrefclk_out + + + ext_qpll1outrefclk_out + + + + + exts_qpll1pd + + + ext_qpll1pd + + + + + exts_qpll1rate + + + ext_qpll1rate + + + + + exts_qpll1refclk + + + ext_qpll1refclk + + + + + exts_qpll1reset + + + ext_qpll1reset + + + + + + + false + + + + + + pcie3_us_int_shared_logic + pcie3_us_int_shared_logic + PCIE3 Ultrascale Internal Shared Logic Interface + + + + + + + ints_qpll1lock_out + + + int_qpll1lock_out + + + + + ints_qpll1outclk_out + + + int_qpll1outclk_out + + + + + ints_qpll1outrefclk_out + + + int_qpll1outrefclk_out + + + + + + + true + + + + + + pcie4_usp_ext_gtcom + pcie4_usp_ext_gtcommon + PCIE4 Ultrascale+ External GT COMMON Interface + + + + + + + exts_qpll0lock_out + + + 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C_AXIBAR_1 + 0x0000000000000000 + + + C_AXIBAR_2 + 0x0000000000000000 + + + C_AXIBAR_3 + 0x0000000000000000 + + + C_AXIBAR_4 + 0x0000000000000000 + + + C_AXIBAR_5 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_0 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_1 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_2 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_3 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_4 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_5 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_0 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_1 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_2 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_3 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_4 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_5 + 0x0000000000000000 + + + EN_AXI_SLAVE_IF + Enable AXI Slave IF + TRUE + + + C_INCLUDE_BAROFFSET_REG + 1 + + + C_BASEADDR + 0x00001000 + + + C_HIGHADDR + 0x00001FFF + + + C_S_AXI_ID_WIDTH + 4 + + + C_S_AXI_NUM_READ + AXI Address width + 8 + + + C_M_AXI_NUM_READ + AXI Address width + 8 + + + C_S_AXI_NUM_WRITE + AXI Address width + 8 + + + C_M_AXI_NUM_WRITE + AXI Address width + 16 + + + MSIX_IMPL_EXT + FALSE + + + AXI_ACLK_LOOPBACK + FALSE + + + PF0_BAR0_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x0A + + + PF0_BAR0_CONTROL + Pf0 Bar0 Control + 0x4 + + + PF0_BAR1_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x05 + + + PF0_BAR1_CONTROL + Pf0 Bar1 Control + 0x0 + + + PF0_BAR2_APERTURE_SIZE + Pf0 Bar2 Aperture Size + 0x05 + + + PF0_BAR2_CONTROL + Pf0 Bar2 Control + 0x0 + + + PF0_BAR3_APERTURE_SIZE + Pf0 Bar3 Aperture Size + 0x05 + + + PF0_BAR3_CONTROL + Pf0 Bar3 Control + 0x0 + + + PF0_BAR4_APERTURE_SIZE + Pf0 Bar4 Aperture Size + 0x05 + + + PF0_BAR4_CONTROL + Pf0 Bar4 Control + 0x0 + + + PF0_BAR5_APERTURE_SIZE + Pf0 Bar5 Aperture Size + 0x05 + + + PF0_BAR5_CONTROL + Pf0 Bar5 Control + 0x0 + + + PCIEBAR_NUM + 6 + + + C_PCIEBAR2AXIBAR_0 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_1 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_2 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_3 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_4 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_5 + 0x0000000000000000 + + + BARLITE1 + 0 + + + BARLITE2 + 7 + + + VCU118_BOARD + FALSE + + + SPLIT_DMA + FALSE + + + PIPE_LINE_STAGE + 2 + + + AXIS_PIPE_LINE_STAGE + 0 + + + MULT_PF_DES + FALSE + + + RUNBIT_FIX + FALSE + + + xlnx_ref_board + None + + + GTWIZ_IN_CORE + 1 + + + GTCOM_IN_CORE + 2 + + + INS_LOSS_PROFILE + Add-in_Card + + + FUNC_MODE + 1 + + + PF1_ENABLED + 0 + + + DMA_RESET_SOURCE_SEL + 0 + + + PF1_BAR0_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x12 + + + PF1_BAR0_CONTROL + Pf0 Bar0 Control + 0x4 + + + PF1_BAR1_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x0A + + + PF1_BAR1_CONTROL + Pf0 Bar1 Control + 0x0 + + + PF1_BAR2_APERTURE_SIZE + Pf0 Bar2 Aperture Size + 0x0A + + + PF1_BAR2_CONTROL + Pf0 Bar2 Control + 0x6 + + + PF1_BAR3_APERTURE_SIZE + Pf0 Bar3 Aperture Size + 0x0A + + + PF1_BAR3_CONTROL + Pf0 Bar3 Control + 0x0 + + + PF1_BAR4_APERTURE_SIZE + Pf0 Bar4 Aperture Size + 0x0A + + + PF1_BAR4_CONTROL + Pf0 Bar4 Control + 0x6 + + + PF1_BAR5_APERTURE_SIZE + Pf0 Bar5 Aperture Size + 0x0A + + + PF1_BAR5_CONTROL + Pf0 Bar5 Control + 0x0 + + + PF1_PCIEBAR2AXIBAR_0 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_1 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_2 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_3 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_4 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_5 + 0x0000000000000000 + + + C_MSIX_INT_TABLE_EN + 0 + + + VU9P_TUL_EX + VU9P TUL board + FALSE + + + PCIE_BLK_TYPE + 0 + + + CCIX_ENABLE + Ccix Enable + FALSE + + + CCIX_DVSEC + Ccix Dvsec Enable + FALSE + + + EXT_SYS_CLK_BUFG + FALSE + + + C_NUM_OF_SC + 1 + + + USR_IRQ_EXDES + FALSE + + + AXI_VIP_IN_EXDES + FALSE + + + PIPE_DEBUG_EN + FALSE + + + XDMA_NON_INCREMENTAL_EXDES + FALSE + + + XDMA_ST_INFINITE_DESC_EXDES + FALSE + + + EXT_XVC_VSEC_ENABLE + Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design + FALSE + + + ACS_EXT_CAP_ENABLE + FALSE + + + EN_PCIE_DEBUG_PORTS + FALSE + + + MULTQ_EN + 0 + + + DMA_MM + 0 + + + DMA_ST + 1 + + + C_PCIE_PFS_SUPPORTED + 0 + + + C_SRIOV_EN + 0 + + + BARLITE_EXT_PF0 + 0x00 + + + BARLITE_EXT_PF1 + 0x00 + + + BARLITE_EXT_PF2 + 0x00 + + + BARLITE_EXT_PF3 + 0x00 + + + BARLITE_INT_PF0 + 0x01 + + + BARLITE_INT_PF1 + 0x00 + + + BARLITE_INT_PF2 + 0x00 + + + BARLITE_INT_PF3 + 0x00 + + + NUM_VFS_PF0 + 0 + + + NUM_VFS_PF1 + 0 + + + NUM_VFS_PF2 + 0 + + + NUM_VFS_PF3 + 0 + + + FIRSTVF_OFFSET_PF0 + 0 + + + FIRSTVF_OFFSET_PF1 + 0 + + + FIRSTVF_OFFSET_PF2 + 0 + + + FIRSTVF_OFFSET_PF3 + 0 + + + VF_BARLITE_EXT_PF0 + 0x00 + + + VF_BARLITE_EXT_PF1 + 0x00 + + + VF_BARLITE_EXT_PF2 + 0x00 + + + VF_BARLITE_EXT_PF3 + 0x00 + + + VF_BARLITE_INT_PF0 + 0x01 + + + VF_BARLITE_INT_PF1 + 0x01 + + + VF_BARLITE_INT_PF2 + 0x01 + + + VF_BARLITE_INT_PF3 + 0x01 + + + C_C2H_NUM_CHNL + 1 + + + C_H2C_NUM_CHNL + 1 + + + H2C_XDMA_CHNL + 0x0F + + + C2H_XDMA_CHNL + 0x0F + + + AXISTEN_IF_ENABLE_MSG_ROUTE + 0x00000 + + + ENABLE_MORE + FALSE + + + DISABLE_BRAM_PIPELINE + FALSE + + + DISABLE_EQ_SYNCHRONIZER + FALSE + + + C_ENABLE_RESOURCE_REDUCTION + FALSE + + + GEN4_EIEOS_0S7 + TRUE + + + C_S_AXI_SUPPORTS_NARROW_BURST + 0 + + + ENABLE_ATS_SWITCH + ATS Switch Enable + FALSE + + + C_ATS_SWITCH_UNIQUE_BDF + 1 + + + C_LAST_CORE_CAP_ADDR + 0x100 + + + C_VSEC_CAP_ADDR + 0x128 + + + SOFT_RESET_EN + FALSE + + + INTERRUPT_OUT_WIDTH + 1 + + + C_MSI_RX_PIN_EN + 0 + + + C_INTX_RX_PIN_EN + 1 + + + PCIE_ID_IF + FALSE + + + TL_PF_ENABLE_REG + 0 + + + AXSIZE_BYTE_ACCESS_EN + FALSE + + + + + + choice_list_08bf412c + 128 + 256 + 512 + + + choice_list_0be33969 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + + + choice_list_0f93492c + Chip-to-Chip + Add-in_Card + Backplane + + + choice_list_110bd32e + 2 + 4 + + + choice_list_16d2adcc + GTH_Quad_225 + GTH_Quad_224 + + + choice_list_1cfc6134 + 1 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_24b724fb + Basic + Advanced + + + choice_list_2a501329 + None + Tandem + Tandem_with_Field_Updates + PR_over_PCIe + + + choice_list_2dba17cd + None + Check_Parity + Propagate_Parity + + + choice_list_34d65ff4 + 128 + + + choice_list_35d06715 + 2 + + + choice_list_38306dd1 + SOFT + HARD + + + choice_list_3ca2cbc7 + BAR_0 + + + choice_list_3cee6ea1 + 16450_compatible_serial_controller + 16550_compatible_serial_controller + 16650_compatible_serial_controller + 16750_compatible_serial_controller + 16850_compatible_serial_controller + 16950_compatible_serial_controller + Bi_directional_parallel_port + ECP_1.X_compliant_parallel_port + GPIB(IEEE_488.1/2)_controller + Generic_XT_compatible_serial_controller + Generic_modem + Hayes_compatible_modem_with_16450_compatible_interface + Hayes_compatible_modem_with_16550_compatible_interface + Hayes_compatible_modem_with_16650_compatible_interface + Hayes_compatible_modem_with_16750_compatible_interface + IEEE_1284_controller + IEEE_1284_target_device + Multiport_serial_controller + Other_communications_device + Parallel_port + Smart_Card + + + choice_list_4665eb01 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_list_47140c0d + 0000 + 0001 + + + choice_list_4e419c85 + Default + Falling_Edge + + + choice_list_52d29139 + Bytes + Kilobytes + Megabytes + Gigabytes + + + choice_list_55451da8 + X1 + X2 + X4 + X8 + + + choice_list_574f38f3 + 2.5_GT/s + 5.0_GT/s + 8.0_GT/s + + + choice_list_57749bc8 + DMA + + + choice_list_589df8e9 + RAM + Other_memory_controller + Flash + + + choice_list_5e150e6c + 50us + 50ms + + + choice_list_5e2921cd + Kilobytes + + + choice_list_5e45706a + 1_vector + 2_vectors + 4_vectors + 8_vectors + 16_vectors + 32_vectors + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_6a0870a7 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + 30 + 31 + + + choice_list_6b979ebc + 250 + + + choice_list_6eff49bd + ACTIVE_LOW + ACTIVE_HIGH + + + choice_list_7a7dde49 + true + false + + + choice_list_8112d406 + 8 + 16 + 32 + + + choice_list_86c5d341 + 500 + + + choice_list_88156f2e + QPLL1 + QPLL0 + + + choice_list_8a9e69a3 + AXI_Lite_Master + DMA + + + choice_list_8aad6ae4 + 1 + 2 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_8b5e4915 + 4 + 5 + + + choice_list_914704bd + 100_MHz + 125_MHz + + + choice_list_91b49d0b + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + + + choice_list_97bc19ec + 256_bit + + + choice_list_993a8980 + Wireless_controller + Satellite_communication_controllers + Data_acquisition_and_signal_processing_controllers + Intelligent_I/O_controllers + Docking_stations + Device_was_built_before_Class_Code_definitions_were_finalized + Memory_controller + Simple_communication_controllers + Serial_bus_controllers + Encryption/Decryption_controllers + Display_controller + Multimedia_device + Input_devices + Mass_storage_controller + Processors + Device_does_not_fit_in_any_defined_classes + Bridge_device + Network_controller + Base_system_peripherals + + + choice_list_9aec9108 + Internal + External + + + choice_list_9e15bd51 + CONSTANT + + + choice_list_9f5580fd + Pre-Production + + + choice_list_a71f3969 + AXI_Memory_Mapped + AXI_Stream + + + choice_list_aa031417 + 1 + 2 + 3 + 4 + + + choice_list_ab8591cd + PCI_Express_Endpoint_device + PCI_Express_Endpoint_device + + + choice_list_ac75ef1e + Custom + + + choice_list_ae9f88f6 + 1 + + + choice_list_b0ffef10 + 0 + 1 + 2 + 3 + 4 + 5 + 7 + + + choice_list_bdd7203f + True + False + + + choice_list_be0f0e98 + X0Y0 + X0Y1 + X0Y2 + X0Y3 + + + choice_list_bea500ca + None + MSI-X_External + MSI-X_Internal + MSI-X_AXI4-Stream + + + choice_list_c0448d62 + None + VCU117 + VCU119 + ZCU117 + KCU116 + VCU1262 + VCU1299 + VCU1525 + KC705 + KCU1500 + XIL-ACCEL-RD-VU9P + XIL-ACCEL-RD-KU115 + VCU1550 + XBB1551 + + + choice_list_c15e8c67 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_c3d223d9 + Memory + + + choice_list_c63ab5b1 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + choice_list_ca005b72 + No_ASPM + L1_Supported + + + choice_list_ca108395 + 2 + 4 + 8 + 16 + 32 + + + choice_list_d123c74c + Bytes + Kilobytes + Megabytes + + + choice_list_d1e1a340 + Kilobytes + Megabytes + Gigabytes + + + choice_list_d4378f0e + Simple_communication_controllers + Device_was_built_before_Class_Code_definitions_were_finalized + Mass_storage_controller + Network_controller + Display_controller + Multimedia_device + Memory_controller + Base_system_peripherals + Input_devices + Docking_stations + Processors + Serial_bus_controllers + Wireless_controller + Intelligent_I/O_controllers + Satellite_communication_controllers + + + choice_list_d53faa96 + 100_MHz + 125_MHz + 250_MHz + + + choice_list_d85ad257 + 0 + + + choice_list_df7cde9e + RAM + Flash + Other_memory_controller + + + choice_list_e7c484ae + TRUE + FALSE + + + choice_list_e7f13338 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_e9cf6440 + Disabled + 32bit_Enabled + 64bit_Enabled + + + choice_list_ec64e624 + N/A + + + choice_list_f1174048 + NONE + INTA + INTB + INTC + INTD + + + choice_list_f94ec5c4 + 4 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_fab783d7 + User_Reset + Phy_Ready + + + choice_list_fc3456a9 + Disabled + Enabled + + + choice_list_fe1fb7c4 + 0 + 4 + 8 + 12 + 16 + + + choice_pairs_3c87fcdb + 1 + 0 + + + choice_pairs_3f7a0c72 + BAR_0 + 0 + BAR_1 + 1 + BAR_2 + 2 + + + choice_pairs_53749dec + 1 + 0 + + + choice_pairs_6f00a734 + 0 + 1 + 2 + + + + + xilinx_elaboratesubcores_view_fileset + + ip_0/xdma_pcie3_ip.xci + xci + + + ip_0/xdma_pcie3_ip.xml + xml + + + ip_1/xdma_v4_1_1_blk_mem_64_reg_be.xci + xci + + + ip_1/xdma_v4_1_1_blk_mem_64_reg_be.xml + xml + + + ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xci + xci + + + ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xml + xml + + + + The Xilinx PCI Express DMA + + + Component_Name + xdma + + + + true + + + + + + functional_mode + Functional Mode + DMA + + + + true + + + + + + mode_selection + Mode + Basic + + + + true + + + + + + device_port_type + Device Port Type + PCI_Express_Endpoint_device + + + + false + + + + + + pcie_blk_locn + Pcie Blk Locn + X0Y0 + + + + true + + + + + + pl_link_cap_max_link_width + Pl Link Cap Max Link Width + X8 + + + + true + + + + + + pl_link_cap_max_link_speed + Pl Link Cap Max Link Speed + 8.0_GT/s + + + + true + + + + + + ref_clk_freq + 100_MHz + + + + true + + + + + + drp_clk_sel + Internal + + + + false + + + + + + free_run_freq + 100_MHz + + + + true + + + + + + axi_addr_width + AXI Address width + 64 + + + + false + + + + + + axi_data_width + AXI Data width + 256_bit + + + + true + + + + + + axisten_freq + AXIsten if freq + 250 + + + + true + + + + + + en_axi_slave_if + Enable AXI Slave Interface + true + + + + true + + + + + + en_axi_master_if + Enable AXI Master Interface + true + + + + true + + + + + + pipe_sim + false + + + + true + + + + + + en_ext_ch_gt_drp + false + + + + true + + + + + + en_pcie_drp + false + + + + true + + + + + + dedicate_perst + true + + + + true + + + + + + sys_reset_polarity + ACTIVE_LOW + + + + true + + + + + + mcap_enablement + MCAP Enable + None + + + ext_startup_primitive + false + + + + false + + + + + + enable_code + 0000 + + + vendor_id + Vendor Id + 10EE + + + + true + + + + + + pf0_device_id + PF0 Device Id + 8038 + + + + true + + + + + + pf0_revision_id + PF0 Revision Id + 00 + + + + true + + + + + + pf0_subsystem_vendor_id + PF0 Subsystem Vendor Id + 10EE + + + + true + + + + + + pf0_subsystem_id + PF0 Subsystem Id + 0007 + + + + true + + + + + + pf0_Use_Class_Code_Lookup_Assistant + false + + + + true + + + + + + pf0_base_class_menu + Pf0 Base Class Menu + Simple_communication_controllers + + + + true + + + + + + pf0_class_code_base + Pf0 Class Code Base + 07 + + + + true + + + + + + pf0_sub_class_interface_menu + Pf0 Sub Class Interface Menu + 16450_compatible_serial_controller + + + + true + + + + + + pf0_class_code_sub + pf0 Class Code Sub + 00 + + + + true + + + + + + pf0_class_code_interface + pf0 Class Code Interface + 01 + + + + true + + + + + + pf0_class_code + pf0 Class Code + 070001 + + + + false + + + + + + axilite_master_en + false + + + + true + + + + + + axilite_master_size + 1 + + + + false + + + + + + axilite_master_scale + Megabytes + + + + false + + + + + + xdma_en + true + + + + false + + + + + + xdma_size + 64 + + + + false + + + + + + xdma_scale + Kilobytes + + + + false + + + + + + axist_bypass_en + false + + + + true + + + + + + axist_bypass_size + 1 + + + + false + + + + + + axist_bypass_scale + Megabytes + + + + false + + + + + + pciebar2axibar_axil_master + 0x00000000 + + + + false + + + + + + pciebar2axibar_xdma + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_axist_bypass + 0x0000000000000000 + + + + false + + + + + + pf0_interrupt_pin + pf0 Interrupt Pin + INTA + + + + true + + + + + + pf0_msi_enabled + pf0 Msi Enabled + true + + + + true + + + + + + pf0_msi_cap_multimsgcap + pf0 Msi Cap Multimsgcap + 1_vector + + + + true + + + + + + comp_timeout + 50ms + + + + true + + + + + + timeout0_sel + 14 + + + + true + + + + + + timeout1_sel + 15 + + + + true + + + + + + timeout_mult + 3 + + + + true + + + + + + old_bridge_timeout + false + + + Shared_Logic + 1 + + + + true + + + + + + Shared_Logic_Clk + false + + + Shared_Logic_Both + false + + + Shared_Logic_Gtc + false + + + Shared_Logic_Gtc_7xG2 + false + + + Shared_Logic_Clk_7xG2 + false + + + Shared_Logic_Both_7xG2 + false + + + en_transceiver_status_ports + false + + + + true + + + + + + xdma_rnum_chnl + 1 + + + + true + + + + + + xdma_wnum_chnl + 1 + + + + true + + + + + + xdma_axilite_slave + false + + + + true + + + + + + xdma_num_usr_irq + 1 + + + + true + + + + + + xdma_rnum_rids + 32 + + + xdma_wnum_rids + 16 + + + SYS_RST_N_BOARD_INTERFACE + Custom + + + PCIE_BOARD_INTERFACE + Custom + + + en_gt_selection + false + + + select_quad + GTH_Quad_225 + + + + false + + + + + + RX_PPM_OFFSET + Specify the PPM offset between received data and transmitted data + 0 + + + RX_SSC_PPM + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 15 + + + PHY_LP_TXPRESET + Phy Lp Txpreset + 4 + + + coreclk_freq + CORE CLOCK FREQ + 500 + + + + false + + + + + + plltype + PLL TYPE + QPLL1 + + + xdma_axi_intf_mm + XDMA Interface + AXI_Stream + + + + true + + + + + + xdma_pcie_64bit_en + false + + + silicon_rev + Pre-Production + + + xdma_dsc_bypass + false + + + performance + false + + + pcie_extended_tag + true + + + rx_detect + Receiver Detect + Default + + + pf0_link_status_slot_clock_config + Pf0 Link Status Slot Clock Config + true + + + dsc_bypass_rd + 0000 + + + dsc_bypass_wr + 0000 + + + xdma_sts_ports + false + + + pf0_msix_enabled + Pf0 Msix Enabled + false + + + pf0_msix_cap_table_size + Pf0 Msix Cap Table Size + 000 + + + + false + + + + + + pf0_msix_cap_table_offset + Pf0 Msix Cap Table Offset + 00000000 + + + + false + + + + + + pf0_msix_cap_table_bir + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + pf0_msix_cap_pba_offset + Pf0 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + pf0_msix_cap_pba_bir + Pf0 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + pf1_msix_enabled + Pf1 Msix Enabled + false + + + pf1_msix_cap_table_size + Pf1 Msix Cap Table Size + 020 + + + pf1_msix_cap_table_offset + Pf1 Msix Cap Table Offset + 00009000 + + + pf1_msix_cap_table_bir + Pf1 Msix Cap Table Bir + BAR_0 + + + pf1_msix_cap_pba_offset + Pf1 Msix Cap Pba Offset + 00009FE0 + + + pf1_msix_cap_pba_bir + Pf1 Msix Cap Pba Bir + BAR_0 + + + cfg_mgmt_if + true + + + + true + + + + + + ins_loss_profile + Add-in_Card + + + axil_master_64bit_en + false + + + + false + + + + + + axi_bypass_64bit_en + false + + + + false + + + + + + axil_master_prefetchable + false + + + + false + + + + + + xdma_pcie_prefetchable + false + + + + false + + + + + + axi_bypass_prefetchable + false + + + + false + + + + + + cfg_ext_if + false + + + legacy_cfg_ext_if + false + + + + false + + + + + + parity_settings + None + + + + true + + + + + + ecc_en + false + + + + true + + + + + + en_debug_ports + false + + + axi_id_width + 4 + + + + true + + + + + + vu9p_board + false + + + type1_membase_memlimit_enable + Type1 Config MemBase and MemLimit + Disabled + + + + false + + + + + + type1_prefetchable_membase_memlimit + Type1 Config Prefetchable MemBase and MemLimit + Disabled + + + + false + + + + + + enable_jtag_dbg + false + + + + true + + + + + + enable_ibert + false + + + + true + + + + + + axibar_num + 1 + + + + true + + + + + + axibar_0 + 0x0000000000000000 + + + + true + + + + + + axibar_1 + 0x0000000000000000 + + + + false + + + + + + axibar_2 + 0x0000000000000000 + + + + false + + + + + + axibar_3 + 0x0000000000000000 + + + + false + + + + + + axibar_4 + 0x0000000000000000 + + + + false + + + + + + axibar_5 + 0x0000000000000000 + + + + false + + + + + + axibar_highaddr_0 + 0x0000000000000000 + + + + true + + + + + + axibar_highaddr_1 + 0x0000000000000000 + + + + false + + + + + + axibar_highaddr_2 + 0x0000000000000000 + + + + false + + + + + + axibar_highaddr_3 + 0x0000000000000000 + + + + false + + + + + + axibar_highaddr_4 + 0x0000000000000000 + + + + false + + + + + + axibar_highaddr_5 + 0x0000000000000000 + + + + false + + + + + + axibar2pciebar_0 + 0x0000000000000000 + + + + true + + + + + + axibar2pciebar_1 + 0x0000000000000000 + + + + false + + + + + + axibar2pciebar_2 + 0x0000000000000000 + + + + false + + + + + + axibar2pciebar_3 + 0x0000000000000000 + + + + false + + + + + + axibar2pciebar_4 + 0x0000000000000000 + + + + false + + + + + + axibar2pciebar_5 + 0x0000000000000000 + + + + false + + + + + + include_baroffset_reg + true + + + + false + + + + + + BASEADDR + 0x00001000 + + + + true + + + + + + HIGHADDR + 0x00001FFF + + + + true + + + + + + s_axi_id_width + 4 + + + + true + + + + + + c_m_axi_num_write + AXI Master outstanding write Transactions Selection + 8 + + + + true + + + + + + c_m_axi_num_read + AXI Master outstanding read Transactions Selection + 8 + + + + false + + + + + + c_s_axi_num_write + AXI Slave outstanding write Transactions Selection + 8 + + + + false + + + + + + c_s_axi_num_read + AXI Slave outstanding read Transactions Selection + 8 + + + + false + + + + + + pf0_msix_impl_locn + Pf0 Msix Implementation Location + Internal + + + + false + + + + + + axi_aclk_loopback + false + + + pf0_bar0_enabled + Pf0 Bar0 Enabled + true + + + + true + + + + + + pf0_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf0_bar0_size + Pf0 Bar0 Size + 128 + + + + true + + + + + + pf0_bar0_scale + Pf0 Bar0 Scale + Kilobytes + + + + true + + + + + + pf0_bar0_64bit + Pf0 Bar0 64bit + false + + + + true + + + + + + pf0_bar0_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar1_enabled + Pf0 Bar0 Enabled + false + + + + true + + + + + + pf0_bar1_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf0_bar1_size + Pf0 Bar0 Size + 4 + + + + false + + + + + + pf0_bar1_scale + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf0_bar1_64bit + Pf0 Bar0 64bit + false + + + + false + + + + + + pf0_bar1_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar2_enabled + Pf0 Bar0 Enabled + false + + + + false + + + + + + pf0_bar2_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf0_bar2_size + Pf0 Bar0 Size + 4 + + + + false + + + + + + pf0_bar2_scale + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf0_bar2_64bit + Pf0 Bar0 64bit + false + + + + false + + + + + + pf0_bar2_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar3_enabled + Pf0 Bar0 Enabled + false + + + + false + + + + + + pf0_bar3_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf0_bar3_size + Pf0 Bar0 Size + 4 + + + + false + + + + + + pf0_bar3_scale + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf0_bar3_64bit + Pf0 Bar0 64bit + false + + + + false + + + + + + pf0_bar3_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar4_enabled + Pf0 Bar0 Enabled + false + + + + false + + + + + + pf0_bar4_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf0_bar4_size + Pf0 Bar0 Size + 4 + + + + false + + + + + + pf0_bar4_scale + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf0_bar4_64bit + Pf0 Bar0 64bit + false + + + + false + + + + + + pf0_bar4_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar5_enabled + Pf0 Bar0 Enabled + false + + + + false + + + + + + pf0_bar5_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf0_bar5_size + Pf0 Bar0 Size + 4 + + + + false + + + + + + pf0_bar5_scale + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf0_bar5_64bit + Pf0 Bar0 64bit + false + + + + false + + + + + + pf0_bar5_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + bar_indicator + BAR_0 + + + + false + + + + + + bar0_indicator + 1 + + + + true + + + + + + bar1_indicator + 0 + + + + true + + + + + + bar2_indicator + 0 + + + + true + + + + + + bar3_indicator + 0 + + + + true + + + + + + bar4_indicator + 0 + + + + true + + + + + + bar5_indicator + 0 + + + + true + + + + + + barlite2 + 7 + + + en_dbg_descramble + false + + + vcu118_board + false + + + tl_pf_enable_reg + NUM PF Enable + 1 + + + pf1_vendor_id + Vendor Id + 10EE + + + pf1_device_id + PF1 Device Id + 1041 + + + pf1_class_code + Pf1 Class Code + 070001 + + + + false + + + + + + PF1_REVISION_ID + Pf1 Revision Id + 00 + + + PF1_SUBSYSTEM_VENDOR_ID + Pf1 Subsystem Vendor Id + 10EE + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0007 + + + PF1_Use_Class_Code_Lookup_Assistant + false + + + + true + + + + + + pf1_base_class_menu + Pf1 Base Class Menu + Simple_communication_controllers + + + pf1_class_code_base + Pf1 Class Code Base + 07 + + + + true + + + + + + pf1_class_code_sub + Pf1 Class Code Sub + 00 + + + + true + + + + + + pf1_sub_class_interface_menu + Pf1 Sub Class Interface Menu + 16450_compatible_serial_controller + + + + true + + + + + + pf1_class_code_interface + Pf1 Class Code Interface + 01 + + + + true + + + + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + NONE + + + pf1_msi_enabled + Pf1 Msi Enabled + false + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 1_vector + + + pf1_bar0_enabled + Pf1 Bar0 Enabled + true + + + pf1_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar0_size + Pf1 Bar0 Size + 32 + + + pf1_bar0_scale + Pf1 Bar0 Scale + Megabytes + + + pf1_bar0_64bit + Pf1 Bar0 64bit + false + + + pf1_bar0_prefetchable + Pf1 Bar0 Prefetchable + false + + + pf1_bar1_enabled + Pf1 Bar1 Enabled + true + + + pf1_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar1_size + Pf1 Bar1 Size + 128 + + + pf1_bar1_scale + Pf1 Bar1 Scale + Kilobytes + + + pf1_bar1_64bit + Pf1 Bar1 64bit + false + + + pf1_bar1_prefetchable + Pf1 Bar1 Prefetchable + false + + + pf1_bar2_enabled + Pf1 Bar2 Enabled + true + + + pf1_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar2_size + Pf1 Bar2 Size + 128 + + + pf1_bar2_scale + Pf1 Bar2 Scale + Kilobytes + + + pf1_bar2_64bit + Pf1 Bar2 64bit + true + + + pf1_bar2_prefetchable + Pf1 Bar2 Prefetchable + false + + + pf1_bar3_enabled + Pf1 Bar3 Enabled + false + + + + false + + + + + + pf1_bar3_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf1_bar3_size + Pf1 Bar3 Size + 128 + + + + false + + + + + + pf1_bar3_scale + Pf1 Bar3 Scale + Kilobytes + + + + false + + + + + + pf1_bar3_64bit + Pf1 Bar3 64bit + false + + + pf1_bar3_prefetchable + Pf1 Bar3 Prefetchable + false + + + + false + + + + + + pf1_bar4_enabled + Pf1 Bar4 Enabled + true + + + pf1_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar4_size + Pf1 Bar4 Size + 128 + + + pf1_bar4_scale + Pf1 Bar4 Scale + Kilobytes + + + pf1_bar4_64bit + Pf1 Bar4 64bit + true + + + pf1_bar4_prefetchable + Pf1 Bar4 Prefetchable + false + + + pf1_bar5_enabled + Pf1 Bar5 Enabled + false + + + + false + + + + + + pf1_bar5_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf1_bar5_size + Pf1 Bar5 Size + 128 + + + + false + + + + + + pf1_bar5_scale + Pf1 Bar5 Scale + Kilobytes + + + + false + + + + + + pf1_bar5_prefetchable + Pf1 Bar5 Prefetchable + false + + + + false + + + + + + pf2_device_id + PF2 Device Id + 1040 + + + pf2_class_code + pf2 Class Code + 058000 + + + PF2_REVISION_ID + pf2 Revision Id + 00 + + + PF2_SUBSYSTEM_VENDOR_ID + pf2 Subsystem Vendor Id + 10EE + + + PF2_SUBSYSTEM_ID + pf2 Subsystem Id + 0007 + + + PF2_Use_Class_Code_Lookup_Assistant + false + + + pf2_base_class_menu + pf2 Base Class Menu + Memory_controller + + + pf2_class_code_base + pf2 Class Code Base + 05 + + + pf2_class_code_sub + pf2 Class Code Sub + 80 + + + pf2_sub_class_interface_menu + pf2 Sub Class Interface Menu + Other_memory_controller + + + pf2_class_code_interface + pf2 Class Code Interface + 00 + + + PF2_INTERRUPT_PIN + pf2 Interrupt Pin + NONE + + + pf2_msi_enabled + pf2 Msi Enabled + false + + + PF2_MSI_CAP_MULTIMSGCAP + pf2 Msi Cap Multimsgcap + 1_vector + + + pf2_bar0_enabled + pf2 Bar0 Enabled + true + + + pf2_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar0_size + pf2 Bar0 Size + 128 + + + pf2_bar0_scale + pf2 Bar0 Scale + Kilobytes + + + pf2_bar0_64bit + pf2 Bar0 64bit + false + + + pf2_bar0_prefetchable + pf2 Bar0 Prefetchable + false + + + pf2_bar1_enabled + pf2 Bar1 Enabled + true + + + pf2_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar1_size + pf2 Bar1 Size + 128 + + + pf2_bar1_scale + pf2 Bar1 Scale + Kilobytes + + + pf2_bar1_64bit + pf2 Bar1 64bit + false + + + pf2_bar1_prefetchable + pf2 Bar1 Prefetchable + false + + + pf2_bar2_enabled + pf2 Bar2 Enabled + true + + + pf2_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar2_size + pf2 Bar2 Size + 128 + + + pf2_bar2_scale + pf2 Bar2 Scale + Kilobytes + + + pf2_bar2_64bit + pf2 Bar2 64bit + false + + + pf2_bar2_prefetchable + pf2 Bar2 Prefetchable + false + + + pf2_bar3_enabled + pf2 Bar3 Enabled + true + + + pf2_bar3_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar3_size + pf2 Bar3 Size + 128 + + + pf2_bar3_scale + pf2 Bar3 Scale + Kilobytes + + + pf2_bar3_64bit + pf2 Bar3 64bit + false + + + pf2_bar3_prefetchable + pf2 Bar3 Prefetchable + false + + + pf2_bar4_enabled + pf2 Bar4 Enabled + true + + + pf2_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar4_size + pf2 Bar4 Size + 128 + + + pf2_bar4_scale + pf2 Bar4 Scale + Kilobytes + + + pf2_bar4_64bit + pf2 Bar4 64bit + false + + + pf2_bar4_prefetchable + pf2 Bar4 Prefetchable + false + + + pf2_bar5_enabled + pf2 Bar5 Enabled + true + + + pf2_bar5_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar5_size + pf2 Bar5 Size + 128 + + + pf2_bar5_scale + pf2 Bar5 Scale + Kilobytes + + + pf2_bar5_prefetchable + pf2 Bar5 Prefetchable + false + + + pf3_device_id + PF3 Device Id + 1039 + + + pf3_class_code + Pf3 Class Code + 058000 + + + PF3_REVISION_ID + Pf3 Revision Id + 00 + + + PF3_SUBSYSTEM_VENDOR_ID + Pf3 Subsystem Vendor Id + 10EE + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0007 + + + PF3_Use_Class_Code_Lookup_Assistant + false + + + pf3_base_class_menu + Pf3 Base Class Menu + Memory_controller + + + pf3_class_code_base + Pf3 Class Code Base + 05 + + + pf3_class_code_sub + Pf3 Class Code Sub + 80 + + + pf3_sub_class_interface_menu + Pf3 Sub Class Interface Menu + Other_memory_controller + + + pf3_class_code_interface + Pf3 Class Code Interface + 00 + + + PF3_INTERRUPT_PIN + Pf3 Interrupt Pin + NONE + + + pf3_msi_enabled + Pf3 Msi Enabled + false + + + PF3_MSI_CAP_MULTIMSGCAP + Pf3 Msi Cap Multimsgcap + 1_vector + + + pf3_bar0_enabled + Pf3 Bar0 Enabled + true + + + pf3_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar0_size + Pf3 Bar0 Size + 128 + + + pf3_bar0_scale + Pf3 Bar0 Scale + Kilobytes + + + pf3_bar0_64bit + Pf3 Bar0 64bit + false + + + pf3_bar0_prefetchable + Pf3 Bar0 Prefetchable + false + + + pf3_bar1_enabled + Pf3 Bar1 Enabled + true + + + pf3_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar1_size + Pf3 Bar1 Size + 128 + + + pf3_bar1_scale + Pf3 Bar1 Scale + Kilobytes + + + pf3_bar1_64bit + Pf3 Bar1 64bit + false + + + pf3_bar1_prefetchable + Pf3 Bar1 Prefetchable + false + + + pf3_bar2_enabled + Pf3 Bar2 Enabled + true + + + pf3_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar2_size + Pf3 Bar2 Size + 128 + + + pf3_bar2_scale + Pf3 Bar2 Scale + Kilobytes + + + pf3_bar2_64bit + Pf3 Bar2 64bit + false + + + pf3_bar2_prefetchable + Pf3 Bar2 Prefetchable + false + + + pf3_bar3_enabled + Pf3 Bar3 Enabled + true + + + pf3_bar3_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar3_size + Pf3 Bar3 Size + 128 + + + pf3_bar3_scale + Pf3 Bar3 Scale + Kilobytes + + + pf3_bar3_64bit + Pf3 Bar3 64bit + false + + + pf3_bar3_prefetchable + Pf3 Bar3 Prefetchable + false + + + pf3_bar4_enabled + Pf3 Bar4 Enabled + true + + + pf3_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar4_size + Pf3 Bar4 Size + 128 + + + pf3_bar4_scale + Pf3 Bar4 Scale + Kilobytes + + + pf3_bar4_64bit + Pf3 Bar4 64bit + false + + + pf3_bar4_prefetchable + Pf3 Bar4 Prefetchable + false + + + pf3_bar5_enabled + Pf3 Bar5 Enabled + true + + + pf3_bar5_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar5_size + Pf3 Bar5 Size + 128 + + + pf3_bar5_scale + Pf3 Bar5 Scale + Kilobytes + + + pf3_bar5_prefetchable + Pf3 Bar5 Prefetchable + false + + + split_dma + false + + + + false + + + + + + mult_pf_des + false + + + xlnx_ref_board + Xlnx Ref Board + None + + + + true + + + + + + en_l23_entry + false + + + pf1_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf1_pciebar2axibar_2 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf1_pciebar2axibar_4 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf2_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf3_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + gtwiz_in_core_us + 1 + + + gtwiz_in_core_usp + 1 + + + dma_reset_source_sel + User_Reset + + + en_dma_and_bridge + false + + + en_coreclk_es1 + false + + + pipe_line_stage + number of Pipe Line Stages + 2 + + + + false + + + + + + axis_pipe_line_stage + number of Pipe Line Stages on PCIe axis interface + 0 + + + + false + + + + + + vu9p_tul_ex + false + + + vcu1525_ddr_ex + false + + + en_bridge + false + + + enable_ccix + FALSE + + + enable_dvsec + FALSE + + + ext_sys_clk_bufg + false + + + usr_irq_exdes + false + + + axi_vip_in_exdes + false + + + xdma_non_incremental_exdes + false + + + xdma_st_infinite_desc_exdes + false + + + gtcom_in_core_usp + 2 + + + en_mqdma + false + + + SRIOV_CAP_ENABLE + false + + + + false + + + + + + ext_xvc_vsec_enable + Enable to add the PCIe XVC-VSEC to the Examlpe Design + false + + + + false + + + + + + acs_ext_cap_enable + ACS Ext Capability + false + + + pf0_bar0_enabled_mqdma + Pf0 Bar1 Enabled + true + + + pf0_bar0_type_mqdma + Pf0 Bar0 Type + DMA + + + pf0_bar0_64bit_mqdma + Pf0 Bar0 64bit + false + + + pf0_bar0_prefetchable_mqdma + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar0_scale_mqdma + Pf0 Bar0 Scale + Kilobytes + + + pf0_bar0_size_mqdma + Pf0 Bar0 Size + 128 + + + pf0_bar1_enabled_mqdma + Pf0 Bar1 Enabled + false + + + pf0_bar1_type_mqdma + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf0_bar1_64bit_mqdma + Pf0 Bar1 64bit + false + + + + false + + + + + + pf0_bar1_prefetchable_mqdma + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf0_bar1_scale_mqdma + Pf0 Bar1 Scale + Kilobytes + + + + false + + + + + + pf0_bar1_size_mqdma + Pf0 Bar1 Size + 128 + + + + false + + + + + + pf0_bar2_enabled_mqdma + Pf0 Bar2 Enabled + false + + + pf0_bar2_type_mqdma + Pf0 Bar2 Type + N/A + + + + false + + + + + + pf0_bar2_64bit_mqdma + Pf0 Bar2 64bit + false + + + + false + + + + + + pf0_bar2_prefetchable_mqdma + Pf0 Bar2 Prefetchable + false + + + + false + + + + + + pf0_bar2_scale_mqdma + Pf0 Bar2 Scale + Kilobytes + + + + false + + + + + + pf0_bar2_size_mqdma + Pf0 Bar2 Size + 128 + + + + false + + + + + + pf0_bar3_enabled_mqdma + Pf0 Bar3 Enabled + false + + + pf0_bar3_type_mqdma + Pf0 Bar3 Type + N/A + + + + false + + + + + + pf0_bar3_64bit_mqdma + Pf0 Bar3 64bit + false + + + + false + + + + + + pf0_bar3_prefetchable_mqdma + Pf0 Bar3 Prefetchable + false + + + + false + + + + + + pf0_bar3_scale_mqdma + Pf0 Bar3 Scale + Kilobytes + + + + false + + + + + + pf0_bar3_size_mqdma + Pf0 Bar3 Size + 128 + + + + false + + + + + + pf0_bar4_enabled_mqdma + Pf0 Bar4 Enabled + false + + + pf0_bar4_type_mqdma + Pf0 Bar4 Type + N/A + + + + false + + + + + + pf0_bar4_64bit_mqdma + Pf0 Bar4 64bit + false + + + + false + + + + + + pf0_bar4_prefetchable_mqdma + Pf0 Bar4 Prefetchable + false + + + + false + + + + + + pf0_bar4_scale_mqdma + Pf0 Bar4 Scale + Kilobytes + + + + false + + + + + + pf0_bar4_size_mqdma + Pf0 Bar4 Size + 128 + + + + false + + + + + + pf0_bar5_enabled_mqdma + Pf0 Bar5 Enabled + false + + + pf0_bar5_type_mqdma + Pf0 Bar5 Type + N/A + + + + false + + + + + + pf0_bar5_prefetchable_mqdma + Pf0 Bar5 Prefetchable + false + + + pf0_bar5_scale_mqdma + Pf0 Bar5 Scale + Kilobytes + + + + false + + + + + + pf0_bar5_size_mqdma + Pf0 Bar5 Size + 128 + + + + false + + + + + + pf1_bar0_enabled_mqdma + Pf0 Bar0 Enabled + true + + + + false + + + + + + pf1_bar0_type_mqdma + Pf0 Bar0 Type + DMA + + + + false + + + + + + pf1_bar0_64bit_mqdma + Pf0 Bar0 64bit + false + + + + false + + + + + + pf1_bar0_prefetchable_mqdma + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf1_bar0_scale_mqdma + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf1_bar0_size_mqdma + Pf0 Bar0 Size + 128 + + + + false + + + + + + pf1_bar1_enabled_mqdma + Pf0 Bar1 Enabled + false + + + + false + + + + + + pf1_bar1_type_mqdma + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf1_bar1_64bit_mqdma + Pf0 Bar1 64bit + false + + + + false + + + + + + pf1_bar1_prefetchable_mqdma + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf1_bar1_scale_mqdma + Pf0 Bar1 Scale + Kilobytes + + + + false + + + + + + pf1_bar1_size_mqdma + Pf0 Bar1 Size + 128 + + + + false + + + + + + pf1_bar2_enabled_mqdma + Pf0 Bar2 Enabled + false + + + + false + + + + + + pf1_bar2_type_mqdma + Pf0 Bar2 Type + N/A + + + + false + + + + + + pf1_bar2_64bit_mqdma + Pf0 Bar2 64bit + false + + + + false + + + + + + pf1_bar2_prefetchable_mqdma + Pf0 Bar2 Prefetchable + false + + + + false + + + + + + pf1_bar2_scale_mqdma + Pf0 Bar2 Scale + Kilobytes + + + + false + + + + + + pf1_bar2_size_mqdma + Pf0 Bar2 Size + 128 + + + + false + + + + + + pf1_bar3_enabled_mqdma + Pf0 Bar3 Enabled + false + + + + false + + + + + + pf1_bar3_type_mqdma + Pf0 Bar3 Type + N/A + + + + false + + + + + + pf1_bar3_64bit_mqdma + Pf0 Bar3 64bit + false + + + + false + + + + + + pf1_bar3_prefetchable_mqdma + Pf0 Bar3 Prefetchable + false + + + + false + + + + + + pf1_bar3_scale_mqdma + Pf0 Bar3 Scale + Kilobytes + + + + false + + + + + + pf1_bar3_size_mqdma + Pf0 Bar3 Size + 128 + + + + false + + + + + + pf1_bar4_enabled_mqdma + Pf0 Bar4 Enabled + false + + + + false + + + + + + pf1_bar4_type_mqdma + Pf0 Bar4 Type + N/A + + + + false + + + + + + pf1_bar4_64bit_mqdma + Pf0 Bar4 64bit + false + + + + false + + + + + + pf1_bar4_prefetchable_mqdma + Pf0 Bar4 Prefetchable + false + + + + false + + + + + + pf1_bar4_scale_mqdma + Pf0 Bar4 Scale + Kilobytes + + + + false + + + + + + pf1_bar4_size_mqdma + Pf0 Bar4 Size + 128 + + + + false + + + + + + pf1_bar5_enabled_mqdma + Pf0 Bar5 Enabled + false + + + + false + + + + + + pf1_bar5_type_mqdma + Pf0 Bar5 Type + N/A + + + + false + + + + + + pf1_bar5_prefetchable_mqdma + Pf0 Bar5 Prefetchable + false + + + pf1_bar5_scale_mqdma + Pf0 Bar5 Scale + Kilobytes + + + + false + + + + + + pf1_bar5_size_mqdma + Pf0 Bar5 Size + 128 + + + + false + + + + + + pf2_bar0_enabled_mqdma + Pf0 Bar0 Enabled + true + + + + false + + + + + + pf2_bar0_type_mqdma + Pf0 Bar0 Type + DMA + + + + false + + + + + + pf2_bar0_64bit_mqdma + Pf0 Bar0 64bit + false + + + + false + + + + + + pf2_bar0_prefetchable_mqdma + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf2_bar0_scale_mqdma + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf2_bar0_size_mqdma + Pf0 Bar0 Size + 128 + + + + false + + + + + + pf2_bar1_enabled_mqdma + Pf0 Bar1 Enabled + false + + + + false + + + + + + pf2_bar1_type_mqdma + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf2_bar1_64bit_mqdma + Pf0 Bar1 64bit + false + + + + false + + + + + + pf2_bar1_prefetchable_mqdma + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf2_bar1_scale_mqdma + Pf0 Bar1 Scale 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pf2_bar4_enabled_mqdma + Pf0 Bar4 Enabled + false + + + + false + + + + + + pf2_bar4_type_mqdma + Pf0 Bar4 Type + N/A + + + + false + + + + + + pf2_bar4_64bit_mqdma + Pf0 Bar4 64bit + false + + + + false + + + + + + pf2_bar4_prefetchable_mqdma + Pf0 Bar4 Prefetchable + false + + + + false + + + + + + pf2_bar4_scale_mqdma + Pf0 Bar4 Scale + Kilobytes + + + + false + + + + + + pf2_bar4_size_mqdma + Pf0 Bar4 Size + 128 + + + + false + + + + + + pf2_bar5_enabled_mqdma + Pf0 Bar5 Enabled + false + + + + false + + + + + + pf2_bar5_type_mqdma + Pf0 Bar5 Type + N/A + + + + false + + + + + + pf2_bar5_prefetchable_mqdma + Pf0 Bar5 Prefetchable + false + + + pf2_bar5_scale_mqdma + Pf0 Bar5 Scale + Kilobytes + + + + false + + + + + + pf2_bar5_size_mqdma + Pf0 Bar5 Size + 128 + + + + false + + + + + + pf3_bar0_enabled_mqdma + Pf0 Bar0 Enabled + true + + + + false + + + + + + pf3_bar0_type_mqdma + Pf0 Bar0 Type + DMA + + + + false + + + + + + pf3_bar0_64bit_mqdma + Pf0 Bar0 64bit + false + + + + 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pf1_expansion_rom_size_mqdma + Pf0 Expansion Rom Size + 2 + + + + false + + + + + + pf2_expansion_rom_type_mqdma + N/A + + + + false + + + + + + pf2_expansion_rom_enabled_mqdma + Pf0 Expansion Rom Enabled + false + + + pf2_expansion_rom_scale_mqdma + Pf0 Expansion Rom Scale + Kilobytes + + + + false + + + + + + pf2_expansion_rom_size_mqdma + Pf0 Expansion Rom Size + 2 + + + + false + + + + + + pf3_expansion_rom_type_mqdma + N/A + + + + false + + + + + + pf3_expansion_rom_enabled_mqdma + Pf0 Expansion Rom Enabled + false + + + pf3_expansion_rom_scale_mqdma + Pf0 Expansion Rom Scale + Kilobytes + + + + false + + + + + + pf3_expansion_rom_size_mqdma + Pf0 Expansion Rom Size + 2 + + + + false + + + + + + pf0_sriov_bar0_enabled + Pf0 Sriov Bar0 Enabled + true + + + pf0_sriov_bar0_type + Pf0 Sriov Bar0 Type + DMA + + + pf0_sriov_bar0_64bit + Pf0 Sriov Bar0 64bit + false + + + pf0_sriov_bar0_prefetchable + Pf0 Sriov Bar0 Prefetchable + false + + + + false + + + + + + pf0_sriov_bar0_size + Pf0 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pf1_vendor_id_mqdma + Vendor Id + 10EE + + + pf2_vendor_id_mqdma + Vendor Id + 10EE + + + pf3_vendor_id_mqdma + Vendor Id + 10EE + + + PF0_DEVICE_ID_mqdma + Pf2 Device Id + 9038 + + + PF1_DEVICE_ID_mqdma + Pf2 Device Id + 0007 + + + PF2_DEVICE_ID_mqdma + Pf2 Device Id + 9038 + + + PF3_DEVICE_ID_mqdma + Pf3 Device Id + 9038 + + + PF0_REVISION_ID_mqdma + Pf2 Revision Id + 00 + + + PF1_REVISION_ID_mqdma + Pf2 Revision Id + 00 + + + PF2_REVISION_ID_mqdma + Pf2 Revision Id + 00 + + + PF3_REVISION_ID_mqdma + Pf3 Revision Id + 00 + + + PF0_SUBSYSTEM_VENDOR_ID_mqdma + Pf2 Subsystem Vendor Id + 10EE + + + PF1_SUBSYSTEM_VENDOR_ID_mqdma + Pf2 Subsystem Vendor Id + 10EE + + + PF2_SUBSYSTEM_VENDOR_ID_mqdma + Pf2 Subsystem Vendor Id + 10EE + + + PF3_SUBSYSTEM_VENDOR_ID_mqdma + Pf3 Subsystem Vendor Id + 10EE + + + PF0_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF1_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF2_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF3_SUBSYSTEM_ID_mqdma + Pf3 Subsystem Id + 0007 + + + pf0_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf1_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf2_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf3_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf0_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf0_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf0_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf0_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf0_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf0_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + pf1_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf1_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf1_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf1_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf1_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf1_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + pf2_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf2_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf2_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf2_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf2_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf2_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + pf3_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf3_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf3_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf3_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf3_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf3_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 1 + + + pf0_sriov_cap_ver + Pf0 Sriov Cap Ver + 1 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0000 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 0 + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 00000553 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 1 + + + + false + + + + + + PF1_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + 0 + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0001 + + + + false + + + + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 00000553 + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0000 + + + + false + + + + + + PF2_SRIOV_CAP_VER + Pf2 Sriov Cap Ver + 1 + + + + false + + + + + + PF2_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF2_SRIOV_FIRST_VF_OFFSET + Pf2 Sriov First Vf Offset + 0 + + + PF2_SRIOV_FUNC_DEP_LINK + Pf2 Sriov Func Dep Link + 0002 + + + + false + + + + + + PF2_SRIOV_SUPPORTED_PAGE_SIZE + Pf2 Sriov Supported Page Size + 00000553 + + + PF2_SRIOV_VF_DEVICE_ID + Pf2 Sriov Vf Device Id + 0000 + + + + false + + + + + + PF3_SRIOV_CAP_INITIAL_VF + Pf3 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF3_SRIOV_CAP_VER + Pf3 Sriov Cap Ver + 1 + + + + false + + + + + + PF3_SRIOV_FIRST_VF_OFFSET + Pf3 Sriov First Vf Offset + 0 + + + PF3_SRIOV_FUNC_DEP_LINK + Pf3 Sriov Func Dep Link + 0003 + + + + false + + + + + + PF3_SRIOV_SUPPORTED_PAGE_SIZE + Pf3 Sriov Supported Page Size + 00000553 + + + PF3_SRIOV_VF_DEVICE_ID + Pf3 Sriov Vf Device Id + 0000 + + + + false + + + + + + pf0_ari_enabled + Pf0 Ari Enabled + false + + + pf0_msix_enabled_mqdma + Pf0 Msix Enabled + false + + + pf1_msix_enabled_mqdma + Pf1 Msix Enabled + false + + + pf2_msix_enabled_mqdma + Pf2 Msix Enabled + false + + + pf3_msix_enabled_mqdma + Pf3 Msix Enabled + false + + + PF0_MSIX_CAP_TABLE_SIZE_mqdma + Pf0 Msix Cap Table Size + 000 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_SIZE_mqdma + Pf1 Msix Cap Table Size + 000 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_SIZE_mqdma + Pf2 Msix Cap Table Size + 000 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_SIZE_mqdma + Pf3 Msix Cap Table Size + 000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_OFFSET_mqdma + Pf0 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_OFFSET_mqdma + Pf1 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_OFFSET_mqdma + Pf2 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_OFFSET_mqdma + Pf3 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF0_MSIX_CAP_PBA_OFFSET_mqdma + Pf0 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF1_MSIX_CAP_PBA_OFFSET_mqdma + Pf1 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF2_MSIX_CAP_PBA_OFFSET_mqdma + Pf2 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF3_MSIX_CAP_PBA_OFFSET_mqdma + Pf3 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_PBA_BIR_mqdma + Pf0 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_PBA_BIR_mqdma + Pf1 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_PBA_BIR_mqdma + Pf2 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_PBA_BIR_mqdma + Pf3 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + MSI_X_OPTIONS + None + + + + false + + + + + + dsc_bypass_rd_out + 0000 + + + dsc_bypass_wr_out + 0000 + + + num_queues + 1 + + + enable_auto_rxeq + False + + + enable_pcie_debug + False + + + axisten_if_enable_msg_route + 27FFF + + + en_axi_mm_mqdma + true + + + + true + + + + + + en_axi_st_mqdma + false + + + + true + + + + + + enable_more_clk + false + + + tl_credits_cd + 15 + + + tl_credits_ch + 15 + + + set_finite_credit + false + + + disable_bram_pipeline + false + + + disable_eq_synchronizer + false + + + enable_resource_reduction + false + + + c_ats_enable + ATS Extended Capability Enable + false + + + c_pri_enable + Page Request Extended Capability Enable + false + + + usplus_es1_seqnum_bypass + false + + + bridge_registers_offset_enable + false + + + enable_gen4 + false + + + gen4_eieos_0s7 + true + + + c_s_axi_supports_narrow_burst + false + + + enable_ats_switch + FALSE + + + c_ats_switch_unique_bdf + 1 + + + ctrl_skip_mask + true + + + pf0_ats_enabled + Pf0 Ats Enabled + false + + + pf0_pri_enabled + Pf0 Pri Enabled + false + + + aspm_support + ASPM Support + No_ASPM + + + pf0_aer_cap_ecrc_gen_and_check_capable + false + + + gen_pipe_debug + false + + + soft_reset_en + DMA Bridge Reset + false + + + msi_rx_pin_en + FALSE + + + intx_rx_pin_en + true + + + msix_type + MSI-X Type + HARD + + + runbit_fix + false + + + axsize_byte_access_en + false + + + + + DMA/Bridge Subsystem for PCI Express (PCIe) + + XPM_CDC + XPM_MEMORY + XPM_FIFO + + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + + -- cgit v1.2.3