From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- projects/VU095/verilog/project.vh | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 projects/VU095/verilog/project.vh (limited to 'projects/VU095/verilog/project.vh') diff --git a/projects/VU095/verilog/project.vh b/projects/VU095/verilog/project.vh new file mode 100644 index 0000000..1bb437e --- /dev/null +++ b/projects/VU095/verilog/project.vh @@ -0,0 +1,7 @@ +// `define ENABLE_DLL_TOGGLER +`define DQ_WIDTH 64 +// DIMM related +`define ODT_WIDTH 1 +`define CS_WIDTH 1 +`define CKE_WIDTH 1 +`define CK_WIDTH 1 \ No newline at end of file -- cgit v1.2.3