From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../sim_scripts/scratchpad/modelsim/compile.do | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do (limited to 'projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do') diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do new file mode 100644 index 0000000..92227c8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do @@ -0,0 +1,28 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -64 -incr -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr \ +"../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + -- cgit v1.2.3