From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../sim_scripts/xdma/xsim/README.txt | 49 +++++ .../sim_scripts/xdma/xsim/XUPVVH.smi | 30 +++ .../sim_scripts/xdma/xsim/cmd.tcl | 12 ++ .../sim_scripts/xdma/xsim/file_info.txt | 48 +++++ .../sim_scripts/xdma/xsim/glbl.v | 71 +++++++ .../xdma/xsim/protoinst_files/bd_9f2c.protoinst | 9 + .../sim_scripts/xdma/xsim/vlog.prj | 54 ++++++ .../sim_scripts/xdma/xsim/xdma.sh | 212 +++++++++++++++++++++ 8 files changed, 485 insertions(+) create mode 100644 projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/README.txt create mode 100644 projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/XUPVVH.smi create mode 100644 projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl create mode 100644 projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/file_info.txt create mode 100644 projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/glbl.v create mode 100644 projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst create mode 100644 projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/vlog.prj create mode 100755 projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/xdma.sh (limited to 'projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim') diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/README.txt new file mode 100644 index 0000000..120b61d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:48 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/XUPVVH.smi b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/XUPVVH.smi new file mode 100644 index 0000000..7951bb9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/XUPVVH.smi @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/file_info.txt new file mode 100644 index 0000000..f3f7702 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/file_info.txt @@ -0,0 +1,48 @@ +gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_cxs_remap.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_16k.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_32k.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_msix.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_rep.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_tph.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync_cell.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pl_eq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode_attr.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pipe.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pcie4c_uscale_core_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/vlog.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/vlog.prj new file mode 100644 index 0000000..cfc4710 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/vlog.prj @@ -0,0 +1,54 @@ +verilog xil_defaultlib --include "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" --include "../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v" \ + +sv xil_defaultlib --include "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" --include "../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/xdma.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/xdma.sh new file mode 100755 index 0000000..a28e6a4 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/xdma.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:48 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L gtwizard_ultrascale_v1_7_7 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_4 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot xdma xil_defaultlib.xdma xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim xdma -key {Behavioral:sim_1:Functional:xdma} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb xdma.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 -- cgit v1.2.3