From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001
From: Ataberk <olgunataberk@gmail.com>
Date: Sun, 25 Sep 2022 17:22:03 +0200
Subject: Initial commit

---
 projects/XUPVVH/verilog/project.vh | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 projects/XUPVVH/verilog/project.vh

(limited to 'projects/XUPVVH/verilog/project.vh')

diff --git a/projects/XUPVVH/verilog/project.vh b/projects/XUPVVH/verilog/project.vh
new file mode 100644
index 0000000..4084e1d
--- /dev/null
+++ b/projects/XUPVVH/verilog/project.vh
@@ -0,0 +1,11 @@
+`define XUPP3R_x4// MIG does not support DM|DBI w/ RDIMMs.
+`define DQ_WIDTH   72
+
+// DIMM related - x8 double ranks
+`ifdef XUPP3R_x4
+// DEFAULT CONFIGS USE BELOW
+`define ODT_WIDTH  2
+`define CS_WIDTH   2
+`define CKE_WIDTH  2
+`define CK_WIDTH   1
+`endif
\ No newline at end of file
-- 
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