From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../sources_1/ip/instr_blk_mem/instr_blk_mem.xci | 264 ++ .../sources_1/ip/instr_blk_mem/instr_blk_mem.xml | 4053 ++++++++++++++++++++ 2 files changed, 4317 insertions(+) create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xml (limited to 'projects/XUSP3R/XUSP3R.srcs/sources_1/ip/instr_blk_mem') diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci new file mode 100644 index 0000000..43476b1 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci @@ -0,0 +1,264 @@ + + + xilinx.com + xci + unknown + 1.0 + + + instr_blk_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + + OTHER + NONE + 8192 + 32 + + + 100000000 + 0.000 + 11 + 11 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 4 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 7.524303 mW + virtexuplus + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + instr_blk_mem.mem + no_coe_file_loaded + 0 + 0 + 0 + 0 + 1 + 2048 + 2048 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 2048 + 2048 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + no_coe_file_loaded + ALL + instr_blk_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + 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256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + instr_blk_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + false + + + + + + RD_ADDR_CHNG_B + false + + + + false + + + + + + Use_Error_Injection_Pins + false + + + + false + + + + + + Error_Injection_Type + Single_Bit_Error_Injection + + + + false + + + + + + Use_Byte_Write_Enable + false + + + + true + + + + + + Byte_Size + 9 + + + + false + + + + + + Algorithm + Minimum_Area + + + + true + + + + + + Primitive + 8kx2 + + + + false + + + + + + Assume_Synchronous_Clk + false + + + + false + + + + + + Write_Width_A + 64 + + + + true + + + + + + Write_Depth_A + 2048 + + + + true + + + + + + Read_Width_A + 64 + + + + true + + + + + + Operating_Mode_A + WRITE_FIRST + + + + true + + + + + + Enable_A + Use_ENA_Pin + + + + true + + + + + + Write_Width_B + 64 + + + + false + + + + + + Read_Width_B + 64 + + + + false + + + + + + Operating_Mode_B + WRITE_FIRST + + + + false + + + + + + Enable_B + Always_Enabled + + + + false + + + + + + Register_PortA_Output_of_Memory_Primitives + false + + + + true + + + + + + Register_PortA_Output_of_Memory_Core + false + + + + true + + + + + + Use_REGCEA_Pin + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Primitives + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Core + false + + + + false + + + + + + Use_REGCEB_Pin + false + + + + false + + + + + + register_porta_input_of_softecc + false + + + + false + + + + + + register_portb_output_of_softecc + false + + + + false + + + + + + Pipeline_Stages + 0 + + + + false + + + + + + Load_Init_File + false + + + + true + + + + + + Coe_File + no_coe_file_loaded + + + + false + + + + + + Fill_Remaining_Memory_Locations + true + + + + true + + + + + + Remaining_Memory_Locations + 0 + + + + true + + + + + + Use_RSTA_Pin + false + + + + true + + + + + + Reset_Memory_Latch_A + false + + + + false + + + + + + Reset_Priority_A + CE + + + + false + + + + + + Output_Reset_Value_A + 0 + + + + false + + + + + + Use_RSTB_Pin + false + + + + false + + + + + + Reset_Memory_Latch_B + false + + + + false + + + + + + Reset_Priority_B + CE + + + + false + + + + + + Output_Reset_Value_B + 0 + + + + false + + + + + + Reset_Type + SYNC + + + + false + + + + + + Additional_Inputs_for_Power_Estimation + false + + + + true + + + + + + Port_A_Clock + 100 + + + + true + + + + + + Port_A_Write_Rate + 50 + + + + true + + + + + + Port_B_Clock + 0 + + + + true + + + + + + Port_B_Write_Rate + 0 + + + + true + + + + + + Port_A_Enable_Rate + 100 + + + + true + + + + + + Port_B_Enable_Rate + 0 + + + + true + + + + + + Collision_Warnings + ALL + + + + true + + + + + + Disable_Collision_Warnings + false + + + + true + + + + + + Disable_Out_of_Range_Warnings + false + + + + true + + + + + + use_bram_block + Stand_Alone + + + + true + + + + + + MEM_FILE + no_mem_loaded + + + + true + + + + + + CTRL_ECC_ALGO + NONE + + + + true + + + + + + EN_SAFETY_CKT + false + + + + false + + + + + + + + Block Memory Generator + + XPM_MEMORY + + 1 + + + + + + + + + + + + 2018.2 + + + + + + + + + -- cgit v1.2.3