From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci | 150 ++ .../ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml | 2149 ++++++++++++++++++++ 2 files changed, 2299 insertions(+) create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml (limited to 'projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_0') diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci new file mode 100644 index 0000000..abdf016 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci @@ -0,0 +1,150 @@ + + + xilinx.com + xci + unknown + 1.0 + + + phy_ddr4_microblaze_mcs + + + Reset + + + CLK_BOARD_INTERFACE + + 100000000 + 0.000 + RESET_BOARD_INTERFACE + ACTIVE_HIGH + 0 + Custom + phy_ddr4_microblaze_mcs + 0 + 0 + 0 + 6216 + 0 + 6216 + 0 + 6216 + 0 + 6216 + 100.0 + 0 + 32 + 0 + 32 + 0 + 32 + 0 + 32 + Custom + Custom + Custom + Custom + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0xFFFF + 1 + 0x0000 + 2 + 0xFFFF + 0 + 2 + 98304 + microblaze_0 + 1 + mcs_0 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + Custom + 1 + 9600 + Custom + 8 + 0 + 0 + 0 + 0 + 0 + 0 + false + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Flow + 9 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml new file mode 100644 index 0000000..50a93c5 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml @@ -0,0 +1,2149 @@ + + + xilinx.com + customized_ip + phy_ddr4_microblaze_mcs + 1.0 + + + CLK.Clk + + + + + + + CLK + + + Clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + ASSOCIATED_ASYNC_RESET + Reset + + + none + + + + + BOARD.ASSOCIATED_PARAM + CLK_BOARD_INTERFACE + + + none + + + + + + + RST.Reset + + + + + + + RST + + + Reset + + + + + + POLARITY + ACTIVE_HIGH + + + none + + + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + none + + + + + + + IO + + + + + + + ADDR_STROBE + + + IO_addr_strobe + + + + + ADDRESS + + + IO_address + + + + + BYTE_ENABLE + + + IO_byte_enable + + + + + READ_DATA + + + IO_read_data + + + + + READ_STROBE + + + IO_read_strobe + + + + + READY + + + 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73728 + 81920 + 98304 + 131072 + + + choice_pairs_ffa336e4 + 0 + 1 + + + + + xilinx_elaborateports_view_fileset + + ../bd_0/bd_9f2c.bd + block_diagram + + + + xilinx_elaboratebd_view_fileset + + ../bd_0/bd_9f2c.bd + block_diagram + + + + MicroBlaze Micro Controller System (MCS) is a light-weight general purpose micro controller system, based on the MicroBlaze processor. It is primarily intended for simple control applications, where a hardware solution would be less flexible and more difficult to implement. Software development with the Xilinx Software Development Kit (SDK) is supported, including a software driver for the peripherals. Debugging including UART is available either via SDK or directly with the Xilinx Microprocessor Debugger. +The MCS consists of the processor itself, local memory with sizes ranging from 4KB to 128KB, up to 4 Fixed Interval Timers, up to 4 Programmable Interval Timers, up to 4 32-bit General Purpose Output ports, up to 4 32-bit General Purpose Input ports, and an Interrupt Controller with up to 16 external interrupt inputs. + + + + JTAG_CHAIN + Debug JTAG User-defined Register + 2 + + + + false + + + + + + MICROBLAZE_INSTANCE + MicroBlaze Instance Name + microblaze_0 + + + AVOID_PRIMITIVES + 0 + + + PATH + Instance Hierarchical Design Name + mcs_0 + + + FREQ + Input Clock Frequency (MHz) + 100.0 + + + OPTIMIZATION + Select MicroBlaze Optimization + 1 + + + DEBUG_ENABLED + Enable Debug Support + 0 + + + TRACE + Enable MicroBlaze Trace Bus + 1 + + + ECC + Error Correction Code + 0 + + + MEMSIZE + Memory Size + 98304 + + + USE_IO_BUS + Enable IO Bus + 1 + + + USE_UART_RX + Enable Receiver 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GPIO2_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO3_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO4_BOARD_INTERFACE + Custom + + + + true + + + + + + UART_BOARD_INTERFACE + Custom + + + + true + + + + + + + + MicroBlaze MCS + + XPM_MEMORY + + 9 + + true + subcore + + + + + + + + + + + + + + + 2018.2 + + + + + + -- cgit v1.2.3