From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci | 655 +++ .../sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xml | 4864 ++++++++++++++++++++ 2 files changed, 5519 insertions(+) create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xml (limited to 'projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_1') diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci new file mode 100644 index 0000000..5201bc7 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci @@ -0,0 +1,655 @@ + + + xilinx.com + xci + unknown + 1.0 + + + phy_ddr4_phy + + + 17 + 0 + 0 + 0 + 2 + HP_IO + 2 + X0Y11 + X0Y10 + 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MEMORY DEVICE WIDTH + 72 + + + PLL_WIDTH + PLL WIDTH + 3 + + + IOBTYPE + IOBTYPE + 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b +000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, + 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_000_000_000_000_000_000_001_000_001_001_001_001, 39'b001_001_001_000_000_001_001_001_00 +1_001_001_001_001, 39'b000_001_001_001_001_101_101_001_001_001_001_001_001 + + + BYTES + BYTES + 12 + + + DBYTES + DBYTES + 9 + + + PING_PONG_CH1_BYTES_MAP + PING_PONG_CH1_BYTES_MAP + 12'b000000000000 + + + PING_PONG_PHY + PING PONG PHY + 1 + + + RX_DATA_TYPE + RX DATA TYPE + { 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, + 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b011110_11_11110_11, 15'b000000_00_10111_11, + 15'b111001_11_11111_11, 15'b011111_11_11111_11 } + + + INIT + INIT + { 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, + 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111101, + 15'b111111111111111, 15'b111111111111111 } + + + SELF_CALIBRATE + SELF CALIBRATE + {12{2'b11}} + + + TX_OUTPUT_PHASE_90 + TX OUTPUT PHASE 90 + { 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000 +011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000011000011, 13'b0000000101111, 13'b1110011111111, + 13'b0111111111111 } + + + RXTX_BITSLICE_EN + RXTX BITSLICE EN + {13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b01111 +01111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0000000101111, 13'b1110011111111, + 13'b0111101111111 } + + + EN_OTHER_PN_CLOCK_PARAM + EN OTHER PN CLOCK PARAM + {12{2'b00}} + + + PHY_BYTE_ALLOC_PARAM + PHY BYTE ALLOC PARAM + {{9{2'b11}}, {3{2'b00}}} + + + DATA_BUF_ADDR_WIDTH + DATA BUF ADDR WIDTH + 5 + + + CLKIN_PERIOD + CLKIN PERIOD + 10000 + + + MEM_TYPE + MEM TYPE + 0 + + + AXI_ID_WIDTH + AXI ID WIDTH + 0 + + + AXI_DATA_WIDTH + AXI DATA WIDTH + 0 + + + AXI_ADDR_WIDTH + AXI ADDR WIDTH + 0 + + + USE_DM_PORT + USE DM PORT + 0 + + + BUFG_LOC_1 + BUFG LOC 1 + X0Y70 + + + BUFG_LOC_2 + BUFG LOC 2 + X0Y11 + + + BUFG_DIV_LOC_1 + BUFG DIV LOC 1 + X0Y11 + + + BUFG_DIV_LOC_2 + BUFG DIV LOC 2 + X0Y10 + + + PBLOCK_SLICE_LOC + PBLOCK SLICE LOC + 0 + + + PBLOCK_RAMB36_LOC + PBLOCK RAMB36 LOC + 0 + + + PBLOCK_RAMB18_LOC + PBLOCK RAMB18 LOC + 0 + + + PBLOCK_SLICE_LOC_SC + PBLOCK SLICE LOC SC + 0 + + + PBLOCK_RAMB36_LOC_SC + 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Component_Name + phy_ddr4_phy + + + + + DDR4 SDRAM PHY IP + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + -- cgit v1.2.3