From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../XUSP3R.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci | 406 +++++++++++++++++++++ 1 file changed, 406 insertions(+) create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci (limited to 'projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci') diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci new file mode 100644 index 0000000..21be212 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci @@ -0,0 +1,406 @@ + + + xilinx.com + xci + unknown + 1.0 + + + phy_ddr4 + + + + + + + + + + + + + + + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0.000 + 31 + 576 + 72 + X0Y11 + X0Y10 + X0Y70 + X0Y11 + 0 + 0 + DDR4_SDRAM + 17 + 0 + 0 + 32 + 64 + 4 + 2 + 2 + 0 + 0 + 0 + 1 + 1 + 0 + 15 + 10000 + 9 + 0 + VCO + 10 + 8Gb + 31 + 1 + 0 + 0 + 4 + 0 + 0 + 938 + 1 + 9 + 18 + 72 + 0 + 1.2V + false + No + 1600 + 0 + 0 + MTA18ASF2G72PZ-2G3 + RDIMMs + 4 + 16GB + 8 + 8192 + 72 + 17179869184 + 833 + DDR4_833_Timing + 0 + 0 + 1 + 0 + 1 + 17 + 0 + 0 + 083 + 1 + 1 + 166500000 + 1 + 0 + 0.84 + 0 + 4 + 1 + 5 + 1500 + 0 + 9 + 16 + 2 + 22 + 10 + 5200 + 234 + 80 + 10 + + 4 + 3 + 4 + 5 + 10 + + 5 + 2 + 60 + 128 + 0 + 256 + DDR4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + FALSE + 10000 + 0 + 0 + 0 + 0 + 0 + 0 + NONE + Disable + 1 + 0.0 + 0 + 0.0 + 0 + 0.0 + 0 + 0.0 + 0 + 1 + 0 + None + None + None + None + 0 + 17 + 2 + 1 + 1 + 1 + DDR4_SDRAM + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + false + 32 + RD_PRI_REG + 64 + 4 + false + false + 0 + 0 + 0 + 0 + 8 + Sequential + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 15 + 9 + 0 + 0 + 0 + 0 + 512 + 10 + 9 + true + false + no_file_loaded + 1 + NONE + 72 + false + 10000 + 0 + 0 + false + ROW_COLUMN_BANK + MainMemory + MTA18ASF2G72PZ-2G3 + RDIMMs + 1.2V + 0 + 0 + 0 + 0 + RZQ/6 + Normal + RZQ/7 + 0 + 4:1 + false + false + Single + false + 1500 + false + false + false + 1 + false + 1 + 1 + Custom + Custom + false + phy_ddr4 + false + false + Disable + false + true + SIMPLE_TG + OFF + false + 1 + false + 1 + false + 1 + Phy_Only_Single + false + Custom + Differential + false + BFM + Differential + false + false + false + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2018.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.2.3