From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- .../sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bd | 441 + .../sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bxml | 100 + .../ip/phy_ddr4_x8/bd_0/hdl/bd_9d69_wrapper.v | 173 + .../bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xci | 955 + .../bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xml | 26887 +++++++++++++++++++ .../phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xci | 71 + .../phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xml | 583 + .../bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xci | 272 + .../bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xml | 7497 ++++++ .../ip/phy_ddr4_x8/bd_0/ip/ip_2/bd_9d69_ilmb_0.xci | 113 + .../ip/phy_ddr4_x8/bd_0/ip/ip_2/bd_9d69_ilmb_0.xml | 3323 +++ .../ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xci | 115 + .../ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xml | 3325 +++ .../bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xml | 3874 +++ .../bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xml | 3874 +++ .../bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xci | 275 + .../bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xml | 4056 +++ .../bd_0/ip/ip_7/bd_9d69_second_dlmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_7/bd_9d69_second_dlmb_cntlr_0.xml | 3874 +++ .../bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xml | 3874 +++ .../bd_0/ip/ip_9/bd_9d69_second_lmb_bram_I_0.xci | 275 + .../bd_0/ip/ip_9/bd_9d69_second_lmb_bram_I_0.xml | 4056 +++ .../ip_0/phy_ddr4_x8_microblaze_mcs.xci | 150 + .../ip_0/phy_ddr4_x8_microblaze_mcs.xml | 2141 ++ .../ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xci | 655 + .../ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xml | 4864 ++++ .../sources_1/ip/phy_ddr4_x8/phy_ddr4_x8.xci | 401 + .../sources_1/ip/phy_ddr4_x8/phy_ddr4_x8.xml | 8591 ++++++ 31 files changed, 85423 insertions(+) create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bd create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bxml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/hdl/bd_9d69_wrapper.v create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_2/bd_9d69_ilmb_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_2/bd_9d69_ilmb_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_7/bd_9d69_second_dlmb_cntlr_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_7/bd_9d69_second_dlmb_cntlr_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_9/bd_9d69_second_lmb_bram_I_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_9/bd_9d69_second_lmb_bram_I_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_0/phy_ddr4_x8_microblaze_mcs.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_0/phy_ddr4_x8_microblaze_mcs.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/phy_ddr4_x8.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/phy_ddr4_x8.xml (limited to 'projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8') diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bd b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bd new file mode 100644 index 0000000..ee1ca98 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bd @@ -0,0 +1,441 @@ + + + + + xilinx.com + BlockDiagram + bd_9d69 + 1.00.a + + + isTop + true + + + + + IO + + + + + + TRACE + + + + + + CLK.CLK + Clk + Clock + + + + + + + CLK + + + Clk + + + + + + FREQ_HZ + 100000000 + + + + + + + + PHASE + 0.000 + + + + + + + + ASSOCIATED_ASYNC_RESET + Reset + + + + + + + + + + RST.RESET + Reset + Reset + + + + + + + RST + + + Reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + Clk + + in + + + + Reset + + in + + + + + + + + xilinx.com + BlockDiagram + bd_9d69_imp + 1.00.a + + + microblaze_I + + + bd_9d69_microblaze_I_0 + 17 + mb_microblaze_0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 3 + 0 + 0 + + + + + rst_0 + + + bd_9d69_rst_0_0 + + + + ilmb + + + bd_9d69_ilmb_0 + 2 + + + + dlmb + + + bd_9d69_dlmb_0 + 3 + + + + dlmb_cntlr + + + bd_9d69_dlmb_cntlr_0 + 0x0000000000000000 + 0x000000000000FFFF + 0x00000000C0010000 + + + + + ilmb_cntlr + + + bd_9d69_ilmb_cntlr_0 + 0x0000000000000000 + 0x000000000000FFFF + 0x0000000080010000 + + + + lmb_bram_I + + + bd_9d69_lmb_bram_I_0 + True_Dual_Port_RAM + + + + second_dlmb_cntlr + + + bd_9d69_second_dlmb_cntlr_0 + 0x0000000000010000 + 0x0000000000017FFF + 0x00000000C0010000 + + + + + second_ilmb_cntlr + + + bd_9d69_second_ilmb_cntlr_0 + 0x0000000000010000 + 0x0000000000017FFF + 0x0000000080010000 + + + + second_lmb_bram_I + + + bd_9d69_second_lmb_bram_I_0 + True_Dual_Port_RAM + + + + iomodule_0 + + + bd_9d69_iomodule_0_0 + iomodule + 0x0000000080000000 + 0x000000008000FFFF + 0x00000000C0000000 + 1 + 0x00000000C0000000 + 0x00000000FFFFFFFF + 0x00000000C0000000 + 1 + 1 + 17 + + + + + + ilmb + + + + + dlmb + + + + + ilmb_sl_0 + + + + + dlmb_sl_0 + + + + + dlmb_sl_1 + + + + + ilmb_port + + + + + dlmb_port + + + + + ilmb_sl_1 + + + + + dlmb_sl_2 + + + + + ilmb_port_2 + + + + + dlmb_port_2 + + + + + + + Clk2 + + + + + + + + + + + + + Reset + + + + + MB_Reset + + + + + LMB_Rst2 + + + + + + + + + + IO_Rst + + + + + + + + + + + + + + + + xilinx.com + Addressing/microblaze_I + microblaze + 10.0 + + + DLMB + + + + + + + + ILMB + + + + + + + + + + Data + 4G + 32 + + + SEG_dlmb_cntlr_Mem + /dlmb_cntlr/SLMB/Mem + 0x00000000 + 64K + + + SEG_iomodule_0_IO + /iomodule_0/SLMB/IO + 0xC0000000 + 1G + + + SEG_iomodule_0_Reg + /iomodule_0/SLMB/Reg + 0x80000000 + 64K + + + SEG_second_dlmb_cntlr_Mem + /second_dlmb_cntlr/SLMB/Mem + 0x00010000 + 32K + + + + + Instruction + 4G + 32 + + + SEG_ilmb_cntlr_Mem + /ilmb_cntlr/SLMB/Mem + 0x00000000 + 64K + + + SEG_second_ilmb_cntlr_Mem + /second_ilmb_cntlr/SLMB/Mem + 0x00010000 + 32K + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bxml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bxml new file mode 100644 index 0000000..61f2511 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bxml @@ -0,0 +1,100 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/hdl/bd_9d69_wrapper.v b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/hdl/bd_9d69_wrapper.v new file mode 100644 index 0000000..8059f19 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/hdl/bd_9d69_wrapper.v @@ -0,0 +1,173 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Command: generate_target bd_9d69_wrapper.bd +//Design : bd_9d69_wrapper +//Purpose: IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module bd_9d69_wrapper + (Clk, + IO_addr_strobe, + IO_address, + IO_byte_enable, + IO_read_data, + IO_read_strobe, + IO_ready, + IO_write_data, + IO_write_strobe, + Reset, + TRACE_data_access, + TRACE_data_address, + TRACE_data_byte_enable, + TRACE_data_read, + TRACE_data_write, + TRACE_data_write_value, + TRACE_dcache_hit, + TRACE_dcache_rdy, + TRACE_dcache_read, + TRACE_dcache_req, + TRACE_delay_slot, + TRACE_ex_piperun, + TRACE_exception_kind, + TRACE_exception_taken, + TRACE_icache_hit, + TRACE_icache_rdy, + TRACE_icache_req, + TRACE_instruction, + TRACE_jump_hit, + TRACE_jump_taken, + TRACE_mb_halted, + TRACE_mem_piperun, + TRACE_msr_reg, + TRACE_new_reg_value, + TRACE_of_piperun, + TRACE_pc, + TRACE_pid_reg, + TRACE_reg_addr, + TRACE_reg_write, + TRACE_valid_instr); + input Clk; + output IO_addr_strobe; + output [31:0]IO_address; + output [3:0]IO_byte_enable; + input [31:0]IO_read_data; + output IO_read_strobe; + input IO_ready; + output [31:0]IO_write_data; + output IO_write_strobe; + input Reset; + output TRACE_data_access; + output [0:31]TRACE_data_address; + output [0:3]TRACE_data_byte_enable; + output TRACE_data_read; + output TRACE_data_write; + output [0:31]TRACE_data_write_value; + output TRACE_dcache_hit; + output TRACE_dcache_rdy; + output TRACE_dcache_read; + output TRACE_dcache_req; + output TRACE_delay_slot; + output TRACE_ex_piperun; + output [0:4]TRACE_exception_kind; + output TRACE_exception_taken; + output TRACE_icache_hit; + output TRACE_icache_rdy; + output TRACE_icache_req; + output [0:31]TRACE_instruction; + output TRACE_jump_hit; + output TRACE_jump_taken; + output TRACE_mb_halted; + output TRACE_mem_piperun; + output [0:14]TRACE_msr_reg; + output [0:31]TRACE_new_reg_value; + output TRACE_of_piperun; + output [0:31]TRACE_pc; + output [0:7]TRACE_pid_reg; + output [0:4]TRACE_reg_addr; + output TRACE_reg_write; + output TRACE_valid_instr; + + wire Clk; + wire IO_addr_strobe; + wire [31:0]IO_address; + wire [3:0]IO_byte_enable; + wire [31:0]IO_read_data; + wire IO_read_strobe; + wire IO_ready; + wire [31:0]IO_write_data; + wire IO_write_strobe; + wire Reset; + wire TRACE_data_access; + wire [0:31]TRACE_data_address; + wire [0:3]TRACE_data_byte_enable; + wire TRACE_data_read; + wire TRACE_data_write; + wire [0:31]TRACE_data_write_value; + wire TRACE_dcache_hit; + wire TRACE_dcache_rdy; + wire TRACE_dcache_read; + wire TRACE_dcache_req; + wire TRACE_delay_slot; + wire TRACE_ex_piperun; + wire [0:4]TRACE_exception_kind; + wire TRACE_exception_taken; + wire TRACE_icache_hit; + wire TRACE_icache_rdy; + wire TRACE_icache_req; + wire [0:31]TRACE_instruction; + wire TRACE_jump_hit; + wire TRACE_jump_taken; + wire TRACE_mb_halted; + wire TRACE_mem_piperun; + wire [0:14]TRACE_msr_reg; + wire [0:31]TRACE_new_reg_value; + wire TRACE_of_piperun; + wire [0:31]TRACE_pc; + wire [0:7]TRACE_pid_reg; + wire [0:4]TRACE_reg_addr; + wire TRACE_reg_write; + wire TRACE_valid_instr; + + bd_9d69 bd_9d69_i + (.Clk(Clk), + .IO_addr_strobe(IO_addr_strobe), + .IO_address(IO_address), + .IO_byte_enable(IO_byte_enable), + .IO_read_data(IO_read_data), + .IO_read_strobe(IO_read_strobe), + .IO_ready(IO_ready), + .IO_write_data(IO_write_data), + .IO_write_strobe(IO_write_strobe), + .Reset(Reset), + .TRACE_data_access(TRACE_data_access), + .TRACE_data_address(TRACE_data_address), + .TRACE_data_byte_enable(TRACE_data_byte_enable), + .TRACE_data_read(TRACE_data_read), + .TRACE_data_write(TRACE_data_write), + .TRACE_data_write_value(TRACE_data_write_value), + .TRACE_dcache_hit(TRACE_dcache_hit), + .TRACE_dcache_rdy(TRACE_dcache_rdy), + .TRACE_dcache_read(TRACE_dcache_read), + .TRACE_dcache_req(TRACE_dcache_req), + .TRACE_delay_slot(TRACE_delay_slot), + .TRACE_ex_piperun(TRACE_ex_piperun), + .TRACE_exception_kind(TRACE_exception_kind), + .TRACE_exception_taken(TRACE_exception_taken), + .TRACE_icache_hit(TRACE_icache_hit), + .TRACE_icache_rdy(TRACE_icache_rdy), + .TRACE_icache_req(TRACE_icache_req), + .TRACE_instruction(TRACE_instruction), + .TRACE_jump_hit(TRACE_jump_hit), + .TRACE_jump_taken(TRACE_jump_taken), + .TRACE_mb_halted(TRACE_mb_halted), + .TRACE_mem_piperun(TRACE_mem_piperun), + .TRACE_msr_reg(TRACE_msr_reg), + .TRACE_new_reg_value(TRACE_new_reg_value), + .TRACE_of_piperun(TRACE_of_piperun), + .TRACE_pc(TRACE_pc), + .TRACE_pid_reg(TRACE_pid_reg), + .TRACE_reg_addr(TRACE_reg_addr), + .TRACE_reg_write(TRACE_reg_write), + .TRACE_valid_instr(TRACE_valid_instr)); +endmodule diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xci new file mode 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C_NUMBER_OF_RD_ADDR_BRK + Number of Read Address Watchpoints + 0 + + + C_NUMBER_OF_WR_ADDR_BRK + Number of Write Address Watchpoints + 0 + + + C_DEBUG_EVENT_COUNTERS + Number of Performance Monitor Event Counters + 5 + + + C_DEBUG_LATENCY_COUNTERS + Number of Performance Monitor Latency Counters + 1 + + + C_DEBUG_COUNTER_WIDTH + Performance Monitor Counter Width + 32 + + + C_DEBUG_TRACE_SIZE + Trace Buffer Size + 8192 + + + C_DEBUG_EXTERNAL_TRACE + External Trace + 0 + + + C_DEBUG_TRACE_ASYNC_RESET + Use Asynchrnous Reset for External Trace + 0 + + + C_DEBUG_PROFILE_SIZE + Profile Buffer Size + 0 + + + C_INTERRUPT_IS_EDGE + Sense Interrupt on Edge vs. Level + 0 + + + C_EDGE_IS_POSITIVE + Sense Interrupt on Rising vs. Falling Edge + 1 + + + C_ASYNC_INTERRUPT + 1 + + + C_ASYNC_WAKEUP + 3 + + + C_M0_AXIS_DATA_WIDTH + 32 + + + C_S0_AXIS_DATA_WIDTH + 32 + + + C_M1_AXIS_DATA_WIDTH + 32 + + + C_S1_AXIS_DATA_WIDTH + 32 + + + C_M2_AXIS_DATA_WIDTH + 32 + + + C_S2_AXIS_DATA_WIDTH + 32 + + + C_M3_AXIS_DATA_WIDTH + 32 + + + C_S3_AXIS_DATA_WIDTH + 32 + + + C_M4_AXIS_DATA_WIDTH + 32 + + + C_S4_AXIS_DATA_WIDTH + 32 + + + C_M5_AXIS_DATA_WIDTH + 32 + + + C_S5_AXIS_DATA_WIDTH + 32 + + + C_M6_AXIS_DATA_WIDTH + 32 + + + C_S6_AXIS_DATA_WIDTH + 32 + + + C_M7_AXIS_DATA_WIDTH + 32 + + + C_S7_AXIS_DATA_WIDTH + 32 + + + C_M8_AXIS_DATA_WIDTH + 32 + + + C_S8_AXIS_DATA_WIDTH + 32 + + + C_M9_AXIS_DATA_WIDTH + 32 + + + C_S9_AXIS_DATA_WIDTH + 32 + + + C_M10_AXIS_DATA_WIDTH + 32 + + + C_S10_AXIS_DATA_WIDTH + 32 + + + C_M11_AXIS_DATA_WIDTH + 32 + + + C_S11_AXIS_DATA_WIDTH + 32 + + + C_M12_AXIS_DATA_WIDTH + 32 + + + C_S12_AXIS_DATA_WIDTH + 32 + + + C_M13_AXIS_DATA_WIDTH + 32 + + + C_S13_AXIS_DATA_WIDTH + 32 + + + C_M14_AXIS_DATA_WIDTH + 32 + + + C_S14_AXIS_DATA_WIDTH + 32 + + + C_M15_AXIS_DATA_WIDTH + 32 + + + C_S15_AXIS_DATA_WIDTH + 32 + + + C_ICACHE_BASEADDR + Base Address + 0x0000000000000000 + + + C_ICACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + C_USE_ICACHE + Enable Instruction Cache + 0 + + + C_ALLOW_ICACHE_WR + Enable Writes + 1 + + + C_ADDR_TAG_BITS + 17 + + + C_CACHE_BYTE_SIZE + Size in Bytes + 8192 + + + C_ICACHE_LINE_LEN + Line Length + 4 + + + C_ICACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 0 + + + C_ICACHE_STREAMS + Number of Streams + 0 + + + + true + + + + + + C_ICACHE_VICTIMS + Number of Victims + 0 + + + + true + + + + + + C_ICACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + + true + + + + + + C_ICACHE_DATA_WIDTH + Data Width + 0 + + + + true + + + + + + C_M_AXI_IC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_DATA_WIDTH + 32 + + + C_M_AXI_IC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IC_USER_VALUE + 31 + + + + true + + + + + + C_M_AXI_IC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_BUSER_WIDTH + 1 + + + + true + + + + + + C_DCACHE_BASEADDR + Base Address + 0x0000000000000000 + + + C_DCACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + C_USE_DCACHE + Enable Data Cache + 0 + + + C_ALLOW_DCACHE_WR + Enable Writes + 1 + + + C_DCACHE_ADDR_TAG + 17 + + + C_DCACHE_BYTE_SIZE + Size in Bytes + 8192 + + + C_DCACHE_LINE_LEN + Line Length + 4 + + + C_DCACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 0 + + + C_DCACHE_USE_WRITEBACK + Enable Write-back Storage Policy + 0 + + + + true + + + + + + C_DCACHE_VICTIMS + Number of Victims + 0 + + + + false + + + + + + C_DCACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + C_DCACHE_DATA_WIDTH + Data Width + 0 + + + + false + + + + + + C_M_AXI_DC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_DATA_WIDTH + 32 + + + C_M_AXI_DC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DC_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_M_AXI_DC_USER_VALUE + 31 + + + + true + + + + + + C_M_AXI_DC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_BUSER_WIDTH + 1 + + + + true + + + + + + + + + choice_list_29910ba8 + GENERIC + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_b1aff63c + 32 + 48 + 64 + + + choice_list_b94541ab + 0 + 2 + 4 + 8 + + + choice_list_dd2843c6 + 1 + 2 + 4 + 8 + + + choice_list_f86403bf + 4 + 8 + 16 + + + choice_pairs_0000a26c + 0 + 1 + 2 + 3 + + + choice_pairs_1075faf2 + 0 + 1 + 2 + + + choice_pairs_126baff7 + 0 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_13d40c7c + 0 + 32 + 64 + 128 + 256 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_2058dc69 + 0 + 1 + + + choice_pairs_22d9f392 + 0 + 1 + 2 + 3 + + + choice_pairs_3eb333f8 + 0 + 1 + 2 + + + choice_pairs_443ae6cc + 0 + 1 + 2 + 3 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_56d5ba32 + 0 + 1 + 2 + + + choice_pairs_5ab38e91 + 0 + 1 + 2 + + + choice_pairs_5b1842a1 + 0 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_75c71b2b + 0 + 1 + 2 + 3 + + + choice_pairs_7ad6afc0 + 0 + 1 + 2 + 3 + + + choice_pairs_7bfd418d + 0 + 1 + 2 + + + choice_pairs_7dd2834f + 0 + 8 + 9 + 10 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_8b498448 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + + + choice_pairs_b1fa18d9 + 0 + 1 + 2 + + + choice_pairs_c471ed24 + 32 + 36 + 40 + 44 + 48 + 52 + 64 + + + choice_pairs_db57ca32 + 0 + 1 + 2 + + + choice_pairs_e7a1eb81 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_ff364cce + 2 + 3 + + + + + microblaze + + + + endian + little + + + instance_path + + + + bootloop_file + data/mb_bootloop_le.elf + + + processor_type + MICROBLAZE_LE + + + is_visible + true + + + + + The MicroBlaze 32 bit soft processor core, providing an instruction set optimized for embedded applications with many user-configurable options. MicroBlaze has many advanced architecture features like Instruction and Data-side cache with AXI interfaces, Floating-Point unit (FPU), Memory Management Unit (MMU), and fault tolerance support. +It is highly recommended to create MicroBlaze systems within Vivado IP Integrator, to enable export to the Xilinx Software Development Kit (SDK) for software development. + + + + C_SCO + 0 + + + + true + + + + + + C_FREQ + 100000000 + + + + true + + + + + + C_DATA_SIZE + 32 + + + + true + + + + + + C_ADDR_SIZE + Select Extended Addressing + 32 + + + + true + + + + + + C_DYNAMIC_BUS_SIZING + 0 + + + + true + + + + + + C_PC_WIDTH + 17 + + + + true + + + + + + C_INSTANCE + mb_microblaze_0 + + + + true + + + + + + C_AVOID_PRIMITIVES + 0 + + + + true + + + + + + C_FAULT_TOLERANT + Enable Fault Tolerance Support + 0 + + + + true + + + + + + C_ECC_USE_CE_EXCEPTION + Correctable Error Exception + 0 + + + + true + + + + + + C_LOCKSTEP_SLAVE + Lockstep Slave + 0 + + + + true + + + + + + C_ENDIANNESS + Endianness + 1 + + + + true + + + + + + C_AREA_OPTIMIZED + Select implementation optimization + 0 + + + + true + + + + + + C_OPTIMIZATION + 0 + + + + true + + + + + + C_INTERCONNECT + Select Bus Interface + 2 + + + + true + + + + + + C_BASE_VECTORS + Vector Base Address + 0x00000000 + + + + true + + + + + + C_USE_CONFIG_RESET + 0 + + + + true + + + + + + C_NUM_SYNC_FF_CLK + Synchronizing FFs to Clk region + 2 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_IRQ + Synchronizing FFs to Clk region for interrupt input + 1 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_DEBUG + Synchronizing FFs to Clk region in debug module + 2 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_CLK + Synchronizing FFs to Dbg_Clk region + 1 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_TRACE_CLK + Synchronizing FFs to Dbg_Trace_Clk region + 2 + + + + true + + + + + + C_M_AXI_DP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_D_AXI + Enable Peripheral AXI Data Interface + 0 + + + + true + + + + + + C_DP_AXI_MON + Use Monitor Interface for Peripheral AXI Data Interface + 0 + + + + true + + + + + + C_DC_AXI_MON + Use Monitor Interface for Cache AXI Data Interface + 0 + + + + true + + + + + + C_D_LMB + Enable Local Memory Bus Data Interface + 1 + + + + true + + + + + + C_D_LMB_MON + Use Monitor Interface for Local Memory Bus Data Interface + 0 + + + + true + + + + + + C_M_AXI_IP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IP_ADDR_WIDTH + 32 + + + + true + + + + + + C_I_AXI + Enable Peripheral AXI Instruction Interface + 0 + + + + true + + + + + + C_IP_AXI_MON + Use Monitor Interface for Peripheral AXI Instruction Interface + 0 + + + + true + + + + + + C_IC_AXI_MON + Use Monitor Interface for Cache AXI Instruction Interface + 0 + + + + true + + + + + + C_I_LMB + Enable Local Memory Bus Instruction Interface + 1 + + + + true + + + + + + C_I_LMB_MON + Use Monitor Interface for Local Memory Bus Instruction Interface + 0 + + + + true + + + + + + C_TRACE + Enable Trace Bus Interface + 1 + + + + true + + + + + + C_LOCKSTEP_SELECT + Lockstep Interface + 0 + + + + true + + + + + + C_ENABLE_DISCRETE_PORTS + Enable Discrete Ports + 0 + + + + true + + + + + + C_M_AXI_DC_USER_SIGNALS + Enable M_AXI_DC User Signals + 0 + + + + true + + + + + + C_M_AXI_IC_USER_SIGNALS + Enable M_AXI_IC User Signals + 0 + + + + true + + + + + + G_TEMPLATE_LIST + Select Configuration + 0 + + + + true + + + + + + G_USE_EXCEPTIONS + Enable Exceptions + 0 + + + + true + + + + + + C_USE_MSR_INSTR + Enable Additional Machine Status Register Instructions + 0 + + + + true + + + + + + C_USE_PCMP_INSTR + Enable Pattern Comparator + 1 + + + + true + + + + + + C_USE_REORDER_INSTR + Enable Reversed Load/Store and Swap Instructions + 0 + + + + true + + + + + + C_USE_BARREL + Enable Barrel Shifter + 1 + + + + true + + + + + + C_USE_DIV + Enable Integer Divider + 1 + + + + true + + + + + + C_USE_HW_MUL + Enable Integer Multiplier + 1 + + + + true + + + + + + C_USE_FPU + Enable Floating Point Unit + 0 + + + + true + + + + + + C_UNALIGNED_EXCEPTIONS + Enable Unaligned Data Exception + 0 + + + + true + + + + + + C_ILL_OPCODE_EXCEPTION + Enable Illegal Instruction Exception + 0 + + + + true + + + + + + C_M_AXI_I_BUS_EXCEPTION + Enable Instruction-side AXI Exception + 0 + + + + false + + + + + + C_M_AXI_D_BUS_EXCEPTION + Enable Data-side AXI Exception + 0 + + + + false + + + + + + C_DIV_ZERO_EXCEPTION + Enable Integer Divide Exception + 0 + + + + true + + + + + + C_FPU_EXCEPTION + Enable Floating Point Unit Exceptions + 0 + + + + false + + + + + + C_FSL_EXCEPTION + Enable Stream Exception + 0 + + + + false + + + + + + C_USE_STACK_PROTECTION + Enable stack protection + 0 + + + + true + + + + + + C_IMPRECISE_EXCEPTIONS + Allow Imprecise Exceptions + 0 + + + + true + + + + + + C_PVR + Specifies Processor Version Register + 0 + + + + true + + + + + + C_PVR_USER1 + Specify USER1 Bits in Processor Version Register + 0x00 + + + + false + + + + + + C_PVR_USER2 + Specify USER2 Bits in Processor Version Register + 0x00000000 + + + + false + + + + + + C_DEBUG_ENABLED + MicroBlaze Debug Module Interface + 0 + + + + true + + + + + + C_DEBUG_INTERFACE + MicroBlaze Debug Connection + 0 + + + + true + + + + + + C_NUMBER_OF_PC_BRK + Number of PC Breakpoints + 1 + + + + false + + + + + + C_NUMBER_OF_RD_ADDR_BRK + Number of Read Address Watchpoints + 0 + + + + false + + + + + + C_NUMBER_OF_WR_ADDR_BRK + Number of Write Address Watchpoints + 0 + + + + false + + + + + + C_DEBUG_EVENT_COUNTERS + Number of Performance Monitor Event Counters + 5 + + + + false + + + + + + C_DEBUG_LATENCY_COUNTERS + Number of Performance Monitor Latency Counters + 1 + + + + false + + + + + + C_DEBUG_COUNTER_WIDTH + Performance Monitor Counter Width + 32 + + + + false + + + + + + C_DEBUG_TRACE_SIZE + Trace Buffer Size + 8192 + + + + false + + + + + + C_DEBUG_EXTERNAL_TRACE + External Trace + 0 + + + + false + + + + + + C_DEBUG_TRACE_ASYNC_RESET + Use Asynchrnous Reset for External Trace + 0 + + + + true + + + + + + C_DEBUG_PROFILE_SIZE + Profile Buffer Size + 0 + + + + false + + + + + + C_INTERRUPT_IS_EDGE + Sense Interrupt on Edge vs. Level + 0 + + + + true + + + + + + C_EDGE_IS_POSITIVE + Sense Interrupt on Rising vs. Falling Edge + 1 + + + + true + + + + + + C_ASYNC_INTERRUPT + 1 + + + + true + + + + + + C_ASYNC_WAKEUP + 3 + + + + true + + + + + + C_RESET_MSR_IE + IE + 0 + + + + true + + + + + + C_RESET_MSR_BIP + BIP + 0 + + + + true + + + + + + C_RESET_MSR_ICE + ICE + 0 + + + + true + + + + + + C_RESET_MSR_DCE + DCE + 0 + + + + true + + + + + + C_RESET_MSR_EE + EE + 0 + + + + true + + + + + + C_RESET_MSR_EIP + EIP + 0 + + + + true + + + + + + C_OPCODE_0x0_ILLEGAL + Generate Illegal Instruction Exception for NULL Instruction + 0 + + + + false + + + + + + C_FSL_LINKS + Number of Stream Links + 0 + + + + true + + + + + + C_USE_EXTENDED_FSL_INSTR + Enable Additional Stream Instructions + 0 + + + + false + + + + + + C_M0_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S0_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M1_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S1_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M2_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S2_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M3_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S3_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M4_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S4_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M5_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S5_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M6_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S6_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M7_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S7_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M8_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S8_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M9_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S9_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M10_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S10_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M11_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S11_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M12_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S12_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M13_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S13_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M14_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S14_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M15_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S15_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M0_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S0_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M1_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S1_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M2_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S2_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M3_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S3_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M4_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S4_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M5_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S5_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M6_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S6_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M7_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S7_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M8_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S8_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M9_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S9_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M10_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S10_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + 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+ + + + TRI_I + + + GPI2 + + + + + TRI_O + + + GPO2 + + + + + + C_USE_GPO2 + 0 + + + + true + + + + + + C_GPO2_SIZE + 32 + + + + true + + + + + + C_GPO2_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI2 + 0 + + + + true + + + + + + C_GPI2_SIZE + 32 + + + + true + + + + + + C_GPI2_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO2_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO3 + GPIO3 + General Purpose IO + + + + + + + TRI_I + + + GPI3 + + + + + TRI_O + + + GPO3 + + + + + + C_USE_GPO3 + 0 + + + + true + + + + + + C_GPO3_SIZE + 32 + + + + true + + + + + + C_GPO3_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI3 + 0 + + + + true + + + + + + C_GPI3_SIZE + 32 + + + + true + + + + + + C_GPI3_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO3_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO4 + GPIO4 + General Purpose IO + + + + + + + TRI_I + + + GPI4 + + + + + TRI_O + + + GPO4 + + + + + + C_USE_GPO4 + 0 + + + + true + + + + + + C_GPO4_SIZE + 32 + + + + true + + + + + + C_GPO4_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI4 + 0 + + + + true + + + + + + C_GPI4_SIZE + 32 + + + + true + + + + + + C_GPI4_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO4_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + + + SLMB + LMB memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + UART RX + UART Receive Data Register + UART Receive Data Register + 0x0 + 8 + true + read-only + + 0x0 + + + UART RX + Receive Data + Data received by the UART. + 0 + 8 + true + read-only + + 0 + 0 + + modify + false + + + + + false + + + + + + UART TX + UART Transmit Data Register + UART Transmit Data Register + 0x4 + 8 + true + write-only + + 0x0 + + + UART TX + Transmit Data + Data to be transmitted by the UART. + 0 + 8 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART Status + UART Status Register + UART Status Register + 0x8 + 8 + true + read-only + + 0x0 + + + Rx Valid Data + Rx Valid Data + Indicates if the receive register has valid data: + 0 - Receive register is empty. + 1 - Receive register has valid data. + + 0 + 1 + true + read-only + + 0 + 0 + + false + + + Tx Used + Tx Used + Indicates if the transmit register is in use: + 0 - Transmit register is not in use. + 1 - Transmit register is in use. + + 3 + 1 + true + read-only + + 0 + 0 + + false + + + Overrun Error + Overrun Error + Indicates that an overrun error has occurred: + 0 - No overrun has occurred. + 1 - An overrun has occurred. + + 5 + 1 + true + read-only + + 0 + 0 + + false + + + Frame Error + Frame Error + Indicates that an frame error has occurred: + 0 - No frame error has occurred. + 1 - A frame error has occurred. + + 6 + 1 + true + read-only + + 0 + 0 + + false + + + Parity Error + Parity Error + Indicates that a parity error has occurred: + 0 - No parity error has occurred. + 1 - A parity error occurred. + + 7 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ MODE + Interrupt Mode Register + Interrupt Mode Register + 0xC + 17 + true + write-only + + 0x0 + + + IRQ Mode + IRQ Mode + Interrupt Mode. +For each bit: + W - When written with 1 the corresponding interrupt will use fast mode. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + GPO 1 + General Purpose Output 1 Register + General Purpose Output 1 Register + 0x10 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 2 + General Purpose Output 2 Register + General Purpose Output 2 Register + 0x14 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 3 + General Purpose Output 3 Register + General Purpose Output 3 Register + 0x18 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 4 + General Purpose Output 4 Register + General Purpose Output 4 Register + 0x1C + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 1 + General Purpose Input 1 Register + General Purpose Input 1 Register + 0x20 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 2 + General Purpose Input 2 Register + General Purpose Input 2 Register + 0x24 + 32 + true + read-only + + 0 + + + CPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 3 + General Purpose Input 3 Register + General Purpose Input 3 Register + 0x28 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 4 + General Purpose Input 4 Register + General Purpose Input 4 Register + 0x2C + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ STATUS + Interrupt Status Register + Interrupt Status Register + 0x30 + 17 + true + read-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC Interrupt + External interrupt input signal + Interrupt Status Register. +For each bit: + R - Reads active interrupt signal. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ PENDING + Interrupt Pending Register + Interrupt Pending Register + 0x34 + 17 + true + read-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC Interrupt + Enabled interrupt events that have occurred + Interrupt Pending. +For each bit: + R - Reads enabled interrupt event that has occurred. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ ENABLE + Interrupt Enable Register + Interrupt Enable Register + 0x38 + 17 + true + write-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt enabled. + 0 + 1 + true + write-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt enabled. + 1 + 1 + true + write-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt enabled. + 2 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 interrupt enabled. + 3 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 interrupt enabled. + 4 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 interrupt enabled. + 5 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 interrupt enabled. + 6 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 interrupt enabled. + 7 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 interrupt enabled. + 8 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 interrupt enabled. + 9 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 interrupt enabled. + 10 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 interrupt enabled. + 11 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 interrupt enabled. + 12 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 interrupt enabled. + 13 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 interrupt enabled. + 14 + 1 + true + write-only + + 0 + 0 + + false + + + INTC Interrupt + Enable external interrupt input signals + Interrupt Enable. +For each bit: + W - Enable external interrupt input signal. + + 16 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ ACK + Interrupt Acknowledge Register + Interrupt Acknowledge Register + 0x3C + 17 + true + write-only + + 0x0 + + + IRQ Acknowledge + IRQ Acknowledge + Interrupt Acknowledge. +For each bit: + W - When written with 1 clear bit in IRQ_STATUS and IRQ_PENDING. + + 0 + 17 + true + write-only + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + PIT1 PRELOAD + PIT 1 Preload Register + PIT 1 Preload Register + 0x40 + 32 + true + write-only + + 0x0 + + + PIT1 Preload + PIT1 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1 COUNTER + PIT 1 Counter Register + PIT 1 Counter Register + 0x44 + 32 + true + read-only + + 0x0 + + + PIT1 Counter + PIT1 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1 CONTROL + PIT 1 Control Register + PIT 1 Control Register + 0x48 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT1_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART BAUD + UART Programmable Baud Rate + UART Programmable Baud Rate + 0x4C + 8 + true + write-only + + 0x0 + + + UART BAUD + Baud Rate + Programmable UART Baud Rate. + 0 + 20 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 PRELOAD + PIT 2 Preload Register + PIT 2 Preload Register + 0x50 + 32 + true + write-only + + 0x0 + + + PIT2 Preload + PIT2 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 COUNTER + PIT 2 Counter Register + PIT 2 Counter Register + 0x54 + 32 + true + read-only + + 0x0 + + + PIT2 Counter + PIT2 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 CONTROL + PIT 2 Control Register + PIT 2 Control Register + 0x58 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT2_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 PRELOAD + PIT 3 Preload Register + PIT 3 Preload Register + 0x60 + 32 + true + write-only + + 0x0 + + + PIT3 Preload + PIT3 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 COUNTER + PIT 3 Counter Register + PIT 3 Counter Register + 0x64 + 32 + true + read-only + + 0x0 + + + PIT3 Counter + PIT3 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 CONTROL + PIT 3 Control Register + PIT 3 Control Register + 0x68 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT3_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 PRELOAD + PIT 4 Preload Register + PIT 4 Preload Register + 0x70 + 32 + true + write-only + + 0x0 + + + PIT4 Preload + PIT4 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 COUNTER + PIT 4 Counter Register + PIT 4 Counter Register + 0x74 + 32 + true + read-only + + 0x0 + + + PIT4 Counter + PIT4 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 CONTROL + PIT 4 Control Register + PIT 4 Control Register + 0x78 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT4_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 0 + Interrupt Vector Register 0 + Interrupt Vector Register 0 + 0x80 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 0 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 1 + Interrupt Vector Register 1 + Interrupt Vector Register 1 + 0x84 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 1 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 2 + Interrupt Vector Register 2 + Interrupt Vector Register 2 + 0x88 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 2 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 3 + Interrupt Vector Register 3 + Interrupt Vector Register 3 + 0x8C + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 3 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 4 + Interrupt Vector Register 4 + Interrupt Vector Register 4 + 0x90 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 4 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 5 + Interrupt Vector Register 5 + Interrupt Vector Register 5 + 0x94 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 5 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 6 + Interrupt Vector Register 6 + Interrupt Vector Register 6 + 0x98 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 6 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 7 + Interrupt Vector Register 7 + Interrupt Vector Register 7 + 0x9C + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 7 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 8 + Interrupt Vector Register 8 + Interrupt Vector Register 8 + 0xA0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 8 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 9 + Interrupt Vector Register 9 + Interrupt Vector Register 9 + 0xA4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 9 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 10 + Interrupt Vector Register 10 + Interrupt Vector Register 10 + 0xA8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 10 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 11 + Interrupt Vector Register 11 + Interrupt Vector Register 11 + 0xAC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 11 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 12 + Interrupt Vector Register 12 + Interrupt Vector Register 12 + 0xB0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 12 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 13 + Interrupt Vector Register 13 + Interrupt Vector Register 13 + 0xB4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 13 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 14 + Interrupt Vector Register 14 + Interrupt Vector Register 14 + 0xB8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 14 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 16 + Interrupt Vector Register 16 + Interrupt Vector Register 16 + 0xC0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 16 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + IRQ VECTOR 17 + Interrupt Vector Register 17 + Interrupt Vector Register 17 + 0xC4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 17 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 18 + Interrupt Vector Register 18 + Interrupt Vector Register 18 + 0xC8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 18 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 19 + Interrupt Vector Register 19 + Interrupt Vector Register 19 + 0xCC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 19 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 20 + Interrupt Vector Register 20 + Interrupt Vector Register 20 + 0xD0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 20 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 21 + Interrupt Vector Register 21 + Interrupt Vector Register 21 + 0xD4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 21 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 22 + Interrupt Vector Register 22 + Interrupt Vector Register 22 + 0xD8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 22 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 23 + Interrupt Vector Register 23 + Interrupt Vector Register 23 + 0xDC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 23 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 24 + Interrupt Vector Register 24 + Interrupt Vector Register 24 + 0xE0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 24 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 25 + Interrupt Vector Register 25 + Interrupt Vector Register 25 + 0xE4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 25 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 26 + Interrupt Vector Register 26 + Interrupt Vector Register 26 + 0xE8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 26 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 27 + Interrupt Vector Register 27 + Interrupt Vector Register 27 + 0xEC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 27 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 28 + Interrupt Vector Register 28 + Interrupt Vector Register 28 + 0xF0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 28 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 29 + Interrupt Vector Register 29 + Interrupt Vector Register 29 + 0xF4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 29 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 30 + Interrupt Vector Register 30 + Interrupt Vector Register 30 + 0xF8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector 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GLOBAL + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_2/bd_9d69_ilmb_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_2/bd_9d69_ilmb_0.xml new file mode 100644 index 0000000..1288881 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_2/bd_9d69_ilmb_0.xml @@ -0,0 +1,3323 @@ + + + xilinx.com + customized_ip + bd_9d69_ilmb_0 + 1.0 + + + LMB_Sl_0 + LMB_Sl_00 + Local Memory Bus Mirrored Slave interface 0 + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + 0 + 0 + + + + + + READDBUS + + + Sl_DBus + + 0 + 31 + + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + 0 + 0 + + + + + + RST + + + LMB_Rst + + + + + UE + + + Sl_UE + + 0 + 0 + + + + + + WAIT + + + Sl_Wait + + 0 + 0 + + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + 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peripherals and BRAM + + + C_LMB_DWIDTH + C Lmb Dwidth + 32 + + + + true + + + + + + C_LMB_AWIDTH + C Lmb Awidth + 32 + + + + true + + + + + + C_EXT_RESET_HIGH + C Ext Reset High + 1 + + + + true + + + + + + C_LMB_NUM_SLAVES + LMB Number of Slaves + 2 + + + + true + + + + + + Component_Name + bd_9d69_ilmb_0 + + + + + Local Memory Bus (LMB) 1.0 + 9 + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xci new file mode 100644 index 0000000..9a5c4db --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xci @@ -0,0 +1,115 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9d69_dlmb_0 + + + + 100000000 + 0.000 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 1 + 32 + 32 + 3 + 1 + 32 + 32 + 3 + bd_9d69_dlmb_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 9 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xml new file mode 100644 index 0000000..9a9bb29 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xml @@ -0,0 +1,3325 @@ + + + xilinx.com + customized_ip + bd_9d69_dlmb_0 + 1.0 + + + LMB_Sl_0 + LMB_Sl_00 + Local Memory Bus Mirrored Slave interface 0 + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + 0 + 0 + + + + + + READDBUS + + + Sl_DBus + + 0 + 31 + + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + 0 + 0 + + + + + + RST + + + LMB_Rst + + + + + UE + + + Sl_UE + + 0 + 0 + + + + + + WAIT + + + Sl_Wait + + 0 + 0 + + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + true + + + + + + LMB_Sl_1 + LMB_Sl_01 + Local Memory Bus Mirrored Slave interface 1 + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + 1 + 1 + + + + + + READDBUS + + + Sl_DBus + + 32 + 63 + + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + 1 + 1 + + + + + + RST + + + LMB_Rst + + + + + UE + + + Sl_UE + + 1 + 1 + + + + + + WAIT + + + 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LMB_M + Local Memory Bus Mirrored Master interface + + + + + + + ABUS + + + M_ABus + + + + + ADDRSTROBE + + + M_AddrStrobe + + + + + BE + + + M_BE + + + + + CE + + + LMB_CE + + + + + READDBUS + + + LMB_ReadDBus + + + + + READSTROBE + + + M_ReadStrobe + + + + + READY + + + LMB_Ready + + + + + RST + + + LMB_Rst + + + + + UE + + + LMB_UE + + + + + WAIT + + + LMB_Wait + + + + + WRITEDBUS + + + M_DBus + + + + + WRITESTROBE + + + M_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M + + + ASSOCIATED_RESET + SYS_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.SYS_Rst + SYS_Rst + Reset + + + + + + + RST + + + SYS_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + + + LMB_Channel + LMB_M + LMB_Sl_0 + LMB_Sl_1 + LMB_Sl_2 + LMB_Sl_3 + LMB_Sl_4 + LMB_Sl_5 + LMB_Sl_6 + LMB_Sl_7 + LMB_Sl_8 + LMB_Sl_9 + LMB_Sl_10 + LMB_Sl_11 + LMB_Sl_12 + LMB_Sl_13 + LMB_Sl_14 + LMB_Sl_15 + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + + + SYS_Rst + + in + + + std_logic + dummy_view + + + + + + LMB_Rst + + out + + + std_logic + dummy_view + + + + + + M_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + M_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + M_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + M_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + M_DBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + M_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + in + + 0 + 95 + + + + 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std_logic + dummy_view + + + + + + LMB_BE + + out + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + + + + + C_LMB_NUM_SLAVES + LMB Number of Slaves + 3 + + + C_LMB_DWIDTH + C Lmb Dwidth + 32 + + + C_LMB_AWIDTH + C Lmb Awidth + 32 + + + C_EXT_RESET_HIGH + C Ext Reset High + 1 + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_4873554b + 0 + 1 + + + The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM + + + C_LMB_DWIDTH + C Lmb Dwidth + 32 + + + + true + + + + + + C_LMB_AWIDTH + C Lmb Awidth + 32 + + + + true + + + + + + C_EXT_RESET_HIGH + C Ext Reset High + 1 + + + + true + + + + + + C_LMB_NUM_SLAVES + LMB Number of Slaves + 3 + + + + true + + + + + + Component_Name + bd_9d69_dlmb_0 + + + + + Local Memory Bus (LMB) 1.0 + 9 + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xci new file mode 100644 index 0000000..fb5397e --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9d69_dlmb_cntlr_0 + + + NONE + 65536 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000000000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000000000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_9d69_dlmb_cntlr_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 15 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xml new file mode 100644 index 0000000..24fa55f --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xml @@ -0,0 +1,3874 @@ + + + xilinx.com + customized_ip + bd_9d69_dlmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + 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Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000000000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x000000000000FFFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x00000000C0010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_9d69_dlmb_cntlr_0 + + + + + LMB BRAM Controller + 15 + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xci new file mode 100644 index 0000000..28a22df --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9d69_ilmb_cntlr_0 + + + NONE + 65536 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000000000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000000000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_9d69_ilmb_cntlr_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 15 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xml new file mode 100644 index 0000000..9cb924d --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xml @@ -0,0 +1,3874 @@ + + + xilinx.com + customized_ip + bd_9d69_ilmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + 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15 + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xci new file mode 100644 index 0000000..844f27d --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xci @@ -0,0 +1,275 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9d69_lmb_bram_I_0 + + + 4096 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + BRAM_CTRL + NONE + 65536 + 32 + READ_WRITE + BRAM_CTRL + NONE + 65536 + 32 + READ_WRITE + + 100000000 + 0.000 + 32 + 32 + 1 + 4 + 0 + 1 + 8 + 0 + 0 + 16 + NONE + 0 + 0 + 0 + ./ + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + Estimated Power for IP : 19.660986 mW + virtexuplus + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + bd_9d69_lmb_bram_I_0.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 16384 + 16384 + 32 + 32 + 0 + 0 + CE + CE + ALL + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 4 + 4 + 16384 + 16384 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 8 + NONE + no_coe_file_loaded + ALL + bd_9d69_lmb_bram_I_0 + false + false + false + false + false + true + false + false + true + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + false + Native + false + bd_9d69_lmb_bram_I_0.mem + True_Dual_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + true + false + false + false + true + true + 16384 + 32 + 32 + No_ECC + false + false + false + BRAM_Controller + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 1 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xml new file mode 100644 index 0000000..7d7be46 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xml @@ -0,0 +1,4056 @@ + + + xilinx.com + customized_ip + bd_9d69_lmb_bram_I_0 + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn 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choice_pairs_246d8066 + WRITE_FIRST + READ_FIRST + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_9d69_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false 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a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_7/bd_9d69_second_dlmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_7/bd_9d69_second_dlmb_cntlr_0.xci new file mode 100644 index 0000000..c271cb4 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_7/bd_9d69_second_dlmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9d69_second_dlmb_cntlr_0 + + + NONE + 32768 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000010000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x0000000000017FFF + 0 + 32 + 32 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000010000 + 0 + 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frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable 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false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_9d69_second_dlmb_cntlr_0 + + + + + LMB BRAM Controller + 15 + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xci new file mode 100644 index 0000000..0f09db1 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9d69_second_ilmb_cntlr_0 + + + NONE + 32768 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000010000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x0000000000017FFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000010000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x0000000000017FFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_9d69_second_ilmb_cntlr_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 15 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xml new file mode 100644 index 0000000..ed60d02 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xml @@ -0,0 +1,3874 @@ + + + xilinx.com + customized_ip + bd_9d69_second_ilmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 32768 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + 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+ C_HAS_MEM_OUTPUT_REGS_B + 0 + + + C_HAS_MUX_OUTPUT_REGS_A + 0 + + + C_HAS_MUX_OUTPUT_REGS_B + 0 + + + C_MUX_PIPELINE_STAGES + 0 + + + C_HAS_SOFTECC_INPUT_REGS_A + 0 + + + C_HAS_SOFTECC_OUTPUT_REGS_B + 0 + + + C_USE_SOFTECC + 0 + + + C_USE_ECC + 0 + + + C_EN_ECC_PIPE + 0 + + + C_HAS_INJECTERR + 0 + + + C_SIM_COLLISION_CHECK + ALL + + + C_COMMON_CLK + 0 + + + C_DISABLE_WARN_BHV_COLL + 0 + + + C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 1 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 8 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 17.246228 mW + + + + + + choice_list_0132492a + 32 + 64 + 128 + + + choice_list_302d3091 + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_6fc15197 + 32 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f9a6a28b + Native + + + choice_pairs_1f270a52 + BRAM_Controller + Stand_Alone + + + choice_pairs_246d8066 + WRITE_FIRST + READ_FIRST + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_9d69_second_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A 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TRACE_dcache_read + + + + + DCACHE_REQ + + + TRACE_dcache_req + + + + + DELAY_SLOT + + + TRACE_delay_slot + + + + + EX_PIPERUN + + + TRACE_ex_piperun + + + + + EXCEPTION_KIND + + + TRACE_exception_kind + + + + + EXCEPTION_TAKEN + + + TRACE_exception_taken + + + + + ICACHE_HIT + + + TRACE_icache_hit + + + + + ICACHE_RDY + + + TRACE_icache_rdy + + + + + ICACHE_REQ + + + TRACE_icache_req + + + + + INSTRUCTION + + + TRACE_instruction + + + + + JUMP_HIT + + + TRACE_jump_hit + + + + + JUMP_TAKEN + + + TRACE_jump_taken + + + + + MB_HALTED + + + TRACE_mb_halted + + + + + MEM_PIPERUN + + + TRACE_mem_piperun + + + + + MSR_REG + + + TRACE_msr_reg + + + + + NEW_REG_VALUE + + + TRACE_new_reg_value + + + + + OF_PIPERUN + + + TRACE_of_piperun + + + + + PC + + + TRACE_pc + + + + + PID_REG + + + TRACE_pid_reg + + + + + REG_ADDR + + + TRACE_reg_addr + + + + + REG_WRITE + + + TRACE_reg_write + + + + + VALID_INSTR + + + TRACE_valid_instr + + + + + + + + + xilinx_elaborateports + Elaborate Ports + :vivado.xilinx.com:elaborate.ports + + xilinx_elaborateports_view_fileset + + + + outputProductCRC + 8:0a2c987f + + + + + xilinx_elaboratebd + Elaborate BD + :vivado.xilinx.com:elaborate.bd + + xilinx_elaboratebd_view_fileset + + + + outputProductCRC + 8:0a2c987f + + + + + + + Clk + + in + + + std_logic + xilinx_elaborateports + + + + + + Reset + + in + + + std_logic + xilinx_elaborateports + + + + + + TRACE_data_access + + out + + + std_logic + xilinx_elaborateports + + + + + + TRACE_data_address + + out + + 0 + 31 + + + + std_logic_vector + xilinx_elaborateports + + + + + + TRACE_data_byte_enable + + out + + 0 + 3 + + + + std_logic_vector + xilinx_elaborateports + + + + + + TRACE_data_read + + out + + + std_logic + xilinx_elaborateports + + + + + + TRACE_data_write + + out + + + std_logic + xilinx_elaborateports + + + + + + TRACE_data_write_value + + out + + 0 + 31 + + + + std_logic_vector + xilinx_elaborateports + + + + + + TRACE_dcache_hit + + out + + + std_logic + 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+ + + + + + IO_address + + out + + 31 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + + + IO_byte_enable + + out + + 3 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + + + IO_read_data + + in + + 31 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + 0 + + + + + IO_read_strobe + + out + + + std_logic + xilinx_elaborateports + + + + + + IO_ready + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + IO_write_data + + out + + 31 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + + + IO_write_strobe + + out + + + std_logic + xilinx_elaborateports + + + + + + + + + choice_list_ac75ef1e + Custom + + + choice_list_f585525a + 110 + 300 + 1200 + 2400 + 4800 + 9600 + 19200 + 38400 + 57600 + 115200 + 128000 + 230400 + 460800 + 921600 + + + choice_pairs_007f01e9 + 0 + 1 + 2 + 3 + 4 + 5 + 7 + 8 + 9 + + + choice_pairs_0d2d32a8 + 0 + 1 + 2 + + + choice_pairs_4847022f + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 8 + 9 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_5502e96b + 1 + 2 + 3 + 4 + + + choice_pairs_563648c8 + 0 + 1 + + + choice_pairs_5f1e379e + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 9 + + + choice_pairs_7ba91213 + 0 + 1 + 2 + 3 + + + choice_pairs_f0f6eb36 + 0 + 1 + 2 + 3 + 4 + 6 + 7 + 8 + 9 + + + choice_pairs_f7e0b771 + 4096 + 8192 + 12288 + 16384 + 20480 + 24576 + 32768 + 36864 + 40960 + 49152 + 65536 + 69632 + 73728 + 81920 + 98304 + 131072 + + + choice_pairs_ffa336e4 + 0 + 1 + + + + + xilinx_elaborateports_view_fileset + + ../bd_0/bd_9d69.bd + block_diagram + + + + xilinx_elaboratebd_view_fileset + + ../bd_0/bd_9d69.bd + block_diagram + + + + MicroBlaze Micro Controller System (MCS) is a light-weight general purpose micro controller system, based on the MicroBlaze processor. It is primarily intended for simple control applications, where a hardware solution would be less flexible and more difficult to implement. Software development with the Xilinx Software Development Kit (SDK) is supported, including a software driver for the peripherals. Debugging including UART is available either via SDK or directly with the Xilinx Microprocessor Debugger. +The MCS consists of the processor itself, local memory with sizes ranging from 4KB to 128KB, up to 4 Fixed Interval Timers, up to 4 Programmable Interval Timers, up to 4 32-bit General Purpose Output ports, up to 4 32-bit General Purpose Input ports, and an Interrupt Controller with up to 16 external interrupt inputs. + + + + JTAG_CHAIN + Debug JTAG User-defined Register + 2 + + + + false + + + + + + MICROBLAZE_INSTANCE + MicroBlaze Instance Name + microblaze_0 + + + AVOID_PRIMITIVES + 0 + + + PATH + Instance Hierarchical Design Name + mcs_0 + + + FREQ + Input Clock Frequency (MHz) + 100.0 + + + OPTIMIZATION + Select MicroBlaze Optimization + 1 + + + DEBUG_ENABLED + Enable Debug Support + 0 + + + TRACE + Enable MicroBlaze Trace Bus + 1 + + + ECC + Error Correction Code + 0 + + + MEMSIZE + Memory Size + 98304 + + + USE_IO_BUS + Enable IO Bus + 1 + + + USE_UART_RX + Enable Receiver + 0 + + + + true + + + + + + USE_UART_TX + Enable Transmitter + 0 + + + + true + + + + + + UART_BAUDRATE + Define Baud Rate + 9600 + + + + false + + + + + + UART_PROG_BAUDRATE + Programmable Baud Rate + 0 + + + + false + + + + + + UART_DATA_BITS + Number of Data Bits + 8 + + + + false + + + + + + UART_USE_PARITY + Use Parity + 0 + + + + false + + + + + + UART_ODD_PARITY + Even or Odd Parity + 0 + + + + false + + + + + + UART_RX_INTERRUPT + Implement Receive Interrupt + 0 + + + + false + + + + + + UART_TX_INTERRUPT + Implement Transmit Interrupt + 0 + + + + false + + + + + + UART_ERROR_INTERRUPT + Implement Error Interrupt + 0 + + + + false + + + + + + USE_FIT1 + Use Timer + 0 + + + FIT1_No_CLOCKS + Number of Clocks Between Strobes + 6216 + + + + false + + + + + + FIT1_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_FIT2 + Use Timer + 0 + + + FIT2_No_CLOCKS + Number of Clocks Between Strobes + 6216 + + + + false + + + + + + FIT2_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_FIT3 + Use Timer + 0 + + + FIT3_No_CLOCKS + Number of Clocks Between Strobes + 6216 + + + + false + + + + + + FIT3_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_FIT4 + Use Timer + 0 + + + FIT4_No_CLOCKS + Number of Clocks Between Strobes + 6216 + + + + false + + + + + + FIT4_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_PIT1 + Use Timer + 0 + + + PIT1_SIZE + Number of Bits for Timer + 32 + + + + false + + + + + + PIT1_READABLE + Shall Counter Value Be Readable + 1 + + + + false + + + + + + PIT1_PRESCALER + Define Prescaler + 0 + + + + false + + + + + + PIT1_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_PIT2 + Use Timer + 0 + + + PIT2_SIZE + Number of Bits for Timer + 32 + + + + false + + + + + + PIT2_READABLE + Shall Counter Value Be Readable + 1 + + + + false + + + + + + PIT2_PRESCALER + Define Prescaler + 0 + + + + false + + + + + + PIT2_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_PIT3 + Use Timer + 0 + + + PIT3_SIZE + Number of Bits for Timer + 32 + + + + false + + + + + + PIT3_READABLE + Shall Counter Value Be Readable + 1 + + + + false + + + + + + PIT3_PRESCALER + Define Prescaler + 0 + + + + false + + + + + + PIT3_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_PIT4 + Use Timer + 0 + + + PIT4_SIZE + Number of Bits for Timer + 32 + + + + false + + + + + + PIT4_READABLE + Shall Counter Value Be Readable + 1 + + + + false + + + + + + PIT4_PRESCALER + Define Prescaler + 0 + + + + false + + + + + + PIT4_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_GPO1 + Use GPO + 0 + + + + true + + + + + + GPO1_SIZE + Number of Bits + 32 + + + + false + + + + + + GPO1_INIT + Initial Value of GPO + 0x00000000 + + + + false + + + + + + USE_GPO2 + Use GPO + 0 + + + + true + + + + + + GPO2_SIZE + Number of Bits + 32 + + + + false + + + + + + GPO2_INIT + Initial Value of GPO + 0x00000000 + + + + false + + + + + + USE_GPO3 + Use GPO + 0 + + + + true + + + + + + GPO3_SIZE + Number of Bits + 32 + + + + false + + + + + + GPO3_INIT + Initial Value of GPO + 0x00000000 + + + + false + + + + + + USE_GPO4 + Use GPO + 0 + + + + true + + + + + + GPO4_SIZE + Number of Bits + 32 + + + + false + + + + + + GPO4_INIT + Initial Value of GPO + 0x00000000 + + + + false + + + + + + USE_GPI1 + Use GPI + 0 + + + + true + + + + + + GPI1_SIZE + Number of Bits + 32 + + + + false + + + + + + GPI1_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_GPI2 + Use GPI + 0 + + + + true + + + + + + GPI2_SIZE + Number of Bits + 32 + + + + false + + + + + + GPI2_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_GPI3 + Use GPI + 0 + + + + true + + + + + + GPI3_SIZE + Number of Bits + 32 + + + + false + + + + + + GPI3_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_GPI4 + Use GPI + 0 + + + + true + + + + + + GPI4_SIZE + Number of Bits + 32 + + + + false + + + + + + GPI4_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + INTC_USE_EXT_INTR + Use External Interrupts + 0 + + + INTC_INTR_SIZE + Number of External Inputs + 1 + + + + false + + + + + + INTC_LEVEL_EDGE + Level or Edge of External Interrupts + 0x0000 + + + + false + + + + + + INTC_POSITIVE + Positive or Negative External Interrupts + 0xFFFF + + + + false + + + + + + INTC_ASYNC_INTR + Interrupts asynchronous + The setting of each bit in this option indicates whether the incoming interrupt is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous. + 0xFFFF + + + + false + + + + + + INTC_NUM_SYNC_FF + Number of synchronization flip-flops + Number of synchronization flip-flops used to synchronize asynchronous interupt inputs + 2 + + + Component_Name + phy_ddr4_x8_microblaze_mcs + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_BOARD_INTERFACE + Custom + + + + true + + + + + + RESET_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO1_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO2_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO3_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO4_BOARD_INTERFACE + Custom + + + + true + + + + + + UART_BOARD_INTERFACE + Custom + + + + true + + + + + + + + MicroBlaze MCS + + XPM_MEMORY + + 9 + + true + subcore + + + + + + + + + + + + + + + 2018.2 + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xci new file mode 100644 index 0000000..39a8207 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xci @@ -0,0 +1,655 @@ + + + xilinx.com + xci + unknown + 1.0 + + + phy_ddr4_x8_phy + + + 17 + 0 + 0 + 0 + 2 + HP_IO + 2 + X0Y11 + X0Y10 + X0Y70 + X0Y11 + 12 + DDR4_SDRAM + 1 + 0 + 0 + 2 + 1 + 10000 + 10 + 2 + 8 + 5 + 9 + 9 + 9 + 72 + {{9{2'b01}}, {3{2'b00}}} + { 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, + 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111110011, + 15'b111111111111111, 15'b111111111111111 } + 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b +000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, + 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_000_000_000_001_000_001_001_001_001_001_001_001, 39'b001_001_001_000_000_001_001_001_00 +1_001_001_001_001, 39'b000_001_001_001_001_101_101_001_001_001_001_001_001 + false + 1 + 8 + 72 + 0 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + {{9{2'b11}}, {3{2'b00}}} + 12'b000000000000 + 1 + 3 + 2 + {13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b01111 +01111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0000101111111, 13'b1110011111111, + 13'b0111101111111 } + { 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, + 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b000010_11_11111_11, + 15'b111001_11_11111_11, 15'b011111_11_11111_11 } + {12{2'b11}} + FALSE + 1 + { 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000 +011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000101111111, 13'b1110011111111, + 13'b0111111111111 } + 1 + 1 + 4 + 1500 + 2 + 5 + 10 + 60 + 256 + DDR4_SDRAM + 15 + 9 + VCO + 10 + 9 + true + false + 1 + DM_NO_DBI + 72 + false + 0 + No + 10000 + 833 + MTA18ASF2G72PDZ-2G3 + RDIMMs + 1.2V + 4:1 + false + false + Single + 1 + 1500 + 0.84 + no_file_loaded + false + 0 + 0 + 0 + 0 + NONE + phy_ddr4_x8_phy + false + Disable + false + 1 + 1 + false + Phy_Only_Single + false + BFM + Differential + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE 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C0.LR_WIDTH + LR WIDTH + 1 + + + C0.CK_WIDTH + CK WIDTH + 1 + + + C0.CKE_WIDTH + CKE WIDTH + 2 + + + C0.CS_WIDTH + CS WIDTH + 2 + + + C0.ODT_WIDTH + ODT WIDTH + 2 + + + C0.StackHeight + 1 + + + PING_PONG_PHY + Ping Pong Phy + 1 + + + + + DDR4 SDRAM (MIG) + 5 + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + -- cgit v1.2.3