From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- projects/XUSP3R/.gitignore | 6 + .../axis_clock_converter/axis_clock_converter.xci | 112 + .../axis_clock_converter/axis_clock_converter.xml | 1406 + .../sources_1/ip/instr_blk_mem/instr_blk_mem.xci | 264 + .../sources_1/ip/instr_blk_mem/instr_blk_mem.xml | 4053 ++ .../ip/instr_blk_mem_sim/instr_blk_mem_sim.xci | 265 + .../ip/instr_blk_mem_sim/instr_blk_mem_sim.xml | 4054 ++ .../sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd | 441 + .../sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml | 100 + .../ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v | 173 + .../bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci | 955 + .../bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xml | 26887 +++++++++ .../ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xci | 71 + .../ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xml | 583 + .../bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xci | 272 + .../bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xml | 7497 +++ .../ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci | 113 + .../ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xml | 3323 ++ .../ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xci | 115 + .../ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xml | 3325 ++ .../phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci | 152 + .../phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml | 3874 ++ .../phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci | 152 + .../phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xml | 3874 ++ .../phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci | 275 + .../phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml | 4056 ++ .../bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xml | 3874 ++ .../bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xml | 3874 ++ .../bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci | 275 + .../bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xml | 4056 ++ .../ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci | 150 + .../ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml | 2149 + .../sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci | 655 + .../sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xml | 4864 ++ .../XUSP3R.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci | 406 + .../XUSP3R.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml | 8571 +++ .../sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd | 441 + .../sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml | 100 + .../ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v | 173 + .../bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci | 955 + .../bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xml | 26887 +++++++++ .../bd_0/ip/ip_1/bd_ba6a_rst_0_0.xci | 71 + .../bd_0/ip/ip_1/bd_ba6a_rst_0_0.xml | 583 + .../bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xci | 272 + .../bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml | 7497 +++ .../phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xci | 113 + .../phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xml | 3323 ++ .../phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xci | 115 + .../phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xml | 3325 ++ .../bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xml | 3874 ++ .../bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xml | 3874 ++ .../bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xci | 275 + .../bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xml | 4056 ++ .../bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xml | 3874 ++ .../bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xml | 3874 ++ .../bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xci | 275 + .../bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xml | 4056 ++ .../ip_0/phy_ddr4_udimm_microblaze_mcs.xci | 150 + .../ip_0/phy_ddr4_udimm_microblaze_mcs.xml | 2141 + .../ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xci | 655 + .../ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xml | 4864 ++ .../sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xci | 398 + .../sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xml | 8558 +++ .../sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bd | 441 + .../sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bxml | 100 + .../ip/phy_ddr4_x8/bd_0/hdl/bd_9d69_wrapper.v | 173 + .../bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xci | 955 + .../bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xml | 26887 +++++++++ .../phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xci | 71 + .../phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xml | 583 + .../bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xci | 272 + .../bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xml | 7497 +++ .../ip/phy_ddr4_x8/bd_0/ip/ip_2/bd_9d69_ilmb_0.xci | 113 + .../ip/phy_ddr4_x8/bd_0/ip/ip_2/bd_9d69_ilmb_0.xml | 3323 ++ .../ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xci | 115 + .../ip/phy_ddr4_x8/bd_0/ip/ip_3/bd_9d69_dlmb_0.xml | 3325 ++ .../bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_4/bd_9d69_dlmb_cntlr_0.xml | 3874 ++ .../bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xml | 3874 ++ .../bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xci | 275 + .../bd_0/ip/ip_6/bd_9d69_lmb_bram_I_0.xml | 4056 ++ .../bd_0/ip/ip_7/bd_9d69_second_dlmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_7/bd_9d69_second_dlmb_cntlr_0.xml | 3874 ++ .../bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xci | 152 + .../bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xml | 3874 ++ .../bd_0/ip/ip_9/bd_9d69_second_lmb_bram_I_0.xci | 275 + .../bd_0/ip/ip_9/bd_9d69_second_lmb_bram_I_0.xml | 4056 ++ .../ip_0/phy_ddr4_x8_microblaze_mcs.xci | 150 + .../ip_0/phy_ddr4_x8_microblaze_mcs.xml | 2141 + .../ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xci | 655 + .../ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xml | 4864 ++ .../sources_1/ip/phy_ddr4_x8/phy_ddr4_x8.xci | 401 + .../sources_1/ip/phy_ddr4_x8/phy_ddr4_x8.xml | 8591 +++ .../sources_1/ip/pr_read_mem/pr_read_mem.xci | 266 + .../sources_1/ip/pr_read_mem/pr_read_mem.xml | 4053 ++ .../sources_1/ip/pr_ref_mem/pr_ref_mem.xci | 266 + .../sources_1/ip/pr_ref_mem/pr_ref_mem.xml | 4055 ++ .../sources_1/ip/rdback_fifo/rdback_fifo.xci | 536 + .../sources_1/ip/rdback_fifo/rdback_fifo.xml | 10635 ++++ .../sources_1/ip/scratchpad/scratchpad.xci | 263 + .../sources_1/ip/scratchpad/scratchpad.xml | 4052 ++ .../ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xci | 1430 + .../ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xml | 22832 ++++++++ .../sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xci | 1159 + .../sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml | 25761 +++++++++ .../ip/xdma/ip_1/xdma_v4_1_1_blk_mem_64_reg_be.xci | 274 + .../ip/xdma/ip_1/xdma_v4_1_1_blk_mem_64_reg_be.xml | 4061 ++ .../xdma/ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xci | 274 + .../xdma/ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xml | 4061 ++ .../XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/xdma.xci | 1786 + .../XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/xdma.xml | 56296 +++++++++++++++++++ .../sources_1/ip/zq_calib_mem/zq_calib_mem.xci | 266 + .../sources_1/ip/zq_calib_mem/zq_calib_mem.xml | 4054 ++ projects/XUSP3R/XUSP3R.xpr | 836 + projects/XUSP3R/apply_patches.sh | 12 + projects/XUSP3R/coe/pr_read.coe | 15 + projects/XUSP3R/coe/pr_ref.coe | 51 + projects/XUSP3R/coe/pr_zq.coe | 42 + projects/XUSP3R/constraints/x4_1R_RDIMM.xdc | 184 + projects/XUSP3R/constraints/x8_1R_RDIMM.xdc | 174 + projects/XUSP3R/constraints/x8_1R_UDIMM.xdc | 160 + projects/XUSP3R/constraints/x8_2R_RDIMM.xdc | 177 + projects/XUSP3R/patches/rd_en.patch | 492 + projects/XUSP3R/patches/write.patch | 124 + projects/XUSP3R/verilog/ddr4_adapter.v | 361 + projects/XUSP3R/verilog/ddr4_mc_odt.v | 130 + projects/XUSP3R/verilog/project.vh | 21 + projects/XUSP3R/verilog/softmc_top.v | 842 + 135 files changed, 416387 insertions(+) create mode 100644 projects/XUSP3R/.gitignore create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xml create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xci create mode 100644 projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xml create mode 100644 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b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci @@ -0,0 +1,112 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axis_clock_converter + + + + 100000000 + 1 + 1 + 1 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + ACTIVE_LOW + + + + 100000000 + 0.000 + ACTIVE_LOW + + 100000000 + 1 + 1 + 1 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + ACTIVE_LOW + + + + 100000000 + 0.000 + ACTIVE_LOW + 0 + 0b00000000000000000000000000011011 + 256 + 1 + 1 + 1 + virtexuplus + 1 + 2 + 2 + 1 + 0 + 1:2 + axis_clock_converter + 1 + 1 + 0 + 1 + 2 + 32 + 0 + 0 + 0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Flow + 18 + TRUE + . + + . + 2018.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml new file mode 100644 index 0000000..f025496 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml @@ -0,0 +1,1406 @@ + + + xilinx.com + customized_ip + axis_clock_converter + 1.0 + + + S_AXIS + S_AXIS + + + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TDATA + + + s_axis_tdata + + + + + TSTRB + + + s_axis_tstrb + + + + + TKEEP + + + s_axis_tkeep + + + + + TLAST + + + s_axis_tlast + + + + + TID + + + s_axis_tid + + + + + TDEST + + + s_axis_tdest + + + + + TUSER + + + s_axis_tuser + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + M_AXIS + M_AXIS + + + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + TDATA + + + m_axis_tdata + + + + + TSTRB + + + m_axis_tstrb + + + + + TKEEP + + + m_axis_tkeep + + + + + TLAST + + + m_axis_tlast + + + + + TID + + + m_axis_tid + + + + + TDEST + + + m_axis_tdest + + + + + TUSER + + + m_axis_tuser + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + S_RSTIF + S_RSTIF + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + + + M_RSTIF + M_RSTIF + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + 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+ + C_AXIS_SIGNAL_SET + 0b00000000000000000000000000011011 + + + C_IS_ACLK_ASYNC + 1 + + + C_SYNCHRONIZER_STAGE + 2 + + + C_S_AXIS_ACLK_RATIO + 1 + + + C_M_AXIS_ACLK_RATIO + 2 + + + C_ACLKEN_CONV_MODE + 0 + + + + + + choice_list_27ecedf0 + 16:1 + 15:1 + 14:1 + 13:1 + 12:1 + 11:1 + 10:1 + 9:1 + 8:1 + 7:1 + 6:1 + 5:1 + 4:1 + 3:1 + 2:1 + 1:1 + 1:2 + 1:3 + 1:4 + 1:5 + 1:6 + 1:7 + 1:8 + 1:9 + 1:10 + 1:11 + 1:12 + 1:13 + 1:14 + 1:15 + 1:16 + + + choice_pairs_37189c7b + 0 + 1 + + + choice_pairs_7e3eb5e2 + 0 + 1 + 2 + 3 + + + The AXI4-Stream Clock Converter IP provides the infrastructure to change the clocking rate between a AXI4-Stream master and slave. + + + TDATA_NUM_BYTES + TDATA Width (bytes) + 32 + + + + true + + + + + + TID_WIDTH + TID Width (bits) + 0 + + + + true + + + + + + TDEST_WIDTH + TDEST Width (bits) + 0 + + + + true + + + + + + TUSER_WIDTH + TUSER Width (bits) + 0 + + + + true + + + + + + IS_ACLK_ASYNC + Asynchronous Clocks + 1 + + + + true + + + + + + HAS_TSTRB + Enable TSTRB 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choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + instr_blk_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + 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+ C_WRITE_MODE_A + WRITE_FIRST + + + C_WRITE_WIDTH_A + 64 + + + C_READ_WIDTH_A + 64 + + + C_WRITE_DEPTH_A + 1024 + + + C_READ_DEPTH_A + 1024 + + + C_ADDRA_WIDTH + 10 + + + C_HAS_RSTB + 0 + + + C_RST_PRIORITY_B + CE + + + C_RSTRAM_B + 0 + + + C_INITB_VAL + 0 + + + C_HAS_ENB + 0 + + + C_HAS_REGCEB + 0 + + + C_USE_BYTE_WEB + 0 + + + C_WEB_WIDTH + 1 + + + C_WRITE_MODE_B + WRITE_FIRST + + + C_WRITE_WIDTH_B + 64 + + + C_READ_WIDTH_B + 64 + + + C_WRITE_DEPTH_B + 1024 + + + C_READ_DEPTH_B + 1024 + + + C_ADDRB_WIDTH + 10 + + + C_HAS_MEM_OUTPUT_REGS_A + 0 + + + C_HAS_MEM_OUTPUT_REGS_B + 0 + + + C_HAS_MUX_OUTPUT_REGS_A + 0 + + + C_HAS_MUX_OUTPUT_REGS_B + 0 + + + C_MUX_PIPELINE_STAGES + 0 + + + C_HAS_SOFTECC_INPUT_REGS_A + 0 + + + C_HAS_SOFTECC_OUTPUT_REGS_B + 0 + + + C_USE_SOFTECC + 0 + + + C_USE_ECC + 0 + + + C_EN_ECC_PIPE + 0 + + + C_HAS_INJECTERR + 0 + + + C_SIM_COLLISION_CHECK + ALL + + + C_COMMON_CLK + 0 + + + C_DISABLE_WARN_BHV_COLL + 0 + + + C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 0 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 2 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 4.238151 mW + + + + + + choice_list_0e6ad450 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + instr_blk_mem_sim + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + false + + + + + + RD_ADDR_CHNG_B + false + + + + false + + + + + + Use_Error_Injection_Pins + false + + + + false + + + + + + Error_Injection_Type + Single_Bit_Error_Injection + + + + false + + + + + + Use_Byte_Write_Enable + false + + + + true + + + + + + Byte_Size + 9 + + + + false + + + + + + Algorithm + Minimum_Area + + + + true + + + + + + Primitive + 8kx2 + + + + false + + + + + + Assume_Synchronous_Clk + false + + + + false + + + + + + Write_Width_A + 64 + + + + true + + + + + + Write_Depth_A + 1024 + + + + true + + + + + + Read_Width_A + 64 + + + + true + + + + + + Operating_Mode_A + WRITE_FIRST + + + + true + + + + + + Enable_A + Use_ENA_Pin + + + + true + + + + + + Write_Width_B + 64 + + + + false + + + + + + Read_Width_B + 64 + + + + false + + + + + + Operating_Mode_B + WRITE_FIRST + + + + false + + + + + + Enable_B + Always_Enabled + + + + false + + + + + + Register_PortA_Output_of_Memory_Primitives + false + + + + true + + + + + + Register_PortA_Output_of_Memory_Core + false + + + + true + + + + + + Use_REGCEA_Pin + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Primitives + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Core + false + + + + false + + + + + + Use_REGCEB_Pin + false + + + + false + + + + + + register_porta_input_of_softecc + false + + + + false + + + + + + register_portb_output_of_softecc + false + + + + false + + + + + + Pipeline_Stages + 0 + + + + false + + + + + + Load_Init_File + false + + + + true + + + + + + Coe_File + no_coe_file_loaded + + + + false + + + + + + Fill_Remaining_Memory_Locations + false + + + + true + + + + + + Remaining_Memory_Locations + 0 + + + + false + + + + + + Use_RSTA_Pin + false + + + + true + + + + + + Reset_Memory_Latch_A + false + + + + false + + + + + + Reset_Priority_A + CE + + + + false + + + + + + Output_Reset_Value_A + 0 + + + + false + + + + + + Use_RSTB_Pin + false + + + + false + + + + + + Reset_Memory_Latch_B + false + + + + false + + + + + + Reset_Priority_B + CE + + + + false + + + + + + Output_Reset_Value_B + 0 + + + + false + + + + + + Reset_Type + SYNC + + + + false + + + + + + Additional_Inputs_for_Power_Estimation + false + + + + true + + + + + + Port_A_Clock + 100 + + + + true + + + + + + Port_A_Write_Rate + 50 + + + + true + + + + + + Port_B_Clock + 0 + + + + true + + + + + + Port_B_Write_Rate + 0 + + + + true + + + + + + Port_A_Enable_Rate + 100 + + + + true + + + + + + Port_B_Enable_Rate + 0 + + + + true + + + + + + Collision_Warnings + ALL + + + + true + + + + + + Disable_Collision_Warnings + false + + + + true + + + + + + Disable_Out_of_Range_Warnings + false + + + + true + + + + + + use_bram_block + Stand_Alone + + + + true + + + + + + MEM_FILE + no_mem_loaded + + + + true + + + + + + CTRL_ECC_ALGO + NONE + + + + true + + + + + + EN_SAFETY_CKT + false + + + + false + + + + + + + + Block Memory Generator + + XPM_MEMORY + + 1 + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd new file mode 100644 index 0000000..3a5cc8a --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd @@ -0,0 +1,441 @@ + + + + + xilinx.com + BlockDiagram + bd_9f2c + 1.00.a + + + isTop + true + + + + + IO + + + + + + TRACE + + + + + + CLK.CLK + Clk + Clock + + + + + + + CLK + + + Clk + + + + + + FREQ_HZ + 100000000 + + + + + + + + PHASE + 0.000 + + + + + + + + ASSOCIATED_ASYNC_RESET + Reset + + + + + + + + + + RST.RESET + Reset + Reset + + + + + + + RST + + + Reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + Clk + + in + + + + Reset + + in + + + + + + + + xilinx.com + BlockDiagram + bd_9f2c_imp + 1.00.a + + + microblaze_I + + + bd_9f2c_microblaze_I_0 + 17 + mb_microblaze_0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 3 + 0 + 0 + + + + + rst_0 + + + bd_9f2c_rst_0_0 + + + + ilmb + + + bd_9f2c_ilmb_0 + 2 + + + + dlmb + + + bd_9f2c_dlmb_0 + 3 + + + + dlmb_cntlr + + + bd_9f2c_dlmb_cntlr_0 + 0x0000000000000000 + 0x000000000000FFFF + 0x00000000C0010000 + + + + + ilmb_cntlr + + + bd_9f2c_ilmb_cntlr_0 + 0x0000000000000000 + 0x000000000000FFFF + 0x0000000080010000 + + + + lmb_bram_I + + + bd_9f2c_lmb_bram_I_0 + True_Dual_Port_RAM + + + + second_dlmb_cntlr + + + bd_9f2c_second_dlmb_cntlr_0 + 0x0000000000010000 + 0x0000000000017FFF + 0x00000000C0010000 + + + + + second_ilmb_cntlr + + + bd_9f2c_second_ilmb_cntlr_0 + 0x0000000000010000 + 0x0000000000017FFF + 0x0000000080010000 + + + + second_lmb_bram_I + + + bd_9f2c_second_lmb_bram_I_0 + True_Dual_Port_RAM + + + + iomodule_0 + + + bd_9f2c_iomodule_0_0 + iomodule + 0x0000000080000000 + 0x000000008000FFFF + 0x00000000C0000000 + 1 + 0x00000000C0000000 + 0x00000000FFFFFFFF + 0x00000000C0000000 + 1 + 1 + 17 + + + + + + ilmb + + + + + dlmb + + + + + ilmb_sl_0 + + + + + dlmb_sl_0 + + + + + dlmb_sl_1 + + + + + ilmb_port + + + + + dlmb_port + + + + + ilmb_sl_1 + + + + + dlmb_sl_2 + + + + + ilmb_port_2 + + + + + dlmb_port_2 + + + + + + + Clk2 + + + + + + + + + + + + + Reset + + + + + MB_Reset + + + + + LMB_Rst2 + + + + + + + + + + IO_Rst + + + + + + + + + + + + + + + + xilinx.com + Addressing/microblaze_I + microblaze + 10.0 + + + DLMB + + + + + + + + ILMB + + + + + + + + + + Data + 4G + 32 + + + SEG_dlmb_cntlr_Mem + /dlmb_cntlr/SLMB/Mem + 0x00000000 + 64K + + + SEG_iomodule_0_IO + /iomodule_0/SLMB/IO + 0xC0000000 + 1G + + + SEG_iomodule_0_Reg + /iomodule_0/SLMB/Reg + 0x80000000 + 64K + + + SEG_second_dlmb_cntlr_Mem + /second_dlmb_cntlr/SLMB/Mem + 0x00010000 + 32K + + + + + Instruction + 4G + 32 + + + SEG_ilmb_cntlr_Mem + /ilmb_cntlr/SLMB/Mem + 0x00000000 + 64K + + + SEG_second_ilmb_cntlr_Mem + /second_ilmb_cntlr/SLMB/Mem + 0x00010000 + 32K + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml new file mode 100644 index 0000000..16f5b83 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml @@ -0,0 +1,100 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v new file mode 100644 index 0000000..febbf3b --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v @@ -0,0 +1,173 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Command: generate_target bd_9f2c_wrapper.bd +//Design : bd_9f2c_wrapper +//Purpose: IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module bd_9f2c_wrapper + (Clk, + IO_addr_strobe, + IO_address, + IO_byte_enable, + IO_read_data, + IO_read_strobe, + IO_ready, + IO_write_data, + IO_write_strobe, + Reset, + TRACE_data_access, + TRACE_data_address, + TRACE_data_byte_enable, + TRACE_data_read, + TRACE_data_write, + TRACE_data_write_value, + TRACE_dcache_hit, + TRACE_dcache_rdy, + TRACE_dcache_read, + TRACE_dcache_req, + TRACE_delay_slot, + TRACE_ex_piperun, + TRACE_exception_kind, + TRACE_exception_taken, + TRACE_icache_hit, + TRACE_icache_rdy, + TRACE_icache_req, + TRACE_instruction, + TRACE_jump_hit, + TRACE_jump_taken, + TRACE_mb_halted, + TRACE_mem_piperun, + TRACE_msr_reg, + TRACE_new_reg_value, + TRACE_of_piperun, + TRACE_pc, + TRACE_pid_reg, + TRACE_reg_addr, + TRACE_reg_write, + TRACE_valid_instr); + input Clk; + output IO_addr_strobe; + output [31:0]IO_address; + output [3:0]IO_byte_enable; + input [31:0]IO_read_data; + output IO_read_strobe; + input IO_ready; + output [31:0]IO_write_data; + output IO_write_strobe; + input Reset; + output TRACE_data_access; + output [0:31]TRACE_data_address; + output [0:3]TRACE_data_byte_enable; + output TRACE_data_read; + output TRACE_data_write; + output [0:31]TRACE_data_write_value; + output TRACE_dcache_hit; + output TRACE_dcache_rdy; + output TRACE_dcache_read; + output TRACE_dcache_req; + output TRACE_delay_slot; + output TRACE_ex_piperun; + output [0:4]TRACE_exception_kind; + output TRACE_exception_taken; + output TRACE_icache_hit; + output TRACE_icache_rdy; + output TRACE_icache_req; + output [0:31]TRACE_instruction; + output TRACE_jump_hit; + output TRACE_jump_taken; + output TRACE_mb_halted; + output TRACE_mem_piperun; + output [0:14]TRACE_msr_reg; + output [0:31]TRACE_new_reg_value; + output TRACE_of_piperun; + output [0:31]TRACE_pc; + output [0:7]TRACE_pid_reg; + output [0:4]TRACE_reg_addr; + output TRACE_reg_write; + output TRACE_valid_instr; + + wire Clk; + wire IO_addr_strobe; + wire [31:0]IO_address; + wire [3:0]IO_byte_enable; + wire [31:0]IO_read_data; + wire IO_read_strobe; + wire IO_ready; + wire [31:0]IO_write_data; + wire IO_write_strobe; + wire Reset; + wire TRACE_data_access; + wire [0:31]TRACE_data_address; + wire [0:3]TRACE_data_byte_enable; + wire TRACE_data_read; + wire TRACE_data_write; + wire [0:31]TRACE_data_write_value; + wire TRACE_dcache_hit; + wire TRACE_dcache_rdy; + wire TRACE_dcache_read; + wire TRACE_dcache_req; + wire TRACE_delay_slot; + wire TRACE_ex_piperun; + wire [0:4]TRACE_exception_kind; + wire TRACE_exception_taken; + wire TRACE_icache_hit; + wire TRACE_icache_rdy; + wire TRACE_icache_req; + wire [0:31]TRACE_instruction; + wire TRACE_jump_hit; + wire TRACE_jump_taken; + wire TRACE_mb_halted; + wire TRACE_mem_piperun; + wire [0:14]TRACE_msr_reg; + wire [0:31]TRACE_new_reg_value; + wire TRACE_of_piperun; + wire [0:31]TRACE_pc; + wire [0:7]TRACE_pid_reg; + wire [0:4]TRACE_reg_addr; + wire TRACE_reg_write; + wire TRACE_valid_instr; + + bd_9f2c bd_9f2c_i + (.Clk(Clk), + .IO_addr_strobe(IO_addr_strobe), + .IO_address(IO_address), + .IO_byte_enable(IO_byte_enable), + .IO_read_data(IO_read_data), + .IO_read_strobe(IO_read_strobe), + .IO_ready(IO_ready), + .IO_write_data(IO_write_data), + .IO_write_strobe(IO_write_strobe), + .Reset(Reset), + .TRACE_data_access(TRACE_data_access), + .TRACE_data_address(TRACE_data_address), + .TRACE_data_byte_enable(TRACE_data_byte_enable), + .TRACE_data_read(TRACE_data_read), + .TRACE_data_write(TRACE_data_write), + .TRACE_data_write_value(TRACE_data_write_value), + .TRACE_dcache_hit(TRACE_dcache_hit), + .TRACE_dcache_rdy(TRACE_dcache_rdy), + .TRACE_dcache_read(TRACE_dcache_read), + .TRACE_dcache_req(TRACE_dcache_req), + .TRACE_delay_slot(TRACE_delay_slot), + .TRACE_ex_piperun(TRACE_ex_piperun), + .TRACE_exception_kind(TRACE_exception_kind), + .TRACE_exception_taken(TRACE_exception_taken), + .TRACE_icache_hit(TRACE_icache_hit), + .TRACE_icache_rdy(TRACE_icache_rdy), + .TRACE_icache_req(TRACE_icache_req), + .TRACE_instruction(TRACE_instruction), + .TRACE_jump_hit(TRACE_jump_hit), + .TRACE_jump_taken(TRACE_jump_taken), + .TRACE_mb_halted(TRACE_mb_halted), + .TRACE_mem_piperun(TRACE_mem_piperun), + .TRACE_msr_reg(TRACE_msr_reg), + .TRACE_new_reg_value(TRACE_new_reg_value), + .TRACE_of_piperun(TRACE_of_piperun), + .TRACE_pc(TRACE_pc), + .TRACE_pid_reg(TRACE_pid_reg), + .TRACE_reg_addr(TRACE_reg_addr), + .TRACE_reg_write(TRACE_reg_write), + .TRACE_valid_instr(TRACE_valid_instr)); +endmodule diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci new file mode 100644 index 0000000..258278c --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci @@ -0,0 +1,955 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_microblaze_I_0 + + + + 100000000 + 0.000 + + 30000000 + 0.000 + 1 + 32 + 0 + LEVEL_HIGH + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 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AXI Exception + 0 + + + + true + + + + + + C_M_AXI_IP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IP_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_I_BUS_EXCEPTION + Enable Instruction-side AXI Exception + 0 + + + + true + + + + + + C_D_LMB + Enable Local Memory Bus Data Interface + 1 + + + C_D_AXI + Enable Peripheral AXI Data Interface + 0 + + + C_I_LMB + Enable Local Memory Bus Instruction Interface + 1 + + + C_I_AXI + Enable Peripheral AXI Instruction Interface + 0 + + + C_USE_MSR_INSTR + Enable Additional Machine Status Register Instructions + 0 + + + C_USE_PCMP_INSTR + Enable Pattern Comparator + 1 + + + C_USE_BARREL + Enable Barrel Shifter + 1 + + + C_USE_DIV + Enable Integer Divider + 1 + + + C_USE_HW_MUL + Enable Integer Multiplier + 1 + + + C_USE_FPU + Enable Floating Point Unit + 0 + + + C_USE_REORDER_INSTR + Enable Reversed Load/Store and Swap Instructions + 0 + + + C_UNALIGNED_EXCEPTIONS + Enable Unaligned Data Exception + 0 + + + C_ILL_OPCODE_EXCEPTION + Enable Illegal Instruction Exception + 0 + + + C_DIV_ZERO_EXCEPTION + Enable Integer Divide Exception + 0 + + + + true + + + + + + C_FPU_EXCEPTION + Enable Floating Point Unit Exceptions + 0 + + + + false + + + + + + C_FSL_LINKS + Number of Stream Links + 0 + + + C_USE_EXTENDED_FSL_INSTR + Enable Additional Stream Instructions + 0 + + + C_FSL_EXCEPTION + Enable Stream Exception + 0 + + + + false + + + + + + C_USE_STACK_PROTECTION + Enable stack protection + 0 + + + + true + + + + + + C_IMPRECISE_EXCEPTIONS + Allow Imprecise Exceptions + 0 + + + C_USE_INTERRUPT + 0 + + + C_USE_EXT_BRK + 0 + + + C_USE_EXT_NM_BRK + 0 + + + C_USE_NON_SECURE + 0 + + + C_USE_MMU + Memory Management + 0 + + + + true + + + + + + C_MMU_DTLB_SIZE + Data Shadow Translation Look-Aside Buffer Size + 4 + + + + false + + + + + + C_MMU_ITLB_SIZE + Instruction Shadow Translation Look-Aside Buffer Size + 2 + + + + false + + + + + + C_MMU_TLB_ACCESS + Enable Access to Memory Management Special Registers + 3 + + + + false + + + + + + C_MMU_ZONES + Number of Memory Protection Zones + 16 + + + + false + + + + + + C_MMU_PRIVILEGED_INSTR + Privileged Instructions + 0 + + + + false + + + + + + C_USE_BRANCH_TARGET_CACHE + Enable Branch Target Cache + 0 + + + + true + + + + + + C_BRANCH_TARGET_CACHE_SIZE + Branch Target Cache Size + 0 + + + + true + + + + + + C_PC_WIDTH + 17 + + + C_PVR + Specifies Processor Version Register + 0 + + + C_PVR_USER1 + Specify USER1 Bits in Processor Version Register + 0x00 + + + C_PVR_USER2 + Specify USER2 Bits in Processor Version Register + 0x00000000 + + + C_DYNAMIC_BUS_SIZING + 0 + + + C_RESET_MSR + Specify Reset Value for Select MSR Bits + 0x00000000 + + + C_OPCODE_0x0_ILLEGAL + Generate Illegal Instruction Exception for NULL Instruction + 0 + + + C_DEBUG_ENABLED + MicroBlaze Debug Module Interface + 0 + + + C_DEBUG_INTERFACE + MicroBlaze Debug Connection + 0 + + + C_NUMBER_OF_PC_BRK + Number of PC Breakpoints + 1 + + + C_NUMBER_OF_RD_ADDR_BRK + Number of Read Address Watchpoints + 0 + + + C_NUMBER_OF_WR_ADDR_BRK + Number of Write Address Watchpoints + 0 + + + C_DEBUG_EVENT_COUNTERS + Number of Performance Monitor Event Counters + 5 + + + C_DEBUG_LATENCY_COUNTERS + Number of Performance Monitor Latency Counters + 1 + + + C_DEBUG_COUNTER_WIDTH + Performance Monitor Counter Width + 32 + + + C_DEBUG_TRACE_SIZE + Trace Buffer Size + 8192 + + + C_DEBUG_EXTERNAL_TRACE + External Trace + 0 + + + C_DEBUG_TRACE_ASYNC_RESET + Use Asynchrnous Reset for External Trace + 0 + + + C_DEBUG_PROFILE_SIZE + Profile Buffer Size + 0 + + + C_INTERRUPT_IS_EDGE + Sense Interrupt on Edge vs. Level + 0 + + + C_EDGE_IS_POSITIVE + Sense Interrupt on Rising vs. Falling Edge + 1 + + + C_ASYNC_INTERRUPT + 1 + + + C_ASYNC_WAKEUP + 3 + + + C_M0_AXIS_DATA_WIDTH + 32 + + + C_S0_AXIS_DATA_WIDTH + 32 + + + C_M1_AXIS_DATA_WIDTH + 32 + + + C_S1_AXIS_DATA_WIDTH + 32 + + + C_M2_AXIS_DATA_WIDTH + 32 + + + C_S2_AXIS_DATA_WIDTH + 32 + + + C_M3_AXIS_DATA_WIDTH + 32 + + + C_S3_AXIS_DATA_WIDTH + 32 + + + C_M4_AXIS_DATA_WIDTH + 32 + + + C_S4_AXIS_DATA_WIDTH + 32 + + + C_M5_AXIS_DATA_WIDTH + 32 + + + C_S5_AXIS_DATA_WIDTH + 32 + + + C_M6_AXIS_DATA_WIDTH + 32 + + + C_S6_AXIS_DATA_WIDTH + 32 + + + C_M7_AXIS_DATA_WIDTH + 32 + + + C_S7_AXIS_DATA_WIDTH + 32 + + + C_M8_AXIS_DATA_WIDTH + 32 + + + C_S8_AXIS_DATA_WIDTH + 32 + + + C_M9_AXIS_DATA_WIDTH + 32 + + + C_S9_AXIS_DATA_WIDTH + 32 + + + C_M10_AXIS_DATA_WIDTH + 32 + + + C_S10_AXIS_DATA_WIDTH + 32 + + + C_M11_AXIS_DATA_WIDTH + 32 + + + C_S11_AXIS_DATA_WIDTH + 32 + + + C_M12_AXIS_DATA_WIDTH + 32 + + + C_S12_AXIS_DATA_WIDTH + 32 + + + C_M13_AXIS_DATA_WIDTH + 32 + + + C_S13_AXIS_DATA_WIDTH + 32 + + + C_M14_AXIS_DATA_WIDTH + 32 + + + C_S14_AXIS_DATA_WIDTH + 32 + + + C_M15_AXIS_DATA_WIDTH + 32 + + + C_S15_AXIS_DATA_WIDTH + 32 + + + C_ICACHE_BASEADDR + Base Address + 0x0000000000000000 + + + C_ICACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + C_USE_ICACHE + Enable Instruction Cache + 0 + + + C_ALLOW_ICACHE_WR + Enable Writes + 1 + + + C_ADDR_TAG_BITS + 17 + + + C_CACHE_BYTE_SIZE + Size in Bytes + 8192 + + + C_ICACHE_LINE_LEN + Line Length + 4 + + + C_ICACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 0 + + + C_ICACHE_STREAMS + Number of Streams + 0 + + + + true + + + + + + C_ICACHE_VICTIMS + Number of Victims + 0 + + + + true + + + + + + C_ICACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + + true + + + + + + C_ICACHE_DATA_WIDTH + Data Width + 0 + + + + true + + + + + + C_M_AXI_IC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_DATA_WIDTH + 32 + + + C_M_AXI_IC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IC_USER_VALUE + 31 + + + + true + + + + + + C_M_AXI_IC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_BUSER_WIDTH + 1 + + + + true + + + + + + C_DCACHE_BASEADDR + Base Address + 0x0000000000000000 + + + C_DCACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + C_USE_DCACHE + Enable Data Cache + 0 + + + C_ALLOW_DCACHE_WR + Enable Writes + 1 + + + C_DCACHE_ADDR_TAG + 17 + + + C_DCACHE_BYTE_SIZE + Size in Bytes + 8192 + + + C_DCACHE_LINE_LEN + Line Length + 4 + + + C_DCACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 0 + + + C_DCACHE_USE_WRITEBACK + Enable Write-back Storage Policy + 0 + + + + true + + + + + + C_DCACHE_VICTIMS + Number of Victims + 0 + + + + false + + + + + + C_DCACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + C_DCACHE_DATA_WIDTH + Data Width + 0 + + + + false + + + + + + C_M_AXI_DC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_DATA_WIDTH + 32 + + + C_M_AXI_DC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DC_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_M_AXI_DC_USER_VALUE + 31 + + + + true + + + + + + C_M_AXI_DC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_BUSER_WIDTH + 1 + + + + true + + + + + + + + + choice_list_29910ba8 + GENERIC + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_b1aff63c + 32 + 48 + 64 + + + choice_list_b94541ab + 0 + 2 + 4 + 8 + + + choice_list_dd2843c6 + 1 + 2 + 4 + 8 + + + choice_list_f86403bf + 4 + 8 + 16 + + + choice_pairs_0000a26c + 0 + 1 + 2 + 3 + + + choice_pairs_1075faf2 + 0 + 1 + 2 + + + choice_pairs_126baff7 + 0 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_13d40c7c + 0 + 32 + 64 + 128 + 256 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_2058dc69 + 0 + 1 + + + choice_pairs_22d9f392 + 0 + 1 + 2 + 3 + + + choice_pairs_3eb333f8 + 0 + 1 + 2 + + + choice_pairs_443ae6cc + 0 + 1 + 2 + 3 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_56d5ba32 + 0 + 1 + 2 + + + choice_pairs_5ab38e91 + 0 + 1 + 2 + + + choice_pairs_5b1842a1 + 0 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_75c71b2b + 0 + 1 + 2 + 3 + + + choice_pairs_7ad6afc0 + 0 + 1 + 2 + 3 + + + choice_pairs_7bfd418d + 0 + 1 + 2 + + + choice_pairs_7dd2834f + 0 + 8 + 9 + 10 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_8b498448 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + + + choice_pairs_b1fa18d9 + 0 + 1 + 2 + + + choice_pairs_c471ed24 + 32 + 36 + 40 + 44 + 48 + 52 + 64 + + + choice_pairs_db57ca32 + 0 + 1 + 2 + + + choice_pairs_e7a1eb81 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_ff364cce + 2 + 3 + + + + + microblaze + + + + endian + little + + + instance_path + + + + bootloop_file + data/mb_bootloop_le.elf + + + processor_type + MICROBLAZE_LE + + + is_visible + true + + + + + The MicroBlaze 32 bit soft processor core, providing an instruction set optimized for embedded applications with many user-configurable options. MicroBlaze has many advanced architecture features like Instruction and Data-side cache with AXI interfaces, Floating-Point unit (FPU), Memory Management Unit (MMU), and fault tolerance support. +It is highly recommended to create MicroBlaze systems within Vivado IP Integrator, to enable export to the Xilinx Software Development Kit (SDK) for software development. + + + + C_SCO + 0 + + + + true + + + + + + C_FREQ + 100000000 + + + + true + + + + + + C_DATA_SIZE + 32 + + + + true + + + + + + C_ADDR_SIZE + Select Extended Addressing + 32 + + + + true + + + + + + C_DYNAMIC_BUS_SIZING + 0 + + + + true + + + + + + C_PC_WIDTH + 17 + + + + true + + + + + + C_INSTANCE + mb_microblaze_0 + + + + true + + + + + + C_AVOID_PRIMITIVES + 0 + + + + true + + + + + + C_FAULT_TOLERANT + Enable Fault Tolerance Support + 0 + + + + true + + + + + + C_ECC_USE_CE_EXCEPTION + Correctable Error Exception + 0 + + + + true + + + + + + C_LOCKSTEP_SLAVE + Lockstep Slave + 0 + + + + true + + + + + + C_ENDIANNESS + Endianness + 1 + + + + true + + + + + + C_AREA_OPTIMIZED + Select implementation optimization + 0 + + + + true + + + + + + C_OPTIMIZATION + 0 + + + + true + + + + + + C_INTERCONNECT + Select Bus Interface + 2 + + + + true + + + + + + C_BASE_VECTORS + Vector Base Address + 0x00000000 + + + + true + + + + + + C_USE_CONFIG_RESET + 0 + + + + true + + + + + + C_NUM_SYNC_FF_CLK + Synchronizing FFs to Clk region + 2 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_IRQ + Synchronizing FFs to Clk region for interrupt input + 1 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_DEBUG + Synchronizing FFs to Clk region in debug module + 2 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_CLK + Synchronizing FFs to Dbg_Clk region + 1 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_TRACE_CLK + Synchronizing FFs to Dbg_Trace_Clk region + 2 + + + + true + + + + + + C_M_AXI_DP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_D_AXI + Enable Peripheral AXI Data Interface + 0 + + + + true + + + + + + C_DP_AXI_MON + Use Monitor Interface for Peripheral AXI Data Interface + 0 + + + + true + + + + + + C_DC_AXI_MON + Use Monitor Interface for Cache AXI Data Interface + 0 + + + + true + + + + + + C_D_LMB + Enable Local Memory Bus Data Interface + 1 + + + + true + + + + + + C_D_LMB_MON + Use Monitor Interface for Local Memory Bus Data Interface + 0 + + + + true + + + + + + C_M_AXI_IP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IP_ADDR_WIDTH + 32 + + + + true + + + + + + C_I_AXI + Enable Peripheral AXI Instruction Interface + 0 + + + + true + + + + + + C_IP_AXI_MON + Use Monitor Interface for Peripheral AXI Instruction Interface + 0 + + + + true + + + + + + C_IC_AXI_MON + Use Monitor Interface for Cache AXI Instruction Interface + 0 + + + + true + + + + + + C_I_LMB + Enable Local Memory Bus Instruction Interface + 1 + + + + true + + + + + + C_I_LMB_MON + Use Monitor Interface for Local Memory Bus Instruction Interface + 0 + + + + true + + + + + + C_TRACE + Enable Trace Bus Interface + 1 + + + + true + + + + + + C_LOCKSTEP_SELECT + Lockstep Interface + 0 + + + + true + + + + + + C_ENABLE_DISCRETE_PORTS + Enable Discrete Ports + 0 + + + + true + + + + + + C_M_AXI_DC_USER_SIGNALS + Enable M_AXI_DC User Signals + 0 + + + + true + + + + + + C_M_AXI_IC_USER_SIGNALS + Enable M_AXI_IC User Signals + 0 + + + + true + + + + + + G_TEMPLATE_LIST + Select Configuration + 0 + + + + true + + + + + + G_USE_EXCEPTIONS + Enable Exceptions + 0 + + + + true + + + + + + C_USE_MSR_INSTR + Enable Additional Machine Status Register Instructions + 0 + + + + true + + + + + + C_USE_PCMP_INSTR + Enable Pattern Comparator + 1 + + + + true + + + + + + C_USE_REORDER_INSTR + Enable Reversed Load/Store and Swap Instructions + 0 + + + + true + + + + + + C_USE_BARREL + Enable Barrel Shifter + 1 + + + + true + + + + + + C_USE_DIV + Enable Integer Divider + 1 + + + + true + + + + + + C_USE_HW_MUL + Enable Integer Multiplier + 1 + + + + true + + + + + + C_USE_FPU + Enable Floating Point Unit + 0 + + + + true + + + + + + C_UNALIGNED_EXCEPTIONS + Enable Unaligned Data Exception + 0 + + + + true + + + + + + C_ILL_OPCODE_EXCEPTION + Enable Illegal Instruction Exception + 0 + + + + true + + + + + + C_M_AXI_I_BUS_EXCEPTION + Enable Instruction-side AXI Exception + 0 + + + + false + + + + + + C_M_AXI_D_BUS_EXCEPTION + Enable Data-side AXI Exception + 0 + + + + false + + + + + + C_DIV_ZERO_EXCEPTION + Enable Integer Divide Exception + 0 + + + + true + + + + + + C_FPU_EXCEPTION + Enable Floating Point Unit Exceptions + 0 + + + + false + + + + + + C_FSL_EXCEPTION + Enable Stream Exception + 0 + + + + false + + + + + + C_USE_STACK_PROTECTION + Enable stack protection + 0 + + + + true + + + + + + C_IMPRECISE_EXCEPTIONS + Allow Imprecise Exceptions + 0 + + + + true + + + + + + C_PVR + Specifies Processor Version Register + 0 + + + + true + + + + + + C_PVR_USER1 + Specify USER1 Bits in Processor Version Register + 0x00 + + + + false + + + + + + C_PVR_USER2 + Specify USER2 Bits in Processor Version Register + 0x00000000 + + + + false + + + + + + C_DEBUG_ENABLED + MicroBlaze Debug Module Interface + 0 + + + + true + + + + + + C_DEBUG_INTERFACE + MicroBlaze Debug Connection + 0 + + + + true + + + + + + C_NUMBER_OF_PC_BRK + Number of PC Breakpoints + 1 + + + + false + + + + + + C_NUMBER_OF_RD_ADDR_BRK + Number of Read Address Watchpoints + 0 + + + + false + + + + + + C_NUMBER_OF_WR_ADDR_BRK + Number of Write Address Watchpoints + 0 + + + + false + + + + + + C_DEBUG_EVENT_COUNTERS + Number of Performance Monitor Event Counters + 5 + + + + false + + + + + + C_DEBUG_LATENCY_COUNTERS + Number of Performance Monitor Latency Counters + 1 + + + + false + + + + + + C_DEBUG_COUNTER_WIDTH + Performance Monitor Counter Width + 32 + + + + false + + + + + + C_DEBUG_TRACE_SIZE + Trace Buffer Size + 8192 + + + + false + + + + + + C_DEBUG_EXTERNAL_TRACE + External Trace + 0 + + + + false + + + + + + C_DEBUG_TRACE_ASYNC_RESET + Use Asynchrnous Reset for External Trace + 0 + + + + true + + + + + + C_DEBUG_PROFILE_SIZE + Profile Buffer Size + 0 + + + + false + + + + + + C_INTERRUPT_IS_EDGE + Sense Interrupt on Edge vs. Level + 0 + + + + true + + + + + + C_EDGE_IS_POSITIVE + Sense Interrupt on Rising vs. Falling Edge + 1 + + + + true + + + + + + C_ASYNC_INTERRUPT + 1 + + + + true + + + + + + C_ASYNC_WAKEUP + 3 + + + + true + + + + + + C_RESET_MSR_IE + IE + 0 + + + + true + + + + + + C_RESET_MSR_BIP + BIP + 0 + + + + true + + + + + + C_RESET_MSR_ICE + ICE + 0 + + + + true + + + + + + C_RESET_MSR_DCE + DCE + 0 + + + + true + + + + + + C_RESET_MSR_EE + EE + 0 + + + + true + + + + + + C_RESET_MSR_EIP + EIP + 0 + + + + true + + + + + + C_OPCODE_0x0_ILLEGAL + Generate Illegal Instruction Exception for NULL Instruction + 0 + + + + false + + + + + + C_FSL_LINKS + Number of Stream Links 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+ + + INTERRUPT + + + PIT1_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.PIT2_Interrupt + PIT2_Interrupt + + + + + + + INTERRUPT + + + PIT2_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.PIT3_Interrupt + PIT3_Interrupt + + + + + + + INTERRUPT + + + PIT3_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.PIT4_Interrupt + PIT4_Interrupt + + + + + + + INTERRUPT + + + PIT4_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI1_Interrupt + GPI1_Interrupt + + + + + + + INTERRUPT + + + GPI1_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI2_Interrupt + GPI2_Interrupt + + + + + + + INTERRUPT + + + GPI2_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI3_Interrupt + GPI3_Interrupt + + + + + + + INTERRUPT + + + GPI3_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.GPI4_Interrupt + GPI4_Interrupt + + + + + + + INTERRUPT + + + GPI4_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Interrupt + INTC_Interrupt + + + + + + + INTERRUPT + + + INTC_Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + none + + + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Irq_Single + INTC_IRQ + + + + + + + INTERRUPT + + + INTC_IRQ + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTC_Irq + INTC_IRQ + + + + + + + ACK + + + INTC_Processor_Ack + + + + + ADDRESS + + + INTC_Interrupt_Address + + + + + INTERRUPT + + + INTC_IRQ + + + + + + SENSITIVITY + LEVEL_HIGH + + + LOW_LATENCY + 0 + + + + + + false + + + + + + INTERRUPT.INTC_Irq_Out + INTC_IRQ_OUT + + + + + + + INTERRUPT + + + INTC_IRQ_OUT + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + UART + UART + UART TX/RX + + + + + + + RxD + + + UART_Rx + + + + + TxD + + + UART_Tx + + + + + + BOARD.ASSOCIATED_PARAM + UART_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO1 + GPIO1 + General Purpose IO + + + + + + + TRI_I + + + GPI1 + + + + + TRI_O + + + GPO1 + + + + + + C_USE_GPO1 + 0 + + + + true + + + + + + C_GPO1_SIZE + 32 + + + + true + + + + + + C_GPO1_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI1 + 0 + + + + true + + + + + + C_GPI1_SIZE + 32 + + + + true + + + + + + C_GPI1_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO1_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO2 + GPIO2 + General Purpose IO + + + + + + + TRI_I + + + GPI2 + + + + + TRI_O + + + GPO2 + + + + + + C_USE_GPO2 + 0 + + + + true + + + + + + C_GPO2_SIZE + 32 + + + + true + + + + + + C_GPO2_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI2 + 0 + + + + true + + + + + + C_GPI2_SIZE + 32 + + + + true + + + + + + C_GPI2_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO2_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO3 + GPIO3 + General Purpose IO + + + + + + + TRI_I + + + GPI3 + + + + + TRI_O + + + GPO3 + + + + + + C_USE_GPO3 + 0 + + + + true + + + + + + C_GPO3_SIZE + 32 + + + + true + + + + + + C_GPO3_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI3 + 0 + + + + true + + + + + + C_GPI3_SIZE + 32 + + + + true + + + + + + C_GPI3_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO3_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO4 + GPIO4 + General Purpose IO + + + + + + + TRI_I + + + GPI4 + + + + + TRI_O + + + GPO4 + + + + + + C_USE_GPO4 + 0 + + + + true + + + + + + C_GPO4_SIZE + 32 + + + + true + + + + + + C_GPO4_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI4 + 0 + + + + true + + + + + + C_GPI4_SIZE + 32 + + + + true + + + + + + C_GPI4_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO4_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + + + SLMB + LMB memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + UART RX + UART Receive Data Register + UART Receive Data Register + 0x0 + 8 + true + read-only + + 0x0 + + + UART RX + Receive Data + Data received by the UART. + 0 + 8 + true + read-only + + 0 + 0 + + modify + false + + + + + false + + + + + + UART TX + UART Transmit Data Register + UART Transmit Data Register + 0x4 + 8 + true + write-only + + 0x0 + + + UART TX + Transmit Data + Data to be transmitted by the UART. + 0 + 8 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART Status + UART Status Register + UART Status Register + 0x8 + 8 + true + read-only + + 0x0 + + + Rx Valid Data + Rx Valid Data + Indicates if the receive register has valid data: + 0 - Receive register is empty. + 1 - Receive register has valid data. + + 0 + 1 + true + read-only + + 0 + 0 + + false + + + Tx Used + Tx Used + Indicates if the transmit register is in use: + 0 - Transmit register is not in use. + 1 - Transmit register is in use. + + 3 + 1 + true + read-only + + 0 + 0 + + false + + + Overrun Error + Overrun Error + Indicates that an overrun error has occurred: + 0 - No overrun has occurred. + 1 - An overrun has occurred. + + 5 + 1 + true + read-only + + 0 + 0 + + false + + + Frame Error + Frame Error + Indicates that an frame error has occurred: + 0 - No frame error has occurred. + 1 - A frame error has occurred. + + 6 + 1 + true + read-only + + 0 + 0 + + false + + + Parity Error + Parity Error + Indicates that a parity error has occurred: + 0 - No parity error has occurred. + 1 - A parity error occurred. + + 7 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ MODE + Interrupt Mode Register + Interrupt Mode Register + 0xC + 17 + true + write-only + + 0x0 + + + IRQ Mode + IRQ Mode + Interrupt Mode. +For each bit: + W - When written with 1 the corresponding interrupt will use fast mode. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + GPO 1 + General Purpose Output 1 Register + General Purpose Output 1 Register + 0x10 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 2 + General Purpose Output 2 Register + General Purpose Output 2 Register + 0x14 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 3 + General Purpose Output 3 Register + General Purpose Output 3 Register + 0x18 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 4 + General Purpose Output 4 Register + General Purpose Output 4 Register + 0x1C + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 1 + General Purpose Input 1 Register + General Purpose Input 1 Register + 0x20 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 2 + General Purpose Input 2 Register + General Purpose Input 2 Register + 0x24 + 32 + true + read-only + + 0 + + + CPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 3 + General Purpose Input 3 Register + General Purpose Input 3 Register + 0x28 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 4 + General Purpose Input 4 Register + General Purpose Input 4 Register + 0x2C + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ STATUS + Interrupt Status Register + Interrupt Status Register + 0x30 + 17 + true + read-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC Interrupt + External interrupt input signal + Interrupt Status Register. +For each bit: + R - Reads active interrupt signal. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ PENDING + Interrupt Pending Register + Interrupt Pending Register + 0x34 + 17 + true + read-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC Interrupt + Enabled interrupt events that have occurred + Interrupt Pending. +For each bit: + R - Reads enabled interrupt event that has occurred. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ ENABLE + Interrupt Enable Register + Interrupt Enable Register + 0x38 + 17 + true + write-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt enabled. + 0 + 1 + true + write-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt enabled. + 1 + 1 + true + write-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt enabled. + 2 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 interrupt enabled. + 3 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 interrupt enabled. + 4 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 interrupt enabled. + 5 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 interrupt enabled. + 6 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 interrupt enabled. + 7 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 interrupt enabled. + 8 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 interrupt enabled. + 9 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 interrupt enabled. + 10 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 interrupt enabled. + 11 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 interrupt enabled. + 12 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 interrupt enabled. + 13 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 interrupt enabled. + 14 + 1 + true + write-only + + 0 + 0 + + false + + + INTC Interrupt + Enable external interrupt input signals + Interrupt Enable. +For each bit: + W - Enable external interrupt input signal. + + 16 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ ACK + Interrupt Acknowledge Register + Interrupt Acknowledge Register + 0x3C + 17 + true + write-only + + 0x0 + + + IRQ Acknowledge + IRQ Acknowledge + Interrupt Acknowledge. +For each bit: + W - When written with 1 clear bit in IRQ_STATUS and IRQ_PENDING. + + 0 + 17 + true + write-only + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + PIT1 PRELOAD + PIT 1 Preload Register + PIT 1 Preload Register + 0x40 + 32 + true + write-only + + 0x0 + + + PIT1 Preload + PIT1 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1 COUNTER + PIT 1 Counter Register + PIT 1 Counter Register + 0x44 + 32 + true + read-only + + 0x0 + + + PIT1 Counter + PIT1 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1 CONTROL + PIT 1 Control Register + PIT 1 Control Register + 0x48 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT1_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART BAUD + UART Programmable Baud Rate + UART Programmable Baud Rate + 0x4C + 8 + true + write-only + + 0x0 + + + UART BAUD + Baud Rate + Programmable UART Baud Rate. + 0 + 20 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 PRELOAD + PIT 2 Preload Register + PIT 2 Preload Register + 0x50 + 32 + true + write-only + + 0x0 + + + PIT2 Preload + PIT2 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 COUNTER + PIT 2 Counter Register + PIT 2 Counter Register + 0x54 + 32 + true + read-only + + 0x0 + + + PIT2 Counter + PIT2 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 CONTROL + PIT 2 Control Register + PIT 2 Control Register + 0x58 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT2_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 PRELOAD + PIT 3 Preload Register + PIT 3 Preload Register + 0x60 + 32 + true + write-only + + 0x0 + + + PIT3 Preload + PIT3 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 COUNTER + PIT 3 Counter Register + PIT 3 Counter Register + 0x64 + 32 + true + read-only + + 0x0 + + + PIT3 Counter + PIT3 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 CONTROL + PIT 3 Control Register + PIT 3 Control Register + 0x68 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT3_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 PRELOAD + PIT 4 Preload Register + PIT 4 Preload Register + 0x70 + 32 + true + write-only + + 0x0 + + + PIT4 Preload + PIT4 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 COUNTER + PIT 4 Counter Register + PIT 4 Counter Register + 0x74 + 32 + true + read-only + + 0x0 + + + PIT4 Counter + PIT4 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 CONTROL + PIT 4 Control Register + PIT 4 Control Register + 0x78 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT4_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 0 + Interrupt Vector Register 0 + Interrupt Vector Register 0 + 0x80 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 0 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 1 + Interrupt Vector Register 1 + Interrupt Vector Register 1 + 0x84 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 1 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 2 + Interrupt Vector Register 2 + Interrupt Vector Register 2 + 0x88 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 2 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 3 + Interrupt Vector Register 3 + Interrupt Vector Register 3 + 0x8C + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 3 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 4 + Interrupt Vector Register 4 + Interrupt Vector Register 4 + 0x90 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 4 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 5 + Interrupt Vector Register 5 + Interrupt Vector Register 5 + 0x94 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 5 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 6 + Interrupt Vector Register 6 + Interrupt Vector Register 6 + 0x98 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 6 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 7 + Interrupt Vector Register 7 + Interrupt Vector Register 7 + 0x9C + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 7 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 8 + Interrupt Vector Register 8 + Interrupt Vector Register 8 + 0xA0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 8 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 9 + Interrupt Vector Register 9 + Interrupt Vector Register 9 + 0xA4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 9 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 10 + Interrupt Vector Register 10 + Interrupt Vector Register 10 + 0xA8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 10 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 11 + Interrupt Vector Register 11 + Interrupt Vector Register 11 + 0xAC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 11 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 12 + Interrupt Vector Register 12 + Interrupt Vector Register 12 + 0xB0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 12 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 13 + Interrupt Vector Register 13 + Interrupt Vector Register 13 + 0xB4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 13 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 14 + Interrupt Vector Register 14 + Interrupt Vector Register 14 + 0xB8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 14 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 16 + Interrupt Vector Register 16 + Interrupt Vector Register 16 + 0xC0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 16 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + IRQ VECTOR 17 + Interrupt Vector Register 17 + Interrupt Vector Register 17 + 0xC4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 17 with highest priority. + + 0 + 32 + true + write-only + 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b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci new file mode 100644 index 0000000..fbfdffc --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci @@ -0,0 +1,113 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_ilmb_0 + + + + 100000000 + 0.000 + 32 + 32 + READ_ONLY + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 1 + 32 + 32 + 2 + 1 + 32 + 32 + 2 + bd_9f2c_ilmb_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 9 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xml new file mode 100644 index 0000000..5012054 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xml @@ -0,0 +1,3323 @@ + + + xilinx.com + customized_ip + bd_9f2c_ilmb_0 + 1.0 + + + LMB_Sl_0 + LMB_Sl_00 + Local Memory Bus Mirrored Slave interface 0 + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + 0 + 0 + + + + + + READDBUS + + + Sl_DBus + + 0 + 31 + + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + 0 + 0 + + + + + + RST + + + LMB_Rst + + + + + UE + + + Sl_UE + + 0 + 0 + + + + + + WAIT + + + Sl_Wait + + 0 + 0 + + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + 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std_logic_vector + dummy_view + + + + + + + + C_LMB_NUM_SLAVES + LMB Number of Slaves + 3 + + + C_LMB_DWIDTH + C Lmb Dwidth + 32 + + + C_LMB_AWIDTH + C Lmb Awidth + 32 + + + C_EXT_RESET_HIGH + C Ext Reset High + 1 + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_4873554b + 0 + 1 + + + The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM + + + C_LMB_DWIDTH + C Lmb Dwidth + 32 + + + + true + + + + + + C_LMB_AWIDTH + C Lmb Awidth + 32 + + + + true + + + + + + C_EXT_RESET_HIGH + C Ext Reset High + 1 + + + + true + + + + + + C_LMB_NUM_SLAVES + LMB Number of Slaves + 3 + + + + true + + + + + + Component_Name + bd_9f2c_dlmb_0 + + + + + Local Memory Bus (LMB) 1.0 + 9 + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci new file mode 100644 index 0000000..8b47f4b --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_dlmb_cntlr_0 + + + NONE + 65536 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000000000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000000000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_9f2c_dlmb_cntlr_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 15 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml new file mode 100644 index 0000000..7ebe875 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml @@ -0,0 +1,3874 @@ + + + xilinx.com + customized_ip + bd_9f2c_dlmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + LMB_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + Sl_Ready + + out + + + std_logic + dummy_view + + + + + + Sl_Wait + + out + + + std_logic + dummy_view + + + + + + Sl_UE + + out + + + std_logic + dummy_view + + + + + + Sl_CE + + out + + + std_logic + dummy_view + + + + + + LMB1_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + Sl1_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + Sl1_Ready + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_Wait + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + LMB2_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_BE + + in + + 0 + 3 + + + + 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and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_9f2c_dlmb_cntlr_0 + + + + + LMB BRAM Controller + 15 + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci new file mode 100644 index 0000000..736c50f --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_ilmb_cntlr_0 + + + NONE + 65536 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000000000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000000000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_9f2c_ilmb_cntlr_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 15 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xml new file mode 100644 index 0000000..901e1aa --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xml @@ -0,0 +1,3874 @@ + + + xilinx.com + customized_ip + bd_9f2c_ilmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + 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Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000000000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x000000000000FFFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x0000000080010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + 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a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci new file mode 100644 index 0000000..e49dbab --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci @@ -0,0 +1,275 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_lmb_bram_I_0 + + + 4096 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + BRAM_CTRL + NONE + 65536 + 32 + READ_WRITE + BRAM_CTRL + NONE + 65536 + 32 + READ_WRITE + + 100000000 + 0.000 + 32 + 32 + 1 + 4 + 0 + 1 + 8 + 0 + 0 + 16 + NONE + 0 + 0 + 0 + ./ + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + Estimated Power for IP : 19.660986 mW + virtexuplus + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + bd_9f2c_lmb_bram_I_0.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 16384 + 16384 + 32 + 32 + 0 + 0 + CE + CE + ALL + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 4 + 4 + 16384 + 16384 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 8 + NONE + no_coe_file_loaded + ALL + bd_9f2c_lmb_bram_I_0 + false + false + false + false + false + true + false + false + true + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + false + Native + false + bd_9f2c_lmb_bram_I_0.mem + True_Dual_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + true + false + false + false + true + true + 16384 + 32 + 32 + No_ECC + false + false + false + BRAM_Controller + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 1 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml new file mode 100644 index 0000000..e5b972f --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml @@ -0,0 +1,4056 @@ + + + xilinx.com + customized_ip + bd_9f2c_lmb_bram_I_0 + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + AXI_SLAVE_S_AXI + AXI_SLAVE + AXI_SLAVE + + + + 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Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_9f2c_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false 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a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci new file mode 100644 index 0000000..b0eab43 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_second_dlmb_cntlr_0 + + + NONE + 32768 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000010000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x0000000000017FFF + 0 + 32 + 32 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000010000 + 0 + 0 + 0 + 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HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + 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+ ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + 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frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable 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false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_9f2c_second_dlmb_cntlr_0 + + + + + LMB BRAM Controller + 15 + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci new file mode 100644 index 0000000..c90eab9 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9f2c_second_ilmb_cntlr_0 + + + NONE + 32768 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000010000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x0000000000017FFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000010000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x0000000000017FFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_9f2c_second_ilmb_cntlr_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 15 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xml new file mode 100644 index 0000000..554b605 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xml @@ -0,0 +1,3874 @@ + + + xilinx.com + customized_ip + bd_9f2c_second_ilmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 32768 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + 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SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in 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C_HAS_MUX_OUTPUT_REGS_A + 0 + + + C_HAS_MUX_OUTPUT_REGS_B + 0 + + + C_MUX_PIPELINE_STAGES + 0 + + + C_HAS_SOFTECC_INPUT_REGS_A + 0 + + + C_HAS_SOFTECC_OUTPUT_REGS_B + 0 + + + C_USE_SOFTECC + 0 + + + C_USE_ECC + 0 + + + C_EN_ECC_PIPE + 0 + + + C_HAS_INJECTERR + 0 + + + C_SIM_COLLISION_CHECK + ALL + + + C_COMMON_CLK + 0 + + + C_DISABLE_WARN_BHV_COLL + 0 + + + C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 1 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 8 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 17.246228 mW + + + + + + choice_list_0132492a + 32 + 64 + 128 + + + choice_list_302d3091 + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_6fc15197 + 32 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f9a6a28b + Native + + + choice_pairs_1f270a52 + BRAM_Controller + Stand_Alone + + + choice_pairs_246d8066 + WRITE_FIRST + READ_FIRST + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_9f2c_second_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A 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9 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_5502e96b + 1 + 2 + 3 + 4 + + + choice_pairs_563648c8 + 0 + 1 + + + choice_pairs_5f1e379e + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 9 + + + choice_pairs_7ba91213 + 0 + 1 + 2 + 3 + + + choice_pairs_f0f6eb36 + 0 + 1 + 2 + 3 + 4 + 6 + 7 + 8 + 9 + + + choice_pairs_f7e0b771 + 4096 + 8192 + 12288 + 16384 + 20480 + 24576 + 32768 + 36864 + 40960 + 49152 + 65536 + 69632 + 73728 + 81920 + 98304 + 131072 + + + choice_pairs_ffa336e4 + 0 + 1 + + + + + xilinx_elaborateports_view_fileset + + ../bd_0/bd_9f2c.bd + block_diagram + + + + xilinx_elaboratebd_view_fileset + + ../bd_0/bd_9f2c.bd + block_diagram + + + + MicroBlaze Micro Controller System (MCS) is a light-weight general purpose micro controller system, based on the MicroBlaze processor. It is primarily intended for simple control applications, where a hardware solution would be less flexible and more difficult to implement. Software development with the Xilinx Software Development Kit (SDK) is supported, including a software driver for the peripherals. Debugging including UART is available either via SDK or directly with the Xilinx Microprocessor Debugger. +The MCS consists of the processor itself, local memory with sizes ranging from 4KB to 128KB, up to 4 Fixed Interval Timers, up to 4 Programmable Interval Timers, up to 4 32-bit General Purpose Output ports, up to 4 32-bit General Purpose Input ports, and an Interrupt Controller with up to 16 external interrupt inputs. + + + + JTAG_CHAIN + Debug JTAG User-defined Register + 2 + + + + false + + + + + + MICROBLAZE_INSTANCE + MicroBlaze Instance Name + microblaze_0 + + + AVOID_PRIMITIVES + 0 + + + PATH + Instance Hierarchical Design Name + mcs_0 + + + FREQ + Input Clock Frequency (MHz) + 100.0 + + + OPTIMIZATION + Select MicroBlaze Optimization + 1 + + + DEBUG_ENABLED + Enable Debug Support + 0 + + + TRACE + Enable MicroBlaze Trace Bus + 1 + + + ECC + Error Correction Code + 0 + + + MEMSIZE + Memory Size + 98304 + + + USE_IO_BUS + Enable IO Bus + 1 + + + USE_UART_RX + Enable Receiver + 0 + + + + true + + + + + + USE_UART_TX + Enable Transmitter + 0 + + + + true + + + + + + UART_BAUDRATE + Define Baud Rate + 9600 + + + + false + + + + + + UART_PROG_BAUDRATE + Programmable Baud Rate + 0 + + + + false + + + + + + UART_DATA_BITS + Number of Data Bits + 8 + + + + false + + + + + + UART_USE_PARITY + Use Parity + 0 + + + + false + + + + + + UART_ODD_PARITY + Even or Odd Parity + 0 + + + + false + + + + + + UART_RX_INTERRUPT + Implement Receive Interrupt + 0 + + + + false + + + + + + UART_TX_INTERRUPT + Implement Transmit Interrupt + 0 + + + + false + + + + + + UART_ERROR_INTERRUPT + Implement Error Interrupt + 0 + + + + false + + + + + + USE_FIT1 + Use Timer + 0 + + + FIT1_No_CLOCKS + Number of Clocks Between Strobes + 6216 + + + + false + + + + + + FIT1_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_FIT2 + Use Timer + 0 + + + FIT2_No_CLOCKS + Number of Clocks Between Strobes + 6216 + + + + false + + + + + + FIT2_INTERRUPT + Generate Interrupt + 0 + + + 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+ + + + + + INTC_USE_EXT_INTR + Use External Interrupts + 0 + + + INTC_INTR_SIZE + Number of External Inputs + 1 + + + + false + + + + + + INTC_LEVEL_EDGE + Level or Edge of External Interrupts + 0x0000 + + + + false + + + + + + INTC_POSITIVE + Positive or Negative External Interrupts + 0xFFFF + + + + false + + + + + + INTC_ASYNC_INTR + Interrupts asynchronous + The setting of each bit in this option indicates whether the incoming interrupt is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous. + 0xFFFF + + + + false + + + + + + INTC_NUM_SYNC_FF + Number of synchronization flip-flops + Number of synchronization flip-flops used to synchronize asynchronous interupt inputs + 2 + + + Component_Name + phy_ddr4_microblaze_mcs + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_BOARD_INTERFACE + Custom + + + + true + + + + + + RESET_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO1_BOARD_INTERFACE + Custom + + + + true + + + + + + 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15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111101, + 15'b111111111111111, 15'b111111111111111 } + 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b +000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, + 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_011_011_011_011_111_111_011_011_011_011_111_111, 39'b000_000_000_000_000_000_000_001_000_001_001_001_001, 39'b001_001_001_000_000_001_001_001_00 +1_001_001_001_001, 39'b000_001_001_001_001_101_101_001_001_001_001_001_001 + false + 1 + 4 + 72 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + {{9{2'b11}}, {3{2'b00}}} + 12'b000000000000 + 1 + 3 + 1 + {13'b0111101111101, 13'b0111101111101, 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Differential + + + Reference_Clock + Differential + + + Debug_Signal + Disable + + + IO_Power_Reduction + IO_Power_Reduction + false + + + DCI_Cascade + DCI Cascade + false + + + Default_Bank_Selections + Default Bank Selections + false + + + Simulation_Mode + BFM + + + PARTIAL_RECONFIG_FLOW_MIG + false + + + + false + + + + + + MCS_DBG_EN + false + + + C0.DDR4_CK_SKEW_0 + 0 + + + C0.DDR4_CK_SKEW_1 + 0 + + + C0.DDR4_CK_SKEW_2 + 0 + + + C0.DDR4_CK_SKEW_3 + 0 + + + C0.DDR4_ADDR_SKEW_0 + 0 + + + C0.DDR4_ADDR_SKEW_1 + 0 + + + C0.DDR4_ADDR_SKEW_2 + 0 + + + C0.DDR4_ADDR_SKEW_3 + 0 + + + C0.DDR4_ADDR_SKEW_4 + 0 + + + C0.DDR4_ADDR_SKEW_5 + 0 + + + C0.DDR4_ADDR_SKEW_6 + 0 + + + C0.DDR4_ADDR_SKEW_7 + 0 + + + C0.DDR4_ADDR_SKEW_8 + 0 + + + C0.DDR4_ADDR_SKEW_9 + 0 + + + C0.DDR4_ADDR_SKEW_10 + 0 + + + C0.DDR4_ADDR_SKEW_11 + 0 + + + C0.DDR4_ADDR_SKEW_12 + 0 + + + C0.DDR4_ADDR_SKEW_13 + 0 + + + C0.DDR4_ADDR_SKEW_14 + 0 + + + C0.DDR4_ADDR_SKEW_15 + 0 + + + C0.DDR4_ADDR_SKEW_16 + 0 + + + C0.DDR4_ADDR_SKEW_17 + 0 + + + C0.DDR4_BA_SKEW_0 + 0 + + + C0.DDR4_BA_SKEW_1 + 0 + + + C0.DDR4_BG_SKEW_0 + 0 + + + C0.DDR4_BG_SKEW_1 + 0 + + + C0.DDR4_CS_SKEW_0 + 0 + + + C0.DDR4_CS_SKEW_1 + 0 + + + C0.DDR4_CS_SKEW_2 + 0 + + + C0.DDR4_CS_SKEW_3 + 0 + + + C0.DDR4_CKE_SKEW_0 + 0 + + + C0.DDR4_CKE_SKEW_1 + 0 + + + C0.DDR4_CKE_SKEW_2 + 0 + + + C0.DDR4_CKE_SKEW_3 + 0 + + + C0.DDR4_ACT_SKEW + 0 + + + C0.DDR4_PAR_SKEW + 0 + + + C0.DDR4_ODT_SKEW_0 + 0 + + + C0.DDR4_ODT_SKEW_1 + 0 + + + C0.DDR4_ODT_SKEW_2 + 0 + + + C0.DDR4_ODT_SKEW_3 + 0 + + + C0.DDR4_LR_SKEW_0 + 0 + + + C0.DDR4_LR_SKEW_1 + 0 + + + C0.ADDR_WIDTH + ADDR WIDTH + 17 + + + C0.BANK_GROUP_WIDTH + BANK GROUP WIDTH + 2 + + + C0.LR_WIDTH + LR WIDTH + 1 + + + C0.CK_WIDTH + CK WIDTH + 1 + + + C0.CKE_WIDTH + CKE WIDTH + 1 + + + C0.CS_WIDTH + CS WIDTH + 1 + + + C0.ODT_WIDTH + ODT WIDTH + 1 + + + C0.StackHeight + 1 + + + PING_PONG_PHY + Ping Pong Phy + 1 + + + + + DDR4 SDRAM (MIG) + 5 + + + + + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd new file mode 100644 index 0000000..f18736e --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd @@ -0,0 +1,441 @@ + + + + + xilinx.com + BlockDiagram + bd_ba6a + 1.00.a + + + isTop + true + + + + + IO + + + + + + TRACE + + + + + + CLK.CLK + Clk + Clock + + + + + + + CLK + + + Clk + + + + + + FREQ_HZ + 100000000 + + + + + + + + PHASE + 0.000 + + + + + + + + ASSOCIATED_ASYNC_RESET + Reset + + + + + + + + + + RST.RESET + Reset + Reset + + + + + + + RST + + + Reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + Clk + + in + + + + Reset + + in + + + + + + + + xilinx.com + BlockDiagram + bd_ba6a_imp + 1.00.a + + + microblaze_I + + + bd_ba6a_microblaze_I_0 + 17 + mb_microblaze_0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 3 + 0 + 0 + + + + + rst_0 + + + bd_ba6a_rst_0_0 + + + + ilmb + + + bd_ba6a_ilmb_0 + 2 + + + + dlmb + + + bd_ba6a_dlmb_0 + 3 + + + + dlmb_cntlr + + + bd_ba6a_dlmb_cntlr_0 + 0x0000000000000000 + 0x000000000000FFFF + 0x00000000C0010000 + + + + + ilmb_cntlr + + + bd_ba6a_ilmb_cntlr_0 + 0x0000000000000000 + 0x000000000000FFFF + 0x0000000080010000 + + + + lmb_bram_I + + + bd_ba6a_lmb_bram_I_0 + True_Dual_Port_RAM + + + + second_dlmb_cntlr + + + bd_ba6a_second_dlmb_cntlr_0 + 0x0000000000010000 + 0x0000000000017FFF + 0x00000000C0010000 + + + + + second_ilmb_cntlr + + + bd_ba6a_second_ilmb_cntlr_0 + 0x0000000000010000 + 0x0000000000017FFF + 0x0000000080010000 + + + + second_lmb_bram_I + + + bd_ba6a_second_lmb_bram_I_0 + True_Dual_Port_RAM + + + + iomodule_0 + + + bd_ba6a_iomodule_0_0 + iomodule + 0x0000000080000000 + 0x000000008000FFFF + 0x00000000C0000000 + 1 + 0x00000000C0000000 + 0x00000000FFFFFFFF + 0x00000000C0000000 + 1 + 1 + 17 + + + + + + ilmb + + + + + dlmb + + + + + ilmb_sl_0 + + + + + dlmb_sl_0 + + + + + dlmb_sl_1 + + + + + ilmb_port + + + + + dlmb_port + + + + + ilmb_sl_1 + + + + + dlmb_sl_2 + + + + + ilmb_port_2 + + + + + dlmb_port_2 + + + + + + + Clk2 + + + + + + + + + + + + + Reset + + + + + MB_Reset + + + + + LMB_Rst2 + + + + + + + + + + IO_Rst + + + + + + + + + + + + + + + + xilinx.com + Addressing/microblaze_I + microblaze + 10.0 + + + DLMB + + + + + + + + ILMB + + + + + + + + + + Data + 4G + 32 + + + SEG_dlmb_cntlr_Mem + /dlmb_cntlr/SLMB/Mem + 0x00000000 + 64K + + + SEG_iomodule_0_IO + /iomodule_0/SLMB/IO + 0xC0000000 + 1G + + + SEG_iomodule_0_Reg + /iomodule_0/SLMB/Reg + 0x80000000 + 64K + + + SEG_second_dlmb_cntlr_Mem + /second_dlmb_cntlr/SLMB/Mem + 0x00010000 + 32K + + + + + Instruction + 4G + 32 + + + SEG_ilmb_cntlr_Mem + /ilmb_cntlr/SLMB/Mem + 0x00000000 + 64K + + + SEG_second_ilmb_cntlr_Mem + /second_ilmb_cntlr/SLMB/Mem + 0x00010000 + 32K + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml new file mode 100644 index 0000000..9824039 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml @@ -0,0 +1,100 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v new file mode 100644 index 0000000..6046704 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v @@ -0,0 +1,173 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Command: generate_target bd_ba6a_wrapper.bd +//Design : bd_ba6a_wrapper +//Purpose: IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module bd_ba6a_wrapper + (Clk, + IO_addr_strobe, + IO_address, + IO_byte_enable, + IO_read_data, + IO_read_strobe, + IO_ready, + IO_write_data, + IO_write_strobe, + Reset, + TRACE_data_access, + TRACE_data_address, + TRACE_data_byte_enable, + TRACE_data_read, + TRACE_data_write, + TRACE_data_write_value, + TRACE_dcache_hit, + TRACE_dcache_rdy, + TRACE_dcache_read, + TRACE_dcache_req, + TRACE_delay_slot, + TRACE_ex_piperun, + TRACE_exception_kind, + TRACE_exception_taken, + TRACE_icache_hit, + TRACE_icache_rdy, + TRACE_icache_req, + TRACE_instruction, + TRACE_jump_hit, + TRACE_jump_taken, + TRACE_mb_halted, + TRACE_mem_piperun, + TRACE_msr_reg, + TRACE_new_reg_value, + TRACE_of_piperun, + TRACE_pc, + TRACE_pid_reg, + TRACE_reg_addr, + TRACE_reg_write, + TRACE_valid_instr); + input Clk; + output IO_addr_strobe; + output [31:0]IO_address; + output [3:0]IO_byte_enable; + input [31:0]IO_read_data; + output IO_read_strobe; + input IO_ready; + output [31:0]IO_write_data; + output IO_write_strobe; + input Reset; + output TRACE_data_access; + output [0:31]TRACE_data_address; + output [0:3]TRACE_data_byte_enable; + output TRACE_data_read; + output TRACE_data_write; + output [0:31]TRACE_data_write_value; + output TRACE_dcache_hit; + output TRACE_dcache_rdy; + output TRACE_dcache_read; + output TRACE_dcache_req; + output TRACE_delay_slot; + output TRACE_ex_piperun; + output [0:4]TRACE_exception_kind; + output TRACE_exception_taken; + output TRACE_icache_hit; + output TRACE_icache_rdy; + output TRACE_icache_req; + output [0:31]TRACE_instruction; + output TRACE_jump_hit; + output TRACE_jump_taken; + output TRACE_mb_halted; + output TRACE_mem_piperun; + output [0:14]TRACE_msr_reg; + output [0:31]TRACE_new_reg_value; + output TRACE_of_piperun; + output [0:31]TRACE_pc; + output [0:7]TRACE_pid_reg; + output [0:4]TRACE_reg_addr; + output TRACE_reg_write; + output TRACE_valid_instr; + + wire Clk; + wire IO_addr_strobe; + wire [31:0]IO_address; + wire [3:0]IO_byte_enable; + wire [31:0]IO_read_data; + wire IO_read_strobe; + wire IO_ready; + wire [31:0]IO_write_data; + wire IO_write_strobe; + wire Reset; + wire TRACE_data_access; + wire [0:31]TRACE_data_address; + wire [0:3]TRACE_data_byte_enable; + wire TRACE_data_read; + wire TRACE_data_write; + wire [0:31]TRACE_data_write_value; + wire TRACE_dcache_hit; + wire TRACE_dcache_rdy; + wire TRACE_dcache_read; + wire TRACE_dcache_req; + wire TRACE_delay_slot; + wire TRACE_ex_piperun; + wire [0:4]TRACE_exception_kind; + wire TRACE_exception_taken; + wire TRACE_icache_hit; + wire TRACE_icache_rdy; + wire TRACE_icache_req; + wire [0:31]TRACE_instruction; + wire TRACE_jump_hit; + wire TRACE_jump_taken; + wire TRACE_mb_halted; + wire TRACE_mem_piperun; + wire [0:14]TRACE_msr_reg; + wire [0:31]TRACE_new_reg_value; + wire TRACE_of_piperun; + wire [0:31]TRACE_pc; + wire [0:7]TRACE_pid_reg; + wire [0:4]TRACE_reg_addr; + wire TRACE_reg_write; + wire TRACE_valid_instr; + + bd_ba6a bd_ba6a_i + (.Clk(Clk), + .IO_addr_strobe(IO_addr_strobe), + .IO_address(IO_address), + .IO_byte_enable(IO_byte_enable), + .IO_read_data(IO_read_data), + .IO_read_strobe(IO_read_strobe), + .IO_ready(IO_ready), + .IO_write_data(IO_write_data), + .IO_write_strobe(IO_write_strobe), + .Reset(Reset), + .TRACE_data_access(TRACE_data_access), + .TRACE_data_address(TRACE_data_address), + .TRACE_data_byte_enable(TRACE_data_byte_enable), + .TRACE_data_read(TRACE_data_read), + .TRACE_data_write(TRACE_data_write), + .TRACE_data_write_value(TRACE_data_write_value), + .TRACE_dcache_hit(TRACE_dcache_hit), + .TRACE_dcache_rdy(TRACE_dcache_rdy), + .TRACE_dcache_read(TRACE_dcache_read), + .TRACE_dcache_req(TRACE_dcache_req), + .TRACE_delay_slot(TRACE_delay_slot), + .TRACE_ex_piperun(TRACE_ex_piperun), + .TRACE_exception_kind(TRACE_exception_kind), + .TRACE_exception_taken(TRACE_exception_taken), + .TRACE_icache_hit(TRACE_icache_hit), + .TRACE_icache_rdy(TRACE_icache_rdy), + .TRACE_icache_req(TRACE_icache_req), + .TRACE_instruction(TRACE_instruction), + .TRACE_jump_hit(TRACE_jump_hit), + .TRACE_jump_taken(TRACE_jump_taken), + .TRACE_mb_halted(TRACE_mb_halted), + .TRACE_mem_piperun(TRACE_mem_piperun), + .TRACE_msr_reg(TRACE_msr_reg), + .TRACE_new_reg_value(TRACE_new_reg_value), + .TRACE_of_piperun(TRACE_of_piperun), + .TRACE_pc(TRACE_pc), + .TRACE_pid_reg(TRACE_pid_reg), + .TRACE_reg_addr(TRACE_reg_addr), + .TRACE_reg_write(TRACE_reg_write), + .TRACE_valid_instr(TRACE_valid_instr)); +endmodule diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci new file mode 100644 index 0000000..066b427 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci @@ -0,0 +1,955 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_microblaze_I_0 + + + + 100000000 + 0.000 + + 30000000 + 0.000 + 1 + 32 + 0 + LEVEL_HIGH + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 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Base Address + 0x0000000000000000 + + + C_DCACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + C_USE_DCACHE + Enable Data Cache + 0 + + + C_ALLOW_DCACHE_WR + Enable Writes + 1 + + + C_DCACHE_ADDR_TAG + 17 + + + C_DCACHE_BYTE_SIZE + Size in Bytes + 8192 + + + C_DCACHE_LINE_LEN + Line Length + 4 + + + C_DCACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 0 + + + C_DCACHE_USE_WRITEBACK + Enable Write-back Storage Policy + 0 + + + + true + + + + + + C_DCACHE_VICTIMS + Number of Victims + 0 + + + + false + + + + + + C_DCACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + C_DCACHE_DATA_WIDTH + Data Width + 0 + + + + false + + + + + + C_M_AXI_DC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_DATA_WIDTH + 32 + + + C_M_AXI_DC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DC_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_M_AXI_DC_USER_VALUE + 31 + + + + true + + + + + + C_M_AXI_DC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_BUSER_WIDTH + 1 + + + + true + + + + + + + + + choice_list_29910ba8 + GENERIC + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_b1aff63c + 32 + 48 + 64 + + + choice_list_b94541ab + 0 + 2 + 4 + 8 + + + choice_list_dd2843c6 + 1 + 2 + 4 + 8 + + + choice_list_f86403bf + 4 + 8 + 16 + + + choice_pairs_0000a26c + 0 + 1 + 2 + 3 + + + choice_pairs_1075faf2 + 0 + 1 + 2 + + + choice_pairs_126baff7 + 0 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_13d40c7c + 0 + 32 + 64 + 128 + 256 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_2058dc69 + 0 + 1 + + + choice_pairs_22d9f392 + 0 + 1 + 2 + 3 + + + choice_pairs_3eb333f8 + 0 + 1 + 2 + + + choice_pairs_443ae6cc + 0 + 1 + 2 + 3 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_56d5ba32 + 0 + 1 + 2 + + + choice_pairs_5ab38e91 + 0 + 1 + 2 + + + choice_pairs_5b1842a1 + 0 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_75c71b2b + 0 + 1 + 2 + 3 + + + choice_pairs_7ad6afc0 + 0 + 1 + 2 + 3 + + + choice_pairs_7bfd418d + 0 + 1 + 2 + + + choice_pairs_7dd2834f + 0 + 8 + 9 + 10 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_8b498448 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + + + choice_pairs_b1fa18d9 + 0 + 1 + 2 + + + choice_pairs_c471ed24 + 32 + 36 + 40 + 44 + 48 + 52 + 64 + + + choice_pairs_db57ca32 + 0 + 1 + 2 + + + choice_pairs_e7a1eb81 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_ff364cce + 2 + 3 + + + + + microblaze + + + + endian + little + + + instance_path + + + + bootloop_file + data/mb_bootloop_le.elf + + + processor_type + MICROBLAZE_LE + + + is_visible + true + + + + + The MicroBlaze 32 bit soft processor core, providing an instruction set optimized for embedded applications with many user-configurable options. MicroBlaze has many advanced architecture features like Instruction and Data-side cache with AXI interfaces, Floating-Point unit (FPU), Memory Management Unit (MMU), and fault tolerance support. +It is highly recommended to create MicroBlaze systems within Vivado IP Integrator, to enable export to the Xilinx Software Development Kit (SDK) for software development. + + + + C_SCO + 0 + + + + true + + + + + + C_FREQ + 100000000 + + + + true + + + + + + C_DATA_SIZE + 32 + + + + true + + + + + + C_ADDR_SIZE + Select Extended Addressing + 32 + + + + true + + + + + + C_DYNAMIC_BUS_SIZING + 0 + + + + true + + + + + + C_PC_WIDTH + 17 + + + + true + + + + + + C_INSTANCE + mb_microblaze_0 + + + + true + + + + + + C_AVOID_PRIMITIVES + 0 + + + + true + + + + + + C_FAULT_TOLERANT + Enable Fault Tolerance Support + 0 + + + + true + + + + + + C_ECC_USE_CE_EXCEPTION + Correctable Error Exception + 0 + + + + true + + + + + + C_LOCKSTEP_SLAVE + Lockstep Slave + 0 + + + + true + + + + + + C_ENDIANNESS + Endianness + 1 + + + + true + + + + + + C_AREA_OPTIMIZED + Select implementation optimization + 0 + + + + true + + + + + + C_OPTIMIZATION + 0 + + + + true + + + + + + C_INTERCONNECT + Select Bus Interface + 2 + + + + true + + + + + + C_BASE_VECTORS + Vector Base Address + 0x00000000 + + + + true + + + + + + C_USE_CONFIG_RESET + 0 + + + + true + + + + + + C_NUM_SYNC_FF_CLK + Synchronizing FFs to Clk region + 2 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_IRQ + Synchronizing FFs to Clk region for interrupt input + 1 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_DEBUG + Synchronizing FFs to Clk region in debug module + 2 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_CLK + Synchronizing FFs to Dbg_Clk region + 1 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_TRACE_CLK + Synchronizing FFs to Dbg_Trace_Clk region + 2 + + + + true + + + + + + C_M_AXI_DP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_D_AXI + Enable Peripheral AXI Data Interface + 0 + + + + true + + + + + + C_DP_AXI_MON + Use Monitor Interface for Peripheral AXI Data Interface + 0 + + + + true + + + + + + C_DC_AXI_MON + Use Monitor Interface for Cache AXI Data Interface + 0 + + + + true + + + + + + C_D_LMB + Enable Local Memory Bus Data Interface + 1 + + + + true + + + + + + C_D_LMB_MON + Use Monitor Interface for Local Memory Bus Data Interface + 0 + + + + true + + + + + + C_M_AXI_IP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IP_ADDR_WIDTH + 32 + + + + true + + + + + + C_I_AXI + Enable Peripheral AXI Instruction Interface + 0 + + + + true + + + + + + C_IP_AXI_MON + Use Monitor Interface for Peripheral AXI Instruction Interface + 0 + + + + true + + + + + + C_IC_AXI_MON + Use Monitor Interface for Cache AXI Instruction Interface + 0 + + + + true + + + + + + C_I_LMB + Enable Local Memory Bus Instruction Interface + 1 + + + + true + + + + + + C_I_LMB_MON + Use Monitor Interface for Local Memory Bus Instruction Interface + 0 + + + + true + + + + + + C_TRACE + Enable Trace Bus Interface + 1 + + + + true + + + + + + C_LOCKSTEP_SELECT + Lockstep Interface + 0 + + + + true + + + + + + C_ENABLE_DISCRETE_PORTS + Enable Discrete Ports + 0 + + + + true + + + + + + C_M_AXI_DC_USER_SIGNALS + Enable M_AXI_DC User Signals + 0 + + + + true + + + + + + C_M_AXI_IC_USER_SIGNALS + Enable M_AXI_IC User Signals + 0 + + + + true + + + + + + G_TEMPLATE_LIST + Select Configuration + 0 + + + + true + + + + + + G_USE_EXCEPTIONS + Enable Exceptions + 0 + + + + true + + + + + + C_USE_MSR_INSTR + Enable Additional Machine Status Register Instructions + 0 + + + + true + + + + + + C_USE_PCMP_INSTR + Enable Pattern Comparator + 1 + + + + true + + + + + + C_USE_REORDER_INSTR + Enable Reversed Load/Store and Swap Instructions + 0 + + + + true + + + + + + C_USE_BARREL + Enable Barrel Shifter + 1 + + + + true + + + + + + C_USE_DIV + Enable Integer Divider + 1 + + + + true + + + + + + C_USE_HW_MUL + Enable Integer Multiplier + 1 + + + + true + + + + + + C_USE_FPU + Enable Floating Point Unit + 0 + + + + true + + + + + + C_UNALIGNED_EXCEPTIONS + Enable Unaligned Data Exception + 0 + + + + true + + + + + + C_ILL_OPCODE_EXCEPTION + Enable Illegal Instruction Exception + 0 + + + + true + + + + + + C_M_AXI_I_BUS_EXCEPTION + Enable Instruction-side AXI Exception + 0 + + + + false + + + + + + C_M_AXI_D_BUS_EXCEPTION + Enable Data-side AXI Exception + 0 + + + + false + + + + + + C_DIV_ZERO_EXCEPTION + Enable Integer Divide Exception + 0 + + + + true + + + + + + C_FPU_EXCEPTION + Enable Floating Point Unit Exceptions + 0 + + + + false + + + + + + C_FSL_EXCEPTION + Enable Stream Exception + 0 + + + + false + + + + + + C_USE_STACK_PROTECTION + Enable stack protection + 0 + + + + true + + + + + + C_IMPRECISE_EXCEPTIONS + Allow Imprecise Exceptions + 0 + + + + true + + + + + + C_PVR + Specifies Processor Version Register + 0 + + + + true + + + + + + C_PVR_USER1 + Specify USER1 Bits in Processor Version Register + 0x00 + + + + false + + + + + + C_PVR_USER2 + Specify USER2 Bits in Processor Version Register + 0x00000000 + + + + false + + + + + + C_DEBUG_ENABLED + MicroBlaze Debug Module Interface + 0 + + + + true + + + + + + C_DEBUG_INTERFACE + MicroBlaze Debug Connection + 0 + + + + true + + + + + + C_NUMBER_OF_PC_BRK + Number of PC Breakpoints + 1 + + + + false + + + + + + C_NUMBER_OF_RD_ADDR_BRK + Number of Read Address Watchpoints + 0 + + + + false + + + + + + C_NUMBER_OF_WR_ADDR_BRK + Number of Write Address Watchpoints + 0 + + + + false + + + + + + C_DEBUG_EVENT_COUNTERS + Number of Performance Monitor Event Counters + 5 + + + + false + + + + + + C_DEBUG_LATENCY_COUNTERS + Number of Performance Monitor Latency Counters + 1 + + + + false + + + + + + C_DEBUG_COUNTER_WIDTH + Performance Monitor Counter Width + 32 + + + + false + + + + + + C_DEBUG_TRACE_SIZE + Trace Buffer Size + 8192 + + + + false + + + + + + C_DEBUG_EXTERNAL_TRACE + External Trace + 0 + + + + false + + + + + + C_DEBUG_TRACE_ASYNC_RESET + Use Asynchrnous Reset for External Trace + 0 + + + + true + + + + + + C_DEBUG_PROFILE_SIZE + Profile Buffer Size + 0 + + + + false + + + + + + C_INTERRUPT_IS_EDGE + Sense Interrupt on Edge vs. Level + 0 + + + + true + + + + + + C_EDGE_IS_POSITIVE + Sense Interrupt on Rising vs. Falling Edge + 1 + + + + true + + + + + + C_ASYNC_INTERRUPT + 1 + + + + true + + + + + + C_ASYNC_WAKEUP + 3 + + + + true + + + + + + C_RESET_MSR_IE + IE + 0 + + + + true + + + + + + C_RESET_MSR_BIP + BIP + 0 + + + + true + + + + + + C_RESET_MSR_ICE + ICE + 0 + + + + true + + + + + + C_RESET_MSR_DCE + DCE + 0 + + + + true + + + + + + C_RESET_MSR_EE + EE + 0 + + + + true + + + + + + C_RESET_MSR_EIP + EIP + 0 + + + + true + + + + + + C_OPCODE_0x0_ILLEGAL + Generate Illegal Instruction Exception for NULL Instruction + 0 + + + + false + + + + + + C_FSL_LINKS + Number of Stream Links + 0 + + + + true + + + + + + C_USE_EXTENDED_FSL_INSTR + Enable Additional Stream Instructions + 0 + + + + false + + + + + + C_M0_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S0_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M1_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S1_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M2_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S2_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M3_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S3_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M4_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S4_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M5_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S5_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M6_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S6_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M7_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S7_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + 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32 + + + + true + + + + + + C_S1_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M2_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S2_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M3_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S3_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M4_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S4_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M5_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S5_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M6_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S6_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M7_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S7_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M8_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S8_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M9_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S9_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M10_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S10_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M11_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S11_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M12_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S12_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M13_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S13_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M14_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S14_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M15_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S15_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_ICACHE_BASEADDR + Base Address + 0x0000000000000000 + + + + false + + + + + + C_ICACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + + false + + + + + + C_USE_ICACHE + Enable Instruction Cache + 0 + + + + true + + + + + + C_ALLOW_ICACHE_WR + Enable Writes + 1 + + + + false + + + + + + C_ADDR_TAG_BITS + Set number of I-cache address tag bits + 17 + + + + true + + + + + + C_CACHE_BYTE_SIZE + Size in Bytes + 8192 + + + + false + + + + + + C_ICACHE_LINE_LEN + Line Length + 4 + + + + false + + + + + + C_ICACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 0 + + + + false + + + + + + C_ICACHE_VICTIMS + Number of Victims + 0 + + + + false + + + + + + C_ICACHE_STREAMS + Number of Streams + 0 + + + + false + + + + + + C_ICACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + + false + + + + + + C_ICACHE_DATA_WIDTH + Data Width + 0 + + + + false + + + + + + C_M_AXI_IC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_BUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_USER_VALUE + 31 + + + + true + + + + + + C_DCACHE_BASEADDR + Base Address + 0x0000000000000000 + + + + false + + + + + + C_DCACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + + false + + + + + + C_USE_DCACHE + Enable Data Cache + 0 + + + + true + + + + + + C_ALLOW_DCACHE_WR + Enable Writes + 1 + + + + false + + + + + + C_DCACHE_ADDR_TAG + Set number of D-cache address tag bits + 17 + + + + true + + + + + + C_DCACHE_BYTE_SIZE + Size in Bytes + 8192 + + + + false + + + + + + C_DCACHE_LINE_LEN + Line Length + 4 + + + + false + + + + + + C_DCACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 0 + + + + false + + + + + + C_DCACHE_USE_WRITEBACK + Enable Write-back Storage Policy + 0 + + + + false + + + + + + C_DCACHE_VICTIMS + Number of Victims + 0 + + + + false + + + + + + C_DCACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + + false + + + + + + C_DCACHE_DATA_WIDTH + Data Width + 0 + + + + false + + + + + + C_M_AXI_DC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_WUSER_WIDTH + 1 + + + + true + + + + + + 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C_USE_NON_SECURE + Use Non-Secure AXI access permission + 0 + + + + true + + + + + + C_USE_BRANCH_TARGET_CACHE + Enable Branch Target Cache + 0 + + + + true + + + + + + C_BRANCH_TARGET_CACHE_SIZE + Branch Target Cache Size + 0 + + + + true + + + + + + Component_Name + bd_ba6a_microblaze_I_0 + + + + + MicroBlaze + + XPM_MEMORY + + 7 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xci new file mode 100644 index 0000000..a6b4d4c --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xci @@ -0,0 +1,71 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_rst_0_0 + + + ACTIVE_LOW + + + 100000000 + 0.000 + ACTIVE_HIGH + 0 + 4 + 1 + 4 + virtexuplus + 1 + 1 + 1 + 1 + 0 + 4 + 1 + 4 + 1 + 1 + 1 + 1 + bd_ba6a_rst_0_0 + Custom + false + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 12 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xml new file mode 100644 index 0000000..2bb95d5 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xml @@ -0,0 +1,583 @@ + + + xilinx.com + customized_ip + bd_ba6a_rst_0_0 + 1.0 + + + clock + Clock + + + + + + + CLK + + + slowest_sync_clk + + + + + + ASSOCIATED_RESET + mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset + + + FREQ_HZ + Slowest Sync clock frequency + Slowest Synchronous clock frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + + + ext_reset + Ext_Reset + + + + + + + RST + + + ext_reset_in + + + + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + + required + + + + + + POLARITY + ACTIVE_HIGH + + + none + + + + + + + aux_reset + aux_reset + + + + + + + RST + + + aux_reset_in + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + + + dbg_reset + DBG_Reset + + + + + + + RST + + + mb_debug_sys_rst + + + + + + POLARITY + ACTIVE_HIGH + + + + + mb_rst + MB_rst + + + + + + + RST + + + mb_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PROCESSOR + + + + + bus_struct_reset + bus_struct_reset + + + + + + + RST + + + bus_struct_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + interconnect_low_rst + interconnect_low_rst + + + + + + + RST + + + interconnect_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + INTERCONNECT + + + + + peripheral_high_rst + peripheral_high_rst + + + + + + + RST + + + peripheral_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + + + peripheral_low_rst + peripheral_low_rst + + + + + + + RST + + + peripheral_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + PERIPHERAL + + + + + + + + slowest_sync_clk + + in + + + std_logic + dummy_view + + + + + + ext_reset_in + + in + + + std_logic + dummy_view + + + + + + aux_reset_in + + in + + + std_logic + dummy_view + + + + 1 + + + + + mb_debug_sys_rst + + in + + + std_logic + dummy_view + + + + 0 + + + + + dcm_locked + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + mb_reset + + out + + + std_logic + dummy_view + + + + 0x0 + + + + + bus_struct_reset + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + peripheral_reset + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + interconnect_aresetn + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 1 + + + + + peripheral_aresetn + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 1 + + + + + + + C_FAMILY + virtexuplus + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RESET_HIGH + Ext Reset High + 1 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + + + + choice_list_ac75ef1e + Custom + + + Processor Reset System + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_EXT_RESET_HIGH + Ext Reset High + 1 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + Component_Name + bd_ba6a_rst_0_0 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + RESET_BOARD_INTERFACE + Custom + + + + + Processor System Reset + 12 + + + + + + + + + + 2018.2 + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xci new file mode 100644 index 0000000..092f511 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xci @@ -0,0 +1,272 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_iomodule_0_0 + + + + 100000000 + 0.000 + 1 + LEVEL_HIGH + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 32 + 32 + READ_WRITE + 0 + 0x0000000080000000 + virtexuplus + 0 + 6216 + 0 + 6216 + 0 + 6216 + 0 + 6216 + 100000000 + 0 + 32 + 0 + 32 + 0 + 32 + 0 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x000000008000FFFF + iomodule + 17 + 0xFFFF + 0x00000000 + 1 + 1 + 0x0000 + 2 + 0xFFFF + 0 + 0x00000000C0000000 + 0x00000000FFFFFFFF + 0x00000000C0000000 + 32 + 32 + 0x00000000C0000000 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 9600 + 8 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0x0000000080000000 + 0 + 6216 + 0 + 6216 + 0 + 6216 + 0 + 6216 + 100000000 + 0 + 32 + 0 + 32 + 0 + 32 + 0 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x000000008000FFFF + iomodule + 17 + 0xFFFF + 0x00000000 + 1 + 1 + 0 + 0x0000 + 2 + 0xFFFF + 0 + 1 + 0x00000000C0000000 + 0x00000000FFFFFFFF + 0x00000000C0000000 + 32 + 32 + 0x00000000C0000000 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 9600 + 8 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + bd_ba6a_iomodule_0_0 + Custom + Custom + Custom + Custom + Custom + false + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 3 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml new file mode 100644 index 0000000..240f1be --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml @@ -0,0 +1,7497 @@ + + + xilinx.com + customized_ip + bd_ba6a_iomodule_0_0 + 1.0 + + + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + CLK.CLK + Clk + Clock Input + + + + + + + CLK + + + Clk + + + + + + ASSOCIATED_BUSIF + SLMB + + + ASSOCIATED_RESET + Rst:TMR_Rst + + + FREQ_HZ + Clk frequency + Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.Rst + Rst + Reset Input + + + + + + + RST + + + Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + + + RST.TMR_Rst + TMR_Rst + TMR Reset Input + + + + + + + RST + + + TMR_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + + + IO_BUS + IO_BUS + MicroBlaze MCS IO Bus Interface + + + + + + + ADDR_STROBE + + + IO_Addr_Strobe + + + + + ADDRESS + + + IO_Address + + + + + BYTE_ENABLE + + + IO_Byte_Enable + + + + + READ_DATA + + + IO_Read_Data + + + + + READ_STROBE + + + IO_Read_Strobe + + + + + READY + + + IO_Ready + + + + + WRITE_DATA + + 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+ + ADDRESS + + + INTC_Interrupt_Address + + + + + INTERRUPT + + + INTC_IRQ + + + + + + SENSITIVITY + LEVEL_HIGH + + + LOW_LATENCY + 0 + + + + + + false + + + + + + INTERRUPT.INTC_Irq_Out + INTC_IRQ_OUT + + + + + + + INTERRUPT + + + INTC_IRQ_OUT + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + UART + UART + UART TX/RX + + + + + + + RxD + + + UART_Rx + + + + + TxD + + + UART_Tx + + + + + + BOARD.ASSOCIATED_PARAM + UART_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO1 + GPIO1 + General Purpose IO + + + + + + + TRI_I + + + GPI1 + + + + + TRI_O + + + GPO1 + + + + + + C_USE_GPO1 + 0 + + + + true + + + + + + C_GPO1_SIZE + 32 + + + + true + + + + + + C_GPO1_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI1 + 0 + + + + true + + + + + + C_GPI1_SIZE + 32 + + + + true + + + + + + C_GPI1_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO1_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO2 + GPIO2 + General Purpose IO + + + + + + + TRI_I + + + GPI2 + + + + + TRI_O + + + GPO2 + + + + + + C_USE_GPO2 + 0 + + + + true + + + + + + C_GPO2_SIZE + 32 + + + + true + + + + + + C_GPO2_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI2 + 0 + + + + true + + + + + + C_GPI2_SIZE + 32 + + + + true + + + + + + C_GPI2_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO2_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO3 + GPIO3 + General Purpose IO + + + + + + + TRI_I + + + GPI3 + + + + + TRI_O + + + GPO3 + + + + + + C_USE_GPO3 + 0 + + + + true + + + + + + C_GPO3_SIZE + 32 + + + + true + + + + + + C_GPO3_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI3 + 0 + + + + true + + + + + + C_GPI3_SIZE + 32 + + + + true + + + + + + C_GPI3_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO3_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + GPIO4 + GPIO4 + General Purpose IO + + + + + + + TRI_I + + + GPI4 + + + + + TRI_O + + + GPO4 + + + + + + C_USE_GPO4 + 0 + + + + true + + + + + + C_GPO4_SIZE + 32 + + + + true + + + + + + C_GPO4_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI4 + 0 + + + + true + + + + + + C_GPI4_SIZE + 32 + + + + true + + + + + + C_GPI4_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO4_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + + + SLMB + LMB memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + UART RX + UART Receive Data Register + UART Receive Data Register + 0x0 + 8 + true + read-only + + 0x0 + + + UART RX + Receive Data + Data received by the UART. + 0 + 8 + true + read-only + + 0 + 0 + + modify + false + + + + + false + + + + + + UART TX + UART Transmit Data Register + UART Transmit Data Register + 0x4 + 8 + true + write-only + + 0x0 + + + UART TX + Transmit Data + Data to be transmitted by the UART. + 0 + 8 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART Status + UART Status Register + UART Status Register + 0x8 + 8 + true + read-only + + 0x0 + + + Rx Valid Data + Rx Valid Data + Indicates if the receive register has valid data: + 0 - Receive register is empty. + 1 - Receive register has valid data. + + 0 + 1 + true + read-only + + 0 + 0 + + false + + + Tx Used + Tx Used + Indicates if the transmit register is in use: + 0 - Transmit register is not in use. + 1 - Transmit register is in use. + + 3 + 1 + true + read-only + + 0 + 0 + + false + + + Overrun Error + Overrun Error + Indicates that an overrun error has occurred: + 0 - No overrun has occurred. + 1 - An overrun has occurred. + + 5 + 1 + true + read-only + + 0 + 0 + + false + + + Frame Error + Frame Error + Indicates that an frame error has occurred: + 0 - No frame error has occurred. + 1 - A frame error has occurred. + + 6 + 1 + true + read-only + + 0 + 0 + + false + + + Parity Error + Parity Error + Indicates that a parity error has occurred: + 0 - No parity error has occurred. + 1 - A parity error occurred. + + 7 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ MODE + Interrupt Mode Register + Interrupt Mode Register + 0xC + 17 + true + write-only + + 0x0 + + + IRQ Mode + IRQ Mode + Interrupt Mode. +For each bit: + W - When written with 1 the corresponding interrupt will use fast mode. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + GPO 1 + General Purpose Output 1 Register + General Purpose Output 1 Register + 0x10 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 2 + General Purpose Output 2 Register + General Purpose Output 2 Register + 0x14 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 3 + General Purpose Output 3 Register + General Purpose Output 3 Register + 0x18 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 4 + General Purpose Output 4 Register + General Purpose Output 4 Register + 0x1C + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 1 + General Purpose Input 1 Register + General Purpose Input 1 Register + 0x20 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 2 + General Purpose Input 2 Register + General Purpose Input 2 Register + 0x24 + 32 + true + read-only + + 0 + + + CPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 3 + General Purpose Input 3 Register + General Purpose Input 3 Register + 0x28 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 4 + General Purpose Input 4 Register + General Purpose Input 4 Register + 0x2C + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ STATUS + Interrupt Status Register + Interrupt Status Register + 0x30 + 17 + true + read-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC Interrupt + External interrupt input signal + Interrupt Status Register. +For each bit: + R - Reads active interrupt signal. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ PENDING + Interrupt Pending Register + Interrupt Pending Register + 0x34 + 17 + true + read-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC Interrupt + Enabled interrupt events that have occurred + Interrupt Pending. +For each bit: + R - Reads enabled interrupt event that has occurred. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ ENABLE + Interrupt Enable Register + Interrupt Enable Register + 0x38 + 17 + true + write-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt enabled. + 0 + 1 + true + write-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt enabled. + 1 + 1 + true + write-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt enabled. + 2 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 interrupt enabled. + 3 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 interrupt enabled. + 4 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 interrupt enabled. + 5 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 interrupt enabled. + 6 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 interrupt enabled. + 7 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 interrupt enabled. + 8 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 interrupt enabled. + 9 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 interrupt enabled. + 10 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 interrupt enabled. + 11 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 interrupt enabled. + 12 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 interrupt enabled. + 13 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 interrupt enabled. + 14 + 1 + true + write-only + + 0 + 0 + + false + + + INTC Interrupt + Enable external interrupt input signals + Interrupt Enable. +For each bit: + W - Enable external interrupt input signal. + + 16 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ ACK + Interrupt Acknowledge Register + Interrupt Acknowledge Register + 0x3C + 17 + true + write-only + + 0x0 + + + IRQ Acknowledge + IRQ Acknowledge + Interrupt Acknowledge. +For each bit: + W - When written with 1 clear bit in IRQ_STATUS and IRQ_PENDING. + + 0 + 17 + true + write-only + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + PIT1 PRELOAD + PIT 1 Preload Register + PIT 1 Preload Register + 0x40 + 32 + true + write-only + + 0x0 + + + PIT1 Preload + PIT1 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1 COUNTER + PIT 1 Counter Register + PIT 1 Counter Register + 0x44 + 32 + true + read-only + + 0x0 + + + PIT1 Counter + PIT1 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1 CONTROL + PIT 1 Control Register + PIT 1 Control Register + 0x48 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT1_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART BAUD + UART Programmable Baud Rate + UART Programmable Baud Rate + 0x4C + 8 + true + write-only + + 0x0 + + + UART BAUD + Baud Rate + Programmable UART Baud Rate. + 0 + 20 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 PRELOAD + PIT 2 Preload Register + PIT 2 Preload Register + 0x50 + 32 + true + write-only + + 0x0 + + + PIT2 Preload + PIT2 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 COUNTER + PIT 2 Counter Register + PIT 2 Counter Register + 0x54 + 32 + true + read-only + + 0x0 + + + PIT2 Counter + PIT2 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 CONTROL + PIT 2 Control Register + PIT 2 Control Register + 0x58 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT2_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 PRELOAD + PIT 3 Preload Register + PIT 3 Preload Register + 0x60 + 32 + true + write-only + + 0x0 + + + PIT3 Preload + PIT3 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 COUNTER + PIT 3 Counter Register + PIT 3 Counter Register + 0x64 + 32 + true + read-only + + 0x0 + + + PIT3 Counter + PIT3 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 CONTROL + PIT 3 Control Register + PIT 3 Control Register + 0x68 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT3_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 PRELOAD + PIT 4 Preload Register + PIT 4 Preload Register + 0x70 + 32 + true + write-only + + 0x0 + + + PIT4 Preload + PIT4 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 COUNTER + PIT 4 Counter Register + PIT 4 Counter Register + 0x74 + 32 + true + read-only + + 0x0 + + + PIT4 Counter + PIT4 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 CONTROL + PIT 4 Control Register + PIT 4 Control Register + 0x78 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT4_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 0 + Interrupt Vector Register 0 + Interrupt Vector Register 0 + 0x80 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 0 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 1 + Interrupt Vector Register 1 + Interrupt Vector Register 1 + 0x84 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 1 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 2 + Interrupt Vector Register 2 + Interrupt Vector Register 2 + 0x88 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 2 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 3 + Interrupt Vector Register 3 + Interrupt Vector Register 3 + 0x8C + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 3 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 4 + Interrupt Vector Register 4 + Interrupt Vector Register 4 + 0x90 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 4 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 5 + Interrupt Vector Register 5 + Interrupt Vector Register 5 + 0x94 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 5 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 6 + Interrupt Vector Register 6 + Interrupt Vector Register 6 + 0x98 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 6 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 7 + Interrupt Vector Register 7 + Interrupt Vector Register 7 + 0x9C + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 7 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 8 + Interrupt Vector Register 8 + Interrupt Vector Register 8 + 0xA0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 8 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 9 + Interrupt Vector Register 9 + Interrupt Vector Register 9 + 0xA4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 9 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 10 + Interrupt Vector Register 10 + Interrupt Vector Register 10 + 0xA8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 10 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 11 + Interrupt Vector Register 11 + Interrupt Vector Register 11 + 0xAC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 11 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 12 + Interrupt Vector Register 12 + Interrupt Vector Register 12 + 0xB0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 12 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 13 + Interrupt Vector Register 13 + Interrupt Vector Register 13 + 0xB4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 13 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 14 + Interrupt Vector Register 14 + Interrupt Vector Register 14 + 0xB8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 14 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 16 + Interrupt Vector Register 16 + Interrupt Vector Register 16 + 0xC0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 16 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + IRQ VECTOR 17 + Interrupt Vector Register 17 + Interrupt Vector Register 17 + 0xC4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 17 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 18 + Interrupt Vector Register 18 + Interrupt Vector Register 18 + 0xC8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 18 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 19 + Interrupt Vector Register 19 + Interrupt Vector Register 19 + 0xCC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 19 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 20 + Interrupt Vector Register 20 + Interrupt Vector Register 20 + 0xD0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 20 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 21 + Interrupt Vector Register 21 + Interrupt Vector Register 21 + 0xD4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 21 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 22 + Interrupt Vector Register 22 + Interrupt Vector Register 22 + 0xD8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 22 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 23 + Interrupt Vector Register 23 + Interrupt Vector Register 23 + 0xDC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 23 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 24 + Interrupt Vector Register 24 + Interrupt Vector Register 24 + 0xE0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 24 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 25 + Interrupt Vector Register 25 + Interrupt Vector Register 25 + 0xE4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 25 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 26 + Interrupt Vector Register 26 + Interrupt Vector Register 26 + 0xE8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 26 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 27 + Interrupt Vector Register 27 + Interrupt Vector Register 27 + 0xEC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 27 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 28 + Interrupt Vector Register 28 + Interrupt Vector Register 28 + 0xF0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 28 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 29 + Interrupt Vector Register 29 + Interrupt Vector Register 29 + 0xF4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 29 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 30 + Interrupt Vector Register 30 + Interrupt Vector Register 30 + 0xF8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 30 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 31 + Interrupt Vector Register 31 + Interrupt Vector Register 31 + 0xFC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 31 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + + IO + 0 + 65536 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_IO_BASEADDR + + + OFFSET_HIGH_PARAM + C_IO_HIGHADDR + + + + + + true + + + + + + + + + + Clk + + in + + + std_logic + dummy_view + + + + + + Rst + + in + + + std_logic + dummy_view + + + + + + Config_Reset + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + TMR_Rst + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + TMR_Disable + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + ToVote + + out + + 1023 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + FromAVote + + in + + 1023 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + FromBVote + + in + + 1023 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + IO_Addr_Strobe + + out + + + std_logic + dummy_view + + + + + + + true + + + + + + IO_Read_Strobe + + out + + + std_logic + dummy_view + + + + + + + true + + + + + + IO_Write_Strobe + + out + + + std_logic + dummy_view + + + + + + + true + + + + + + IO_Address + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + true + + + + + + IO_Byte_Enable + + out + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + + + + true + + + + + + IO_Write_Data + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + true + + + + + + IO_Read_Data + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + true + + + + + + IO_Ready + + in + + + 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+ + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + 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in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + Sl1_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + Sl1_Ready + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_Wait + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + LMB2_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_ReadStrobe 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C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_BRAM_AWIDTH + BRAM Address Bus Width + 32 + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + false + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + false + + + + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_449ac0d2 + 0 + 1 + 2 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_8d6e70ff + 0 + 2 + + + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000000000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x000000000000FFFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x00000000C0010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_ba6a_dlmb_cntlr_0 + + + + + LMB BRAM Controller + 15 + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xci new file mode 100644 index 0000000..7b4a912 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_ilmb_cntlr_0 + + + NONE + 65536 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000000000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000000000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_ba6a_ilmb_cntlr_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 15 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xml new file mode 100644 index 0000000..18d0cc5 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xml @@ -0,0 +1,3874 @@ + + + xilinx.com + customized_ip + bd_ba6a_ilmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 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C_HAS_SOFTECC_INPUT_REGS_A + 0 + + + C_HAS_SOFTECC_OUTPUT_REGS_B + 0 + + + C_USE_SOFTECC + 0 + + + C_USE_ECC + 0 + + + C_EN_ECC_PIPE + 0 + + + C_HAS_INJECTERR + 0 + + + C_SIM_COLLISION_CHECK + ALL + + + C_COMMON_CLK + 0 + + + C_DISABLE_WARN_BHV_COLL + 0 + + + C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 1 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 16 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 19.660986 mW + + + + + + choice_list_0132492a + 32 + 64 + 128 + + + choice_list_302d3091 + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_6fc15197 + 32 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f9a6a28b + Native + + + choice_pairs_1f270a52 + BRAM_Controller + Stand_Alone + + + choice_pairs_246d8066 + WRITE_FIRST + READ_FIRST + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_ba6a_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false 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a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci new file mode 100644 index 0000000..cb44116 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_second_dlmb_cntlr_0 + + + NONE + 32768 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000010000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x0000000000017FFF + 0 + 32 + 32 + 0x00000000C0010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 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WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 32768 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + LMB_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + Sl_Ready + + out + + + std_logic + dummy_view + + + + + + Sl_Wait + + out + + + std_logic + dummy_view + + + + + + Sl_UE + + out + + + std_logic + dummy_view + + + + + + Sl_CE + + out + + + std_logic + dummy_view + + + + + + LMB1_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + Sl1_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + Sl1_Ready + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_Wait + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + LMB2_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + Sl2_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + Sl2_Ready + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_Wait + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + LMB3_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + Sl3_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + Sl3_Ready + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl3_Wait + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl3_UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl3_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + BRAM_Rst_A + + out + + + std_logic + dummy_view + + + + + + BRAM_Clk_A + + out + + + std_logic + dummy_view + + + + + + BRAM_Addr_A + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + BRAM_EN_A + + out + + + std_logic + dummy_view + + + + + + BRAM_WEN_A + + out + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + + + BRAM_Dout_A + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + BRAM_Din_A + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + S_AXI_CTRL_ACLK + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARESETN + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_WDATA + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RDATA + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + + + C_FAMILY + virtexuplus + + + C_HIGHADDR + LMB BRAM High Address + 0x0000000000017FFF + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000010000 + + + C_NUM_LMB + Number of LMB Ports + 1 + + + C_MASK + SLMB Address Decode Mask + 0x00000000C0010000 + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + C_ECC + Error Correction Code + 0 + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_BRAM_AWIDTH + BRAM Address Bus Width + 32 + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + false + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + false + + + + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_449ac0d2 + 0 + 1 + 2 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_8d6e70ff + 0 + 2 + + + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000010000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x0000000000017FFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x00000000C0010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_ba6a_second_dlmb_cntlr_0 + + + + + LMB BRAM Controller + 15 + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xci new file mode 100644 index 0000000..9019caf --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_ba6a_second_ilmb_cntlr_0 + + + NONE + 32768 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000010000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x0000000000017FFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000010000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x0000000000017FFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_ba6a_second_ilmb_cntlr_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 15 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xml new file mode 100644 index 0000000..e246cb6 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xml @@ -0,0 +1,3874 @@ + + + xilinx.com + customized_ip + bd_ba6a_second_ilmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 32768 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + 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choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_ba6a_second_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A 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choice_pairs_4873554b + 0 + 1 + + + choice_pairs_5502e96b + 1 + 2 + 3 + 4 + + + choice_pairs_563648c8 + 0 + 1 + + + choice_pairs_5f1e379e + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 9 + + + choice_pairs_7ba91213 + 0 + 1 + 2 + 3 + + + choice_pairs_f0f6eb36 + 0 + 1 + 2 + 3 + 4 + 6 + 7 + 8 + 9 + + + choice_pairs_f7e0b771 + 4096 + 8192 + 12288 + 16384 + 20480 + 24576 + 32768 + 36864 + 40960 + 49152 + 65536 + 69632 + 73728 + 81920 + 98304 + 131072 + + + choice_pairs_ffa336e4 + 0 + 1 + + + + + xilinx_elaborateports_view_fileset + + ../bd_0/bd_ba6a.bd + block_diagram + + + + xilinx_elaboratebd_view_fileset + + ../bd_0/bd_ba6a.bd + block_diagram + + + + MicroBlaze Micro Controller System (MCS) is a light-weight general purpose micro controller system, based on the MicroBlaze processor. It is primarily intended for simple control applications, where a hardware solution would be less flexible and more difficult to implement. Software development with the Xilinx Software Development Kit (SDK) is supported, including a software driver for the peripherals. Debugging including UART is available either via SDK or directly with the Xilinx Microprocessor Debugger. +The MCS consists of the processor itself, local memory with sizes ranging from 4KB to 128KB, up to 4 Fixed Interval Timers, up to 4 Programmable Interval Timers, up to 4 32-bit General Purpose Output ports, up to 4 32-bit General Purpose Input ports, and an Interrupt Controller with up to 16 external interrupt inputs. + + + + JTAG_CHAIN + Debug JTAG User-defined Register + 2 + + + + false + + + + + + MICROBLAZE_INSTANCE + MicroBlaze Instance Name + microblaze_0 + + + AVOID_PRIMITIVES + 0 + + + PATH + Instance Hierarchical Design Name + mcs_0 + + + FREQ + Input Clock Frequency (MHz) + 100.0 + + + OPTIMIZATION + Select MicroBlaze Optimization + 1 + + + DEBUG_ENABLED + Enable Debug Support + 0 + + + TRACE + Enable MicroBlaze Trace Bus + 1 + + + ECC + Error Correction Code + 0 + + + MEMSIZE + Memory Size + 98304 + + + USE_IO_BUS + Enable IO Bus + 1 + + + USE_UART_RX + Enable Receiver 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15'b111111111111111, 15'b111111111111111, + 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111101, 15'b111111111111111, + 15'b111111111111111 } + 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b +000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, + 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_000_000_000_000_000_000_000_000_001_001_001_001, 39'b001_001_001_000_000_001_001_001_001_001_001_001_001, 39'b000_001_001_001_001_101_101_001_00 +1_001_001_001_001 + false + 1 + 8 + 64 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + {{8{2'b11}}, {3{2'b00}}} + 11'b00000000000 + 1 + 3 + 1 + {13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 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+ NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xml new file mode 100644 index 0000000..77dbdc5 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xml @@ -0,0 +1,4864 @@ + + + xilinx.com + customized_ip + phy_ddr4_udimm_phy + 1.0 + + + + sys_clk_p + + in + + + wire + dummy_view + + + + 0 + + + + + + true + + + + + + sys_clk_n + + in + + + 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C0.DDR4_BA_SKEW_1 + 0 + + + C0.DDR4_BG_SKEW_0 + 0 + + + C0.DDR4_BG_SKEW_1 + 0 + + + C0.DDR4_CS_SKEW_0 + 0 + + + C0.DDR4_CS_SKEW_1 + 0 + + + C0.DDR4_CS_SKEW_2 + 0 + + + C0.DDR4_CS_SKEW_3 + 0 + + + C0.DDR4_CKE_SKEW_0 + 0 + + + C0.DDR4_CKE_SKEW_1 + 0 + + + C0.DDR4_CKE_SKEW_2 + 0 + + + C0.DDR4_CKE_SKEW_3 + 0 + + + C0.DDR4_ACT_SKEW + 0 + + + C0.DDR4_PAR_SKEW + 0 + + + C0.DDR4_ODT_SKEW_0 + 0 + + + C0.DDR4_ODT_SKEW_1 + 0 + + + C0.DDR4_ODT_SKEW_2 + 0 + + + C0.DDR4_ODT_SKEW_3 + 0 + + + C0.DDR4_LR_SKEW_0 + 0 + + + C0.DDR4_LR_SKEW_1 + 0 + + + C0.ADDR_WIDTH + ADDR WIDTH + 17 + + + C0.BANK_GROUP_WIDTH + BANK GROUP WIDTH + 2 + + + C0.LR_WIDTH + LR WIDTH + 1 + + + C0.CK_WIDTH + CK WIDTH + 1 + + + C0.CKE_WIDTH + CKE WIDTH + 1 + + + C0.CS_WIDTH + CS WIDTH + 1 + + + C0.ODT_WIDTH + ODT WIDTH + 1 + + + C0.StackHeight + 1 + + + PING_PONG_PHY + Ping Pong Phy + 1 + + + + + DDR4 SDRAM (MIG) + 5 + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bd b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bd new file mode 100644 index 0000000..ee1ca98 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bd @@ -0,0 +1,441 @@ + + + + + xilinx.com + BlockDiagram + bd_9d69 + 1.00.a + + + isTop + true + + + + + IO + + + + + + TRACE + + + + + + CLK.CLK + Clk + Clock + + + + + + + CLK + + + Clk + + + + + + FREQ_HZ + 100000000 + + + + + + + + PHASE + 0.000 + + + + + + + + ASSOCIATED_ASYNC_RESET + Reset + + + + + + + + + + RST.RESET + Reset + Reset + + + + + + + RST + + + Reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + Clk + + in + + + + Reset + + in + + + + + + + + xilinx.com + BlockDiagram + bd_9d69_imp + 1.00.a + + + microblaze_I + + + bd_9d69_microblaze_I_0 + 17 + mb_microblaze_0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 3 + 0 + 0 + + + + + rst_0 + + + bd_9d69_rst_0_0 + + + + ilmb + + + bd_9d69_ilmb_0 + 2 + + + + dlmb + + + bd_9d69_dlmb_0 + 3 + + + + dlmb_cntlr + + + bd_9d69_dlmb_cntlr_0 + 0x0000000000000000 + 0x000000000000FFFF + 0x00000000C0010000 + + + + + ilmb_cntlr + + + bd_9d69_ilmb_cntlr_0 + 0x0000000000000000 + 0x000000000000FFFF + 0x0000000080010000 + + + + lmb_bram_I + + + bd_9d69_lmb_bram_I_0 + True_Dual_Port_RAM + + + + second_dlmb_cntlr + + + bd_9d69_second_dlmb_cntlr_0 + 0x0000000000010000 + 0x0000000000017FFF + 0x00000000C0010000 + + + + + second_ilmb_cntlr + + + bd_9d69_second_ilmb_cntlr_0 + 0x0000000000010000 + 0x0000000000017FFF + 0x0000000080010000 + + + + second_lmb_bram_I + + + bd_9d69_second_lmb_bram_I_0 + True_Dual_Port_RAM + + + + iomodule_0 + + + bd_9d69_iomodule_0_0 + iomodule + 0x0000000080000000 + 0x000000008000FFFF + 0x00000000C0000000 + 1 + 0x00000000C0000000 + 0x00000000FFFFFFFF + 0x00000000C0000000 + 1 + 1 + 17 + + + + + + ilmb + + + + + dlmb + + + + + ilmb_sl_0 + + + + + dlmb_sl_0 + + + + + dlmb_sl_1 + + + + + ilmb_port + + + + + dlmb_port + + + + + ilmb_sl_1 + + + + + dlmb_sl_2 + + + + + ilmb_port_2 + + + + + dlmb_port_2 + + + + + + + Clk2 + + + + + + + + + + + + + Reset + + + + + MB_Reset + + + + + LMB_Rst2 + + + + + + + + + + IO_Rst + + + + + + + + + + + + + + + + xilinx.com + Addressing/microblaze_I + microblaze + 10.0 + + + DLMB + + + + + + + + ILMB + + + + + + + + + + Data + 4G + 32 + + + SEG_dlmb_cntlr_Mem + /dlmb_cntlr/SLMB/Mem + 0x00000000 + 64K + + + SEG_iomodule_0_IO + /iomodule_0/SLMB/IO + 0xC0000000 + 1G + + + SEG_iomodule_0_Reg + /iomodule_0/SLMB/Reg + 0x80000000 + 64K + + + SEG_second_dlmb_cntlr_Mem + /second_dlmb_cntlr/SLMB/Mem + 0x00010000 + 32K + + + + + Instruction + 4G + 32 + + + SEG_ilmb_cntlr_Mem + /ilmb_cntlr/SLMB/Mem + 0x00000000 + 64K + + + SEG_second_ilmb_cntlr_Mem + /second_ilmb_cntlr/SLMB/Mem + 0x00010000 + 32K + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bxml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bxml new file mode 100644 index 0000000..61f2511 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/bd_9d69.bxml @@ -0,0 +1,100 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/hdl/bd_9d69_wrapper.v b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/hdl/bd_9d69_wrapper.v new file mode 100644 index 0000000..8059f19 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/hdl/bd_9d69_wrapper.v @@ -0,0 +1,173 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Command: generate_target bd_9d69_wrapper.bd +//Design : bd_9d69_wrapper +//Purpose: IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module bd_9d69_wrapper + (Clk, + IO_addr_strobe, + IO_address, + IO_byte_enable, + IO_read_data, + IO_read_strobe, + IO_ready, + IO_write_data, + IO_write_strobe, + Reset, + TRACE_data_access, + TRACE_data_address, + TRACE_data_byte_enable, + TRACE_data_read, + TRACE_data_write, + TRACE_data_write_value, + TRACE_dcache_hit, + TRACE_dcache_rdy, + TRACE_dcache_read, + TRACE_dcache_req, + TRACE_delay_slot, + TRACE_ex_piperun, + TRACE_exception_kind, + TRACE_exception_taken, + TRACE_icache_hit, + TRACE_icache_rdy, + TRACE_icache_req, + TRACE_instruction, + TRACE_jump_hit, + TRACE_jump_taken, + TRACE_mb_halted, + TRACE_mem_piperun, + TRACE_msr_reg, + TRACE_new_reg_value, + TRACE_of_piperun, + TRACE_pc, + TRACE_pid_reg, + TRACE_reg_addr, + TRACE_reg_write, + TRACE_valid_instr); + input Clk; + output IO_addr_strobe; + output [31:0]IO_address; + output [3:0]IO_byte_enable; + input [31:0]IO_read_data; + output IO_read_strobe; + input IO_ready; + output [31:0]IO_write_data; + output IO_write_strobe; + input Reset; + output TRACE_data_access; + output [0:31]TRACE_data_address; + output [0:3]TRACE_data_byte_enable; + output TRACE_data_read; + output TRACE_data_write; + output [0:31]TRACE_data_write_value; + output TRACE_dcache_hit; + output TRACE_dcache_rdy; + output TRACE_dcache_read; + output TRACE_dcache_req; + output TRACE_delay_slot; + output TRACE_ex_piperun; + output [0:4]TRACE_exception_kind; + output TRACE_exception_taken; + output TRACE_icache_hit; + output TRACE_icache_rdy; + output TRACE_icache_req; + output [0:31]TRACE_instruction; + output TRACE_jump_hit; + output TRACE_jump_taken; + output TRACE_mb_halted; + output TRACE_mem_piperun; + output [0:14]TRACE_msr_reg; + output [0:31]TRACE_new_reg_value; + output TRACE_of_piperun; + output [0:31]TRACE_pc; + output [0:7]TRACE_pid_reg; + output [0:4]TRACE_reg_addr; + output TRACE_reg_write; + output TRACE_valid_instr; + + wire Clk; + wire IO_addr_strobe; + wire [31:0]IO_address; + wire [3:0]IO_byte_enable; + wire [31:0]IO_read_data; + wire IO_read_strobe; + wire IO_ready; + wire [31:0]IO_write_data; + wire IO_write_strobe; + wire Reset; + wire TRACE_data_access; + wire [0:31]TRACE_data_address; + wire [0:3]TRACE_data_byte_enable; + wire TRACE_data_read; + wire TRACE_data_write; + wire [0:31]TRACE_data_write_value; + wire TRACE_dcache_hit; + wire TRACE_dcache_rdy; + wire TRACE_dcache_read; + wire TRACE_dcache_req; + wire TRACE_delay_slot; + wire TRACE_ex_piperun; + wire [0:4]TRACE_exception_kind; + wire TRACE_exception_taken; + wire TRACE_icache_hit; + wire TRACE_icache_rdy; + wire TRACE_icache_req; + wire [0:31]TRACE_instruction; + wire TRACE_jump_hit; + wire TRACE_jump_taken; + wire TRACE_mb_halted; + wire TRACE_mem_piperun; + wire [0:14]TRACE_msr_reg; + wire [0:31]TRACE_new_reg_value; + wire TRACE_of_piperun; + wire [0:31]TRACE_pc; + wire [0:7]TRACE_pid_reg; + wire [0:4]TRACE_reg_addr; + wire TRACE_reg_write; + wire TRACE_valid_instr; + + bd_9d69 bd_9d69_i + (.Clk(Clk), + .IO_addr_strobe(IO_addr_strobe), + .IO_address(IO_address), + .IO_byte_enable(IO_byte_enable), + .IO_read_data(IO_read_data), + .IO_read_strobe(IO_read_strobe), + .IO_ready(IO_ready), + .IO_write_data(IO_write_data), + .IO_write_strobe(IO_write_strobe), + .Reset(Reset), + .TRACE_data_access(TRACE_data_access), + .TRACE_data_address(TRACE_data_address), + .TRACE_data_byte_enable(TRACE_data_byte_enable), + .TRACE_data_read(TRACE_data_read), + .TRACE_data_write(TRACE_data_write), + .TRACE_data_write_value(TRACE_data_write_value), + .TRACE_dcache_hit(TRACE_dcache_hit), + .TRACE_dcache_rdy(TRACE_dcache_rdy), + .TRACE_dcache_read(TRACE_dcache_read), + .TRACE_dcache_req(TRACE_dcache_req), + .TRACE_delay_slot(TRACE_delay_slot), + .TRACE_ex_piperun(TRACE_ex_piperun), + .TRACE_exception_kind(TRACE_exception_kind), + .TRACE_exception_taken(TRACE_exception_taken), + .TRACE_icache_hit(TRACE_icache_hit), + .TRACE_icache_rdy(TRACE_icache_rdy), + .TRACE_icache_req(TRACE_icache_req), + .TRACE_instruction(TRACE_instruction), + .TRACE_jump_hit(TRACE_jump_hit), + .TRACE_jump_taken(TRACE_jump_taken), + .TRACE_mb_halted(TRACE_mb_halted), + .TRACE_mem_piperun(TRACE_mem_piperun), + .TRACE_msr_reg(TRACE_msr_reg), + .TRACE_new_reg_value(TRACE_new_reg_value), + .TRACE_of_piperun(TRACE_of_piperun), + .TRACE_pc(TRACE_pc), + .TRACE_pid_reg(TRACE_pid_reg), + .TRACE_reg_addr(TRACE_reg_addr), + .TRACE_reg_write(TRACE_reg_write), + .TRACE_valid_instr(TRACE_valid_instr)); +endmodule diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xci new file mode 100644 index 0000000..0003d0d --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xci @@ -0,0 +1,955 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9d69_microblaze_I_0 + + + + 100000000 + 0.000 + + 30000000 + 0.000 + 1 + 32 + 0 + LEVEL_HIGH + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 100000000 + 0 + 0 + 0 + 0 + 0 + 100000000 + 1 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0.000 + 0 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0.000 + 0 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0.000 + 0 + 0 + 0 + 0 + 0 + LEVEL_HIGH + 0 + 0 + 0 + 100000000 + 0 + 0 + 0 + 0 + 0 + 100000000 + 1 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0.000 + 0 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0.000 + 0 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 17 + 1 + 1 + 0 + 1 + 3 + 0 + 0x0000000000000000 + 0 + 8192 + 32 + 17 + 0 + 0x0000000000000000 + 8192 + 0 + 0 + 0x000000003FFFFFFF + 4 + 0 + 0 + 32 + 0 + 5 + 0 + 0 + 1 + 0 + 0 + 8192 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + virtexuplus + 0 + 0 + 100000000 + 0 + 0 + 32 + 0 + 0x0000000000000000 + 0 + 0 + 0x000000003FFFFFFF + 4 + 0 + 0 + 0 + 0 + bd_9d69_microblaze_I_0 + 2 + 0 + 0 + 1 + 0 + 0 + 4 + 2 + 0 + 3 + 16 + 32 + 32 + 0 + 31 + 32 + 0 + 0 + 32 + 32 + 31 + 32 + 0 + 1 + 0 + 0 + 2 + 2 + 1 + 1 + 2 + 0 + 0 + 17 + 32 + 0 + 0x00 + 0x00000000 + 0x00000000 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 32 + 17 + 1 + 1 + 0 + 1 + 3 + 0 + 0x00000000 + 0 + 8192 + 32 + 17 + 0 + 0x0000000000000000 + 8192 + 0 + 0 + 0x000000003FFFFFFF + 4 + 0 + 0 + 0 + 32 + 0 + 5 + 0 + 0 + 1 + 0 + 0 + 8192 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 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xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 7 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xml new file mode 100644 index 0000000..e98e8b8 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_0/bd_9d69_microblaze_I_0.xml @@ -0,0 +1,26887 @@ + + + xilinx.com + customized_ip + bd_9d69_microblaze_I_0 + 1.0 + + + CLK.CLK + Clk + Clock input + + + + + + + CLK + + + Clk + + + + + + ASSOCIATED_BUSIF + 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choice_pairs_5b1842a1 + 0 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_75c71b2b + 0 + 1 + 2 + 3 + + + choice_pairs_7ad6afc0 + 0 + 1 + 2 + 3 + + + choice_pairs_7bfd418d + 0 + 1 + 2 + + + choice_pairs_7dd2834f + 0 + 8 + 9 + 10 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_8b498448 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + + + choice_pairs_b1fa18d9 + 0 + 1 + 2 + + + choice_pairs_c471ed24 + 32 + 36 + 40 + 44 + 48 + 52 + 64 + + + choice_pairs_db57ca32 + 0 + 1 + 2 + + + choice_pairs_e7a1eb81 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_pairs_ff364cce + 2 + 3 + + + + + microblaze + + + + endian + little + + + instance_path + + + + bootloop_file + data/mb_bootloop_le.elf + + + processor_type + MICROBLAZE_LE + + + is_visible + true + + + + + The MicroBlaze 32 bit soft processor core, providing an instruction set optimized for embedded applications with many user-configurable options. MicroBlaze has many advanced architecture features like Instruction and Data-side cache with AXI interfaces, Floating-Point unit (FPU), Memory Management Unit (MMU), and fault tolerance support. +It is highly recommended to create MicroBlaze systems within Vivado IP Integrator, to enable export to the Xilinx Software Development Kit (SDK) for software development. + + + + C_SCO + 0 + + + + true + + + + + + C_FREQ + 100000000 + + + + true + + + + + + C_DATA_SIZE + 32 + + + + true + + + + + + C_ADDR_SIZE + Select Extended Addressing + 32 + + + + true + + + + + + C_DYNAMIC_BUS_SIZING + 0 + + + + true + + + + + + C_PC_WIDTH + 17 + + + + true + + + + + + C_INSTANCE + mb_microblaze_0 + + + + true + + + + + + C_AVOID_PRIMITIVES + 0 + + + + true + + + + + + C_FAULT_TOLERANT + Enable Fault Tolerance Support + 0 + + + + true + + + + + + C_ECC_USE_CE_EXCEPTION + Correctable Error Exception + 0 + + + + true + + + + + + C_LOCKSTEP_SLAVE + Lockstep Slave + 0 + + + + true + + + + + + C_ENDIANNESS + Endianness + 1 + + + + true + + + + + + C_AREA_OPTIMIZED + Select implementation optimization + 0 + + + + true + + + + + + C_OPTIMIZATION + 0 + + + + true + + + + + + C_INTERCONNECT + Select Bus Interface + 2 + + + + true + + + + + + C_BASE_VECTORS + Vector Base Address + 0x00000000 + + + + true + + + + + + C_USE_CONFIG_RESET + 0 + + + + true + + + + + + C_NUM_SYNC_FF_CLK + Synchronizing FFs to Clk region + 2 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_IRQ + Synchronizing FFs to Clk region for interrupt input + 1 + + + + true + + + + + + C_NUM_SYNC_FF_CLK_DEBUG + Synchronizing FFs to Clk region in debug module + 2 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_CLK + Synchronizing FFs to Dbg_Clk region + 1 + + + + true + + + + + + C_NUM_SYNC_FF_DBG_TRACE_CLK + Synchronizing FFs to Dbg_Trace_Clk region + 2 + + + + true + + + + + + C_M_AXI_DP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DP_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_D_AXI + Enable Peripheral AXI Data Interface + 0 + + + + true + + + + + + C_DP_AXI_MON + Use Monitor Interface for Peripheral AXI Data Interface + 0 + + + + true + + + + + + C_DC_AXI_MON + Use Monitor Interface for Cache AXI Data Interface + 0 + + + + true + + + + + + C_D_LMB + Enable Local Memory Bus Data Interface + 1 + + + + true + + + + + + C_D_LMB_MON + Use Monitor Interface for Local Memory Bus Data Interface + 0 + + + + true + + + + + + C_M_AXI_IP_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IP_DATA_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IP_ADDR_WIDTH + 32 + + + + true + + + + + + C_I_AXI + Enable Peripheral AXI Instruction Interface + 0 + + + + true + + + + + + C_IP_AXI_MON + Use Monitor Interface for Peripheral AXI Instruction Interface + 0 + + + + true + + + + + + C_IC_AXI_MON + Use Monitor Interface for Cache AXI Instruction Interface + 0 + + + + true + + + + + + C_I_LMB + Enable Local Memory Bus Instruction Interface + 1 + + + + true + + + + + + C_I_LMB_MON + Use Monitor Interface for Local Memory Bus Instruction Interface + 0 + + + + true + + + + + + C_TRACE + Enable Trace Bus Interface + 1 + + + + true + + + + + + C_LOCKSTEP_SELECT + Lockstep Interface + 0 + + + + true + + + + + + C_ENABLE_DISCRETE_PORTS + Enable Discrete Ports + 0 + + + + true + + + + + + C_M_AXI_DC_USER_SIGNALS + Enable M_AXI_DC User Signals + 0 + + + + true + + + + + + C_M_AXI_IC_USER_SIGNALS + Enable M_AXI_IC User Signals + 0 + + + + true + + + + + + G_TEMPLATE_LIST + Select Configuration + 0 + + + + true + + + + + + G_USE_EXCEPTIONS + Enable Exceptions + 0 + + + + true + + + + + + C_USE_MSR_INSTR + Enable Additional Machine Status Register Instructions + 0 + + + + true + + + + + + C_USE_PCMP_INSTR + Enable Pattern Comparator + 1 + + + + true + + + + + + C_USE_REORDER_INSTR + Enable Reversed Load/Store and Swap Instructions + 0 + + + + true + + + + + + C_USE_BARREL + Enable Barrel Shifter + 1 + + + + true + + + + + + C_USE_DIV + Enable Integer Divider + 1 + + + + true + + + + + + C_USE_HW_MUL + Enable Integer Multiplier + 1 + + + + true + + + + + + C_USE_FPU + Enable Floating Point Unit + 0 + + + + true + + + + + + C_UNALIGNED_EXCEPTIONS + Enable Unaligned Data Exception + 0 + + + + true + + + + + + C_ILL_OPCODE_EXCEPTION + Enable Illegal Instruction Exception + 0 + + + + true + + + + + + C_M_AXI_I_BUS_EXCEPTION + Enable Instruction-side AXI Exception + 0 + + + + false + + + + + + C_M_AXI_D_BUS_EXCEPTION + Enable Data-side AXI Exception + 0 + + + + false + + + + + + C_DIV_ZERO_EXCEPTION + Enable Integer Divide Exception + 0 + + + + true + + + + + + C_FPU_EXCEPTION + Enable Floating Point Unit Exceptions + 0 + + + + false + + + + + + C_FSL_EXCEPTION + Enable Stream Exception + 0 + + + + false + + + + + + C_USE_STACK_PROTECTION + Enable stack protection + 0 + + + + true + + + + + + C_IMPRECISE_EXCEPTIONS + Allow Imprecise Exceptions + 0 + + + + true + + + + + + C_PVR + Specifies Processor Version Register + 0 + + + + true + + + + + + C_PVR_USER1 + Specify USER1 Bits in Processor Version Register + 0x00 + + + + false + + + + + + C_PVR_USER2 + Specify USER2 Bits in Processor Version Register + 0x00000000 + + + + false + + + + + + C_DEBUG_ENABLED + MicroBlaze Debug Module Interface + 0 + + + + true + + + + + + C_DEBUG_INTERFACE + MicroBlaze Debug Connection + 0 + + + + true + + + + + + C_NUMBER_OF_PC_BRK + Number of PC Breakpoints + 1 + + + + false + + + + + + C_NUMBER_OF_RD_ADDR_BRK + Number of Read Address Watchpoints + 0 + + + + false + + + + + + C_NUMBER_OF_WR_ADDR_BRK + Number of Write Address Watchpoints + 0 + + + + false + + + + + + C_DEBUG_EVENT_COUNTERS + Number of Performance Monitor Event Counters + 5 + + + + false + + + + + + C_DEBUG_LATENCY_COUNTERS + Number of Performance Monitor Latency Counters + 1 + + + + false + + + + + + C_DEBUG_COUNTER_WIDTH + Performance Monitor Counter Width + 32 + + + + false + + + + + + C_DEBUG_TRACE_SIZE + Trace Buffer Size + 8192 + + + + false + + + + + + C_DEBUG_EXTERNAL_TRACE + External Trace + 0 + + + + false + + + + + + C_DEBUG_TRACE_ASYNC_RESET + Use Asynchrnous Reset for External Trace + 0 + + + + true + + + + + + C_DEBUG_PROFILE_SIZE + Profile Buffer Size + 0 + + + + false + + + + + + C_INTERRUPT_IS_EDGE + Sense Interrupt on Edge vs. Level + 0 + + + + true + + + + + + C_EDGE_IS_POSITIVE + Sense Interrupt on Rising vs. Falling Edge + 1 + + + + true + + + + + + C_ASYNC_INTERRUPT + 1 + + + + true + + + + + + C_ASYNC_WAKEUP + 3 + + + + true + + + + + + C_RESET_MSR_IE + IE + 0 + + + + true + + + + + + C_RESET_MSR_BIP + BIP + 0 + + + + true + + + + + + C_RESET_MSR_ICE + ICE + 0 + + + + true + + + + + + C_RESET_MSR_DCE + DCE + 0 + + + + true + + + + + + C_RESET_MSR_EE + EE + 0 + + + + true + + + + + + C_RESET_MSR_EIP + EIP + 0 + + + + true + + + + + + C_OPCODE_0x0_ILLEGAL + Generate Illegal Instruction Exception for NULL Instruction + 0 + + + + false + + + + + + C_FSL_LINKS + Number of Stream Links + 0 + + + + true + + + + + + C_USE_EXTENDED_FSL_INSTR + Enable Additional Stream Instructions + 0 + + + + false + + + + + + C_M0_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S0_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M1_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S1_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M2_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S2_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M3_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S3_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M4_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S4_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M5_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S5_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M6_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S6_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_M7_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + C_S7_AXIS_PROTOCOL + GENERIC + + + + true + + + + + + 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C_M11_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S11_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M12_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S12_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M13_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S13_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M14_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S14_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_M15_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_S15_AXIS_DATA_WIDTH + 32 + + + + true + + + + + + C_ICACHE_BASEADDR + Base Address + 0x0000000000000000 + + + + false + + + + + + C_ICACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + + false + + + + + + C_USE_ICACHE + Enable Instruction Cache + 0 + + + + true + + + + + + C_ALLOW_ICACHE_WR + Enable Writes + 1 + + + + false + + + + + + C_ADDR_TAG_BITS + Set number of I-cache address tag bits + 17 + + + + true + + + + + + C_CACHE_BYTE_SIZE + Size in Bytes + 8192 + + + + false + + + + + + C_ICACHE_LINE_LEN + Line Length + 4 + + + + false + + + + + + C_ICACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 0 + + + + false + + + + + + C_ICACHE_VICTIMS + Number of Victims + 0 + + + + false + + + + + + C_ICACHE_STREAMS + Number of Streams + 0 + + + + false + + + + + + C_ICACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + + false + + + + + + C_ICACHE_DATA_WIDTH + Data Width + 0 + + + + false + + + + + + C_M_AXI_IC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_IC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_IC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_BUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_IC_USER_VALUE + 31 + + + + true + + + + + + C_DCACHE_BASEADDR + Base Address + 0x0000000000000000 + + + + false + + + + + + C_DCACHE_HIGHADDR + High Address + 0x000000003FFFFFFF + + + + false + + + + + + C_USE_DCACHE + Enable Data Cache + 0 + + + + true + + + + + + C_ALLOW_DCACHE_WR + Enable Writes + 1 + + + + false + + + + + + C_DCACHE_ADDR_TAG + Set number of D-cache address tag bits + 17 + + + + true + + + + + + C_DCACHE_BYTE_SIZE + Size in Bytes + 8192 + + + + false + + + + + + C_DCACHE_LINE_LEN + Line Length + 4 + + + + false + + + + + + C_DCACHE_ALWAYS_USED + Use Cache for All Memory Accesses + 0 + + + + false + + + + + + C_DCACHE_USE_WRITEBACK + Enable Write-back Storage Policy + 0 + + + + false + + + + + + C_DCACHE_VICTIMS + Number of Victims + 0 + + + + false + + + + + + C_DCACHE_FORCE_TAG_LUTRAM + Use Distributed RAM for Tags + 0 + + + + false + + + + + + C_DCACHE_DATA_WIDTH + Data Width + 0 + + + + false + + + + + + C_M_AXI_DC_THREAD_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_ADDR_WIDTH + 32 + + + + true + + + + + + C_M_AXI_DC_AWUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_ARUSER_WIDTH + 5 + + + + true + + + + + + C_M_AXI_DC_WUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_RUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_BUSER_WIDTH + 1 + + + + true + + + + + + C_M_AXI_DC_EXCLUSIVE_ACCESS + 0 + + + + true + + + + + + C_M_AXI_DC_USER_VALUE + 31 + + + + true + + + + + + C_USE_MMU + Memory Management + 0 + + + + true + + + + + + C_MMU_DTLB_SIZE + Data Shadow Translation Look-Aside Buffer Size + 4 + + + + false + + + + + + C_MMU_ITLB_SIZE + Instruction Shadow Translation Look-Aside Buffer Size + 2 + + + + false + + + + + + C_MMU_TLB_ACCESS + Enable Access to Memory Management Special Registers + 3 + + + + false + + + + + + C_MMU_ZONES + Number of Memory Protection Zones + 16 + + + + false + + + + + + C_MMU_PRIVILEGED_INSTR + Privileged Instructions + 0 + + + + false + + + + + + C_USE_INTERRUPT + Use Interrupt + 0 + + + + true + + + + + + C_INTERRUPT_MON + Use Monitor Interface for Interrupt + 0 + + + + true + + + + + + C_USE_EXT_BRK + Use Ext_Brk + 0 + + + + true + + + + + + C_USE_EXT_NM_BRK + Use Ext_Nm_Brk + 0 + + + + true + + + + + + C_USE_NON_SECURE + Use Non-Secure AXI access permission + 0 + + + + true + + + + + + C_USE_BRANCH_TARGET_CACHE + Enable Branch Target Cache + 0 + + + + true + + + + + + C_BRANCH_TARGET_CACHE_SIZE + Branch Target Cache Size + 0 + + + + true + + + + + + Component_Name + bd_9d69_microblaze_I_0 + + + + + MicroBlaze + + XPM_MEMORY + + 7 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xci new file mode 100644 index 0000000..ebb842d --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xci @@ -0,0 +1,71 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9d69_rst_0_0 + + + ACTIVE_LOW + + + 100000000 + 0.000 + ACTIVE_HIGH + 0 + 4 + 1 + 4 + virtexuplus + 1 + 1 + 1 + 1 + 0 + 4 + 1 + 4 + 1 + 1 + 1 + 1 + bd_9d69_rst_0_0 + Custom + false + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 12 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xml new file mode 100644 index 0000000..f5c2ce0 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_1/bd_9d69_rst_0_0.xml @@ -0,0 +1,583 @@ + + + xilinx.com + customized_ip + bd_9d69_rst_0_0 + 1.0 + + + clock + Clock + + + + + + + CLK + + + slowest_sync_clk + + + + + + ASSOCIATED_RESET + mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset + + + FREQ_HZ + Slowest Sync clock frequency + Slowest Synchronous clock frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + + + ext_reset + Ext_Reset + + + + + + + RST + + + ext_reset_in + + + + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + + required + + + + + + POLARITY + ACTIVE_HIGH + + + none + + + + + + + aux_reset + aux_reset + + + + + + + RST + + + aux_reset_in + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + + + dbg_reset + DBG_Reset + + + + + + + RST + + + mb_debug_sys_rst + + + + + + POLARITY + ACTIVE_HIGH + + + + + mb_rst + MB_rst + + + + + + + RST + + + mb_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PROCESSOR + + + + + bus_struct_reset + bus_struct_reset + + + + + + + RST + + + bus_struct_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + interconnect_low_rst + interconnect_low_rst + + + + + + + RST + + + interconnect_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + INTERCONNECT + + + + + peripheral_high_rst + peripheral_high_rst + + + + + + + RST + + + peripheral_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + + + peripheral_low_rst + peripheral_low_rst + + + + + + + RST + + + peripheral_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + PERIPHERAL + + + + + + + + slowest_sync_clk + + in + + + std_logic + dummy_view + + + + + + ext_reset_in + + in + + + std_logic + dummy_view + + + + + + aux_reset_in + + in + + + std_logic + dummy_view + + + + 1 + + + + + mb_debug_sys_rst + + in + + + std_logic + dummy_view + + + + 0 + + + + + dcm_locked + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + mb_reset + + out + + + std_logic + dummy_view + + + + 0x0 + + + + + bus_struct_reset + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + peripheral_reset + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + interconnect_aresetn + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 1 + + + + + peripheral_aresetn + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 1 + + + + + + + C_FAMILY + virtexuplus + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RESET_HIGH + Ext Reset High + 1 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + + + + choice_list_ac75ef1e + Custom + + + Processor Reset System + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_EXT_RESET_HIGH + Ext Reset High + 1 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + Component_Name + bd_9d69_rst_0_0 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + RESET_BOARD_INTERFACE + Custom + + + + + Processor System Reset + 12 + + + + + + + + + + 2018.2 + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xci new file mode 100644 index 0000000..ff7bd1d --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xci @@ -0,0 +1,272 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9d69_iomodule_0_0 + + + + 100000000 + 0.000 + 1 + LEVEL_HIGH + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 32 + 32 + READ_WRITE + 0 + 0x0000000080000000 + virtexuplus + 0 + 6216 + 0 + 6216 + 0 + 6216 + 0 + 6216 + 100000000 + 0 + 32 + 0 + 32 + 0 + 32 + 0 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x000000008000FFFF + iomodule + 17 + 0xFFFF + 0x00000000 + 1 + 1 + 0x0000 + 2 + 0xFFFF + 0 + 0x00000000C0000000 + 0x00000000FFFFFFFF + 0x00000000C0000000 + 32 + 32 + 0x00000000C0000000 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 9600 + 8 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0x0000000080000000 + 0 + 6216 + 0 + 6216 + 0 + 6216 + 0 + 6216 + 100000000 + 0 + 32 + 0 + 32 + 0 + 32 + 0 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x00000000 + 32 + 0x000000008000FFFF + iomodule + 17 + 0xFFFF + 0x00000000 + 1 + 1 + 0 + 0x0000 + 2 + 0xFFFF + 0 + 1 + 0x00000000C0000000 + 0x00000000FFFFFFFF + 0x00000000C0000000 + 32 + 32 + 0x00000000C0000000 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 0 + 1 + 32 + 0 + 9600 + 8 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + bd_9d69_iomodule_0_0 + Custom + Custom + Custom + Custom + Custom + false + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 3 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xml new file mode 100644 index 0000000..cf84d43 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_10/bd_9d69_iomodule_0_0.xml @@ -0,0 +1,7497 @@ + + + xilinx.com + customized_ip + bd_9d69_iomodule_0_0 + 1.0 + + + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + CLK.CLK + Clk + Clock Input + + + + + + + CLK + + + Clk + + + + + + ASSOCIATED_BUSIF + SLMB + + + ASSOCIATED_RESET + Rst:TMR_Rst + + + FREQ_HZ + Clk frequency + Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.Rst + Rst + Reset Input + + + + + + + RST + + + Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + + + RST.TMR_Rst + TMR_Rst + TMR Reset Input + + + + + + + RST + + + TMR_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + + + IO_BUS + IO_BUS + MicroBlaze MCS IO Bus Interface + + + + + + + ADDR_STROBE + + + IO_Addr_Strobe + + + + + ADDRESS + + + IO_Address + + + + + BYTE_ENABLE + + + IO_Byte_Enable + + + + + READ_DATA + + + IO_Read_Data + + + + + READ_STROBE + + + IO_Read_Strobe + + + + + READY + + + IO_Ready + + + + + WRITE_DATA + + + IO_Write_Data + + + + + WRITE_STROBE + + + IO_Write_Strobe + + + + + + + true + + + + + + INTERRUPT.UART_Interrupt + UART_Interrupt + + + + + + + INTERRUPT + + + UART_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT1_Interrupt + FIT1_Interrupt + + + + + + + INTERRUPT + + + FIT1_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT2_Interrupt + FIT2_Interrupt + + + + + + + INTERRUPT + + + FIT2_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT3_Interrupt + FIT3_Interrupt + + + + + + + INTERRUPT + + + FIT3_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + INTERRUPT.FIT4_Interrupt + FIT4_Interrupt + + + + + + + INTERRUPT + + + FIT4_Interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + 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C_USE_GPO4 + 0 + + + + true + + + + + + C_GPO4_SIZE + 32 + + + + true + + + + + + C_GPO4_INIT + 0x00000000 + + + + true + + + + + + C_USE_GPI4 + 0 + + + + true + + + + + + C_GPI4_SIZE + 32 + + + + true + + + + + + C_GPI4_INTERRUPT + 0 + + + + true + + + + + + BOARD.ASSOCIATED_PARAM + GPIO4_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + + + SLMB + LMB memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + UART RX + UART Receive Data Register + UART Receive Data Register + 0x0 + 8 + true + read-only + + 0x0 + + + UART RX + Receive Data + Data received by the UART. + 0 + 8 + true + read-only + + 0 + 0 + + modify + false + + + + + false + + + + + + UART TX + UART Transmit Data Register + UART Transmit Data Register + 0x4 + 8 + true + write-only + + 0x0 + + + UART TX + Transmit Data + Data to be transmitted by the UART. + 0 + 8 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART Status + UART Status Register + UART Status Register + 0x8 + 8 + true + read-only + + 0x0 + + + Rx Valid Data + Rx Valid Data + Indicates if the receive register has valid data: + 0 - Receive register is empty. + 1 - Receive register has valid data. + + 0 + 1 + true + read-only + + 0 + 0 + + false + + + Tx Used + Tx Used + Indicates if the transmit register is in use: + 0 - Transmit register is not in use. + 1 - Transmit register is in use. + + 3 + 1 + true + read-only + + 0 + 0 + + false + + + Overrun Error + Overrun Error + Indicates that an overrun error has occurred: + 0 - No overrun has occurred. + 1 - An overrun has occurred. + + 5 + 1 + true + read-only + + 0 + 0 + + false + + + Frame Error + Frame Error + Indicates that an frame error has occurred: + 0 - No frame error has occurred. + 1 - A frame error has occurred. + + 6 + 1 + true + read-only + + 0 + 0 + + false + + + Parity Error + Parity Error + Indicates that a parity error has occurred: + 0 - No parity error has occurred. + 1 - A parity error occurred. + + 7 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ MODE + Interrupt Mode Register + Interrupt Mode Register + 0xC + 17 + true + write-only + + 0x0 + + + IRQ Mode + IRQ Mode + Interrupt Mode. +For each bit: + W - When written with 1 the corresponding interrupt will use fast mode. + + 0 + 17 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + GPO 1 + General Purpose Output 1 Register + General Purpose Output 1 Register + 0x10 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 2 + General Purpose Output 2 Register + General Purpose Output 2 Register + 0x14 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 3 + General Purpose Output 3 Register + General Purpose Output 3 Register + 0x18 + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPO 4 + General Purpose Output 4 Register + General Purpose Output 4 Register + 0x1C + 32 + true + write-only + + 0 + + + GPO + General Purpose Output + General Purpose Output. +For each bit: + W - Writes general purpose output value. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 1 + General Purpose Input 1 Register + General Purpose Input 1 Register + 0x20 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 2 + General Purpose Input 2 Register + General Purpose Input 2 Register + 0x24 + 32 + true + read-only + + 0 + + + CPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 3 + General Purpose Input 3 Register + General Purpose Input 3 Register + 0x28 + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + GPI 4 + General Purpose Input 4 Register + General Purpose Input 4 Register + 0x2C + 32 + true + read-only + + 0 + + + GPI + General Purpose Input + General Purpose Input. +For each bit: + R - Reads general purpose input value. + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ STATUS + Interrupt Status Register + Interrupt Status Register + 0x30 + 17 + true + read-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC Interrupt + External interrupt input signal + Interrupt Status Register. +For each bit: + R - Reads active interrupt signal. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ PENDING + Interrupt Pending Register + Interrupt Pending Register + 0x34 + 17 + true + read-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt. + 0 + 1 + true + read-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt. + 1 + 1 + true + read-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt. + 2 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 lapsed. + 3 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 lapsed. + 4 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 lapsed. + 5 + 1 + true + read-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 lapsed. + 6 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 strobe. + 7 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 strobe. + 8 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 strobe. + 9 + 1 + true + read-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 strobe. + 10 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 changed. + 11 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 changed. + 12 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 changed. + 13 + 1 + true + read-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 changed. + 14 + 1 + true + read-only + + 0 + 0 + + false + + + INTC Interrupt + Enabled interrupt events that have occurred + Interrupt Pending. +For each bit: + R - Reads enabled interrupt event that has occurred. + + 16 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ ENABLE + Interrupt Enable Register + Interrupt Enable Register + 0x38 + 17 + true + write-only + + 0x0 + + + UART ERR + UART Error + UART Error interrupt enabled. + 0 + 1 + true + write-only + + 0 + 0 + + false + + + UART TX + UART Transmitted Data + UART Transmitted Data interrupt enabled. + 1 + 1 + true + write-only + + 0 + 0 + + false + + + UART RX + UART Received Data + UART Received Data interrupt enabled. + 2 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 1 + PIT 1 + PIT 1 interrupt enabled. + 3 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 2 + PIT 2 + PIT 2 interrupt enabled. + 4 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 3 + PIT 3 + PIT 3 interrupt enabled. + 5 + 1 + true + write-only + + 0 + 0 + + false + + + PIT 4 + PIT 4 + PIT 4 interrupt enabled. + 6 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 1 + FIT 1 + FIT 1 interrupt enabled. + 7 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 2 + FIT 2 + FIT 2 interrupt enabled. + 8 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 3 + FIT 3 + FIT 3 interrupt enabled. + 9 + 1 + true + write-only + + 0 + 0 + + false + + + FIT 4 + FIT 4 + FIT 4 interrupt enabled. + 10 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 1 + GPI 1 + GPI 1 interrupt enabled. + 11 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 2 + GPI 2 + GPI 2 interrupt enabled. + 12 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 3 + GPI 3 + GPI 3 interrupt enabled. + 13 + 1 + true + write-only + + 0 + 0 + + false + + + GPI 4 + GPI 4 + GPI 4 interrupt enabled. + 14 + 1 + true + write-only + + 0 + 0 + + false + + + INTC Interrupt + Enable external interrupt input signals + Interrupt Enable. +For each bit: + W - Enable external interrupt input signal. + + 16 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ ACK + Interrupt Acknowledge Register + Interrupt Acknowledge Register + 0x3C + 17 + true + write-only + + 0x0 + + + IRQ Acknowledge + IRQ Acknowledge + Interrupt Acknowledge. +For each bit: + W - When written with 1 clear bit in IRQ_STATUS and IRQ_PENDING. + + 0 + 17 + true + write-only + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + PIT1 PRELOAD + PIT 1 Preload Register + PIT 1 Preload Register + 0x40 + 32 + true + write-only + + 0x0 + + + PIT1 Preload + PIT1 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1 COUNTER + PIT 1 Counter Register + PIT 1 Counter Register + 0x44 + 32 + true + read-only + + 0x0 + + + PIT1 Counter + PIT1 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT1 CONTROL + PIT 1 Control Register + PIT 1 Control Register + 0x48 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT1_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + UART BAUD + UART Programmable Baud Rate + UART Programmable Baud Rate + 0x4C + 8 + true + write-only + + 0x0 + + + UART BAUD + Baud Rate + Programmable UART Baud Rate. + 0 + 20 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 PRELOAD + PIT 2 Preload Register + PIT 2 Preload Register + 0x50 + 32 + true + write-only + + 0x0 + + + PIT2 Preload + PIT2 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 COUNTER + PIT 2 Counter Register + PIT 2 Counter Register + 0x54 + 32 + true + read-only + + 0x0 + + + PIT2 Counter + PIT2 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT2 CONTROL + PIT 2 Control Register + PIT 2 Control Register + 0x58 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT2_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 PRELOAD + PIT 3 Preload Register + PIT 3 Preload Register + 0x60 + 32 + true + write-only + + 0x0 + + + PIT3 Preload + PIT3 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 COUNTER + PIT 3 Counter Register + PIT 3 Counter Register + 0x64 + 32 + true + read-only + + 0x0 + + + PIT3 Counter + PIT3 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT3 CONTROL + PIT 3 Control Register + PIT 3 Control Register + 0x68 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT3_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 PRELOAD + PIT 4 Preload Register + PIT 4 Preload Register + 0x70 + 32 + true + write-only + + 0x0 + + + PIT4 Preload + PIT4 Preload + Determines the initial value of the counter and the timer period. +The period is the value + 2. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 COUNTER + PIT 4 Counter Register + PIT 4 Counter Register + 0x74 + 32 + true + read-only + + 0x0 + + + PIT4 Counter + PIT4 Counter + Samples the current counter value. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + PIT4 CONTROL + PIT 4 Control Register + PIT 4 Control Register + 0x78 + 2 + true + write-only + + 0x0 + + + EN + Enable + Count Enable: + 0 - Counting Disabled. + 1 - Counting Enabled. + + 0 + 1 + true + write-only + + 0 + 0 + + false + + + PRELOAD + Preload + Counter preload: + 0 - Counter counts past zero and then stops. + 1 - Counter automatically reloaded with PIT4_PRELOAD. + + 1 + 1 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 0 + Interrupt Vector Register 0 + Interrupt Vector Register 0 + 0x80 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 0 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 1 + Interrupt Vector Register 1 + Interrupt Vector Register 1 + 0x84 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 1 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 2 + Interrupt Vector Register 2 + Interrupt Vector Register 2 + 0x88 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 2 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 3 + Interrupt Vector Register 3 + Interrupt Vector Register 3 + 0x8C + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 3 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 4 + Interrupt Vector Register 4 + Interrupt Vector Register 4 + 0x90 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 4 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 5 + Interrupt Vector Register 5 + Interrupt Vector Register 5 + 0x94 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 5 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 6 + Interrupt Vector Register 6 + Interrupt Vector Register 6 + 0x98 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 6 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 7 + Interrupt Vector Register 7 + Interrupt Vector Register 7 + 0x9C + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 7 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 8 + Interrupt Vector Register 8 + Interrupt Vector Register 8 + 0xA0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 8 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 9 + Interrupt Vector Register 9 + Interrupt Vector Register 9 + 0xA4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 9 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 10 + Interrupt Vector Register 10 + Interrupt Vector Register 10 + 0xA8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 10 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 11 + Interrupt Vector Register 11 + Interrupt Vector Register 11 + 0xAC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 11 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 12 + Interrupt Vector Register 12 + Interrupt Vector Register 12 + 0xB0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 12 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 13 + Interrupt Vector Register 13 + Interrupt Vector Register 13 + 0xB4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 13 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 14 + Interrupt Vector Register 14 + Interrupt Vector Register 14 + 0xB8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 14 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 16 + Interrupt Vector Register 16 + Interrupt Vector Register 16 + 0xC0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 16 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + IRQ VECTOR 17 + Interrupt Vector Register 17 + Interrupt Vector Register 17 + 0xC4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 17 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 18 + Interrupt Vector Register 18 + Interrupt Vector Register 18 + 0xC8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 18 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 19 + Interrupt Vector Register 19 + Interrupt Vector Register 19 + 0xCC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 19 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 20 + Interrupt Vector Register 20 + Interrupt Vector Register 20 + 0xD0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 20 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 21 + Interrupt Vector Register 21 + Interrupt Vector Register 21 + 0xD4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 21 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 22 + Interrupt Vector Register 22 + Interrupt Vector Register 22 + 0xD8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 22 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 23 + Interrupt Vector Register 23 + Interrupt Vector Register 23 + 0xDC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 23 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 24 + Interrupt Vector Register 24 + Interrupt Vector Register 24 + 0xE0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 24 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 25 + Interrupt Vector Register 25 + Interrupt Vector Register 25 + 0xE4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 25 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 26 + Interrupt Vector Register 26 + Interrupt Vector Register 26 + 0xE8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 26 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 27 + Interrupt Vector Register 27 + Interrupt Vector Register 27 + 0xEC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 27 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 28 + Interrupt Vector Register 28 + Interrupt Vector Register 28 + 0xF0 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 28 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 29 + Interrupt Vector Register 29 + Interrupt Vector Register 29 + 0xF4 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 29 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 30 + Interrupt Vector Register 30 + Interrupt Vector Register 30 + 0xF8 + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 30 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + IRQ VECTOR 31 + Interrupt Vector Register 31 + Interrupt Vector Register 31 + 0xFC + 1 + true + write-only + + 0x0 + + + IRQ Vector + Interrupt Vector Address + Interrupt vector address of active interrupt 31 with highest priority. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + false + + + + + + + IO + 0 + 65536 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_IO_BASEADDR + + + OFFSET_HIGH_PARAM + C_IO_HIGHADDR + + + + + + true + + + + + + + + + + Clk + + in + + + std_logic + dummy_view + + + + + + Rst + + in + + + std_logic + dummy_view + + + + + + Config_Reset + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + TMR_Rst + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + TMR_Disable + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + ToVote + + out + + 1023 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + FromAVote + + in + + 1023 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + FromBVote + + in + + 1023 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + IO_Addr_Strobe + + out + + + std_logic + dummy_view + + + + + + + true + + + + + + IO_Read_Strobe + + out + + + std_logic + dummy_view + + + + + + + true + + + + + + IO_Write_Strobe + + out + + + std_logic + dummy_view + + + + + + + true + + + + + + IO_Address + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + true + + + + + + IO_Byte_Enable + + out + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + + + + true + + + + + + IO_Write_Data + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + true + + + + + + IO_Read_Data + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + true + + + + + + IO_Ready + + in + + + std_logic + dummy_view + + + + 0 + + + + + + true + + + + + + UART_Rx + Serial Data In + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + UART_Tx + Serial Data Out + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + UART_Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + FIT1_Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + FIT1_Toggle + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + FIT2_Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + FIT2_Toggle + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + FIT3_Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + FIT3_Toggle + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + FIT4_Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + FIT4_Toggle + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + PIT1_Enable + + in + + + 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READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + LMB_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + Sl_Ready + + out + + + std_logic + dummy_view + + + + + + Sl_Wait + + out + + + std_logic + dummy_view + + + + + + Sl_UE + + out + + + std_logic + dummy_view + + + + + + Sl_CE + + out + + + std_logic + dummy_view + + + + + + LMB1_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + Sl1_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + Sl1_Ready + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_Wait + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl1_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + LMB2_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB2_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + Sl2_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + Sl2_Ready + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_Wait + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Sl2_CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + LMB3_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + LMB3_ReadStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + 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std_logic_vector + dummy_view + + + + + + BRAM_Din_A + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + S_AXI_CTRL_ACLK + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARESETN + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_AWREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_WDATA + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_WREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_BREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARADDR + + in + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARVALID + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + S_AXI_CTRL_ARREADY + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RDATA + + out + + 31 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RRESP + + out + + 1 + 0 + + + + std_logic_vector + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RVALID + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + S_AXI_CTRL_RREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + + + C_FAMILY + virtexuplus + + + C_HIGHADDR + LMB BRAM High Address + 0x000000000000FFFF + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000000000 + + + C_NUM_LMB + Number of LMB Ports + 1 + + + C_MASK + SLMB Address Decode Mask + 0x00000000C0010000 + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + C_ECC + Error Correction Code + 0 + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_BRAM_AWIDTH + BRAM Address Bus Width + 32 + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + false + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + false + + + + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_449ac0d2 + 0 + 1 + 2 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_8d6e70ff + 0 + 2 + + + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000000000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x000000000000FFFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x00000000C0010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_9d69_dlmb_cntlr_0 + + + + + LMB BRAM Controller + 15 + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xci new file mode 100644 index 0000000..28a22df --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9d69_ilmb_cntlr_0 + + + NONE + 65536 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000000000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000000000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x000000000000FFFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_9d69_ilmb_cntlr_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 15 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xml new file mode 100644 index 0000000..9cb924d --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_5/bd_9d69_ilmb_cntlr_0.xml @@ -0,0 +1,3874 @@ + + + xilinx.com + customized_ip + bd_9d69_ilmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB3_ABus + + + + + ADDRSTROBE + + + LMB3_AddrStrobe + + + + + BE + + + LMB3_BE + + + + + CE + + + Sl3_CE + + + + + READDBUS + + + Sl3_DBus + + + + + READSTROBE + + + LMB3_ReadStrobe + + + + + READY + + + Sl3_Ready + + + + + UE + + + Sl3_UE + + + + + WAIT + + + Sl3_Wait + + + + + WRITEDBUS + + + LMB3_WriteDBus + + + + + WRITESTROBE + + + LMB3_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + BRAM_PORT + BRAM_PORT + Data Processor Local Bus + + + + + + + ADDR + + + BRAM_Addr_A + + + + + CLK + + + BRAM_Clk_A + + + + + DIN + + + BRAM_Dout_A + + + + + DOUT + + + BRAM_Din_A + + + + + EN + + + BRAM_EN_A + + + + + RST + + + BRAM_Rst_A + + + + + WE + + + BRAM_WEN_A + + + + + + MEM_SIZE + 65536 + + + MASTER_TYPE + BRAM_CTRL + + + MEM_WIDTH + 32 + + + none + + + + + MEM_ECC + NONE + + + none + + + + + READ_WRITE_MODE + + + + none + + + + + + + S_AXI_CTRL + S_AXI_CTRL + Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + 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choice_pairs_246d8066 + WRITE_FIRST + READ_FIRST + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_a6697bba + Single_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + bd_9d69_lmb_bram_I_0 + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + True_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + true + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false 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READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + CLK.LMB_Clk + LMB_Clk + Clock Input + + + + + + + CLK + + + LMB_Clk + + + + + + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_Rst + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + LMB_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + LMB_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + LMB_AddrStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_ReadStrobe + + in + + + std_logic + dummy_view + + + + + + LMB_WriteStrobe + + in + + + std_logic + dummy_view + + + + 0 + + + + + LMB_BE + + in + + 0 + 3 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + Sl_DBus + + out + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + + + Sl_Ready + + out + + + std_logic + dummy_view + + + + + + Sl_Wait + + out + + + std_logic + dummy_view + + + + + + Sl_UE + + out + + + std_logic + dummy_view + + + + + + Sl_CE + + out + + + std_logic + dummy_view + + + + + + LMB1_ABus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_WriteDBus + + in + + 0 + 31 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + false + + + + + + LMB1_AddrStrobe + + in + + + std_logic + dummy_view + + + + 0 + + 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S_AXI_CTRL_RREADY + + in + + + std_logic + dummy_view + + + + 0 + + + + + + false + + + + + + UE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + CE + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + Interrupt + + out + + + std_logic + dummy_view + + + + + + + false + + + + + + + + C_FAMILY + virtexuplus + + + C_HIGHADDR + LMB BRAM High Address + 0x0000000000017FFF + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000010000 + + + C_NUM_LMB + Number of LMB Ports + 1 + + + C_MASK + SLMB Address Decode Mask + 0x00000000C0010000 + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + C_ECC + Error Correction Code + 0 + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_BRAM_AWIDTH + BRAM Address Bus Width + 32 + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + false + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + false + + + + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_449ac0d2 + 0 + 1 + 2 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_8d6e70ff + 0 + 2 + + + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + C_BASEADDR + LMB BRAM Base Address + 0x0000000000010000 + + + + true + + + + + + C_HIGHADDR + LMB BRAM High Address + 0x0000000000017FFF + + + + true + + + + + + C_MASK + SLMB Address Decode Mask + 0x00000000C0010000 + + + + true + + + + + + C_MASK1 + SLMB1 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK2 + SLMB2 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_MASK3 + SLMB3 Address Decode Mask + 0x0000000000800000 + + + + false + + + + + + C_NUM_LMB + Number of LMB Ports + 1 + + + + true + + + + + + C_LMB_AWIDTH + LMB Address Bus Width + 32 + + + + true + + + + + + C_LMB_DWIDTH + LMB Data Bus Width + 32 + + + + true + + + + + + C_ECC + Error Correction Code + 0 + + + + true + + + + + + C_INTERCONNECT + Select Interconnect + 0 + + + + false + + + + + + C_FAULT_INJECT + Fault Inject Registers + 0 + + + + false + + + + + + C_CE_FAILING_REGISTERS + Correctable Error First Failing Register + 0 + + + + false + + + + + + C_UE_FAILING_REGISTERS + Uncorrectable Error First Failing Register + 0 + + + + false + + + + + + C_ECC_STATUS_REGISTERS + ECC Status and Control Register + 0 + + + + false + + + + + + C_ECC_ONOFF_REGISTER + ECC On/Off Register + 0 + + + + false + + + + + + C_ECC_ONOFF_RESET_VALUE + ECC On/Off Reset Value + 1 + + + + false + + + + + + C_CE_COUNTER_WIDTH + Correctable Error Counter Register Width + 0 + + + + false + + + + + + C_WRITE_ACCESS + Write Access setting + 2 + + + + false + + + + + + C_S_AXI_CTRL_ACLK_FREQ_HZ + S_AXI_CTRL Clock Frequency + 100000000 + + + + false + + + + + + C_S_AXI_CTRL_ADDR_WIDTH + S_AXI_CTRL Address Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_DATA_WIDTH + S_AXI_CTRL Data Width + 32 + + + + true + + + + + + C_S_AXI_CTRL_PROTOCOL + S_AXI_CTRL Protocol + AXI4LITE + + + + false + + + + + + Component_Name + bd_9d69_second_dlmb_cntlr_0 + + + + + LMB BRAM Controller + 15 + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xci new file mode 100644 index 0000000..0f09db1 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_9d69_second_ilmb_cntlr_0 + + + NONE + 32768 + 32 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 32 + READ_WRITE + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 1 + 1 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0x0000000000010000 + 32 + 0 + 0 + 0 + 0 + 1 + 0 + virtexuplus + 0 + 0x0000000000017FFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 32 + 32 + 0 + 2 + 0x0000000000010000 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0x0000000000017FFF + 0 + 32 + 32 + 0x0000000080010000 + 0x0000000000800000 + 0x0000000000800000 + 0x0000000000800000 + 1 + 100000000 + 32 + 32 + AXI4LITE + 0 + 2 + bd_9d69_second_ilmb_cntlr_0 + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Integrator + 15 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xml new file mode 100644 index 0000000..ed60d02 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/bd_0/ip/ip_8/bd_9d69_second_ilmb_cntlr_0.xml @@ -0,0 +1,3874 @@ + + + xilinx.com + customized_ip + bd_9d69_second_ilmb_cntlr_0 + 1.0 + + + INTERRUPT.INTERRUPT + Interrupt + Interrupt output + + + + + + + INTERRUPT + + + Interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + SUGGESTED_PRIORITY + HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + SLMB + SLMB + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB_ABus + + + + + ADDRSTROBE + + + LMB_AddrStrobe + + + + + BE + + + LMB_BE + + + + + CE + + + Sl_CE + + + + + READDBUS + + + Sl_DBus + + + + + READSTROBE + + + LMB_ReadStrobe + + + + + READY + + + Sl_Ready + + + + + UE + + + Sl_UE + + + + + WAIT + + + Sl_Wait + + + + + WRITEDBUS + + + LMB_WriteDBus + + + + + WRITESTROBE + + + LMB_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + SLMB1 + SLMB1 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB1_ABus + + + + + ADDRSTROBE + + + LMB1_AddrStrobe + + + + + BE + + + LMB1_BE + + + + + CE + + + Sl1_CE + + + + + READDBUS + + + Sl1_DBus + + + + + READSTROBE + + + LMB1_ReadStrobe + + + + + READY + + + Sl1_Ready + + + + + UE + + + Sl1_UE + + + + + WAIT + + + Sl1_Wait + + + + + WRITEDBUS + + + LMB1_WriteDBus + + + + + WRITESTROBE + + + LMB1_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB2 + SLMB2 + Data Processor Local Bus + + + + + + + + + ABUS + + + LMB2_ABus + + + + + ADDRSTROBE + + + LMB2_AddrStrobe + + + + + BE + + + LMB2_BE + + + + + CE + + + Sl2_CE + + + + + READDBUS + + + Sl2_DBus + + + + + READSTROBE + + + LMB2_ReadStrobe + + + + + READY + + + Sl2_Ready + + + + + UE + + + Sl2_UE + + + + + WAIT + + + Sl2_Wait + + + + + WRITEDBUS + + + LMB2_WriteDBus + + + + + WRITESTROBE + + + LMB2_WriteStrobe + + + + + + ADDR_WIDTH + 32 + + + none + + + + + DATA_WIDTH + 32 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + + + + false + + + + + + SLMB3 + SLMB3 + Data Processor Local Bus + + + + + + + + + ABUS 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Slave AXI4Lite Control + + + + + + + + + ARADDR + + + S_AXI_CTRL_ARADDR + + + + + ARREADY + + + S_AXI_CTRL_ARREADY + + + + + ARVALID + + + S_AXI_CTRL_ARVALID + + + + + AWADDR + + + S_AXI_CTRL_AWADDR + + + + + AWREADY + + + S_AXI_CTRL_AWREADY + + + + + AWVALID + + + S_AXI_CTRL_AWVALID + + + + + BREADY + + + S_AXI_CTRL_BREADY + + + + + BRESP + + + S_AXI_CTRL_BRESP + + + + + BVALID + + + S_AXI_CTRL_BVALID + + + + + RDATA + + + S_AXI_CTRL_RDATA + + + + + RREADY + + + S_AXI_CTRL_RREADY + + + + + RRESP + + + S_AXI_CTRL_RRESP + + + + + RVALID + + + S_AXI_CTRL_RVALID + + + + + WDATA + + + S_AXI_CTRL_WDATA + + + + + WREADY + + + S_AXI_CTRL_WREADY + + + + + WSTRB + + + S_AXI_CTRL_WSTRB + + + + + WVALID + + + S_AXI_CTRL_WVALID + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + 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+ + ASSOCIATED_BUSIF + SLMB:SLMB1:SLMB2:SLMB3 + + + ASSOCIATED_RESET + LMB_Rst + + + FREQ_HZ + LMB_Clk frequency + LMB_Clk frequency + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.LMB_Rst + Reset + Reset + + + + + + + RST + + + LMB_Rst + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + CLK.S_AXI_CTRL_ACLK + S_AXI_CTRL_ACLK + Slave AXI4Lite Control Clock Input + + + + + + + CLK + + + S_AXI_CTRL_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI_CTRL + + + ASSOCIATED_RESET + S_AXI_CTRL_ARESETN + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.S_AXI_CTRL_ARESETN + S_AXI_CTRL_ARESETN + Slave AXI4Lite Control Reset Input + + + + + + + RST + + + S_AXI_CTRL_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + SLMB + SLMB memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB1 + SLMB1 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB2 + SLMB2 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + SLMB3 + SLMB3 memory map + + Mem + 0 + 8192 + 32 + memory + read-write + + + OFFSET_BASE_PARAM + C_BASEADDR + + + OFFSET_HIGH_PARAM + C_HIGHADDR + + + + + + S_AXI_CTRL + S_AXI_CTRL memory map + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + ECC Status + ECC Status Register + ECC Status Register + 0x0 + 2 + true + read-write + + 0x0 + + + UE Status + UE Status + Indicates if an uncorrectable error has occurred: + 0 - No uncorrectable error occurred. + 1 - Uncorrectable error occurred, cleared when 1 is written. + + 0 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + CE Status + CE Status + Indicates if a correctable error has occurred: + 0 - No correctable error occurred. + 1 - Correctable error occurred, cleared when 1 is written. + + 1 + 1 + true + read-write + oneToClear + + 0 + 0 + + false + + + + + false + + + + + + ECC EN IRQ + ECC Interrupt Enable Register + ECC Interrupt Enable Register + 0x4 + 2 + true + read-write + + 0x0 + + + UE EN IRQ + UE Enable Interrupt + Determines effect of ECC Status Register UE bit: + 0 - UE bit is not propagated to interrupt signal. + 1 - UE bit is propagated to interrupt signal. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CE EN IRQ + CE Enable Interrupt + Determines effect of ECC Status Register CE bit: + 0 - CE bit is not propagated to interrupt signal. + 1 - CE bit is propagated to interrupt signal. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + ECC ONOFF + ECC On/Off Register + ECC On/Off Register + 0x8 + 1 + true + read-write + + 1 + + + ON OFF + On/Off + Determines if ECC checking is enabled: + 0 - ECC checking is disabled. + 1 - ECC checking is enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE CNT + Correctable Error Counter Register + Correctable Error Counter Register + 0xC + 1 + true + read-write + + 0 + + + CE CNT + Correctable Error Count + Holds number of correctable errors encountered. + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + CE FFD + Correctable Error First Failing Data Register + Correctable Error First Failing Data Register + 0x100 + 32 + true + read-only + + 0 + + + CE FFD + Correctable Error First Failing Data + Data of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFE + Correctable Error First Failing ECC Register + Correctable Error First Failing ECC Register + 0x180 + 7 + true + read-only + + 0 + + + CE FFE + Correctable Error First Failing ECC + ECC of the first occurrence of a correctable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + CE FFA + Correctable Error First Failing Address Register + Correctable Error First Failing Address Register + 0x1C0 + 32 + true + read-only + + 0 + + + CE FFA + Correctable Error First Failing Address + Address of the first occurrence of a correctable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFD + Uncorrectable Error First Failing Data Register + Uncorrectable Error First Failing Data Register + 0x200 + 32 + true + read-only + + 0 + + + UE FFD + Uncorrectable Error First Failing Data + Data of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFE + Uncorrectable Error First Failing ECC Register + Uncorrectable Error First Failing ECC Register + 0x280 + 7 + true + read-only + + 0 + + + UE FFE + Uncorrectable Error First Failing ECC + ECC of the first occurrence of an uncorrectable error. + 0 + 7 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + UE FFA + Uncorrectable Error First Failing Address Register + Uncorrectable Error First Failing Address Register + 0x2C0 + 32 + true + read-only + + 0 + + + UE FFA + Uncorrectable Error First Failing Address + Address of the first occurrence of an uncorrectable error. + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + FI D + Fault Inject Data Register + Fault Inject Data Register + 0x300 + 32 + true + write-only + + 0 + + + FI D + Fault Inject Data + Bits set to 1 toggle the bits of next data word written. + 0 + 32 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + FI ECC + Fault Inject ECC Register + Fault Inject ECC Register + 0x380 + 7 + true + write-only + + 0 + + + FI ECC + Fault Inject ECC + Bits set to 1 toggle the bits of next ECC written. + 0 + 7 + true + write-only + oneToToggle + + 0 + 0 + + false + + + + + false + + + + + + + + + + + LMB_Clk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + 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AXI4_Lite + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. 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choice_pairs_5502e96b + 1 + 2 + 3 + 4 + + + choice_pairs_563648c8 + 0 + 1 + + + choice_pairs_5f1e379e + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 9 + + + choice_pairs_7ba91213 + 0 + 1 + 2 + 3 + + + choice_pairs_f0f6eb36 + 0 + 1 + 2 + 3 + 4 + 6 + 7 + 8 + 9 + + + choice_pairs_f7e0b771 + 4096 + 8192 + 12288 + 16384 + 20480 + 24576 + 32768 + 36864 + 40960 + 49152 + 65536 + 69632 + 73728 + 81920 + 98304 + 131072 + + + choice_pairs_ffa336e4 + 0 + 1 + + + + + xilinx_elaborateports_view_fileset + + ../bd_0/bd_9d69.bd + block_diagram + + + + xilinx_elaboratebd_view_fileset + + ../bd_0/bd_9d69.bd + block_diagram + + + + MicroBlaze Micro Controller System (MCS) is a light-weight general purpose micro controller system, based on the MicroBlaze processor. It is primarily intended for simple control applications, where a hardware solution would be less flexible and more difficult to implement. Software development with the Xilinx Software Development Kit (SDK) is supported, including a software driver for the peripherals. Debugging including UART is available either via SDK or directly with the Xilinx Microprocessor Debugger. +The MCS consists of the processor itself, local memory with sizes ranging from 4KB to 128KB, up to 4 Fixed Interval Timers, up to 4 Programmable Interval Timers, up to 4 32-bit General Purpose Output ports, up to 4 32-bit General Purpose Input ports, and an Interrupt Controller with up to 16 external interrupt inputs. + + + + JTAG_CHAIN + Debug JTAG User-defined Register + 2 + + + + false + + + + + + MICROBLAZE_INSTANCE + MicroBlaze Instance Name + microblaze_0 + + + AVOID_PRIMITIVES + 0 + + + PATH + Instance Hierarchical Design Name + mcs_0 + + + FREQ + Input Clock Frequency (MHz) + 100.0 + + + OPTIMIZATION + Select MicroBlaze Optimization + 1 + + + DEBUG_ENABLED + Enable Debug Support + 0 + + + TRACE + Enable MicroBlaze Trace Bus + 1 + + + ECC + Error Correction Code + 0 + + + MEMSIZE + Memory Size + 98304 + + + USE_IO_BUS + Enable IO Bus + 1 + + + USE_UART_RX + Enable Receiver + 0 + + + + true + + + + + + USE_UART_TX + Enable Transmitter + 0 + + + + true + + + + + + UART_BAUDRATE + Define Baud Rate + 9600 + + + + false + + + + + + UART_PROG_BAUDRATE + Programmable Baud Rate + 0 + + + + false + + + + + + UART_DATA_BITS + Number of Data Bits + 8 + + + + false + + + + + + UART_USE_PARITY + Use Parity + 0 + + + + false + + + + + + UART_ODD_PARITY + Even or Odd Parity + 0 + + + + false + + + + + + UART_RX_INTERRUPT + Implement Receive Interrupt + 0 + + + + false + + + + + + UART_TX_INTERRUPT + Implement Transmit Interrupt + 0 + + + + false + + + + + + UART_ERROR_INTERRUPT + Implement Error Interrupt + 0 + + + + false + + + + + + USE_FIT1 + Use Timer + 0 + + + FIT1_No_CLOCKS + Number of Clocks Between Strobes + 6216 + + + + false + + + + + + FIT1_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_FIT2 + Use Timer + 0 + + + FIT2_No_CLOCKS + Number of Clocks Between Strobes + 6216 + + + + false + + + + + + FIT2_INTERRUPT + Generate Interrupt + 0 + + + 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true + + + + + + GPO3_SIZE + Number of Bits + 32 + + + + false + + + + + + GPO3_INIT + Initial Value of GPO + 0x00000000 + + + + false + + + + + + USE_GPO4 + Use GPO + 0 + + + + true + + + + + + GPO4_SIZE + Number of Bits + 32 + + + + false + + + + + + GPO4_INIT + Initial Value of GPO + 0x00000000 + + + + false + + + + + + USE_GPI1 + Use GPI + 0 + + + + true + + + + + + GPI1_SIZE + Number of Bits + 32 + + + + false + + + + + + GPI1_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_GPI2 + Use GPI + 0 + + + + true + + + + + + GPI2_SIZE + Number of Bits + 32 + + + + false + + + + + + GPI2_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_GPI3 + Use GPI + 0 + + + + true + + + + + + GPI3_SIZE + Number of Bits + 32 + + + + false + + + + + + GPI3_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + USE_GPI4 + Use GPI + 0 + + + + true + + + + + + GPI4_SIZE + Number of Bits + 32 + + + + false + + + + + + GPI4_INTERRUPT + Generate Interrupt + 0 + + + + false + + + + + + INTC_USE_EXT_INTR + Use External Interrupts + 0 + + + INTC_INTR_SIZE + Number of External Inputs + 1 + + + + false + + + + + + INTC_LEVEL_EDGE + Level or Edge of External Interrupts + 0x0000 + + + + false + + + + + + INTC_POSITIVE + Positive or Negative External Interrupts + 0xFFFF + + + + false + + + + + + INTC_ASYNC_INTR + Interrupts asynchronous + The setting of each bit in this option indicates whether the incoming interrupt is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous. + 0xFFFF + + + + false + + + + + + INTC_NUM_SYNC_FF + Number of synchronization flip-flops + Number of synchronization flip-flops used to synchronize asynchronous interupt inputs + 2 + + + Component_Name + phy_ddr4_x8_microblaze_mcs + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_BOARD_INTERFACE + Custom + + + + true + + + + + + RESET_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO1_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO2_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO3_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO4_BOARD_INTERFACE + Custom + + + + true + + + + + + UART_BOARD_INTERFACE + Custom + + + + true + + + + + + + + MicroBlaze MCS + + XPM_MEMORY + + 9 + + true + subcore + + + + + + + + + + + + + + + 2018.2 + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xci new file mode 100644 index 0000000..39a8207 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xci @@ -0,0 +1,655 @@ + + + xilinx.com + xci + unknown + 1.0 + + + phy_ddr4_x8_phy + + + 17 + 0 + 0 + 0 + 2 + HP_IO + 2 + X0Y11 + X0Y10 + X0Y70 + X0Y11 + 12 + DDR4_SDRAM + 1 + 0 + 0 + 2 + 1 + 10000 + 10 + 2 + 8 + 5 + 9 + 9 + 9 + 72 + {{9{2'b01}}, {3{2'b00}}} + { 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, + 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111111111, 15'b111111111110011, + 15'b111111111111111, 15'b111111111111111 } + 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b +000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, + 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_011_011_011_011_111_111_011_011_011_011_000_011, 39'b000_000_000_000_001_000_001_001_001_001_001_001_001, 39'b001_001_001_000_000_001_001_001_00 +1_001_001_001_001, 39'b000_001_001_001_001_101_101_001_001_001_001_001_001 + false + 1 + 8 + 72 + 0 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + {{9{2'b11}}, {3{2'b00}}} + 12'b000000000000 + 1 + 3 + 2 + {13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b01111 +01111101, 13'b0111101111101, 13'b0111101111101, 13'b0111101111101, 13'b0000101111111, 13'b1110011111111, + 13'b0111101111111 } + { 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, + 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b011110_11_11110_01, 15'b000010_11_11111_11, + 15'b111001_11_11111_11, 15'b011111_11_11111_11 } + {12{2'b11}} + FALSE + 1 + { 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000 +011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000011000000, 13'b0000101111111, 13'b1110011111111, + 13'b0111111111111 } + 1 + 1 + 4 + 1500 + 2 + 5 + 10 + 60 + 256 + DDR4_SDRAM + 15 + 9 + VCO + 10 + 9 + true + false + 1 + DM_NO_DBI + 72 + false + 0 + No + 10000 + 833 + MTA18ASF2G72PDZ-2G3 + RDIMMs + 1.2V + 4:1 + false + false + Single + 1 + 1500 + 0.84 + no_file_loaded + false + 0 + 0 + 0 + 0 + NONE + phy_ddr4_x8_phy + false + Disable + false + 1 + 1 + false + Phy_Only_Single + false + BFM + Differential + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE 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+ NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + NONE + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xml new file mode 100644 index 0000000..67a8803 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/ip_1/phy_ddr4_x8_phy.xml @@ -0,0 +1,4864 @@ + + + xilinx.com + customized_ip + phy_ddr4_x8_phy + 1.0 + + + + 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C_HAS_RSTA + 0 + + + C_RST_PRIORITY_A + CE + + + C_RSTRAM_A + 0 + + + C_INITA_VAL + 0 + + + C_HAS_ENA + 1 + + + C_HAS_REGCEA + 0 + + + C_USE_BYTE_WEA + 0 + + + C_WEA_WIDTH + 1 + + + C_WRITE_MODE_A + WRITE_FIRST + + + C_WRITE_WIDTH_A + 64 + + + C_READ_WIDTH_A + 64 + + + C_WRITE_DEPTH_A + 16 + + + C_READ_DEPTH_A + 16 + + + C_ADDRA_WIDTH + 4 + + + C_HAS_RSTB + 0 + + + C_RST_PRIORITY_B + CE + + + C_RSTRAM_B + 0 + + + C_INITB_VAL + 0 + + + C_HAS_ENB + 0 + + + C_HAS_REGCEB + 0 + + + C_USE_BYTE_WEB + 0 + + + C_WEB_WIDTH + 1 + + + C_WRITE_MODE_B + WRITE_FIRST + + + C_WRITE_WIDTH_B + 64 + + + C_READ_WIDTH_B + 64 + + + C_WRITE_DEPTH_B + 16 + + + C_READ_DEPTH_B + 16 + + + C_ADDRB_WIDTH + 4 + + + C_HAS_MEM_OUTPUT_REGS_A + 0 + + + C_HAS_MEM_OUTPUT_REGS_B + 0 + + + C_HAS_MUX_OUTPUT_REGS_A + 0 + + + C_HAS_MUX_OUTPUT_REGS_B + 0 + + + C_MUX_PIPELINE_STAGES + 0 + + + C_HAS_SOFTECC_INPUT_REGS_A + 0 + + + C_HAS_SOFTECC_OUTPUT_REGS_B + 0 + + + C_USE_SOFTECC + 0 + + + C_USE_ECC + 0 + + + C_EN_ECC_PIPE + 0 + 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BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + pr_read_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + 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a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci new file mode 100644 index 0000000..0e0554e --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci @@ -0,0 +1,266 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pr_ref_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + + OTHER + NONE + 8192 + 32 + + + 100000000 + 0.000 + 6 + 6 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 5.931282 mW + virtexuplus + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + pr_ref_mem.mem + pr_ref_mem.mif + 0 + 1 + 0 + 0 + 1 + 64 + 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b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml new file mode 100644 index 0000000..e1caf51 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml @@ -0,0 +1,4055 @@ + + + xilinx.com + customized_ip + pr_ref_mem + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + AXI_SLAVE_S_AXI + AXI_SLAVE + AXI_SLAVE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARBURST + + + s_axi_arburst + + + + + ARID + + + s_axi_arid + + + + + ARLEN + + + s_axi_arlen + + + + + ARREADY + + + s_axi_arready + + + + + ARSIZE + + + s_axi_arsize + + + + + ARVALID + + + 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choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + pr_ref_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + 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+ C_AXI_TYPE + 1 + + + C_HAS_AXI_WR_CHANNEL + 1 + + + C_HAS_AXI_RD_CHANNEL + 1 + + + C_HAS_SLAVE_CE + 0 + + + C_HAS_MASTER_CE + 0 + + + C_ADD_NGC_CONSTRAINT + 0 + + + C_USE_COMMON_OVERFLOW + 0 + + + C_USE_COMMON_UNDERFLOW + 0 + + + C_USE_DEFAULT_SETTINGS + 0 + + + C_AXI_ID_WIDTH + 1 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 64 + + + C_AXI_LEN_WIDTH + 8 + + + C_AXI_LOCK_WIDTH + 1 + + + C_HAS_AXI_ID + 0 + + + C_HAS_AXI_AWUSER + 0 + + + C_HAS_AXI_WUSER + 0 + + + C_HAS_AXI_BUSER + 0 + + + C_HAS_AXI_ARUSER + 0 + + + C_HAS_AXI_RUSER + 0 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_HAS_AXIS_TDATA + 1 + + + C_HAS_AXIS_TID + 0 + + + C_HAS_AXIS_TDEST + 0 + + + C_HAS_AXIS_TUSER + 1 + + + C_HAS_AXIS_TREADY + 1 + + + C_HAS_AXIS_TLAST + 0 + + + C_HAS_AXIS_TSTRB + 0 + + + C_HAS_AXIS_TKEEP + 0 + + + C_AXIS_TDATA_WIDTH + 8 + + + C_AXIS_TID_WIDTH + 1 + + + C_AXIS_TDEST_WIDTH + 1 + + + C_AXIS_TUSER_WIDTH + 4 + + + C_AXIS_TSTRB_WIDTH + 1 + + + C_AXIS_TKEEP_WIDTH + 1 + + + C_WACH_TYPE + 0 + + + C_WDCH_TYPE + 0 + + + C_WRCH_TYPE + 0 + + + C_RACH_TYPE + 0 + + + C_RDCH_TYPE + 0 + + + C_AXIS_TYPE + 0 + + + C_IMPLEMENTATION_TYPE_WACH + 1 + + + C_IMPLEMENTATION_TYPE_WDCH + 1 + + + C_IMPLEMENTATION_TYPE_WRCH + 1 + + + C_IMPLEMENTATION_TYPE_RACH + 1 + + + C_IMPLEMENTATION_TYPE_RDCH + 1 + + + C_IMPLEMENTATION_TYPE_AXIS + 1 + + + C_APPLICATION_TYPE_WACH + 0 + + + C_APPLICATION_TYPE_WDCH + 0 + + + C_APPLICATION_TYPE_WRCH + 0 + + + C_APPLICATION_TYPE_RACH + 0 + + + C_APPLICATION_TYPE_RDCH + 0 + + + C_APPLICATION_TYPE_AXIS + 0 + + + C_PRIM_FIFO_TYPE_WACH + 512x36 + + + C_PRIM_FIFO_TYPE_WDCH + 512x72 + + + C_PRIM_FIFO_TYPE_WRCH + 512x36 + + + C_PRIM_FIFO_TYPE_RACH + 512x36 + + + C_PRIM_FIFO_TYPE_RDCH + 512x72 + + + C_PRIM_FIFO_TYPE_AXIS + 1kx18 + + + C_USE_ECC_WACH + 0 + + + C_USE_ECC_WDCH + 0 + + + C_USE_ECC_WRCH + 0 + + + C_USE_ECC_RACH + 0 + + + C_USE_ECC_RDCH + 0 + + + C_USE_ECC_AXIS + 0 + + + C_ERROR_INJECTION_TYPE_WACH + 0 + + + C_ERROR_INJECTION_TYPE_WDCH + 0 + + + C_ERROR_INJECTION_TYPE_WRCH + 0 + + + C_ERROR_INJECTION_TYPE_RACH + 0 + + + C_ERROR_INJECTION_TYPE_RDCH + 0 + + + C_ERROR_INJECTION_TYPE_AXIS + 0 + + + C_DIN_WIDTH_WACH + 1 + + + C_DIN_WIDTH_WDCH + 64 + + + C_DIN_WIDTH_WRCH + 2 + + + C_DIN_WIDTH_RACH + 32 + + + C_DIN_WIDTH_RDCH + 64 + + + C_DIN_WIDTH_AXIS + 1 + + + C_WR_DEPTH_WACH + 16 + + + C_WR_DEPTH_WDCH + 1024 + + + C_WR_DEPTH_WRCH + 16 + + + C_WR_DEPTH_RACH + 16 + + + C_WR_DEPTH_RDCH + 1024 + + + C_WR_DEPTH_AXIS + 1024 + + + C_WR_PNTR_WIDTH_WACH + 4 + + + C_WR_PNTR_WIDTH_WDCH + 10 + + + C_WR_PNTR_WIDTH_WRCH + 4 + + + C_WR_PNTR_WIDTH_RACH + 4 + + + C_WR_PNTR_WIDTH_RDCH + 10 + + + C_WR_PNTR_WIDTH_AXIS + 10 + + + C_HAS_DATA_COUNTS_WACH + 0 + + + C_HAS_DATA_COUNTS_WDCH + 0 + + + C_HAS_DATA_COUNTS_WRCH + 0 + + + C_HAS_DATA_COUNTS_RACH + 0 + + + C_HAS_DATA_COUNTS_RDCH + 0 + + + C_HAS_DATA_COUNTS_AXIS + 0 + + + C_HAS_PROG_FLAGS_WACH + 0 + + + C_HAS_PROG_FLAGS_WDCH + 0 + + + C_HAS_PROG_FLAGS_WRCH + 0 + + + C_HAS_PROG_FLAGS_RACH + 0 + + + C_HAS_PROG_FLAGS_RDCH + 0 + + + C_HAS_PROG_FLAGS_AXIS + 0 + + + C_PROG_FULL_TYPE_WACH + 0 + + + C_PROG_FULL_TYPE_WDCH + 0 + + + C_PROG_FULL_TYPE_WRCH + 0 + + + C_PROG_FULL_TYPE_RACH + 0 + + + C_PROG_FULL_TYPE_RDCH + 0 + + + C_PROG_FULL_TYPE_AXIS + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WRCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_165ed04b + 64 + + + choice_list_22f447d7 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_62eb4a48 + 512 + 1024 + 2048 + 4096 + 8192 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_19452de4 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_40558afa + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + choice_pairs_ef3e87e1 + Embedded_Reg + + + choice_pairs_f78383bc + Synchronous_Reset + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + rdback_fifo + + + + true + + + + + + Fifo_Implementation + Common_Clock_Builtin_FIFO + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + First_Word_Fall_Through + + + + true + + + + + + asymmetric_port_width + true + + + + true + + + + + + Input_Data_Width + 512 + + + + true + + + + + + Input_Depth + 1024 + + + + true + + + + + + Output_Data_Width + 256 + + + + true + + + + + + Output_Depth + 2048 + + + + false + + + + + + Enable_ECC + false + + + + false + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + false + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + false + + + + + + Full_Flags_Reset_Value + 0 + + + + false + + + + + + Use_Dout_Reset + true + + + + false + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + true + + + + + + Almost_Full_Flag + false + + + + false + + + + + + Almost_Empty_Flag + false + + + + false + + + + + + Valid_Flag + true + + + + true + + + + + + Valid_Sense + Active_High + + + + true + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + false + + + + false + + + + + + Data_Count_Width + 10 + + + + false + + + + + + Write_Data_Count + false + + + + false + + + + + + Write_Data_Count_Width + 10 + + + + false + + + + + + Read_Data_Count + false + + + + false + + + + + + Read_Data_Count_Width + 11 + + + + false + + + + + + Disable_Timing_Violations + false + + + + false + + + + + + Read_Clock_Frequency + 1 + + + + false + + + + + + Write_Clock_Frequency + 1 + + + + false + + + + + + Programmable_Full_Type + Single_Programmable_Full_Threshold_Constant + + + + true + + + + + + Full_Threshold_Assert_Value + 800 + + + + true + + + + + + Full_Threshold_Negate_Value + 799 + + + + false + + + + + + Programmable_Empty_Type + No_Programmable_Empty_Threshold + + + + true + + + + + + Empty_Threshold_Assert_Value + 4 + + + + false + + + + + + Empty_Threshold_Negate_Value + 5 + + + + false + + + + + + PROTOCOL + AXI4 + + + + false + + + + + + Clock_Type_AXI + Common_Clock + + + + true + + + + + + HAS_ACLKEN + false + + + + false + + + + + + Clock_Enable_Type + Slave_Interface_Clock_Enable + + + + false + + + + + + READ_WRITE_MODE + READ_WRITE + + + + true + + + + + + ID_WIDTH + 0 + + + + false + + + + + + ADDRESS_WIDTH + 32 + + + + false + + + + + + DATA_WIDTH + 64 + + + + false + + + + + + AWUSER_Width + 0 + + + + false + + + + + + WUSER_Width + 0 + + + + false + + + + + + BUSER_Width + 0 + + + + false + + + + + + ARUSER_Width + 0 + + + + false + + + + + + RUSER_Width + 0 + + + + false + + + + + + TDATA_NUM_BYTES + 1 + + + + true + + + + + + TID_WIDTH + 0 + + + + false + + + + + + TDEST_WIDTH + 0 + + + + false + + + + + + TUSER_WIDTH + 4 + + + + false + + + + + + Enable_TREADY + true + + + + false + + + + + + Enable_TLAST + false + + + + true + + + + + + HAS_TSTRB + false + + + + false + + + + + + TSTRB_WIDTH + 1 + + + + false + + + + + + HAS_TKEEP + false + + + + false + + + + + + TKEEP_WIDTH + 1 + + + + false + + + + + + wach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wach + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wach + false + + + + false + + + + + + Inject_Sbit_Error_wach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wach + false + + + + false + + + + + + Input_Depth_wach + 16 + + + + true + + + + + + Enable_Data_Counts_wach + false + + + + false + + + + + + Programmable_Full_Type_wach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wdch + false + + + + false + + + + + + Inject_Sbit_Error_wdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wdch + false + + + + false + + + + + + Input_Depth_wdch + 1024 + + + + true + + + + + + Enable_Data_Counts_wdch + false + + + + false + + + + + + Programmable_Full_Type_wdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wrch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wrch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wrch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wrch + false + + + + false + + + + + + Inject_Sbit_Error_wrch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wrch + false + + + + false + + + + + + Input_Depth_wrch + 16 + + + + true + + + + + + Enable_Data_Counts_wrch + false + + + + false + + + + + + Programmable_Full_Type_wrch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wrch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wrch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wrch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rach + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rach + false + + + + false + + + + + + Inject_Sbit_Error_rach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rach + false + + + + false + + + + + + Input_Depth_rach + 16 + + + + true + + + + + + Enable_Data_Counts_rach + false + + + + false + + + + + + Programmable_Full_Type_rach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rdch + false + + + + false + + + + + + Inject_Sbit_Error_rdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rdch + false + + + + false + + + + + + Input_Depth_rdch + 1024 + + + + true + + + + + + Enable_Data_Counts_rdch + false + + + + false + + + + + + Programmable_Full_Type_rdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + axis_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_axis + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_axis + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_axis + false + + + + false + + + + + + Inject_Sbit_Error_axis + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_axis + Double Bit Error Injection + false + + + + false + + + + + + Input_Depth_axis + 1024 + + + + true + + + + + + Enable_Data_Counts_axis + false + + + + false + + + + + + Programmable_Full_Type_axis + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_axis + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_axis + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_axis + Empty Threshold Assert Value + 1022 + + + + false + + + + + + Register_Slice_Mode_wach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wrch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_axis + Register Slice Options + Fully_Registered + + + + true + + + + + + Underflow_Flag_AXI + Underflow Flag + false + + + + false + + + + + + Underflow_Sense_AXI + Underflow (Read Error) + Active_High + + + + false + + + + + + Overflow_Flag_AXI + Overflow Flag + false + + + + false + + + + + + Overflow_Sense_AXI + Overflow (Write Error) + Active_High + + + + false + + + + + + Disable_Timing_Violations_AXI + false + + + + true + + + + + + Add_NGC_Constraint_AXI + false + + + + true + + + + + + Enable_Common_Underflow + false + + + + true + + + + + + Enable_Common_Overflow + false + + + + true + + + + + + enable_read_pointer_increment_by2 + false + + + + true + + + + + + Use_Embedded_Registers_axis + false + + + + false + + + + + + enable_low_latency + false + + + + false + + + + + + use_dout_register + false + + + + false + + + + + + Master_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Slave_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Output_Register_Type + Embedded_Reg + + + + true + + + + + + Enable_Safety_Circuit + false + + + + false + + + + + + Enable_ECC_Type + Hard_ECC + + + + false + + + + + + C_SELECT_XPM + 0 + + + + + FIFO Generator + + XPM_MEMORY + XPM_CDC + + 2 + + + + + + + + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/scratchpad/scratchpad.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/scratchpad/scratchpad.xci new file mode 100644 index 0000000..b4ce5eb --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/scratchpad/scratchpad.xci @@ -0,0 +1,263 @@ + + + xilinx.com + xci + unknown + 1.0 + + + scratchpad + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + + OTHER + NONE + 8192 + 32 + + + 100000000 + 0.000 + 10 + 10 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 2.119075 mW + virtexuplus + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + scratchpad.mem + no_coe_file_loaded + 0 + 0 + 0 + 0 + 1 + 1024 + 1024 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1024 + 1024 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + no_coe_file_loaded + ALL + scratchpad + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 1024 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2018.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/scratchpad/scratchpad.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/scratchpad/scratchpad.xml new file mode 100644 index 0000000..711e5ee --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/scratchpad/scratchpad.xml @@ -0,0 +1,4052 @@ + + + xilinx.com + customized_ip + scratchpad + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + AXI_SLAVE_S_AXI + AXI_SLAVE + AXI_SLAVE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARBURST + + + s_axi_arburst + + + + + ARID + + + s_axi_arid + + + + + ARLEN + + + s_axi_arlen + + + + + ARREADY + + + s_axi_arready + + + + + ARSIZE + + + s_axi_arsize + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWBURST + + + s_axi_awburst + + + + + AWID + + + s_axi_awid + + + + + AWLEN + + + s_axi_awlen + + + + + AWREADY + + + s_axi_awready + + + + + AWSIZE + + + s_axi_awsize + + + + + AWVALID + + + s_axi_awvalid + + + + + BID + + + s_axi_bid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RID + + + s_axi_rid + + + + + RLAST + + + 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C_PRIM_TYPE + 1 + + + C_LOAD_INIT_FILE + 0 + + + C_INIT_FILE_NAME + no_coe_file_loaded + + + C_INIT_FILE + scratchpad.mem + + + C_USE_DEFAULT_DATA + 0 + + + C_DEFAULT_DATA + 0 + + + C_HAS_RSTA + 0 + + + C_RST_PRIORITY_A + CE + + + C_RSTRAM_A + 0 + + + C_INITA_VAL + 0 + + + C_HAS_ENA + 1 + + + C_HAS_REGCEA + 0 + + + C_USE_BYTE_WEA + 0 + + + C_WEA_WIDTH + 1 + + + C_WRITE_MODE_A + WRITE_FIRST + + + C_WRITE_WIDTH_A + 32 + + + C_READ_WIDTH_A + 32 + + + C_WRITE_DEPTH_A + 1024 + + + C_READ_DEPTH_A + 1024 + + + C_ADDRA_WIDTH + 10 + + + C_HAS_RSTB + 0 + + + C_RST_PRIORITY_B + CE + + + C_RSTRAM_B + 0 + + + C_INITB_VAL + 0 + + + C_HAS_ENB + 0 + + + C_HAS_REGCEB + 0 + + + C_USE_BYTE_WEB + 0 + + + C_WEB_WIDTH + 1 + + + C_WRITE_MODE_B + WRITE_FIRST + + + C_WRITE_WIDTH_B + 32 + + + C_READ_WIDTH_B + 32 + + + C_WRITE_DEPTH_B + 1024 + + + C_READ_DEPTH_B + 1024 + + + C_ADDRB_WIDTH + 10 + + + C_HAS_MEM_OUTPUT_REGS_A + 0 + + + C_HAS_MEM_OUTPUT_REGS_B + 0 + + + C_HAS_MUX_OUTPUT_REGS_A + 0 + + + C_HAS_MUX_OUTPUT_REGS_B + 0 + + + C_MUX_PIPELINE_STAGES + 0 + + + C_HAS_SOFTECC_INPUT_REGS_A + 0 + + + C_HAS_SOFTECC_OUTPUT_REGS_B + 0 + + + C_USE_SOFTECC + 0 + + + C_USE_ECC + 0 + + + C_EN_ECC_PIPE + 0 + + + C_HAS_INJECTERR + 0 + + + C_SIM_COLLISION_CHECK + ALL + + + C_COMMON_CLK + 0 + + + C_DISABLE_WARN_BHV_COLL + 0 + + + C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 0 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 1 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 2.119075 mW + + + + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_784e1e2a + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + scratchpad + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + false + + + + + + RD_ADDR_CHNG_B + false + + + + false + + + + + + Use_Error_Injection_Pins + false + + + + false + + + + + + Error_Injection_Type + Single_Bit_Error_Injection + + + + false + + + + + + Use_Byte_Write_Enable + false + + + + true + + + + + + Byte_Size + 9 + + + + false + + + + + + Algorithm + Minimum_Area + + + + true + + + + + + Primitive + 8kx2 + + + + false + + + + + + Assume_Synchronous_Clk + false + + + + false + + + + + + Write_Width_A + 32 + + + + true + + + + + + Write_Depth_A + 1024 + + + + true + + + + + + Read_Width_A + 32 + + + + true + + + + + + Operating_Mode_A + WRITE_FIRST + + + + true + + + + + + Enable_A + Use_ENA_Pin + + + + true + + + + + + Write_Width_B + 32 + + + + false + + + + + + Read_Width_B + 32 + + + + false + + + + + + Operating_Mode_B + WRITE_FIRST + + + + false + + + + + + Enable_B + Always_Enabled + + + + false + + + + + + Register_PortA_Output_of_Memory_Primitives + false + + + + true + + + + + + Register_PortA_Output_of_Memory_Core + false + + + + true + + + + + + Use_REGCEA_Pin + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Primitives + false + + + + false + + + + + + Register_PortB_Output_of_Memory_Core + false + + + + false + + + + + + Use_REGCEB_Pin + false + + + + false + + + + + + register_porta_input_of_softecc + false + + + + false + + + + + + register_portb_output_of_softecc + false + + + + false + + + + + + Pipeline_Stages + 0 + + + + false + + + + + + Load_Init_File + false + + + + true + + + + + + Coe_File + no_coe_file_loaded + + + + false + + + + + + Fill_Remaining_Memory_Locations + false + + + + true + + + + + + Remaining_Memory_Locations + 0 + + + + false + + + + + + Use_RSTA_Pin + false + + + + true + + + + + + Reset_Memory_Latch_A + false + + + + false + + + + + + Reset_Priority_A + CE + + + + false + + + + + + Output_Reset_Value_A + 0 + + + + false + + + + + + Use_RSTB_Pin + false + + + + false + + + + + + Reset_Memory_Latch_B + false + + + + false + + + + + + Reset_Priority_B + CE + + + + false + + + + + + Output_Reset_Value_B + 0 + + + + false + + + + + + Reset_Type + SYNC + + + + false + + + + + + Additional_Inputs_for_Power_Estimation + false + + + + true + + + + + + Port_A_Clock + 100 + + + + true + + + + + + Port_A_Write_Rate + 50 + + + + true + + + + + + Port_B_Clock + 0 + + + + true + + + + + + Port_B_Write_Rate + 0 + + + + true + + + + + + Port_A_Enable_Rate + 100 + + + + true + + + + + + Port_B_Enable_Rate + 0 + + + + true + + + + + + Collision_Warnings + ALL + + + + true + + + + + + Disable_Collision_Warnings + false + + + + true + + + + + + Disable_Out_of_Range_Warnings + false + + + + true + + + + + + use_bram_block + Stand_Alone + + + + true + + + + + + MEM_FILE + no_mem_loaded + + + + true + + + + + + CTRL_ECC_ALGO + NONE + + + + true + + + + + + EN_SAFETY_CKT + false + + + + false + + + + + + + + Block Memory Generator + + XPM_MEMORY + + 1 + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xci new file mode 100644 index 0000000..8190fd6 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xci @@ -0,0 +1,1430 @@ + + + xilinx.com + xci + unknown + 1.0 + + + xdma_pcie4_ip_gt + + + "000000000000000000000000000000000000000000000000000000000000111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" + 2 + 2500.0 + 0 + 0 + 100 + 67 + 3 + 1 + 0 + 2 + 1 + 0 + 1 + 1 + 1 + 1 + 500 + 1 + 0 + 0 + 0 + 0 + 1 + "00000000" + "00000000" + 1 + 4 + 0 + "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + "00000000" + 1 + "00000001" + 1 + 1 + 5000 + "00000000000000000000000000000000000000000000000000000000000000000000000000011100" + 1 + "1010000011" + 1 + "0101111100" + 1 + 1 + 20 + 8 + 131 + 1 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txmaincursor_in txmargin_in txpcsreset_in txpd_in txpmareset_in txpostcursor_in txprbsforceerr_in txprbssel_in txprecursor_in txrate_in txswing_in bufgtce_out bufgtcemask_out bufgtdiv_out bufgtreset_out bufgtrstmask_out drpdo_common_out drprdy_common_out gtpowergood_out pcierategen3_out pcierateidle_out pcierateqpllpd_out pcierateqpllreset_out pciesynctxsyncdone_out pcieusergen3rdy_out pcie +userphystatusrst_out pcieuserratestart_out phystatus_out rxelecidle_out rxoutclkfabric_out rxoutclkpcs_out rxprbserr_out rxprbslocked_out rxrecclkout_out rxstatus_out rxvalid_out txoutclkfabric_out txoutclkpcs_out qpll1freqlock_in qpll0freqlock_in cpllfreqlock_in qpll0lock_out qpll1lock_out drpclk_in cpllreset_in qpll1outclk_out qpll1outrefclk_out qpll0outclk_out qpll0outrefclk_out pcierateqpll0_in pcierateqpll1_in gtrefclk00_in gtrefclk01_in qpll0reset_in qpll1reset_in drpwe_in drpaddr_in drpen +_in drprst_in drprdy_out drpdi_in drpdo_out rxcdrhold_in rxdfeagchold_in rxdfecfokhold_in rxdfelfhold_in rxdfekhhold_in rxdfetap2hold_in rxdfetap3hold_in rxdfetap4hold_in rxdfetap5hold_in rxdfetap6hold_in rxdfetap7hold_in rxdfetap8hold_in rxdfetap9hold_in rxdfetap10hold_in rxdfetap11hold_in rxdfetap12hold_in rxdfetap13hold_in rxdfetap14hold_in rxdfetap15hold_in rxdfeuthold_in rxdfevphold_in rxoshold_in rxlpmgchold_in rxlpmhfhold_in rxlpmlfhold_in rxlpmoshold_in rxratedone_out rxcdrfreqreset_in r +esetovrd_in txoutclksel_in cplllock_out gtrefclk0_in + 100 + BOTH + 0 + GTY + 1 + 15 + 96 + 5 + gtye4 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + 0 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + -1 + -1 + -1 + -1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + -1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + 1 + 1 + 1 + -1 + -1 + -1 + -1 + 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GTY-Aurora_64B66B + GTY-Aurora_8B10B + GTY-Bandwidth_Engine + GTY-CAUI_10 + GTY-CAUI_10_raw + GTY-CAUI_4 + GTY-CEI_11G_SR + GTY-CPRI_10G + GTY-CPRI_10_1G + GTY-CPRI_10_1G_lowloss + GTY-CPRI_6G + GTY-DisplayPort_1_62G + GTY-DisplayPort_2_7G + GTY-DisplayPort_5_4G + GTY-Gigabit_Ethernet + GTY-HDMI + GTY-HD_SDI + GTY-HMC_12_5G + GTY-Interlaken_10G + GTY-Interlaken_12_5G + GTY-Interlaken_25G + GTY-JESD204 + GTY-JESD204B_highloss + GTY-JESD204B_lowloss + GTY-OTL4_10 + GTY-OTU2 + GTY-OTU2e + GTY-OTU4 + GTY-QSGMII + GTY-RXAUI + GTY-SATA + GTY-SRIO_Gen2 + GTY-XAUI + GTY-XLAUI + + + choice_pairs_40d02874 + 10GBASE_KR + CUSTOM + PCIE_GEN1_GEN2 + PCIE_GEN3 + QPI + + + choice_pairs_4e550952 + NONE + EXAMPLE_DESIGN + + + choice_pairs_7b0c3758 + RX + BOTH + TX + + + choice_pairs_85f99b7f + K28.1 + K28.5 + NONE + + + choice_pairs_8846c8f0 + RAW + 8B10B + 64B66B + 64B66B_CAUI + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_88c85933 + 8B10B + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + RAW + 64B66B + 64B66B_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_93c2d4ee + CORE + EXAMPLE_DESIGN + + + choice_pairs_9c19f015 + 1 + 2 + + + choice_pairs_a537ddda + 0 + 1 + + + choice_pairs_aa541099 + AUTO + DFE + LPM + + + choice_pairs_ae574462 + OFF + PCS + PMA + AUTO + + + choice_pairs_b0974ef0 + 1 + 2 + 0 + + + choice_pairs_d4feb97d + DISABLE + ENABLE + + + choice_pairs_f05b8192 + CHANNEL + NAME + + + The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. + + + GT_TYPE + Transceiver type + For devices which contain more than one serial transceiver type, select the type of transceiver to configure + GTY + + + INTERNAL_GT_PRIM_TYPE + gtye4 + + + + false + + + + + + GT_REV + Transceiver revision + Select the serial transceiver silicon revision + 0 + + + GT_DIRECTION + Transmit and/or Receive direction + Enable transmit and/or receive + BOTH + + + RX_ENABLE + Enabled + Enable the receiver for use + true + + + + false + + + + + + TX_ENABLE + Enabled + Enable the transmitter for use + true + + + + false + + + + + + CHANNEL_ENABLE + Enable channel + Indicate whether this transceiver channel is instantiated and enabled for use + X1Y35 X1Y34 X1Y33 X1Y32 X1Y31 X1Y30 X1Y29 X1Y28 + + + TX_MASTER_CHANNEL + Master TX channel + Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) + X1Y35 + + + RX_MASTER_CHANNEL + Master RX channel + Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) + X1Y35 + + + INTERNAL_TOTAL_NUM_CHANNELS + Total number of channels + 8 + + + + false + + + + + + INTERNAL_TOTAL_NUM_COMMONS + Total number of commons required + 2 + + + + false + + + + + + LOCATE_COMMON + Include transceiver COMMON in the + If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. + CORE + + + INTERNAL_NUM_COMMONS_CORE + Number of commons in core + 2 + + + + false + + + + + + INTERNAL_NUM_COMMONS_EXAMPLE + Number of commons in example + 0 + + + + false + + + + + + INTERNAL_TX_USRCLK_FREQUENCY + 400.0000000 + + + + false + + + + + + INTERNAL_RX_USRCLK_FREQUENCY + 400.0000000 + + + + false + + + + + + RX_PPM_OFFSET + PPM offset between receiver and transmitter + Specify the PPM offset between received data and transmitted data + 0 + + + OOB_ENABLE + Enable Out of Band signaling (OOB)/Electrical Idle + Enable or disable Out of Band signaling (OOB)/Electrical Idle + false + + + + false + + + + + + RX_SSC_PPM + Spread spectrum clocking + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Insertion loss at Nyquist (dB) + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 15 + + + PCIE_CORECLK_FREQ + 500 + + + PCIE_USERCLK_FREQ + 250 + + + TX_LINE_RATE + Line rate (Gb/s) + Enter the transmitter line rate in Gb/s + 8 + + + TX_PLL_TYPE + PLL type + Select the transmitter PLL type + QPLL1 + + + TX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type + 100 + + + TX_DATA_ENCODING + Encoding + Select the encoding format for data transmission, or choose 'Raw' for no data encoding + 8B10B + + + TX_USER_DATA_WIDTH + User data width + Select the width at which the user logic will provide parallel data to the serial transceiver for transmission + 16 + + + TX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal transmitter data path + 20 + + + TX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the transmitter buffer + 0 + + + TX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection + 0 + + + TX_OUTCLK_SOURCE + TXOUTCLK source + Select the source of TXOUTCLK + TXPROGDIVCLK + + + TX_DIFF_SWING_EMPH_MODE + Differential swing and emphasis mode + Select the transmitter differential swing and emphasis mode for your application + PCIE_GEN1_GEN2 + + + RX_LINE_RATE + Line rate (Gb/s) + Enter the receiver line rate in Gb/s + 8 + + + RX_PLL_TYPE + PLL type + Select the receiver PLL type + QPLL1 + + + RX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type + 100 + + + RX_DATA_DECODING + Decoding + Select the decoding format for data reception, or choose 'Raw' for no data decoding + 8B10B + + + RX_USER_DATA_WIDTH + User data width + Select the width at which the serial transceiver will provide received parallel data to the user logic + 16 + + + RX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal receiver data path + 20 + + + RX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the receiver elastic buffer + 1 + + + RX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection + 0 + + + RX_EQ_MODE + Equalization mode + Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. + DFE + + + RX_JTOL_FC + Mask corner frequency (MHz) + Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. + 1 + + + RX_JTOL_LF_SLOPE + Mask low frequency slope (dB/decade) + Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. + -20 + + + RX_OUTCLK_SOURCE + RXOUTCLK source + Select the source of RXOUTCLK + RXOUTCLKPMA + + + SIM_CPLL_CAL_BYPASS + 1 + + + PCIE_ENABLE + true + + + RX_TERMINATION + Termination + Select the receiver termination + PROGRAMMABLE + + + RX_TERMINATION_PROG_VALUE + Programmable termination voltage (mV) + Select the termination voltage (in mV) when in programmable mode + 800 + + + RX_COUPLING + Link coupling + Select the link coupling + AC + + + RX_BUFFER_BYPASS_MODE + Receiver elastic buffer bypass mode + Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode + MULTI + + + + false + + + + + + RX_BUFFER_RESET_ON_CB_CHANGE + Reset receiver elastic buffer on channel bonding change + Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL + ENABLE + + + + false + + + + + + RX_BUFFER_RESET_ON_COMMAALIGN + Reset receiver elastic buffer on comma alignment + Control whether the receiver elastic buffer is reset on comma alignment + DISABLE + + + RX_BUFFER_RESET_ON_RATE_CHANGE + Reset receiver elastic buffer on rate change + Control whether the receiver elastic buffer is reset on rate change + ENABLE + + + TX_BUFFER_RESET_ON_RATE_CHANGE + Reset transmitter buffer on rate change + Control whether the transmitter buffer is reset on rate change + ENABLE + + + + false + + + + + + RESET_SEQUENCE_INTERVAL + Reset sequence time interval (ns) + Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval + 0 + + + RX_COMMA_PRESET + Comma value preset + K28.5 + + + RX_COMMA_VALID_ONLY + Valid comma values for 8B/10B decoding + Select the range of comma characters decoded by the 8B/10B decoder + 0 + + + RX_COMMA_P_ENABLE + Detect plus comma + Indicate whether or not the specified bit pattern is detected as a plus comma + true + + + RX_COMMA_M_ENABLE + Detect minus comma + Indicate whether or not the specified bit pattern is detected as a minus comma + true + + + RX_COMMA_DOUBLE_ENABLE + Detect combined plus/minus (double-length) comma + Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence + false + + + RX_COMMA_P_VAL + Plus comma value + Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received + 0101111100 + + + RX_COMMA_M_VAL + Minus comma value + Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received + 1010000011 + + + RX_COMMA_MASK + Mask + Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" + 1111111111 + + + RX_COMMA_ALIGN_WORD + Alignment boundary + Select which data byte boundaries are allowed for comma alignment + 1 + + + RX_COMMA_SHOW_REALIGN_ENABLE + Show realign comma + Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency + true + + + RX_SLIDE_MODE + Manual alignment (RXSLIDE) mode + Select whether to enable manual alignment, and in what mode if enabled + PMA + + + RX_CB_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable channel bonding, and how many sequences to use if enabled + 0 + + + RX_CB_LEN_SEQ + Length of each sequence + Select the number of characters in each channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_SKEW + Sequence maximum skew + Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_LEVEL + Maximum channel bonding level to be used + Select the maximum channel bonding level that will be used in the system channel bonding topology + 4 + + + + false + + + + + + RX_CB_MASK + 00000000 + + + + false + + + + + + RX_CB_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + + + + false + + + + + + RX_CB_K + 00000000 + + + + false + + + + + + RX_CB_DISP + 00000000 + + + + false + + + + + + RX_CB_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable clock correction, and how many sequences to use if enabled + 1 + + + RX_CC_LEN_SEQ + Length of each sequence + Select the number of characters in each channel clock correction sequence + 1 + + + RX_CC_PERIODICITY + Periodicity of the sequence (in bytes) + Specify the separation between clock correction sequences, in bytes + 5000 + + + RX_CC_KEEP_IDLE + Keep idle + Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received + ENABLE + + + RX_CC_PRECEDENCE + Precedence + Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time + ENABLE + + + + false + + + + + + RX_CC_REPEAT_WAIT + Minimum repetition + Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction + 0 + + + RX_CC_MASK + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + 00000000 + + + + false + + + + + + RX_CC_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000011100 + + + RX_CC_K + 00000001 + + + + false + + + + + + RX_CC_DISP + 00000000 + + + + false + + + + + + RX_CC_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_0 + Value + Specify the value for this clock correction sequence and pattern + 00011100 + + + RX_CC_K_0_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_1 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_0 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_1 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + ENABLE_OPTIONAL_PORTS + Enable optional ports + Indicate whether a port should be included + txprgdivresetdone_out rcalenb_in txpisopd_in rxratemode_in dmonfiforeset_in dmonitorclk_in dmonitorout_out txdlysresetdone_out rxdlysresetdone_out rxphaligndone_out rxsyncdone_out eyescanreset_in txdiffctrl_in rxtermination_in cpllpd_in drpaddr_common_in drpclk_common_in drpdi_common_in drpen_common_in drpwe_common_in loopback_in pcieeqrxeqadaptdone_in pcierstidle_in pciersttxsyncstart_in pcieuserratedone_in qpll0pd_in qpll1pd_in rxcdrreset_in rxdfelpmreset_in rxlpmen_in rxpcsreset_in rxpd_in rx +pmareset_in rxpolarity_in rxprbscntreset_in rxprbssel_in rxrate_in txdeemph_in txdetectrx_in txelecidle_in txmaincursor_in txmargin_in txpcsreset_in txpd_in txpmareset_in txpostcursor_in txprbsforceerr_in txprbssel_in txprecursor_in txrate_in txswing_in bufgtce_out bufgtcemask_out bufgtdiv_out bufgtreset_out bufgtrstmask_out drpdo_common_out drprdy_common_out gtpowergood_out pcierategen3_out pcierateidle_out pcierateqpllpd_out pcierateqpllreset_out pciesynctxsyncdone_out pcieusergen3rdy_out pcie +userphystatusrst_out pcieuserratestart_out phystatus_out rxelecidle_out rxoutclkfabric_out rxoutclkpcs_out rxprbserr_out rxprbslocked_out rxrecclkout_out rxstatus_out rxvalid_out txoutclkfabric_out txoutclkpcs_out qpll1freqlock_in qpll0freqlock_in cpllfreqlock_in qpll0lock_out qpll1lock_out drpclk_in cpllreset_in qpll1outclk_out qpll1outrefclk_out qpll0outclk_out qpll0outrefclk_out pcierateqpll0_in pcierateqpll1_in gtrefclk00_in gtrefclk01_in qpll0reset_in qpll1reset_in drpwe_in drpaddr_in drpen +_in drprst_in drprdy_out drpdi_in drpdo_out rxcdrhold_in rxdfeagchold_in rxdfecfokhold_in rxdfelfhold_in rxdfekhhold_in rxdfetap2hold_in rxdfetap3hold_in rxdfetap4hold_in rxdfetap5hold_in rxdfetap6hold_in rxdfetap7hold_in rxdfetap8hold_in rxdfetap9hold_in rxdfetap10hold_in rxdfetap11hold_in rxdfetap12hold_in rxdfetap13hold_in rxdfetap14hold_in rxdfetap15hold_in rxdfeuthold_in rxdfevphold_in rxoshold_in rxlpmgchold_in rxlpmhfhold_in rxlpmlfhold_in rxlpmoshold_in rxratedone_out rxcdrfreqreset_in r +esetovrd_in txoutclksel_in cplllock_out gtrefclk0_in + + + RX_REFCLK_SOURCE + Receiver reference clock source + Select a reference clock input to drive the PLL chosen for receiver operation + + + + TX_REFCLK_SOURCE + Transmitter reference clock source + Select a reference clock input to drive the PLL chosen for transmitter operation + + + + RX_RECCLK_OUTPUT + Drive recovered clock out of device + Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use + + + + LOCATE_RESET_CONTROLLER + Include reset controller in the + Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + LOCATE_TX_BUFFER_BYPASS_CONTROLLER + Include transmitter buffer bypass controller in the + If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + LOCATE_RX_BUFFER_BYPASS_CONTROLLER + Include receiver elastic buffer bypass controller in the + If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_IN_SYSTEM_IBERT_CORE + Include In-System IBERT core + Indicate whether or not the In-System IBERT core should be instantiated in the example design. + NONE + + + LOCATE_TX_USER_CLOCKING + Include simple transmitter user clocking network in the + Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_RX_USER_CLOCKING + Include simple receiver user clocking network in the + Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_USER_DATA_WIDTH_SIZING + Include user data width sizing in the + Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + EXAMPLE_DESIGN + + + ORGANIZE_PORTS_BY + In the example design, organize ports across multiple channels by + If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) + NAME + + + PRESET + Transceiver configuration preset + You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard + None + + + INTERNAL_PRESET + Transceiver configuration preset + None + + + INTERNAL_PORT_USAGE_UPDATED + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLEMENT_UPDATED + 23 + + + + false + + + + + + INTERNAL_CHANNEL_SITES_UPDATED + 5 + + + + false + + + + + + INTERNAL_CHANNEL_COLUMN_LOC_MAX + 96 + + + + false + + + + + + INTERNAL_RX_COMMA_PRESET_UPDATE + 8 + + + + false + + + + + + INTERNAL_UPDATE_IP_SYMBOL_drpclk_in + true + + + + false + + + + + + SECONDARY_QPLL_ENABLE + Enable secondary QPLL + Enable and configure the QPLL which is not used in this core configuration + false + + + SECONDARY_QPLL_LINE_RATE + Line rate of second core (Gb/s) + Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL + 10.3125 + + + + false + + + + + + SECONDARY_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection + 0 + + + + false + + + + + + SECONDARY_QPLL_REFCLK_FREQUENCY + Actual Reference clock frequency (MHz) + Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate + 257.8125 + + + + false + + + + + + TXPROGDIV_FREQ_ENABLE + Enable selectable TXOUTCLK frequency + Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency + false + + + TXPROGDIV_FREQ_SOURCE + Programmable divider clock source + Select which PLL source is used to generate the selectable TXOUTCLK frequency + QPLL1 + + + + false + + + + + + TXPROGDIV_FREQ_VAL + TXOUTCLK frequency (MHz) + Select the TXOUTCLK frequency to be generated by the TX programmable divider + 400 + + + + false + + + + + + SATA_TX_BURST_LEN + TX COM sequence burst length + Select the number of bursts that make up a SATA COM sequence + 15 + + + FREERUN_FREQUENCY + Free-running and DRP clock frequency (MHz) + Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface + 100 + + + INCLUDE_CPLL_CAL + 1 + + + USER_GTPOWERGOOD_DELAY_EN + Select 1 to enable powergood delay circuit + 1 + + + DISABLE_LOC_XDC + Select to disable generation of LOC constraints in xdc + 0 + + + ENABLE_COMMON_USRCLK + 0 + + + USB_ENABLE + false + + + PCIE_64BIT + false + + + PCIE_GEN4_EIOS + false + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGBYPASSB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGMONITORENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGPDB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK01_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0PD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0RESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1PD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1RESET_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD2_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD3_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD4_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RCALENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0DATA_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0RESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0WIDTH_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1DATA_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1RESET_IN + 0 + + + + false + + + + + + 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false + false + Kilobytes + 128 + N/A + false + false + false + Kilobytes + 128 + N/A + false + false + Kilobytes + 128 + N/A + Simple_communication_controllers + 07 + 01 + 00 + 1024_bytes + false + false + Kilobytes + 2 + true + false + false + true + false + Kilobytes + 2 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + 1 + 16450_compatible_serial_controller + false + false + false + true + false + Kilobytes + 64 + Memory + false + false + false + Kilobytes + 128 + N/A + false + false + false + Kilobytes + 128 + N/A + false + false + false + Kilobytes + 128 + N/A + false + false + false + Kilobytes + 128 + N/A + false + false + Kilobytes + 128 + N/A + Memory_controller + 05 + 00 + 80 + false + Kilobytes + 2 + false + false + false + true + false + Kilobytes + 2 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Other_memory_controller + 10EE + false + true + false + Kilobytes + 64 + Memory + false + false + false + Kilobytes + 128 + N/A + false + false + false + Kilobytes + 128 + N/A + false + false + false + Kilobytes + 128 + N/A + false + false + false + Kilobytes + 128 + N/A + false + false + Kilobytes + 128 + N/A + Memory_controller + 05 + 00 + 80 + false + Kilobytes + 2 + false + false + false + true + false + Kilobytes + 2 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Other_memory_controller + 10EE + false + true + false + Kilobytes + 64 + Memory + false + false + false + Kilobytes + 128 + N/A + false + false + false + Kilobytes + 128 + N/A + false + false + false + Kilobytes + 128 + N/A + false + false + false + Kilobytes + 128 + N/A + false + false + Kilobytes + 128 + N/A + Memory_controller + 05 + 00 + 80 + false + Kilobytes + 2 + false + false + false + true + false + Kilobytes + 2 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Other_memory_controller + 10EE + false + QPLL1 + true + GTY_Quad_227 + false + false + ACTIVE_LOW + 15 + 15 + X8G3 + false + true + Enabled + 64bit_Enabled + 10EE + false + None + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml new file mode 100644 index 0000000..54a9027 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml @@ -0,0 +1,25761 @@ + + + xilinx.com + customized_ip + xdma_pcie4_ip + 1.0 + + + m_axis_cq + m_axis_cq + The Completer Request interface is used to transmit Completion TLP's to the Client Application + + + + + + + TDATA + + + m_axis_cq_tdata + + + + + TKEEP + + + m_axis_cq_tkeep + + + + + TLAST + + + m_axis_cq_tlast + + + + + TREADY + + + m_axis_cq_tready + + + + + TUSER + + + m_axis_cq_tuser + + + + + TVALID + + + m_axis_cq_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 88 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + s_axis_cc + s_axis_cc + The Completer Completion Interface is used to transmit Completion TLP's + + + + + + + TDATA + + + s_axis_cc_tdata + + + + + TKEEP + + + s_axis_cc_tkeep + + + + + TLAST + + + s_axis_cc_tlast + + + + + TREADY + + + s_axis_cc_tready + + + + + TUSER + + + s_axis_cc_tuser + + + + + TVALID + + + s_axis_cc_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 33 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + s_axis_rq + s_axis_rq + The Requestor Request interface received requests TLP's from the Client Application + + + + + + + TDATA + + + s_axis_rq_tdata + + + + + TKEEP + + + s_axis_rq_tkeep + + + + + TLAST + + + s_axis_rq_tlast + + + + + TREADY + + + s_axis_rq_tready + + + + + TUSER + + + s_axis_rq_tuser + + + + + TVALID + + + s_axis_rq_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 62 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + m_axis_rc + m_axis_rc + The Requestor Completer interface transmits completions to the client application + + + + + + + TDATA + + + m_axis_rc_tdata + + + + + TKEEP + + + m_axis_rc_tkeep + + + + + TLAST + + + m_axis_rc_tlast + + + + + TREADY + + + m_axis_rc_tready + + + + + TUSER + + + m_axis_rc_tuser + + + + + TVALID + + + m_axis_rc_tvalid + + + + + + TDATA_NUM_BYTES + 32 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 75 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + RST.sys_rst + RST.sys_rst + sys_rst interface + + + + + + + RST + + + sys_reset + + + + + + BOARD.ASSOCIATED_PARAM + SYS_RST_N_BOARD_INTERFACE + + + + required + + + + + + TYPE + PCIE_PERST + + + POLARITY + ACTIVE_LOW + + + none + + + + + + + pcie4_mgt + pcie_7x_mgt + PCIExpress Serial Link Interface + + + + + + + rxn + + + pci_exp_rxn + + + + + rxp + + + pci_exp_rxp + + + + + txn + + + pci_exp_txn + + + + + txp + + + pci_exp_txp + + + + + + BOARD.ASSOCIATED_PARAM + PCIE_BOARD_INTERFACE + + + + required + + + + + + + + + true + + + + + + pcie4_cfg_fc + pcie_cfg_fc + Configuration Flow Control INTERFACE + + + + + + + CPLD + + + cfg_fc_cpld + + + + + CPLH + + + cfg_fc_cplh + + + + + NPD + + + cfg_fc_npd + + + + + NPH + + + cfg_fc_nph + + + + + PD + + + cfg_fc_pd + + + + + PH + + + cfg_fc_ph + + + + + SEL + + + cfg_fc_sel + + + + + + + true + + + + + + pcie4_cfg_mgmt + pcie4_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr + + + + + BYTE_EN + + + cfg_mgmt_byte_enable + + + + + DEBUG_ACCESS + + + cfg_mgmt_debug_access + + + + + FUNCTION_NUMBER + + + cfg_mgmt_function_number + + + + + READ_DATA + + + cfg_mgmt_read_data + + + + + READ_EN + + + cfg_mgmt_read + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done + + + + + WRITE_DATA + + + cfg_mgmt_write_data + + + + + WRITE_EN + + + cfg_mgmt_write + + + + + + + true + + + + + + pcie4_cfg_pm + pcie4_cfg_pm + PCIE4 Power Management Interface + + + + + + + pm_aspm_l1entry_reject + + + cfg_pm_aspm_l1_entry_reject + + + + + pm_aspm_tx_l0s_entry_disable + + + cfg_pm_aspm_tx_l0s_entry_disable + + + + + + + true + + + + + + pcie4_cfg_msi + pcie4_us_cfg_msi + PCIE MSI interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr + + + + + data + + + cfg_interrupt_msi_data + + + + + enable + + + cfg_interrupt_msi_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msi_int + + + + + mask_update + + + cfg_interrupt_msi_mask_update + + + + + mmenable + + + cfg_interrupt_msi_mmenable + + + + + pending_status + + + cfg_interrupt_msi_pending_status + + + + + pending_status_data_enable + + + cfg_interrupt_msi_pending_status_data_enable + + + + + pending_status_function_num + + + cfg_interrupt_msi_pending_status_function_num + + + + + select + + + cfg_interrupt_msi_select + + + + + sent + + + cfg_interrupt_msi_sent + + + + + tph_present + + + cfg_interrupt_msi_tph_present + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag + + + + + tph_type + + + cfg_interrupt_msi_tph_type + + + + + + + true + + + + + + pcie4_cfg_msix_internal + pcie4_cfg_msix_internal + PCIE MSIx Int Interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr + + + + + enable + + + cfg_interrupt_msix_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + mint_vector + + + cfg_interrupt_msi_int + + + + + sent + + + cfg_interrupt_msi_sent + + + + + tph_present + + + cfg_interrupt_msi_tph_present + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag + + + + + tph_type + + + cfg_interrupt_msi_tph_type + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_external_msix + pcie4_cfg_external_msix + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address + + + + + data + + + cfg_interrupt_msix_data + + + + + enable + + + cfg_interrupt_msix_enable + + + + + fail + + + cfg_interrupt_msi_fail + + + + + function_number + + + cfg_interrupt_msi_function_number + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + sent + + + cfg_interrupt_msi_sent + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_msix_external + pcie4_cfg_msix_external + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address + + + + + data + + + cfg_interrupt_msix_data + + + + + enable + + + cfg_interrupt_msix_enable + + + + + int_vector + + + cfg_interrupt_msix_int + + + + + mask + + + cfg_interrupt_msix_mask + + + + + vec_pending + + + cfg_interrupt_msix_vec_pending + + + + + vec_pending_status + + + cfg_interrupt_msix_vec_pending_status + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask + + + + + + + false + + + + + + pcie4_cfg_interrupt + pcie4_cfg_interrupt + PCIE Legacy Interrupt + + + + + + + INTx_VECTOR + + + cfg_interrupt_int + + + + + PENDING + + + cfg_interrupt_pending + + + + + SENT + + + cfg_interrupt_sent + + + + + + pcie4_cfg_ext + pcie4_us_cfg_ext + Configuration Extend Interface + + + + + + + function_number + + + cfg_ext_function_number + + + + + read_data + + + cfg_ext_read_data + + + + + read_data_valid + + + cfg_ext_read_data_valid + + + + + read_received + + + cfg_ext_read_received + + + + + register_number + + + cfg_ext_register_number + + + + + write_byte_enable + + + cfg_ext_write_byte_enable + + + + + write_data + + + cfg_ext_write_data + + + + + write_received + + + cfg_ext_write_received + + + + + + + false + + + + + + pcie4_cfg_mesg_tx + pcie4_us_cfg_mesg_tx + Configuration Transmit Message Interface + + + + + + + TRANSMIT + + + cfg_msg_transmit + + + + + TRANSMIT_DATA + + + cfg_msg_transmit_data + + + + + TRANSMIT_DONE + + + cfg_msg_transmit_done + + + + + TRANSMIT_TYPE + + + cfg_msg_transmit_type + + + + + + + true + + + + + + pcie4_cfg_mesg_rcvd + pcie4_us_cfg_mesg_rcvd + Configuration Received Message Interface + + + + + + + recd + + + cfg_msg_received + + + + + recd_data + + + cfg_msg_received_data + + + + + recd_type + + + cfg_msg_received_type + + + + + + + true + + + + + + pcie4_cfg_control + pcie4_us_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + bus_number + + + cfg_bus_number + + + + + config_space_enable + + + cfg_config_space_enable + + + + + ds_bus_number + + + cfg_ds_bus_number + + + + + ds_device_number + + + cfg_ds_device_number + + + + + ds_port_number + + + cfg_ds_port_number + + + + + dsn + + + cfg_dsn + + + + + err_cor_in + + + cfg_err_cor_in + + + + + err_uncor_in + + + cfg_err_uncor_in + + + + + flr_done + + + cfg_flr_done + + + + + flr_in_process + + + cfg_flr_in_process + + + + + hot_reset_in + + + cfg_hot_reset_in + + + + + hot_reset_out + + + cfg_hot_reset_out + + + + + link_training_enable + + + cfg_link_training_enable + + + + + power_state_change_ack + + + cfg_power_state_change_ack + + + + + power_state_change_interrupt + + + cfg_power_state_change_interrupt + + + + + req_pm_transition_l23_ready + + + cfg_req_pm_transition_l23_ready + + + + + vf_flr_done + + + cfg_vf_flr_done + + + + + vf_flr_func_num + + + cfg_vf_flr_func_num + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process + + + + + + + true + + + + + + pcie4_pcie_id + pcie4_pcie_id + PCIE 4 PCIE ID interface + + + + + + + subsys_vend_id + + + cfg_subsys_vend_id + + + + + vend_id + + + cfg_vend_id + + + + + + + false + + + + + + pcie4_pcie_id_pf0 + pcie4_pcie_id_pf0 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf0 + + + cfg_dev_id_pf0 + + + + + rev_id_pf0 + + + cfg_rev_id_pf0 + + + + + subsys_id_pf0 + + + cfg_subsys_id_pf0 + + + + + + + false + + + + + + pcie4_pcie_id_pf1 + pcie4_pcie_id_pf1 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf1 + + + cfg_dev_id_pf1 + + + + + rev_id_pf1 + + + cfg_rev_id_pf1 + + + + + subsys_id_pf1 + + + cfg_subsys_id_pf1 + + + + + + + false + + + + + + pcie4_pcie_id_pf2 + pcie4_pcie_id_pf2 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf2 + + + cfg_dev_id_pf2 + + + + + rev_id_pf2 + + + cfg_rev_id_pf2 + + + + + subsys_id_pf2 + + + cfg_subsys_id_pf2 + + + + + + + false + + + + + + pcie4_pcie_id_pf3 + pcie4_pcie_id_pf3 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf3 + + + cfg_dev_id_pf3 + + + + + rev_id_pf3 + + + cfg_rev_id_pf3 + + + + + subsys_id_pf3 + + + cfg_subsys_id_pf3 + + + + + + + false + + + + + + pcie4_cfg_status + pcie4_us_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req + + + + + cq_np_req_count + + + pcie_cq_np_req_count + + + + + current_speed + + + cfg_current_speed + + + + + err_cor_out + + + cfg_err_cor_out + + + + + err_fatal_out + + + cfg_err_fatal_out + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out + + + + + function_power_state + + + cfg_function_power_state + + + + + function_status + + + cfg_function_status + + + + + link_power_state + + + cfg_link_power_state + + + + + local_error_out + + + cfg_local_error_out + + + + + local_error_valid + + + cfg_local_error_valid + + + + + ltssm_state + + + cfg_ltssm_state + + + + + max_payload + + + cfg_max_payload + + + + + max_read_req + + + cfg_max_read_req + + + + + negotiated_width + + + cfg_negotiated_width + + + + + obff_enable + + + cfg_obff_enable + + + + + phy_link_down + + + cfg_phy_link_down + + + + + phy_link_status + + + cfg_phy_link_status + + + + + pl_status_change + + + cfg_pl_status_change + + + + + rcb_status + + + cfg_rcb_status + + + + + rq_seq_num0 + + + pcie_rq_seq_num0 + + + + + rq_seq_num1 + + + pcie_rq_seq_num1 + + + + + rq_seq_num_vld0 + + + pcie_rq_seq_num_vld0 + + + + + rq_seq_num_vld1 + + + pcie_rq_seq_num_vld1 + + + + + rq_tag0 + + + pcie_rq_tag0 + + + + + rq_tag1 + + + pcie_rq_tag1 + + + + + rq_tag_av + + + pcie_rq_tag_av + + + + + rq_tag_vld0 + + + pcie_rq_tag_vld0 + + + + + rq_tag_vld1 + + + pcie_rq_tag_vld1 + + + + + rx_pm_state + + + cfg_rx_pm_state + + + + + tph_requester_enable + + + cfg_tph_requester_enable + + + + + tph_st_mode + + + cfg_tph_st_mode + + + + + tx_pm_state + + + cfg_tx_pm_state + + + + + vf_power_state + + + cfg_vf_power_state + + + + + vf_status + + + cfg_vf_status + + + + + vf_tph_requester_enable + + + cfg_vf_tph_requester_enable + + + + + vf_tph_st_mode + + + cfg_vf_tph_st_mode + + + + + + + true + + + + + + pcie4_transmit_fc + pcie4_us_transmit_fc + Transmit Flow Control Interfce + + + + + + + npd_av + + + pcie_tfc_npd_av + + + + + nph_av + + + pcie_tfc_nph_av + + + + + + + true + + + + + + pcie4_drp + pcie4_us_drp + PCIE DRP Interface + + + + + + + DADDR + + + drp_addr + + + + + DEN + + + drp_en + + + + + DI + + + drp_di + + + + + DO + + + drp_do + + + + + DRDY + + + drp_rdy + + + + + DWE + + + drp_we + + + + + + + false + + + + + + CLK.sys_clk + CLK.sys_clk + sys_clk interface + + + + + + + CLK + + + sys_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + CLK.sys_clk_gt + CLK.sys_clk_gt + sys_clk_gt interface + + + + + + + CLK + + + sys_clk_gt + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + 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ext_qpll0lock_out + + + + + exts_qpll0outclk_out + + + ext_qpll0outclk_out + + + + + exts_qpll0outrefclk_out + + + ext_qpll0outrefclk_out + + + + + exts_qpll0pd + + + ext_qpll0pd + + + + + exts_qpll0reset + + + ext_qpll0reset + + + + + exts_qpll1lock_out + + + ext_qpll1lock_out + + + + + exts_qpll1outclk_out + + + ext_qpll1outclk_out + + + + + exts_qpll1outrefclk_out + + + ext_qpll1outrefclk_out + + + + + exts_qpll1pd + + + ext_qpll1pd + + + + + exts_qpll1reset + + + ext_qpll1reset + + + + + exts_qpllxrate + + + ext_qpllxrate + + + + + exts_qpllxrcalenb + + + ext_qpllxrcalenb + + + + + exts_qpllxrefclk + + + ext_qpllxrefclk + + + + + + + false + + + + + + pcie4_usp_int_gtcom + pcie4_usp_int_gtcommon + PCIE4 Ultrascale+ Internal GT COMMON Interface + + + + + + + ints_qpll0lock_out + + + int_qpll0lock_out + + + + + ints_qpll0outclk_out + + + int_qpll0outclk_out + + + + + ints_qpll0outrefclk_out + + + int_qpll0outrefclk_out + + + + + ints_qpll1lock_out + + + int_qpll1lock_out + + + + + ints_qpll1outclk_out + + + int_qpll1outclk_out + + + + + ints_qpll1outrefclk_out + + + int_qpll1outrefclk_out + + + + + + + false + + + + + + pcie_ext_ch_gt + pcie_ext_ch_gt + channel DRP signals + + + + + + + DADDR + + + ext_ch_gt_drpaddr + + + + + DEN + + + ext_ch_gt_drpen + + + + + DI + + + ext_ch_gt_drpdi + + + + + DO + + + ext_ch_gt_drpdo + + + + + DRDY + + + ext_ch_gt_drprdy + + + + + DWE + + + ext_ch_gt_drpwe + + + + + + + false + + + + + + transceiver_debug + transceiver_debug + Transceiver Debug Interface + + + + + + + bufgtdiv + + + gt_bufgtdiv + + + + + cpll_lock + + + gt_cplllock + + + + + dmonfiforeset + + + gt_dmonfiforeset + + + + + dmonitorclk + + + gt_dmonitorclk + + + + + dmonitorout + + + gt_dmonitorout + + + + + eyescandataerror + + + gt_eyescandataerror + + + + + gen34_eios_det + + + gt_gen34_eios_det + + + + + gtpowergood + + + gt_gtpowergood + + + + + loopback + + + gt_loopback + + + + + pcieuserratedone + + + gt_pcieuserratedone + + + + + pcieuserratestart + + + gt_pcieuserratestart + + + + + phystatus + + + gt_phystatus + + + + + prst_n + + + phy_prst_n + + + + + qpll0_lock + + + gt_qpll0lock + + + + + qpll1_lock + + + gt_qpll1lock + + + + + rate_idle + + + gt_pcierateidle + + + + + rrst_n + + + phy_rrst_n + + + + + rst_fsm + + + phy_rst_fsm + + + + + rst_idle + + + phy_rst_idle + + + + + rxbufreset + + + gt_rxbufreset + + + + + rxbufstatus + + + gt_rxbufstatus + + + + + rxcdrlock + + + gt_rxcdrlock + + + + + rxcdrreset + + + gt_rxcdrreset + + + + + rxcommadet + + + gt_rxcommadet + + + + + rxdfelpmreset + + + gt_rxdfelpmreset + + + + + rxdlysresetdone + + + gt_rxdlysresetdone + + + + + rxeq_fsm + + + phy_rxeq_fsm + + + + + rxoutclk + + + gt_rxoutclk + + + + + rxoutclkfabric + + + gt_rxoutclkfabric + + + + + rxoutclkpcs + + + gt_rxoutclkpcs + + + + + rxpcsreset + + + gt_rxpcsreset + + + + + rxphaligndone + + + gt_rxphaligndone + + + + + rxpmareset + + + gt_rxpmareset + + + + + rxpmaresetdone + + + gt_rxpmaresetdone + + + + + rxprbscntreset + + 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drprdy_out + + + + + drprst_in + + + drprst_in + + + + + drpwe_in + + + drpwe_in + + + + + ext_phy_clk_bufg_gt_ce + + + ext_phy_clk_bufg_gt_ce + + + + + ext_phy_clk_bufg_gt_reset + + + ext_phy_clk_bufg_gt_reset + + + + + ext_phy_clk_bufgtcemask + + + ext_phy_clk_bufgtcemask + + + + + ext_phy_clk_bufgtdiv + + + ext_phy_clk_bufgtdiv + + + + + ext_phy_clk_gt_bufgtrstmask + + + ext_phy_clk_gt_bufgtrstmask + + + + + ext_phy_clk_int_clock + + + ext_phy_clk_int_clock + + + + + ext_phy_clk_pclk + + + ext_phy_clk_pclk + + + + + ext_phy_clk_pclk2_gt + + + ext_phy_clk_pclk2_gt + + + + + ext_phy_clk_phy_coreclk + + + ext_phy_clk_phy_coreclk + + + + + ext_phy_clk_phy_mcapclk + + + ext_phy_clk_phy_mcapclk + + + + + ext_phy_clk_phy_pclk2 + + + ext_phy_clk_phy_pclk2 + + + + + ext_phy_clk_phy_userclk + + + ext_phy_clk_phy_userclk + + + + + ext_phy_clk_rst_idle + + + ext_phy_clk_rst_idle + + + + + ext_phy_clk_txoutclk + + + ext_phy_clk_txoutclk + + + + + eyescanreset_in + + + eyescanreset_in + + + + + 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Enable + FALSE + + + PF0_ARI_CAP_NEXT_FUNC + Pf0 ARI Cap Next Func + 0x00 + + + PF1_ARI_CAP_NEXT_FUNC + Pf1 ARI Cap Next Func + 0x00 + + + PF2_ARI_CAP_NEXT_FUNC + Pf2 ARI Cap Next Func + 0x00 + + + PF3_ARI_CAP_NEXT_FUNC + Pf3 ARI Cap Next Func + 0x00 + + + AXISTEN_IF_CC_ALIGNMENT_MODE + Axisten If Cc Alignment Mode + 0x1 + + + AXISTEN_IF_CQ_ALIGNMENT_MODE + Axisten If Cq Alignment Mode + 0x1 + + + AXISTEN_IF_RC_ALIGNMENT_MODE + Axisten If Rc Alignment Mode + 0x0 + + + AXISTEN_IF_RQ_ALIGNMENT_MODE + Axisten If Rq Alignment Mode + 0x0 + + + AXISTEN_IF_EXT_512_CQ_STRADDLE + Axisten If CQ Straddle + FALSE + + + AXISTEN_IF_EXT_512_CC_STRADDLE + Axisten If CC Straddle + FALSE + + + AXISTEN_IF_EXT_512_RQ_STRADDLE + Axisten If RQ Straddle + FALSE + + + AXISTEN_IF_EXT_512_RC_STRADDLE + Axisten If RC Straddle + FALSE + + + AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE + Axisten If 512 4TLP/2TLP Rc Straddle + FALSE + + + AXISTEN_IF_RC_STRADDLE + Axisten If Rc Straddle + TRUE + + + PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE + Pf0 Aer Cap Ecrc Gen and Check Capable + FALSE + + + PF0_AER_CAP_NEXTPTR + Pf0 Aer Cap Nextptr + 0x1C0 + + + PF0_ARI_CAP_NEXTPTR + Pf0 Ari Cap Nextptr + 0x1C0 + + + PF0_BAR0_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x009 + + + PF0_BAR0_CONTROL + Pf0 Bar0 Control + 0x4 + + + PF0_BAR1_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x000 + + + PF0_BAR1_CONTROL + Pf0 Bar1 Control + 0x0 + + + PF0_BAR2_APERTURE_SIZE + Pf0 Bar2 Aperture Size + 0x000 + + + PF0_BAR2_CONTROL + Pf0 Bar2 Control + 0x0 + + + PF0_BAR3_APERTURE_SIZE + Pf0 Bar3 Aperture Size + 0x000 + + + PF0_BAR3_CONTROL + Pf0 Bar3 Control + 0x0 + + + PF0_BAR4_APERTURE_SIZE + Pf0 Bar4 Aperture Size + 0x000 + + + PF0_BAR4_CONTROL + Pf0 Bar4 Control + 0x0 + + + PF0_BAR5_APERTURE_SIZE + Pf0 Bar5 Aperture Size + 0x000 + + + PF0_BAR5_CONTROL + Pf0 Bar5 Control + 0x0 + + + PF0_CAPABILITY_POINTER + Pf0 Capability Pointer + 0x40 + + + PF0_CLASS_CODE + Pf0 Class Code + 0x070001 + + + PF0_VENDOR_ID + Pf0 Vendor Id + 0x10EE + + + PF0_DEVICE_ID + Pf0 Device Id + 0x9038 + + + PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 128b Cas Atomic Completer Support + FALSE + + + PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 32b Atomic Completer Support + FALSE + + + PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 64b Atomic Completer Support + FALSE + + + PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT + Pf0 Dev Cap2 Tph Completer Support + FALSE + + + PF0_DEV_CAP_EXT_TAG_SUPPORTED + Pf0 Dev Cap Ext Tag Supported + TRUE + + + PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE + Pf0 Dev Cap Function Level Reset Capable + FALSE + + + PF0_DEV_CAP_MAX_PAYLOAD_SIZE + Pf0 Dev Cap Max Payload Size + 0x3 + + + DSN_CAP_ENABLE + Dsn Cap Enable + FALSE + + + PF0_VC_CAP_ENABLE + Vc Cap Enable + FALSE + + + PF0_DSN_CAP_NEXTPTR + Pf0 Dsn Cap Nextptr + 0x1C0 + + + PF0_EXPANSION_ROM_APERTURE_SIZE + Pf0 Expansion Rom Aperture Size + 0x000 + + + PF0_EXPANSION_ROM_ENABLE + Pf0 Expansion Rom Enable + FALSE + + + PF0_INTERRUPT_PIN + Pf0 Interrupt Pin + 0x1 + + + PF0_LINK_STATUS_SLOT_CLOCK_CONFIG + Pf0 Link Status Slot Clock Config + TRUE + + + PF0_MSIX_CAP_NEXTPTR + Pf0 Msix Cap Nextptr + 0x70 + + + PF0_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + PF0_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + PF0_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + PF0_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + PF0_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + PF0_MSI_CAP_MULTIMSGCAP + Pf0 Msi Cap Multimsgcap + 0 + + + PF0_MSI_CAP_NEXTPTR + Pf0 Msi Cap Nextptr + 0x70 + + + PF0_PM_CAP_NEXTPTR + Pf0 Pm Cap Nextptr + 0x48 + + + PF0_PM_CAP_PMESUPPORT_D0 + Pf0 Pm Cap Pmesupport D0 + FALSE + + + PF0_PM_CAP_PMESUPPORT_D1 + Pf0 Pm Cap Pmesupport D1 + FALSE + + + PF0_PM_CAP_PMESUPPORT_D3HOT + Pf0 Pm Cap Pmesupport D3hot + FALSE + + + PF0_PM_CAP_SUPP_D1_STATE + Pf0 Pm Cap Supp D1 State + FALSE + + + PF0_REVISION_ID + Pf0 Revision Id + 0x00 + + + PF0_SRIOV_BAR0_APERTURE_SIZE + Pf0 Sriov Bar0 Aperture Size + 0x00 + + + PF0_SRIOV_BAR0_CONTROL + Pf0 Sriov Bar0 Control + 0x0 + + + PF0_SRIOV_BAR1_APERTURE_SIZE + Pf0 Sriov Bar1 Aperture Size + 0x00 + + + PF0_SRIOV_BAR1_CONTROL + Pf0 Sriov Bar1 Control + 0x0 + + + PF0_SRIOV_BAR2_APERTURE_SIZE + Pf0 Sriov Bar2 Aperture Size + 0x00 + + + PF0_SRIOV_BAR2_CONTROL + Pf0 Sriov Bar2 Control + 0x0 + + + PF0_SRIOV_BAR3_APERTURE_SIZE + Pf0 Sriov Bar3 Aperture Size + 0x00 + + + PF0_SRIOV_BAR3_CONTROL + Pf0 Sriov Bar3 Control + 0x0 + + + PF0_SRIOV_BAR4_APERTURE_SIZE + Pf0 Sriov Bar4 Aperture Size + 0x00 + + + PF0_SRIOV_BAR4_CONTROL + Pf0 Sriov Bar4 Control + 0x0 + + + PF0_SRIOV_BAR5_APERTURE_SIZE + Pf0 Sriov Bar5 Aperture Size + 0x00 + + + PF0_SRIOV_BAR5_CONTROL + Pf0 Sriov Bar5 Control + 0x0 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0x0000 + + + PF0_SRIOV_CAP_NEXTPTR + Pf0 Sriov Cap Nextptr + 0x000 + + + PF0_SRIOV_CAP_TOTAL_VF + Pf0 Sriov Cap Total Vf + 0x0000 + + + PF0_SRIOV_CAP_VER + Pf0 Sriov Cap Ver + 0x1 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 0x0000 + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0x0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 0x00000553 + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0x0000 + + + PF0_SUBSYSTEM_VENDOR_ID + Pf0 Subsystem Vendor Id + 0x10EE + + + PF0_SUBSYSTEM_ID + Pf0 Subsystem Id + 0x0007 + + + PF0_TPHR_CAP_ENABLE + Pf0 Tphr Cap Enable + FALSE + + + PF0_TPHR_CAP_NEXTPTR + Pf0 Tphr Cap Nextptr + 0x000 + + + PF0_TPHR_CAP_ST_MODE_SEL + Pf0 Tphr Cap St Mode Sel + 0x0 + + + PF0_TPHR_CAP_ST_TABLE_LOC + Pf0 Tphr Cap St Table Loc + 0x0 + + + PF0_TPHR_CAP_ST_TABLE_SIZE + Pf0 Tphr Cap St Table Size + 0x000 + + + PF0_TPHR_CAP_VER + Pf0 Tphr Cap Ver + 0x1 + + + PF1_TPHR_CAP_ST_MODE_SEL + Pf1 Tphr Cap St Mode Sel + 0x0 + + + PF2_TPHR_CAP_ST_MODE_SEL + Pf2 Tphr Cap St Mode Sel + 0x0 + + + PF3_TPHR_CAP_ST_MODE_SEL + Pf3 Tphr Cap St Mode Sel + 0x0 + + + PF0_TPHR_CAP_DEV_SPECIFIC_MODE + Pf0 Tphr Cap Dev Specific Mode + TRUE + + + PF0_TPHR_CAP_INT_VEC_MODE + Pf0 Tphr Cap Int Vec Mode + FALSE + + + PF0_SECONDARY_PCIE_CAP_NEXTPTR + Secondary Pcie Extended Capability Nextptr + 0x000 + + + MCAP_CAP_NEXTPTR + MCAP Cap Nextptr + 0x000 + + + PF0_VC_CAP_NEXTPTR + Pf0 Vc Cap Nextptr + 0x000 + + + SPARE_WORD1 + Secondary Pcie Extended Capability Nextptr + 0x00000000 + + + PF1_AER_CAP_NEXTPTR + Pf1 Aer Cap Nextptr + 0x000 + + + PF1_ARI_CAP_NEXTPTR + Pf1 Ari Cap Nextptr + 0x000 + + + PF1_BAR0_APERTURE_SIZE + Pf1 Bar0 Aperture Size + 0x009 + + + PF1_BAR0_CONTROL + Pf1 Bar0 Control + 0x4 + + + PF1_BAR1_APERTURE_SIZE + Pf1 Bar1 Aperture Size + 0x000 + + + PF1_BAR1_CONTROL + Pf1 Bar1 Control + 0x0 + + + PF1_BAR2_APERTURE_SIZE + Pf1 Bar2 Aperture Size + 0x000 + + + PF1_BAR2_CONTROL + Pf1 Bar2 Control + 0x0 + + + PF1_BAR3_APERTURE_SIZE + Pf1 Bar3 Aperture Size + 0x000 + + + PF1_BAR3_CONTROL + Pf1 Bar3 Control + 0x0 + + + PF1_BAR4_APERTURE_SIZE + Pf1 Bar4 Aperture Size + 0x000 + + + PF1_BAR4_CONTROL + Pf1 Bar4 Control + 0x0 + + + PF1_BAR5_APERTURE_SIZE + Pf1 Bar5 Aperture Size + 0x000 + + + PF1_BAR5_CONTROL + Pf1 Bar5 Control + 0x0 + + + PF1_CAPABILITY_POINTER + Pf1 Capability Pointer + 0x40 + + + PF1_CLASS_CODE + Pf1 Class Code + 0x058000 + + + PF1_DEVICE_ID + Pf1 Device Id + 0x9011 + + + PF1_DEV_CAP_MAX_PAYLOAD_SIZE + Pf1 Dev Cap Max Payload Size + 0x3 + + + PF1_DSN_CAP_NEXTPTR + Pf1 Dsn Cap Nextptr + 0x000 + + + PF1_EXPANSION_ROM_APERTURE_SIZE + Pf1 Expansion Rom Aperture Size + 0x000 + + + PF1_EXPANSION_ROM_ENABLE + Pf1 Expansion Rom Enable + FALSE + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + 0x0 + + + PF1_MSIX_CAP_NEXTPTR + Pf1 Msix Cap Nextptr + 0x70 + + + PF1_MSIX_CAP_PBA_BIR + Pf1 Msix Cap Pba Bir + 0 + + + PF1_MSIX_CAP_PBA_OFFSET + Pf1 Msix Cap Pba Offset + 0x00000000 + + + PF1_MSIX_CAP_TABLE_BIR + Pf1 Msix Cap Table Bir + 0 + + + PF1_MSIX_CAP_TABLE_OFFSET + Pf1 Msix Cap Table Offset + 0x00000000 + + + PF1_MSIX_CAP_TABLE_SIZE + Pf1 Msix Cap Table Size + 0x000 + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 0 + + + PF1_MSI_CAP_NEXTPTR + Pf1 Msi Cap Nextptr + 0x70 + + + PF1_PM_CAP_NEXTPTR + Pf1 Pm Cap Nextptr + 0x70 + + + PF1_REVISION_ID + Pf1 Revision Id + 0x00 + + + PF1_SRIOV_BAR0_APERTURE_SIZE + Pf1 Sriov Bar0 Aperture Size + 0x00 + + + PF1_SRIOV_BAR0_CONTROL + Pf1 Sriov Bar0 Control + 0x0 + + + PF1_SRIOV_BAR1_APERTURE_SIZE + Pf1 Sriov Bar1 Aperture Size + 0x00 + + + PF1_SRIOV_BAR1_CONTROL + Pf1 Sriov Bar1 Control + 0x0 + + + PF1_SRIOV_BAR2_APERTURE_SIZE + Pf1 Sriov Bar2 Aperture Size + 0x00 + + + PF1_SRIOV_BAR2_CONTROL + Pf1 Sriov Bar2 Control + 0x0 + + + PF1_SRIOV_BAR3_APERTURE_SIZE + Pf1 Sriov Bar3 Aperture Size + 0x00 + + + PF1_SRIOV_BAR3_CONTROL + Pf1 Sriov Bar3 Control + 0x0 + + + PF1_SRIOV_BAR4_APERTURE_SIZE + Pf1 Sriov Bar4 Aperture Size + 0x00 + + + PF1_SRIOV_BAR4_CONTROL + Pf1 Sriov Bar4 Control + 0x0 + + + PF1_SRIOV_BAR5_APERTURE_SIZE + Pf1 Sriov Bar5 Aperture Size + 0x00 + + + PF1_SRIOV_BAR5_CONTROL + Pf1 Sriov Bar5 Control + 0x0 + + + PF1_SRIOV_CAP_INITIAL_VF + Pf1 Sriov Cap Initial Vf + 0x0000 + + + PF1_SRIOV_CAP_NEXTPTR + Pf1 Sriov Cap Nextptr + 0x000 + + + PF1_SRIOV_CAP_TOTAL_VF + Pf1 Sriov Cap Total Vf + 0x0000 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 0x1 + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + 0x0000 + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0x0001 + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 0x00000553 + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0x0000 + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0x0007 + + + PF1_TPHR_CAP_NEXTPTR + Pf1 Tphr Cap Nextptr + 0x000 + + + PF2_AER_CAP_NEXTPTR + Pf2 Aer Cap Nextptr + 0x000 + + + PF2_ARI_CAP_NEXTPTR + Pf2 Ari Cap Nextptr + 0x000 + + + PF2_BAR0_APERTURE_SIZE + Pf2 Bar0 Aperture Size + 0x009 + + + PF2_BAR0_CONTROL + Pf2 Bar0 Control + 0x4 + + + PF2_BAR1_APERTURE_SIZE + Pf2 Bar1 Aperture Size + 0x000 + + + PF2_BAR1_CONTROL + Pf2 Bar1 Control + 0x0 + + + PF2_BAR2_APERTURE_SIZE + Pf2 Bar2 Aperture Size + 0x000 + + + PF2_BAR2_CONTROL + Pf2 Bar2 Control + 0x0 + + + PF2_BAR3_APERTURE_SIZE + Pf2 Bar3 Aperture Size + 0x000 + + + PF2_BAR3_CONTROL + Pf2 Bar3 Control + 0x0 + + + PF2_BAR4_APERTURE_SIZE + Pf2 Bar4 Aperture Size + 0x000 + + + PF2_BAR4_CONTROL + Pf2 Bar4 Control + 0x0 + + + PF2_BAR5_APERTURE_SIZE + Pf2 Bar5 Aperture Size + 0x000 + + + PF2_BAR5_CONTROL + Pf2 Bar5 Control + 0x0 + + + PF2_CAPABILITY_POINTER + Pf2 Capability Pointer + 0x40 + + + PF2_CLASS_CODE + Pf2 Class Code + 0x058000 + + + PF2_DEVICE_ID + Pf2 Device Id + 0x9038 + + + PF2_DEV_CAP_MAX_PAYLOAD_SIZE + Pf2 Dev Cap Max Payload Size + 0x3 + + + PF2_DSN_CAP_NEXTPTR + Pf2 Dsn Cap Nextptr + 0x000 + + + PF2_EXPANSION_ROM_APERTURE_SIZE + Pf2 Expansion Rom Aperture Size + 0x000 + + + PF2_EXPANSION_ROM_ENABLE + Pf2 Expansion Rom Enable + FALSE + + + PF2_INTERRUPT_PIN + Pf2 Interrupt Pin + 0x0 + + + PF2_MSIX_CAP_NEXTPTR + Pf2 Msix Cap Nextptr + 0x70 + + + PF2_MSIX_CAP_PBA_BIR + Pf2 Msix Cap Pba Bir + 0 + + + PF2_MSIX_CAP_PBA_OFFSET + Pf2 Msix Cap Pba Offset + 0x00000000 + + + PF2_MSIX_CAP_TABLE_BIR + Pf2 Msix Cap Table Bir + 0 + + + PF2_MSIX_CAP_TABLE_OFFSET + Pf2 Msix Cap Table Offset + 0x00000000 + + + PF2_MSIX_CAP_TABLE_SIZE + Pf2 Msix Cap Table Size + 0x000 + + + PF2_MSI_CAP_MULTIMSGCAP + Pf2 Msi Cap Multimsgcap + 0 + + + PF2_MSI_CAP_NEXTPTR + Pf2 Msi Cap Nextptr + 0x70 + + + PF2_PM_CAP_NEXTPTR + Pf2 Pm Cap Nextptr + 0x70 + + + PF2_REVISION_ID + Pf2 Revision Id + 0x00 + + + PF2_SRIOV_BAR0_APERTURE_SIZE + Pf2 Sriov Bar0 Aperture Size + 0x00 + + + PF2_SRIOV_BAR0_CONTROL + Pf2 Sriov Bar0 Control + 0x0 + + + PF2_SRIOV_BAR1_APERTURE_SIZE + Pf2 Sriov Bar1 Aperture Size + 0x00 + + + PF2_SRIOV_BAR1_CONTROL + Pf2 Sriov Bar1 Control + 0x0 + + + PF2_SRIOV_BAR2_APERTURE_SIZE + Pf2 Sriov Bar2 Aperture Size + 0x00 + + + PF2_SRIOV_BAR2_CONTROL + Pf2 Sriov Bar2 Control + 0x0 + + + PF2_SRIOV_BAR3_APERTURE_SIZE + Pf2 Sriov Bar3 Aperture Size + 0x00 + + + PF2_SRIOV_BAR3_CONTROL + Pf2 Sriov Bar3 Control + 0x0 + + + PF2_SRIOV_BAR4_APERTURE_SIZE + Pf2 Sriov Bar4 Aperture Size + 0x00 + + + PF2_SRIOV_BAR4_CONTROL + Pf2 Sriov Bar4 Control + 0x0 + + + PF2_SRIOV_BAR5_APERTURE_SIZE + Pf2 Sriov Bar5 Aperture Size + 0x00 + + + PF2_SRIOV_BAR5_CONTROL + Pf2 Sriov Bar5 Control + 0x0 + + + PF2_SRIOV_CAP_INITIAL_VF + Pf2 Sriov Cap Initial Vf + 0x0000 + + + PF2_SRIOV_CAP_NEXTPTR + Pf2 Sriov Cap Nextptr + 0x000 + + + PF2_SRIOV_CAP_TOTAL_VF + Pf2 Sriov Cap Total Vf + 0x0000 + + + PF2_SRIOV_CAP_VER + Pf2 Sriov Cap Ver + 0x1 + + + PF2_SRIOV_FIRST_VF_OFFSET + Pf2 Sriov First Vf Offset + 0x0000 + + + PF2_SRIOV_FUNC_DEP_LINK + Pf2 Sriov Func Dep Link + 0x0002 + + + PF2_SRIOV_SUPPORTED_PAGE_SIZE + Pf2 Sriov Supported Page Size + 0x00000553 + + + PF2_SRIOV_VF_DEVICE_ID + Pf2 Sriov Vf Device Id + 0x0000 + + + PF2_SUBSYSTEM_ID + Pf2 Subsystem Id + 0x0007 + + + PF2_TPHR_CAP_NEXTPTR + Pf2 Tphr Cap Nextptr + 0x000 + + + PF3_AER_CAP_NEXTPTR + Pf3 Aer Cap Nextptr + 0x000 + + + PF3_ARI_CAP_NEXTPTR + Pf3 Ari Cap Nextptr + 0x000 + + + PF3_BAR0_APERTURE_SIZE + Pf3 Bar0 Aperture Size + 0x009 + + + PF3_BAR0_CONTROL + Pf3 Bar0 Control + 0x4 + + + PF3_BAR1_APERTURE_SIZE + Pf3 Bar1 Aperture Size + 0x000 + + + PF3_BAR1_CONTROL + Pf3 Bar1 Control + 0x0 + + + PF3_BAR2_APERTURE_SIZE + Pf3 Bar2 Aperture Size + 0x000 + + + PF3_BAR2_CONTROL + Pf3 Bar2 Control + 0x0 + + + PF3_BAR3_APERTURE_SIZE + Pf3 Bar3 Aperture Size + 0x000 + + + PF3_BAR3_CONTROL + Pf3 Bar3 Control + 0x0 + + + PF3_BAR4_APERTURE_SIZE + Pf3 Bar4 Aperture Size + 0x000 + + + PF3_BAR4_CONTROL + Pf3 Bar4 Control + 0x0 + + + PF3_BAR5_APERTURE_SIZE + Pf3 Bar5 Aperture Size + 0x000 + + + PF3_BAR5_CONTROL + Pf3 Bar5 Control + 0x0 + + + PF3_CAPABILITY_POINTER + Pf3 Capability Pointer + 0x40 + + + PF3_CLASS_CODE + Pf3 Class Code + 0x058000 + + + PF3_DEVICE_ID + Pf3 Device Id + 0x9038 + + + PF3_DEV_CAP_MAX_PAYLOAD_SIZE + Pf3 Dev Cap Max Payload Size + 0x3 + + + PF3_DSN_CAP_NEXTPTR + Pf3 Dsn Cap Nextptr + 0x000 + + + PF3_EXPANSION_ROM_APERTURE_SIZE + Pf3 Expansion Rom Aperture Size + 0x000 + + + PF3_EXPANSION_ROM_ENABLE + Pf3 Expansion Rom Enable + FALSE + + + PF3_INTERRUPT_PIN + Pf3 Interrupt Pin + 0x0 + + + PF3_MSIX_CAP_NEXTPTR + Pf3 Msix Cap Nextptr + 0x70 + + + PF3_MSIX_CAP_PBA_BIR + Pf3 Msix Cap Pba Bir + 0 + + + PF3_MSIX_CAP_PBA_OFFSET + Pf3 Msix Cap Pba Offset + 0x00000000 + + + PF3_MSIX_CAP_TABLE_BIR + Pf3 Msix Cap Table Bir + 0 + + + PF3_MSIX_CAP_TABLE_OFFSET + Pf3 Msix Cap Table Offset + 0x00000000 + + + PF3_MSIX_CAP_TABLE_SIZE + Pf3 Msix Cap Table Size + 0x000 + + + PF3_MSI_CAP_MULTIMSGCAP + Pf3 Msi Cap Multimsgcap + 0 + + + PF3_MSI_CAP_NEXTPTR + Pf3 Msi Cap Nextptr + 0x70 + + + PF3_PM_CAP_NEXTPTR + Pf3 Pm Cap Nextptr + 0x70 + + + PF3_REVISION_ID + Pf3 Revision Id + 0x00 + + + PF3_SRIOV_BAR0_APERTURE_SIZE + Pf3 Sriov Bar0 Aperture Size + 0x00 + + + PF3_SRIOV_BAR0_CONTROL + Pf3 Sriov Bar0 Control + 0x0 + + + PF3_SRIOV_BAR1_APERTURE_SIZE + Pf3 Sriov Bar1 Aperture Size + 0x00 + + + PF3_SRIOV_BAR1_CONTROL + Pf3 Sriov Bar1 Control + 0x0 + + + PF3_SRIOV_BAR2_APERTURE_SIZE + Pf3 Sriov Bar2 Aperture Size + 0x00 + + + PF3_SRIOV_BAR2_CONTROL + Pf3 Sriov Bar2 Control + 0x0 + + + PF3_SRIOV_BAR3_APERTURE_SIZE + Pf3 Sriov Bar3 Aperture Size + 0x00 + + + PF3_SRIOV_BAR3_CONTROL + Pf3 Sriov Bar3 Control + 0x0 + + + PF3_SRIOV_BAR4_APERTURE_SIZE + Pf3 Sriov Bar4 Aperture Size + 0x00 + + + PF3_SRIOV_BAR4_CONTROL + Pf3 Sriov Bar4 Control + 0x0 + + + PF3_SRIOV_BAR5_APERTURE_SIZE + Pf3 Sriov Bar5 Aperture Size + 0x00 + + + PF3_SRIOV_BAR5_CONTROL + Pf3 Sriov Bar5 Control + 0x0 + + + PF3_SRIOV_CAP_INITIAL_VF + Pf3 Sriov Cap Initial Vf + 0x0000 + + + PF3_SRIOV_CAP_NEXTPTR + Pf3 Sriov Cap Nextptr + 0x000 + + + PF3_SRIOV_CAP_TOTAL_VF + Pf3 Sriov Cap Total Vf + 0x0000 + + + PF3_SRIOV_CAP_VER + Pf3 Sriov Cap Ver + 0x1 + + + PF3_SRIOV_FIRST_VF_OFFSET + Pf3 Sriov First Vf Offset + 0x0000 + + + PF3_SRIOV_FUNC_DEP_LINK + Pf3 Sriov Func Dep Link + 0x0003 + + + PF3_SRIOV_SUPPORTED_PAGE_SIZE + Pf3 Sriov Supported Page Size + 0x00000553 + + + PF3_SRIOV_VF_DEVICE_ID + Pf3 Sriov Vf Device Id + 0x0000 + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0x0007 + + + PF3_TPHR_CAP_NEXTPTR + Pf3 Tphr Cap Nextptr + 0x000 + + + PL_UPSTREAM_FACING + Pl Upstream Facing + TRUE + + + PL_DISABLE_LANE_REVERSAL + Pl Disable Lane Reversal + TRUE + + + PF0_MSI_CAP_PERVECMASKCAP + en pf0 msi per vec masking + FALSE + + + PF1_MSI_CAP_PERVECMASKCAP + en pf1 msi per vec masking + FALSE + + + PF2_MSI_CAP_PERVECMASKCAP + en pf2 msi per vec masking + FALSE + + + PF3_MSI_CAP_PERVECMASKCAP + en pf3 msi per vec masking + FALSE + + + SRIOV_CAP_ENABLE + Sriov Cap Enable + 0x1 + + + TL_CREDITS_CD + Tl Credits Cd + 0x000 + + + TL_CREDITS_CH + Tl Credits Ch + 0x00 + + + TL_CREDITS_NPD + Tl Credits Npd + 0x004 + + + TL_CREDITS_NPH + Tl Credits Nph + 0x20 + + + TL_CREDITS_PD + Tl Credits Pd + 0x3E0 + + + TL_CREDITS_PH + Tl Credits Ph + 0x20 + + + EXTENDED_CFG_EXTEND_INTERFACE_ENABLE + Tl Extended Cfg Extend Interface Enable + FALSE + + + EXT_XVC_VSEC_ENABLE + Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design + FALSE + + + LEGACY_CFG_EXTEND_INTERFACE_ENABLE + FALSE + + + ACS_EXT_CAP_ENABLE + FALSE + + + ACS_CAP_NEXTPTR + 0x000 + + + TL_LEGACY_MODE_ENABLE + Tl Legacy Mode Enable + FALSE + + + TL_PF_ENABLE_REG + 0 + + + VF0_CAPABILITY_POINTER + Vf0 Capability Pointer + 0x70 + + + TL_COMPLETION_RAM_SIZE + Completion Space + 0x2 + + + gen_x0y0_xdc + Generate X0Y0 XDC + 0 + + + gen_x0y1_xdc + Generate X0Y1 XDC + 0 + + + gen_x0y2_xdc + Generate X0Y2 XDC + 0 + + + gen_x0y3_xdc + Generate X0Y3 XDC + 0 + + + gen_x0y4_xdc + Generate X0Y4 XDC + 0 + + + gen_x0y5_xdc + Generate X0Y5 XDC + 0 + + + gen_x1y0_xdc + Generate X1Y0 XDC + 0 + + + gen_x1y1_xdc + Generate X1Y1 XDC + 0 + + + gen_x1y2_xdc + Generate X1Y2 XDC + 1 + + + gen_x1y3_xdc + Generate X1Y3 XDC + 0 + + + gen_x1y4_xdc + Generate X1Y4 XDC + 0 + + + gen_x1y5_xdc + Generate X1Y5 XDC + 0 + + + xlnx_ref_board + Xlnx Ref Board + 0 + + + pcie_blk_locn + Pcie Blk Locn + 8 + + + PIPE_SIM + FALSE + + + AXISTEN_IF_ENABLE_CLIENT_TAG + TRUE + + + PCIE_FAST_CONFIG + PCIE FAST CONFIG + NONE + + + EXT_STARTUP_PRIMITIVE + EXT STARTUP PRIMITIVE + FALSE + + + PL_INTERFACE + PL INTERFACE + FALSE + + + PCIE_CONFIGURATION + PCIE CONFIGURATION + FALSE + + + CFG_STATUS_IF + TRUE + + + TX_FC_IF + TRUE + + + CFG_EXT_IF + FALSE + + + CFG_FC_IF + TRUE + + + PER_FUNC_STATUS_IF + TRUE + + + CFG_MGMT_IF + TRUE + + + RCV_MSG_IF + TRUE + + + CFG_TX_MSG_IF + TRUE + + + CFG_CTL_IF + TRUE + + + CFG_PM_IF + TRUE + + + PCIE_ID_IF + FALSE + + + MSI_EN + TRUE + + + MSIX_EN + FALSE + + + PCIE4_DRP + FALSE + + + DIS_GT_WIZARD + FALSE + + + BMD_PIO_MODE + FALSE + + + SRIOV_EXD_MODE + FALSE + + + DBG_CHECKER + FALSE + + + ENABLE_IBERT + FALSE + + + GEN4_EIEOS_0S7 + TRUE + + + CTRL_SKIP_MASK + TRUE + + + ENABLE_JTAG_DBG + FALSE + + + TWO_PORT_SWITCH + FALSE + + + TWO_PORT_CONFIG + X8G3 + + + TRANSCEIVER_CTRL_STATUS_PORTS + FALSE + + + SHARED_LOGIC + 1 + + + GTWIZ_IN_CORE + 1 + + + GTCOM_IN_CORE + 2 + + + AXISTEN_IF_RX_PARITY_EN + FALSE + + + AXISTEN_IF_TX_PARITY_EN + FALSE + + + AXISTEN_IF_MSIX_RX_PARITY_EN + FALSE + + + LL_TX_TLP_PARITY_CHK + FALSE + + + LL_RX_TLP_PARITY_GEN + FALSE + + + TL2CFG_IF_PARITY_CHK + FALSE + + + AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE + FALSE + + + DEDICATE_PERST + FALSE + + + SYS_RESET_POLARITY + 0 + + + MCAP_ENABLEMENT + NONE + + + MCAP_FPGA_BITSTREAM_VERSION + MCAP Bitstream Version Register Value + 0x00000000 + + + EXT_CH_GT_DRP + FALSE + + + EN_GT_SELECTION + FALSE + + + SELECT_QUAD + GTY_Quad_227 + + + silicon_revision + Silicon Revision + Beta + + + DEV_PORT_TYPE + 0 + + + VFG0_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG0_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG0_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG0_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG0_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + VFG1_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG1_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG1_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG1_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG1_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + VFG2_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG2_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG2_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG2_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG2_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + VFG3_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + 0 + + + VFG3_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 0x00000000 + + + VFG3_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + 0 + + + VFG3_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 0x00000000 + + + VFG3_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 0x000 + + + EN_PARITY + FALSE + + + INS_LOSS_PROFILE + ADD-IN_CARD + + + MSI_X_OPTIONS + None + + + COMPLETER_MODEL + FALSE + + + DBG_DESCRAMBLE_EN + FALSE + + + MSI_INT + MSI Ints + 32 + + + VU9P_BOARD + FALSE + + + PHY_LP_TXPRESET + 4 + + + IS_BOARD_PROJECT + Is Board Flow Enabled + 0 + + + GT_DRP_CLK_SRC + GT DRP Clk Source + 0 + + + FREE_RUN_FREQ + Free Run Freq + 1 + + + PM_ENABLE_L23_ENTRY + FALSE + + + AWS_MODE_VALUE + aws mode value + 0 + + + MULT_PF_DES + TRUE + + + EXT_SYS_CLK_BUFG + FALSE + + + AXISTEN_IF_ENABLE_MSG_ROUTE + 0x20000 + + + AXISTEN_IF_ENABLE_RX_MSG_INTFC + FALSE + + + ENABLE_MORE + FALSE + + + DISABLE_BRAM_PIPELINE + FALSE + + + DISABLE_EQ_SYNCHRONIZER + FALSE + + + ENABLE_AUTO_RXEQ + FALSE + + + + + + choice_list_002f5e3f + PCI_Express_Endpoint_device + Legacy_PCI_Express_Endpoint_device + Root_Port_of_PCI_Express_Root_Complex + + + choice_list_0cee66fe + 1 + 4 + 64 + + + choice_list_0f93492c + Chip-to-Chip + Add-in_Card + Backplane + + + choice_list_165ed04b + 64 + + + choice_list_1e9fb93b + X1 + X2 + X4 + X8 + X16 + + + choice_list_24b724fb + Basic + Advanced + + + choice_list_34d65ff4 + 128 + + + choice_list_35d06715 + 2 + + + choice_list_38306dd1 + SOFT + HARD + + + choice_list_3ca2cbc7 + BAR_0 + + + choice_list_3d9ff82c + 500 + 250 + + + choice_list_4a68658a + None + Tandem_PROM + Tandem_PCIe + Tandem_PCIe_with_Field_Updates + PR_over_PCIe + + + choice_list_504db607 + GTY_Quad_228 + GTY_Quad_227 + GTY_Quad_226 + GTY_Quad_225 + GTY_Quad_224 + + + choice_list_52d29139 + Bytes + Kilobytes + Megabytes + Gigabytes + + + choice_list_574f38f3 + 2.5_GT/s + 5.0_GT/s + 8.0_GT/s + + + choice_list_589df8e9 + RAM + Other_memory_controller + Flash + + + choice_list_5e2921cd + Kilobytes + + + choice_list_5e45706a + 1_vector + 2_vectors + 4_vectors + 8_vectors + 16_vectors + 32_vectors + + + choice_list_61bc5fcf + 0 + 4 + 7 + 8 + 12 + 16 + 20 + 24 + 28 + 32 + 36 + 40 + 44 + 48 + 52 + 56 + 60 + 64 + 68 + 72 + 76 + 80 + 84 + 88 + 92 + 96 + 100 + 104 + 108 + 112 + 116 + 120 + 124 + 128 + 132 + 136 + 140 + 144 + 148 + 152 + 156 + 160 + 164 + 168 + 172 + 176 + 180 + 184 + 188 + 192 + 196 + 200 + 204 + 208 + 212 + 216 + 220 + 224 + 228 + 232 + 236 + 240 + 244 + 248 + 252 + + + choice_list_6b979ebc + 250 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_6eff49bd + ACTIVE_LOW + ACTIVE_HIGH + + + choice_list_75aee2a8 + X8G3 + X16G3 + + + choice_list_7a7dde49 + true + false + + + choice_list_7d45a81a + 128_bytes + 256_bytes + 512_bytes + 1024_bytes + + + choice_list_81a1639d + DWORD_Aligned + Address_Aligned + + + choice_list_88156f2e + QPLL1 + QPLL0 + + + choice_list_8b5e4915 + 4 + 5 + + + choice_list_914704bd + 100_MHz + 125_MHz + + + choice_list_97bc19ec + 256_bit + + + choice_list_993a8980 + Wireless_controller + Satellite_communication_controllers + Data_acquisition_and_signal_processing_controllers + Intelligent_I/O_controllers + Docking_stations + Device_was_built_before_Class_Code_definitions_were_finalized + Memory_controller + Simple_communication_controllers + Serial_bus_controllers + Encryption/Decryption_controllers + Display_controller + Multimedia_device + Input_devices + Mass_storage_controller + Processors + Device_does_not_fit_in_any_defined_classes + Bridge_device + Network_controller + Base_system_peripherals + + + choice_list_9aec9108 + Internal + External + + + choice_list_a8dbd818 + X0Y1 + X0Y3 + X1Y2 + X1Y4 + + + choice_list_aa031417 + 1 + 2 + 3 + 4 + + + choice_list_ac75ef1e + Custom + + + choice_list_bdd7203f + True + False + + + choice_list_bea500ca + None + MSI-X_External + MSI-X_Internal + MSI-X_AXI4-Stream + + + choice_list_c15e8c67 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_c3d223d9 + Memory + + + choice_list_ca005b72 + No_ASPM + L1_Supported + + + choice_list_cca95a59 + None + VCU1262 + VCU117 + VCU118 + KCU116 + ZCU117 + ZCU106 + XIL-ACCEL-RD-VU9P + XIL-ACCEL-RD-VU9P-HP + ADM-PCIE-KU3 + ADM-PCIE-8K5 + XIL_ACCEL_RD_KU115 + BITTWARE-XUPP3R-VU9P + VCU1525 + VCU1550 + + + choice_list_d123c74c + Bytes + Kilobytes + Megabytes + + + choice_list_d53faa96 + 100_MHz + 125_MHz + 250_MHz + + + choice_list_d85ad257 + 0 + + + choice_list_d992adf6 + Generic_XT_compatible_serial_controller + 16450_compatible_serial_controller + Parallel_port + IEEE_1284_controller + Multiport_serial_controller + 16650_compatible_serial_controller + IEEE_1284_target_device + Hayes_compatible_modem_with_16550_compatible_interface + ECP_1.X_compliant_parallel_port + 16850_compatible_serial_controller + Hayes_compatible_modem_with_16750_compatible_interface + Smart_Card + Bi_directional_parallel_port + Other_communications_device + GPIB(IEEE_488.1/2)_controller + 16550_compatible_serial_controller + Hayes_compatible_modem_with_16450_compatible_interface + 16750_compatible_serial_controller + Hayes_compatible_modem_with_16650_compatible_interface + Generic_modem + 16950_compatible_serial_controller + + + choice_list_e9cf6440 + Disabled + 32bit_Enabled + 64bit_Enabled + + + choice_list_ec64e624 + N/A + + + choice_list_f1174048 + NONE + INTA + INTB + INTC + INTD + + + choice_list_f149a468 + Extreme + Good + + + choice_list_fc3456a9 + Disabled + Enabled + + + choice_pairs_3c87fcdb + 1 + 0 + + + choice_pairs_53749dec + 1 + 0 + + + choice_pairs_6f00a734 + 0 + 1 + 2 + + + + + xilinx_elaboratesubcores_view_fileset + + ip_0/xdma_pcie4_ip_gt.xci + xci + + + ip_0/xdma_pcie4_ip_gt.xml + xml + + + + The Xilinx UltraScale+ PCI Express Integrated Block (1-lane, 2-lane, 4-lane, 8-lane and 16-lane) in conjunction with flexible Ultra series architectural features such as integrated GTs (Gigabit Transceivers) and BRAM (Block RAMs) are used to implement a PCI Express Base Specification v3.1 compliant PCI Express Endpoint. + + + device_port_type + Device Port Type + PCI_Express_Endpoint_device + + + xlnx_ref_board + Xlnx Ref Board + None + + + + true + + + + + + PL_LINK_CAP_MAX_LINK_SPEED + Pl Link Cap Max Link Speed + 8.0_GT/s + + + PL_LINK_CAP_MAX_LINK_WIDTH + Pl Link Cap Max Link Width + The Xilinx Ultrascale Series Gen3 Integrated Block for PCI Expressification v3.0 compliant PCI Express Endpoint. + X8 + + + REF_CLK_FREQ + Ref Clk Freq + 100_MHz + + + AXISTEN_IF_EXT_512_CQ_STRADDLE + Axisten If Rc Straddle + false + + + + false + + + + + + AXISTEN_IF_EXT_512_CC_STRADDLE + Axisten If Rc Straddle + false + + + AXISTEN_IF_EXT_512_RQ_STRADDLE + Axisten If Rc Straddle + false + + + + false + + + + + + AXISTEN_IF_EXT_512_RC_STRADDLE + Axisten If Rc Straddle + true + + + AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE + Axisten If 512 4TLP/2TLP Rc Straddle + false + + + + false + + + + + + AXISTEN_IF_RC_STRADDLE + Axisten If Rc Straddle + true + + + axisten_if_enable_client_tag + Enable Client Tag + true + + + PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE + Pf0 Aer Cap Ecrc Gen and Check Capable + false + + + type1_membase_memlimit_enable + Type1 Config MemBase and MemLimit + Enabled + + + type1_prefetchable_membase_memlimit + Type1 Config Prefetchable MemBase and MemLimit + 64bit_Enabled + + + PF0_CLASS_CODE + Pf0 Class Code + 070001 + + + + false + + + + + + PF0_DEVICE_ID + Pf0 Device Id + 9038 + + + PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 128b Cas Atomic Completer Support + false + + + PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 32b Atomic Completer Support + false + + + PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT + Pf0 Dev Cap2 64b Atomic Completer Support + false + + + PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT + Pf0 Dev Cap2 Tph Completer Support + false + + + PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE + Pf0 Dev Cap Function Level Reset Capable + false + + + PF0_INTERRUPT_PIN + Pf0 Interrupt Pin + INTA + + + PF0_LINK_STATUS_SLOT_CLOCK_CONFIG + Pf0 Link Status Slot Clock Config + true + + + PF0_MSIX_CAP_PBA_BIR + Pf0 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF0_MSIX_CAP_PBA_OFFSET + Pf0 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_BIR + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_OFFSET + Pf0 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_SIZE + Pf0 Msix Cap Table Size + 000 + + + + false + + + + + + PF0_MSI_CAP_MULTIMSGCAP + Pf0 Msi Cap Multimsgcap + 1_vector + + + PF0_PM_CAP_PMESUPPORT_D1 + Pf0 Pm Cap Pmesupport D1 + false + + + PF0_PM_CAP_PMESUPPORT_D3HOT + Pf0 Pm Cap Pmesupport D3hot + false + + + PF0_PM_CAP_SUPP_D1_STATE + Pf0 Pm Cap Supp D1 State + false + + + PF0_REVISION_ID + Pf0 Revision Id + 00 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 1 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 0 + + + + false + + + + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0000 + + + PF0_SUBSYSTEM_ID + Pf0 Subsystem Id + 0007 + + + PF1_CLASS_CODE + Pf1 Class Code + 058000 + + + PF1_DEVICE_ID + Pf1 Device Id + 9011 + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + NONE + + + PF1_MSIX_CAP_PBA_BIR + Pf1 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_BIR + Pf1 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_SIZE + Pf1 Msix Cap Table Size + 000 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_OFFSET + Pf1 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF1_MSIX_CAP_PBA_OFFSET + Pf1 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 1_vector + + + PF1_REVISION_ID + Pf1 Revision Id + 00 + + + PF1_SRIOV_CAP_INITIAL_VF + Pf1 Sriov Cap Initial Vf + 0 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 1 + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + 0 + + + + false + + + + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0001 + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0000 + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0007 + + + PF2_CLASS_CODE + Pf2 Class Code + 058000 + + + PF2_DEVICE_ID + Pf2 Device Id + 9038 + + + PF2_INTERRUPT_PIN + Pf2 Interrupt Pin + NONE + + + PF2_MSIX_CAP_PBA_BIR + Pf2 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_BIR + Pf2 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_SIZE + Pf2 Msix Cap Table Size + 000 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_OFFSET + Pf2 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF2_MSIX_CAP_PBA_OFFSET + Pf2 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF2_MSI_CAP_MULTIMSGCAP + Pf2 Msi Cap Multimsgcap + 1_vector + + + PF2_REVISION_ID + Pf2 Revision Id + 00 + + + PF2_SRIOV_CAP_INITIAL_VF + Pf2 Sriov Cap Initial Vf + 0 + + + PF2_SRIOV_CAP_VER + Pf2 Sriov Cap Ver + 1 + + + PF2_SRIOV_FIRST_VF_OFFSET + Pf2 Sriov First Vf Offset + 0 + + + + false + + + + + + PF2_SRIOV_FUNC_DEP_LINK + Pf2 Sriov Func Dep Link + 0002 + + + PF2_SRIOV_SUPPORTED_PAGE_SIZE + Pf2 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF2_SRIOV_VF_DEVICE_ID + Pf2 Sriov Vf Device Id + 0000 + + + PF2_SUBSYSTEM_ID + Pf2 Subsystem Id + 0007 + + + PF3_CLASS_CODE + Pf3 Class Code + 058000 + + + PF3_DEVICE_ID + Pf3 Device Id + 9038 + + + PF3_INTERRUPT_PIN + Pf3 Interrupt Pin + NONE + + + PF3_MSIX_CAP_PBA_BIR + Pf3 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_BIR + Pf3 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_SIZE + Pf3 Msix Cap Table Size + 000 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_OFFSET + Pf3 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF3_MSIX_CAP_PBA_OFFSET + Pf3 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF3_MSI_CAP_MULTIMSGCAP + Pf3 Msi Cap Multimsgcap + 1_vector + + + PF3_REVISION_ID + Pf3 Revision Id + 00 + + + PF3_SRIOV_CAP_INITIAL_VF + Pf3 Sriov Cap Initial Vf + 0 + + + PF3_SRIOV_CAP_VER + Pf3 Sriov Cap Ver + 1 + + + PF3_SRIOV_FIRST_VF_OFFSET + Pf3 Sriov First Vf Offset + 0 + + + + false + + + + + + PF3_SRIOV_FUNC_DEP_LINK + Pf3 Sriov Func Dep Link + 0003 + + + PF3_SRIOV_SUPPORTED_PAGE_SIZE + Pf3 Sriov Supported Page Size + 00000553 + + + + false + + + + + + PF3_SRIOV_VF_DEVICE_ID + Pf3 Sriov Vf Device Id + 0000 + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0007 + + + TL_PF_ENABLE_REG + 1 + + + SRIOV_CAP_ENABLE + Sriov Cap Enable + false + + + Component_Name + xdma_pcie4_ip + + + PF0_Use_Class_Code_Lookup_Assistant + false + + + PF1_Use_Class_Code_Lookup_Assistant + false + + + PF2_Use_Class_Code_Lookup_Assistant + false + + + PF3_Use_Class_Code_Lookup_Assistant + false + + + PF0_PM_CAP_PMESUPPORT_D0 + Pf0 Pm Cap Pmesupport D0 + false + + + PF0_SUBSYSTEM_VENDOR_ID + Pf0 Subsystem Vendor Id + 10EE + + + PF1_SUBSYSTEM_VENDOR_ID + Pf1 Subsystem Vendor Id + 10EE + + + PF2_SUBSYSTEM_VENDOR_ID + Pf2 Subsystem Vendor Id + 10EE + + + PF3_SUBSYSTEM_VENDOR_ID + Pf3 Subsystem Vendor Id + 10EE + + + pf1_sriov_bar5_scale + Pf1 Sriov Bar5 Scale + Kilobytes + + + + false + + + + + + pf2_sriov_bar5_scale + Pf2 Sriov Bar5 Scale + Kilobytes + + + + false + + + + + + pf3_sriov_bar5_scale + Pf3 Sriov Bar5 Scale + Kilobytes + + + + false + + + + + + pf0_class_code_sub + Pf0 Class Code Sub + 00 + + + pf1_sriov_bar4_type + Pf1 Sriov Bar4 Type + N/A + + + + false + + + + + + pf2_sriov_bar4_type + Pf2 Sriov Bar4 Type + N/A + + + + false + + + + + + pf3_sriov_bar4_type + Pf3 Sriov Bar4 Type + N/A + + + + false + + + + + + pf0_vc_cap_enabled + Pf0 Vc Cap Enabled + false + + + pf1_sriov_bar5_type + Pf1 Sriov Bar5 Type + N/A + + + + false + + + + + + pf2_sriov_bar5_type + Pf2 Sriov Bar5 Type + N/A + + + + false + + + + + + pf3_sriov_bar5_type + Pf3 Sriov Bar5 Type + N/A + + + + false + + + + + + pf1_sriov_bar0_enabled + Pf1 Sriov Bar0 Enabled + true + + + + false + + + + + + pf2_sriov_bar0_enabled + Pf2 Sriov Bar0 Enabled + true + + + + false + + + + + + pf3_sriov_bar0_enabled + Pf3 Sriov Bar0 Enabled + true + + + + false + + + + + + pf0_sriov_bar5_enabled + Pf0 Sriov Bar5 Enabled + false + + + pf2_sriov_bar5_enabled + Pf2 Sriov Bar5 Enabled + false + + + + false + + + + + + pf3_sriov_bar5_enabled + Pf3 Sriov Bar5 Enabled + false + + + + false + + + + + + pcie_blk_locn + Pcie Blk Locn + X1Y2 + + + pf0_sriov_bar1_64bit + Pf0 Sriov Bar1 64bit + false + + + + false + + + + + + pf1_class_code_base + Pf1 Class Code Base + 05 + + + pf2_class_code_base + Pf2 Class Code Base + 05 + + + pf3_class_code_base + Pf3 Class Code Base + 05 + + + pf1_sriov_bar3_prefetchable + Pf1 Sriov Bar3 Prefetchable + false + + + + false + + + + + + pf2_sriov_bar3_prefetchable + Pf2 Sriov Bar3 Prefetchable + false + + + + false + + + + + + pf3_sriov_bar3_prefetchable + Pf3 Sriov Bar3 Prefetchable + false + + + + false + + + + + + pf1_sriov_bar0_64bit + Pf1 Sriov Bar0 64bit + false + + + + false + + + + + + pf2_sriov_bar0_64bit + Pf2 Sriov Bar0 64bit + false + + + + false + + + + + + pf3_sriov_bar0_64bit + Pf3 Sriov Bar0 64bit + false + + + + false + + + + + + pf1_bar3_type + Pf1 Bar3 Type + N/A + + + + false + + + + + + pf2_bar3_type + Pf2 Bar3 Type + N/A + + + + false + + + + + + pf3_bar3_type + Pf3 Bar3 Type + N/A + + + + false + + + + + + pf2_bar2_enabled + Pf2 Bar2 Enabled + false + + + + false + + + + + + pf3_bar2_enabled + Pf3 Bar2 Enabled + false + + + + false + + + + + + pf1_bar2_enabled + Pf1 Bar2 Enabled + false + + + + false + + + + + + pf1_bar2_type + Pf1 Bar2 Type + N/A + + + + false + + + + + + pf1_bar2_64bit + Pf1 Bar2 64bit + false + + + + false + + + + + + pf1_bar2_prefetchable + Pf1 Bar2 Prefetchable + false + + + + false + + + + + + pf1_bar2_scale + Pf1 Bar2 Scale + Kilobytes + + + + false + + + + + + pf1_bar2_size + Pf1 Bar2 Size + 128 + + + + false + + + + + + pf0_class_code_interface + Pf0 Class Code Interface + 01 + + + pf0_sriov_bar1_scale + Pf0 Sriov Bar1 Scale + Kilobytes + + + + false + + + + + + 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modulation in PPM + 0 + + + INS_LOSS_NYQ + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 15 + + + ins_loss_profile + Add-in_Card + + + + true + + + + + + enable_gen4 + false + + + en_transceiver_status_ports + false + + + + true + + + + + + Shared_Logic + 1 + + + gtwiz_in_core + 1 + + + gtcom_in_core + 2 + + + dedicate_perst + false + + + sys_reset_polarity + ACTIVE_LOW + + + mcap_enablement + MCAP Enable + None + + + mcap_fpga_bitstream_version + MCAP Bitstream Version Register Value + 00000000 + + + + false + + + + + + enable_code + 0000 + + + en_ext_ch_gt_drp + false + + + ext_startup_primitive + false + + + en_gt_selection + false + + + select_quad + GTY_Quad_227 + + + + false + + + + + + copy_pf0 + true + + + copy_sriov_pf0 + true + + + cfg_pm_if + true + + + pcie_id_if + FALSE + + + PL_DISABLE_LANE_REVERSAL + true + + + MSI_X_OPTIONS + None + + + completer_model + false + + + en_dbg_descramble + false + + + enable_jtag_dbg + false + + + + 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C_USE_SOFTECC + 0 + + + C_USE_ECC + 0 + + + C_EN_ECC_PIPE + 0 + + + C_HAS_INJECTERR + 0 + + + C_SIM_COLLISION_CHECK + ALL + + + C_COMMON_CLK + 1 + + + C_DISABLE_WARN_BHV_COLL + 0 + + + C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 0 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 1 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 2.618 mW + + + + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f92be8b1 + 18 + 36 + 72 + 144 + 288 + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_eab86dfe + READ_FIRST + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + xdma_v4_1_1_blk_mem_64_reg_be + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Simple_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + true + + + + + + ECC + false + + + + true + + + + + + softecc + false + + + + true + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + 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+ + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xci new file mode 100644 index 0000000..08559b5 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xci @@ -0,0 +1,274 @@ + + + xilinx.com + xci + unknown + 1.0 + + + xdma_v4_1_1_blk_mem_64_noreg_be + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + + OTHER + NONE + 8192 + 32 + + + 100000000 + 0.000 + 9 + 9 + 1 + 4 + 0 + 1 + 9 + 1 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 2.618 mW + virtexuplus + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 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+ GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xml new file mode 100644 index 0000000..45d431f --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xml @@ -0,0 +1,4061 @@ + + + xilinx.com + customized_ip + xdma_v4_1_1_blk_mem_64_noreg_be + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + AXI_SLAVE_S_AXI + AXI_SLAVE + AXI_SLAVE + + + + + + + ARADDR + + + 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C_DISABLE_WARN_BHV_COLL + 0 + + + C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 0 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 1 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 2.618 mW + + + + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_list_f92be8b1 + 18 + 36 + 72 + 144 + 288 + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + choice_pairs_eab86dfe + READ_FIRST + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + xdma_v4_1_1_blk_mem_64_noreg_be + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Simple_Dual_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + true + + + + + + ECC + false + + + + true + + + + + + softecc + false + + + + true + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + 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a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/xdma.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/xdma.xml new file mode 100644 index 0000000..3a70890 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/xdma/xdma.xml @@ -0,0 +1,56296 @@ + + + xilinx.com + customized_ip + xdma + 1.0 + + + CLK.SYS_CLK + + + + + + + CLK + + + sys_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + + true + + + + + + CLK.sys_clk_gt + CLK.sys_clk_gt + sys_clk_gt interface + + + + + + + CLK + + + sys_clk_gt + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + + true + + + + + + CLK.axi_aclk + + + + + + + CLK + + + axi_aclk + + + + + + ASSOCIATED_BUSIF + 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+ + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + true + + + + + + S_AXIS_C2H_1 + S_AXIS_C2H_1 + + + + + + + TDATA + + + s_axis_c2h_tdata_1 + + + + + TKEEP + + + s_axis_c2h_tkeep_1 + + + + + TLAST + + + s_axis_c2h_tlast_1 + + + + + TREADY + + + s_axis_c2h_tready_1 + + + + + TUSER + + + s_axis_c2h_tuser_1 + + + + + TVALID + + + s_axis_c2h_tvalid_1 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + M_AXIS_H2C_1 + M_AXIS_H2C_1 + + + + + + + TDATA + + + m_axis_h2c_tdata_1 + + + + + TKEEP + + + m_axis_h2c_tkeep_1 + + + + + TLAST + + + m_axis_h2c_tlast_1 + + + + + TREADY + + + m_axis_h2c_tready_1 + + + + + TUSER + + + m_axis_h2c_tuser_1 + + + + + TVALID + + + m_axis_h2c_tvalid_1 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + S_AXIS_C2H_2 + S_AXIS_C2H_2 + + + + + + + TDATA + + + s_axis_c2h_tdata_2 + + + + + TKEEP + + + s_axis_c2h_tkeep_2 + + + + + TLAST + + + s_axis_c2h_tlast_2 + + + + + TREADY + + + s_axis_c2h_tready_2 + + + + + TUSER + + + s_axis_c2h_tuser_2 + + + + + TVALID + + + s_axis_c2h_tvalid_2 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + M_AXIS_H2C_2 + M_AXIS_H2C_2 + + + + + + + TDATA + + + m_axis_h2c_tdata_2 + + + + + TKEEP + + + m_axis_h2c_tkeep_2 + + + + + TLAST + + + m_axis_h2c_tlast_2 + + + + + TREADY + + + m_axis_h2c_tready_2 + + + + + TUSER + + + m_axis_h2c_tuser_2 + + + + + TVALID + + + m_axis_h2c_tvalid_2 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + S_AXIS_C2H_3 + S_AXIS_C2H_3 + + + + + + + TDATA + + + s_axis_c2h_tdata_3 + + + + + TKEEP + + + s_axis_c2h_tkeep_3 + + + + + TLAST + + + s_axis_c2h_tlast_3 + + + + + TREADY + + + s_axis_c2h_tready_3 + + + + + TUSER + + + s_axis_c2h_tuser_3 + + + + + TVALID + + + s_axis_c2h_tvalid_3 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + M_AXIS_H2C_3 + M_AXIS_H2C_3 + + + + + + + TDATA + + + m_axis_h2c_tdata_3 + + + + + TKEEP + + + m_axis_h2c_tkeep_3 + + + + + TLAST + + + m_axis_h2c_tlast_3 + + + + + TREADY + + + m_axis_h2c_tready_3 + + + + + TUSER + + + m_axis_h2c_tuser_3 + + + + + TVALID + + + m_axis_h2c_tvalid_3 + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + m_axis_cq + m_axis_cq + The Completer Request interface is used to transmit Completion TLP's to the Client Application + + + + + + + TDATA + + + m_axis_cq_tdata_sd + + + + + TKEEP + + + m_axis_cq_tkeep_sd + + + + + TLAST + + + m_axis_cq_tlast_sd + + + + + TREADY + + + m_axis_cq_tready_sd + + + + + TUSER + + + m_axis_cq_tuser_sd + + + + + TVALID + + + m_axis_cq_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + s_axis_cc + s_axis_cc + The Completer Completion Interface is used to transmit Completion TLP's + + + + + + + TDATA + + + s_axis_cc_tdata_sd + + + + + TKEEP + + + s_axis_cc_tkeep_sd + + + + + TLAST + + + s_axis_cc_tlast_sd + + + + + TREADY + + + s_axis_cc_tready_sd + + + + + TUSER + + + s_axis_cc_tuser_sd + + + + + TVALID + + + s_axis_cc_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + s_axis_rq + s_axis_rq + The Requestor Request interface received requests TLP's from the Client Application + + + + + + + TDATA + + + s_axis_rq_tdata_sd + + + + + TKEEP + + + s_axis_rq_tkeep_sd + + + + + TLAST + + + s_axis_rq_tlast_sd + + + + + TREADY + + + s_axis_rq_tready_sd + + + + + TUSER + + + s_axis_rq_tuser_sd + + + + + TVALID + + + s_axis_rq_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + m_axis_rc + m_axis_rc + The Requestor Completer interface transmits completions to the client application + + + + + + + TDATA + + + m_axis_rc_tdata_sd + + + + + TKEEP + + + m_axis_rc_tkeep_sd + + + + + TLAST + + + m_axis_rc_tlast_sd + + + + + TREADY + + + m_axis_rc_tready_sd + + + + + TUSER + + + m_axis_rc_tuser_sd + + + + + TVALID + + + m_axis_rc_tvalid_sd + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + pcie4_cfg_mesg_tx + pcie4_us_cfg_mesg_tx + Configuration Transmit Message Interface + + + + + + + TRANSMIT + + + cfg_msg_transmit_sd + + + + + TRANSMIT_DATA + + + cfg_msg_transmit_data_sd + + + + + TRANSMIT_DONE + + + cfg_msg_transmit_done_sd + + + + + TRANSMIT_TYPE + + + cfg_msg_transmit_type_sd + + + + + + + false + + + + + + pcie4_cfg_mesg_rcvd + pcie4_us_cfg_mesg_rcvd + Configuration Received Message Interface + + + + + + + recd + + + cfg_msg_received_sd + + + + + recd_data + + + cfg_msg_received_data_sd + + + + + recd_type + + + cfg_msg_received_type_sd + + + + + + + false + + + + + + pcie4_cfg_status + pcie4_us_cfg_status + Configuration Status Interface + + + + + + + cq_np_req + + + pcie_cq_np_req_sd + + + + + cq_np_req_count + + + pcie_cq_np_req_count_sd + + + + + current_speed + + + cfg_current_speed_sd + + + + + err_cor_out + + + cfg_err_cor_out_sd + + + + + err_fatal_out + + + cfg_err_fatal_out_sd + + + + + err_nonfatal_out + + + cfg_err_nonfatal_out_sd + + + + + function_status + + + cfg_function_status_sd + + + + + local_error_out + + + cfg_local_error_out_sd + + + + + ltssm_state + + + cfg_ltssm_state_sd + + + + + max_payload + + + cfg_max_payload_sd + + + + + max_read_req + + + cfg_max_read_req_sd + + + + + negotiated_width + + + cfg_negotiated_width_sd + + + + + phy_link_down + + + cfg_phy_link_down_sd + + + + + phy_link_status + + + cfg_phy_link_status_sd + + + + + pl_status_change + + + cfg_pl_status_change_sd + + + + + rq_seq_num0 + + + pcie_rq_seq_num0_sd + + + + + rq_seq_num1 + + + pcie_rq_seq_num1_sd + + + + + rq_seq_num_vld0 + + + pcie_rq_seq_num_vld0_sd + + + + + rq_seq_num_vld1 + + + pcie_rq_seq_num_vld1_sd + + + + + tfc_npd_av + + + pcie_tfc_npd_av_sd + + + + + tfc_nph_av + + + pcie_tfc_nph_av_sd + + + + + + + false + + + + + + pcie4_cfg_control + pcie4_us_cfg_control + It allows a broad range of information exchange between user application and the core + + + + + + + ds_bus_number + + + cfg_ds_bus_number_sd + + + + + ds_device_number + + + cfg_ds_device_number_sd + + + + + ds_function_number + + + cfg_ds_function_number_sd + + + + + ds_port_number + + + cfg_ds_port_number_sd + + + + + dsn + + + cfg_dsn_sd + + + + + err_cor_in + + + cfg_err_cor_in_sd + + + + + err_uncor_in + + + cfg_err_uncor_in_sd + + + + + flr_done + + + cfg_flr_done_sd + + + + + flr_in_process + + + cfg_flr_in_process_sd + + + + + hot_reset_out + + + cfg_hot_reset_out_sd + + + + + link_training_enable + + + cfg_link_training_enable_sd + + + + + vf_flr_in_process + + + cfg_vf_flr_in_process_sd + + + + + + + false + + + + + + pcie4_cfg_fc + pcie_cfg_fc + Configuration Flow Control INTERFACE + + + + + + + NPH + + + cfg_fc_nph_sd + + + + + SEL + + + cfg_fc_sel_sd + + + + + + + false + + + + + + pcie4_cfg_msi + pcie4_us_cfg_msi + PCIE MSI interrupt + + + + + + + attr + + + cfg_interrupt_msi_attr_sd + + + + + data + + + cfg_interrupt_msi_data_sd + + + + + enable + + + cfg_interrupt_msi_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msi_int_sd + + + + + mask_update + + + cfg_interrupt_msi_mask_update_sd + + + + + pending_status + + + cfg_interrupt_msi_pending_status_sd + + + + + pending_status_data_enable + + + cfg_interrupt_msi_pending_status_data_enable_sd + + + + + pending_status_function_num + + + cfg_interrupt_msi_pending_status_function_num_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + tph_present + + + cfg_interrupt_msi_tph_present_sd + + + + + tph_st_tag + + + cfg_interrupt_msi_tph_st_tag_sd + + + + + tph_type + + + cfg_interrupt_msi_tph_type_sd + + + + + + + false + + + + + + pcie4_cfg_msix_external + pcie4_cfg_msix_external + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_external_msix + pcie4_cfg_external_msix + PCIE MSI-X Interrupt + + + + + + + address + + + cfg_interrupt_msix_address_sd + + + + + data + + + cfg_interrupt_msix_data_sd + + + + + enable + + + cfg_interrupt_msix_enable_sd + + + + + fail + + + cfg_interrupt_msi_fail_sd + + + + + function_number + + + cfg_interrupt_msi_function_number_sd + + + + + int_vector + + + cfg_interrupt_msix_int_sd + + + + + mask + + + cfg_interrupt_msix_mask_sd + + + + + sent + + + cfg_interrupt_msi_sent_sd + + + + + vf_enable + + + cfg_interrupt_msix_vf_enable_sd + + + + + vf_mask + + + cfg_interrupt_msix_vf_mask_sd + + + + + + + false + + + + + + pcie4_cfg_interrupt + pcie4_cfg_interrupt + PCIE Legacy Interrupt + + + + + + + INTx_VECTOR + + + cfg_interrupt_int_sd + + + + + PENDING + + + cfg_interrupt_pending_sd + + + + + SENT + + + cfg_interrupt_sent_sd + + + + + + + false + + + + + + pcie_cfg_mgmt + pcie_cfg_mgmt + PCIE Configuration Management Interface + + + + + + + ADDR + + + cfg_mgmt_addr + + + + + BYTE_EN + + + cfg_mgmt_byte_enable + + + + + READ_DATA + + + cfg_mgmt_read_data + + + + + READ_EN + + + cfg_mgmt_read + + + + + READ_WRITE_DONE + + + cfg_mgmt_read_write_done + + + + + TYPE1_CFG_REG_ACCESS + + + cfg_mgmt_type1_cfg_reg_access + + + + + WRITE_DATA + + + cfg_mgmt_write_data + + + + + WRITE_EN + + + cfg_mgmt_write + + + + + + + true + + + + + + pcie_mgt + pcie_7x_mgt + + + + + + + rxn + + + pci_exp_rxn + + + + + rxp + + + pci_exp_rxp + + + + + txn + + + pci_exp_txn + + + + + txp + + + pci_exp_txp + + + + + + BOARD.ASSOCIATED_PARAM + PCIE_BOARD_INTERFACE + + + + required + + + + + + + + + true + + + + + + drp + drp + DRP interface + + + + + + + DADDR + + + drp_addr + + + + + DEN + + + drp_en + + + + + DI + + + drp_di + + + + + DO + + + drp_do + + + + + DRDY + + + drp_rdy + + + + + DWE + + + drp_we + + + + + + + false + + + + + + pcie_debug_ports + pcie_debug_ports + PCIe Debug Interface + + + + + + + cfg_current_speed + + + cfg_current_speed_o + + + + + cfg_ltssm_state + + + cfg_ltssm_state_o + + + + + cfg_negotiated_width + + + cfg_negotiated_width_o + + + + + + + false + + + + + + pcie4_pcie_id + pcie4_pcie_id + PCIE 4 PCIE ID interface + + + + + + + subsys_vend_id + + + cfg_subsys_vend_id + + + + + vend_id + + + cfg_vend_id + + + + + + + false + + + + + + pcie4_pcie_id_pf0 + pcie4_pcie_id_pf0 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf0 + + + cfg_dev_id_pf0 + + + + + rev_id_pf0 + + + cfg_rev_id_pf0 + + + + + subsys_id_pf0 + + + cfg_subsys_id_pf0 + + + + + + + false + + + + + + pcie4_pcie_id_pf1 + pcie4_pcie_id_pf1 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf1 + + + cfg_dev_id_pf1 + + + + + rev_id_pf1 + + + cfg_rev_id_pf1 + + + + + subsys_id_pf1 + + + cfg_subsys_id_pf1 + + + + + + + false + + + + + + pcie4_pcie_id_pf2 + pcie4_pcie_id_pf2 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf2 + + + cfg_dev_id_pf2 + + + + + rev_id_pf2 + + + cfg_rev_id_pf2 + + + + + subsys_id_pf2 + + + cfg_subsys_id_pf2 + + + + + + + false + + + + + + pcie4_pcie_id_pf3 + pcie4_pcie_id_pf3 + PCIE 4 PCIE ID interface + + + + + + + dev_id_pf3 + + + cfg_dev_id_pf3 + + + + + rev_id_pf3 + + + cfg_rev_id_pf3 + + + + + subsys_id_pf3 + + + cfg_subsys_id_pf3 + + + + + + + false + + + + + + pcie3_7x_transceiver_debug + pcie3_7x_transceiver_debug + Transceiver Debug Interface of pcie3_7x + + + + + + + cpll_lock + + + pipe_cpll_lock + + + + + debug + + + pipe_debug + + + + + debug_0 + + + pipe_debug_0 + + + + + debug_1 + + + pipe_debug_1 + + + + + debug_2 + + + pipe_debug_2 + + + + + debug_3 + + + pipe_debug_3 + + + + + debug_4 + + + pipe_debug_4 + + + + + debug_5 + + + pipe_debug_5 + + + + + debug_6 + + + pipe_debug_6 + + + + + debug_7 + + + pipe_debug_7 + + + + + debug_8 + + + pipe_debug_8 + + + + + debug_9 + + + pipe_debug_9 + + + + + dmonitorout + + + pipe_dmonitorout + + + + + drp_fsm + + + pipe_drp_fsm + + + + + eyescandataerror + + + pipe_eyescandataerror + + + + + gt_ch_drp_rdy + + + gt_ch_drp_rdy + + + + + loopback + + + pipe_loopback + + + + + qpll_lock + + + pipe_qpll_lock + + + + + qrst_fsm + + + pipe_qrst_fsm + + + + + qrst_idle + + + pipe_qrst_idle + + + + + rate_fsm + + + pipe_rate_fsm + + + + + rate_idle + + + pipe_rate_idle + + + + + rst_fsm + + + pipe_rst_fsm + + + + + rst_idle + + + pipe_rst_idle + + + + + rxbufstatus + + + pipe_rxbufstatus + + + + + rxcommadet + + + pipe_rxcommadet + + + + + rxdisperr + + + pipe_rxdisperr + + + + + rxdlysresetdone + + + pipe_rxdlysresetdone + + + + + rxnotintable + + + pipe_rxnotintable + + + + + rxphaligndone + + + pipe_rxphaligndone + + + + + rxpmaresetdone + + + pipe_rxpmaresetdone + + + + + rxprbscntreset + + + pipe_rxprbscntreset + + + + + rxprbserr + + + pipe_rxprbserr + + + + + rxprbssel + + + pipe_rxprbssel + + + + + rxstatus + + + pipe_rxstatus + + + + + rxsyncdone + + + pipe_rxsyncdone + + + + + sync_fsm_rx + + + pipe_sync_fsm_rx + + + + + sync_fsm_tx + + + pipe_sync_fsm_tx + + + + + txdlysresetdone + + + pipe_txdlysresetdone + + + + + txinhibit + + + pipe_txinhibit + + + + + txphaligndone + + + pipe_txphaligndone + + + + + txphinitdone + + + pipe_txphinitdone + + + + + txprbsforceerr + + + pipe_txprbsforceerr + + + + + txprbssel + + + pipe_txprbssel + + + + + + + false + + + + + + pcie3_us_transceiver_debug + pcie3_us_transceiver_debug + Transceiver Debug Interface of pcie3_us + + + + + + + bufgtdiv + + + gt_bufgtdiv + + + + + cpll_lock + + + gt_cplllock + + + + + dmonfiforeset + + + gt_dmonfiforeset + + + + + dmonitorclk + + + gt_dmonitorclk + + + + + dmonitorout + + + gt_dmonitorout + + + + + eyescandataerror + + + gt_eyescandataerror + + + + + gtpowergood + + + gt_gtpowergood + + + + + loopback + + + gt_loopback + + + + + pcieuserratedone + + + gt_pcieuserratedone + + + + + pcieuserratestart + + + gt_pcieuserratestart + + + + + phystatus + + + gt_phystatus + + + + + prst_n + + + phy_prst_n + + + + + qpll_lock + + + gt_qpll1lock + + + + + rate_idle + + + gt_pcierateidle + + + + + rrst_n + + + phy_rrst_n + + + + + rst_fsm + + + phy_rst_fsm + + + + + rst_idle + + + phy_rst_idle + + + + + rxbufstatus + + + gt_rxbufstatus + + + + + rxcdrlock + + + gt_rxcdrlock + + + + + rxcommadet + + + gt_rxcommadet + + + + + rxdlysresetdone + + + gt_rxdlysresetdone + + + + + rxeq_fsm + + + phy_rxeq_fsm + + + + + rxoutclk + + + gt_rxoutclk + + + + + rxphaligndone + + + gt_rxphaligndone + + + + + rxpmaresetdone + + + gt_rxpmaresetdone + + + + + rxprbscntreset + + + gt_rxprbscntreset + + + + + rxprbserr + + + gt_rxprbserr + + + + + rxprbssel + + + gt_rxprbssel + + + + + rxrecclkout + + + gt_rxrecclkout + + + + + rxresetdone + + + gt_rxresetdone + + + + + rxstatus + + + gt_rxstatus + + + + + rxsyncdone + + + gt_rxsyncdone + + + + + rxvalid + + + gt_rxvalid + + + + + txdlysresetdone + + + gt_txdlysresetdone + + + + + txelecidle + + + gt_txelecidle + + + + + txeq_ctrl + + + phy_txeq_ctrl + + + + + txeq_fsm + + + phy_txeq_fsm + + + + + txeq_preset + + + phy_txeq_preset + + + + + txinhibit + + + gt_txinhibit + + + + + txphaligndone + + + gt_txphaligndone + + + + + txphinitdone + + + gt_txphinitdone + + + + + txprbsforceerr + + + gt_txprbsforceerr + + + + + txprbssel + + + gt_txprbssel + + + + + txresetdone + + + gt_txresetdone + + + + + + + false + + + + + + pcie4_us_plus_transceiver_debug + pcie4_us_plus_transceiver_debug + Transceiver Debug Interface of pcie4_us_plus + + + + + + + bufgtdiv + + + gt_bufgtdiv + + + + + cpll_lock + + + gt_cplllock + + + + + dmonfiforeset + + + gt_dmonfiforeset + + + + + dmonitorclk + + + gt_dmonitorclk + + + + + dmonitorout + + + gt_dmonitorout + + + + + eyescandataerror + + + gt_eyescandataerror + + + + + gen34_eios_det + + + gt_gen34_eios_det + + + + + gtpowergood + + + gt_gtpowergood + + + + + loopback + + + gt_loopback + + + + + pcieuserratedone + + + gt_pcieuserratedone + + + + + pcieuserratestart + + + gt_pcieuserratestart + + + + + phystatus + + + gt_phystatus + + + + + prst_n + + + phy_prst_n + + + + + qpll0_lock + + + gt_qpll0lock + + + + + qpll1_lock + + + gt_qpll1lock + + + + + rate_idle + + + gt_pcierateidle + + + + + rrst_n + + + phy_rrst_n + + + + + rst_fsm + + + phy_rst_fsm + + + + + rst_idle + + + phy_rst_idle + + + + + rxbufreset + + + gt_rxbufreset + + + + + rxbufstatus + + + gt_rxbufstatus + + + + + rxcdrlock + + + gt_rxcdrlock + + + + + rxcdrreset + + + gt_rxcdrreset + + + + + rxcommadet + + + gt_rxcommadet + + + + + rxdfelpmreset + + + gt_rxdfelpmreset + + + + + rxdlysresetdone + + + gt_rxdlysresetdone + + + + + rxeq_fsm + + + phy_rxeq_fsm + + + + + rxoutclk + + + gt_rxoutclk + + + + + rxoutclkfabric + + + gt_rxoutclkfabric + + + + + rxoutclkpcs + + + gt_rxoutclkpcs + + + + + rxpcsreset + + + gt_rxpcsreset + + + + + rxphaligndone + + + gt_rxphaligndone + + + + + rxpmareset + + + gt_rxpmareset + + + + + rxpmaresetdone + + + gt_rxpmaresetdone + + + + + rxprbscntreset + + + gt_rxprbscntreset + + + + + rxprbserr + + + gt_rxprbserr + + + + + rxprbslocked + + + gt_rxprbslocked + + + + + rxprbssel + + + gt_rxprbssel + + + + + rxrecclkout + + + gt_rxrecclkout + + + + + rxresetdone + + + gt_rxresetdone + + + + + rxstatus + + + gt_rxstatus + + + + + rxsyncdone + + + gt_rxsyncdone + + + + + rxvalid + + + gt_rxvalid + + + + + txdlysresetdone + + + gt_txdlysresetdone + + + + + txelecidle + + + gt_txelecidle + + + + + txeq_ctrl + + + phy_txeq_ctrl + + + + + txeq_fsm + + + phy_txeq_fsm + + + + + txeq_preset + + + phy_txeq_preset + + + + + txinhibit + + + gt_txinhibit + + + + + txoutclk + + + gt_txoutclk + + + + + txoutclkfabric + + + gt_txoutclkfabric + + + + + txoutclkpcs + + + gt_txoutclkpcs + + + + + txpcsreset + + + gt_txpcsreset + + + + + txphaligndone + + + gt_txphaligndone + + + + + txphinitdone + + + gt_txphinitdone + + + + + txpmareset + + + gt_txpmareset + + + + + txpmaresetdone + + + gt_txpmaresetdone + + + + + txprbsforceerr + + + gt_txprbsforceerr + + + + + txprbssel + + + gt_txprbssel + + + + + txprogdivresetdone + + + gt_txprogdivresetdone + + + + + txresetdone + + + gt_txresetdone + + + + + txsyncdone + + + gt_txsyncdone + + + + + + + false + + + + + + pcie3_us_gt_if + pcie3_us_gt_if + GT Interface + + + + + + + bufgtce_out + + + bufgtce_us_out + + + + + bufgtcemask_out + + + bufgtcemask_us_out + + + + + bufgtdiv_out + + + bufgtdiv_us_out + + + + + bufgtreset_out + + + bufgtreset_us_out + + + + + bufgtrstmask_out + + + bufgtrstmask_us_out + + + + + cplllock_out + + + cplllock_us_out + + + + + cpllpd_in + + + cpllpd_us_in + + + + + cpllreset_in + + + cpllreset_us_in + + + + + dmonfiforeset_in + + + dmonfiforeset_us_in + + + + + dmonitorclk_in + + + dmonitorclk_us_in + + + + + dmonitorout_out + + + dmonitorout_us_out + + + + + drpaddr_in + + + drpaddr_us_in + + + + + drpclk_in + + + drpclk_us_in + + + + + drpdi_in + + + drpdi_us_in + + + + + drpdo_out + + + drpdo_us_out + + + + + drpen_in + + + drpen_us_in + + + + + drprdy_out + + + drprdy_us_out + + + + + drpwe_in + + + drpwe_us_in + + + + + eyescandataerror_out + + + eyescandataerror_us_out + + + + + eyescanreset_in + + + eyescanreset_us_in + + + + + gthrxn_in + + + gthrxn_us_in + + + + + gthrxp_in + + + gthrxp_us_in + + + + + gthtxn_out + + + gthtxn_us_out + + + + + gthtxp_out + + + gthtxp_us_out + + + + + gtpowergood_out + + + gtpowergood_us_out + + + + + gtrefclk0_in + + + gtrefclk0_us_in + + + + + gtrefclk01_in + + + gtrefclk01_us_in + + + + + gtrxreset_in + + + gtrxreset_us_in + + + + + gttxreset_in + + + gttxreset_us_in + + + + + gtwiz_reset_rx_done_in + + + gtwiz_reset_rx_done_us_in + + + + + gtwiz_reset_tx_done_in + + + gtwiz_reset_tx_done_us_in + + + + + gtwiz_userclk_rx_active_in + + + gtwiz_userclk_rx_active_us_in + + + + + gtwiz_userclk_tx_active_in + + + gtwiz_userclk_tx_active_us_in + + + + + gtwiz_userclk_tx_reset_in + + + gtwiz_userclk_tx_reset_us_in + + + + + loopback_in + + + loopback_us_in + + + + + pcieeqrxeqadaptdone_in + + + pcieeqrxeqadaptdone_us_in + + + + + pcierategen3_out + + + pcierategen3_us_out + + + + + pcierateidle_out + + + pcierateidle_us_out + + + + + pcierateqpllpd_out + + + pcierateqpllpd_us_out + + + + + pcierateqpllreset_out + + + pcierateqpllreset_us_out + + + + + pcierstidle_in + + + pcierstidle_us_in + + + + + pciersttxsyncstart_in + + + pciersttxsyncstart_us_in + + + + + pciesynctxsyncdone_out + + + pciesynctxsyncdone_us_out + + + + + pcieusergen3rdy_out + + + pcieusergen3rdy_us_out + + + + + pcieuserphystatusrst_out + + + pcieuserphystatusrst_us_out + + + + + pcieuserratedone_in + + + pcieuserratedone_us_in + + + + + pcieuserratestart_out + + + pcieuserratestart_us_out + + + + + pcsrsvdin_in + + + pcsrsvdin_us_in + + + + + pcsrsvdout_out + + + pcsrsvdout_us_out + + + + + phystatus_out + + + phystatus_us_out + + + + + qpll0clk_in + + + qpll0clk_us_in + + + + + qpll0refclk_in + + + qpll0refclk_us_in + + + + + qpll1clk_in + + + qpll1clk_us_in + + + + + qpll1lock_out + + + qpll1lock_us_out + + + + + qpll1outclk_out + + + qpll1outclk_us_out + + + + + qpll1outrefclk_out + + + qpll1outrefclk_us_out + + + + + qpll1pd_in + + + qpll1pd_us_in + + + + + qpll1refclk_in + + + qpll1refclk_us_in + + + + + qpll1reset_in + + + qpll1reset_us_in + + + + + qpllrsvd2_in + + + qpllrsvd2_us_in + + + + + qpllrsvd3_in + + + qpllrsvd3_us_in + + + + + rx8b10ben_in + + + rx8b10ben_us_in + + + + + rxbufreset_in + + + rxbufreset_us_in + + + + + rxbufstatus_out + + + rxbufstatus_us_out + + + + + rxbyteisaligned_out + + + rxbyteisaligned_us_out + + + + + rxbyterealign_out + + + rxbyterealign_us_out + + + + + rxcdrhold_in + + + rxcdrhold_us_in + + + + + rxcdrlock_out + + + rxcdrlock_us_out + + + + + rxclkcorcnt_out + + + rxclkcorcnt_us_out + + + + + rxcommadet_out + + + rxcommadet_us_out + + + + + rxcommadeten_in + + + rxcommadeten_us_in + + + + + rxctrl0_out + + + rxctrl0_us_out + + + + + rxctrl1_out + + + rxctrl1_us_out + + + + + rxctrl2_out + + + rxctrl2_us_out + + + + + rxctrl3_out + + + rxctrl3_us_out + + + + + rxdata_out + + + rxdata_us_out + + + + + rxdfeagchold_in + + + rxdfeagchold_us_in + + + + + rxdfecfokhold_in + + + rxdfecfokhold_us_in + + + + + rxdfekhhold_in + + + rxdfekhhold_us_in + + + + + rxdfelfhold_in + + + rxdfelfhold_us_in + + + + + rxdfetap2hold_in + + + rxdfetap2hold_us_in + + + + + rxdfetap3hold_in + + + rxdfetap3hold_us_in + + + + + rxdfetap4hold_in + + + rxdfetap4hold_us_in + + + + + rxdfetap5hold_in + + + rxdfetap5hold_us_in + + + + + rxdfetap6hold_in + + + rxdfetap6hold_us_in + + + + + rxdfetap7hold_in + + + rxdfetap7hold_us_in + + + + + rxdfetap8hold_in + + + rxdfetap8hold_us_in + + + + + rxdfetap9hold_in + + + rxdfetap9hold_us_in + + + + + rxdfetap10hold_in + + + rxdfetap10hold_us_in + + + + + rxdfetap11hold_in + + + rxdfetap11hold_us_in + + + + + rxdfetap12hold_in + + + rxdfetap12hold_us_in + + + + + rxdfetap13hold_in + + + rxdfetap13hold_us_in + + + + + rxdfetap14hold_in + + + rxdfetap14hold_us_in + + + + + rxdfetap15hold_in + + + rxdfetap15hold_us_in + + + + + rxdfeuthold_in + + + rxdfeuthold_us_in + + + + + rxdfevphold_in + + + rxdfevphold_us_in + + + + + rxdlysresetdone_out + + + rxdlysresetdone_us_out + + + + + rxelecidle_out + + + rxelecidle_us_out + + + + + rxlpmen_in + + + rxlpmen_us_in + + + + + rxlpmgchold_in + + + rxlpmgchold_us_in + + + + + rxlpmhfhold_in + + + rxlpmhfhold_us_in + + + + + rxlpmlfhold_in + + + rxlpmlfhold_us_in + + + + + rxlpmoshold_in + + + rxlpmoshold_us_in + + + + + rxmcommaalignen_in + + + rxmcommaalignen_us_in + + + + + rxoshold_in + + + rxoshold_us_in + + + + + rxoutclk_out + + + rxoutclk_us_out + + + + + rxpcommaalignen_in + + + rxpcommaalignen_us_in + + + + + rxpd_in + + + rxpd_us_in + + + + + rxphaligndone_out + + + rxphaligndone_us_out + + + + + rxpmaresetdone_out + + + rxpmaresetdone_us_out + + + + + rxpolarity_in + + + rxpolarity_us_in + + + + + rxprbscntreset_in + + + rxprbscntreset_us_in + + + + + rxprbserr_out + + + rxprbserr_us_out + + + + + rxprbslocked_out + + + rxprbslocked_us_out + + + + + rxprbssel_in + + + rxprbssel_us_in + + + + + rxprgdivresetdone_out + + + rxprgdivresetdone_us_out + + + + + rxprogdivreset_in + + + rxprogdivreset_us_in + + + + + rxrate_in + + + rxrate_us_in + + + + + rxratedone_out + + + rxratedone_us_out + + + + + rxratemode_in + + + rxratemode_us_in + + + + + rxresetdone_out + + + rxresetdone_us_out + + + + + rxslide_in + + + rxslide_us_in + + + + + rxstatus_out + + + rxstatus_us_out + + + + + rxsyncdone_out + + + rxsyncdone_us_out + + + + + rxuserrdy_in + + + rxuserrdy_us_in + + + + + rxusrclk2_in + + + rxusrclk2_us_in + + + + + rxusrclk_in + + + rxusrclk_us_in + + + + + rxvalid_out + + + rxvalid_us_out + + + + + tx8b10ben_in + + + tx8b10ben_us_in + + + + + txctrl0_in + + + txctrl0_us_in + + + + + txctrl1_in + + + txctrl1_us_in + + + + + txctrl2_in + + + txctrl2_us_in + + + + + txdata_in + + + txdata_us_in + + + + + txdeemph_in + + + txdeemph_us_in + + + + + txdetectrx_in + + + txdetectrx_us_in + + + + + txdiffctrl_in + + + txdiffctrl_us_in + + + + + txdlybypass_in + + + txdlybypass_us_in + + + + + txdlyen_in + + + txdlyen_us_in + + + + + txdlyhold_in + + + txdlyhold_us_in + + + + + txdlyovrden_in + + + txdlyovrden_us_in + + + + + txdlysreset_in + + + txdlysreset_us_in + + + + + txdlysresetdone_out + + + txdlysresetdone_us_out + + + + + txdlyupdown_in + + + txdlyupdown_us_in + + + + + txelecidle_in + + + txelecidle_us_in + + + + + txinhibit_in + + + txinhibit_us_in + + + + + txmaincursor_in + + + txmaincursor_us_in + + + + + txmargin_in + + + txmargin_us_in + + + + + txoutclk_out + + + txoutclk_us_out + + + + + txoutclksel_in + + + txoutclksel_us_in + + + + + txpd_in + + + txpd_us_in + + + + + txphalign_in + + + txphalign_us_in + + + + + txphaligndone_out + + + txphaligndone_us_out + + + + + txphalignen_in + + + txphalignen_us_in + + + + + txphdlypd_in + + + txphdlypd_us_in + + + + + txphdlyreset_in + + + txphdlyreset_us_in + + + + + txphdlytstclk_in + + + txphdlytstclk_us_in + + + + + txphinit_in + + + txphinit_us_in + + + + + txphinitdone_out + + + txphinitdone_us_out + + + + + txphovrden_in + + + txphovrden_us_in + + + + + txpmaresetdone_out + + + txpmaresetdone_us_out + + + + + txpostcursor_in + + + txpostcursor_us_in + + + + + txprbsforceerr_in + + + txprbsforceerr_us_in + + + + + txprbssel_in + + + txprbssel_us_in + + + + + txprecursor_in + + + txprecursor_us_in + + + + + txprgdivresetdone_out + + + txprgdivresetdone_us_out + + + + + txprogdivreset_in + + + txprogdivreset_us_in + + + + + txrate_in + + + txrate_us_in + + + + + txresetdone_out + + + txresetdone_us_out + + + + + txswing_in + + + txswing_us_in + + + + + txsyncallin_in + + + txsyncallin_us_in + + + + + txsyncdone_out + + + txsyncdone_us_out + + + + + txsyncin_in + + + txsyncin_us_in + + + + + txsyncmode_in + + + txsyncmode_us_in + + + + + txsyncout_out + + + txsyncout_us_out + + + + + txuserrdy_in + + + txuserrdy_us_in + + + + + txusrclk2_in + + + txusrclk2_us_in + + + + + txusrclk_in + + + txusrclk_us_in + + + + + + + false + + + + + + pcie4_gt_if + pcie4_gt_if + GT Interface + + + + + + + bufgtce_out + + + bufgtce_usp_out + + + + + bufgtcemask_out + + + bufgtcemask_usp_out + + + + + bufgtdiv_out + + + bufgtdiv_usp_out + + + + + bufgtreset_out + + + bufgtreset_usp_out + + + + + bufgtrstmask_out + + + bufgtrstmask_usp_out + + + + + cpllfreqlock_in + + + cpllfreqlock_usp_in + + + + + cplllock_out + + + cplllock_usp_out + + + + + cpllpd_in + + + cpllpd_usp_in + + + + + cpllreset_in + + + cpllreset_usp_in + + + + + dmonfiforeset_in + + + dmonfiforeset_usp_in + + + + + dmonitorclk_in + + + dmonitorclk_usp_in + + + + + dmonitorout_out + + + dmonitorout_usp_out + + + + + drpaddr_in + + + drpaddr_usp_in + + + + + drpclk_in + + + drpclk_usp_in + + + + + drpdi_in + + + drpdi_usp_in + + + + + drpdo_out + + + drpdo_usp_out + + + + + drpen_in + + + drpen_usp_in + + + + + drprdy_out + + + drprdy_usp_out + + + + + drprst_in + + + drprst_usp_in + + + + + drpwe_in + + + drpwe_usp_in + + + + + ext_phy_clk_bufg_gt_ce + + + ext_phy_clk_bufg_gt_ce + + + + + ext_phy_clk_bufg_gt_reset + + + ext_phy_clk_bufg_gt_reset + + + + + ext_phy_clk_bufgtcemask + + + ext_phy_clk_bufgtcemask + + + + + ext_phy_clk_bufgtdiv + + + ext_phy_clk_bufgtdiv + + + + + ext_phy_clk_gt_bufgtrstmask + + + ext_phy_clk_gt_bufgtrstmask + + + + + ext_phy_clk_int_clock + + + ext_phy_clk_int_clock + + + + + ext_phy_clk_pclk + + + ext_phy_clk_pclk + + + + + ext_phy_clk_pclk2_gt + + + ext_phy_clk_pclk2_gt + + + + + ext_phy_clk_phy_coreclk + + + ext_phy_clk_phy_coreclk + + + + + ext_phy_clk_phy_mcapclk + + + ext_phy_clk_phy_mcapclk + + + + + ext_phy_clk_phy_pclk2 + + + ext_phy_clk_phy_pclk2 + + + + + ext_phy_clk_phy_userclk + + + ext_phy_clk_phy_userclk + + + + + ext_phy_clk_rst_idle + + + ext_phy_clk_rst_idle + + + + + ext_phy_clk_txoutclk + + + ext_phy_clk_txoutclk + + + + + eyescanreset_in + + + eyescanreset_usp_in + + + + + gtpowergood_out + + + gtpowergood_usp_out + + + + + gtrefclk0_in + + + gtrefclk0_usp_in + + + + + gtrefclk00_in + + + gtrefclk00_usp_in + + + + + gtrefclk01_in + + + gtrefclk01_usp_in + + + + + gtrxreset_in + + + gtrxreset_usp_in + + + + + gttxreset_in + + + gttxreset_usp_in + + + + + gtwiz_reset_rx_done_in + + + gtwiz_reset_rx_done_usp_in + + + + + gtwiz_reset_tx_done_in + + + gtwiz_reset_tx_done_usp_in + + + + + gtwiz_userclk_rx_active_in + + + gtwiz_userclk_rx_active_usp_in + + + + + gtwiz_userclk_tx_active_in + + + gtwiz_userclk_tx_active_usp_in + + + + + loopback_in + + + loopback_usp_in + + + + + pcieeqrxeqadaptdone_in + + + pcieeqrxeqadaptdone_usp_in + + + + + pcierategen3_out + + + pcierategen3_usp_out + + + + + pcierateidle_out + + + pcierateidle_usp_out + + + + + pcierateqpll0_in + + + pcierateqpll0_usp_in + + + + + pcierateqpll1_in + + + pcierateqpll1_usp_in + + + + + pcierateqpllpd_out + + + pcierateqpllpd_usp_out + + + + + pcierateqpllreset_out + + + pcierateqpllreset_usp_out + + + + + pcierstidle_in + + + pcierstidle_usp_in + + + + + pciersttxsyncstart_in + + + pciersttxsyncstart_usp_in + + + + + pciesynctxsyncdone_out + + + pciesynctxsyncdone_usp_out + + + + + pcieusergen3rdy_out + + + pcieusergen3rdy_usp_out + + + + + pcieuserphystatusrst_out + + + pcieuserphystatusrst_usp_out + + + + + pcieuserratedone_in + + + pcieuserratedone_usp_in + + + + + pcieuserratestart_out + + + pcieuserratestart_usp_out + + + + + phystatus_out + + + phystatus_usp_out + + + + + qpll0freqlock_in + + + qpll0freqlock_usp_in + + + + + qpll0lock_out + + + qpll0lock_usp_out + + + + + qpll0outclk_out + + + qpll0outclk_usp_out + + + + + qpll0outrefclk_out + + + qpll0outrefclk_usp_out + + + + + qpll0pd_in + + + qpll0pd_usp_in + + + + + qpll0reset_in + + + qpll0reset_usp_in + + + + + qpll1freqlock_in + + + qpll1freqlock_usp_in + + + + + qpll1lock_out + + + qpll1lock_usp_out + + + + + qpll1outclk_out + + + qpll1outclk_usp_out + + + + + qpll1outrefclk_out + + + qpll1outrefclk_usp_out + + + + + qpll1pd_in + + + qpll1pd_usp_in + + + + + qpll1reset_in + + + qpll1reset_usp_in + + + + + rcalenb_in + + + rcalenb_usp_in + + + + + resetovrd_in + + + resetovrd_usp_in + + + + + rx8b10ben_in + + + rx8b10ben_usp_in + + + + + rxbufreset_in + + + rxbufreset_usp_in + + + + + rxbufstatus_out + + + rxbufstatus_usp_out + + + + + rxbyteisaligned_out + + + rxbyteisaligned_usp_out + + + + + rxbyterealign_out + + + rxbyterealign_usp_out + + + + + rxcdrfreqreset_in + + + rxcdrfreqreset_usp_in + + + + + rxcdrhold_in + + + rxcdrhold_usp_in + + + + + rxcdrlock_out + + + rxcdrlock_usp_out + + + + + rxcdrreset_in + + + rxcdrreset_usp_in + + + + + rxclkcorcnt_out + + + rxclkcorcnt_usp_out + + + + + rxcommadet_out + + + rxcommadet_usp_out + + + + + rxcommadeten_in + + + rxcommadeten_usp_in + + + + + rxctrl0_out + + + rxctrl0_usp_out + + + + + rxctrl1_out + + + rxctrl1_usp_out + + + + + rxctrl2_out + + + rxctrl2_usp_out + + + + + rxctrl3_out + + + rxctrl3_usp_out + + + + + rxdata_out + + + rxdata_usp_out + + + + + rxdfeagchold_in + + + rxdfeagchold_usp_in + + + + + rxdfecfokhold_in + + + rxdfecfokhold_usp_in + + + + + rxdfekhhold_in + + + rxdfekhhold_usp_in + + + + + rxdfelfhold_in + + + rxdfelfhold_usp_in + + + + + rxdfelpmreset_in + + + rxdfelpmreset_usp_in + + + + + rxdfetap2hold_in + + + rxdfetap2hold_usp_in + + + + + rxdfetap3hold_in + + + rxdfetap3hold_usp_in + + + + + rxdfetap4hold_in + + + rxdfetap4hold_usp_in + + + + + rxdfetap5hold_in + + + rxdfetap5hold_usp_in + + + + + rxdfetap6hold_in + + + rxdfetap6hold_usp_in + + + + + rxdfetap7hold_in + + + rxdfetap7hold_usp_in + + + + + rxdfetap8hold_in + + + rxdfetap8hold_usp_in + + + + + rxdfetap9hold_in + + + rxdfetap9hold_usp_in + + + + + rxdfetap10hold_in + + + rxdfetap10hold_usp_in + + + + + rxdfetap11hold_in + + + rxdfetap11hold_usp_in + + + + + rxdfetap12hold_in + + + rxdfetap12hold_usp_in + + + + + rxdfetap13hold_in + + + rxdfetap13hold_usp_in + + + + + rxdfetap14hold_in + + + rxdfetap14hold_usp_in + + + + + rxdfetap15hold_in + + + rxdfetap15hold_usp_in + + + + + rxdfeuthold_in + + + rxdfeuthold_usp_in + + + + + rxdfevphold_in + + + rxdfevphold_usp_in + + + + + rxdlysresetdone_out + + + rxdlysresetdone_usp_out + + + + + rxelecidle_out + + + rxelecidle_usp_out + + + + + rxlpmen_in + + + rxlpmen_usp_in + + + + + rxlpmgchold_in + + + rxlpmgchold_usp_in + + + + + rxlpmhfhold_in + + + rxlpmhfhold_usp_in + + + + + rxlpmlfhold_in + + + rxlpmlfhold_usp_in + + + + + rxlpmoshold_in + + + rxlpmoshold_usp_in + + + + + rxmcommaalignen_in + + + rxmcommaalignen_usp_in + + + + + rxoshold_in + + + rxoshold_usp_in + + + + + rxoutclk_out + + + rxoutclk_usp_out + + + + + rxoutclkfabric_out + + + rxoutclkfabric_usp_out + + + + + rxoutclkpcs_out + + + rxoutclkpcs_usp_out + + + + + rxpcommaalignen_in + + + rxpcommaalignen_usp_in + + + + + rxpcsreset_in + + + rxpcsreset_usp_in + + + + + rxpd_in + + + rxpd_usp_in + + + + + rxphaligndone_out + + + rxphaligndone_usp_out + + + + + rxpmareset_in + + + rxpmareset_usp_in + + + + + rxpmaresetdone_out + + + rxpmaresetdone_usp_out + + + + + rxpolarity_in + + + rxpolarity_usp_in + + + + + rxprbscntreset_in + + + rxprbscntreset_usp_in + + + + + rxprbserr_out + + + rxprbserr_usp_out + + + + + rxprbslocked_out + + + rxprbslocked_usp_out + + + + + rxprbssel_in + + + rxprbssel_usp_in + + + + + rxprogdivreset_in + + + rxprogdivreset_usp_in + + + + + rxrate_in + + + rxrate_usp_in + + + + + rxratedone_out + + + rxratedone_usp_out + + + + + rxratemode_in + + + rxratemode_usp_in + + + + + rxrecclkout_out + + + rxrecclkout_usp_out + + + + + rxresetdone_out + + + rxresetdone_usp_out + + + + + rxslide_in + + + rxslide_usp_in + + + + + rxstatus_out + + + rxstatus_usp_out + + + + + rxsyncdone_out + + + rxsyncdone_usp_out + + + + + rxtermination_in + + + rxtermination_usp_in + + + + + rxuserrdy_in + + + rxuserrdy_usp_in + + + + + rxusrclk2_in + + + rxusrclk2_usp_in + + + + + rxusrclk_in + + + rxusrclk_usp_in + + + + + rxvalid_out + + + rxvalid_usp_out + + + + + tx8b10ben_in + + + tx8b10ben_usp_in + + + + + txctrl0_in + + + txctrl0_usp_in + + + + + txctrl1_in + + + txctrl1_usp_in + + + + + txctrl2_in + + + txctrl2_usp_in + + + + + txdata_in + + + txdata_usp_in + + + + + txdeemph_in + + + txdeemph_usp_in + + + + + txdetectrx_in + + + txdetectrx_usp_in + + + + + txdiffctrl_in + + + txdiffctrl_usp_in + + + + + txdlybypass_in + + + txdlybypass_usp_in + + + + + txdlyen_in + + + txdlyen_usp_in + + + + + txdlyhold_in + + + txdlyhold_usp_in + + + + + txdlyovrden_in + + + txdlyovrden_usp_in + + + + + txdlysreset_in + + + txdlysreset_usp_in + + + + + txdlysresetdone_out + + + txdlysresetdone_usp_out + + + + + txdlyupdown_in + + + txdlyupdown_usp_in + + + + + txelecidle_in + + + txelecidle_usp_in + + + + + txmaincursor_in + + + txmaincursor_usp_in + + + + + txmargin_in + + + txmargin_usp_in + + + + + txoutclk_out + + + txoutclk_usp_out + + + + + txoutclkfabric_out + + + txoutclkfabric_usp_out + + + + + txoutclkpcs_out + + + txoutclkpcs_usp_out + + + + + txoutclksel_in + + + txoutclksel_usp_in + + + + + txpcsreset_in + + + txpcsreset_usp_in + + + + + txpd_in + + + txpd_usp_in + + + + + txphalign_in + + + txphalign_usp_in + + + + + txphaligndone_out + + + txphaligndone_usp_out + + + + + txphalignen_in + + + txphalignen_usp_in + + + + + txphdlypd_in + + + txphdlypd_usp_in + + + + + txphdlyreset_in + + + txphdlyreset_usp_in + + + + + txphdlytstclk_in + + + txphdlytstclk_usp_in + + + + + txphinit_in + + + txphinit_usp_in + + + + + txphinitdone_out + + + txphinitdone_usp_out + + + + + txphovrden_in + + + txphovrden_usp_in + + + + + txpisopd_in + + + txpisopd_usp_in + + + + + txpmareset_in + + + txpmareset_usp_in + + + + + txpmaresetdone_out + + + txpmaresetdone_usp_out + + + + + txpostcursor_in + + + txpostcursor_usp_in + + + + + txprbsforceerr_in + + + txprbsforceerr_usp_in + + + + + txprbssel_in + + + txprbssel_usp_in + + + + + txprecursor_in + + + txprecursor_usp_in + + + + + txprgdivresetdone_out + + + txprgdivresetdone_usp_out + + + + + txprogdivreset_in + + + txprogdivreset_usp_in + + + + + txrate_in + + + txrate_usp_in + + + + + txresetdone_out + + + txresetdone_usp_out + + + + + txswing_in + + + txswing_usp_in + + + + + txsyncallin_in + + + txsyncallin_usp_in + + + + + txsyncdone_out + + + txsyncdone_usp_out + + + + + txsyncin_in + + + txsyncin_usp_in + + + + + txsyncmode_in + + + txsyncmode_usp_in + + + + + txsyncout_out + + + txsyncout_usp_out + + + + + txuserrdy_in + + + txuserrdy_usp_in + + + + + txusrclk2_in + + + txusrclk2_usp_in + + + + + txusrclk_in + + + txusrclk_usp_in + + + + + + + false + + + + + + pcie_ext_ch_gt + pcie_ext_ch_gt + GT DRP interface + + + + + + + DADDR + + + ext_ch_gt_drpaddr + + + + + DEN + + + ext_ch_gt_drpen + + + + + DI + + + ext_ch_gt_drpdi + + + + + DO + + + ext_ch_gt_drpdo + + + + + DRDY + + + ext_ch_gt_drprdy + + + + + DWE + + + ext_ch_gt_drpwe + + + + + + + false + + + + + + pcie_cfg_ext + pcie4_us_cfg_ext + Configuration Extend Interface + + + + + + + function_number + + + cfg_ext_function_number + + + + + read_data + + + cfg_ext_read_data + + + + + read_data_valid + + + cfg_ext_read_data_valid + + + + + read_received + + + cfg_ext_read_received + + + + + register_number + + + cfg_ext_register_number + + + + + write_byte_enable + + + cfg_ext_write_byte_enable + + + + + write_data + + + cfg_ext_write_data + + + + + write_received + + + cfg_ext_write_received + + + + + + + false + + + + + + CLK.ext_ch_gt_drpclk + + + + + + + CLK + + + ext_ch_gt_drpclk + + + + + + ASSOCIATED_BUSIF + pcie_ext_ch_gt + + + FREQ_HZ + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + + false + + + + + + pcie_ext_pipe_rp_usp + pcie3_ext_pipe_rp_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_in + + + + + COMMANDS_OUT + + + common_commands_out + + + + + RX_0 + + + pipe_rx_0_sigs + + + + + RX_1 + + + pipe_rx_1_sigs + + + + + RX_2 + + + pipe_rx_2_sigs + + + + + RX_3 + + + pipe_rx_3_sigs + + + + + RX_4 + + + pipe_rx_4_sigs + + + + + RX_5 + + + pipe_rx_5_sigs + + + + + RX_6 + + + pipe_rx_6_sigs + + + + + RX_7 + + + pipe_rx_7_sigs + + + + + RX_8 + + + pipe_rx_8_sigs + + + + + RX_9 + + + pipe_rx_9_sigs + + + + + RX_10 + + + pipe_rx_10_sigs + + + + + RX_11 + + + pipe_rx_11_sigs + + + + + RX_12 + + + pipe_rx_12_sigs + + + + + RX_13 + + + pipe_rx_13_sigs + + + + + RX_14 + + + pipe_rx_14_sigs + + + + + RX_15 + + + pipe_rx_15_sigs + + + + + TX_0 + + + pipe_tx_0_sigs + + + + + TX_1 + + + pipe_tx_1_sigs + + + + + TX_2 + + + pipe_tx_2_sigs + + + + + TX_3 + + + pipe_tx_3_sigs + + + + + TX_4 + + + pipe_tx_4_sigs + + + + + TX_5 + + + pipe_tx_5_sigs + + + + + TX_6 + + + pipe_tx_6_sigs + + + + + TX_7 + + + pipe_tx_7_sigs + + + + + TX_8 + + + pipe_tx_8_sigs + + + + + TX_9 + + + pipe_tx_9_sigs + + + + + TX_10 + + + pipe_tx_10_sigs + + + + + TX_11 + + + pipe_tx_11_sigs + + + + + TX_12 + + + pipe_tx_12_sigs + + + + + TX_13 + + + pipe_tx_13_sigs + + + + + TX_14 + + + pipe_tx_14_sigs + + + + + TX_15 + + + pipe_tx_15_sigs + + + + + + + false + + + + + + pcie_ext_pipe_ep_usp + pcie3_ext_pipe_ep_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + RX_8 + + + pipe_tx_8_sigs + + + + + RX_9 + + + pipe_tx_9_sigs + + + + + RX_10 + + + pipe_tx_10_sigs + + + + + RX_11 + + + pipe_tx_11_sigs + + + + + RX_12 + + + pipe_tx_12_sigs + + + + + RX_13 + + + pipe_tx_13_sigs + + + + + RX_14 + + + pipe_tx_14_sigs + + + + + RX_15 + + + pipe_tx_15_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + TX_8 + + + pipe_rx_8_sigs + + + + + TX_9 + + + pipe_rx_9_sigs + + + + + TX_10 + + + pipe_rx_10_sigs + + + + + TX_11 + + + pipe_rx_11_sigs + + + + + TX_12 + + + pipe_rx_12_sigs + + + + + TX_13 + + + pipe_rx_13_sigs + + + + + TX_14 + + + pipe_rx_14_sigs + + + + + TX_15 + + + pipe_rx_15_sigs + + + + + + + false + + + + + + pcie_ext_pipe_ep_legacy_usp + pcie3_ext_pipe_ep_legacy_usp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + RX_8 + + + pipe_tx_8_sigs + + + + + RX_9 + + + pipe_tx_9_sigs + + + + + RX_10 + + + pipe_tx_10_sigs + + + + + RX_11 + + + pipe_tx_11_sigs + + + + + RX_12 + + + pipe_tx_12_sigs + + + + + RX_13 + + + pipe_tx_13_sigs + + + + + RX_14 + + + pipe_tx_14_sigs + + + + + RX_15 + + + pipe_tx_15_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + TX_8 + + + pipe_rx_8_sigs + + + + + TX_9 + + + pipe_rx_9_sigs + + + + + TX_10 + + + pipe_rx_10_sigs + + + + + TX_11 + + + pipe_rx_11_sigs + + + + + TX_12 + + + pipe_rx_12_sigs + + + + + TX_13 + + + pipe_rx_13_sigs + + + + + TX_14 + + + pipe_rx_14_sigs + + + + + TX_15 + + + pipe_rx_15_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_rp + pcie3_ext_pipe_rp + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_in + + + + + COMMANDS_OUT + + + common_commands_out + + + + + RX_0 + + + pipe_rx_0_sigs + + + + + RX_1 + + + pipe_rx_1_sigs + + + + + RX_2 + + + pipe_rx_2_sigs + + + + + RX_3 + + + pipe_rx_3_sigs + + + + + RX_4 + + + pipe_rx_4_sigs + + + + + RX_5 + + + pipe_rx_5_sigs + + + + + RX_6 + + + pipe_rx_6_sigs + + + + + RX_7 + + + pipe_rx_7_sigs + + + + + TX_0 + + + pipe_tx_0_sigs + + + + + TX_1 + + + pipe_tx_1_sigs + + + + + TX_2 + + + pipe_tx_2_sigs + + + + + TX_3 + + + pipe_tx_3_sigs + + + + + TX_4 + + + pipe_tx_4_sigs + + + + + TX_5 + + + pipe_tx_5_sigs + + + + + TX_6 + + + pipe_tx_6_sigs + + + + + TX_7 + + + pipe_tx_7_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_ep + pcie3_ext_pipe_ep + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + + + false + + + + + + pcie3_ext_pipe_ep_legacy + pcie3_ext_pipe_ep_legacy + PCIE3 External PIPE Interface + + + + + + + COMMANDS_IN + + + common_commands_out + + + + + COMMANDS_OUT + + + common_commands_in + + + + + RX_0 + + + pipe_tx_0_sigs + + + + + RX_1 + + + pipe_tx_1_sigs + + + + + RX_2 + + + pipe_tx_2_sigs + + + + + RX_3 + + + pipe_tx_3_sigs + + + + + RX_4 + + + pipe_tx_4_sigs + + + + + RX_5 + + + pipe_tx_5_sigs + + + + + RX_6 + + + pipe_tx_6_sigs + + + + + RX_7 + + + pipe_tx_7_sigs + + + + + TX_0 + + + pipe_rx_0_sigs + + + + + TX_1 + + + pipe_rx_1_sigs + + + + + TX_2 + + + pipe_rx_2_sigs + + + + + TX_3 + + + pipe_rx_3_sigs + + + + + TX_4 + + + pipe_rx_4_sigs + + + + + TX_5 + + + pipe_rx_5_sigs + + + + + TX_6 + + + pipe_rx_6_sigs + + + + + TX_7 + + + pipe_rx_7_sigs + + + + + + + false + + + + + + dsc_bypass_c2h_0 + dsc_bypass_c2h_0 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_0 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_0 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_0 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_0 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_0 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_0 + + + + + + + false + + + + + + dsc_bypass_c2h_1 + dsc_bypass_c2h_1 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_1 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_1 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_1 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_1 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_1 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_1 + + + + + + + false + + + + + + dsc_bypass_c2h_2 + dsc_bypass_c2h_2 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_2 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_2 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_2 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_2 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_2 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_2 + + + + + + + false + + + + + + dsc_bypass_c2h_3 + dsc_bypass_c2h_3 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + c2h_dsc_byp_ctl_3 + + + + + dsc_byp_dst_addr + + + c2h_dsc_byp_dst_addr_3 + + + + + dsc_byp_len + + + c2h_dsc_byp_len_3 + + + + + dsc_byp_load + + + c2h_dsc_byp_load_3 + + + + + dsc_byp_ready + + + c2h_dsc_byp_ready_3 + + + + + dsc_byp_src_addr + + + c2h_dsc_byp_src_addr_3 + + + + + + + false + + + + + + dsc_bypass_h2c_0 + dsc_bypass_h2c_0 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_0 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_0 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_0 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_0 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_0 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_0 + + + + + + + false + + + + + + dsc_bypass_h2c_1 + dsc_bypass_h2c_1 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_1 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_1 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_1 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_1 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_1 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_1 + + + + + + + false + + + + + + dsc_bypass_h2c_2 + dsc_bypass_h2c_2 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_2 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_2 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_2 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_2 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_2 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_2 + + + + + + + false + + + + + + dsc_bypass_h2c_3 + dsc_bypass_h2c_3 + Descriptor Bypass Interface + + + + + + + dsc_byp_ctl + + + h2c_dsc_byp_ctl_3 + + + + + dsc_byp_dst_addr + + + h2c_dsc_byp_dst_addr_3 + + + + + dsc_byp_len + + + h2c_dsc_byp_len_3 + + + + + dsc_byp_load + + + h2c_dsc_byp_load_3 + + + + + dsc_byp_ready + + + h2c_dsc_byp_ready_3 + + + + + dsc_byp_src_addr + + + h2c_dsc_byp_src_addr_3 + + + + + + + false + + + + + + dma_status_ports + dma_status_ports + XDMA Status Ports Interface + + + + + + + c2h_sts0 + + + c2h_sts_0 + + + + + c2h_sts1 + + + c2h_sts_1 + + + + + c2h_sts2 + + + c2h_sts_2 + + + + + c2h_sts3 + + + c2h_sts_3 + + + + + h2c_sts0 + + + h2c_sts_0 + + + + + h2c_sts1 + + + h2c_sts_1 + + + + + h2c_sts2 + + + h2c_sts_2 + + + + + h2c_sts3 + + + h2c_sts_3 + + + + + + + false + + + + + + cap + cap + + + + + + + GNT + + + cap_gnt + + + + + REL + + + cap_rel + + + + + REQ + + + cap_req + + + + + + + false + + + + + + startup + startup + STARTUP Interface + + + + + + + cfgclk + + + startup_cfgclk + + + + + cfgmclk + + + startup_cfgmclk + + + + + di + + + startup_di + + + + + do + + + startup_do + + + + + dts + + + startup_dts + + + + + eos + + + startup_eos + + + + + fcsbo + + + startup_fcsbo + + + + + fcsbts + + + startup_fcsbts + + + + + gsr + + + startup_gsr + + + + + gts + + + startup_gts + + + + + keyclearb + + + startup_keyclearb + + + + + pack + + + startup_pack + + + + + preq + + + startup_preq + + + + + userdoneo + + + startup_usrdoneo + + + + + usrcclko + + + startup_usrcclko + + + + + usrclkts + + + startup_usrcclkts + + + + + usrdonets + + + startup_usrdonets + + + + + + + false + + + + + + atspri_s_axis_rq + atspri_s_axis_rq + The Requestor Request interface received requests TLP's from the Client Application + + + + + + + TDATA + + + atspri_s_axis_rq_tdata + + + + + TKEEP + + + atspri_s_axis_rq_tkeep + + + + + TLAST + + + atspri_s_axis_rq_tlast + + + + + TREADY + + + atspri_s_axis_rq_tready + + + + + TUSER + + + atspri_s_axis_rq_tuser + + + + + TVALID + + + atspri_s_axis_rq_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + atspri_m_axis_cq + atspri_m_axis_cq + The Completer Request interface is used to transmit Completion TLP's to the Client Application + + + + + + + TDATA + + + atspri_m_axis_cq_tdata + + + + + TKEEP + + + atspri_m_axis_cq_tkeep + + + + + TLAST + + + atspri_m_axis_cq_tlast + + + + + TREADY + + + atspri_m_axis_cq_tready + + + + + TUSER + + + atspri_m_axis_cq_tuser + + + + + TVALID + + + atspri_m_axis_cq_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + cfg_status_ats + cfg_status_ats + Configuration Status Interface For ATS + + + + + + + cfg_status_ats_en + + + cfg_status_ats_en + + + + + cfg_status_ats_stu + + + cfg_status_ats_stu + + + + + + + false + + + + + + cfg_status_pri + cfg_status_pri + Configuration Status Interface For PRI + + + + + + + cfg_status_clr_s + + + cfg_status_clr_s + + + + + cfg_status_ost_pr_alloc + + + cfg_status_ost_pr_alloc + + + + + cfg_status_pr_en + + + cfg_status_pr_en + + + + + cfg_status_pr_rf + + + cfg_status_pr_rf + + + + + cfg_status_pr_rst + + + cfg_status_pr_rst + + + + + cfg_status_pr_uprgi + + + cfg_status_pr_uprgi + + + + + cfg_status_set_rf + + + cfg_status_set_rf + + + + + cfg_status_set_s + + + cfg_status_set_s + + + + + cfg_status_set_uprgi + + + cfg_status_set_uprgi + + + + + + + false + + + + + + dma_debug_ports + XDMA Debug Ports + + + + + + + cc_tdata_out + + + m_axis_cc_tdata_out + + + + + cc_tkeep_out + + + m_axis_cc_tkeep_out + + + + + cc_tlast_out + + + m_axis_cc_tlast_out + + + + + cc_tready_out + + + m_axis_cc_tready_out + + + + + cc_tuser_out + + + m_axis_cc_tuser_out + + + + + cc_tvalid_out + + + m_axis_cc_tvalid_out + + + + + cq_tdata_out + + + s_axis_cq_tdata_out + + + + + cq_tkeep_out + + + s_axis_cq_tkeep_out + + + + + cq_tlast_out + + + s_axis_cq_tlast_out + + + + + cq_tready_out + + + s_axis_cq_tready_out + + + + + cq_tuser_out + + + s_axis_cq_tuser_out + + + + + cq_tvalid_out + + + s_axis_cq_tvalid_out + + + + + rc_tdata_out + + + s_axis_rc_tdata_out + + + + + rc_tkeep_out + + + s_axis_rc_tkeep_out + + + + + rc_tlast_out + + + s_axis_rc_tlast_out + + + + + rc_tready_out + + + s_axis_rc_tready_out + + + + + rc_tuser_out + + + s_axis_rc_tuser_out + + + + + rc_tvalid_out + + + s_axis_rc_tvalid_out + + + + + rq_tdata_out + + + m_axis_rq_tdata_out + + + + + rq_tkeep_out + + + m_axis_rq_tkeep_out + + + + + rq_tlast_out + + + m_axis_rq_tlast_out + + + + + rq_tready_out + + + m_axis_rq_tready_out + + + + + rq_tuser_out + + + m_axis_rq_tuser_out + + + + + rq_tvalid_out + + + m_axis_rq_tvalid_out + + + + + + + false + + + + + + pcie3_us_ext_shared_logic + pcie3_us_ext_shared_logic + PCIE3 Ultrascale External Shared Logic Interface + + + + + + + exts_qpll1lock_out + + + ext_qpll1lock_out + + + + + exts_qpll1outclk_out + + + ext_qpll1outclk_out + + + + + exts_qpll1outrefclk_out + + + ext_qpll1outrefclk_out + + + + + exts_qpll1pd + + + ext_qpll1pd + + + + + exts_qpll1rate + + + ext_qpll1rate + + + + + exts_qpll1refclk + + + ext_qpll1refclk + + + + + exts_qpll1reset + + + ext_qpll1reset + + + + + + + false + + + + + + pcie3_us_int_shared_logic + pcie3_us_int_shared_logic + PCIE3 Ultrascale Internal Shared Logic Interface + + + + + + + ints_qpll1lock_out + + + int_qpll1lock_out + + + + + ints_qpll1outclk_out + + + int_qpll1outclk_out + + + + + ints_qpll1outrefclk_out + + + int_qpll1outrefclk_out + + + + + + + false + + + + + + pcie4_usp_ext_gtcom + pcie4_usp_ext_gtcommon + PCIE4 Ultrascale+ External GT COMMON Interface + + + + + + + exts_qpll0lock_out + + + ext_usp_qpll0lock_out + + + + + exts_qpll0outclk_out + + + ext_usp_qpll0outclk_out + + + + + exts_qpll0outrefclk_out + + + ext_usp_qpll0outrefclk_out + + + + + exts_qpll0pd + + + ext_usp_qpll0pd + + + + + exts_qpll0reset + + + ext_usp_qpll0reset + + + + + exts_qpll1lock_out + + + ext_usp_qpll1lock_out + + + + + exts_qpll1outclk_out + + + ext_usp_qpll1outclk_out + + + + + exts_qpll1outrefclk_out + + + ext_usp_qpll1outrefclk_out + + + + + exts_qpll1pd + + + ext_usp_qpll1pd + + + + + exts_qpll1reset + + + ext_usp_qpll1reset + + + + + exts_qpllxrate + + + ext_usp_qpllxrate + + + + + exts_qpllxrcalenb + + + ext_usp_qpllxrcalenb + + + + + exts_qpllxrefclk + + + ext_usp_qpllxrefclk + + + + + + + false + + + + + + pcie4_usp_int_gtcom + pcie4_usp_int_gtcommon + PCIE4 Ultrascale+ Internal GT COMMON Interface + + + + + + + ints_qpll0lock_out + + + int_usp_qpll0lock_out + + + + + ints_qpll0outclk_out + + + int_usp_qpll0outclk_out + + + + + ints_qpll0outrefclk_out + + + int_usp_qpll0outrefclk_out + + + + + ints_qpll1lock_out + + + int_usp_qpll1lock_out + + + + + ints_qpll1outclk_out + + + int_usp_qpll1outclk_out + + + + + ints_qpll1outrefclk_out + + + int_usp_qpll1outrefclk_out + + + + + + + false + + + + + + pipe_clock + pipe_clock + PCIExpress Enternal PIPE Clock interface + + + + + + + dclk_in + + + pipe_dclk_in + + + + + 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0x0000000000000000 + + + C_AXIBAR_2 + 0x0000000000000000 + + + C_AXIBAR_3 + 0x0000000000000000 + + + C_AXIBAR_4 + 0x0000000000000000 + + + C_AXIBAR_5 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_0 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_1 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_2 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_3 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_4 + 0x0000000000000000 + + + C_AXIBAR_HIGHADDR_5 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_0 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_1 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_2 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_3 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_4 + 0x0000000000000000 + + + C_AXIBAR2PCIEBAR_5 + 0x0000000000000000 + + + EN_AXI_SLAVE_IF + Enable AXI Slave IF + TRUE + + + C_INCLUDE_BAROFFSET_REG + 1 + + + C_BASEADDR + 0x00001000 + + + C_HIGHADDR + 0x00001FFF + + + C_S_AXI_ID_WIDTH + 4 + + + C_S_AXI_NUM_READ + AXI Address width + 8 + + + C_M_AXI_NUM_READ + AXI Address width + 8 + + + C_S_AXI_NUM_WRITE + AXI Address width + 8 + + + C_M_AXI_NUM_WRITE + AXI Address width + 16 + + + MSIX_IMPL_EXT + FALSE + + + AXI_ACLK_LOOPBACK + FALSE + + + PF0_BAR0_APERTURE_SIZE + Pf0 Bar0 Aperture Size + 0x0A + + + PF0_BAR0_CONTROL + Pf0 Bar0 Control + 0x4 + + + PF0_BAR1_APERTURE_SIZE + Pf0 Bar1 Aperture Size + 0x05 + + + PF0_BAR1_CONTROL + Pf0 Bar1 Control + 0x0 + + + PF0_BAR2_APERTURE_SIZE + Pf0 Bar2 Aperture Size + 0x05 + + + PF0_BAR2_CONTROL + Pf0 Bar2 Control + 0x0 + + + PF0_BAR3_APERTURE_SIZE + Pf0 Bar3 Aperture Size + 0x05 + + + PF0_BAR3_CONTROL + Pf0 Bar3 Control + 0x0 + + + PF0_BAR4_APERTURE_SIZE + Pf0 Bar4 Aperture Size + 0x05 + + + PF0_BAR4_CONTROL + Pf0 Bar4 Control + 0x0 + + + PF0_BAR5_APERTURE_SIZE + Pf0 Bar5 Aperture Size + 0x05 + + + PF0_BAR5_CONTROL + Pf0 Bar5 Control + 0x0 + + + PCIEBAR_NUM + 6 + + + C_PCIEBAR2AXIBAR_0 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_1 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_2 + 0x0000000000000000 + + + C_PCIEBAR2AXIBAR_3 + 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PF1_BAR4_CONTROL + Pf0 Bar4 Control + 0x6 + + + PF1_BAR5_APERTURE_SIZE + Pf0 Bar5 Aperture Size + 0x0A + + + PF1_BAR5_CONTROL + Pf0 Bar5 Control + 0x0 + + + PF1_PCIEBAR2AXIBAR_0 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_1 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_2 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_3 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_4 + 0x0000000000000000 + + + PF1_PCIEBAR2AXIBAR_5 + 0x0000000000000000 + + + C_MSIX_INT_TABLE_EN + 0 + + + VU9P_TUL_EX + VU9P TUL board + FALSE + + + PCIE_BLK_TYPE + 0 + + + CCIX_ENABLE + Ccix Enable + FALSE + + + CCIX_DVSEC + Ccix Dvsec Enable + FALSE + + + EXT_SYS_CLK_BUFG + FALSE + + + C_NUM_OF_SC + 1 + + + USR_IRQ_EXDES + FALSE + + + AXI_VIP_IN_EXDES + FALSE + + + PIPE_DEBUG_EN + FALSE + + + XDMA_NON_INCREMENTAL_EXDES + FALSE + + + XDMA_ST_INFINITE_DESC_EXDES + FALSE + + + EXT_XVC_VSEC_ENABLE + Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design + FALSE + + + ACS_EXT_CAP_ENABLE + FALSE + + + EN_PCIE_DEBUG_PORTS + FALSE + + + MULTQ_EN + 0 + + + DMA_MM + 0 + + + DMA_ST + 1 + + + C_PCIE_PFS_SUPPORTED + 0 + + + C_SRIOV_EN + 0 + + + BARLITE_EXT_PF0 + 0x00 + + + BARLITE_EXT_PF1 + 0x00 + + + BARLITE_EXT_PF2 + 0x00 + + + BARLITE_EXT_PF3 + 0x00 + + + BARLITE_INT_PF0 + 0x01 + + + BARLITE_INT_PF1 + 0x00 + + + BARLITE_INT_PF2 + 0x00 + + + BARLITE_INT_PF3 + 0x00 + + + NUM_VFS_PF0 + 0 + + + NUM_VFS_PF1 + 0 + + + NUM_VFS_PF2 + 0 + + + NUM_VFS_PF3 + 0 + + + FIRSTVF_OFFSET_PF0 + 0 + + + FIRSTVF_OFFSET_PF1 + 0 + + + FIRSTVF_OFFSET_PF2 + 0 + + + FIRSTVF_OFFSET_PF3 + 0 + + + VF_BARLITE_EXT_PF0 + 0x00 + + + VF_BARLITE_EXT_PF1 + 0x00 + + + VF_BARLITE_EXT_PF2 + 0x00 + + + VF_BARLITE_EXT_PF3 + 0x00 + + + VF_BARLITE_INT_PF0 + 0x01 + + + VF_BARLITE_INT_PF1 + 0x01 + + + VF_BARLITE_INT_PF2 + 0x01 + + + VF_BARLITE_INT_PF3 + 0x01 + + + C_C2H_NUM_CHNL + 1 + + + C_H2C_NUM_CHNL + 1 + + + H2C_XDMA_CHNL + 0x0F + + + C2H_XDMA_CHNL + 0x0F + + + AXISTEN_IF_ENABLE_MSG_ROUTE + 0x00000 + + + ENABLE_MORE + FALSE + + + DISABLE_BRAM_PIPELINE + FALSE + + + DISABLE_EQ_SYNCHRONIZER + FALSE + + + C_ENABLE_RESOURCE_REDUCTION + FALSE + + + GEN4_EIEOS_0S7 + TRUE + + + C_S_AXI_SUPPORTS_NARROW_BURST + 0 + + + ENABLE_ATS_SWITCH + ATS Switch Enable + FALSE + + + C_ATS_SWITCH_UNIQUE_BDF + 1 + + + C_LAST_CORE_CAP_ADDR + 0x100 + + + C_VSEC_CAP_ADDR + 0x128 + + + SOFT_RESET_EN + FALSE + + + INTERRUPT_OUT_WIDTH + 1 + + + C_MSI_RX_PIN_EN + 0 + + + C_INTX_RX_PIN_EN + 1 + + + PCIE_ID_IF + FALSE + + + TL_PF_ENABLE_REG + 0 + + + AXSIZE_BYTE_ACCESS_EN + FALSE + + + + + + choice_list_08bf412c + 128 + 256 + 512 + + + choice_list_0be33969 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + + + choice_list_0f93492c + Chip-to-Chip + Add-in_Card + Backplane + + + choice_list_110bd32e + 2 + 4 + + + choice_list_1cfc6134 + 1 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_1e9fb93b + X1 + X2 + X4 + X8 + X16 + + + choice_list_24b724fb + Basic + Advanced + + + choice_list_2dba17cd + None + Check_Parity + Propagate_Parity + + + choice_list_34d65ff4 + 128 + + + choice_list_35d06715 + 2 + + + choice_list_38306dd1 + SOFT + HARD + + + choice_list_3ca2cbc7 + BAR_0 + + + choice_list_3cee6ea1 + 16450_compatible_serial_controller + 16550_compatible_serial_controller + 16650_compatible_serial_controller + 16750_compatible_serial_controller + 16850_compatible_serial_controller + 16950_compatible_serial_controller + Bi_directional_parallel_port + ECP_1.X_compliant_parallel_port + GPIB(IEEE_488.1/2)_controller + Generic_XT_compatible_serial_controller + Generic_modem + Hayes_compatible_modem_with_16450_compatible_interface + Hayes_compatible_modem_with_16550_compatible_interface + Hayes_compatible_modem_with_16650_compatible_interface + Hayes_compatible_modem_with_16750_compatible_interface + IEEE_1284_controller + IEEE_1284_target_device + Multiport_serial_controller + Other_communications_device + Parallel_port + Smart_Card + + + choice_list_4665eb01 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choice_list_47140c0d + 0000 + 0001 + + + choice_list_4a68658a + None + Tandem_PROM + Tandem_PCIe + Tandem_PCIe_with_Field_Updates + PR_over_PCIe + + + choice_list_4e419c85 + Default + Falling_Edge + + + choice_list_504db607 + GTY_Quad_228 + GTY_Quad_227 + GTY_Quad_226 + GTY_Quad_225 + GTY_Quad_224 + + + choice_list_52d29139 + Bytes + Kilobytes + Megabytes + Gigabytes + + + choice_list_574f38f3 + 2.5_GT/s + 5.0_GT/s + 8.0_GT/s + + + choice_list_57749bc8 + DMA + + + choice_list_589df8e9 + RAM + Other_memory_controller + Flash + + + choice_list_5e150e6c + 50us + 50ms + + + choice_list_5e2921cd + Kilobytes + + + choice_list_5e45706a + 1_vector + 2_vectors + 4_vectors + 8_vectors + 16_vectors + 32_vectors + + + choice_list_640e51e1 + DMA + AXI_Bridge + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_6a0870a7 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + 30 + 31 + + + choice_list_6b979ebc + 250 + + + choice_list_6eff49bd + ACTIVE_LOW + ACTIVE_HIGH + + + choice_list_7a7dde49 + true + false + + + choice_list_8112d406 + 8 + 16 + 32 + + + choice_list_81ddc592 + Kilobytes + Megabytes + Gigabytes + Terabytes + Petabytes + Exabytes + + + choice_list_86c5d341 + 500 + + + choice_list_88156f2e + QPLL1 + QPLL0 + + + choice_list_8a9e69a3 + AXI_Lite_Master + DMA + + + choice_list_8aad6ae4 + 1 + 2 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_8b5e4915 + 4 + 5 + + + choice_list_914704bd + 100_MHz + 125_MHz + + + choice_list_91b49d0b + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + + + choice_list_97bc19ec + 256_bit + + + choice_list_993a8980 + Wireless_controller + Satellite_communication_controllers + Data_acquisition_and_signal_processing_controllers + Intelligent_I/O_controllers + Docking_stations + Device_was_built_before_Class_Code_definitions_were_finalized + Memory_controller + Simple_communication_controllers + Serial_bus_controllers + Encryption/Decryption_controllers + Display_controller + Multimedia_device + Input_devices + Mass_storage_controller + Processors + Device_does_not_fit_in_any_defined_classes + Bridge_device + Network_controller + Base_system_peripherals + + + choice_list_9aec9108 + Internal + External + + + choice_list_9e15bd51 + CONSTANT + + + choice_list_9f5580fd + Pre-Production + + + choice_list_a71f3969 + AXI_Memory_Mapped + AXI_Stream + + + choice_list_a8dbd818 + X0Y1 + X0Y3 + X1Y2 + X1Y4 + + + choice_list_aa031417 + 1 + 2 + 3 + 4 + + + choice_list_ab8591cd + PCI_Express_Endpoint_device + PCI_Express_Endpoint_device + + + choice_list_ac75ef1e + Custom + + + choice_list_ae9f88f6 + 1 + + + choice_list_b0ffef10 + 0 + 1 + 2 + 3 + 4 + 5 + 7 + + + choice_list_bdd7203f + True + False + + + choice_list_bea500ca + None + MSI-X_External + MSI-X_Internal + MSI-X_AXI4-Stream + + + choice_list_c0448d62 + None + VCU117 + VCU119 + ZCU117 + KCU116 + VCU1262 + VCU1299 + VCU1525 + KC705 + KCU1500 + XIL-ACCEL-RD-VU9P + XIL-ACCEL-RD-KU115 + VCU1550 + XBB1551 + + + choice_list_c15e8c67 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_c3d223d9 + Memory + + + choice_list_c63ab5b1 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + choice_list_ca005b72 + No_ASPM + L1_Supported + + + choice_list_ca108395 + 2 + 4 + 8 + 16 + 32 + + + choice_list_d123c74c + Bytes + Kilobytes + Megabytes + + + choice_list_d1e1a340 + Kilobytes + Megabytes + Gigabytes + + + choice_list_d4378f0e + Simple_communication_controllers + Device_was_built_before_Class_Code_definitions_were_finalized + Mass_storage_controller + Network_controller + Display_controller + Multimedia_device + Memory_controller + Base_system_peripherals + Input_devices + Docking_stations + Processors + Serial_bus_controllers + Wireless_controller + Intelligent_I/O_controllers + Satellite_communication_controllers + + + choice_list_d53faa96 + 100_MHz + 125_MHz + 250_MHz + + + choice_list_d85ad257 + 0 + + + choice_list_df7cde9e + RAM + Flash + Other_memory_controller + + + choice_list_e7c484ae + TRUE + FALSE + + + choice_list_e7f13338 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_e9cf6440 + Disabled + 32bit_Enabled + 64bit_Enabled + + + choice_list_ec64e624 + N/A + + + choice_list_f1174048 + NONE + INTA + INTB + INTC + INTD + + + choice_list_f94ec5c4 + 4 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_fab783d7 + User_Reset + Phy_Ready + + + choice_list_fc3456a9 + Disabled + Enabled + + + choice_list_fe1fb7c4 + 0 + 4 + 8 + 12 + 16 + + + choice_pairs_3c87fcdb + 1 + 0 + + + choice_pairs_3f7a0c72 + BAR_0 + 0 + BAR_1 + 1 + BAR_2 + 2 + + + choice_pairs_53749dec + 1 + 0 + + + choice_pairs_6f00a734 + 0 + 1 + 2 + + + + + xilinx_elaboratesubcores_view_fileset + + ip_0/xdma_pcie4_ip.xci + xci + + + ip_0/xdma_pcie4_ip.xml + xml + + + ip_1/xdma_v4_1_1_blk_mem_64_reg_be.xci + xci + + + ip_1/xdma_v4_1_1_blk_mem_64_reg_be.xml + xml + + + ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xci + xci + + + ip_2/xdma_v4_1_1_blk_mem_64_noreg_be.xml + xml + + + + The Xilinx PCI Express DMA + + + Component_Name + xdma + + + + true + + + + + + functional_mode + Functional Mode + DMA + + + + true + + + + + + mode_selection + Mode + Basic + + + + true + + + + + + device_port_type + Device Port Type + PCI_Express_Endpoint_device + + + + false + + + + + + pcie_blk_locn + Pcie Blk Locn + X1Y2 + + + + true + + + + + + pl_link_cap_max_link_width + Pl Link Cap Max Link Width + X8 + + + + true + + + + + + pl_link_cap_max_link_speed + Pl Link Cap Max Link Speed + 8.0_GT/s + + + + true + + + + + + ref_clk_freq + 100_MHz + + + + true + + + + + + drp_clk_sel + Internal + + + + false + + + + + + free_run_freq + 100_MHz + + + + true + + + + + + axi_addr_width + AXI Address width + 64 + + + + false + + + + + + axi_data_width + AXI Data width + 256_bit + + + + true + + + + + + axisten_freq + AXIsten if freq + 250 + + + + true + + + + + + en_axi_slave_if + Enable AXI Slave Interface + true + + + + true + + + + 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xdma_sts_ports + false + + + pf0_msix_enabled + Pf0 Msix Enabled + false + + + pf0_msix_cap_table_size + Pf0 Msix Cap Table Size + 000 + + + + false + + + + + + pf0_msix_cap_table_offset + Pf0 Msix Cap Table Offset + 00000000 + + + + false + + + + + + pf0_msix_cap_table_bir + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + pf0_msix_cap_pba_offset + Pf0 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + pf0_msix_cap_pba_bir + Pf0 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + pf1_msix_enabled + Pf1 Msix Enabled + false + + + pf1_msix_cap_table_size + Pf1 Msix Cap Table Size + 020 + + + pf1_msix_cap_table_offset + Pf1 Msix Cap Table Offset + 00009000 + + + pf1_msix_cap_table_bir + Pf1 Msix Cap Table Bir + BAR_0 + + + pf1_msix_cap_pba_offset + Pf1 Msix Cap Pba Offset + 00009FE0 + + + pf1_msix_cap_pba_bir + Pf1 Msix Cap Pba Bir + BAR_0 + + + cfg_mgmt_if + true + + + + true + + + + + + ins_loss_profile + Add-in_Card + + + axil_master_64bit_en + false + + + + false + + + + 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pf0_bar5_64bit + Pf0 Bar0 64bit + false + + + + false + + + + + + pf0_bar5_prefetchable + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + bar_indicator + BAR_0 + + + + false + + + + + + bar0_indicator + 1 + + + + true + + + + + + bar1_indicator + 0 + + + + true + + + + + + bar2_indicator + 0 + + + + true + + + + + + bar3_indicator + 0 + + + + true + + + + + + bar4_indicator + 0 + + + + true + + + + + + bar5_indicator + 0 + + + + true + + + + + + barlite2 + 7 + + + en_dbg_descramble + false + + + vcu118_board + false + + + tl_pf_enable_reg + NUM PF Enable + 1 + + + pf1_vendor_id + Vendor Id + 10EE + + + pf1_device_id + PF1 Device Id + 1041 + + + pf1_class_code + Pf1 Class Code + 070001 + + + + false + + + + + + PF1_REVISION_ID + Pf1 Revision Id + 00 + + + PF1_SUBSYSTEM_VENDOR_ID + Pf1 Subsystem Vendor Id + 10EE + + + PF1_SUBSYSTEM_ID + Pf1 Subsystem Id + 0007 + + + PF1_Use_Class_Code_Lookup_Assistant + false + + + + true + + + + + + pf1_base_class_menu + Pf1 Base Class Menu + Simple_communication_controllers + + + pf1_class_code_base + Pf1 Class Code Base + 07 + + + + true + + + + + + pf1_class_code_sub + Pf1 Class Code Sub + 00 + + + + true + + + + + + pf1_sub_class_interface_menu + Pf1 Sub Class Interface Menu + 16450_compatible_serial_controller + + + + true + + + + + + pf1_class_code_interface + Pf1 Class Code Interface + 01 + + + + true + + + + + + PF1_INTERRUPT_PIN + Pf1 Interrupt Pin + NONE + + + pf1_msi_enabled + Pf1 Msi Enabled + false + + + PF1_MSI_CAP_MULTIMSGCAP + Pf1 Msi Cap Multimsgcap + 1_vector + + + pf1_bar0_enabled + Pf1 Bar0 Enabled + true + + + pf1_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar0_size + Pf1 Bar0 Size + 32 + + + pf1_bar0_scale + Pf1 Bar0 Scale + Megabytes + + + pf1_bar0_64bit + Pf1 Bar0 64bit + false + + + pf1_bar0_prefetchable + Pf1 Bar0 Prefetchable + false + + + pf1_bar1_enabled + Pf1 Bar1 Enabled + true + + + pf1_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar1_size + Pf1 Bar1 Size + 128 + + + pf1_bar1_scale + Pf1 Bar1 Scale + Kilobytes + + + pf1_bar1_64bit + Pf1 Bar1 64bit + false + + + pf1_bar1_prefetchable + Pf1 Bar1 Prefetchable + false + + + pf1_bar2_enabled + Pf1 Bar2 Enabled + true + + + pf1_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar2_size + Pf1 Bar2 Size + 128 + + + pf1_bar2_scale + Pf1 Bar2 Scale + Kilobytes + + + pf1_bar2_64bit + Pf1 Bar2 64bit + true + + + pf1_bar2_prefetchable + Pf1 Bar2 Prefetchable + false + + + pf1_bar3_enabled + Pf1 Bar3 Enabled + false + + + + false + + + + + + pf1_bar3_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf1_bar3_size + Pf1 Bar3 Size + 128 + + + + false + + + + + + pf1_bar3_scale + Pf1 Bar3 Scale + Kilobytes + + + + false + + + + + + pf1_bar3_64bit + Pf1 Bar3 64bit + false + + + pf1_bar3_prefetchable + Pf1 Bar3 Prefetchable + false + + + + false + + + + + + pf1_bar4_enabled + Pf1 Bar4 Enabled + true + + + pf1_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf1_bar4_size + Pf1 Bar4 Size + 128 + + + pf1_bar4_scale + Pf1 Bar4 Scale + Kilobytes + + + pf1_bar4_64bit + Pf1 Bar4 64bit + true + + + pf1_bar4_prefetchable + Pf1 Bar4 Prefetchable + false + + + pf1_bar5_enabled + Pf1 Bar5 Enabled + false + + + + false + + + + + + pf1_bar5_type + Pf0 Bar0 Type + Memory + + + + false + + + + + + pf1_bar5_size + Pf1 Bar5 Size + 128 + + + + false + + + + + + pf1_bar5_scale + Pf1 Bar5 Scale + Kilobytes + + + + false + + + + + + pf1_bar5_prefetchable + Pf1 Bar5 Prefetchable + false + + + + false + + + + + + pf2_device_id + PF2 Device Id + 1040 + + + pf2_class_code + pf2 Class Code + 058000 + + + PF2_REVISION_ID + pf2 Revision Id + 00 + + + PF2_SUBSYSTEM_VENDOR_ID + pf2 Subsystem Vendor Id + 10EE + + + PF2_SUBSYSTEM_ID + pf2 Subsystem Id + 0007 + + + PF2_Use_Class_Code_Lookup_Assistant + false + + + pf2_base_class_menu + pf2 Base Class Menu + Memory_controller + + + pf2_class_code_base + pf2 Class Code Base + 05 + + + pf2_class_code_sub + pf2 Class Code Sub + 80 + + + pf2_sub_class_interface_menu + pf2 Sub Class Interface Menu + Other_memory_controller + + + pf2_class_code_interface + pf2 Class Code Interface + 00 + + + PF2_INTERRUPT_PIN + pf2 Interrupt Pin + NONE + + + pf2_msi_enabled + pf2 Msi Enabled + false + + + PF2_MSI_CAP_MULTIMSGCAP + pf2 Msi Cap Multimsgcap + 1_vector + + + pf2_bar0_enabled + pf2 Bar0 Enabled + true + + + pf2_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar0_size + pf2 Bar0 Size + 128 + + + pf2_bar0_scale + pf2 Bar0 Scale + Kilobytes + + + pf2_bar0_64bit + pf2 Bar0 64bit + false + + + pf2_bar0_prefetchable + pf2 Bar0 Prefetchable + false + + + pf2_bar1_enabled + pf2 Bar1 Enabled + true + + + pf2_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar1_size + pf2 Bar1 Size + 128 + + + pf2_bar1_scale + pf2 Bar1 Scale + Kilobytes + + + pf2_bar1_64bit + pf2 Bar1 64bit + false + + + pf2_bar1_prefetchable + pf2 Bar1 Prefetchable + false + + + pf2_bar2_enabled + pf2 Bar2 Enabled + true + + + pf2_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar2_size + pf2 Bar2 Size + 128 + + + pf2_bar2_scale + pf2 Bar2 Scale + Kilobytes + + + pf2_bar2_64bit + pf2 Bar2 64bit + false + + + pf2_bar2_prefetchable + pf2 Bar2 Prefetchable + false + + + pf2_bar3_enabled + pf2 Bar3 Enabled + true + + + pf2_bar3_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar3_size + pf2 Bar3 Size + 128 + + + pf2_bar3_scale + pf2 Bar3 Scale + Kilobytes + + + pf2_bar3_64bit + pf2 Bar3 64bit + false + + + pf2_bar3_prefetchable + pf2 Bar3 Prefetchable + false + + + pf2_bar4_enabled + pf2 Bar4 Enabled + true + + + pf2_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar4_size + pf2 Bar4 Size + 128 + + + pf2_bar4_scale + pf2 Bar4 Scale + Kilobytes + + + pf2_bar4_64bit + pf2 Bar4 64bit + false + + + pf2_bar4_prefetchable + pf2 Bar4 Prefetchable + false + + + pf2_bar5_enabled + pf2 Bar5 Enabled + true + + + pf2_bar5_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf2_bar5_size + pf2 Bar5 Size + 128 + + + pf2_bar5_scale + pf2 Bar5 Scale + Kilobytes + + + pf2_bar5_prefetchable + pf2 Bar5 Prefetchable + false + + + pf3_device_id + PF3 Device Id + 1039 + + + pf3_class_code + Pf3 Class Code + 058000 + + + PF3_REVISION_ID + Pf3 Revision Id + 00 + + + PF3_SUBSYSTEM_VENDOR_ID + Pf3 Subsystem Vendor Id + 10EE + + + PF3_SUBSYSTEM_ID + Pf3 Subsystem Id + 0007 + + + PF3_Use_Class_Code_Lookup_Assistant + false + + + pf3_base_class_menu + Pf3 Base Class Menu + Memory_controller + + + pf3_class_code_base + Pf3 Class Code Base + 05 + + + pf3_class_code_sub + Pf3 Class Code Sub + 80 + + + pf3_sub_class_interface_menu + Pf3 Sub Class Interface Menu + Other_memory_controller + + + pf3_class_code_interface + Pf3 Class Code Interface + 00 + + + PF3_INTERRUPT_PIN + Pf3 Interrupt Pin + NONE + + + pf3_msi_enabled + Pf3 Msi Enabled + false + + + PF3_MSI_CAP_MULTIMSGCAP + Pf3 Msi Cap Multimsgcap + 1_vector + + + pf3_bar0_enabled + Pf3 Bar0 Enabled + true + + + pf3_bar0_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar0_size + Pf3 Bar0 Size + 128 + + + pf3_bar0_scale + Pf3 Bar0 Scale + Kilobytes + + + pf3_bar0_64bit + Pf3 Bar0 64bit + false + + + pf3_bar0_prefetchable + Pf3 Bar0 Prefetchable + false + + + pf3_bar1_enabled + Pf3 Bar1 Enabled + true + + + pf3_bar1_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar1_size + Pf3 Bar1 Size + 128 + + + pf3_bar1_scale + Pf3 Bar1 Scale + Kilobytes + + + pf3_bar1_64bit + Pf3 Bar1 64bit + false + + + pf3_bar1_prefetchable + Pf3 Bar1 Prefetchable + false + + + pf3_bar2_enabled + Pf3 Bar2 Enabled + true + + + pf3_bar2_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar2_size + Pf3 Bar2 Size + 128 + + + pf3_bar2_scale + Pf3 Bar2 Scale + Kilobytes + + + pf3_bar2_64bit + Pf3 Bar2 64bit + false + + + pf3_bar2_prefetchable + Pf3 Bar2 Prefetchable + false + + + pf3_bar3_enabled + Pf3 Bar3 Enabled + true + + + pf3_bar3_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar3_size + Pf3 Bar3 Size + 128 + + + pf3_bar3_scale + Pf3 Bar3 Scale + Kilobytes + + + pf3_bar3_64bit + Pf3 Bar3 64bit + false + + + pf3_bar3_prefetchable + Pf3 Bar3 Prefetchable + false + + + pf3_bar4_enabled + Pf3 Bar4 Enabled + true + + + pf3_bar4_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar4_size + Pf3 Bar4 Size + 128 + + + pf3_bar4_scale + Pf3 Bar4 Scale + Kilobytes + + + pf3_bar4_64bit + Pf3 Bar4 64bit + false + + + pf3_bar4_prefetchable + Pf3 Bar4 Prefetchable + false + + + pf3_bar5_enabled + Pf3 Bar5 Enabled + true + + + pf3_bar5_type + Pf0 Bar0 Type + Memory + + + + true + + + + + + pf3_bar5_size + Pf3 Bar5 Size + 128 + + + pf3_bar5_scale + Pf3 Bar5 Scale + Kilobytes + + + pf3_bar5_prefetchable + Pf3 Bar5 Prefetchable + false + + + split_dma + false + + + mult_pf_des + false + + + xlnx_ref_board + Xlnx Ref Board + None + + + + true + + + + + + en_l23_entry + false + + + pf1_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf1_pciebar2axibar_2 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf1_pciebar2axibar_4 + 0x0000000000000000 + + + + true + + + + + + pf1_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf2_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pf2_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_0 + 0x0000000000000000 + + + + true + + + + + + pf3_pciebar2axibar_1 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_2 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_3 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_4 + 0x0000000000000000 + + + + false + + + + + + pf3_pciebar2axibar_5 + 0x0000000000000000 + + + + false + + + + + + gtwiz_in_core_us + 1 + + + gtwiz_in_core_usp + 1 + + + dma_reset_source_sel + User_Reset + + + en_dma_and_bridge + false + + + en_coreclk_es1 + false + + + pipe_line_stage + number of Pipe Line Stages + 2 + + + + false + + + + + + axis_pipe_line_stage + number of Pipe Line Stages on PCIe axis interface + 0 + + + + false + + + + + + vu9p_tul_ex + false + + + vcu1525_ddr_ex + false + + + en_bridge + false + + + enable_ccix + FALSE + + + enable_dvsec + FALSE + + + ext_sys_clk_bufg + false + + + usr_irq_exdes + false + + + axi_vip_in_exdes + false + + + xdma_non_incremental_exdes + false + + + xdma_st_infinite_desc_exdes + false + + + gtcom_in_core_usp + 2 + + + en_mqdma + false + + + SRIOV_CAP_ENABLE + false + + + + false + + + + + + ext_xvc_vsec_enable + Enable to add the PCIe XVC-VSEC to the Examlpe Design + false + + + + false + + + + + + acs_ext_cap_enable + ACS Ext Capability + false + + + pf0_bar0_enabled_mqdma + Pf0 Bar1 Enabled + true + + + pf0_bar0_type_mqdma + Pf0 Bar0 Type + DMA + + + pf0_bar0_64bit_mqdma + Pf0 Bar0 64bit + false + + + pf0_bar0_prefetchable_mqdma + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf0_bar0_scale_mqdma + Pf0 Bar0 Scale + Kilobytes + + + pf0_bar0_size_mqdma + Pf0 Bar0 Size + 128 + + + pf0_bar1_enabled_mqdma + Pf0 Bar1 Enabled + false + + + pf0_bar1_type_mqdma + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf0_bar1_64bit_mqdma + Pf0 Bar1 64bit + false + + + + false + + + + + + pf0_bar1_prefetchable_mqdma + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf0_bar1_scale_mqdma + Pf0 Bar1 Scale + Kilobytes + + + + false + + + + + + pf0_bar1_size_mqdma + Pf0 Bar1 Size + 128 + + + + false + + + + + + pf0_bar2_enabled_mqdma + Pf0 Bar2 Enabled + false + + + pf0_bar2_type_mqdma + Pf0 Bar2 Type + N/A + + + + false + + + + + + pf0_bar2_64bit_mqdma + Pf0 Bar2 64bit + false + + + + false + + + + + + pf0_bar2_prefetchable_mqdma + Pf0 Bar2 Prefetchable + false + + + + false + + + + + + pf0_bar2_scale_mqdma + Pf0 Bar2 Scale + Kilobytes + + + + false + + + + + + pf0_bar2_size_mqdma + Pf0 Bar2 Size + 128 + + + + false + + + + + + pf0_bar3_enabled_mqdma + Pf0 Bar3 Enabled + false + + + pf0_bar3_type_mqdma + Pf0 Bar3 Type + N/A + + + + false + + + + + + pf0_bar3_64bit_mqdma + Pf0 Bar3 64bit + false + + + + false + + + + + + pf0_bar3_prefetchable_mqdma + Pf0 Bar3 Prefetchable + false + + + + false + + + + + + pf0_bar3_scale_mqdma + Pf0 Bar3 Scale + Kilobytes + + + + false + + + + + + pf0_bar3_size_mqdma + Pf0 Bar3 Size + 128 + + + + false + + + + + + pf0_bar4_enabled_mqdma + Pf0 Bar4 Enabled + false + + + pf0_bar4_type_mqdma + Pf0 Bar4 Type + N/A + + + + false + + + + + + pf0_bar4_64bit_mqdma + Pf0 Bar4 64bit + false + + + + false + + + + + + pf0_bar4_prefetchable_mqdma + Pf0 Bar4 Prefetchable + false + + + + false + + + + + + pf0_bar4_scale_mqdma + Pf0 Bar4 Scale + Kilobytes + + + + false + + + + + + pf0_bar4_size_mqdma + Pf0 Bar4 Size + 128 + + + + false + + + + + + pf0_bar5_enabled_mqdma + Pf0 Bar5 Enabled + false + + + pf0_bar5_type_mqdma + Pf0 Bar5 Type + N/A + + + + false + + + + + + pf0_bar5_prefetchable_mqdma + Pf0 Bar5 Prefetchable + false + + + pf0_bar5_scale_mqdma + Pf0 Bar5 Scale + Kilobytes + + + + false + + + + + + pf0_bar5_size_mqdma + Pf0 Bar5 Size + 128 + + + + false + + + + + + pf1_bar0_enabled_mqdma + Pf0 Bar0 Enabled + true + + + + false + + + + + + pf1_bar0_type_mqdma + Pf0 Bar0 Type + DMA + + + + false + + + + + + pf1_bar0_64bit_mqdma + Pf0 Bar0 64bit + false + + + + false + + + + + + pf1_bar0_prefetchable_mqdma + Pf0 Bar0 Prefetchable + false + + + + false + + + + + + pf1_bar0_scale_mqdma + Pf0 Bar0 Scale + Kilobytes + + + + false + + + + + + pf1_bar0_size_mqdma + Pf0 Bar0 Size + 128 + + + + false + + + + + + pf1_bar1_enabled_mqdma + Pf0 Bar1 Enabled + false + + + + false + + + + + + pf1_bar1_type_mqdma + Pf0 Bar1 Type + N/A + + + + false + + + + + + pf1_bar1_64bit_mqdma + Pf0 Bar1 64bit + false + + + + false + + + + + + pf1_bar1_prefetchable_mqdma + Pf0 Bar1 Prefetchable + false + + + + false + + + + + + pf1_bar1_scale_mqdma + Pf0 Bar1 Scale + Kilobytes + + + + false + + + + + + pf1_bar1_size_mqdma + Pf0 Bar1 Size + 128 + + + + false + + + + + + pf1_bar2_enabled_mqdma + Pf0 Bar2 Enabled + false + + + + false + + + + + + pf1_bar2_type_mqdma + Pf0 Bar2 Type + N/A + + + + false + + + + + + pf1_bar2_64bit_mqdma + Pf0 Bar2 64bit + false + + + + false + + + + + + pf1_bar2_prefetchable_mqdma + Pf0 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Sriov Bar0 Size + 2 + + + + false + + + + + + pf3_sriov_bar5_scale + Pf0 Sriov Bar0 Scale + Kilobytes + + + + false + + + + + + pcie_id_if + FALSE + + + pf0_vendor_id_mqdma + Vendor Id + 10EE + + + pf1_vendor_id_mqdma + Vendor Id + 10EE + + + pf2_vendor_id_mqdma + Vendor Id + 10EE + + + pf3_vendor_id_mqdma + Vendor Id + 10EE + + + PF0_DEVICE_ID_mqdma + Pf2 Device Id + 9038 + + + PF1_DEVICE_ID_mqdma + Pf2 Device Id + 0007 + + + PF2_DEVICE_ID_mqdma + Pf2 Device Id + 9038 + + + PF3_DEVICE_ID_mqdma + Pf3 Device Id + 9038 + + + PF0_REVISION_ID_mqdma + Pf2 Revision Id + 00 + + + PF1_REVISION_ID_mqdma + Pf2 Revision Id + 00 + + + PF2_REVISION_ID_mqdma + Pf2 Revision Id + 00 + + + PF3_REVISION_ID_mqdma + Pf3 Revision Id + 00 + + + PF0_SUBSYSTEM_VENDOR_ID_mqdma + Pf2 Subsystem Vendor Id + 10EE + + + PF1_SUBSYSTEM_VENDOR_ID_mqdma + Pf2 Subsystem Vendor Id + 10EE + + + PF2_SUBSYSTEM_VENDOR_ID_mqdma + Pf2 Subsystem Vendor Id + 10EE + + + PF3_SUBSYSTEM_VENDOR_ID_mqdma + Pf3 Subsystem Vendor Id + 10EE + + + PF0_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF1_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF2_SUBSYSTEM_ID_mqdma + Pf2 Subsystem Id + 0007 + + + PF3_SUBSYSTEM_ID_mqdma + Pf3 Subsystem Id + 0007 + + + pf0_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf1_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf2_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf3_Use_Class_Code_Lookup_Assistant_mqdma + false + + + pf0_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf0_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf0_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf0_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf0_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf0_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + pf1_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf1_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf1_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf1_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf1_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf1_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + pf2_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf2_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf2_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf2_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf2_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf2_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + pf3_base_class_menu_mqdma + Pf1 Base Class Menu + Memory_controller + + + pf3_class_code_base_mqdma + Pf1 Class Code Base + 05 + + + + true + + + + + + pf3_class_code_sub_mqdma + Pf1 Class Code Sub + 80 + + + + true + + + + + + pf3_sub_class_interface_menu_mqdma + Pf1 Sub Class Interface Menu + Other_memory_controller + + + + true + + + + + + pf3_class_code_interface_mqdma + Pf1 Class Code Interface + 00 + + + + true + + + + + + pf3_class_code_mqdma + Pf1 Class Code + 058000 + + + + false + + + + + + SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 1 + + + pf0_sriov_cap_ver + Pf0 Sriov Cap Ver + 1 + + + PF0_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF0_SRIOV_FUNC_DEP_LINK + Pf0 Sriov Func Dep Link + 0000 + + + PF0_SRIOV_FIRST_VF_OFFSET + Pf0 Sriov First Vf Offset + 0 + + + PF0_SRIOV_VF_DEVICE_ID + Pf0 Sriov Vf Device Id + 0000 + + + PF0_SRIOV_SUPPORTED_PAGE_SIZE + Pf0 Sriov Supported Page Size + 00000553 + + + PF1_SRIOV_CAP_VER + Pf1 Sriov Cap Ver + 1 + + + + false + + + + + + PF1_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF1_SRIOV_FIRST_VF_OFFSET + Pf1 Sriov First Vf Offset + 0 + + + PF1_SRIOV_FUNC_DEP_LINK + Pf1 Sriov Func Dep Link + 0001 + + + + false + + + + + + PF1_SRIOV_SUPPORTED_PAGE_SIZE + Pf1 Sriov Supported Page Size + 00000553 + + + PF1_SRIOV_VF_DEVICE_ID + Pf1 Sriov Vf Device Id + 0000 + + + + false + + + + + + PF2_SRIOV_CAP_VER + Pf2 Sriov Cap Ver + 1 + + + + false + + + + + + PF2_SRIOV_CAP_INITIAL_VF + Pf0 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF2_SRIOV_FIRST_VF_OFFSET + Pf2 Sriov First Vf Offset + 0 + + + PF2_SRIOV_FUNC_DEP_LINK + Pf2 Sriov Func Dep Link + 0002 + + + + false + + + + + + PF2_SRIOV_SUPPORTED_PAGE_SIZE + Pf2 Sriov Supported Page Size + 00000553 + + + PF2_SRIOV_VF_DEVICE_ID + Pf2 Sriov Vf Device Id + 0000 + + + + false + + + + + + PF3_SRIOV_CAP_INITIAL_VF + Pf3 Sriov Cap Initial Vf + 0 + + + + false + + + + + + PF3_SRIOV_CAP_VER + Pf3 Sriov Cap Ver + 1 + + + + false + + + + + + PF3_SRIOV_FIRST_VF_OFFSET + Pf3 Sriov First Vf Offset + 0 + + + PF3_SRIOV_FUNC_DEP_LINK + Pf3 Sriov Func Dep Link + 0003 + + + + false + + + + + + PF3_SRIOV_SUPPORTED_PAGE_SIZE + Pf3 Sriov Supported Page Size + 00000553 + + + PF3_SRIOV_VF_DEVICE_ID + Pf3 Sriov Vf Device Id + 0000 + + + + false + + + + + + pf0_ari_enabled + Pf0 Ari Enabled + false + + + pf0_msix_enabled_mqdma + Pf0 Msix Enabled + false + + + pf1_msix_enabled_mqdma + Pf1 Msix Enabled + false + + + pf2_msix_enabled_mqdma + Pf2 Msix Enabled + false + + + pf3_msix_enabled_mqdma + Pf3 Msix Enabled + false + + + PF0_MSIX_CAP_TABLE_SIZE_mqdma + Pf0 Msix Cap Table Size + 000 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_SIZE_mqdma + Pf1 Msix Cap Table Size + 000 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_SIZE_mqdma + Pf2 Msix Cap Table Size + 000 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_SIZE_mqdma + Pf3 Msix Cap Table Size + 000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_OFFSET_mqdma + Pf0 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_OFFSET_mqdma + Pf1 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_OFFSET_mqdma + Pf2 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_OFFSET_mqdma + Pf3 Msix Cap Table Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_TABLE_BIR_mqdma + Pf0 Msix Cap Table Bir + BAR_0 + + + + false + + + + + + PF0_MSIX_CAP_PBA_OFFSET_mqdma + Pf0 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF1_MSIX_CAP_PBA_OFFSET_mqdma + Pf1 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF2_MSIX_CAP_PBA_OFFSET_mqdma + Pf2 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF3_MSIX_CAP_PBA_OFFSET_mqdma + Pf3 Msix Cap Pba Offset + 00000000 + + + + false + + + + + + PF0_MSIX_CAP_PBA_BIR_mqdma + Pf0 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF1_MSIX_CAP_PBA_BIR_mqdma + Pf1 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF2_MSIX_CAP_PBA_BIR_mqdma + Pf2 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + PF3_MSIX_CAP_PBA_BIR_mqdma + Pf3 Msix Cap Pba Bir + BAR_0 + + + + false + + + + + + MSI_X_OPTIONS + None + + + + false + + + + + + dsc_bypass_rd_out + 0000 + + + dsc_bypass_wr_out + 0000 + + + num_queues + 1 + + + enable_auto_rxeq + False + + + enable_pcie_debug + False + + + axisten_if_enable_msg_route + 27FFF + + + en_axi_mm_mqdma + true + + + + true + + + + + + en_axi_st_mqdma + false + + + + true + + + + + + enable_more_clk + false + + + tl_credits_cd + 15 + + + tl_credits_ch + 15 + + + set_finite_credit + false + + + disable_bram_pipeline + false + + + disable_eq_synchronizer + false + + + enable_resource_reduction + false + + + c_ats_enable + ATS Extended Capability Enable + false + + + c_pri_enable + Page Request Extended Capability Enable + false + + + usplus_es1_seqnum_bypass + false + + + bridge_registers_offset_enable + false + + + enable_gen4 + false + + + gen4_eieos_0s7 + true + + + c_s_axi_supports_narrow_burst + false + + + enable_ats_switch + FALSE + + + c_ats_switch_unique_bdf + 1 + + + ctrl_skip_mask + true + + + pf0_ats_enabled + Pf0 Ats Enabled + false + + + pf0_pri_enabled + Pf0 Pri Enabled + false + + + aspm_support + ASPM Support + No_ASPM + + + pf0_aer_cap_ecrc_gen_and_check_capable + false + + + gen_pipe_debug + false + + + soft_reset_en + DMA Bridge Reset + false + + + msi_rx_pin_en + FALSE + + + intx_rx_pin_en + true + + + msix_type + MSI-X Type + HARD + + + runbit_fix + false + + + axsize_byte_access_en + false + + + + + DMA/Bridge Subsystem for PCI Express (PCIe) + + XPM_CDC + XPM_MEMORY + XPM_FIFO + + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci new file mode 100644 index 0000000..d6c80db --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci @@ -0,0 +1,266 @@ + + + xilinx.com + xci + unknown + 1.0 + + + zq_calib_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + + OTHER + NONE + 8192 + 32 + + + 100000000 + 0.000 + 6 + 6 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 5.931282 mW + virtexuplus + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zq_calib_mem.mem + zq_calib_mem.mif + 0 + 1 + 0 + 0 + 1 + 48 + 48 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 48 + 48 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + virtexuplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../coe/pr_zq.coe + ALL + zq_calib_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + true + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 48 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + virtexuplus + + xcvu9p + flgb2104 + VERILOG + + MIXED + -2 + E + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2018.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml new file mode 100644 index 0000000..db5f7e2 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml @@ -0,0 +1,4054 @@ + + + xilinx.com + customized_ip + zq_calib_mem + 1.0 + + + CLK.ACLK + ACLK + AXI4 Interconnect Clock Input + + + + + + + CLK + + + s_aclk + + + + + + ASSOCIATED_BUSIF + AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI + + + ASSOCIATED_RESET + s_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + RST.ARESETN + ARESETN + AXI4 Interconnect Reset Input + + + + + + + RST + + + s_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + AXI_SLAVE_S_AXI + AXI_SLAVE + AXI_SLAVE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARBURST + + + s_axi_arburst + + + + + ARID + + + s_axi_arid + + + + + ARLEN + + + s_axi_arlen + + + + + ARREADY + + + s_axi_arready + + + + + ARSIZE + + + s_axi_arsize + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWBURST + + + s_axi_awburst + + + + + AWID + + + s_axi_awid + + + + + AWLEN + + + s_axi_awlen + + + + + AWREADY + + + s_axi_awready + + + + + AWSIZE + + + s_axi_awsize + + + + + AWVALID + + + s_axi_awvalid + + + + + BID + + + s_axi_bid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RID + + + s_axi_rid + + + + + RLAST + + + s_axi_rlast + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WLAST + + + s_axi_wlast + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 1 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 0 + + + none + + + + + HAS_BRESP + 0 + + + none + + + + + HAS_RRESP + 0 + + + none + + + + + SUPPORTS_NARROW_BURST + 0 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + AXILite_SLAVE_S_AXI + AXILite_SLAVE + AXILite_SLAVE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARBURST + + + s_axi_arburst + + + + + ARID + + + s_axi_arid + + + + + ARLEN + + + s_axi_arlen + + + + + ARREADY + + + s_axi_arready + + + + + ARSIZE + + + s_axi_arsize + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWBURST + + + s_axi_awburst + + + + + AWID + + + s_axi_awid + + + + + AWLEN + + + s_axi_awlen + + + + + AWREADY + + + s_axi_awready + + + + + AWSIZE + + + s_axi_awsize + + + + + AWVALID + + + s_axi_awvalid + + + + + BID + + + s_axi_bid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RID + + + s_axi_rid + + + + + RLAST + + + s_axi_rlast + + + + + RREADY + + + s_axi_rready + + + + + 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C_EN_SLEEP_PIN + 0 + + + C_USE_URAM + 0 + + + C_EN_RDADDRA_CHG + 0 + + + C_EN_RDADDRB_CHG + 0 + + + C_EN_DEEPSLEEP_PIN + 0 + + + C_EN_SHUTDOWN_PIN + 0 + + + C_EN_SAFETY_CKT + 0 + + + C_DISABLE_WARN_BHV_RANGE + 0 + + + C_COUNT_36K_BRAM + 1 + + + C_COUNT_18K_BRAM + 0 + + + C_EST_POWER_SUMMARY + Estimated Power for IP : 5.931282 mW + + + + + + choice_list_402310f0 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_5453281d + Native + AXI4 + + + choice_list_5f2d7eda + 16kx1 + 8kx2 + 4kx4 + 2kx9 + 1kx18 + 512x36 + 256x72 + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_89a27b2f + 8 + 9 + + + choice_list_c8df20f0 + NONE + ECCH32-7 + ECCH64-8 + ECCHSIAO32-7 + ECCHSIAO64-8 + ECCHSIAO128-9 + + + choice_list_e9412e2c + BRAM + URAM + + + choice_pairs_07c32259 + WRITE_FIRST + READ_FIRST + NO_CHANGE + + + choice_pairs_27c66b0d + Stand_Alone + BRAM_Controller + + + choice_pairs_2adcaf32 + SYNC + ASYNC + + + choice_pairs_2d73cdeb + Always_Enabled + Use_ENB_Pin + + + choice_pairs_3949ecbf + Always_Enabled + Use_ENA_Pin + + + choice_pairs_3e9ce7ae + Minimum_Area + Low_Power + Fixed_Primitives + + + choice_pairs_44b9b2d1 + ALL + NONE + WARNING_ONLY + GENERATE_X_ONLY + + + choice_pairs_63de7f78 + CE + SR + + + choice_pairs_716d2fba + Single_Bit_Error_Injection + Double_Bit_Error_Injection + Single_and_Double_Bit_Error_Injection + + + choice_pairs_b91edaa2 + Memory_Slave + Peripheral_Slave + + + choice_pairs_c1013cbe + No_ECC + Soft_ECC + BuiltIn_ECC + + + choice_pairs_e4c322cb + AXI4_Full + AXI4_Lite + + + choice_pairs_e932d933 + Single_Port_RAM + Simple_Dual_Port_RAM + True_Dual_Port_RAM + Single_Port_ROM + Dual_Port_ROM + + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + + + Component_Name + zq_calib_mem + + + + true + + + + + + Interface_Type + Native + + + + true + + + + + + AXI_Type + AXI4_Full + + + + true + + + + + + AXI_Slave_Type + Memory_Slave + + + + true + + + + + + Use_AXI_ID + false + + + + false + + + + + + AXI_ID_Width + 4 + + + + false + + + + + + Memory_Type + Single_Port_RAM + + + + true + + + + + + PRIM_type_to_Implement + BRAM + + + + true + + + + + + Enable_32bit_Address + false + + + + true + + + + + + ecctype + No_ECC + + + + false + + + + + + ECC + false + + + + false + + + + + + softecc + false + + + + false + + + + + + EN_SLEEP_PIN + false + + + + true + + + + + + EN_DEEPSLEEP_PIN + false + + + + false + + + + + + EN_SHUTDOWN_PIN + false + + + + false + + + + + + EN_ECC_PIPE + false + + + + false + + + + + + RD_ADDR_CHNG_A + false + + + + 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b/projects/XUSP3R/XUSP3R.xpr new file mode 100644 index 0000000..355c103 --- /dev/null +++ b/projects/XUSP3R/XUSP3R.xpr @@ -0,0 +1,836 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/XUSP3R/apply_patches.sh b/projects/XUSP3R/apply_patches.sh new file mode 100755 index 0000000..ab337bb --- /dev/null +++ b/projects/XUSP3R/apply_patches.sh @@ -0,0 +1,12 @@ +# some of the generated files have CR characters in additon to EOL characters +# which mess with our patch commands. +dos2unix XUSP3R.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv +dos2unix XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/rtl/cal/ddr4_v2_2_cal_rd_en.sv +dos2unix XUSP3R.srcs/sources_1/ip/phy_ddr4_x8_1R/rtl/cal/ddr4_v2_2_cal_rd_en.sv +dos2unix XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv + +for f in ./patches/*.patch +do + patch -p0 < $f +done + diff --git a/projects/XUSP3R/coe/pr_read.coe b/projects/XUSP3R/coe/pr_read.coe new file mode 100644 index 0000000..b9ccb93 --- /dev/null +++ b/projects/XUSP3R/coe/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUSP3R/coe/pr_ref.coe b/projects/XUSP3R/coe/pr_ref.coe new file mode 100644 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/XUSP3R/coe/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUSP3R/coe/pr_zq.coe b/projects/XUSP3R/coe/pr_zq.coe new file mode 100644 index 0000000..16d563c --- /dev/null +++ b/projects/XUSP3R/coe/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUSP3R/constraints/x4_1R_RDIMM.xdc b/projects/XUSP3R/constraints/x4_1R_RDIMM.xdc new file mode 100644 index 0000000..177776f --- /dev/null +++ b/projects/XUSP3R/constraints/x4_1R_RDIMM.xdc @@ -0,0 +1,184 @@ +############################################## +########## Configuration ########## +############################################## +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +############################################## +########## PCIe ########## +############################################## +# set_property LOC PCIE_3_1_X0Y1 [get_cells xdma_i/inst/pcie3_ip_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst] +set_property IOSTANDARD LVCMOS12 [get_ports pcie_rst] +set_property PACKAGE_PIN AR26 [get_ports pcie_rst] +set_property PULLUP true [get_ports pcie_rst] +set_property PACKAGE_PIN AT10 [get_ports clk_ref_n] +create_clock -period 10.000 -name refclk_100 [get_ports clk_ref_p] +############################################## +########## Clocks/Reset ########## +############################################## +create_clock -period 10.000 [get_ports c0_sys_clk_p] +set_clock_groups -asynchronous -group [get_clocks c0_sys_clk_p -include_generated_clocks] + +set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports c0_sys_clk_p] +set_property ODT RTT_48 [get_ports c0_sys_clk_p] +set_property PACKAGE_PIN AV18 [get_ports c0_sys_clk_p] +set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports c0_sys_clk_n] +set_property ODT RTT_48 [get_ports c0_sys_clk_n] + +set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_l] +set_property PACKAGE_PIN AT23 [get_ports sys_rst_l] +############################################## +########## DDR4 Pin Properties ########## +############################################## +### RDIMM 1 - x4 +set_property PACKAGE_PIN BE17 [ get_ports "c0_ddr4_dqs_t[17]" ] +set_property PACKAGE_PIN BF17 [ get_ports "c0_ddr4_dqs_c[17]" ] +set_property PACKAGE_PIN BF19 [ get_ports "c0_ddr4_dq[71]" ] +set_property PACKAGE_PIN BF18 [ get_ports "c0_ddr4_dq[70]" ] +set_property PACKAGE_PIN BD18 [ get_ports "c0_ddr4_dq[69]" ] +set_property PACKAGE_PIN BE18 [ get_ports "c0_ddr4_dq[68]" ] +set_property PACKAGE_PIN BC19 [ get_ports "c0_ddr4_dqs_t[16]" ] +set_property PACKAGE_PIN BD19 [ get_ports "c0_ddr4_dqs_c[16]" ] +set_property PACKAGE_PIN BB17 [ get_ports "c0_ddr4_dq[67]" ] +set_property PACKAGE_PIN BC17 [ get_ports "c0_ddr4_dq[66]" ] +set_property PACKAGE_PIN BB19 [ get_ports "c0_ddr4_dq[65]" ] +set_property PACKAGE_PIN BC18 [ get_ports "c0_ddr4_dq[64]" ] +set_property PACKAGE_PIN AY17 [ get_ports "c0_ddr4_reset_n" ] +#set_property PACKAGE_PIN BA17 [ get_ports "m0_ddr4_c[0]" ] +#set_property PACKAGE_PIN AY18 [ get_ports "m0_ddr4_c[1]" ] +set_property PACKAGE_PIN BA18 [ get_ports "c0_ddr4_cs_n[0]" ] +#set_property PACKAGE_PIN AW20 [ get_ports "m0_ddr4_cs_n[1]" ] +set_property PACKAGE_PIN AY20 [ get_ports "c0_ddr4_cke[0]" ] +#set_property PACKAGE_PIN AV21 [ get_ports "m0_ddr4_cke[1]" ] +set_property PACKAGE_PIN AW21 [ get_ports "c0_ddr4_odt[0]" ] +#set_property PACKAGE_PIN AV19 [ get_ports "m0_ddr4_odt[1]" ] +set_property PACKAGE_PIN AW19 [ get_ports "c0_ddr4_parity" ] +set_property PACKAGE_PIN AV17 [ get_ports "c0_ddr4_act_n" ] +set_property PACKAGE_PIN AT19 [ get_ports "c0_ddr4_ba[0]" ] +set_property PACKAGE_PIN AU19 [ get_ports "c0_ddr4_ba[1]" ] +set_property PACKAGE_PIN AT20 [ get_ports "c0_ddr4_bg[0]" ] +set_property PACKAGE_PIN AU20 [ get_ports "c0_ddr4_bg[1]" ] +set_property PACKAGE_PIN AT18 [ get_ports "c0_ddr4_adr[0]" ] +set_property PACKAGE_PIN AU17 [ get_ports "c0_ddr4_adr[1]" ] +set_property PACKAGE_PIN AR17 [ get_ports "c0_ddr4_ck_t" ] +set_property PACKAGE_PIN AT17 [ get_ports "c0_ddr4_ck_c" ] +set_property PACKAGE_PIN AP18 [ get_ports "c0_ddr4_adr[2]" ] +set_property PACKAGE_PIN AR18 [ get_ports "c0_ddr4_adr[3]" ] +set_property PACKAGE_PIN AP20 [ get_ports "c0_ddr4_adr[4]" ] +set_property PACKAGE_PIN AR20 [ get_ports "c0_ddr4_adr[5]" ] +set_property PACKAGE_PIN AU21 [ get_ports "c0_ddr4_adr[6]" ] +set_property PACKAGE_PIN AN18 [ get_ports "c0_ddr4_adr[7]" ] +set_property PACKAGE_PIN AN17 [ get_ports "c0_ddr4_adr[8]" ] +set_property PACKAGE_PIN AN19 [ get_ports "c0_ddr4_adr[9]" ] +set_property PACKAGE_PIN AP19 [ get_ports "c0_ddr4_adr[10]" ] +set_property PACKAGE_PIN AM16 [ get_ports "c0_ddr4_adr[11]" ] +set_property PACKAGE_PIN AN16 [ get_ports "c0_ddr4_adr[12]" ] +#set_property PACKAGE_PIN AM17 [ get_ports "m0_ddr4_c[2]" ] +set_property PACKAGE_PIN AL19 [ get_ports "c0_ddr4_adr[13]" ] +set_property PACKAGE_PIN AM19 [ get_ports "c0_ddr4_adr[14]" ] +set_property PACKAGE_PIN AL20 [ get_ports "c0_ddr4_adr[15]" ] +set_property PACKAGE_PIN AM20 [ get_ports "c0_ddr4_adr[16]" ] +#set_property PACKAGE_PIN AP16 [ get_ports "m0_ddr4_adr[17]" ] +set_property PACKAGE_PIN BF28 [ get_ports "c0_ddr4_dqs_t[7]" ] +set_property PACKAGE_PIN BF29 [ get_ports "c0_ddr4_dqs_c[7]" ] +set_property PACKAGE_PIN BE27 [ get_ports "c0_ddr4_dq[31]" ] +set_property PACKAGE_PIN BF27 [ get_ports "c0_ddr4_dq[30]" ] +set_property PACKAGE_PIN BD28 [ get_ports "c0_ddr4_dq[29]" ] +set_property PACKAGE_PIN BE28 [ get_ports "c0_ddr4_dq[28]" ] +set_property PACKAGE_PIN BD26 [ get_ports "c0_ddr4_dqs_t[6]" ] +set_property PACKAGE_PIN BE26 [ get_ports "c0_ddr4_dqs_c[6]" ] +set_property PACKAGE_PIN BE25 [ get_ports "c0_ddr4_dq[27]" ] +set_property PACKAGE_PIN BF25 [ get_ports "c0_ddr4_dq[26]" ] +set_property PACKAGE_PIN BC26 [ get_ports "c0_ddr4_dq[25]" ] +set_property PACKAGE_PIN BC27 [ get_ports "c0_ddr4_dq[24]" ] +set_property PACKAGE_PIN BA25 [ get_ports "c0_ddr4_dqs_t[5]" ] +set_property PACKAGE_PIN BB25 [ get_ports "c0_ddr4_dqs_c[5]" ] +set_property PACKAGE_PIN BB26 [ get_ports "c0_ddr4_dq[23]" ] +set_property PACKAGE_PIN BB27 [ get_ports "c0_ddr4_dq[22]" ] +set_property PACKAGE_PIN BA27 [ get_ports "c0_ddr4_dq[21]" ] +set_property PACKAGE_PIN BA28 [ get_ports "c0_ddr4_dq[20]" ] +set_property PACKAGE_PIN AW25 [ get_ports "c0_ddr4_dqs_t[4]" ] +set_property PACKAGE_PIN AY25 [ get_ports "c0_ddr4_dqs_c[4]" ] +set_property PACKAGE_PIN AY26 [ get_ports "c0_ddr4_dq[19]" ] +set_property PACKAGE_PIN AY27 [ get_ports "c0_ddr4_dq[18]" ] +set_property PACKAGE_PIN AW28 [ get_ports "c0_ddr4_dq[17]" ] +set_property PACKAGE_PIN AY28 [ get_ports "c0_ddr4_dq[16]" ] +set_property PACKAGE_PIN AV26 [ get_ports "c0_ddr4_dqs_t[3]" ] +set_property PACKAGE_PIN AW26 [ get_ports "c0_ddr4_dqs_c[3]" ] +set_property PACKAGE_PIN AV27 [ get_ports "c0_ddr4_dq[15]" ] +set_property PACKAGE_PIN AV28 [ get_ports "c0_ddr4_dq[14]" ] +set_property PACKAGE_PIN AU26 [ get_ports "c0_ddr4_dq[13]" ] +set_property PACKAGE_PIN AU27 [ get_ports "c0_ddr4_dq[12]" ] +set_property PACKAGE_PIN AR25 [ get_ports "c0_ddr4_dqs_t[2]" ] +set_property PACKAGE_PIN AT25 [ get_ports "c0_ddr4_dqs_c[2]" ] +set_property PACKAGE_PIN AR27 [ get_ports "c0_ddr4_dq[11]" ] +set_property PACKAGE_PIN AT27 [ get_ports "c0_ddr4_dq[10]" ] +set_property PACKAGE_PIN AR28 [ get_ports "c0_ddr4_dq[9]" ] +set_property PACKAGE_PIN AT28 [ get_ports "c0_ddr4_dq[8]" ] +#set_property PACKAGE_PIN AU25 [ get_ports "m0_ddr4_c[3]" ] +set_property PACKAGE_PIN AP25 [ get_ports "c0_ddr4_dqs_t[1]" ] +set_property PACKAGE_PIN AP26 [ get_ports "c0_ddr4_dqs_c[1]" ] +set_property PACKAGE_PIN AN28 [ get_ports "c0_ddr4_dq[7]" ] +set_property PACKAGE_PIN AP28 [ get_ports "c0_ddr4_dq[6]" ] +set_property PACKAGE_PIN AL25 [ get_ports "c0_ddr4_dq[5]" ] +set_property PACKAGE_PIN AM25 [ get_ports "c0_ddr4_dq[4]" ] +set_property PACKAGE_PIN AM26 [ get_ports "c0_ddr4_dqs_t[0]" ] +set_property PACKAGE_PIN AN26 [ get_ports "c0_ddr4_dqs_c[0]" ] +set_property PACKAGE_PIN AM27 [ get_ports "c0_ddr4_dq[3]" ] +set_property PACKAGE_PIN AN27 [ get_ports "c0_ddr4_dq[2]" ] +set_property PACKAGE_PIN AL27 [ get_ports "c0_ddr4_dq[1]" ] +set_property PACKAGE_PIN AL28 [ get_ports "c0_ddr4_dq[0]" ] +set_property PACKAGE_PIN BF14 [ get_ports "c0_ddr4_dqs_t[15]" ] +set_property PACKAGE_PIN BF13 [ get_ports "c0_ddr4_dqs_c[15]" ] +set_property PACKAGE_PIN BE15 [ get_ports "c0_ddr4_dq[63]" ] +set_property PACKAGE_PIN BF15 [ get_ports "c0_ddr4_dq[62]" ] +set_property PACKAGE_PIN BD16 [ get_ports "c0_ddr4_dq[61]" ] +set_property PACKAGE_PIN BE16 [ get_ports "c0_ddr4_dq[60]" ] +set_property PACKAGE_PIN BD13 [ get_ports "c0_ddr4_dqs_t[14]" ] +set_property PACKAGE_PIN BE13 [ get_ports "c0_ddr4_dqs_c[14]" ] +set_property PACKAGE_PIN BD15 [ get_ports "c0_ddr4_dq[59]" ] +set_property PACKAGE_PIN BD14 [ get_ports "c0_ddr4_dq[58]" ] +set_property PACKAGE_PIN BC14 [ get_ports "c0_ddr4_dq[57]" ] +set_property PACKAGE_PIN BC13 [ get_ports "c0_ddr4_dq[56]" ] +set_property PACKAGE_PIN BA12 [ get_ports "c0_ddr4_dqs_t[13]" ] +set_property PACKAGE_PIN BB12 [ get_ports "c0_ddr4_dqs_c[13]" ] +set_property PACKAGE_PIN AY12 [ get_ports "c0_ddr4_dq[55]" ] +set_property PACKAGE_PIN AY11 [ get_ports "c0_ddr4_dq[54]" ] +set_property PACKAGE_PIN AY16 [ get_ports "c0_ddr4_dq[53]" ] +set_property PACKAGE_PIN AY15 [ get_ports "c0_ddr4_dq[52]" ] +set_property PACKAGE_PIN BB15 [ get_ports "c0_ddr4_dqs_t[12]" ] +set_property PACKAGE_PIN BB14 [ get_ports "c0_ddr4_dqs_c[12]" ] +set_property PACKAGE_PIN BA15 [ get_ports "c0_ddr4_dq[51]" ] +set_property PACKAGE_PIN BA14 [ get_ports "c0_ddr4_dq[50]" ] +set_property PACKAGE_PIN AY13 [ get_ports "c0_ddr4_dq[49]" ] +set_property PACKAGE_PIN BA13 [ get_ports "c0_ddr4_dq[48]" ] +set_property PACKAGE_PIN AW14 [ get_ports "c0_ddr4_dqs_t[11]" ] +set_property PACKAGE_PIN AW13 [ get_ports "c0_ddr4_dqs_c[11]" ] +set_property PACKAGE_PIN AW16 [ get_ports "c0_ddr4_dq[47]" ] +set_property PACKAGE_PIN AW15 [ get_ports "c0_ddr4_dq[46]" ] +set_property PACKAGE_PIN AU13 [ get_ports "c0_ddr4_dq[45]" ] +set_property PACKAGE_PIN AV13 [ get_ports "c0_ddr4_dq[44]" ] +set_property PACKAGE_PIN AU14 [ get_ports "c0_ddr4_dqs_t[10]" ] +set_property PACKAGE_PIN AV14 [ get_ports "c0_ddr4_dqs_c[10]" ] +set_property PACKAGE_PIN AT15 [ get_ports "c0_ddr4_dq[43]" ] +set_property PACKAGE_PIN AU15 [ get_ports "c0_ddr4_dq[42]" ] +set_property PACKAGE_PIN AU16 [ get_ports "c0_ddr4_dq[41]" ] +set_property PACKAGE_PIN AV16 [ get_ports "c0_ddr4_dq[40]" ] +#set_property PACKAGE_PIN AT14 [ get_ports "m0_ddr4_c[4]" ] +set_property PACKAGE_PIN AR16 [ get_ports "c0_ddr4_dqs_t[9]" ] +set_property PACKAGE_PIN AR15 [ get_ports "c0_ddr4_dqs_c[9]" ] +set_property PACKAGE_PIN AP15 [ get_ports "c0_ddr4_dq[39]" ] +set_property PACKAGE_PIN AP14 [ get_ports "c0_ddr4_dq[38]" ] +set_property PACKAGE_PIN AN14 [ get_ports "c0_ddr4_dq[37]" ] +set_property PACKAGE_PIN AN13 [ get_ports "c0_ddr4_dq[36]" ] +set_property PACKAGE_PIN AP13 [ get_ports "c0_ddr4_dqs_t[8]" ] +set_property PACKAGE_PIN AR13 [ get_ports "c0_ddr4_dqs_c[8]" ] +set_property PACKAGE_PIN AL15 [ get_ports "c0_ddr4_dq[35]" ] +set_property PACKAGE_PIN AM15 [ get_ports "c0_ddr4_dq[34]" ] +set_property PACKAGE_PIN AL14 [ get_ports "c0_ddr4_dq[33]" ] +set_property PACKAGE_PIN AM14 [ get_ports "c0_ddr4_dq[32]" ] \ No newline at end of file diff --git a/projects/XUSP3R/constraints/x8_1R_RDIMM.xdc b/projects/XUSP3R/constraints/x8_1R_RDIMM.xdc new file mode 100644 index 0000000..739492a --- /dev/null +++ b/projects/XUSP3R/constraints/x8_1R_RDIMM.xdc @@ -0,0 +1,174 @@ +############################################## +########## Configuration ########## +############################################## +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +############################################## +########## PCIe ########## +############################################## +# set_property LOC PCIE_3_1_X0Y1 [get_cells xdma_i/inst/pcie3_ip_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst] +set_property IOSTANDARD LVCMOS12 [get_ports pcie_rst] +set_property PACKAGE_PIN AR26 [get_ports pcie_rst] +set_property PULLUP true [get_ports pcie_rst] +set_property PACKAGE_PIN AT10 [get_ports clk_ref_n] +create_clock -period 10.000 -name refclk_100 [get_ports clk_ref_p] +############################################## +########## Clocks/Reset ########## +############################################## +create_clock -period 10.000 [get_ports c0_sys_clk_p] +set_clock_groups -asynchronous -group [get_clocks c0_sys_clk_p -include_generated_clocks] + +set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports c0_sys_clk_p] +set_property ODT RTT_48 [get_ports c0_sys_clk_p] +set_property PACKAGE_PIN AV18 [get_ports c0_sys_clk_p] +set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports c0_sys_clk_n] +set_property ODT RTT_48 [get_ports c0_sys_clk_n] + +set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_l] +set_property PACKAGE_PIN AT23 [get_ports sys_rst_l] +############################################## +########## DDR4 Pin Properties ########## +############################################## +################################################################# +# RDIMM1 - x8 1R +################################################################# +set_property PACKAGE_PIN BE17 [ get_ports "c0_ddr4_dm_dbi_n[8]" ] +set_property PACKAGE_PIN BF19 [ get_ports "c0_ddr4_dq[67]" ] +set_property PACKAGE_PIN BF18 [ get_ports "c0_ddr4_dq[66]" ] +set_property PACKAGE_PIN BD18 [ get_ports "c0_ddr4_dq[65]" ] +set_property PACKAGE_PIN BE18 [ get_ports "c0_ddr4_dq[64]" ] +set_property PACKAGE_PIN BC19 [ get_ports "c0_ddr4_dqs_t[8]" ] +set_property PACKAGE_PIN BD19 [ get_ports "c0_ddr4_dqs_c[8]" ] +set_property PACKAGE_PIN BB17 [ get_ports "c0_ddr4_dq[71]" ] +set_property PACKAGE_PIN BC17 [ get_ports "c0_ddr4_dq[70]" ] +set_property PACKAGE_PIN BB19 [ get_ports "c0_ddr4_dq[69]" ] +set_property PACKAGE_PIN BC18 [ get_ports "c0_ddr4_dq[68]" ] +#set_property PACKAGE_PIN BA17 [ get_ports "m0_ddr4_c[0]" ] +#set_property PACKAGE_PIN AY18 [ get_ports "m0_ddr4_c[1]" ] +set_property PACKAGE_PIN BA18 [ get_ports "c0_ddr4_cs_n[0]" ] +set_property PACKAGE_PIN AW20 [ get_ports "c0_ddr4_cke[0]" ] +set_property PACKAGE_PIN AY20 [ get_ports "c0_ddr4_odt[0]" ] +set_property PACKAGE_PIN AV21 [ get_ports "c0_ddr4_act_n" ] +set_property PACKAGE_PIN AW21 [ get_ports "c0_ddr4_reset_n" ] +set_property PACKAGE_PIN AV19 [ get_ports "c0_ddr4_parity" ] +set_property PACKAGE_PIN AT19 [ get_ports "c0_ddr4_ba[0]" ] +set_property PACKAGE_PIN AU19 [ get_ports "c0_ddr4_ba[1]" ] +set_property PACKAGE_PIN AT20 [ get_ports "c0_ddr4_bg[0]" ] +set_property PACKAGE_PIN AU20 [ get_ports "c0_ddr4_bg[1]" ] +set_property PACKAGE_PIN AT18 [ get_ports "c0_ddr4_adr[0]" ] +set_property PACKAGE_PIN AU17 [ get_ports "c0_ddr4_adr[1]" ] +set_property PACKAGE_PIN AR17 [ get_ports "c0_ddr4_ck_t" ] +set_property PACKAGE_PIN AT17 [ get_ports "c0_ddr4_ck_c" ] +set_property PACKAGE_PIN AP18 [ get_ports "c0_ddr4_adr[2]" ] +set_property PACKAGE_PIN AR18 [ get_ports "c0_ddr4_adr[3]" ] +set_property PACKAGE_PIN AP20 [ get_ports "c0_ddr4_adr[4]" ] +set_property PACKAGE_PIN AR20 [ get_ports "c0_ddr4_adr[5]" ] +set_property PACKAGE_PIN AU21 [ get_ports "c0_ddr4_adr[6]" ] +set_property PACKAGE_PIN AN18 [ get_ports "c0_ddr4_adr[7]" ] +set_property PACKAGE_PIN AN17 [ get_ports "c0_ddr4_adr[8]" ] +set_property PACKAGE_PIN AN19 [ get_ports "c0_ddr4_adr[9]" ] +set_property PACKAGE_PIN AP19 [ get_ports "c0_ddr4_adr[10]" ] +set_property PACKAGE_PIN AM16 [ get_ports "c0_ddr4_adr[11]" ] +set_property PACKAGE_PIN AN16 [ get_ports "c0_ddr4_adr[12]" ] +#set_property PACKAGE_PIN AM17 [ get_ports "m0_ddr4_c[2]" ] +set_property PACKAGE_PIN AL19 [ get_ports "c0_ddr4_adr[13]" ] +set_property PACKAGE_PIN AM19 [ get_ports "c0_ddr4_adr[14]" ] +set_property PACKAGE_PIN AL20 [ get_ports "c0_ddr4_adr[15]" ] +set_property PACKAGE_PIN AM20 [ get_ports "c0_ddr4_adr[16]" ] +#set_property PACKAGE_PIN AP16 [ get_ports "m0_ddr4_adr[17]" ] +set_property PACKAGE_PIN BF28 [ get_ports "c0_ddr4_dm_dbi_n[3]" ] +set_property PACKAGE_PIN BE27 [ get_ports "c0_ddr4_dq[27]" ] +set_property PACKAGE_PIN BF27 [ get_ports "c0_ddr4_dq[26]" ] +set_property PACKAGE_PIN BD28 [ get_ports "c0_ddr4_dq[25]" ] +set_property PACKAGE_PIN BE28 [ get_ports "c0_ddr4_dq[24]" ] +set_property PACKAGE_PIN BD26 [ get_ports "c0_ddr4_dqs_t[3]" ] +set_property PACKAGE_PIN BE26 [ get_ports "c0_ddr4_dqs_c[3]" ] +set_property PACKAGE_PIN BE25 [ get_ports "c0_ddr4_dq[31]" ] +set_property PACKAGE_PIN BF25 [ get_ports "c0_ddr4_dq[30]" ] +set_property PACKAGE_PIN BC26 [ get_ports "c0_ddr4_dq[29]" ] +set_property PACKAGE_PIN BC27 [ get_ports "c0_ddr4_dq[28]" ] +set_property PACKAGE_PIN BA25 [ get_ports "c0_ddr4_dm_dbi_n[2]" ] +set_property PACKAGE_PIN BB26 [ get_ports "c0_ddr4_dq[19]" ] +set_property PACKAGE_PIN BB27 [ get_ports "c0_ddr4_dq[18]" ] +set_property PACKAGE_PIN BA27 [ get_ports "c0_ddr4_dq[17]" ] +set_property PACKAGE_PIN BA28 [ get_ports "c0_ddr4_dq[16]" ] +set_property PACKAGE_PIN AW25 [ get_ports "c0_ddr4_dqs_t[2]" ] +set_property PACKAGE_PIN AY25 [ get_ports "c0_ddr4_dqs_c[2]" ] +set_property PACKAGE_PIN AY26 [ get_ports "c0_ddr4_dq[23]" ] +set_property PACKAGE_PIN AY27 [ get_ports "c0_ddr4_dq[22]" ] +set_property PACKAGE_PIN AW28 [ get_ports "c0_ddr4_dq[21]" ] +set_property PACKAGE_PIN AY28 [ get_ports "c0_ddr4_dq[20]" ] +set_property PACKAGE_PIN AV26 [ get_ports "c0_ddr4_dm_dbi_n[1]" ] +set_property PACKAGE_PIN AV27 [ get_ports "c0_ddr4_dq[11]" ] +set_property PACKAGE_PIN AV28 [ get_ports "c0_ddr4_dq[10]" ] +set_property PACKAGE_PIN AU26 [ get_ports "c0_ddr4_dq[9]" ] +set_property PACKAGE_PIN AU27 [ get_ports "c0_ddr4_dq[8]" ] +set_property PACKAGE_PIN AR25 [ get_ports "c0_ddr4_dqs_t[1]" ] +set_property PACKAGE_PIN AT25 [ get_ports "c0_ddr4_dqs_c[1]" ] +set_property PACKAGE_PIN AR27 [ get_ports "c0_ddr4_dq[15]" ] +set_property PACKAGE_PIN AT27 [ get_ports "c0_ddr4_dq[14]" ] +set_property PACKAGE_PIN AR28 [ get_ports "c0_ddr4_dq[13]" ] +set_property PACKAGE_PIN AT28 [ get_ports "c0_ddr4_dq[12]" ] +#set_property PACKAGE_PIN AU25 [ get_ports "m0_ddr4_c[3]" ] +set_property PACKAGE_PIN AP25 [ get_ports "c0_ddr4_dm_dbi_n[0]" ] +set_property PACKAGE_PIN AN28 [ get_ports "c0_ddr4_dq[3]" ] +set_property PACKAGE_PIN AP28 [ get_ports "c0_ddr4_dq[2]" ] +set_property PACKAGE_PIN AL25 [ get_ports "c0_ddr4_dq[1]" ] +set_property PACKAGE_PIN AM25 [ get_ports "c0_ddr4_dq[0]" ] +set_property PACKAGE_PIN AM26 [ get_ports "c0_ddr4_dqs_t[0]" ] +set_property PACKAGE_PIN AN26 [ get_ports "c0_ddr4_dqs_c[0]" ] +set_property PACKAGE_PIN AM27 [ get_ports "c0_ddr4_dq[7]" ] +set_property PACKAGE_PIN AN27 [ get_ports "c0_ddr4_dq[6]" ] +set_property PACKAGE_PIN AL27 [ get_ports "c0_ddr4_dq[5]" ] +set_property PACKAGE_PIN AL28 [ get_ports "c0_ddr4_dq[4]" ] +set_property PACKAGE_PIN BF14 [ get_ports "c0_ddr4_dm_dbi_n[7]" ] +set_property PACKAGE_PIN BE15 [ get_ports "c0_ddr4_dq[59]" ] +set_property PACKAGE_PIN BF15 [ get_ports "c0_ddr4_dq[58]" ] +set_property PACKAGE_PIN BD16 [ get_ports "c0_ddr4_dq[57]" ] +set_property PACKAGE_PIN BE16 [ get_ports "c0_ddr4_dq[56]" ] +set_property PACKAGE_PIN BD13 [ get_ports "c0_ddr4_dqs_t[7]" ] +set_property PACKAGE_PIN BE13 [ get_ports "c0_ddr4_dqs_c[7]" ] +set_property PACKAGE_PIN BD15 [ get_ports "c0_ddr4_dq[63]" ] +set_property PACKAGE_PIN BD14 [ get_ports "c0_ddr4_dq[62]" ] +set_property PACKAGE_PIN BC14 [ get_ports "c0_ddr4_dq[61]" ] +set_property PACKAGE_PIN BC13 [ get_ports "c0_ddr4_dq[60]" ] +set_property PACKAGE_PIN BA12 [ get_ports "c0_ddr4_dm_dbi_n[6]" ] +set_property PACKAGE_PIN AY12 [ get_ports "c0_ddr4_dq[51]" ] +set_property PACKAGE_PIN AY11 [ get_ports "c0_ddr4_dq[50]" ] +set_property PACKAGE_PIN AY16 [ get_ports "c0_ddr4_dq[49]" ] +set_property PACKAGE_PIN AY15 [ get_ports "c0_ddr4_dq[48]" ] +set_property PACKAGE_PIN BB15 [ get_ports "c0_ddr4_dqs_t[6]" ] +set_property PACKAGE_PIN BB14 [ get_ports "c0_ddr4_dqs_c[6]" ] +set_property PACKAGE_PIN BA15 [ get_ports "c0_ddr4_dq[55]" ] +set_property PACKAGE_PIN BA14 [ get_ports "c0_ddr4_dq[54]" ] +set_property PACKAGE_PIN AY13 [ get_ports "c0_ddr4_dq[53]" ] +set_property PACKAGE_PIN BA13 [ get_ports "c0_ddr4_dq[52]" ] +set_property PACKAGE_PIN AW14 [ get_ports "c0_ddr4_dm_dbi_n[5]" ] +set_property PACKAGE_PIN AW16 [ get_ports "c0_ddr4_dq[43]" ] +set_property PACKAGE_PIN AW15 [ get_ports "c0_ddr4_dq[42]" ] +set_property PACKAGE_PIN AU13 [ get_ports "c0_ddr4_dq[41]" ] +set_property PACKAGE_PIN AV13 [ get_ports "c0_ddr4_dq[40]" ] +set_property PACKAGE_PIN AU14 [ get_ports "c0_ddr4_dqs_t[5]" ] +set_property PACKAGE_PIN AV14 [ get_ports "c0_ddr4_dqs_c[5]" ] +set_property PACKAGE_PIN AT15 [ get_ports "c0_ddr4_dq[47]" ] +set_property PACKAGE_PIN AU15 [ get_ports "c0_ddr4_dq[46]" ] +set_property PACKAGE_PIN AU16 [ get_ports "c0_ddr4_dq[45]" ] +set_property PACKAGE_PIN AV16 [ get_ports "c0_ddr4_dq[44]" ] +#set_property PACKAGE_PIN AT14 [ get_ports "m0_ddr4_c[4]" ] +set_property PACKAGE_PIN AR16 [ get_ports "c0_ddr4_dm_dbi_n[4]" ] +set_property PACKAGE_PIN AP15 [ get_ports "c0_ddr4_dq[35]" ] +set_property PACKAGE_PIN AP14 [ get_ports "c0_ddr4_dq[34]" ] +set_property PACKAGE_PIN AN14 [ get_ports "c0_ddr4_dq[33]" ] +set_property PACKAGE_PIN AN13 [ get_ports "c0_ddr4_dq[32]" ] +set_property PACKAGE_PIN AP13 [ get_ports "c0_ddr4_dqs_t[4]" ] +set_property PACKAGE_PIN AR13 [ get_ports "c0_ddr4_dqs_c[4]" ] +set_property PACKAGE_PIN AL15 [ get_ports "c0_ddr4_dq[39]" ] +set_property PACKAGE_PIN AM15 [ get_ports "c0_ddr4_dq[38]" ] +set_property PACKAGE_PIN AL14 [ get_ports "c0_ddr4_dq[37]" ] +set_property PACKAGE_PIN AM14 [ get_ports "c0_ddr4_dq[36]" ] \ No newline at end of file diff --git a/projects/XUSP3R/constraints/x8_1R_UDIMM.xdc b/projects/XUSP3R/constraints/x8_1R_UDIMM.xdc new file mode 100644 index 0000000..ab3568b --- /dev/null +++ b/projects/XUSP3R/constraints/x8_1R_UDIMM.xdc @@ -0,0 +1,160 @@ +############################################## +########## Configuration ########## +############################################## +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +############################################## +########## PCIe ########## +############################################## +# set_property LOC PCIE_3_1_X0Y1 [get_cells xdma_i/inst/pcie3_ip_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst] +set_property IOSTANDARD LVCMOS12 [get_ports pcie_rst] +set_property PACKAGE_PIN AR26 [get_ports pcie_rst] +set_property PULLUP true [get_ports pcie_rst] +set_property PACKAGE_PIN AT10 [get_ports clk_ref_n] +create_clock -period 10.000 -name refclk_100 [get_ports clk_ref_p] +############################################## +########## Clocks/Reset ########## +############################################## +create_clock -period 10.000 [get_ports c0_sys_clk_p] +set_clock_groups -asynchronous -group [get_clocks c0_sys_clk_p -include_generated_clocks] + +set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports c0_sys_clk_p] +set_property ODT RTT_48 [get_ports c0_sys_clk_p] +set_property PACKAGE_PIN AV18 [get_ports c0_sys_clk_p] +set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports c0_sys_clk_n] +set_property ODT RTT_48 [get_ports c0_sys_clk_n] + +set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_l] +set_property PACKAGE_PIN AT23 [get_ports sys_rst_l] +############################################## +########## DDR4 Pin Properties ########## +############################################## +################################################################# +# UDIMM1 - x8 1R +################################################################# +set_property PACKAGE_PIN BA18 [ get_ports "c0_ddr4_cs_n[0]" ] +set_property PACKAGE_PIN AW20 [ get_ports "c0_ddr4_cke[0]" ] +set_property PACKAGE_PIN AY20 [ get_ports "c0_ddr4_odt[0]" ] +set_property PACKAGE_PIN AV21 [ get_ports "c0_ddr4_act_n" ] +set_property PACKAGE_PIN AW21 [ get_ports "c0_ddr4_reset_n" ] +set_property PACKAGE_PIN AT19 [ get_ports "c0_ddr4_ba[0]" ] +set_property PACKAGE_PIN AU19 [ get_ports "c0_ddr4_ba[1]" ] +set_property PACKAGE_PIN AT20 [ get_ports "c0_ddr4_bg[0]" ] +set_property PACKAGE_PIN AU20 [ get_ports "c0_ddr4_bg[1]" ] +set_property PACKAGE_PIN AT18 [ get_ports "c0_ddr4_adr[0]" ] +set_property PACKAGE_PIN AU17 [ get_ports "c0_ddr4_adr[1]" ] +set_property PACKAGE_PIN AR17 [ get_ports "c0_ddr4_ck_t" ] +set_property PACKAGE_PIN AT17 [ get_ports "c0_ddr4_ck_c" ] +set_property PACKAGE_PIN AP18 [ get_ports "c0_ddr4_adr[2]" ] +set_property PACKAGE_PIN AR18 [ get_ports "c0_ddr4_adr[3]" ] +set_property PACKAGE_PIN AP20 [ get_ports "c0_ddr4_adr[4]" ] +set_property PACKAGE_PIN AR20 [ get_ports "c0_ddr4_adr[5]" ] +set_property PACKAGE_PIN AU21 [ get_ports "c0_ddr4_adr[6]" ] +set_property PACKAGE_PIN AN18 [ get_ports "c0_ddr4_adr[7]" ] +set_property PACKAGE_PIN AN17 [ get_ports "c0_ddr4_adr[8]" ] +set_property PACKAGE_PIN AN19 [ get_ports "c0_ddr4_adr[9]" ] +set_property PACKAGE_PIN AP19 [ get_ports "c0_ddr4_adr[10]" ] +set_property PACKAGE_PIN AM16 [ get_ports "c0_ddr4_adr[11]" ] +set_property PACKAGE_PIN AN16 [ get_ports "c0_ddr4_adr[12]" ] +#set_property PACKAGE_PIN AM17 [ get_ports "m0_ddr4_c[2]" ] +set_property PACKAGE_PIN AL19 [ get_ports "c0_ddr4_adr[13]" ] +set_property PACKAGE_PIN AM19 [ get_ports "c0_ddr4_adr[14]" ] +set_property PACKAGE_PIN AL20 [ get_ports "c0_ddr4_adr[15]" ] +set_property PACKAGE_PIN AM20 [ get_ports "c0_ddr4_adr[16]" ] +#set_property PACKAGE_PIN AP16 [ get_ports "m0_ddr4_adr[17]" ] +set_property PACKAGE_PIN BF28 [ get_ports "c0_ddr4_dm_dbi_n[3]" ] +set_property PACKAGE_PIN BE27 [ get_ports "c0_ddr4_dq[27]" ] +set_property PACKAGE_PIN BF27 [ get_ports "c0_ddr4_dq[26]" ] +set_property PACKAGE_PIN BD28 [ get_ports "c0_ddr4_dq[25]" ] +set_property PACKAGE_PIN BE28 [ get_ports "c0_ddr4_dq[24]" ] +set_property PACKAGE_PIN BD26 [ get_ports "c0_ddr4_dqs_t[3]" ] +set_property PACKAGE_PIN BE26 [ get_ports "c0_ddr4_dqs_c[3]" ] +set_property PACKAGE_PIN BE25 [ get_ports "c0_ddr4_dq[31]" ] +set_property PACKAGE_PIN BF25 [ get_ports "c0_ddr4_dq[30]" ] +set_property PACKAGE_PIN BC26 [ get_ports "c0_ddr4_dq[29]" ] +set_property PACKAGE_PIN BC27 [ get_ports "c0_ddr4_dq[28]" ] +set_property PACKAGE_PIN BA25 [ get_ports "c0_ddr4_dm_dbi_n[2]" ] +set_property PACKAGE_PIN BB26 [ get_ports "c0_ddr4_dq[19]" ] +set_property PACKAGE_PIN BB27 [ get_ports "c0_ddr4_dq[18]" ] +set_property PACKAGE_PIN BA27 [ get_ports "c0_ddr4_dq[17]" ] +set_property PACKAGE_PIN BA28 [ get_ports "c0_ddr4_dq[16]" ] +set_property PACKAGE_PIN AW25 [ get_ports "c0_ddr4_dqs_t[2]" ] +set_property PACKAGE_PIN AY25 [ get_ports "c0_ddr4_dqs_c[2]" ] +set_property PACKAGE_PIN AY26 [ get_ports "c0_ddr4_dq[23]" ] +set_property PACKAGE_PIN AY27 [ get_ports "c0_ddr4_dq[22]" ] +set_property PACKAGE_PIN AW28 [ get_ports "c0_ddr4_dq[21]" ] +set_property PACKAGE_PIN AY28 [ get_ports "c0_ddr4_dq[20]" ] +set_property PACKAGE_PIN AV26 [ get_ports "c0_ddr4_dm_dbi_n[1]" ] +set_property PACKAGE_PIN AV27 [ get_ports "c0_ddr4_dq[11]" ] +set_property PACKAGE_PIN AV28 [ get_ports "c0_ddr4_dq[10]" ] +set_property PACKAGE_PIN AU26 [ get_ports "c0_ddr4_dq[9]" ] +set_property PACKAGE_PIN AU27 [ get_ports "c0_ddr4_dq[8]" ] +set_property PACKAGE_PIN AR25 [ get_ports "c0_ddr4_dqs_t[1]" ] +set_property PACKAGE_PIN AT25 [ get_ports "c0_ddr4_dqs_c[1]" ] +set_property PACKAGE_PIN AR27 [ get_ports "c0_ddr4_dq[15]" ] +set_property PACKAGE_PIN AT27 [ get_ports "c0_ddr4_dq[14]" ] +set_property PACKAGE_PIN AR28 [ get_ports "c0_ddr4_dq[13]" ] +set_property PACKAGE_PIN AT28 [ get_ports "c0_ddr4_dq[12]" ] +#set_property PACKAGE_PIN AU25 [ get_ports "m0_ddr4_c[3]" ] +set_property PACKAGE_PIN AP25 [ get_ports "c0_ddr4_dm_dbi_n[0]" ] +set_property PACKAGE_PIN AN28 [ get_ports "c0_ddr4_dq[3]" ] +set_property PACKAGE_PIN AP28 [ get_ports "c0_ddr4_dq[2]" ] +set_property PACKAGE_PIN AL25 [ get_ports "c0_ddr4_dq[1]" ] +set_property PACKAGE_PIN AM25 [ get_ports "c0_ddr4_dq[0]" ] +set_property PACKAGE_PIN AM26 [ get_ports "c0_ddr4_dqs_t[0]" ] +set_property PACKAGE_PIN AN26 [ get_ports "c0_ddr4_dqs_c[0]" ] +set_property PACKAGE_PIN AM27 [ get_ports "c0_ddr4_dq[7]" ] +set_property PACKAGE_PIN AN27 [ get_ports "c0_ddr4_dq[6]" ] +set_property PACKAGE_PIN AL27 [ get_ports "c0_ddr4_dq[5]" ] +set_property PACKAGE_PIN AL28 [ get_ports "c0_ddr4_dq[4]" ] +set_property PACKAGE_PIN BF14 [ get_ports "c0_ddr4_dm_dbi_n[7]" ] +set_property PACKAGE_PIN BE15 [ get_ports "c0_ddr4_dq[59]" ] +set_property PACKAGE_PIN BF15 [ get_ports "c0_ddr4_dq[58]" ] +set_property PACKAGE_PIN BD16 [ get_ports "c0_ddr4_dq[57]" ] +set_property PACKAGE_PIN BE16 [ get_ports "c0_ddr4_dq[56]" ] +set_property PACKAGE_PIN BD13 [ get_ports "c0_ddr4_dqs_t[7]" ] +set_property PACKAGE_PIN BE13 [ get_ports "c0_ddr4_dqs_c[7]" ] +set_property PACKAGE_PIN BD15 [ get_ports "c0_ddr4_dq[63]" ] +set_property PACKAGE_PIN BD14 [ get_ports "c0_ddr4_dq[62]" ] +set_property PACKAGE_PIN BC14 [ get_ports "c0_ddr4_dq[61]" ] +set_property PACKAGE_PIN BC13 [ get_ports "c0_ddr4_dq[60]" ] +set_property PACKAGE_PIN BA12 [ get_ports "c0_ddr4_dm_dbi_n[6]" ] +set_property PACKAGE_PIN AY12 [ get_ports "c0_ddr4_dq[51]" ] +set_property PACKAGE_PIN AY11 [ get_ports "c0_ddr4_dq[50]" ] +set_property PACKAGE_PIN AY16 [ get_ports "c0_ddr4_dq[49]" ] +set_property PACKAGE_PIN AY15 [ get_ports "c0_ddr4_dq[48]" ] +set_property PACKAGE_PIN BB15 [ get_ports "c0_ddr4_dqs_t[6]" ] +set_property PACKAGE_PIN BB14 [ get_ports "c0_ddr4_dqs_c[6]" ] +set_property PACKAGE_PIN BA15 [ get_ports "c0_ddr4_dq[55]" ] +set_property PACKAGE_PIN BA14 [ get_ports "c0_ddr4_dq[54]" ] +set_property PACKAGE_PIN AY13 [ get_ports "c0_ddr4_dq[53]" ] +set_property PACKAGE_PIN BA13 [ get_ports "c0_ddr4_dq[52]" ] +set_property PACKAGE_PIN AW14 [ get_ports "c0_ddr4_dm_dbi_n[5]" ] +set_property PACKAGE_PIN AW16 [ get_ports "c0_ddr4_dq[43]" ] +set_property PACKAGE_PIN AW15 [ get_ports "c0_ddr4_dq[42]" ] +set_property PACKAGE_PIN AU13 [ get_ports "c0_ddr4_dq[41]" ] +set_property PACKAGE_PIN AV13 [ get_ports "c0_ddr4_dq[40]" ] +set_property PACKAGE_PIN AU14 [ get_ports "c0_ddr4_dqs_t[5]" ] +set_property PACKAGE_PIN AV14 [ get_ports "c0_ddr4_dqs_c[5]" ] +set_property PACKAGE_PIN AT15 [ get_ports "c0_ddr4_dq[47]" ] +set_property PACKAGE_PIN AU15 [ get_ports "c0_ddr4_dq[46]" ] +set_property PACKAGE_PIN AU16 [ get_ports "c0_ddr4_dq[45]" ] +set_property PACKAGE_PIN AV16 [ get_ports "c0_ddr4_dq[44]" ] +#set_property PACKAGE_PIN AT14 [ get_ports "m0_ddr4_c[4]" ] +set_property PACKAGE_PIN AR16 [ get_ports "c0_ddr4_dm_dbi_n[4]" ] +set_property PACKAGE_PIN AP15 [ get_ports "c0_ddr4_dq[35]" ] +set_property PACKAGE_PIN AP14 [ get_ports "c0_ddr4_dq[34]" ] +set_property PACKAGE_PIN AN14 [ get_ports "c0_ddr4_dq[33]" ] +set_property PACKAGE_PIN AN13 [ get_ports "c0_ddr4_dq[32]" ] +set_property PACKAGE_PIN AP13 [ get_ports "c0_ddr4_dqs_t[4]" ] +set_property PACKAGE_PIN AR13 [ get_ports "c0_ddr4_dqs_c[4]" ] +set_property PACKAGE_PIN AL15 [ get_ports "c0_ddr4_dq[39]" ] +set_property PACKAGE_PIN AM15 [ get_ports "c0_ddr4_dq[38]" ] +set_property PACKAGE_PIN AL14 [ get_ports "c0_ddr4_dq[37]" ] +set_property PACKAGE_PIN AM14 [ get_ports "c0_ddr4_dq[36]" ] \ No newline at end of file diff --git a/projects/XUSP3R/constraints/x8_2R_RDIMM.xdc b/projects/XUSP3R/constraints/x8_2R_RDIMM.xdc new file mode 100644 index 0000000..c3e143e --- /dev/null +++ b/projects/XUSP3R/constraints/x8_2R_RDIMM.xdc @@ -0,0 +1,177 @@ +############################################## +########## Configuration ########## +############################################## +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +############################################## +########## PCIe ########## +############################################## +# set_property LOC PCIE_3_1_X0Y1 [get_cells xdma_i/inst/pcie3_ip_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst] +set_property IOSTANDARD LVCMOS12 [get_ports pcie_rst] +set_property PACKAGE_PIN AR26 [get_ports pcie_rst] +set_property PULLUP true [get_ports pcie_rst] +set_property PACKAGE_PIN AT10 [get_ports clk_ref_n] +create_clock -period 10.000 -name refclk_100 [get_ports clk_ref_p] +############################################## +########## Clocks/Reset ########## +############################################## +create_clock -period 10.000 [get_ports c0_sys_clk_p] +set_clock_groups -asynchronous -group [get_clocks c0_sys_clk_p -include_generated_clocks] + +set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports c0_sys_clk_p] +set_property ODT RTT_48 [get_ports c0_sys_clk_p] +set_property PACKAGE_PIN AV18 [get_ports c0_sys_clk_p] +set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports c0_sys_clk_n] +set_property ODT RTT_48 [get_ports c0_sys_clk_n] + +set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_l] +set_property PACKAGE_PIN AT23 [get_ports sys_rst_l] +############################################## +########## DDR4 Pin Properties ########## +############################################## +################################################################# +# RDIMM1 - x8 +################################################################# +set_property PACKAGE_PIN BE17 [ get_ports "c0_ddr4_dm_dbi_n[8]" ] +set_property PACKAGE_PIN BF19 [ get_ports "c0_ddr4_dq[67]" ] +set_property PACKAGE_PIN BF18 [ get_ports "c0_ddr4_dq[66]" ] +set_property PACKAGE_PIN BD18 [ get_ports "c0_ddr4_dq[65]" ] +set_property PACKAGE_PIN BE18 [ get_ports "c0_ddr4_dq[64]" ] +set_property PACKAGE_PIN BC19 [ get_ports "c0_ddr4_dqs_t[8]" ] +set_property PACKAGE_PIN BD19 [ get_ports "c0_ddr4_dqs_c[8]" ] +set_property PACKAGE_PIN BB17 [ get_ports "c0_ddr4_dq[71]" ] +set_property PACKAGE_PIN BC17 [ get_ports "c0_ddr4_dq[70]" ] +set_property PACKAGE_PIN BB19 [ get_ports "c0_ddr4_dq[69]" ] +set_property PACKAGE_PIN BC18 [ get_ports "c0_ddr4_dq[68]" ] +set_property PACKAGE_PIN AY17 [ get_ports "c0_ddr4_reset_n" ] +#set_property PACKAGE_PIN BA17 [ get_ports "m0_ddr4_c[0]" ] +#set_property PACKAGE_PIN AY18 [ get_ports "m0_ddr4_c[1]" ] +set_property PACKAGE_PIN BA18 [ get_ports "c0_ddr4_cs_n[0]" ] +set_property PACKAGE_PIN AW20 [ get_ports "c0_ddr4_cs_n[1]" ] +set_property PACKAGE_PIN AY20 [ get_ports "c0_ddr4_cke[0]" ] +set_property PACKAGE_PIN AV21 [ get_ports "c0_ddr4_cke[1]" ] +set_property PACKAGE_PIN AW21 [ get_ports "c0_ddr4_odt[0]" ] +set_property PACKAGE_PIN AV19 [ get_ports "c0_ddr4_odt[1]" ] +set_property PACKAGE_PIN AW19 [ get_ports "c0_ddr4_parity" ] +set_property PACKAGE_PIN AV17 [ get_ports "c0_ddr4_act_n" ] +set_property PACKAGE_PIN AT19 [ get_ports "c0_ddr4_ba[0]" ] +set_property PACKAGE_PIN AU19 [ get_ports "c0_ddr4_ba[1]" ] +set_property PACKAGE_PIN AT20 [ get_ports "c0_ddr4_bg[0]" ] +set_property PACKAGE_PIN AU20 [ get_ports "c0_ddr4_bg[1]" ] +set_property PACKAGE_PIN AT18 [ get_ports "c0_ddr4_adr[0]" ] +set_property PACKAGE_PIN AU17 [ get_ports "c0_ddr4_adr[1]" ] +set_property PACKAGE_PIN AR17 [ get_ports "c0_ddr4_ck_t" ] +set_property PACKAGE_PIN AT17 [ get_ports "c0_ddr4_ck_c" ] +set_property PACKAGE_PIN AP18 [ get_ports "c0_ddr4_adr[2]" ] +set_property PACKAGE_PIN AR18 [ get_ports "c0_ddr4_adr[3]" ] +set_property PACKAGE_PIN AP20 [ get_ports "c0_ddr4_adr[4]" ] +set_property PACKAGE_PIN AR20 [ get_ports "c0_ddr4_adr[5]" ] +set_property PACKAGE_PIN AU21 [ get_ports "c0_ddr4_adr[6]" ] +set_property PACKAGE_PIN AN18 [ get_ports "c0_ddr4_adr[7]" ] +set_property PACKAGE_PIN AN17 [ get_ports "c0_ddr4_adr[8]" ] +set_property PACKAGE_PIN AN19 [ get_ports "c0_ddr4_adr[9]" ] +set_property PACKAGE_PIN AP19 [ get_ports "c0_ddr4_adr[10]" ] +set_property PACKAGE_PIN AM16 [ get_ports "c0_ddr4_adr[11]" ] +set_property PACKAGE_PIN AN16 [ get_ports "c0_ddr4_adr[12]" ] +#set_property PACKAGE_PIN AM17 [ get_ports "m0_ddr4_c[2]" ] +set_property PACKAGE_PIN AL19 [ get_ports "c0_ddr4_adr[13]" ] +set_property PACKAGE_PIN AM19 [ get_ports "c0_ddr4_adr[14]" ] +set_property PACKAGE_PIN AL20 [ get_ports "c0_ddr4_adr[15]" ] +set_property PACKAGE_PIN AM20 [ get_ports "c0_ddr4_adr[16]" ] +#set_property PACKAGE_PIN AP16 [ get_ports "m0_ddr4_adr[17]" ] +set_property PACKAGE_PIN BF28 [ get_ports "c0_ddr4_dm_dbi_n[3]" ] +set_property PACKAGE_PIN BE27 [ get_ports "c0_ddr4_dq[27]" ] +set_property PACKAGE_PIN BF27 [ get_ports "c0_ddr4_dq[26]" ] +set_property PACKAGE_PIN BD28 [ get_ports "c0_ddr4_dq[25]" ] +set_property PACKAGE_PIN BE28 [ get_ports "c0_ddr4_dq[24]" ] +set_property PACKAGE_PIN BD26 [ get_ports "c0_ddr4_dqs_t[3]" ] +set_property PACKAGE_PIN BE26 [ get_ports "c0_ddr4_dqs_c[3]" ] +set_property PACKAGE_PIN BE25 [ get_ports "c0_ddr4_dq[31]" ] +set_property PACKAGE_PIN BF25 [ get_ports "c0_ddr4_dq[30]" ] +set_property PACKAGE_PIN BC26 [ get_ports "c0_ddr4_dq[29]" ] +set_property PACKAGE_PIN BC27 [ get_ports "c0_ddr4_dq[28]" ] +set_property PACKAGE_PIN BA25 [ get_ports "c0_ddr4_dm_dbi_n[2]" ] +set_property PACKAGE_PIN BB26 [ get_ports "c0_ddr4_dq[19]" ] +set_property PACKAGE_PIN BB27 [ get_ports "c0_ddr4_dq[18]" ] +set_property PACKAGE_PIN BA27 [ get_ports "c0_ddr4_dq[17]" ] +set_property PACKAGE_PIN BA28 [ get_ports "c0_ddr4_dq[16]" ] +set_property PACKAGE_PIN AW25 [ get_ports "c0_ddr4_dqs_t[2]" ] +set_property PACKAGE_PIN AY25 [ get_ports "c0_ddr4_dqs_c[2]" ] +set_property PACKAGE_PIN AY26 [ get_ports "c0_ddr4_dq[23]" ] +set_property PACKAGE_PIN AY27 [ get_ports "c0_ddr4_dq[22]" ] +set_property PACKAGE_PIN AW28 [ get_ports "c0_ddr4_dq[21]" ] +set_property PACKAGE_PIN AY28 [ get_ports "c0_ddr4_dq[20]" ] +set_property PACKAGE_PIN AV26 [ get_ports "c0_ddr4_dm_dbi_n[1]" ] +set_property PACKAGE_PIN AV27 [ get_ports "c0_ddr4_dq[11]" ] +set_property PACKAGE_PIN AV28 [ get_ports "c0_ddr4_dq[10]" ] +set_property PACKAGE_PIN AU26 [ get_ports "c0_ddr4_dq[9]" ] +set_property PACKAGE_PIN AU27 [ get_ports "c0_ddr4_dq[8]" ] +set_property PACKAGE_PIN AR25 [ get_ports "c0_ddr4_dqs_t[1]" ] +set_property PACKAGE_PIN AT25 [ get_ports "c0_ddr4_dqs_c[1]" ] +set_property PACKAGE_PIN AR27 [ get_ports "c0_ddr4_dq[15]" ] +set_property PACKAGE_PIN AT27 [ get_ports "c0_ddr4_dq[14]" ] +set_property PACKAGE_PIN AR28 [ get_ports "c0_ddr4_dq[13]" ] +set_property PACKAGE_PIN AT28 [ get_ports "c0_ddr4_dq[12]" ] +#set_property PACKAGE_PIN AU25 [ get_ports "m0_ddr4_c[3]" ] +set_property PACKAGE_PIN AP25 [ get_ports "c0_ddr4_dm_dbi_n[0]" ] +set_property PACKAGE_PIN AN28 [ get_ports "c0_ddr4_dq[3]" ] +set_property PACKAGE_PIN AP28 [ get_ports "c0_ddr4_dq[2]" ] +set_property PACKAGE_PIN AL25 [ get_ports "c0_ddr4_dq[1]" ] +set_property PACKAGE_PIN AM25 [ get_ports "c0_ddr4_dq[0]" ] +set_property PACKAGE_PIN AM26 [ get_ports "c0_ddr4_dqs_t[0]" ] +set_property PACKAGE_PIN AN26 [ get_ports "c0_ddr4_dqs_c[0]" ] +set_property PACKAGE_PIN AM27 [ get_ports "c0_ddr4_dq[7]" ] +set_property PACKAGE_PIN AN27 [ get_ports "c0_ddr4_dq[6]" ] +set_property PACKAGE_PIN AL27 [ get_ports "c0_ddr4_dq[5]" ] +set_property PACKAGE_PIN AL28 [ get_ports "c0_ddr4_dq[4]" ] +set_property PACKAGE_PIN BF14 [ get_ports "c0_ddr4_dm_dbi_n[7]" ] +set_property PACKAGE_PIN BE15 [ get_ports "c0_ddr4_dq[59]" ] +set_property PACKAGE_PIN BF15 [ get_ports "c0_ddr4_dq[58]" ] +set_property PACKAGE_PIN BD16 [ get_ports "c0_ddr4_dq[57]" ] +set_property PACKAGE_PIN BE16 [ get_ports "c0_ddr4_dq[56]" ] +set_property PACKAGE_PIN BD13 [ get_ports "c0_ddr4_dqs_t[7]" ] +set_property PACKAGE_PIN BE13 [ get_ports "c0_ddr4_dqs_c[7]" ] +set_property PACKAGE_PIN BD15 [ get_ports "c0_ddr4_dq[63]" ] +set_property PACKAGE_PIN BD14 [ get_ports "c0_ddr4_dq[62]" ] +set_property PACKAGE_PIN BC14 [ get_ports "c0_ddr4_dq[61]" ] +set_property PACKAGE_PIN BC13 [ get_ports "c0_ddr4_dq[60]" ] +set_property PACKAGE_PIN BA12 [ get_ports "c0_ddr4_dm_dbi_n[6]" ] +set_property PACKAGE_PIN AY12 [ get_ports "c0_ddr4_dq[51]" ] +set_property PACKAGE_PIN AY11 [ get_ports "c0_ddr4_dq[50]" ] +set_property PACKAGE_PIN AY16 [ get_ports "c0_ddr4_dq[49]" ] +set_property PACKAGE_PIN AY15 [ get_ports "c0_ddr4_dq[48]" ] +set_property PACKAGE_PIN BB15 [ get_ports "c0_ddr4_dqs_t[6]" ] +set_property PACKAGE_PIN BB14 [ get_ports "c0_ddr4_dqs_c[6]" ] +set_property PACKAGE_PIN BA15 [ get_ports "c0_ddr4_dq[55]" ] +set_property PACKAGE_PIN BA14 [ get_ports "c0_ddr4_dq[54]" ] +set_property PACKAGE_PIN AY13 [ get_ports "c0_ddr4_dq[53]" ] +set_property PACKAGE_PIN BA13 [ get_ports "c0_ddr4_dq[52]" ] +set_property PACKAGE_PIN AW14 [ get_ports "c0_ddr4_dm_dbi_n[5]" ] +set_property PACKAGE_PIN AW16 [ get_ports "c0_ddr4_dq[43]" ] +set_property PACKAGE_PIN AW15 [ get_ports "c0_ddr4_dq[42]" ] +set_property PACKAGE_PIN AU13 [ get_ports "c0_ddr4_dq[41]" ] +set_property PACKAGE_PIN AV13 [ get_ports "c0_ddr4_dq[40]" ] +set_property PACKAGE_PIN AU14 [ get_ports "c0_ddr4_dqs_t[5]" ] +set_property PACKAGE_PIN AV14 [ get_ports "c0_ddr4_dqs_c[5]" ] +set_property PACKAGE_PIN AT15 [ get_ports "c0_ddr4_dq[47]" ] +set_property PACKAGE_PIN AU15 [ get_ports "c0_ddr4_dq[46]" ] +set_property PACKAGE_PIN AU16 [ get_ports "c0_ddr4_dq[45]" ] +set_property PACKAGE_PIN AV16 [ get_ports "c0_ddr4_dq[44]" ] +#set_property PACKAGE_PIN AT14 [ get_ports "m0_ddr4_c[4]" ] +set_property PACKAGE_PIN AR16 [ get_ports "c0_ddr4_dm_dbi_n[4]" ] +set_property PACKAGE_PIN AP15 [ get_ports "c0_ddr4_dq[35]" ] +set_property PACKAGE_PIN AP14 [ get_ports "c0_ddr4_dq[34]" ] +set_property PACKAGE_PIN AN14 [ get_ports "c0_ddr4_dq[33]" ] +set_property PACKAGE_PIN AN13 [ get_ports "c0_ddr4_dq[32]" ] +set_property PACKAGE_PIN AP13 [ get_ports "c0_ddr4_dqs_t[4]" ] +set_property PACKAGE_PIN AR13 [ get_ports "c0_ddr4_dqs_c[4]" ] +set_property PACKAGE_PIN AL15 [ get_ports "c0_ddr4_dq[39]" ] +set_property PACKAGE_PIN AM15 [ get_ports "c0_ddr4_dq[38]" ] +set_property PACKAGE_PIN AL14 [ get_ports "c0_ddr4_dq[37]" ] +set_property PACKAGE_PIN AM14 [ get_ports "c0_ddr4_dq[36]" ] \ No newline at end of file diff --git a/projects/XUSP3R/patches/rd_en.patch b/projects/XUSP3R/patches/rd_en.patch new file mode 100644 index 0000000..c0349ee --- /dev/null +++ b/projects/XUSP3R/patches/rd_en.patch @@ -0,0 +1,492 @@ +--- XUSP3R.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv +@@ -114,55 +114,86 @@ + + reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn; + (* KEEP = "true" *) reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt; +-reg [18:0] rsMask[0:7]; ++reg [19:0] rsMask[0:15]; + +-function [18:0] rs2mask; ++// RS probably stands for rank select. ++// TODO edit below in worst case. ++function [19:0] rs2mask; + input [3:0] diff; + input slot2; +-case ({diff, slot2}) +- 5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111; +- 5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110; +- 5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000; +- 5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000; ++ input slot1; ++case ({diff, slot2, slot1}) ++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111; ++ 6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000; + default: rs2mask = 19'b000_0000_1000_0000_1111; + endcase + endfunction + + always @(posedge clk) begin: blk1 +- reg [3:0] rsNdx; +- for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1) +- rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]); ++ reg [4:0] rsNdx; ++ for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1) ++ rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]); + end + + always @(*) if (rst) begin + rdEn_nxt = 'b0; + end else begin + rdEn_nxt = (rdEn >> 4) +- | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} ++ | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} + : 'b0); + end + +--- XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/rtl/cal/ddr4_v2_2_cal_rd_en.sv +@@ -114,55 +114,86 @@ + + reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn; + (* KEEP = "true" *) reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt; +-reg [18:0] rsMask[0:7]; ++reg [19:0] rsMask[0:15]; + +-function [18:0] rs2mask; ++// RS probably stands for rank select. ++// TODO edit below in worst case. ++function [19:0] rs2mask; + input [3:0] diff; + input slot2; +-case ({diff, slot2}) +- 5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111; +- 5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110; +- 5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000; +- 5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000; ++ input slot1; ++case ({diff, slot2, slot1}) ++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111; ++ 6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000; + default: rs2mask = 19'b000_0000_1000_0000_1111; + endcase + endfunction + + always @(posedge clk) begin: blk1 +- reg [3:0] rsNdx; +- for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1) +- rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]); ++ reg [4:0] rsNdx; ++ for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1) ++ rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]); + end + + always @(*) if (rst) begin + rdEn_nxt = 'b0; + end else begin + rdEn_nxt = (rdEn >> 4) +- | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} ++ | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} + : 'b0); + end + +--- XUSP3R.srcs/sources_1/ip/phy_ddr4_x8_1R/rtl/cal/ddr4_v2_2_cal_rd_en.sv +@@ -114,55 +114,86 @@ + + reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn; + (* KEEP = "true" *) reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt; +-reg [18:0] rsMask[0:7]; ++reg [19:0] rsMask[0:15]; + +-function [18:0] rs2mask; ++// RS probably stands for rank select. ++// TODO edit below in worst case. ++function [19:0] rs2mask; + input [3:0] diff; + input slot2; +-case ({diff, slot2}) +- 5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111; +- 5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110; +- 5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000; +- 5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000; ++ input slot1; ++case ({diff, slot2, slot1}) ++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111; ++ 6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000; + default: rs2mask = 19'b000_0000_1000_0000_1111; + endcase + endfunction + + always @(posedge clk) begin: blk1 +- reg [3:0] rsNdx; +- for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1) +- rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]); ++ reg [4:0] rsNdx; ++ for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1) ++ rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]); + end + + always @(*) if (rst) begin + rdEn_nxt = 'b0; + end else begin + rdEn_nxt = (rdEn >> 4) +- | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} ++ | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} + : 'b0); + end + +--- XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv +@@ -114,55 +114,86 @@ + + reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn; + (* KEEP = "true" *) reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt; +-reg [18:0] rsMask[0:7]; ++reg [19:0] rsMask[0:15]; + +-function [18:0] rs2mask; ++// RS probably stands for rank select. ++// TODO edit below in worst case. ++function [19:0] rs2mask; + input [3:0] diff; + input slot2; +-case ({diff, slot2}) +- 5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111; +- 5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110; +- 5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100; +- 5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000; +- 5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000; +- 5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000; +- 5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000; +- 5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000; +- 5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000; +- 5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000; +- 5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000; +- 5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000; +- 5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000; +- 5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000; +- 5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000; +- 5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000; ++ input slot1; ++case ({diff, slot2, slot1}) ++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111; ++ 6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110; ++ 6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100; ++ 6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000; ++ 6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000; ++ 6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000; ++ 6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000; ++ 6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000; ++ 6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000; ++ 6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000; ++ 6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000; ++ 6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000; ++ 6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000; ++ 6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000; ++ 6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000; ++ 6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000; ++ 6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000; + default: rs2mask = 19'b000_0000_1000_0000_1111; + endcase + endfunction + + always @(posedge clk) begin: blk1 +- reg [3:0] rsNdx; +- for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1) +- rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]); ++ reg [4:0] rsNdx; ++ for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1) ++ rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]); + end + + always @(*) if (rst) begin + rdEn_nxt = 'b0; + end else begin + rdEn_nxt = (rdEn >> 4) +- | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} ++ | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}} + : 'b0); + end + diff --git a/projects/XUSP3R/patches/write.patch b/projects/XUSP3R/patches/write.patch new file mode 100644 index 0000000..3ad9906 --- /dev/null +++ b/projects/XUSP3R/patches/write.patch @@ -0,0 +1,124 @@ +--- XUSP3R.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv +@@ -157,9 +157,13 @@ + // used in pushing new write CAS commands into the wrQ shift register. These values are + // calculated for both casslot0 and casslot2. + localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2; ++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2; + localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2; ++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2; + localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4; ++localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4; + localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4; ++localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4; + + integer i; + +@@ -192,10 +196,12 @@ + // Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical. + reg [3:0] oe_0_mux_cal; + wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2; +-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal; ++wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) : ++ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal); + + // tCK offset for mc. mccasSlot2 is timing critical. +-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0; ++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) : ++ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0); + + // Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical. + wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1}; + +--- XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/rtl/cal/ddr4_v2_2_cal_write.sv +@@ -157,9 +157,13 @@ + // used in pushing new write CAS commands into the wrQ shift register. These values are + // calculated for both casslot0 and casslot2. + localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2; ++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2; + localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2; ++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2; + localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4; ++localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4; + localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4; ++localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4; + + integer i; + +@@ -192,10 +196,12 @@ + // Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical. + reg [3:0] oe_0_mux_cal; + wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2; +-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal; ++wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) : ++ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal); + + // tCK offset for mc. mccasSlot2 is timing critical. +-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0; ++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) : ++ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0); + + // Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical. + wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1}; + +--- XUSP3R.srcs/sources_1/ip/phy_ddr4_x8_1R/rtl/cal/ddr4_v2_2_cal_write.sv +@@ -157,9 +157,13 @@ + // used in pushing new write CAS commands into the wrQ shift register. These values are + // calculated for both casslot0 and casslot2. + localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2; ++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2; + localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2; ++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2; + localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4; ++localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4; + localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4; ++localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4; + + integer i; + +@@ -192,10 +196,12 @@ + // Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical. + reg [3:0] oe_0_mux_cal; + wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2; +-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal; ++wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) : ++ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal); + + // tCK offset for mc. mccasSlot2 is timing critical. +-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0; ++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) : ++ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0); + + // Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical. + wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1}; + +--- XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv +@@ -157,9 +157,13 @@ + // used in pushing new write CAS commands into the wrQ shift register. These values are + // calculated for both casslot0 and casslot2. + localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2; ++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2; + localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2; ++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2; + localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4; ++localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4; + localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4; ++localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4; + + integer i; + +@@ -192,10 +196,12 @@ + // Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical. + reg [3:0] oe_0_mux_cal; + wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2; +-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal; ++wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) : ++ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal); + + // tCK offset for mc. mccasSlot2 is timing critical. +-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0; ++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) : ++ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0); + + // Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical. + wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1}; + diff --git a/projects/XUSP3R/verilog/ddr4_adapter.v b/projects/XUSP3R/verilog/ddr4_adapter.v new file mode 100644 index 0000000..20f1e10 --- /dev/null +++ b/projects/XUSP3R/verilog/ddr4_adapter.v @@ -0,0 +1,361 @@ +`include "parameters.vh" +`include "project.vh" +// Convert MC emitted DFI signals to a specific DDR4 PHY interface (mem_clock = 4xfab_clk) +// Note that this is a bit hardcoded, but it could be made more flexible to satisfy +// wider (can issue more than 4 commands each fab cycle) PHY interfaces. +// DBUF_WIDTH specifies how many bursts of data will be buffered +// before being issued to DRAM. + +`define ADDR_WIDTH 17 + +module ddr4_adapter #(parameter CKE_WIDTH = 1, RANK_WIDTH = 1, DQ_WIDTH = 64, DRAM_CMD_SLOTS = 4, + DATA_BUF_ADDR_WIDTH = 5, DBUF_WIDTH = 4, DQ_BURST = 8) + +( + // common signals + input clk, + input rst, + + //other control signals + input init_calib_complete, + //input process_iseq, + + // ddr_pipeline <-> outer module if + input [3:0] ddr_write, + input [3:0] ddr_read, + input [3:0] ddr_pre, + input [3:0] ddr_act, + input [3:0] ddr_ref, + input [3:0] ddr_zq, + input [3:0] ddr_nop, + input [3:0] ddr_ap, + input [3:0] ddr_half_bl, + input [3:0] ddr_pall, + input [4*`BG_WIDTH-1:0] ddr_bg, + input [4*`BANK_WIDTH-1:0] ddr_bank, + input [4*`COL_WIDTH-1:0] ddr_col, + input [4*`ROW_WIDTH-1:0] ddr_row, + input [511:0] ddr_wdata, + + // periodic maintenance signals + input ddr_maint_read, // next read will be a maintenance read + + // DDR4-PHY signals + output [DATA_BUF_ADDR_WIDTH-1:0] dBufAdr, // Reserved. Should be tied low. + output [DQ_WIDTH*8-1:0] wrData, // DRAM write data. There are 8 bits for each DQ lane on the DRAM bus. + output [DQ_WIDTH-1:0] wrDataMask,// DRAM write DM/DBI port.There is one bit for each byte of the wrData port. + input wrDataEn, // Write data Enable. The Phy will assert this port for one cycle for each write CAS command. + output [7:0] mc_ACT_n, // DRAM ACT_n command signal for four DRAM clock cycles. + output [`ADDR_WIDTH*8-1:0] mc_ADR, // DRAM address. There are 8 bits in the fabric interface for each address bit on the DRAM bus. + output [`BANK_WIDTH*8-1:0] mc_BA, // DRAM bank address. 8 bits for each DRAM bank address. + output [`BG_WIDTH*8-1:0] mc_BG, // DRAM bank group address. + output [`CS_WIDTH*8-1:0] mc_CS_n, // DRAM CS_n + + //output [`ODT_WIDTH*8-1:0] mc_ODT, // DRAM ODT + output mcRdCAS, // Read CAS command issued. + output mcWrCAS, // Write CAS command issued. + output [1:0] winRank, // Target rank for CAS commands. This value indicates which rank a CAS command is issued to. + output [4:0] winBuf, // Optional control signal. When either mcRdCAS or mcWrCAS is asserted, the Phy will store the value on the winBuf signal. + // input [DQ_WIDTH*8-1:0] rdData, // DRAM read data. + input rdDataEn, // Read data valid. This signal asserts for one fabric cycle for each completed read operation. + input rdDataEnd, // Unused. Tied high. + output [1:0] mcCasSlot, + output mcCasSlot2, + output gt_data_ready, + + output iss_dummy_read + ); + + assign winRank = 2'b0; // single rank -> tie to 0 + assign winBuf = 4'b0; // TODO don't know how this could be used + assign dBufAdr = {DATA_BUF_ADDR_WIDTH{1'b0}}; + + reg [DQ_BURST*DQ_WIDTH-1:0] ddr_wdata_r; + + reg [2*DQ_BURST*DQ_WIDTH-1:0] wrDataBuf, wrDataBuf_ns; + reg slot1_full, slot1_full_ns; + reg slot2_full, slot2_full_ns; + + assign wrData = wrDataBuf[0+:DQ_BURST*DQ_WIDTH]; + + reg iss_dummy_read_r, iss_dummy_read_ns; + reg read_will_be_dummy_r, read_will_be_dummy_ns; + + assign iss_dummy_read = iss_dummy_read_r; + + reg init_calib_complete_r; // can't issue any commands until this signal is asserted + + reg wrDataEn_r; // to delay wrDataEn by one clock cycle + reg [7:0] ACT_n_ns, ACT_n_r; + reg [`ADDR_WIDTH*8-1:0] ADR_ns, ADR_r; + reg [`BANK_WIDTH*8-1:0] BA_ns, BA_r; + reg [`BG_WIDTH*8-1:0] BG_ns, BG_r; + reg [`CS_WIDTH*8-1:0] CS_n_ns, CS_n_r; + reg [`ODT_WIDTH*8-1:0] ODT_ns, ODT_r; + reg RdCAS_ns, RdCAS_r; + reg WrCAS_ns, WrCAS_r; + + reg [1:0] mcCasSlot_r, mcCasSlot_ns; + reg gt_data_ready_r, gt_data_ready_ns; + + // TODO - PG 150 - page 180 + // Specifically, the PHY requires the following after calDone asserts: + // 1. At least one read command every 1 μs. For a multi-rank system any rank is acceptable. + // 2. The gt_data_ready signal is asserted for one system clock cycle after rdDataEn or + // per_rd_done signal asserts at least once within each 1 μs interval. + // 3. There is a three contiguous system clock cycle period with no read CAS commands + // asserted at the PHY interface every 1 μs. + // Somehow enforce above requirements to our PHY command stream, if it is not implicitly + // handled by the controller's maintenance handler modules. + // To drive gt_data_ready + assign gt_data_ready = gt_data_ready_r; + + assign mcCasSlot = mcCasSlot_r; + assign mcCasSlot2 = mcCasSlot[1]; + + assign wrDataMask = {DQ_WIDTH{1'b0}}; + assign mc_ACT_n = ACT_n_r; + assign mc_ADR = ADR_r; + assign mc_BA = BA_r; + assign mc_BG = BG_r; + assign mc_CS_n = CS_n_r; + assign mcRdCAS = RdCAS_r; + assign mcWrCAS = WrCAS_r; + + + integer mc_cmd_i; // iterate over softmc dfi commands + integer adr_bit_i; // iterate over dfi address bits + integer bank_bit_i; // iterate over bank number bits + integer bg_bit_i; // iterate over bank group bits + always@* begin + wrDataBuf_ns = wrDataBuf; + slot1_full_ns = slot1_full; + slot2_full_ns = slot2_full; + ACT_n_ns = {8{`HIGH}}; + ADR_ns = {`ROW_WIDTH*8{1'bx}}; + BA_ns = {`BANK_WIDTH*8{1'bx}}; + BG_ns = {`BG_WIDTH*8{1'bx}}; + CS_n_ns = {`CS_WIDTH*8{1'b1}}; // NOP + ODT_ns = {`ODT_WIDTH*8{1'bx}}; + RdCAS_ns = 1'b0; + WrCAS_ns = 1'b0; + mcCasSlot_ns = 2'b0; + iss_dummy_read_ns = iss_dummy_read_r; + read_will_be_dummy_ns = ddr_maint_read || read_will_be_dummy_r; + + // assign DDR4 PHY address signals + // each pair of bits in a byte corresponds + // to each slot's command address bit + // e.g. ADR[1:0] is slot0's command address bit 0 + // ADR[3:2] is slot1's command address bit 0 + // ADR[9:8] is slot0's command address bit 1... + + // Assume that every command works with column addresses + // ACTs will overwrite LSBs later + for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin + for(adr_bit_i = 0 ; adr_bit_i < `COL_WIDTH ; adr_bit_i = adr_bit_i + 1) begin + ADR_ns[adr_bit_i*8 + mc_cmd_i*2 +: 2] = + {2{ddr_col[mc_cmd_i*`COL_WIDTH + adr_bit_i]}}; + end + end + + // ACTs overwriting LSBs here + for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin + for(adr_bit_i = 0 ; adr_bit_i < `ROW_WIDTH ; adr_bit_i = adr_bit_i + 1) begin + if(ddr_act[mc_cmd_i]) + ADR_ns[adr_bit_i*8 + mc_cmd_i*2 +: 2] = + {2{ddr_row[mc_cmd_i*`ROW_WIDTH + adr_bit_i]}}; + end + end + + // Set bank and bank group signals + for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin + for(bank_bit_i = 0 ; bank_bit_i < `BANK_WIDTH ; bank_bit_i = bank_bit_i + 1) begin + BA_ns[bank_bit_i*8 + mc_cmd_i*2 +: 2] = + {2{ddr_bank[mc_cmd_i*`BANK_WIDTH + bank_bit_i]}}; + end + end + for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin + for(bg_bit_i = 0 ; bg_bit_i < `BG_WIDTH ; bg_bit_i = bg_bit_i + 1) begin + BG_ns[bg_bit_i*8 + mc_cmd_i*2 +: 2] = + {2{ddr_bg[mc_cmd_i*`BG_WIDTH + bg_bit_i]}}; + end + end + + // Set misc. signals (ap, bl4, precharge all) + for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin + if(ddr_ap[mc_cmd_i]) + ADR_ns[10*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; + else if(ddr_write[mc_cmd_i] | ddr_read[mc_cmd_i]) + ADR_ns[10*8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; + if(ddr_half_bl[mc_cmd_i]) + ADR_ns[12*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; + else if(ddr_write[mc_cmd_i] | ddr_read[mc_cmd_i]) + ADR_ns[12*8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; + if(ddr_pall[mc_cmd_i]) + ADR_ns[10*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; + else if(ddr_pre[mc_cmd_i]) + ADR_ns[10*8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; + if(ddr_zq[mc_cmd_i]) // ZQ short + ADR_ns[10*8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; + end + + // For each command slot, decode the commands + // and hopefully convert those to Xilinx PHY + // compatible commands. + for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin + if(ddr_nop[mc_cmd_i]) begin // NOP + // set chip select to HI + CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {1*2{`HIGH}}; + end + else if(ddr_act[mc_cmd_i]) begin // Activate ROW + // There seems to be something wrong with the dfi_cs signal widths + // coming from the mc. Consider LSBs as valid CS signals for now + CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {2*1{`LOW}}; + ACT_n_ns[mc_cmd_i*2 +: 2] = {2{`LOW}}; + end // Activate + else if(ddr_read[mc_cmd_i] || ddr_write[mc_cmd_i]) begin // DDR Read or Write + mcCasSlot_ns = mc_cmd_i[0 +: 2]; + CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {2*1{`LOW}}; + if(ddr_write[mc_cmd_i]) begin // Write burst + ADR_ns[`ADDR_WIDTH*8-3*8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; // WE + ADR_ns[`ADDR_WIDTH*8-2*8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; // CAS + ADR_ns[`ADDR_WIDTH*8-8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~RAS + //fifo_wr_en = HIGH; + WrCAS_ns = `HIGH; + end + else begin // Read burst + ADR_ns[`ADDR_WIDTH*8-3*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~WE + ADR_ns[`ADDR_WIDTH*8-2*8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; // CAS + ADR_ns[`ADDR_WIDTH*8-8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~RAS + RdCAS_ns = `HIGH; + iss_dummy_read_ns = read_will_be_dummy_r; + read_will_be_dummy_ns = `LOW; + end + end // DDR Read-Write + else if(ddr_pre[mc_cmd_i]) begin // Precharge + CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {2*1{`LOW}}; + ADR_ns[`ADDR_WIDTH*8-3*8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; // WE + ADR_ns[`ADDR_WIDTH*8-2*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~CAS + ADR_ns[`ADDR_WIDTH*8-8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; // RAS + end // Precharge + else if(ddr_ref[mc_cmd_i]) begin // Refresh + CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {2*1{`LOW}}; + ADR_ns[`ADDR_WIDTH*8-3*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~WE + ADR_ns[`ADDR_WIDTH*8-2*8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; // CAS + ADR_ns[`ADDR_WIDTH*8-8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; // RAS + end + else if(ddr_zq[mc_cmd_i]) begin // ZQ Calib + CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {2*1{`LOW}}; + ADR_ns[`ADDR_WIDTH*8-3*8 + mc_cmd_i*2 +: 2] = {2{`LOW}}; // WE + ADR_ns[`ADDR_WIDTH*8-2*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~CAS + ADR_ns[`ADDR_WIDTH*8-8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~RAS + end + end // decode block end + + if(WrCAS_r) begin + if(slot1_full && slot2_full && wrDataEn_r) begin + wrDataBuf_ns[0+:DQ_BURST*DQ_WIDTH] = wrDataBuf[DQ_BURST*DQ_WIDTH +: DQ_BURST*DQ_WIDTH]; + wrDataBuf_ns[DQ_BURST*DQ_WIDTH+:DQ_BURST*DQ_WIDTH] = ddr_wdata_r; + end + else if (slot1_full && wrDataEn_r) begin + wrDataBuf_ns[0+:DQ_BURST*DQ_WIDTH] = ddr_wdata_r; + end + else if (slot1_full) begin + wrDataBuf_ns[DQ_BURST*DQ_WIDTH+:DQ_BURST*DQ_WIDTH] = ddr_wdata_r; + slot2_full_ns = `HIGH; + end + else begin + wrDataBuf_ns[0+:DQ_BURST*DQ_WIDTH] = ddr_wdata_r; + slot1_full_ns = `HIGH; + end + end + + // We handle the cases where a wrDataEn and dfi CAS commands + // arrive at the same time + if(wrDataEn_r && ~WrCAS_r) begin + if(slot1_full && slot2_full) begin + wrDataBuf_ns[0+:DQ_BURST*DQ_WIDTH] = wrDataBuf[DQ_BURST*DQ_WIDTH +: DQ_BURST*DQ_WIDTH]; + slot2_full_ns = `LOW; + end + else if (slot1_full) begin + slot1_full_ns = `LOW; + end + end + + if(rdDataEn) begin + if(RdCAS_r) // issued another CAS read this cycle + iss_dummy_read_ns = ddr_maint_read; + else + iss_dummy_read_ns = `LOW; + end + + gt_data_ready_ns = iss_dummy_read_r & rdDataEn; + // this assumes CAS_rw_ctr is either 0, 1 or 2 + //mcCasSlot_ns[1] = CAS_rw_ctr[DRAM_CMD_SLOTS-1][1]; + //mcCasSlot_ns[0] = CAS_rw_ctr[DRAM_CMD_SLOTS-1][0]; + end + + always@(posedge clk) begin + if(rst) begin + wrDataBuf <= {DQ_WIDTH*DQ_BURST{1'b0}}; + init_calib_complete_r <= 1'b0; + iss_dummy_read_r <= 1'b0; + read_will_be_dummy_r <= 1'b0; + wrDataEn_r <= 1'b0; + ACT_n_r <= {8{`HIGH}}; + ADR_r <= {`ADDR_WIDTH*8{1'bx}}; + BA_r <= {`BANK_WIDTH*8{1'bx}}; + BG_r <= {`BG_WIDTH*8{1'bx}}; + CS_n_r <= {`CS_WIDTH*8{1'b1}}; //NOP + ODT_r <= {`ODT_WIDTH*8{1'bx}}; + //fifo_wr_en_r <= 1'b0; + WrCAS_r <= 1'b0; + RdCAS_r <= 1'b0; + mcCasSlot_r <= 2'b0; + slot1_full <= `LOW; + slot2_full <= `LOW; + gt_data_ready_r <= 1'b0; + end + else begin + if(init_calib_complete_r) begin + ddr_wdata_r <= ddr_wdata; + slot1_full <= slot1_full_ns; + slot2_full <= slot2_full_ns; + wrDataBuf <= wrDataBuf_ns; + iss_dummy_read_r <= iss_dummy_read_ns; + read_will_be_dummy_r <= read_will_be_dummy_ns; + wrDataEn_r <= wrDataEn; + ACT_n_r <= ACT_n_ns; + ADR_r <= ADR_ns; + BA_r <= BA_ns; + BG_r <= BG_ns; + CS_n_r <= CS_n_ns; + ODT_r <= ODT_ns; + WrCAS_r <= WrCAS_ns; + RdCAS_r <= RdCAS_ns; + //fifo_wr_en_r <= fifo_wr_en_ns; + mcCasSlot_r <= mcCasSlot_ns; + gt_data_ready_r <= gt_data_ready_ns; + end + else begin + slot1_full <= `LOW; + slot2_full <= `LOW; + wrDataBuf <= {DQ_WIDTH*DQ_BURST{1'b0}}; + init_calib_complete_r <= init_calib_complete_r | init_calib_complete; + iss_dummy_read_r <= `LOW; + read_will_be_dummy_r <= `LOW; + ACT_n_r <= {8{`HIGH}}; + ADR_r <= {`ADDR_WIDTH*8{1'b1}}; + BA_r <= {`BANK_WIDTH*8{1'b1}}; + BG_r <= {`BG_WIDTH*8{1'b1}}; + CS_n_r <= {`CS_WIDTH*8{1'b1}}; + WrCAS_r <= 1'b0; + RdCAS_r <= 1'b0; + //fifo_wr_en_r <= 1'b0; + mcCasSlot_r <= 2'b0; + gt_data_ready_r <= 1'b0; + end + end + end +endmodule diff --git a/projects/XUSP3R/verilog/ddr4_mc_odt.v b/projects/XUSP3R/verilog/ddr4_mc_odt.v new file mode 100644 index 0000000..d8b4940 --- /dev/null +++ b/projects/XUSP3R/verilog/ddr4_mc_odt.v @@ -0,0 +1,130 @@ +// Auto-generated, DDR4 SDRAM Example Design source +// small modifications to issue writes from all command slots +module ddr4_mc_odt #(parameter + ODTWR = 16'h8421 + ,ODTWRDEL = 5'd9 + ,ODTWRDUR = 4'd6 + ,ODTWRODEL = 5'd9 + ,ODTWRODUR = 4'd6 + + ,ODTRD = 16'h8421 + ,ODTRDDEL = 5'd9 + ,ODTRDDUR = 4'd6 + ,ODTRDODEL = 5'd9 + ,ODTRDODUR = 4'd6 + + ,ODTBITS = 4 + ,ODTNOP = 4'b0000 + ,TCQ = 0.1 + )( + input clk + ,input rst + + ,output [ODTBITS*8-1:0] mc_ODT + + ,input casSlot2 + ,input [1:0] casSlot + ,input [1:0] rank + ,input winRead + ,input winWrite + ,input tranSentC + ); + + // ========================================================================================== + // ODT is a multi-fabric-cycle waveform that needs to assert on the same cycle as write CAS, + // and also on the same cycle as read CAS when tCL=tCWL. This block generates the full + // multi-cycle ODT waveform in the same cycle that rdCAS or wrCAS is generated, bypassing + // the first 8 bits per ODT pin to mc_ODT combinationally, and flopping the remaining bits + // in a shift register which are then sent to the XiPhy 8 bits per pin per cycle. If CAS + // commands are issued so that the current ODT waveform overlaps with the waveform from + // previous commands, the waveforms will be OR'd together. + // Note: The original Olympus ODT block had separate timing for the selected rank and + // non-target ranks. This version of the code does not support this. + // ========================================================================================== + + + // ========================================================================================== + // Signal Declarations + // ========================================================================================== + + // Structures holding multi-fabric-cycle ODT pin waveforms for current CAS transaction + wire [31:0] odt_array [ ODTBITS-1:0 ]; + wire [31:0] odt_transent [ ODTBITS-1:0 ]; + + // Shift register holding ODT pin waveforms for previous CAS transactions + reg [23:0] odt_shift [ ODTBITS-1:0 ]; + wire [23:0] odt_shift_nxt[ ODTBITS-1:0 ]; + + // ODT pin waveform for current fabric cycle, with time going from msb to lsb, reverse for XiPhy order + wire [ 7:0] odt_reverse [ ODTBITS-1:0 ]; + + + // ========================================================================================== + // Module Code + // ========================================================================================== + + // Set up basic write ODT timing waveform. Note that time increases moving from msb to lsb. + wire [31:0] odt_pulse_wr_slot0 = 32'hff_ff_ff_ff << (32 - 2*ODTWRDUR); + wire [31:0] odt_pulse_wr_slot1 = odt_pulse_wr_slot0 >> 2; + wire [31:0] odt_pulse_wr_slot2 = odt_pulse_wr_slot0 >> 4; + wire [31:0] odt_pulse_wr_slot3 = odt_pulse_wr_slot0 >> 6; + + // Set up basic read ODT timing waveform. Note that time increases moving from msb to lsb. + wire [31:0] odt_pulse_rd_slot0 = ( 32'hff_ff_ff_ff << (32 - 2*ODTRDDUR) ) >> ( 2*( ODTRDDEL - ODTWRDEL ) ); + wire [31:0] odt_pulse_rd_slot1 = odt_pulse_rd_slot0 >> 2; + wire [31:0] odt_pulse_rd_slot2 = odt_pulse_rd_slot0 >> 4; + wire [31:0] odt_pulse_rd_slot3 = odt_pulse_rd_slot0 >> 6; + + // Select ODT timing waveform based on winning command type and slot position + wire [31:0] win_odt_pulse_slot0 = winRead ? odt_pulse_rd_slot0 : odt_pulse_wr_slot0; + wire [31:0] win_odt_pulse_slot1 = winRead ? odt_pulse_rd_slot1: odt_pulse_wr_slot1; + wire [31:0] win_odt_pulse_slot2 = winRead ? odt_pulse_rd_slot2 : odt_pulse_wr_slot2; + wire [31:0] win_odt_pulse_slot3 = winRead ? odt_pulse_rd_slot3 : odt_pulse_wr_slot3; + wire [31:0] win_odt_pulse = casSlot2 ? (casSlot[0] ? win_odt_pulse_slot3 : win_odt_pulse_slot2) + : (casSlot[0] ? win_odt_pulse_slot1 : win_odt_pulse_slot0); + + // Select ODT pin pattern based on winning command type and rank + wire [15:0] win_odt_cmd_pat = winRead ? ODTRD : ODTWR; + wire [ 3:0] win_odt_pat = { 4 { winRead | winWrite } } & win_odt_cmd_pat[ 4*rank +:4 ]; // spyglass disable W498 + + genvar odt_pin; + generate + for (odt_pin = 0; odt_pin < ODTBITS; odt_pin = odt_pin + 1) begin + // Combine selected waveform and pattern to generate full ODT output for the current winning CAS command + assign odt_array[odt_pin] = { 32 { win_odt_pat[ odt_pin ] } } & win_odt_pulse; + + // Qualify with tranSendC + assign odt_transent[odt_pin] = { 32 { tranSentC } } & odt_array[ odt_pin ]; + + // Parallel load lower 24 bits of qualified ODT output into shift register + assign odt_shift_nxt[odt_pin] = odt_transent[odt_pin][23:0] | { odt_shift[odt_pin][15:0], 8'b0 }; + + // Combine the upper 8 bits of the odt output for the new transaction (bypass path) with + // the upper 8 bits of the shift register output to generate the odt block's output + assign odt_reverse[odt_pin] = odt_transent[odt_pin][31:24] | odt_shift[odt_pin][23:16]; + + // Reverse the msb/lsb order. XiPhy wants increasing time going from lsb to msb + assign mc_ODT[odt_pin*8+:8] = { odt_reverse[odt_pin][0], odt_reverse[odt_pin][1], odt_reverse[odt_pin][2], odt_reverse[odt_pin][3], + odt_reverse[odt_pin][4], odt_reverse[odt_pin][5], odt_reverse[odt_pin][6], odt_reverse[odt_pin][7] }; + end + endgenerate + + + // ========================================================================================== + // Reset flops + // ========================================================================================== + + integer i; + always @(posedge clk) begin + if (rst) begin + for (i = 0; i < ODTBITS; i = i + 1) begin + odt_shift[i] <= #TCQ 28'b0; + end + end else begin + for (i = 0; i < ODTBITS; i = i + 1) begin + odt_shift[i] <= #TCQ odt_shift_nxt[i]; + end + end + end + +endmodule diff --git a/projects/XUSP3R/verilog/project.vh b/projects/XUSP3R/verilog/project.vh new file mode 100644 index 0000000..4df0b82 --- /dev/null +++ b/projects/XUSP3R/verilog/project.vh @@ -0,0 +1,21 @@ +`define XUPP3R_x8_1R_UDIMM// MIG does not support DM|DBI w/ RDIMMs. +`define DQ_WIDTH 64 + +// DIMM related - x8 double ranks +`ifdef XUPP3R_x8 +`define ODT_WIDTH 2 +`define CS_WIDTH 2 +`define CKE_WIDTH 2 +`define CK_WIDTH 1 +`elsif XUPP3R_x8_1R_UDIMM // Redundant here aswell. +`define ODT_WIDTH 1 +`define CS_WIDTH 1 +`define CKE_WIDTH 1 +`define CK_WIDTH 1 +`elsif XUPP3R_x4 +// DEFAULT CONFIGS USE BELOW +`define ODT_WIDTH 1 +`define CS_WIDTH 1 +`define CKE_WIDTH 1 +`define CK_WIDTH 1 +`endif \ No newline at end of file diff --git a/projects/XUSP3R/verilog/softmc_top.v b/projects/XUSP3R/verilog/softmc_top.v new file mode 100644 index 0000000..66ea891 --- /dev/null +++ b/projects/XUSP3R/verilog/softmc_top.v @@ -0,0 +1,842 @@ +`include "parameters.vh" +`include "project.vh" + +`ifdef XUPP3R_x4 + `define XUPP3R +`elsif XUPP3R_x8 + `define XUPP3R +`elsif XUPP3R_x8_1R_UDIMM + `define XUPP3R +`endif + + +module softmc_top #(parameter tCK = 1500, SIM = "false") + ( + // common signals + input c0_sys_clk_p, + input c0_sys_clk_n, + input sys_rst_l, + + // iob <> ddr4 sdram ip signals + output c0_ddr4_act_n, + output [16:0] c0_ddr4_adr, + output [1:0] c0_ddr4_ba, + output [1:0] c0_ddr4_bg, + output [`CKE_WIDTH-1:0] c0_ddr4_cke, + output [`ODT_WIDTH-1:0] c0_ddr4_odt, + output [`CS_WIDTH-1:0] c0_ddr4_cs_n, + output [`CK_WIDTH-1:0] c0_ddr4_ck_t, + output [`CK_WIDTH-1:0] c0_ddr4_ck_c, + output c0_ddr4_reset_n, + `ifdef XUPP3R_x4 + inout [17:0] c0_ddr4_dqs_c, + inout [17:0] c0_ddr4_dqs_t, + inout [71:0] c0_ddr4_dq, + output c0_ddr4_parity, + `elsif XUPP3R_x8 + inout [8:0] c0_ddr4_dm_dbi_n, + inout [71:0] c0_ddr4_dq, + inout [8:0] c0_ddr4_dqs_c, + inout [8:0] c0_ddr4_dqs_t, + output c0_ddr4_parity, + `else + inout [7:0] c0_ddr4_dm_dbi_n, + inout [63:0] c0_ddr4_dq, + inout [7:0] c0_ddr4_dqs_c, + inout [7:0] c0_ddr4_dqs_t, + `endif + // xdma signals + input clk_ref_p, + input clk_ref_n, + input pcie_rst, + output [7:0] pci_exp_txp, + output [7:0] pci_exp_txn, + input [7:0] pci_exp_rxp, + input [7:0] pci_exp_rxn + + ); + + `ifdef XUPP3R_x8 + assign c0_ddr4_odt[1] = 1'b0; + assign c0_ddr4_cs_n[1] = 1'b1; + assign c0_ddr4_cke[1] = 1'b0; + assign c0_ddr4_parity = 1'b0; + `endif + + // Frontend control signals + wire softmc_fin; + wire user_rst; + + // Frontend <-> Fetch signals + wire [`IMEM_ADDR_WIDTH-1:0] fr_addr_in; + wire fr_valid_in; + wire [`INSTR_WIDTH-1:0] fr_data_out; + wire fr_valid_out; + wire [`IMEM_ADDR_WIDTH-1:0] fr_addr_out; + wire fr_ready_out; + + // Frontend <-> misc. control signals + wire per_rd_init; + wire per_zq_init; + wire per_ref_init; + wire rbe_switch_mode; + wire toggle_dll; + + // AXI streaming ports + wire [`XDMA_AXI_DATA_WIDTH-1:0] m_axis_h2c_tdata_0,xdma_h2c_tdata_0; + wire m_axis_h2c_tlast_0, xdma_h2c_tlast_0; + wire m_axis_h2c_tvalid_0, xdma_h2c_tvalid_0; + wire m_axis_h2c_tready_0, xdma_h2c_tready_0; + wire [`XDMA_AXI_DATA_WIDTH/8-1:0] m_axis_h2c_tkeep_0, xdma_h2c_tkeep_0; + wire [`XDMA_AXI_DATA_WIDTH-1:0] s_axis_c2h_tdata_0, xdma_c2h_tdata_0; + wire s_axis_c2h_tlast_0, xdma_c2h_tlast_0; + wire s_axis_c2h_tvalid_0, xdma_c2h_tvalid_0; + wire s_axis_c2h_tready_0, xdma_c2h_tready_0; + wire [`XDMA_AXI_DATA_WIDTH/8-1:0] s_axis_c2h_tkeep_0, xdma_c2h_tkeep_0; + + // ddr_pipeline <-> outer module if + wire [3:0] ddr_write; + wire [3:0] ddr_read; + wire [3:0] ddr_pre; + wire [3:0] ddr_act; + wire [3:0] ddr_ref; + wire [3:0] ddr_sre; + wire [3:0] ddr_srx; + wire [3:0] ddr_zq; + wire [3:0] ddr_nop; + wire [3:0] ddr_ap; + wire [3:0] ddr_pall; + wire [3:0] ddr_half_bl; + wire [4*`BG_WIDTH-1:0] ddr_bg; + wire [4*`BANK_WIDTH-1:0] ddr_bank; + wire [4*`COL_WIDTH-1:0] ddr_col; + wire [4*`ROW_WIDTH-1:0] ddr_row; + wire [511:0] ddr_wdata; + + // periodic maintenance signals + wire ddr_maint_read; + + // phy <-> ddr adapter and xdma app signals + // dlltoggler + wire clk_sel = 0; + wire [7:0] dllt_mc_ACT_n; + wire [135:0] dllt_mc_ADR; + wire [15:0] dllt_mc_BA; + wire [15:0] dllt_mc_BG; + wire [7:0] dllt_mc_CKE; + wire [7:0] dllt_mc_CS_n; + wire dllt_done; + // ddr adapter + wire [4:0] dBufAdr; + wire [`DQ_WIDTH*8-1:0] wrData; + wire [`DQ_WIDTH-1:0] wrDataMask; + wire [511:0] rdData; + wire [4:0] rdDataAddr; + wire [0:0] rdDataEn; + wire [0:0] rdDataEnd; + wire [0:0] per_rd_done; + wire [0:0] rmw_rd_done; + wire [4:0] wrDataAddr; + wire [0:0] wrDataEn; + wire [7:0] mc_ACT_n; + wire [135:0] mc_ADR; + wire [15:0] mc_BA; + wire [15:0] mc_BG; + wire [`CKE_WIDTH*8-1:0] mc_CKE; + wire [`CS_WIDTH*8-1:0] mc_CS_n; + wire [`ODT_WIDTH*8-1:0] mc_ODT; + wire [0:0] mcRdCAS; + wire [0:0] mcWrCAS; + wire [0:0] winInjTxn; + wire [0:0] winRmw; + wire [4:0] winBuf; + wire [1:0] winRank; + wire [5:0] tCWL; + wire dbg_clk; + wire c0_wr_rd_complete; + wire c0_ddr4_clk; + wire c0_ddr4_dll_off_clk; + wire ddr4_ui_clk; + wire c0_ddr4_rst; + wire [511:0] dbg_bus; + wire [1:0] mcCasSlot; + wire mcCasSlot2; + wire gt_data_ready; + + wire read_seq_incoming; // next few instructions will read from DRAM + wire [11:0] incoming_reads; // how many reads next few instructions will issue + wire [11:0] buffer_space; // remaining buffer size + + wire sys_rst = ~sys_rst_l; // low active signal + wire c0_init_calib_complete; + + // There is a possibility that these signals are on + // the critical path as observed in + // the previous iteration of SoftMC + reg c0_init_calib_complete_r, sys_rst_r; + wire iq_full, processing_iseq, rdback_fifo_empty; + + always @(posedge c0_ddr4_clk) begin + c0_init_calib_complete_r <= c0_init_calib_complete; + sys_rst_r <= sys_rst; + end + + reg dllt_active = 1'b0; + + `ifdef ENABLE_DLL_TOGGLER + always @(posedge c0_ddr4_clk) begin + if(toggle_dll) begin + dllt_active <= ~dllt_active; + end + if(dllt_done) begin + dllt_active <= ~dllt_active; + end + end + `endif + + `ifdef XUPP3R_x8 + phy_ddr4_x8 phy_ddr4_i( + .sys_rst (sys_rst), + .c0_sys_clk_p (c0_sys_clk_p), + .c0_sys_clk_n (c0_sys_clk_n), + `ifdef ENABLE_DLL_TOGGLER + .c0_ddr4_ui_clk (ddr4_ui_clk), + .addn_ui_clkout1 (c0_ddr4_dll_off_clk), + `else + .c0_ddr4_ui_clk (c0_ddr4_clk), + `endif + .c0_ddr4_ui_clk_sync_rst (c0_ddr4_rst), + .c0_init_calib_complete (c0_init_calib_complete), + .dbg_clk (dbg_clk), + .c0_ddr4_act_n (c0_ddr4_act_n), + .c0_ddr4_adr (c0_ddr4_adr), + .c0_ddr4_ba (c0_ddr4_ba), + .c0_ddr4_bg (c0_ddr4_bg), + .c0_ddr4_cke (c0_ddr4_cke[0]), + .c0_ddr4_odt (c0_ddr4_odt[0]), + .c0_ddr4_cs_n (c0_ddr4_cs_n[0]), + .c0_ddr4_ck_t (c0_ddr4_ck_t), + .c0_ddr4_ck_c (c0_ddr4_ck_c), + .c0_ddr4_reset_n (c0_ddr4_reset_n), + .c0_ddr4_parity (c0_ddr4_parity), + .wrDataMask (wrDataMask), + .c0_ddr4_dm_dbi_n (c0_ddr4_dm_dbi_n), + .c0_ddr4_dq (c0_ddr4_dq), + .c0_ddr4_dqs_c (c0_ddr4_dqs_c), + .c0_ddr4_dqs_t (c0_ddr4_dqs_t), + + .dBufAdr (dBufAdr), + .wrData (wrData), + .rdData (rdData), + .rdDataAddr (rdDataAddr), + .rdDataEn (rdDataEn), + .rdDataEnd (rdDataEnd), + .per_rd_done (per_rd_done), + .rmw_rd_done (rmw_rd_done), + .wrDataAddr (wrDataAddr), + .wrDataEn (wrDataEn), + + .mc_ACT_n (dllt_active ? dllt_mc_ACT_n : mc_ACT_n), + .mc_ADR (dllt_active ? dllt_mc_ADR : mc_ADR), + .mc_BA (dllt_active ? dllt_mc_BA : mc_BA), + .mc_BG (dllt_active ? dllt_mc_BG : mc_BG), + .mc_CKE (dllt_active ? dllt_mc_CKE : {8{1'b1}}), + .mc_CS_n (dllt_active ? dllt_mc_CS_n : mc_CS_n), + .mc_ODT (mc_ODT), + // CAS command slot select. Slot0 is enabled for example design. + .mcCasSlot (dllt_active ? 2'b0 : mcCasSlot), + // CAS slot 2 select. mcCasSlot2 serves a similar purpose as the mcCasSlot[1:0] signal, but mcCasSlot2 is used in timing + // critical logic in the Phy. Slot0 is enabled for example design. + .mcCasSlot2 (dllt_active ? 1'b0 : mcCasSlot2), + .mcRdCAS (dllt_active ? 1'b0 : mcRdCAS), + .mcWrCAS (dllt_active ? 1'b0 : mcWrCAS), + // Optional read command type indication. The winInjTxn signal is set to '0' for example design. + .winInjTxn ({1{1'b0}}), + // Optional read command type indication. The winRmw signal is set to '0' for example design. + .winRmw ({1{1'b0}}), + // Update VT Tracking. The gt_data_ready signal is set to '0' in this example design. + // This signal must be asserted periodically to keep the DQS Gate aligned as voltage and temperature drift. + // For more information, Refer to PG150 document. + .gt_data_ready (gt_data_ready), + .winBuf (winBuf), + .winRank (winRank), + .tCWL (tCWL), + // Debug Port + .dbg_bus (dbg_bus) + ); + `elsif XUPP3R_x4 + phy_ddr4 phy_ddr4_i( + .sys_rst (sys_rst), + .c0_sys_clk_p (c0_sys_clk_p), + .c0_sys_clk_n (c0_sys_clk_n), + + `ifdef ENABLE_DLL_TOGGLER + .c0_ddr4_ui_clk (ddr4_ui_clk), + .addn_ui_clkout1 (c0_ddr4_dll_off_clk), + `else + .c0_ddr4_ui_clk (c0_ddr4_clk), + `endif + .c0_ddr4_ui_clk_sync_rst (c0_ddr4_rst), + .c0_init_calib_complete (c0_init_calib_complete), + .dbg_clk (dbg_clk), + .c0_ddr4_act_n (c0_ddr4_act_n), + .c0_ddr4_adr (c0_ddr4_adr), + .c0_ddr4_ba (c0_ddr4_ba), + .c0_ddr4_bg (c0_ddr4_bg), + .c0_ddr4_cke (c0_ddr4_cke), + .c0_ddr4_odt (c0_ddr4_odt), + .c0_ddr4_cs_n (c0_ddr4_cs_n), + .c0_ddr4_ck_t (c0_ddr4_ck_t), + .c0_ddr4_ck_c (c0_ddr4_ck_c), + .c0_ddr4_reset_n (c0_ddr4_reset_n), + .c0_ddr4_parity (c0_ddr4_parity), + .c0_ddr4_dq (c0_ddr4_dq), + .c0_ddr4_dqs_c (c0_ddr4_dqs_c), + .c0_ddr4_dqs_t (c0_ddr4_dqs_t), + + .dBufAdr (dBufAdr), + .wrData (wrData), + .rdData (rdData), + .rdDataAddr (rdDataAddr), + .rdDataEn (rdDataEn), + .rdDataEnd (rdDataEnd), + .per_rd_done (per_rd_done), + .rmw_rd_done (rmw_rd_done), + .wrDataAddr (wrDataAddr), + .wrDataEn (wrDataEn), + + .mc_ACT_n (dllt_active ? dllt_mc_ACT_n : mc_ACT_n), + .mc_ADR (dllt_active ? dllt_mc_ADR : mc_ADR), + .mc_BA (dllt_active ? dllt_mc_BA : mc_BA), + .mc_BG (dllt_active ? dllt_mc_BG : mc_BG), + .mc_CKE (dllt_active ? dllt_mc_CKE : {8{1'b1}}), + .mc_CS_n (dllt_active ? dllt_mc_CS_n : mc_CS_n), + .mc_ODT (mc_ODT), + // CAS command slot select. Slot0 is enabled for example design. + .mcCasSlot (dllt_active ? 0 : mcCasSlot), + // CAS slot 2 select. mcCasSlot2 serves a similar purpose as the mcCasSlot[1:0] signal, but mcCasSlot2 is used in timing + // critical logic in the Phy. Slot0 is enabled for example design. + .mcCasSlot2 (dllt_active ? 0 : mcCasSlot2), + .mcRdCAS (dllt_active ? 0 : mcRdCAS), + .mcWrCAS (dllt_active ? 0 : mcWrCAS), + // Optional read command type indication. The winInjTxn signal is set to '0' for example design. + .winInjTxn ({1{1'b0}}), + // Optional read command type indication. The winRmw signal is set to '0' for example design. + .winRmw ({1{1'b0}}), + // Update VT Tracking. The gt_data_ready signal is set to '0' in this example design. + // This signal must be asserted periodically to keep the DQS Gate aligned as voltage and temperature drift. + // For more information, Refer to PG150 document. + .gt_data_ready (gt_data_ready), + .winBuf (winBuf), + .winRank (winRank), + .tCWL (tCWL), + // Debug Port + .dbg_bus (dbg_bus) + ); + `elsif XUPP3R_x8_1R_UDIMM + phy_ddr4_udimm phy_ddr4_i( + .sys_rst (sys_rst), + .c0_sys_clk_p (c0_sys_clk_p), + .c0_sys_clk_n (c0_sys_clk_n), + `ifdef ENABLE_DLL_TOGGLER + .c0_ddr4_ui_clk (ddr4_ui_clk), + .addn_ui_clkout1 (c0_ddr4_dll_off_clk), + `else + .c0_ddr4_ui_clk (c0_ddr4_clk), + `endif + .c0_ddr4_ui_clk_sync_rst (c0_ddr4_rst), + .c0_init_calib_complete (c0_init_calib_complete), + .dbg_clk (dbg_clk), + .c0_ddr4_act_n (c0_ddr4_act_n), + .c0_ddr4_adr (c0_ddr4_adr), + .c0_ddr4_ba (c0_ddr4_ba), + .c0_ddr4_bg (c0_ddr4_bg), + .c0_ddr4_cke (c0_ddr4_cke), + .c0_ddr4_odt (c0_ddr4_odt), + .c0_ddr4_cs_n (c0_ddr4_cs_n), + .c0_ddr4_ck_t (c0_ddr4_ck_t), + .c0_ddr4_ck_c (c0_ddr4_ck_c), + .c0_ddr4_reset_n (c0_ddr4_reset_n), + .wrDataMask (wrDataMask), + .c0_ddr4_dm_dbi_n (c0_ddr4_dm_dbi_n), + .c0_ddr4_dq (c0_ddr4_dq), + .c0_ddr4_dqs_c (c0_ddr4_dqs_c), + .c0_ddr4_dqs_t (c0_ddr4_dqs_t), + + .dBufAdr (dBufAdr), + .wrData (wrData), + .rdData (rdData), + .rdDataAddr (rdDataAddr), + .rdDataEn (rdDataEn), + .rdDataEnd (rdDataEnd), + .per_rd_done (per_rd_done), + .rmw_rd_done (rmw_rd_done), + .wrDataAddr (wrDataAddr), + .wrDataEn (wrDataEn), + + .mc_ACT_n (dllt_active ? dllt_mc_ACT_n : mc_ACT_n), + .mc_ADR (dllt_active ? dllt_mc_ADR : mc_ADR), + .mc_BA (dllt_active ? dllt_mc_BA : mc_BA), + .mc_BG (dllt_active ? dllt_mc_BG : mc_BG), + .mc_CKE (dllt_active ? dllt_mc_CKE : {8{1'b1}}), + .mc_CS_n (dllt_active ? dllt_mc_CS_n : mc_CS_n), + .mc_ODT (mc_ODT), + // CAS command slot select. Slot0 is enabled for example design. + .mcCasSlot (dllt_active ? 2'b0 : mcCasSlot), + // CAS slot 2 select. mcCasSlot2 serves a similar purpose as the mcCasSlot[1:0] signal, but mcCasSlot2 is used in timing + // critical logic in the Phy. Slot0 is enabled for example design. + .mcCasSlot2 (dllt_active ? 1'b0 : mcCasSlot2), + .mcRdCAS (dllt_active ? 1'b0 : mcRdCAS), + .mcWrCAS (dllt_active ? 1'b0 : mcWrCAS), + // Optional read command type indication. The winInjTxn signal is set to '0' for example design. + .winInjTxn ({1{1'b0}}), + // Optional read command type indication. The winRmw signal is set to '0' for example design. + .winRmw ({1{1'b0}}), + // Update VT Tracking. The gt_data_ready signal is set to '0' in this example design. + // This signal must be asserted periodically to keep the DQS Gate aligned as voltage and temperature drift. + // For more information, Refer to PG150 document. + .gt_data_ready (gt_data_ready), + .winBuf (winBuf), + .winRank (winRank), + .tCWL (tCWL), + // Debug Port + .dbg_bus (dbg_bus) + ); + `else + phy_ddr4 phy_ddr4_i( + .sys_rst (sys_rst), + .c0_sys_clk_p (c0_sys_clk_p), + .c0_sys_clk_n (c0_sys_clk_n), + + `ifdef ENABLE_DLL_TOGGLER + .c0_ddr4_ui_clk (ddr4_ui_clk), + .addn_ui_clkout1 (c0_ddr4_dll_off_clk), + `else + .c0_ddr4_ui_clk (c0_ddr4_clk), + `endif + .c0_ddr4_ui_clk_sync_rst (c0_ddr4_rst), + .c0_init_calib_complete (c0_init_calib_complete), + .dbg_clk (dbg_clk), + .c0_ddr4_act_n (c0_ddr4_act_n), + .c0_ddr4_adr (c0_ddr4_adr), + .c0_ddr4_ba (c0_ddr4_ba), + .c0_ddr4_bg (c0_ddr4_bg), + .c0_ddr4_cke (c0_ddr4_cke), + .c0_ddr4_odt (c0_ddr4_odt), + .c0_ddr4_cs_n (c0_ddr4_cs_n), + .c0_ddr4_ck_t (c0_ddr4_ck_t), + .c0_ddr4_ck_c (c0_ddr4_ck_c), + .c0_ddr4_reset_n (c0_ddr4_reset_n), + .wrDataMask (wrDataMask), + .c0_ddr4_dm_dbi_n (c0_ddr4_dm_dbi_n), + .c0_ddr4_dq (c0_ddr4_dq), + .c0_ddr4_dqs_c (c0_ddr4_dqs_c), + .c0_ddr4_dqs_t (c0_ddr4_dqs_t), + + .dBufAdr (dBufAdr), + .wrData (wrData), + .rdData (rdData), + .rdDataAddr (rdDataAddr), + .rdDataEn (rdDataEn), + .rdDataEnd (rdDataEnd), + .per_rd_done (per_rd_done), + .rmw_rd_done (rmw_rd_done), + .wrDataAddr (wrDataAddr), + .wrDataEn (wrDataEn), + + .mc_ACT_n (dllt_active ? dllt_mc_ACT_n : mc_ACT_n), + .mc_ADR (dllt_active ? dllt_mc_ADR : mc_ADR), + .mc_BA (dllt_active ? dllt_mc_BA : mc_BA), + .mc_BG (dllt_active ? dllt_mc_BG : mc_BG), + .mc_CKE (dllt_active ? dllt_mc_CKE : {8{1'b1}}), + .mc_CS_n (dllt_active ? dllt_mc_CS_n : mc_CS_n), + .mc_ODT (mc_ODT), + // CAS command slot select. Slot0 is enabled for example design. + .mcCasSlot (dllt_active ? 0 : mcCasSlot), + // CAS slot 2 select. mcCasSlot2 serves a similar purpose as the mcCasSlot[1:0] signal, but mcCasSlot2 is used in timing + // critical logic in the Phy. Slot0 is enabled for example design. + .mcCasSlot2 (dllt_active ? 0 : mcCasSlot2), + .mcRdCAS (dllt_active ? 0 : mcRdCAS), + .mcWrCAS (dllt_active ? 0 : mcWrCAS), + // Optional read command type indication. The winInjTxn signal is set to '0' for example design. + .winInjTxn ({1{1'b0}}), + // Optional read command type indication. The winRmw signal is set to '0' for example design. + .winRmw ({1{1'b0}}), + // Update VT Tracking. The gt_data_ready signal is set to '0' in this example design. + // This signal must be asserted periodically to keep the DQS Gate aligned as voltage and temperature drift. + // For more information, Refer to PG150 document. + .gt_data_ready (gt_data_ready), + .winBuf (winBuf), + .winRank (winRank), + .tCWL (tCWL), + // Debug Port + .dbg_bus (dbg_bus) + ); + `endif + + softmc_pipeline pipeline( + .clk(c0_ddr4_clk), + .rst(c0_ddr4_rst || user_rst), + + .softmc_end(softmc_fin), + .read_size(incoming_reads), + .read_seq_incoming(read_seq_incoming), + .buffer_space(buffer_space), + + .addr_out(fr_addr_in), + .valid_out(fr_valid_in), + .data_in(fr_data_out), + .valid_in(fr_valid_out), + .addr_in(fr_addr_out), + .ready_out(fr_ready_out), + + .ddr_write(ddr_write), + .ddr_read(ddr_read), + .ddr_pre(ddr_pre), + .ddr_act(ddr_act), + .ddr_ref(ddr_ref), + .ddr_sre(ddr_sre), + .ddr_srx(ddr_srx), + .ddr_zq(ddr_zq), + .ddr_nop(ddr_nop), + .ddr_ap(ddr_ap), + .ddr_pall(ddr_pall), + .ddr_half_bl(ddr_half_bl), + .ddr_bg(ddr_bg), + .ddr_bank(ddr_bank), + .ddr_col(ddr_col), + .ddr_row(ddr_row), + .ddr_wdata(ddr_wdata) + ); + + `ifdef ENABLE_DLL_TOGGLER + //BUFGMUX:GeneralClockMuxBuffer + //UltraScale + //XilinxHDLLibrariesGuide, version2014.4 + BUFGMUX#(.CLK_SEL_TYPE("SYNC") //ASYNC,SYNC + )BUFGMUX_inst( + .O(c0_ddr4_clk), //1-bitoutput:Clockoutput + .I0(ddr4_ui_clk), //1-bitinput:Clockinput(S=0) + .I1(c0_ddr4_dll_off_clk), //1-bitinput:Clockinput(S=1) + .S(clk_sel) //1-bitinput:Clockselect + ); + //End of BUFGMUX_inst instantiation + `endif + + + wire frontend_ready; + + frontend #(.SIM_MEM(SIM)) frontend( + .clk(c0_ddr4_clk), + .rst(c0_ddr4_rst), + + .init_calib_complete(c0_init_calib_complete_r), + .softmc_fin(softmc_fin), + .user_rst(user_rst), + + .dllt_begin(toggle_dll), + + // indicates read_back unit is ready for the next iseq + .frontend_ready(frontend_ready), + + // frontend <-> fetch stage if + .addr_in(fr_addr_in), + .valid_in(fr_valid_in), + .data_out(fr_data_out), + .valid_out(fr_valid_out), + .addr_out(fr_addr_out), + .ready_in(fr_ready_out), + + // frontend <-> xdma interface + .h2c_tdata_0(m_axis_h2c_tdata_0), + .h2c_tlast_0(m_axis_h2c_tlast_0), + .h2c_tvalid_0(m_axis_h2c_tvalid_0), + .h2c_tready_0(m_axis_h2c_tready_0), + .h2c_tkeep_0(m_axis_h2c_tkeep_0), + + .per_rd_init(per_rd_init), + .per_zq_init(per_zq_init), + .per_ref_init(per_ref_init), + .rbe_switch_mode(rbe_switch_mode) + ); + + ddr4_adapter#( + `ifdef XUPP3R + `ifdef XUPP3R_x8_1R_UDIMM + .DQ_WIDTH(64) + `else + .DQ_WIDTH(72) + `endif + `endif + ) ddr4_adapter + ( + .clk(c0_ddr4_clk), + .rst(c0_ddr4_rst || user_rst), + .init_calib_complete(c0_init_calib_complete_r), + //.io_config_strobe, + //.io_config, + .dBufAdr(dBufAdr), // Reserved. Should be tied low. + .wrData(wrData), // DRAM write data. There are 8 bits for each DQ lane on the DRAM bus. + .wrDataMask(wrDataMask),// DRAM write DM/DBI port.There is one bit for each byte of the wrData port. + .wrDataEn(wrDataEn), // Write data Enable. The Phy will assert this port for one cycle for each write CAS command. + .mc_ACT_n(mc_ACT_n), // DRAM ACT_n command signal for four DRAM clock cycles. + .mc_ADR(mc_ADR), // DRAM address. There are 8 bits in the fabric interface for each address bit on the DRAM bus. + .mc_BA(mc_BA), // DRAM bank address. 8 bits for each DRAM bank address. + .mc_BG(mc_BG), // DRAM bank group address. + .mc_CS_n(mc_CS_n), // DRAM CS_n + //.mc_ODT(mc_ODT), // DRAM ODT + .mcRdCAS(mcRdCAS), // Read CAS command issued. + .mcWrCAS(mcWrCAS), // Write CAS command issued. + .winRank(winRank), // Target rank for CAS commands. This value indicates which rank a CAS command is issued to. + .winBuf(winBuf), // Optional control signal. When either mcRdCAS or mcWrCAS is asserted, the Phy will store the value on the winBuf signal. + //.rdData(rdData), // DRAM read data. + .rdDataEn(rdDataEn), // Read data valid. This signal asserts for one fabric cycle for each completed read operation. + .rdDataEnd(rdDataEnd), // Unused. Tied high. + .mcCasSlot(mcCasSlot), + .mcCasSlot2(mcCasSlot2), + .gt_data_ready(gt_data_ready), + .ddr_write(ddr_write), + .ddr_read(ddr_read), + .ddr_pre(ddr_pre), + .ddr_act(ddr_act), + .ddr_ref(ddr_ref), + .ddr_zq(ddr_zq), + .ddr_nop(ddr_nop), + .ddr_ap(ddr_ap), + .ddr_pall(ddr_pall), + .ddr_half_bl(ddr_half_bl), + .ddr_bg(ddr_bg), + .ddr_bank(ddr_bank), + .ddr_col(ddr_col), + .ddr_row(ddr_row), + .ddr_wdata(ddr_wdata), + + .ddr_maint_read(per_rd_init) + ); + `ifdef XUPP3R_x8 + localparam ODTWRDEL = 5'd9; + localparam ODTWRDUR = 4'd6; + localparam ODTWRODEL = 5'd9; + localparam ODTWRODUR = 4'd6; + localparam ODTRDDEL = 5'd10; + localparam ODTRDDUR = 4'd6; + localparam ODTRDODEL = 5'd9; + localparam ODTRDODUR = 4'd6; + localparam ODTNOP = 16'h0000; + localparam ODTWR = 16'h0021; + localparam ODTRD = 16'h0012; + `elsif XUPP3R_x8_1R_UDIMM + localparam ODTWRDEL = 5'd9; + localparam ODTWRDUR = 4'd6; + localparam ODTWRODEL = 5'd9; + localparam ODTWRODUR = 4'd6; + localparam ODTRDDEL = 5'd9; + localparam ODTRDDUR = 4'd6; + localparam ODTRDODEL = 5'd9; + localparam ODTRDODUR = 4'd6; + localparam ODTNOP = 16'h0000; + localparam ODTWR = 16'h0001; + localparam ODTRD = 16'h0000; + `else + localparam ODTWRDEL = 5'd11; + localparam ODTWRDUR = 4'd6; + localparam ODTWRODEL = 5'd9; + localparam ODTWRODUR = 4'd6; + localparam ODTRDDEL = 5'd11; + localparam ODTRDDUR = 4'd6; + localparam ODTRDODEL = 5'd9; + localparam ODTRDODUR = 4'd6; + localparam ODTNOP = 16'h0000; + localparam ODTWR = 16'h0001; + localparam ODTRD = 16'h0000; + `endif + + wire tranSentC; + assign tranSentC = mcRdCAS | mcWrCAS; + + //synthesis translate_on + //******************************************************************************* + ddr4_mc_odt # ( + .ODTWR (ODTWR) + ,.ODTWRDEL (ODTWRDEL) + ,.ODTWRDUR (ODTWRDUR) + ,.ODTWRODEL (ODTWRODEL) + ,.ODTWRODUR (ODTWRODUR) + + ,.ODTRD (ODTRD) + ,.ODTRDDEL (ODTRDDEL) + ,.ODTRDDUR (ODTRDDUR) + ,.ODTRDODEL (ODTRDODEL) + ,.ODTRDODUR (ODTRDODUR) + + ,.ODTNOP (ODTNOP) + ,.ODTBITS (`ODT_WIDTH) + ,.TCQ (0.1) + )u_ddr_tb_odt( + .clk (c0_ddr4_clk) + ,.rst (c0_ddr4_rst) + ,.mc_ODT (mc_ODT) + ,.casSlot (mcCasSlot) + ,.casSlot2 (mcCasSlot2) + ,.rank (winRank) + ,.winRead (mcRdCAS) + ,.winWrite (mcWrCAS) + ,.tranSentC (tranSentC) + ); + + wire sys_clk, sys_clk_gt; + wire [2:0] msi_vector_width; + wire msi_enable; + wire user_lnk_up, usr_irq_req, usr_irq_ack; + `ifdef XUPP3R + IBUFDS_GTE4 refclk_ibuf (.O(sys_clk_gt), .ODIV2(sys_clk), .I(clk_ref_p), .CEB(1'b0), .IB(clk_ref_n)); + `else + IBUFDS_GTE3 # (.REFCLK_HROW_CK_SEL(2'b01)) refclk_ibuf (.O(sys_clk_gt), .ODIV2(sys_clk), .I(clk_ref_p), .CEB(1'b0), .IB(clk_ref_n)); + `endif + wire axi_clk, axi_rst; + + xdma xdma_i + ( + //---------------------------------------------------------------------------------------// + // PCI Express (pci_exp) Interface // + //---------------------------------------------------------------------------------------// + .sys_rst_n ( pcie_rst ), + .sys_clk ( sys_clk ), + .sys_clk_gt ( sys_clk_gt), + + // Tx + .pci_exp_txn ( pci_exp_txn ), + .pci_exp_txp ( pci_exp_txp ), + + // Rx + .pci_exp_rxn ( pci_exp_rxn ), + .pci_exp_rxp ( pci_exp_rxp ), + + // AXI streaming ports + .s_axis_c2h_tdata_0(xdma_c2h_tdata_0), + .s_axis_c2h_tlast_0(xdma_c2h_tlast_0), + .s_axis_c2h_tvalid_0(xdma_c2h_tvalid_0), + .s_axis_c2h_tready_0(xdma_c2h_tready_0), + .s_axis_c2h_tkeep_0(xdma_c2h_tkeep_0), + .m_axis_h2c_tdata_0(xdma_h2c_tdata_0), + .m_axis_h2c_tlast_0(xdma_h2c_tlast_0), + .m_axis_h2c_tvalid_0(xdma_h2c_tvalid_0), + .m_axis_h2c_tready_0(xdma_h2c_tready_0), + .m_axis_h2c_tkeep_0(xdma_h2c_tkeep_0), + + .usr_irq_req (1'b0), + .usr_irq_ack (usr_irq_ack), + .msi_enable (msi_enable), + .msi_vector_width (msi_vector_width), + + + // Config managemnet interface + .cfg_mgmt_addr ( 19'b0 ), + .cfg_mgmt_write ( 1'b0 ), + .cfg_mgmt_write_data ( 32'b0 ), + .cfg_mgmt_byte_enable ( 4'b0 ), + .cfg_mgmt_read ( 1'b0 ), + .cfg_mgmt_read_data (), + .cfg_mgmt_read_write_done (), + `ifndef XUPP3R + .cfg_mgmt_type1_cfg_reg_access ( 1'b0 ), + //---------- Shared Logic Internal ------------------------- + .int_qpll1lock_out ( ), + .int_qpll1outrefclk_out ( ), + .int_qpll1outclk_out ( ), + `endif + + //-- AXI Global + .axi_aclk (axi_clk), // AXI i-face clock driven from pcie clk + .axi_aresetn (axi_rst), // reset synchronous to axi_clk + + .user_lnk_up ( user_lnk_up ) + ); + + // Clock converter for the c2h interface + axis_clock_converter axis_clk_conv_i0 + ( + .s_axis_tvalid(s_axis_c2h_tvalid_0), + .s_axis_tlast(s_axis_c2h_tlast_0), + .s_axis_tdata(s_axis_c2h_tdata_0), + .s_axis_tkeep(s_axis_c2h_tkeep_0), + .s_axis_tready(s_axis_c2h_tready_0), + .m_axis_tvalid(xdma_c2h_tvalid_0), + .m_axis_tlast(xdma_c2h_tlast_0), + .m_axis_tdata(xdma_c2h_tdata_0), + .m_axis_tkeep(xdma_c2h_tkeep_0), + .m_axis_tready(xdma_c2h_tready_0), + .s_axis_aresetn(~c0_ddr4_rst), + .s_axis_aclk(c0_ddr4_clk), + .m_axis_aresetn(axi_rst), + .m_axis_aclk(axi_clk) + ); + + // Clock converter for the h2c interface + axis_clock_converter axis_clk_conv_i1 + ( + .m_axis_tvalid(m_axis_h2c_tvalid_0), + .m_axis_tlast(m_axis_h2c_tlast_0), + .m_axis_tdata(m_axis_h2c_tdata_0), + .m_axis_tkeep(m_axis_h2c_tkeep_0), + .m_axis_tready(m_axis_h2c_tready_0), + .s_axis_tvalid(xdma_h2c_tvalid_0), + .s_axis_tlast(xdma_h2c_tlast_0), + .s_axis_tdata(xdma_h2c_tdata_0), + .s_axis_tkeep(xdma_h2c_tkeep_0), + .s_axis_tready(xdma_h2c_tready_0), + .m_axis_aresetn(~c0_ddr4_rst), + .m_axis_aclk(c0_ddr4_clk), + .s_axis_aresetn(axi_rst), + .s_axis_aclk(axi_clk) + ); + + readback_engine rbe( + + // common signals + .clk(c0_ddr4_clk), + .rst(c0_ddr4_rst || user_rst), + + // other ctrl signals + .flush(frontend_ready), + .switch_mode(rbe_switch_mode), + .read_seq_incoming(read_seq_incoming), // next few instructions will read from DRAM + .incoming_reads(incoming_reads), // how many reads next few instructions will issue + .buffer_space(buffer_space), // remaining buffer size + // DRAM <-> engine if + .rd_data(rdData), + .rd_valid(rdDataEn), + + // rbe <-> rf interface + .ddr_wdata(ddr_wdata), + + .per_rd_init(per_rd_init), + .per_zq_init(per_zq_init), + .per_ref_init(per_ref_init), + + // rbe <-> xdma if + .c2h_tdata_0(s_axis_c2h_tdata_0), + .c2h_tlast_0(s_axis_c2h_tlast_0), + .c2h_tvalid_0(s_axis_c2h_tvalid_0), + .c2h_tready_0(s_axis_c2h_tready_0), + .c2h_tkeep_0(s_axis_c2h_tkeep_0) + + ); + + `ifdef ENABLE_DLL_TOGGLER + dll_toggler dllt + ( + .clk(c0_ddr4_clk), + .rst(c0_ddr4_rst || user_rst || ~c0_init_calib_complete_r), + .toggle_valid(toggle_dll), + .mc_ACT_n(dllt_mc_ACT_n), // DRAM ACT_n command signal for four DRAM clock cycles. + .mc_ADR(dllt_mc_ADR), // DRAM address. There are 8 bits in the fabric interface for each address bit on the DRAM bus. + .mc_BA(dllt_mc_BA), // DRAM bank address. 8 bits for each DRAM bank address. + .mc_BG(dllt_mc_BG), // DRAM bank group address. + .mc_CS_n(dllt_mc_CS_n), // DRAM CS_n + .mc_CKE(dllt_mc_CKE), + .clk_sel(clk_sel), + .dllt_done(dllt_done) + ); + `endif +endmodule -- cgit v1.2.3