From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001
From: Ataberk <olgunataberk@gmail.com>
Date: Sun, 25 Sep 2022 17:22:03 +0200
Subject: Initial commit

---
 sources/hdl/sim_verilog/tb_softmc_top.v | 42 +++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 sources/hdl/sim_verilog/tb_softmc_top.v

(limited to 'sources/hdl/sim_verilog/tb_softmc_top.v')

diff --git a/sources/hdl/sim_verilog/tb_softmc_top.v b/sources/hdl/sim_verilog/tb_softmc_top.v
new file mode 100644
index 0000000..6a61f44
--- /dev/null
+++ b/sources/hdl/sim_verilog/tb_softmc_top.v
@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/06/2018 05:43:09 PM
+// Design Name: 
+// Module Name: tb_softmc_top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_only_softmc(
+
+  );
+  
+  reg clk = 0, rst = 1;
+  softmc_top smct(
+    .clk(clk),
+    .rst(rst)
+  );
+  
+  initial begin
+    #50;
+    rst = 0;
+  end
+  
+  always begin
+    #5;
+    clk = ~clk;
+  end
+endmodule
-- 
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