From 7721980589f4c7fa811689e815a77d63f2556497 Mon Sep 17 00:00:00 2001 From: Ataberk Date: Thu, 2 May 2024 17:22:05 +0200 Subject: Add sources for U50 HBM2 --- sources/hdl/verilog/maintenance_controller.v | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'sources/hdl/verilog/maintenance_controller.v') diff --git a/sources/hdl/verilog/maintenance_controller.v b/sources/hdl/verilog/maintenance_controller.v index 9354d17..169833a 100644 --- a/sources/hdl/verilog/maintenance_controller.v +++ b/sources/hdl/verilog/maintenance_controller.v @@ -172,8 +172,12 @@ module maintenance_controller#(parameter tCK = 1500)( wire periodic_rd_timer_one = maint_prescaler_tick_r_lcl && (periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]); + `ifndef HBM_BENDER wire periodic_rd_request = ~rst && (/*((PERIODIC_RD_TIMER_DIV != 0) && ~dfi_init_complete) ||*/ (~per_rd_ack && (per_rd_request || periodic_rd_timer_one))); + `else + wire periodic_rd_request = 1'b0; + `endif always @(posedge clk) begin if(~init_calib_complete) @@ -221,8 +225,12 @@ module maintenance_controller#(parameter tCK = 1500)( always @(posedge clk) zq_request_r <= zq_request_ns; - always @(/*AS*/init_calib_complete or zq_request_r) - zq_request = init_calib_complete && zq_request_r; + always @(/*AS*/init_calib_complete or zq_request_r) + `ifndef HBM_BENDER + zq_request = init_calib_complete && zq_request_r; + `else + zq_request = 1'b0; + `endif end // zq_request_logic end endgenerate -- cgit v1.2.3