From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001 From: Ataberk Date: Sun, 25 Sep 2022 17:22:03 +0200 Subject: Initial commit --- sources/hdl/verilog/reg_mem.v | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 sources/hdl/verilog/reg_mem.v (limited to 'sources/hdl/verilog/reg_mem.v') diff --git a/sources/hdl/verilog/reg_mem.v b/sources/hdl/verilog/reg_mem.v new file mode 100644 index 0000000..a8d37cd --- /dev/null +++ b/sources/hdl/verilog/reg_mem.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps + +module reg_mem( + input [9:0] addr, + input clk, + input [31:0] din, + output [31:0] dout, + input en, + input we + ); + + reg [31:0] mem [1023:0]; + + integer i; + initial + begin + for(i=0; i<1024; i=i+1) + mem[i]=0; + end + + reg [31:0] out; + + assign dout=out; + + always @(posedge clk) + begin + if(we) + mem[addr]<=din; + else if(en) + out<=mem[addr]; + end + +endmodule -- cgit v1.2.3