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Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:ddr4:2.2 // IP Revision: 10 // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections // (in parentheses) to your own signal names. //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG phy_ddr4 your_instance_name ( .c0_init_calib_complete(c0_init_calib_complete), // output wire c0_init_calib_complete .dbg_clk(dbg_clk), // output wire dbg_clk .c0_sys_clk_p(c0_sys_clk_p), // input wire c0_sys_clk_p .c0_sys_clk_n(c0_sys_clk_n), // input wire c0_sys_clk_n .dbg_bus(dbg_bus), // output wire [511 : 0] dbg_bus .c0_ddr4_parity(c0_ddr4_parity), // output wire c0_ddr4_parity .c0_ddr4_ui_clk(c0_ddr4_ui_clk), // output wire c0_ddr4_ui_clk .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst), // output wire c0_ddr4_ui_clk_sync_rst .addn_ui_clkout1(addn_ui_clkout1), // output wire addn_ui_clkout1 .sys_rst(sys_rst), // input wire sys_rst .rdDataEn(rdDataEn), // output wire [0 : 0] rdDataEn .rdDataEnd(rdDataEnd), // output wire [0 : 0] rdDataEnd .per_rd_done(per_rd_done), // output wire [0 : 0] per_rd_done .rmw_rd_done(rmw_rd_done), // output wire [0 : 0] rmw_rd_done .wrDataEn(wrDataEn), // output wire [0 : 0] wrDataEn .mc_ACT_n(mc_ACT_n), // input wire [7 : 0] mc_ACT_n .mcCasSlot(mcCasSlot), // input wire [1 : 0] mcCasSlot .mcCasSlot2(mcCasSlot2), // input wire [0 : 0] mcCasSlot2 .mcRdCAS(mcRdCAS), // input wire [0 : 0] mcRdCAS .mcWrCAS(mcWrCAS), // input wire [0 : 0] mcWrCAS .winInjTxn(winInjTxn), // input wire [0 : 0] winInjTxn .winRmw(winRmw), // input wire [0 : 0] winRmw .gt_data_ready(gt_data_ready), // input wire gt_data_ready .winRank(winRank), // input wire [1 : 0] winRank .tCWL(tCWL), // output wire [5 : 0] tCWL .wrData(wrData), // input wire [575 : 0] wrData .rdData(rdData), // output wire [575 : 0] rdData .mc_ADR(mc_ADR), // input wire [143 : 0] mc_ADR .mc_BA(mc_BA), // input wire [15 : 0] mc_BA .mc_CKE(mc_CKE), // input wire [7 : 0] mc_CKE .mc_CS_n(mc_CS_n), // input wire [7 : 0] mc_CS_n .mc_ODT(mc_ODT), // input wire [7 : 0] mc_ODT .dBufAdr(dBufAdr), // input wire [4 : 0] dBufAdr .rdDataAddr(rdDataAddr), // output wire [4 : 0] rdDataAddr .wrDataAddr(wrDataAddr), // output wire [4 : 0] wrDataAddr .winBuf(winBuf), // input wire [4 : 0] winBuf .ddr4_act_n(ddr4_act_n), // output wire ddr4_act_n .ddr4_adr(ddr4_adr), // output wire [17 : 0] ddr4_adr .ddr4_ba(ddr4_ba), // output wire [1 : 0] ddr4_ba .ddr4_bg(ddr4_bg), // output wire [1 : 0] ddr4_bg .ddr4_par(ddr4_par), // output wire ddr4_par .ddr4_cke(ddr4_cke), // output wire [0 : 0] ddr4_cke .ddr4_odt(ddr4_odt), // output wire [0 : 0] ddr4_odt .ddr4_cs_n(ddr4_cs_n), // output wire [0 : 0] ddr4_cs_n .ddr4_ck_t(ddr4_ck_t), // output wire ddr4_ck_t .ddr4_ck_c(ddr4_ck_c), // output wire ddr4_ck_c .ddr4_reset_n(ddr4_reset_n), // output wire ddr4_reset_n .ddr4_parity(ddr4_parity), // output wire ddr4_parity .ddr4_dq(ddr4_dq), // inout wire [71 : 0] ddr4_dq .ddr4_dqs_c(ddr4_dqs_c), // inout wire [17 : 0] ddr4_dqs_c .ddr4_dqs_t(ddr4_dqs_t), // inout wire [17 : 0] ddr4_dqs_t .mc_BG(mc_BG) // input wire [15 : 0] mc_BG ); // INST_TAG_END ------ End INSTANTIATION Template --------- // You must compile the wrapper file phy_ddr4.v when simulating // the core, phy_ddr4. When compiling the wrapper file, be sure to // reference the Verilog simulation library.