verilog xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \

sv xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \
"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \

verilog xil_defaultlib "glbl.v"

nosort