xilinx.com xci unknown 1.0 phy_ddr4_udimm 0 0 0 0 0 0 0 0 TDM 8 false 11 11 true true 8 COMPONENTS ROW_COLUMN_BANK Single 1250 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 false 100000000 100000000 0 0 0.000 0 30 512 64 X0Y11 X0Y10 X0Y70 X0Y11 0 0 DDR4_SDRAM 17 0 false 32 64 4 2 2 0 0 0 1 1 0 5 3333 9 0 VCO 10 8Gb 30 1 0 0 8 8 0 938 1 8 8 64 false 0 1.2V false No 1600 0 0 MTA8ATF1G64AZ-2G3 UDIMMs 8 8GB 8 8192 64 8589934592 833 DDR4_833_Timing 0 0 ROW_COLUMN_BANK 1 0 1 16 0 0 083 1 1 166500000 1 1 0.84 0 4 1 5 1500 0 14 16 2 22 10 5200 234 80 10 4 3 4 5 10 5 2 60 128 0 256 DDR4 1 0 0 0 0 0 0 FALSE 3333 0 0 0 0 0 0 NONE Disable 1 0.0 0 0.0 0 0.0 0 0.0 0 1 BFM Differential None None None None 0 17 2 1 1 1 DDR4_SDRAM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 false false 32 RD_PRI_REG 64 4 false false 0 0 0 0 8 Sequential 0 0 0 0 0 0 0 0 5 9 0 0 0 0 512 10 9 true false no_file_loaded 1 DM_NO_DBI 64 false false false 3333 0 0 false ROW_COLUMN_BANK MainMemory MTA8ATF1G64AZ-2G3 UDIMMs 1.2V 0 0 0 0 RZQ/6 Normal RZQ/7 0 4:1 false false false Single false 0 0 0 0 1500 false false false 0 0 0 5 1 false 1 1 Custom Custom false phy_ddr4_udimm false false Disable false false true SIMPLE_TG OFF false 1 false 1 false 1 Phy_Only_Single false Custom Differential false BFM Differential false false false virtexuplus xilinx.com:au200:part0:1.3 xcu200 fsgd2104 VERILOG MIXED -2 E TRUE TRUE IP_Flow 10 TRUE . . 2020.2 OUT_OF_CONTEXT