xilinx.com xci unknown 1.0 cdc_fifo 100000000 0 0 0.000 100000000 0 0 0.000 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 150000000 0 0 0.000 100000000 0 0 0.000 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 300000000 0 0 0.000 0 0 0 0 0 0 0 8 1 1 1 1 4 0 32 1 1 1 64 1 8 1 1 1 1 0 0 11 BlankString 512 1 32 64 1 64 2 0 512 0 1 0 0 0 0 0 0 0 0 virtexuplusHBM 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 6 1 1 1 1 1 1 0 0 4 BlankString 1 0 0 0 2 1 512x72 1kx18 512x36 512x72 512x36 512x72 512x36 5 1022 1022 1022 1022 1022 1022 6 0 0 0 0 0 0 0 2044 1023 1023 1023 1023 1023 1023 2043 0 0 0 0 0 0 0 0 0 11 2048 150 11 0 0 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 11 2048 1024 16 1024 16 1024 16 300 11 10 4 10 4 10 4 1 32 0 0 false false false 0 0 Slave_Interface_Clock_Enable Common_Clock cdc_fifo 64 false 11 false false 0 5 1022 1022 1022 1022 1022 1022 6 false false false false false false false false false Hard_ECC false false false false false false true false false true Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Independent_Clocks_Builtin_FIFO 0 2044 1023 1023 1023 1023 1023 1023 2043 false false false 0 Native false false false false false false false false false false false false false false 512 2048 1024 16 1024 16 1024 16 false 512 2048 Embedded_Reg false false Active_High Active_High AXI4 Standard_FIFO No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold READ_WRITE 0 150 false 11 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered true Synchronous_Reset false 1 0 0 1 1 4 false false Active_High Active_High true true false false true Active_High 0 false Active_High 300 false 11 false FIFO false false false false FIFO FIFO 2 2 false FIFO FIFO FIFO virtexuplusHBM xilinx.com:au50:part0:1.3 xcu50 fsvh2104 VERILOG MIXED -2 E TRUE TRUE IP_Flow 5 TRUE . . 2020.2 OUT_OF_CONTEXT