xilinx.com customized_ip clk_wiz_0 1.0 s_axi_lite S_AXI_LITE ARADDR s_axi_araddr ARREADY s_axi_arready ARVALID s_axi_arvalid AWADDR s_axi_awaddr AWREADY s_axi_awready AWVALID s_axi_awvalid BREADY s_axi_bready BRESP s_axi_bresp BVALID s_axi_bvalid RDATA s_axi_rdata RREADY s_axi_rready RRESP s_axi_rresp RVALID s_axi_rvalid WDATA s_axi_wdata WREADY s_axi_wready WSTRB s_axi_wstrb WVALID s_axi_wvalid DATA_WIDTH 1 none PROTOCOL AXI4LITE none FREQ_HZ 100000000 none ID_WIDTH 0 none ADDR_WIDTH 1 none AWUSER_WIDTH 0 none ARUSER_WIDTH 0 none WUSER_WIDTH 0 none RUSER_WIDTH 0 none BUSER_WIDTH 0 none READ_WRITE_MODE READ_WRITE none HAS_BURST 0 none HAS_LOCK 0 none HAS_PROT 0 none HAS_CACHE 0 none HAS_QOS 0 none HAS_REGION 0 none HAS_WSTRB 0 none HAS_BRESP 0 none HAS_RRESP 0 none SUPPORTS_NARROW_BURST 0 none NUM_READ_OUTSTANDING 1 none NUM_WRITE_OUTSTANDING 1 none MAX_BURST_LENGTH 1 none PHASE 0.000 none CLK_DOMAIN none NUM_READ_THREADS 1 none NUM_WRITE_THREADS 1 none RUSER_BITS_PER_BYTE 0 none WUSER_BITS_PER_BYTE 0 none INSERT_VIP 0 simulation.rtl false s_axi_aclk s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi_lite ASSOCIATED_RESET s_axi_aresetn FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none INSERT_VIP 0 simulation.rtl false ref_clk ref_clk CLK ref_clk FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false s_axi_resetn S_AXI_RESETN RST s_axi_aresetn ASSOCIATED_RESET aresetn POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false intr Intr INTERRUPT interrupt SENSITIVITY LEVEL_HIGH none PortWidth 1 none false CLK_IN1_D CLK_IN1_D Differential Clock input CLK_N clk_in1_n CLK_P clk_in1_p BOARD.ASSOCIATED_PARAM CLK_IN1_BOARD_INTERFACE required CAN_DEBUG false none FREQ_HZ 100000000 none false CLK_IN2_D CLK_IN2_D Differential Clock input CLK_N clk_in2_n CLK_P clk_in2_p BOARD.ASSOCIATED_PARAM CLK_IN2_BOARD_INTERFACE required CAN_DEBUG false none FREQ_HZ 100000000 none false CLKFB_IN_D CLKFB_IN_D Differential Feedback Clock input CLK_N clkfb_in_n CLK_P clkfb_in_p CAN_DEBUG false none FREQ_HZ 100000000 none false CLKFB_OUT_D CLKFB_OUT_D Differential Feeback Clock Output CLK_N clkfb_out_n CLK_P clkfb_out_p CAN_DEBUG false none FREQ_HZ 100000000 none false reset reset RST reset POLARITY ACTIVE_HIGH BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE INSERT_VIP 0 simulation.rtl false resetn resetn RST resetn POLARITY ACTIVE_LOW BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE INSERT_VIP 0 simulation.rtl false clock_CLK_IN1 CLK_IN1 clk_in1 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl BOARD.ASSOCIATED_PARAM CLK_IN1_BOARD_INTERFACE clock_CLK_OUT1 CLK_OUT1 clk_150MHz FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl clock_CLK_OUT2 CLK_OUT2 clk_300MHz FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl xilinx_elaborateports Elaborate Ports :vivado.xilinx.com:elaborate.ports outputProductCRC 9:eb715ca2 s_axi_aclk in std_logic xilinx_elaborateports 0 false s_axi_aresetn in std_logic xilinx_elaborateports 0 false s_axi_awaddr in 10 0 std_logic_vector xilinx_elaborateports 0 false s_axi_awvalid in std_logic xilinx_elaborateports 0 false s_axi_awready out std_logic xilinx_elaborateports false s_axi_wdata in 31 0 std_logic_vector xilinx_elaborateports 0 false s_axi_wstrb in 3 0 std_logic_vector xilinx_elaborateports 0 false s_axi_wvalid in std_logic xilinx_elaborateports 0 false s_axi_wready out std_logic xilinx_elaborateports false s_axi_bresp out 1 0 std_logic_vector xilinx_elaborateports false s_axi_bvalid out std_logic xilinx_elaborateports false s_axi_bready in std_logic xilinx_elaborateports 0 false s_axi_araddr in 10 0 std_logic_vector xilinx_elaborateports 0 false s_axi_arvalid in std_logic xilinx_elaborateports 0 false s_axi_arready out std_logic xilinx_elaborateports false s_axi_rdata out 31 0 std_logic_vector xilinx_elaborateports false s_axi_rresp out 1 0 std_logic_vector xilinx_elaborateports false s_axi_rvalid out std_logic xilinx_elaborateports false s_axi_rready in std_logic xilinx_elaborateports 0 false clk_in1_p in std_logic xilinx_elaborateports 0 false clk_in1_n in std_logic xilinx_elaborateports 0 false clk_in2_p in std_logic xilinx_elaborateports 0 false clk_in2_n in std_logic xilinx_elaborateports 0 false clkfb_in_p in std_logic xilinx_elaborateports 0 false clkfb_in_n in std_logic xilinx_elaborateports 0 false clkfb_out_p out std_logic xilinx_elaborateports false clkfb_out_n out std_logic xilinx_elaborateports false reset in std_logic xilinx_elaborateports 0 false resetn in std_logic xilinx_elaborateports 0 false ref_clk in std_logic xilinx_elaborateports 0 false clk_stop out 3 0 std_logic_vector xilinx_elaborateports 0 false clk_glitch out 3 0 std_logic_vector xilinx_elaborateports 0 false interrupt out std_logic xilinx_elaborateports 0 false clk_oor out 3 0 std_logic_vector xilinx_elaborateports 0 false user_clk0 in std_logic xilinx_elaborateports 0 false user_clk1 in std_logic xilinx_elaborateports 0 false user_clk2 in std_logic xilinx_elaborateports 0 false user_clk3 in std_logic xilinx_elaborateports 0 false clk_in1 in std_logic xilinx_elaborateports clk_150MHz out std_logic xilinx_elaborateports clk_300MHz out std_logic xilinx_elaborateports C_CLKOUT2_USED 1 C_USER_CLK_FREQ0 100.0 C_AUTO_PRIMITIVE PLL C_USER_CLK_FREQ1 100.0 C_USER_CLK_FREQ2 100.0 C_USER_CLK_FREQ3 100.0 C_ENABLE_CLOCK_MONITOR 0 C_ENABLE_USER_CLOCK0 0 C_ENABLE_USER_CLOCK1 0 C_ENABLE_USER_CLOCK2 0 C_ENABLE_USER_CLOCK3 0 C_Enable_PLL0 0 C_Enable_PLL1 0 C_REF_CLK_FREQ 100.0 C_PRECISION 1 C_CLKOUT3_USED 0 C_CLKOUT4_USED 0 C_CLKOUT5_USED 0 C_CLKOUT6_USED 0 C_CLKOUT7_USED 0 C_USE_CLKOUT1_BAR 0 C_USE_CLKOUT2_BAR 0 C_USE_CLKOUT3_BAR 0 C_USE_CLKOUT4_BAR 0 c_component_name clk_wiz_0 C_PLATFORM UNKNOWN C_USE_FREQ_SYNTH 1 C_USE_PHASE_ALIGNMENT 0 C_PRIM_IN_JITTER 0.010 C_SECONDARY_IN_JITTER 0.010 C_JITTER_SEL No_Jitter C_USE_MIN_POWER 0 C_USE_MIN_O_JITTER 0 C_USE_MAX_I_JITTER 0 C_USE_DYN_PHASE_SHIFT 0 C_USE_INCLK_SWITCHOVER 0 C_USE_DYN_RECONFIG 0 C_USE_SPREAD_SPECTRUM 0 C_USE_FAST_SIMULATION 0 C_PRIMTYPE_SEL AUTO C_USE_CLK_VALID 0 C_PRIM_IN_FREQ 100.000 C_PRIM_IN_TIMEPERIOD 10.000 C_IN_FREQ_UNITS Units_MHz C_SECONDARY_IN_FREQ 100.000 C_SECONDARY_IN_TIMEPERIOD 10.000 C_FEEDBACK_SOURCE FDBK_AUTO C_PRIM_SOURCE No_buffer C_PHASESHIFT_MODE LATENCY C_SECONDARY_SOURCE Single_ended_clock_capable_pin C_CLKFB_IN_SIGNALING SINGLE C_USE_RESET 0 C_RESET_LOW 0 C_USE_LOCKED 0 C_USE_INCLK_STOPPED 0 C_USE_CLKFB_STOPPED 0 C_USE_POWER_DOWN 0 C_USE_STATUS 0 C_USE_FREEZE 0 C_NUM_OUT_CLKS 2 C_CLKOUT1_DRIVES BUFG C_CLKOUT2_DRIVES BUFG C_CLKOUT3_DRIVES BUFG C_CLKOUT4_DRIVES BUFG C_CLKOUT5_DRIVES BUFG C_CLKOUT6_DRIVES BUFG C_CLKOUT7_DRIVES BUFG C_INCLK_SUM_ROW0 Input Clock Freq (MHz) Input Jitter (UI) C_INCLK_SUM_ROW1 __primary_________100.000____________0.010 C_INCLK_SUM_ROW2 no_secondary_input_clock C_OUTCLK_SUM_ROW0A C Outclk Sum Row0a Output Output Phase Duty Cycle Pk-to-Pk Phase C_OUTCLK_SUM_ROW0B Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) C_OUTCLK_SUM_ROW1 clk_150MHz__150.00000______0.000______50.0______127.220____105.461 C_OUTCLK_SUM_ROW2 clk_300MHz__300.00000______0.000______50.0______111.879____105.461 C_OUTCLK_SUM_ROW3 no_CLK_OUT3_output C_OUTCLK_SUM_ROW4 no_CLK_OUT4_output C_OUTCLK_SUM_ROW5 no_CLK_OUT5_output C_OUTCLK_SUM_ROW6 no_CLK_OUT6_output C_OUTCLK_SUM_ROW7 no_CLK_OUT7_output C_CLKOUT1_REQUESTED_OUT_FREQ 150 C_CLKOUT2_REQUESTED_OUT_FREQ 300 C_CLKOUT3_REQUESTED_OUT_FREQ 100.000 C_CLKOUT4_REQUESTED_OUT_FREQ 100.000 C_CLKOUT5_REQUESTED_OUT_FREQ 100.000 C_CLKOUT6_REQUESTED_OUT_FREQ 100.000 C_CLKOUT7_REQUESTED_OUT_FREQ 100.000 C_CLKOUT1_REQUESTED_PHASE 0.000 C_CLKOUT2_REQUESTED_PHASE 0.000 C_CLKOUT3_REQUESTED_PHASE 0.000 C_CLKOUT4_REQUESTED_PHASE 0.000 C_CLKOUT5_REQUESTED_PHASE 0.000 C_CLKOUT6_REQUESTED_PHASE 0.000 C_CLKOUT7_REQUESTED_PHASE 0.000 C_CLKOUT1_REQUESTED_DUTY_CYCLE 50.000 C_CLKOUT2_REQUESTED_DUTY_CYCLE 50.000 C_CLKOUT3_REQUESTED_DUTY_CYCLE 50.000 C_CLKOUT4_REQUESTED_DUTY_CYCLE 50.000 C_CLKOUT5_REQUESTED_DUTY_CYCLE 50.000 C_CLKOUT6_REQUESTED_DUTY_CYCLE 50.000 C_CLKOUT7_REQUESTED_DUTY_CYCLE 50.000 C_CLKOUT1_OUT_FREQ 150.00000 C_CLKOUT2_OUT_FREQ 300.00000 C_CLKOUT3_OUT_FREQ 100.000 C_CLKOUT4_OUT_FREQ 100.000 C_CLKOUT5_OUT_FREQ 100.000 C_CLKOUT6_OUT_FREQ 100.000 C_CLKOUT7_OUT_FREQ 100.000 C_CLKOUT1_PHASE 0.000 C_CLKOUT2_PHASE 0.000 C_CLKOUT3_PHASE 0.000 C_CLKOUT4_PHASE 0.000 C_CLKOUT5_PHASE 0.000 C_CLKOUT6_PHASE 0.000 C_CLKOUT7_PHASE 0.000 C_CLKOUT1_DUTY_CYCLE 50.0 C_CLKOUT2_DUTY_CYCLE 50.0 C_CLKOUT3_DUTY_CYCLE 50.000 C_CLKOUT4_DUTY_CYCLE 50.000 C_CLKOUT5_DUTY_CYCLE 50.000 C_CLKOUT6_DUTY_CYCLE 50.000 C_CLKOUT7_DUTY_CYCLE 50.000 C_USE_SAFE_CLOCK_STARTUP 0 C_USE_CLOCK_SEQUENCING 0 C_CLKOUT1_SEQUENCE_NUMBER 1 C_CLKOUT2_SEQUENCE_NUMBER 1 C_CLKOUT3_SEQUENCE_NUMBER 1 C_CLKOUT4_SEQUENCE_NUMBER 1 C_CLKOUT5_SEQUENCE_NUMBER 1 C_CLKOUT6_SEQUENCE_NUMBER 1 C_CLKOUT7_SEQUENCE_NUMBER 1 C_MMCM_NOTES None C_MMCM_BANDWIDTH OPTIMIZED C_MMCM_CLKFBOUT_MULT_F 9.000 C_MMCM_CLKIN1_PERIOD 10.000 C_MMCM_CLKIN2_PERIOD 10.000 C_MMCM_CLKOUT4_CASCADE FALSE C_MMCM_CLOCK_HOLD FALSE C_MMCM_COMPENSATION AUTO C_MMCM_DIVCLK_DIVIDE 1 C_MMCM_REF_JITTER1 0.010 C_MMCM_REF_JITTER2 0.010 C_MMCM_STARTUP_WAIT FALSE C_MMCM_CLKOUT0_DIVIDE_F 6.000 C_MMCM_CLKOUT1_DIVIDE 3 C_MMCM_CLKOUT2_DIVIDE 1 C_MMCM_CLKOUT3_DIVIDE 1 C_MMCM_CLKOUT4_DIVIDE 1 C_MMCM_CLKOUT5_DIVIDE 1 C_MMCM_CLKOUT6_DIVIDE 1 C_MMCM_CLKOUT0_DUTY_CYCLE 0.500 C_MMCM_CLKOUT1_DUTY_CYCLE 0.500 C_MMCM_CLKOUT2_DUTY_CYCLE 0.500 C_MMCM_CLKOUT3_DUTY_CYCLE 0.500 C_MMCM_CLKOUT4_DUTY_CYCLE 0.500 C_MMCM_CLKOUT5_DUTY_CYCLE 0.500 C_MMCM_CLKOUT6_DUTY_CYCLE 0.500 C_MMCM_CLKFBOUT_PHASE 0.000 C_MMCM_CLKOUT0_PHASE 0.000 C_MMCM_CLKOUT1_PHASE 0.000 C_MMCM_CLKOUT2_PHASE 0.000 C_MMCM_CLKOUT3_PHASE 0.000 C_MMCM_CLKOUT4_PHASE 0.000 C_MMCM_CLKOUT5_PHASE 0.000 C_MMCM_CLKOUT6_PHASE 0.000 C_MMCM_CLKFBOUT_USE_FINE_PS FALSE C_MMCM_CLKOUT0_USE_FINE_PS FALSE C_MMCM_CLKOUT1_USE_FINE_PS FALSE C_MMCM_CLKOUT2_USE_FINE_PS FALSE C_MMCM_CLKOUT3_USE_FINE_PS FALSE C_MMCM_CLKOUT4_USE_FINE_PS FALSE C_MMCM_CLKOUT5_USE_FINE_PS FALSE C_MMCM_CLKOUT6_USE_FINE_PS FALSE C_PLL_NOTES No notes C_PLL_BANDWIDTH OPTIMIZED C_PLL_CLK_FEEDBACK CLKFBOUT C_PLL_CLKFBOUT_MULT 1 C_PLL_CLKIN_PERIOD 1.000 C_PLL_COMPENSATION SYSTEM_SYNCHRONOUS C_PLL_DIVCLK_DIVIDE 1 C_PLL_REF_JITTER 0.010 C_PLL_CLKOUT0_DIVIDE 1 C_PLL_CLKOUT1_DIVIDE 1 C_PLL_CLKOUT2_DIVIDE 1 C_PLL_CLKOUT3_DIVIDE 1 C_PLL_CLKOUT4_DIVIDE 1 C_PLL_CLKOUT5_DIVIDE 1 C_PLL_CLKOUT0_DUTY_CYCLE 0.500 C_PLL_CLKOUT1_DUTY_CYCLE 0.500 C_PLL_CLKOUT2_DUTY_CYCLE 0.500 C_PLL_CLKOUT3_DUTY_CYCLE 0.500 C_PLL_CLKOUT4_DUTY_CYCLE 0.500 C_PLL_CLKOUT5_DUTY_CYCLE 0.500 C_PLL_CLKFBOUT_PHASE 0.000 C_PLL_CLKOUT0_PHASE 0.000 C_PLL_CLKOUT1_PHASE 0.000 C_PLL_CLKOUT2_PHASE 0.000 C_PLL_CLKOUT3_PHASE 0.000 C_PLL_CLKOUT4_PHASE 0.000 C_PLL_CLKOUT5_PHASE 0.000 C_CLOCK_MGR_TYPE NA C_OVERRIDE_MMCM 0 C_OVERRIDE_PLL 0 C_PRIMARY_PORT clk_in1 C_SECONDARY_PORT clk_in2 C_CLK_OUT1_PORT clk_150MHz C_CLK_OUT2_PORT clk_300MHz C_CLK_OUT3_PORT clk_out3 C_CLK_OUT4_PORT clk_out4 C_CLK_OUT5_PORT clk_out5 C_CLK_OUT6_PORT clk_out6 C_CLK_OUT7_PORT clk_out7 C_RESET_PORT reset C_LOCKED_PORT locked C_CLKFB_IN_PORT clkfb_in C_CLKFB_IN_P_PORT clkfb_in_p C_CLKFB_IN_N_PORT clkfb_in_n C_CLKFB_OUT_PORT clkfb_out C_CLKFB_OUT_P_PORT clkfb_out_p C_CLKFB_OUT_N_PORT clkfb_out_n C_POWER_DOWN_PORT power_down C_DADDR_PORT daddr C_DCLK_PORT dclk C_DRDY_PORT drdy C_DWE_PORT dwe C_DIN_PORT din C_DOUT_PORT dout C_DEN_PORT den C_PSCLK_PORT psclk C_PSEN_PORT psen C_PSINCDEC_PORT psincdec C_PSDONE_PORT psdone C_CLK_VALID_PORT CLK_VALID C_STATUS_PORT STATUS C_CLK_IN_SEL_PORT clk_in_sel C_INPUT_CLK_STOPPED_PORT input_clk_stopped C_CLKFB_STOPPED_PORT clkfb_stopped C_CLKIN1_JITTER_PS 100.0 C_CLKIN2_JITTER_PS 100.0 C_PRIMITIVE Auto C_SS_MODE CENTER_HIGH C_SS_MOD_PERIOD 4000 C_SS_MOD_TIME 0.004 C_HAS_CDDC 0 C_CDDCDONE_PORT cddcdone C_CDDCREQ_PORT cddcreq C_CLKOUTPHY_MODE VCO C_ENABLE_CLKOUTPHY 0 C_INTERFACE_SELECTION 0 C_S_AXI_ADDR_WIDTH C S Axi Addr Width 11 C_S_AXI_DATA_WIDTH C S Axi Data Width 32 C_POWER_REG 0000 C_CLKOUT0_1 0000 C_CLKOUT0_2 0000 C_CLKOUT1_1 0000 C_CLKOUT1_2 0000 C_CLKOUT2_1 0000 C_CLKOUT2_2 0000 C_CLKOUT3_1 0000 C_CLKOUT3_2 0000 C_CLKOUT4_1 0000 C_CLKOUT4_2 0000 C_CLKOUT5_1 0000 C_CLKOUT5_2 0000 C_CLKOUT6_1 0000 C_CLKOUT6_2 0000 C_CLKFBOUT_1 0000 C_CLKFBOUT_2 0000 C_DIVCLK 0000 C_LOCK_1 0000 C_LOCK_2 0000 C_LOCK_3 0000 C_FILTER_1 0000 C_FILTER_2 0000 C_DIVIDE1_AUTO 1 C_DIVIDE2_AUTO 0.5 C_DIVIDE3_AUTO 1.5 C_DIVIDE4_AUTO 1.5 C_DIVIDE5_AUTO 1.5 C_DIVIDE6_AUTO 1.5 C_DIVIDE7_AUTO 1.5 C_PLLBUFGCEDIV false C_MMCMBUFGCEDIV false C_PLLBUFGCEDIV1 false C_PLLBUFGCEDIV2 false C_PLLBUFGCEDIV3 false C_PLLBUFGCEDIV4 false C_MMCMBUFGCEDIV1 false C_MMCMBUFGCEDIV2 false C_MMCMBUFGCEDIV3 false C_MMCMBUFGCEDIV4 false C_MMCMBUFGCEDIV5 false C_MMCMBUFGCEDIV6 false C_MMCMBUFGCEDIV7 false C_CLKOUT1_MATCHED_ROUTING false C_CLKOUT2_MATCHED_ROUTING false C_CLKOUT3_MATCHED_ROUTING false C_CLKOUT4_MATCHED_ROUTING false C_CLKOUT5_MATCHED_ROUTING false C_CLKOUT6_MATCHED_ROUTING false C_CLKOUT7_MATCHED_ROUTING false C_CLKOUT0_ACTUAL_FREQ 150.00000 C_CLKOUT1_ACTUAL_FREQ 300.00000 C_CLKOUT2_ACTUAL_FREQ 100.000 C_CLKOUT3_ACTUAL_FREQ 100.000 C_CLKOUT4_ACTUAL_FREQ 100.000 C_CLKOUT5_ACTUAL_FREQ 100.000 C_CLKOUT6_ACTUAL_FREQ 100.000 C_M_MAX 128.000 C_M_MIN 2.000 C_D_MAX 93.000 C_D_MIN 1.000 C_O_MAX 128.000 C_O_MIN 1.000 C_VCO_MIN 750.000 C_VCO_MAX 1500.000 choice_list_1d3de01d WAVEFORM LATENCY choice_list_876bfc32 UI PS choice_list_a9bdfce0 LOW HIGH OPTIMIZED choice_list_ac75ef1e Custom choice_list_b9d38208 CLKFBOUT CLKOUT0 choice_list_d0ea4aeb MMCM PLL Auto choice_pairs_035ca1c3 SYSTEM_SYNCHRONOUS SOURCE_SYNCHRONOUS INTERNAL EXTERNAL choice_pairs_0920eb1b Custom sys_diff_clock choice_pairs_11d71346 Single_ended_clock_capable_pin Differential_clock_capable_pin Global_buffer No_buffer choice_pairs_15c806d5 FDBK_AUTO FDBK_AUTO_OFFCHIP FDBK_ONCHIP FDBK_OFFCHIP choice_pairs_39d99e50 Buffer Buffer_with_CE BUFG BUFGCE BUFGCE_DIV No_buffer choice_pairs_3c2d3ec7 SINGLE DIFF choice_pairs_77d3d587 MMCM PLL BUFGCE_DIV choice_pairs_8b28f1f7 Enable_AXI Enable_DRP choice_pairs_8eea9b32 Units_MHz Units_ns choice_pairs_94e02745 AUTO EXTERNAL INTERNAL BUF_IN ZHOLD choice_pairs_a4fbc00c ACTIVE_HIGH ACTIVE_LOW choice_pairs_a7c40375 Custom cmc_clk hbm_clk pcie_refclk qsfp_161mhz qsfp_322mhz choice_pairs_a8642b4c No_Jitter Min_O_Jitter Max_I_Jitter choice_pairs_c5ef7212 Units_UI Units_ps choice_pairs_e1c87518 REL_PRIMARY REL_SECONDARY choice_pairs_f4e10086 CENTER_HIGH CENTER_LOW DOWN_HIGH DOWN_LOW choice_pairs_f669c2f5 frequency Time The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. Component_Name clk_wiz_0 USER_CLK_FREQ0 User Frequency(MHz) 100.0 USER_CLK_FREQ1 User Frequency(MHz) 100.0 USER_CLK_FREQ2 User Frequency(MHz) 100.0 USER_CLK_FREQ3 User Frequency(MHz) 100.0 ENABLE_CLOCK_MONITOR Enable Clock Monitoring false ENABLE_USER_CLOCK0 User Clock false ENABLE_USER_CLOCK1 User Clock false ENABLE_USER_CLOCK2 User Clock false ENABLE_USER_CLOCK3 User Clock false Enable_PLL0 User Clock false Enable_PLL1 User Clock false REF_CLK_FREQ Reference Frequency(MHz) 100.0 PRECISION Tolerance(MHz) 1 PRIMITIVE Primitive Auto PRIMTYPE_SEL Primtype Sel mmcm_adv CLOCK_MGR_TYPE Clock Mgr Type auto USE_FREQ_SYNTH true USE_SPREAD_SPECTRUM false USE_PHASE_ALIGNMENT false USE_MIN_POWER false USE_DYN_PHASE_SHIFT false USE_DYN_RECONFIG false JITTER_SEL No_Jitter PRIM_IN_FREQ 100.000 PRIM_IN_TIMEPERIOD 10.000 IN_FREQ_UNITS Units_MHz PHASESHIFT_MODE LATENCY IN_JITTER_UNITS Units_UI RELATIVE_INCLK REL_PRIMARY USE_INCLK_SWITCHOVER false SECONDARY_IN_FREQ 100.000 SECONDARY_IN_TIMEPERIOD 10.000 SECONDARY_PORT clk_in2 SECONDARY_SOURCE Single_ended_clock_capable_pin JITTER_OPTIONS UI CLKIN1_UI_JITTER 0.010 CLKIN2_UI_JITTER 0.010 PRIM_IN_JITTER 0.010 SECONDARY_IN_JITTER 0.010 CLKIN1_JITTER_PS 100.0 CLKIN2_JITTER_PS 100.0 CLKOUT1_USED true CLKOUT2_USED true CLKOUT3_USED false CLKOUT4_USED false CLKOUT5_USED false CLKOUT6_USED false CLKOUT7_USED false NUM_OUT_CLKS 2 CLK_OUT1_USE_FINE_PS_GUI false CLK_OUT2_USE_FINE_PS_GUI false CLK_OUT3_USE_FINE_PS_GUI false CLK_OUT4_USE_FINE_PS_GUI false CLK_OUT5_USE_FINE_PS_GUI false CLK_OUT6_USE_FINE_PS_GUI false CLK_OUT7_USE_FINE_PS_GUI false PRIMARY_PORT clk_in1 CLK_OUT1_PORT clk_150MHz CLK_OUT2_PORT clk_300MHz CLK_OUT3_PORT clk_out3 CLK_OUT4_PORT clk_out4 CLK_OUT5_PORT clk_out5 CLK_OUT6_PORT clk_out6 CLK_OUT7_PORT clk_out7 DADDR_PORT daddr DCLK_PORT dclk DRDY_PORT drdy DWE_PORT dwe DIN_PORT din DOUT_PORT dout DEN_PORT den PSCLK_PORT psclk PSEN_PORT psen PSINCDEC_PORT psincdec PSDONE_PORT psdone CLKOUT1_REQUESTED_OUT_FREQ 150 CLKOUT1_REQUESTED_PHASE 0.000 CLKOUT1_REQUESTED_DUTY_CYCLE 50.000 CLKOUT2_REQUESTED_OUT_FREQ 300 CLKOUT2_REQUESTED_PHASE 0.000 CLKOUT2_REQUESTED_DUTY_CYCLE 50.000 CLKOUT3_REQUESTED_OUT_FREQ 100.000 CLKOUT3_REQUESTED_PHASE 0.000 CLKOUT3_REQUESTED_DUTY_CYCLE 50.000 CLKOUT4_REQUESTED_OUT_FREQ 100.000 CLKOUT4_REQUESTED_PHASE 0.000 CLKOUT4_REQUESTED_DUTY_CYCLE 50.000 CLKOUT5_REQUESTED_OUT_FREQ 100.000 CLKOUT5_REQUESTED_PHASE 0.000 CLKOUT5_REQUESTED_DUTY_CYCLE 50.000 CLKOUT6_REQUESTED_OUT_FREQ 100.000 CLKOUT6_REQUESTED_PHASE 0.000 CLKOUT6_REQUESTED_DUTY_CYCLE 50.000 CLKOUT7_REQUESTED_OUT_FREQ 100.000 CLKOUT7_REQUESTED_PHASE 0.000 CLKOUT7_REQUESTED_DUTY_CYCLE 50.000 USE_MAX_I_JITTER false USE_MIN_O_JITTER false CLKOUT1_MATCHED_ROUTING false CLKOUT2_MATCHED_ROUTING false CLKOUT3_MATCHED_ROUTING false CLKOUT4_MATCHED_ROUTING false CLKOUT5_MATCHED_ROUTING false CLKOUT6_MATCHED_ROUTING false CLKOUT7_MATCHED_ROUTING false PRIM_SOURCE No_buffer CLKOUT1_DRIVES Buffer CLKOUT2_DRIVES Buffer CLKOUT3_DRIVES Buffer CLKOUT4_DRIVES Buffer CLKOUT5_DRIVES Buffer CLKOUT6_DRIVES Buffer CLKOUT7_DRIVES Buffer FEEDBACK_SOURCE FDBK_AUTO CLKFB_IN_SIGNALING SINGLE CLKFB_IN_PORT clkfb_in CLKFB_IN_P_PORT clkfb_in_p CLKFB_IN_N_PORT clkfb_in_n CLKFB_OUT_PORT clkfb_out CLKFB_OUT_P_PORT clkfb_out_p CLKFB_OUT_N_PORT clkfb_out_n PLATFORM UNKNOWN SUMMARY_STRINGS empty USE_LOCKED false CALC_DONE empty USE_RESET false USE_POWER_DOWN false USE_STATUS false USE_FREEZE false USE_CLK_VALID false USE_INCLK_STOPPED false USE_CLKFB_STOPPED false RESET_PORT reset LOCKED_PORT locked POWER_DOWN_PORT power_down CLK_VALID_PORT CLK_VALID STATUS_PORT STATUS CLK_IN_SEL_PORT clk_in_sel INPUT_CLK_STOPPED_PORT input_clk_stopped CLKFB_STOPPED_PORT clkfb_stopped SS_MODE CENTER_HIGH SS_MOD_FREQ 250 SS_MOD_TIME 0.004 OVERRIDE_MMCM false MMCM_NOTES None MMCM_DIVCLK_DIVIDE 1 MMCM_BANDWIDTH OPTIMIZED MMCM_CLKFBOUT_MULT_F 9 MMCM_CLKFBOUT_PHASE 0.000 MMCM_CLKFBOUT_USE_FINE_PS false MMCM_CLKIN1_PERIOD 10.000 MMCM_CLKIN2_PERIOD 10.000 MMCM_CLKOUT4_CASCADE false MMCM_CLOCK_HOLD false MMCM_COMPENSATION AUTO MMCM_REF_JITTER1 0.010 MMCM_REF_JITTER2 0.010 MMCM_STARTUP_WAIT false MMCM_CLKOUT0_DIVIDE_F 6 MMCM_CLKOUT0_DUTY_CYCLE 0.500 MMCM_CLKOUT0_PHASE 0.000 MMCM_CLKOUT0_USE_FINE_PS false MMCM_CLKOUT1_DIVIDE 3 MMCM_CLKOUT1_DUTY_CYCLE 0.500 MMCM_CLKOUT1_PHASE 0.000 MMCM_CLKOUT1_USE_FINE_PS false MMCM_CLKOUT2_DIVIDE 1 MMCM_CLKOUT2_DUTY_CYCLE 0.500 MMCM_CLKOUT2_PHASE 0.000 MMCM_CLKOUT2_USE_FINE_PS false MMCM_CLKOUT3_DIVIDE 1 MMCM_CLKOUT3_DUTY_CYCLE 0.500 MMCM_CLKOUT3_PHASE 0.000 MMCM_CLKOUT3_USE_FINE_PS false MMCM_CLKOUT4_DIVIDE 1 MMCM_CLKOUT4_DUTY_CYCLE 0.500 MMCM_CLKOUT4_PHASE 0.000 MMCM_CLKOUT4_USE_FINE_PS false MMCM_CLKOUT5_DIVIDE 1 MMCM_CLKOUT5_DUTY_CYCLE 0.500 MMCM_CLKOUT5_PHASE 0.000 MMCM_CLKOUT5_USE_FINE_PS false MMCM_CLKOUT6_DIVIDE 1 MMCM_CLKOUT6_DUTY_CYCLE 0.500 MMCM_CLKOUT6_PHASE 0.000 MMCM_CLKOUT6_USE_FINE_PS false OVERRIDE_PLL false PLL_NOTES None PLL_BANDWIDTH OPTIMIZED PLL_CLKFBOUT_MULT 4 PLL_CLKFBOUT_PHASE 0.000 PLL_CLK_FEEDBACK CLKFBOUT PLL_DIVCLK_DIVIDE 1 PLL_CLKIN_PERIOD 10.000 PLL_COMPENSATION SYSTEM_SYNCHRONOUS PLL_REF_JITTER 0.010 PLL_CLKOUT0_DIVIDE 1 PLL_CLKOUT0_DUTY_CYCLE 0.500 PLL_CLKOUT0_PHASE 0.000 PLL_CLKOUT1_DIVIDE 1 PLL_CLKOUT1_DUTY_CYCLE 0.500 PLL_CLKOUT1_PHASE 0.000 PLL_CLKOUT2_DIVIDE 1 PLL_CLKOUT2_DUTY_CYCLE 0.500 PLL_CLKOUT2_PHASE 0.000 PLL_CLKOUT3_DIVIDE 1 PLL_CLKOUT3_DUTY_CYCLE 0.500 PLL_CLKOUT3_PHASE 0.000 PLL_CLKOUT4_DIVIDE 1 PLL_CLKOUT4_DUTY_CYCLE 0.500 PLL_CLKOUT4_PHASE 0.000 PLL_CLKOUT5_DIVIDE 1 PLL_CLKOUT5_DUTY_CYCLE 0.500 PLL_CLKOUT5_PHASE 0.000 RESET_TYPE Reset Type ACTIVE_HIGH USE_SAFE_CLOCK_STARTUP false USE_CLOCK_SEQUENCING false CLKOUT1_SEQUENCE_NUMBER 1 CLKOUT2_SEQUENCE_NUMBER 1 CLKOUT3_SEQUENCE_NUMBER 1 CLKOUT4_SEQUENCE_NUMBER 1 CLKOUT5_SEQUENCE_NUMBER 1 CLKOUT6_SEQUENCE_NUMBER 1 CLKOUT7_SEQUENCE_NUMBER 1 USE_BOARD_FLOW Generate Board based IO Constraints false CLK_IN1_BOARD_INTERFACE Custom CLK_IN2_BOARD_INTERFACE Custom DIFF_CLK_IN1_BOARD_INTERFACE Custom DIFF_CLK_IN2_BOARD_INTERFACE Custom AUTO_PRIMITIVE PLL RESET_BOARD_INTERFACE Custom ENABLE_CDDC false CDDCDONE_PORT cddcdone CDDCREQ_PORT cddcreq ENABLE_CLKOUTPHY false CLKOUTPHY_REQUESTED_FREQ 600.000 CLKOUT1_JITTER Clkout1 Jitter 127.220 CLKOUT1_PHASE_ERROR Clkout1 Phase 105.461 CLKOUT2_JITTER Clkout2 Jitter 111.879 CLKOUT2_PHASE_ERROR Clkout2 Phase 105.461 CLKOUT3_JITTER Clkout3 Jitter 115.831 CLKOUT3_PHASE_ERROR Clkout3 Phase 87.180 CLKOUT4_JITTER Clkout4 Jitter 0.0 CLKOUT4_PHASE_ERROR Clkout4 Phase 0.0 CLKOUT5_JITTER Clkout5 Jitter 0.0 CLKOUT5_PHASE_ERROR Clkout5 Phase 0.0 CLKOUT6_JITTER Clkout6 Jitter 0.0 CLKOUT6_PHASE_ERROR Clkout6 Phase 0.0 CLKOUT7_JITTER Clkout7 Jitter 0.0 CLKOUT7_PHASE_ERROR Clkout7 Phase 0.0 INPUT_MODE frequency INTERFACE_SELECTION Enable_AXI AXI_DRP Write DRP registers false PHASE_DUTY_CONFIG Phase Duty Cycle Config false Clocking Wizard XPM_CDC 6 2020.2