xilinx.com customized_ip hbm_0 1.0 HBM_REF_CLK_0 true CLK HBM_REF_CLK_0 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl HBM_REF_CLK_1 true CLK HBM_REF_CLK_1 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl true ACLK_00 true CLK AXI_00_ACLK ASSOCIATED_BUSIF SAXI_00 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_00_RT true CLK AXI_00_ACLK ASSOCIATED_BUSIF SAXI_00_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_00_8HI true CLK AXI_00_ACLK ASSOCIATED_BUSIF SAXI_00_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_00_RT_8HI true CLK AXI_00_ACLK ASSOCIATED_BUSIF SAXI_00_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_00_N true RST AXI_00_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_00 true ARADDR AXI_00_ARADDR ARBURST AXI_00_ARBURST ARID AXI_00_ARID ARLEN AXI_00_ARLEN ARREADY AXI_00_ARREADY ARSIZE AXI_00_ARSIZE ARVALID AXI_00_ARVALID AWADDR AXI_00_AWADDR AWBURST AXI_00_AWBURST AWID AXI_00_AWID AWLEN AXI_00_AWLEN AWREADY AXI_00_AWREADY AWSIZE AXI_00_AWSIZE AWVALID AXI_00_AWVALID BID AXI_00_BID BREADY AXI_00_BREADY BRESP AXI_00_BRESP BVALID AXI_00_BVALID RDATA AXI_00_RDATA RID AXI_00_RID RLAST AXI_00_RLAST RREADY AXI_00_RREADY RRESP AXI_00_RRESP RVALID AXI_00_RVALID WDATA AXI_00_WDATA WLAST AXI_00_WLAST WREADY AXI_00_WREADY WSTRB AXI_00_WSTRB WVALID AXI_00_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_00_RT true ARADDR AXI_00_ARADDR ARBURST AXI_00_ARBURST ARID AXI_00_ARID ARLEN AXI_00_ARLEN ARREADY AXI_00_ARREADY ARSIZE AXI_00_ARSIZE ARVALID AXI_00_ARVALID AWADDR AXI_00_AWADDR AWBURST AXI_00_AWBURST AWID AXI_00_AWID AWLEN AXI_00_AWLEN AWREADY AXI_00_AWREADY AWSIZE AXI_00_AWSIZE AWVALID AXI_00_AWVALID BID AXI_00_BID BREADY AXI_00_BREADY BRESP AXI_00_BRESP BVALID AXI_00_BVALID RDATA AXI_00_RDATA RID AXI_00_RID RLAST AXI_00_RLAST RREADY AXI_00_RREADY RRESP AXI_00_RRESP RVALID AXI_00_RVALID WDATA AXI_00_WDATA WLAST AXI_00_WLAST WREADY AXI_00_WREADY WSTRB AXI_00_WSTRB WVALID AXI_00_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_00_8HI true ARADDR AXI_00_ARADDR ARBURST AXI_00_ARBURST ARID AXI_00_ARID ARLEN AXI_00_ARLEN ARREADY AXI_00_ARREADY ARSIZE AXI_00_ARSIZE ARVALID AXI_00_ARVALID AWADDR AXI_00_AWADDR AWBURST AXI_00_AWBURST AWID AXI_00_AWID AWLEN AXI_00_AWLEN AWREADY AXI_00_AWREADY AWSIZE AXI_00_AWSIZE AWVALID AXI_00_AWVALID BID AXI_00_BID BREADY AXI_00_BREADY BRESP AXI_00_BRESP BVALID AXI_00_BVALID RDATA AXI_00_RDATA RID AXI_00_RID RLAST AXI_00_RLAST RREADY AXI_00_RREADY RRESP AXI_00_RRESP RVALID AXI_00_RVALID WDATA AXI_00_WDATA WLAST AXI_00_WLAST WREADY AXI_00_WREADY WSTRB AXI_00_WSTRB WVALID AXI_00_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_00_RT_8HI true ARADDR AXI_00_ARADDR ARBURST AXI_00_ARBURST ARID AXI_00_ARID ARLEN AXI_00_ARLEN ARREADY AXI_00_ARREADY ARSIZE AXI_00_ARSIZE ARVALID AXI_00_ARVALID AWADDR AXI_00_AWADDR AWBURST AXI_00_AWBURST AWID AXI_00_AWID AWLEN AXI_00_AWLEN AWREADY AXI_00_AWREADY AWSIZE AXI_00_AWSIZE AWVALID AXI_00_AWVALID BID AXI_00_BID BREADY AXI_00_BREADY BRESP AXI_00_BRESP BVALID AXI_00_BVALID RDATA AXI_00_RDATA RID AXI_00_RID RLAST AXI_00_RLAST RREADY AXI_00_RREADY RRESP AXI_00_RRESP RVALID AXI_00_RVALID WDATA AXI_00_WDATA WLAST AXI_00_WLAST WREADY AXI_00_WREADY WSTRB AXI_00_WSTRB WVALID AXI_00_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_01 true CLK AXI_01_ACLK ASSOCIATED_BUSIF SAXI_01 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_01_RT true CLK AXI_01_ACLK ASSOCIATED_BUSIF SAXI_01_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_01_8HI true CLK AXI_01_ACLK ASSOCIATED_BUSIF SAXI_01_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_01_RT_8HI true CLK AXI_01_ACLK ASSOCIATED_BUSIF SAXI_01_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_01_N true RST AXI_01_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_01 true ARADDR AXI_01_ARADDR ARBURST AXI_01_ARBURST ARID AXI_01_ARID ARLEN AXI_01_ARLEN ARREADY AXI_01_ARREADY ARSIZE AXI_01_ARSIZE ARVALID AXI_01_ARVALID AWADDR AXI_01_AWADDR AWBURST AXI_01_AWBURST AWID AXI_01_AWID AWLEN AXI_01_AWLEN AWREADY AXI_01_AWREADY AWSIZE AXI_01_AWSIZE AWVALID AXI_01_AWVALID BID AXI_01_BID BREADY AXI_01_BREADY BRESP AXI_01_BRESP BVALID AXI_01_BVALID RDATA AXI_01_RDATA RID AXI_01_RID RLAST AXI_01_RLAST RREADY AXI_01_RREADY RRESP AXI_01_RRESP RVALID AXI_01_RVALID WDATA AXI_01_WDATA WLAST AXI_01_WLAST WREADY AXI_01_WREADY WSTRB AXI_01_WSTRB WVALID AXI_01_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_01_RT true ARADDR AXI_01_ARADDR ARBURST AXI_01_ARBURST ARID AXI_01_ARID ARLEN AXI_01_ARLEN ARREADY AXI_01_ARREADY ARSIZE AXI_01_ARSIZE ARVALID AXI_01_ARVALID AWADDR AXI_01_AWADDR AWBURST AXI_01_AWBURST AWID AXI_01_AWID AWLEN AXI_01_AWLEN AWREADY AXI_01_AWREADY AWSIZE AXI_01_AWSIZE AWVALID AXI_01_AWVALID BID AXI_01_BID BREADY AXI_01_BREADY BRESP AXI_01_BRESP BVALID AXI_01_BVALID RDATA AXI_01_RDATA RID AXI_01_RID RLAST AXI_01_RLAST RREADY AXI_01_RREADY RRESP AXI_01_RRESP RVALID AXI_01_RVALID WDATA AXI_01_WDATA WLAST AXI_01_WLAST WREADY AXI_01_WREADY WSTRB AXI_01_WSTRB WVALID AXI_01_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_01_8HI true ARADDR AXI_01_ARADDR ARBURST AXI_01_ARBURST ARID AXI_01_ARID ARLEN AXI_01_ARLEN ARREADY AXI_01_ARREADY ARSIZE AXI_01_ARSIZE ARVALID AXI_01_ARVALID AWADDR AXI_01_AWADDR AWBURST AXI_01_AWBURST AWID AXI_01_AWID AWLEN AXI_01_AWLEN AWREADY AXI_01_AWREADY AWSIZE AXI_01_AWSIZE AWVALID AXI_01_AWVALID BID AXI_01_BID BREADY AXI_01_BREADY BRESP AXI_01_BRESP BVALID AXI_01_BVALID RDATA AXI_01_RDATA RID AXI_01_RID RLAST AXI_01_RLAST RREADY AXI_01_RREADY RRESP AXI_01_RRESP RVALID AXI_01_RVALID WDATA AXI_01_WDATA WLAST AXI_01_WLAST WREADY AXI_01_WREADY WSTRB AXI_01_WSTRB WVALID AXI_01_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_01_RT_8HI true ARADDR AXI_01_ARADDR ARBURST AXI_01_ARBURST ARID AXI_01_ARID ARLEN AXI_01_ARLEN ARREADY AXI_01_ARREADY ARSIZE AXI_01_ARSIZE ARVALID AXI_01_ARVALID AWADDR AXI_01_AWADDR AWBURST AXI_01_AWBURST AWID AXI_01_AWID AWLEN AXI_01_AWLEN AWREADY AXI_01_AWREADY AWSIZE AXI_01_AWSIZE AWVALID AXI_01_AWVALID BID AXI_01_BID BREADY AXI_01_BREADY BRESP AXI_01_BRESP BVALID AXI_01_BVALID RDATA AXI_01_RDATA RID AXI_01_RID RLAST AXI_01_RLAST RREADY AXI_01_RREADY RRESP AXI_01_RRESP RVALID AXI_01_RVALID WDATA AXI_01_WDATA WLAST AXI_01_WLAST WREADY AXI_01_WREADY WSTRB AXI_01_WSTRB WVALID AXI_01_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_02 true CLK AXI_02_ACLK ASSOCIATED_BUSIF SAXI_02 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_02_RT true CLK AXI_02_ACLK ASSOCIATED_BUSIF SAXI_02_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_02_8HI true CLK AXI_02_ACLK ASSOCIATED_BUSIF SAXI_02_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_02_RT_8HI true CLK AXI_02_ACLK ASSOCIATED_BUSIF SAXI_02_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_02_N true RST AXI_02_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_02 true ARADDR AXI_02_ARADDR ARBURST AXI_02_ARBURST ARID AXI_02_ARID ARLEN AXI_02_ARLEN ARREADY AXI_02_ARREADY ARSIZE AXI_02_ARSIZE ARVALID AXI_02_ARVALID AWADDR AXI_02_AWADDR AWBURST AXI_02_AWBURST AWID AXI_02_AWID AWLEN AXI_02_AWLEN AWREADY AXI_02_AWREADY AWSIZE AXI_02_AWSIZE AWVALID AXI_02_AWVALID BID AXI_02_BID BREADY AXI_02_BREADY BRESP AXI_02_BRESP BVALID AXI_02_BVALID RDATA AXI_02_RDATA RID AXI_02_RID RLAST AXI_02_RLAST RREADY AXI_02_RREADY RRESP AXI_02_RRESP RVALID AXI_02_RVALID WDATA AXI_02_WDATA WLAST AXI_02_WLAST WREADY AXI_02_WREADY WSTRB AXI_02_WSTRB WVALID AXI_02_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_02_RT true ARADDR AXI_02_ARADDR ARBURST AXI_02_ARBURST ARID AXI_02_ARID ARLEN AXI_02_ARLEN ARREADY AXI_02_ARREADY ARSIZE AXI_02_ARSIZE ARVALID AXI_02_ARVALID AWADDR AXI_02_AWADDR AWBURST AXI_02_AWBURST AWID AXI_02_AWID AWLEN AXI_02_AWLEN AWREADY AXI_02_AWREADY AWSIZE AXI_02_AWSIZE AWVALID AXI_02_AWVALID BID AXI_02_BID BREADY AXI_02_BREADY BRESP AXI_02_BRESP BVALID AXI_02_BVALID RDATA AXI_02_RDATA RID AXI_02_RID RLAST AXI_02_RLAST RREADY AXI_02_RREADY RRESP AXI_02_RRESP RVALID AXI_02_RVALID WDATA AXI_02_WDATA WLAST AXI_02_WLAST WREADY AXI_02_WREADY WSTRB AXI_02_WSTRB WVALID AXI_02_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_02_8HI true ARADDR AXI_02_ARADDR ARBURST AXI_02_ARBURST ARID AXI_02_ARID ARLEN AXI_02_ARLEN ARREADY AXI_02_ARREADY ARSIZE AXI_02_ARSIZE ARVALID AXI_02_ARVALID AWADDR AXI_02_AWADDR AWBURST AXI_02_AWBURST AWID AXI_02_AWID AWLEN AXI_02_AWLEN AWREADY AXI_02_AWREADY AWSIZE AXI_02_AWSIZE AWVALID AXI_02_AWVALID BID AXI_02_BID BREADY AXI_02_BREADY BRESP AXI_02_BRESP BVALID AXI_02_BVALID RDATA AXI_02_RDATA RID AXI_02_RID RLAST AXI_02_RLAST RREADY AXI_02_RREADY RRESP AXI_02_RRESP RVALID AXI_02_RVALID WDATA AXI_02_WDATA WLAST AXI_02_WLAST WREADY AXI_02_WREADY WSTRB AXI_02_WSTRB WVALID AXI_02_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_02_RT_8HI true ARADDR AXI_02_ARADDR ARBURST AXI_02_ARBURST ARID AXI_02_ARID ARLEN AXI_02_ARLEN ARREADY AXI_02_ARREADY ARSIZE AXI_02_ARSIZE ARVALID AXI_02_ARVALID AWADDR AXI_02_AWADDR AWBURST AXI_02_AWBURST AWID AXI_02_AWID AWLEN AXI_02_AWLEN AWREADY AXI_02_AWREADY AWSIZE AXI_02_AWSIZE AWVALID AXI_02_AWVALID BID AXI_02_BID BREADY AXI_02_BREADY BRESP AXI_02_BRESP BVALID AXI_02_BVALID RDATA AXI_02_RDATA RID AXI_02_RID RLAST AXI_02_RLAST RREADY AXI_02_RREADY RRESP AXI_02_RRESP RVALID AXI_02_RVALID WDATA AXI_02_WDATA WLAST AXI_02_WLAST WREADY AXI_02_WREADY WSTRB AXI_02_WSTRB WVALID AXI_02_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_03 true CLK AXI_03_ACLK ASSOCIATED_BUSIF SAXI_03 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_03_RT true CLK AXI_03_ACLK ASSOCIATED_BUSIF SAXI_03_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_03_8HI true CLK AXI_03_ACLK ASSOCIATED_BUSIF SAXI_03_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_03_RT_8HI true CLK AXI_03_ACLK ASSOCIATED_BUSIF SAXI_03_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_03_N true RST AXI_03_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_03 true ARADDR AXI_03_ARADDR ARBURST AXI_03_ARBURST ARID AXI_03_ARID ARLEN AXI_03_ARLEN ARREADY AXI_03_ARREADY ARSIZE AXI_03_ARSIZE ARVALID AXI_03_ARVALID AWADDR AXI_03_AWADDR AWBURST AXI_03_AWBURST AWID AXI_03_AWID AWLEN AXI_03_AWLEN AWREADY AXI_03_AWREADY AWSIZE AXI_03_AWSIZE AWVALID AXI_03_AWVALID BID AXI_03_BID BREADY AXI_03_BREADY BRESP AXI_03_BRESP BVALID AXI_03_BVALID RDATA AXI_03_RDATA RID AXI_03_RID RLAST AXI_03_RLAST RREADY AXI_03_RREADY RRESP AXI_03_RRESP RVALID AXI_03_RVALID WDATA AXI_03_WDATA WLAST AXI_03_WLAST WREADY AXI_03_WREADY WSTRB AXI_03_WSTRB WVALID AXI_03_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_03_RT true ARADDR AXI_03_ARADDR ARBURST AXI_03_ARBURST ARID AXI_03_ARID ARLEN AXI_03_ARLEN ARREADY AXI_03_ARREADY ARSIZE AXI_03_ARSIZE ARVALID AXI_03_ARVALID AWADDR AXI_03_AWADDR AWBURST AXI_03_AWBURST AWID AXI_03_AWID AWLEN AXI_03_AWLEN AWREADY AXI_03_AWREADY AWSIZE AXI_03_AWSIZE AWVALID AXI_03_AWVALID BID AXI_03_BID BREADY AXI_03_BREADY BRESP AXI_03_BRESP BVALID AXI_03_BVALID RDATA AXI_03_RDATA RID AXI_03_RID RLAST AXI_03_RLAST RREADY AXI_03_RREADY RRESP AXI_03_RRESP RVALID AXI_03_RVALID WDATA AXI_03_WDATA WLAST AXI_03_WLAST WREADY AXI_03_WREADY WSTRB AXI_03_WSTRB WVALID AXI_03_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_03_8HI true ARADDR AXI_03_ARADDR ARBURST AXI_03_ARBURST ARID AXI_03_ARID ARLEN AXI_03_ARLEN ARREADY AXI_03_ARREADY ARSIZE AXI_03_ARSIZE ARVALID AXI_03_ARVALID AWADDR AXI_03_AWADDR AWBURST AXI_03_AWBURST AWID AXI_03_AWID AWLEN AXI_03_AWLEN AWREADY AXI_03_AWREADY AWSIZE AXI_03_AWSIZE AWVALID AXI_03_AWVALID BID AXI_03_BID BREADY AXI_03_BREADY BRESP AXI_03_BRESP BVALID AXI_03_BVALID RDATA AXI_03_RDATA RID AXI_03_RID RLAST AXI_03_RLAST RREADY AXI_03_RREADY RRESP AXI_03_RRESP RVALID AXI_03_RVALID WDATA AXI_03_WDATA WLAST AXI_03_WLAST WREADY AXI_03_WREADY WSTRB AXI_03_WSTRB WVALID AXI_03_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_03_RT_8HI true ARADDR AXI_03_ARADDR ARBURST AXI_03_ARBURST ARID AXI_03_ARID ARLEN AXI_03_ARLEN ARREADY AXI_03_ARREADY ARSIZE AXI_03_ARSIZE ARVALID AXI_03_ARVALID AWADDR AXI_03_AWADDR AWBURST AXI_03_AWBURST AWID AXI_03_AWID AWLEN AXI_03_AWLEN AWREADY AXI_03_AWREADY AWSIZE AXI_03_AWSIZE AWVALID AXI_03_AWVALID BID AXI_03_BID BREADY AXI_03_BREADY BRESP AXI_03_BRESP BVALID AXI_03_BVALID RDATA AXI_03_RDATA RID AXI_03_RID RLAST AXI_03_RLAST RREADY AXI_03_RREADY RRESP AXI_03_RRESP RVALID AXI_03_RVALID WDATA AXI_03_WDATA WLAST AXI_03_WLAST WREADY AXI_03_WREADY WSTRB AXI_03_WSTRB WVALID AXI_03_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_04 true CLK AXI_04_ACLK ASSOCIATED_BUSIF SAXI_04 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_04_RT true CLK AXI_04_ACLK ASSOCIATED_BUSIF SAXI_04_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_04_8HI true CLK AXI_04_ACLK ASSOCIATED_BUSIF SAXI_04_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_04_RT_8HI true CLK AXI_04_ACLK ASSOCIATED_BUSIF SAXI_04_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_04_N true RST AXI_04_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_04 true ARADDR AXI_04_ARADDR ARBURST AXI_04_ARBURST ARID AXI_04_ARID ARLEN AXI_04_ARLEN ARREADY AXI_04_ARREADY ARSIZE AXI_04_ARSIZE ARVALID AXI_04_ARVALID AWADDR AXI_04_AWADDR AWBURST AXI_04_AWBURST AWID AXI_04_AWID AWLEN AXI_04_AWLEN AWREADY AXI_04_AWREADY AWSIZE AXI_04_AWSIZE AWVALID AXI_04_AWVALID BID AXI_04_BID BREADY AXI_04_BREADY BRESP AXI_04_BRESP BVALID AXI_04_BVALID RDATA AXI_04_RDATA RID AXI_04_RID RLAST AXI_04_RLAST RREADY AXI_04_RREADY RRESP AXI_04_RRESP RVALID AXI_04_RVALID WDATA AXI_04_WDATA WLAST AXI_04_WLAST WREADY AXI_04_WREADY WSTRB AXI_04_WSTRB WVALID AXI_04_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_04_RT true ARADDR AXI_04_ARADDR ARBURST AXI_04_ARBURST ARID AXI_04_ARID ARLEN AXI_04_ARLEN ARREADY AXI_04_ARREADY ARSIZE AXI_04_ARSIZE ARVALID AXI_04_ARVALID AWADDR AXI_04_AWADDR AWBURST AXI_04_AWBURST AWID AXI_04_AWID AWLEN AXI_04_AWLEN AWREADY AXI_04_AWREADY AWSIZE AXI_04_AWSIZE AWVALID AXI_04_AWVALID BID AXI_04_BID BREADY AXI_04_BREADY BRESP AXI_04_BRESP BVALID AXI_04_BVALID RDATA AXI_04_RDATA RID AXI_04_RID RLAST AXI_04_RLAST RREADY AXI_04_RREADY RRESP AXI_04_RRESP RVALID AXI_04_RVALID WDATA AXI_04_WDATA WLAST AXI_04_WLAST WREADY AXI_04_WREADY WSTRB AXI_04_WSTRB WVALID AXI_04_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_04_8HI true ARADDR AXI_04_ARADDR ARBURST AXI_04_ARBURST ARID AXI_04_ARID ARLEN AXI_04_ARLEN ARREADY AXI_04_ARREADY ARSIZE AXI_04_ARSIZE ARVALID AXI_04_ARVALID AWADDR AXI_04_AWADDR AWBURST AXI_04_AWBURST AWID AXI_04_AWID AWLEN AXI_04_AWLEN AWREADY AXI_04_AWREADY AWSIZE AXI_04_AWSIZE AWVALID AXI_04_AWVALID BID AXI_04_BID BREADY AXI_04_BREADY BRESP AXI_04_BRESP BVALID AXI_04_BVALID RDATA AXI_04_RDATA RID AXI_04_RID RLAST AXI_04_RLAST RREADY AXI_04_RREADY RRESP AXI_04_RRESP RVALID AXI_04_RVALID WDATA AXI_04_WDATA WLAST AXI_04_WLAST WREADY AXI_04_WREADY WSTRB AXI_04_WSTRB WVALID AXI_04_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_04_RT_8HI true ARADDR AXI_04_ARADDR ARBURST AXI_04_ARBURST ARID AXI_04_ARID ARLEN AXI_04_ARLEN ARREADY AXI_04_ARREADY ARSIZE AXI_04_ARSIZE ARVALID AXI_04_ARVALID AWADDR AXI_04_AWADDR AWBURST AXI_04_AWBURST AWID AXI_04_AWID AWLEN AXI_04_AWLEN AWREADY AXI_04_AWREADY AWSIZE AXI_04_AWSIZE AWVALID AXI_04_AWVALID BID AXI_04_BID BREADY AXI_04_BREADY BRESP AXI_04_BRESP BVALID AXI_04_BVALID RDATA AXI_04_RDATA RID AXI_04_RID RLAST AXI_04_RLAST RREADY AXI_04_RREADY RRESP AXI_04_RRESP RVALID AXI_04_RVALID WDATA AXI_04_WDATA WLAST AXI_04_WLAST WREADY AXI_04_WREADY WSTRB AXI_04_WSTRB WVALID AXI_04_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_05 true CLK AXI_05_ACLK ASSOCIATED_BUSIF SAXI_05 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_05_RT true CLK AXI_05_ACLK ASSOCIATED_BUSIF SAXI_05_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_05_8HI true CLK AXI_05_ACLK ASSOCIATED_BUSIF SAXI_05_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_05_RT_8HI true CLK AXI_05_ACLK ASSOCIATED_BUSIF SAXI_05_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_05_N true RST AXI_05_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_05 true ARADDR AXI_05_ARADDR ARBURST AXI_05_ARBURST ARID AXI_05_ARID ARLEN AXI_05_ARLEN ARREADY AXI_05_ARREADY ARSIZE AXI_05_ARSIZE ARVALID AXI_05_ARVALID AWADDR AXI_05_AWADDR AWBURST AXI_05_AWBURST AWID AXI_05_AWID AWLEN AXI_05_AWLEN AWREADY AXI_05_AWREADY AWSIZE AXI_05_AWSIZE AWVALID AXI_05_AWVALID BID AXI_05_BID BREADY AXI_05_BREADY BRESP AXI_05_BRESP BVALID AXI_05_BVALID RDATA AXI_05_RDATA RID AXI_05_RID RLAST AXI_05_RLAST RREADY AXI_05_RREADY RRESP AXI_05_RRESP RVALID AXI_05_RVALID WDATA AXI_05_WDATA WLAST AXI_05_WLAST WREADY AXI_05_WREADY WSTRB AXI_05_WSTRB WVALID AXI_05_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_05_RT true ARADDR AXI_05_ARADDR ARBURST AXI_05_ARBURST ARID AXI_05_ARID ARLEN AXI_05_ARLEN ARREADY AXI_05_ARREADY ARSIZE AXI_05_ARSIZE ARVALID AXI_05_ARVALID AWADDR AXI_05_AWADDR AWBURST AXI_05_AWBURST AWID AXI_05_AWID AWLEN AXI_05_AWLEN AWREADY AXI_05_AWREADY AWSIZE AXI_05_AWSIZE AWVALID AXI_05_AWVALID BID AXI_05_BID BREADY AXI_05_BREADY BRESP AXI_05_BRESP BVALID AXI_05_BVALID RDATA AXI_05_RDATA RID AXI_05_RID RLAST AXI_05_RLAST RREADY AXI_05_RREADY RRESP AXI_05_RRESP RVALID AXI_05_RVALID WDATA AXI_05_WDATA WLAST AXI_05_WLAST WREADY AXI_05_WREADY WSTRB AXI_05_WSTRB WVALID AXI_05_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_05_8HI true ARADDR AXI_05_ARADDR ARBURST AXI_05_ARBURST ARID AXI_05_ARID ARLEN AXI_05_ARLEN ARREADY AXI_05_ARREADY ARSIZE AXI_05_ARSIZE ARVALID AXI_05_ARVALID AWADDR AXI_05_AWADDR AWBURST AXI_05_AWBURST AWID AXI_05_AWID AWLEN AXI_05_AWLEN AWREADY AXI_05_AWREADY AWSIZE AXI_05_AWSIZE AWVALID AXI_05_AWVALID BID AXI_05_BID BREADY AXI_05_BREADY BRESP AXI_05_BRESP BVALID AXI_05_BVALID RDATA AXI_05_RDATA RID AXI_05_RID RLAST AXI_05_RLAST RREADY AXI_05_RREADY RRESP AXI_05_RRESP RVALID AXI_05_RVALID WDATA AXI_05_WDATA WLAST AXI_05_WLAST WREADY AXI_05_WREADY WSTRB AXI_05_WSTRB WVALID AXI_05_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_05_RT_8HI true ARADDR AXI_05_ARADDR ARBURST AXI_05_ARBURST ARID AXI_05_ARID ARLEN AXI_05_ARLEN ARREADY AXI_05_ARREADY ARSIZE AXI_05_ARSIZE ARVALID AXI_05_ARVALID AWADDR AXI_05_AWADDR AWBURST AXI_05_AWBURST AWID AXI_05_AWID AWLEN AXI_05_AWLEN AWREADY AXI_05_AWREADY AWSIZE AXI_05_AWSIZE AWVALID AXI_05_AWVALID BID AXI_05_BID BREADY AXI_05_BREADY BRESP AXI_05_BRESP BVALID AXI_05_BVALID RDATA AXI_05_RDATA RID AXI_05_RID RLAST AXI_05_RLAST RREADY AXI_05_RREADY RRESP AXI_05_RRESP RVALID AXI_05_RVALID WDATA AXI_05_WDATA WLAST AXI_05_WLAST WREADY AXI_05_WREADY WSTRB AXI_05_WSTRB WVALID AXI_05_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_06 true CLK AXI_06_ACLK ASSOCIATED_BUSIF SAXI_06 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_06_RT true CLK AXI_06_ACLK ASSOCIATED_BUSIF SAXI_06_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_06_8HI true CLK AXI_06_ACLK ASSOCIATED_BUSIF SAXI_06_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_06_RT_8HI true CLK AXI_06_ACLK ASSOCIATED_BUSIF SAXI_06_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_06_N true RST AXI_06_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_06 true ARADDR AXI_06_ARADDR ARBURST AXI_06_ARBURST ARID AXI_06_ARID ARLEN AXI_06_ARLEN ARREADY AXI_06_ARREADY ARSIZE AXI_06_ARSIZE ARVALID AXI_06_ARVALID AWADDR AXI_06_AWADDR AWBURST AXI_06_AWBURST AWID AXI_06_AWID AWLEN AXI_06_AWLEN AWREADY AXI_06_AWREADY AWSIZE AXI_06_AWSIZE AWVALID AXI_06_AWVALID BID AXI_06_BID BREADY AXI_06_BREADY BRESP AXI_06_BRESP BVALID AXI_06_BVALID RDATA AXI_06_RDATA RID AXI_06_RID RLAST AXI_06_RLAST RREADY AXI_06_RREADY RRESP AXI_06_RRESP RVALID AXI_06_RVALID WDATA AXI_06_WDATA WLAST AXI_06_WLAST WREADY AXI_06_WREADY WSTRB AXI_06_WSTRB WVALID AXI_06_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_06_RT true ARADDR AXI_06_ARADDR ARBURST AXI_06_ARBURST ARID AXI_06_ARID ARLEN AXI_06_ARLEN ARREADY AXI_06_ARREADY ARSIZE AXI_06_ARSIZE ARVALID AXI_06_ARVALID AWADDR AXI_06_AWADDR AWBURST AXI_06_AWBURST AWID AXI_06_AWID AWLEN AXI_06_AWLEN AWREADY AXI_06_AWREADY AWSIZE AXI_06_AWSIZE AWVALID AXI_06_AWVALID BID AXI_06_BID BREADY AXI_06_BREADY BRESP AXI_06_BRESP BVALID AXI_06_BVALID RDATA AXI_06_RDATA RID AXI_06_RID RLAST AXI_06_RLAST RREADY AXI_06_RREADY RRESP AXI_06_RRESP RVALID AXI_06_RVALID WDATA AXI_06_WDATA WLAST AXI_06_WLAST WREADY AXI_06_WREADY WSTRB AXI_06_WSTRB WVALID AXI_06_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_06_8HI true ARADDR AXI_06_ARADDR ARBURST AXI_06_ARBURST ARID AXI_06_ARID ARLEN AXI_06_ARLEN ARREADY AXI_06_ARREADY ARSIZE AXI_06_ARSIZE ARVALID AXI_06_ARVALID AWADDR AXI_06_AWADDR AWBURST AXI_06_AWBURST AWID AXI_06_AWID AWLEN AXI_06_AWLEN AWREADY AXI_06_AWREADY AWSIZE AXI_06_AWSIZE AWVALID AXI_06_AWVALID BID AXI_06_BID BREADY AXI_06_BREADY BRESP AXI_06_BRESP BVALID AXI_06_BVALID RDATA AXI_06_RDATA RID AXI_06_RID RLAST AXI_06_RLAST RREADY AXI_06_RREADY RRESP AXI_06_RRESP RVALID AXI_06_RVALID WDATA AXI_06_WDATA WLAST AXI_06_WLAST WREADY AXI_06_WREADY WSTRB AXI_06_WSTRB WVALID AXI_06_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_06_RT_8HI true ARADDR AXI_06_ARADDR ARBURST AXI_06_ARBURST ARID AXI_06_ARID ARLEN AXI_06_ARLEN ARREADY AXI_06_ARREADY ARSIZE AXI_06_ARSIZE ARVALID AXI_06_ARVALID AWADDR AXI_06_AWADDR AWBURST AXI_06_AWBURST AWID AXI_06_AWID AWLEN AXI_06_AWLEN AWREADY AXI_06_AWREADY AWSIZE AXI_06_AWSIZE AWVALID AXI_06_AWVALID BID AXI_06_BID BREADY AXI_06_BREADY BRESP AXI_06_BRESP BVALID AXI_06_BVALID RDATA AXI_06_RDATA RID AXI_06_RID RLAST AXI_06_RLAST RREADY AXI_06_RREADY RRESP AXI_06_RRESP RVALID AXI_06_RVALID WDATA AXI_06_WDATA WLAST AXI_06_WLAST WREADY AXI_06_WREADY WSTRB AXI_06_WSTRB WVALID AXI_06_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_07 true CLK AXI_07_ACLK ASSOCIATED_BUSIF SAXI_07 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_07_RT true CLK AXI_07_ACLK ASSOCIATED_BUSIF SAXI_07_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_07_8HI true CLK AXI_07_ACLK ASSOCIATED_BUSIF SAXI_07_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_07_RT_8HI true CLK AXI_07_ACLK ASSOCIATED_BUSIF SAXI_07_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_07_N true RST AXI_07_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_07 true ARADDR AXI_07_ARADDR ARBURST AXI_07_ARBURST ARID AXI_07_ARID ARLEN AXI_07_ARLEN ARREADY AXI_07_ARREADY ARSIZE AXI_07_ARSIZE ARVALID AXI_07_ARVALID AWADDR AXI_07_AWADDR AWBURST AXI_07_AWBURST AWID AXI_07_AWID AWLEN AXI_07_AWLEN AWREADY AXI_07_AWREADY AWSIZE AXI_07_AWSIZE AWVALID AXI_07_AWVALID BID AXI_07_BID BREADY AXI_07_BREADY BRESP AXI_07_BRESP BVALID AXI_07_BVALID RDATA AXI_07_RDATA RID AXI_07_RID RLAST AXI_07_RLAST RREADY AXI_07_RREADY RRESP AXI_07_RRESP RVALID AXI_07_RVALID WDATA AXI_07_WDATA WLAST AXI_07_WLAST WREADY AXI_07_WREADY WSTRB AXI_07_WSTRB WVALID AXI_07_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_07_RT true ARADDR AXI_07_ARADDR ARBURST AXI_07_ARBURST ARID AXI_07_ARID ARLEN AXI_07_ARLEN ARREADY AXI_07_ARREADY ARSIZE AXI_07_ARSIZE ARVALID AXI_07_ARVALID AWADDR AXI_07_AWADDR AWBURST AXI_07_AWBURST AWID AXI_07_AWID AWLEN AXI_07_AWLEN AWREADY AXI_07_AWREADY AWSIZE AXI_07_AWSIZE AWVALID AXI_07_AWVALID BID AXI_07_BID BREADY AXI_07_BREADY BRESP AXI_07_BRESP BVALID AXI_07_BVALID RDATA AXI_07_RDATA RID AXI_07_RID RLAST AXI_07_RLAST RREADY AXI_07_RREADY RRESP AXI_07_RRESP RVALID AXI_07_RVALID WDATA AXI_07_WDATA WLAST AXI_07_WLAST WREADY AXI_07_WREADY WSTRB AXI_07_WSTRB WVALID AXI_07_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_07_8HI true ARADDR AXI_07_ARADDR ARBURST AXI_07_ARBURST ARID AXI_07_ARID ARLEN AXI_07_ARLEN ARREADY AXI_07_ARREADY ARSIZE AXI_07_ARSIZE ARVALID AXI_07_ARVALID AWADDR AXI_07_AWADDR AWBURST AXI_07_AWBURST AWID AXI_07_AWID AWLEN AXI_07_AWLEN AWREADY AXI_07_AWREADY AWSIZE AXI_07_AWSIZE AWVALID AXI_07_AWVALID BID AXI_07_BID BREADY AXI_07_BREADY BRESP AXI_07_BRESP BVALID AXI_07_BVALID RDATA AXI_07_RDATA RID AXI_07_RID RLAST AXI_07_RLAST RREADY AXI_07_RREADY RRESP AXI_07_RRESP RVALID AXI_07_RVALID WDATA AXI_07_WDATA WLAST AXI_07_WLAST WREADY AXI_07_WREADY WSTRB AXI_07_WSTRB WVALID AXI_07_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_07_RT_8HI true ARADDR AXI_07_ARADDR ARBURST AXI_07_ARBURST ARID AXI_07_ARID ARLEN AXI_07_ARLEN ARREADY AXI_07_ARREADY ARSIZE AXI_07_ARSIZE ARVALID AXI_07_ARVALID AWADDR AXI_07_AWADDR AWBURST AXI_07_AWBURST AWID AXI_07_AWID AWLEN AXI_07_AWLEN AWREADY AXI_07_AWREADY AWSIZE AXI_07_AWSIZE AWVALID AXI_07_AWVALID BID AXI_07_BID BREADY AXI_07_BREADY BRESP AXI_07_BRESP BVALID AXI_07_BVALID RDATA AXI_07_RDATA RID AXI_07_RID RLAST AXI_07_RLAST RREADY AXI_07_RREADY RRESP AXI_07_RRESP RVALID AXI_07_RVALID WDATA AXI_07_WDATA WLAST AXI_07_WLAST WREADY AXI_07_WREADY WSTRB AXI_07_WSTRB WVALID AXI_07_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_08 true CLK AXI_08_ACLK ASSOCIATED_BUSIF SAXI_08 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_08_RT true CLK AXI_08_ACLK ASSOCIATED_BUSIF SAXI_08_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_08_8HI true CLK AXI_08_ACLK ASSOCIATED_BUSIF SAXI_08_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_08_RT_8HI true CLK AXI_08_ACLK ASSOCIATED_BUSIF SAXI_08_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_08_N true RST AXI_08_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_08 true ARADDR AXI_08_ARADDR ARBURST AXI_08_ARBURST ARID AXI_08_ARID ARLEN AXI_08_ARLEN ARREADY AXI_08_ARREADY ARSIZE AXI_08_ARSIZE ARVALID AXI_08_ARVALID AWADDR AXI_08_AWADDR AWBURST AXI_08_AWBURST AWID AXI_08_AWID AWLEN AXI_08_AWLEN AWREADY AXI_08_AWREADY AWSIZE AXI_08_AWSIZE AWVALID AXI_08_AWVALID BID AXI_08_BID BREADY AXI_08_BREADY BRESP AXI_08_BRESP BVALID AXI_08_BVALID RDATA AXI_08_RDATA RID AXI_08_RID RLAST AXI_08_RLAST RREADY AXI_08_RREADY RRESP AXI_08_RRESP RVALID AXI_08_RVALID WDATA AXI_08_WDATA WLAST AXI_08_WLAST WREADY AXI_08_WREADY WSTRB AXI_08_WSTRB WVALID AXI_08_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_08_RT true ARADDR AXI_08_ARADDR ARBURST AXI_08_ARBURST ARID AXI_08_ARID ARLEN AXI_08_ARLEN ARREADY AXI_08_ARREADY ARSIZE AXI_08_ARSIZE ARVALID AXI_08_ARVALID AWADDR AXI_08_AWADDR AWBURST AXI_08_AWBURST AWID AXI_08_AWID AWLEN AXI_08_AWLEN AWREADY AXI_08_AWREADY AWSIZE AXI_08_AWSIZE AWVALID AXI_08_AWVALID BID AXI_08_BID BREADY AXI_08_BREADY BRESP AXI_08_BRESP BVALID AXI_08_BVALID RDATA AXI_08_RDATA RID AXI_08_RID RLAST AXI_08_RLAST RREADY AXI_08_RREADY RRESP AXI_08_RRESP RVALID AXI_08_RVALID WDATA AXI_08_WDATA WLAST AXI_08_WLAST WREADY AXI_08_WREADY WSTRB AXI_08_WSTRB WVALID AXI_08_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_08_8HI true ARADDR AXI_08_ARADDR ARBURST AXI_08_ARBURST ARID AXI_08_ARID ARLEN AXI_08_ARLEN ARREADY AXI_08_ARREADY ARSIZE AXI_08_ARSIZE ARVALID AXI_08_ARVALID AWADDR AXI_08_AWADDR AWBURST AXI_08_AWBURST AWID AXI_08_AWID AWLEN AXI_08_AWLEN AWREADY AXI_08_AWREADY AWSIZE AXI_08_AWSIZE AWVALID AXI_08_AWVALID BID AXI_08_BID BREADY AXI_08_BREADY BRESP AXI_08_BRESP BVALID AXI_08_BVALID RDATA AXI_08_RDATA RID AXI_08_RID RLAST AXI_08_RLAST RREADY AXI_08_RREADY RRESP AXI_08_RRESP RVALID AXI_08_RVALID WDATA AXI_08_WDATA WLAST AXI_08_WLAST WREADY AXI_08_WREADY WSTRB AXI_08_WSTRB WVALID AXI_08_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_08_RT_8HI true ARADDR AXI_08_ARADDR ARBURST AXI_08_ARBURST ARID AXI_08_ARID ARLEN AXI_08_ARLEN ARREADY AXI_08_ARREADY ARSIZE AXI_08_ARSIZE ARVALID AXI_08_ARVALID AWADDR AXI_08_AWADDR AWBURST AXI_08_AWBURST AWID AXI_08_AWID AWLEN AXI_08_AWLEN AWREADY AXI_08_AWREADY AWSIZE AXI_08_AWSIZE AWVALID AXI_08_AWVALID BID AXI_08_BID BREADY AXI_08_BREADY BRESP AXI_08_BRESP BVALID AXI_08_BVALID RDATA AXI_08_RDATA RID AXI_08_RID RLAST AXI_08_RLAST RREADY AXI_08_RREADY RRESP AXI_08_RRESP RVALID AXI_08_RVALID WDATA AXI_08_WDATA WLAST AXI_08_WLAST WREADY AXI_08_WREADY WSTRB AXI_08_WSTRB WVALID AXI_08_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_09 true CLK AXI_09_ACLK ASSOCIATED_BUSIF SAXI_09 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_09_RT true CLK AXI_09_ACLK ASSOCIATED_BUSIF SAXI_09_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_09_8HI true CLK AXI_09_ACLK ASSOCIATED_BUSIF SAXI_09_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_09_RT_8HI true CLK AXI_09_ACLK ASSOCIATED_BUSIF SAXI_09_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_09_N true RST AXI_09_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_09 true ARADDR AXI_09_ARADDR ARBURST AXI_09_ARBURST ARID AXI_09_ARID ARLEN AXI_09_ARLEN ARREADY AXI_09_ARREADY ARSIZE AXI_09_ARSIZE ARVALID AXI_09_ARVALID AWADDR AXI_09_AWADDR AWBURST AXI_09_AWBURST AWID AXI_09_AWID AWLEN AXI_09_AWLEN AWREADY AXI_09_AWREADY AWSIZE AXI_09_AWSIZE AWVALID AXI_09_AWVALID BID AXI_09_BID BREADY AXI_09_BREADY BRESP AXI_09_BRESP BVALID AXI_09_BVALID RDATA AXI_09_RDATA RID AXI_09_RID RLAST AXI_09_RLAST RREADY AXI_09_RREADY RRESP AXI_09_RRESP RVALID AXI_09_RVALID WDATA AXI_09_WDATA WLAST AXI_09_WLAST WREADY AXI_09_WREADY WSTRB AXI_09_WSTRB WVALID AXI_09_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_09_RT true ARADDR AXI_09_ARADDR ARBURST AXI_09_ARBURST ARID AXI_09_ARID ARLEN AXI_09_ARLEN ARREADY AXI_09_ARREADY ARSIZE AXI_09_ARSIZE ARVALID AXI_09_ARVALID AWADDR AXI_09_AWADDR AWBURST AXI_09_AWBURST AWID AXI_09_AWID AWLEN AXI_09_AWLEN AWREADY AXI_09_AWREADY AWSIZE AXI_09_AWSIZE AWVALID AXI_09_AWVALID BID AXI_09_BID BREADY AXI_09_BREADY BRESP AXI_09_BRESP BVALID AXI_09_BVALID RDATA AXI_09_RDATA RID AXI_09_RID RLAST AXI_09_RLAST RREADY AXI_09_RREADY RRESP AXI_09_RRESP RVALID AXI_09_RVALID WDATA AXI_09_WDATA WLAST AXI_09_WLAST WREADY AXI_09_WREADY WSTRB AXI_09_WSTRB WVALID AXI_09_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_09_8HI true ARADDR AXI_09_ARADDR ARBURST AXI_09_ARBURST ARID AXI_09_ARID ARLEN AXI_09_ARLEN ARREADY AXI_09_ARREADY ARSIZE AXI_09_ARSIZE ARVALID AXI_09_ARVALID AWADDR AXI_09_AWADDR AWBURST AXI_09_AWBURST AWID AXI_09_AWID AWLEN AXI_09_AWLEN AWREADY AXI_09_AWREADY AWSIZE AXI_09_AWSIZE AWVALID AXI_09_AWVALID BID AXI_09_BID BREADY AXI_09_BREADY BRESP AXI_09_BRESP BVALID AXI_09_BVALID RDATA AXI_09_RDATA RID AXI_09_RID RLAST AXI_09_RLAST RREADY AXI_09_RREADY RRESP AXI_09_RRESP RVALID AXI_09_RVALID WDATA AXI_09_WDATA WLAST AXI_09_WLAST WREADY AXI_09_WREADY WSTRB AXI_09_WSTRB WVALID AXI_09_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_09_RT_8HI true ARADDR AXI_09_ARADDR ARBURST AXI_09_ARBURST ARID AXI_09_ARID ARLEN AXI_09_ARLEN ARREADY AXI_09_ARREADY ARSIZE AXI_09_ARSIZE ARVALID AXI_09_ARVALID AWADDR AXI_09_AWADDR AWBURST AXI_09_AWBURST AWID AXI_09_AWID AWLEN AXI_09_AWLEN AWREADY AXI_09_AWREADY AWSIZE AXI_09_AWSIZE AWVALID AXI_09_AWVALID BID AXI_09_BID BREADY AXI_09_BREADY BRESP AXI_09_BRESP BVALID AXI_09_BVALID RDATA AXI_09_RDATA RID AXI_09_RID RLAST AXI_09_RLAST RREADY AXI_09_RREADY RRESP AXI_09_RRESP RVALID AXI_09_RVALID WDATA AXI_09_WDATA WLAST AXI_09_WLAST WREADY AXI_09_WREADY WSTRB AXI_09_WSTRB WVALID AXI_09_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_10 true CLK AXI_10_ACLK ASSOCIATED_BUSIF SAXI_10 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_10_RT true CLK AXI_10_ACLK ASSOCIATED_BUSIF SAXI_10_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_10_8HI true CLK AXI_10_ACLK ASSOCIATED_BUSIF SAXI_10_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_10_RT_8HI true CLK AXI_10_ACLK ASSOCIATED_BUSIF SAXI_10_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_10_N true RST AXI_10_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_10 true ARADDR AXI_10_ARADDR ARBURST AXI_10_ARBURST ARID AXI_10_ARID ARLEN AXI_10_ARLEN ARREADY AXI_10_ARREADY ARSIZE AXI_10_ARSIZE ARVALID AXI_10_ARVALID AWADDR AXI_10_AWADDR AWBURST AXI_10_AWBURST AWID AXI_10_AWID AWLEN AXI_10_AWLEN AWREADY AXI_10_AWREADY AWSIZE AXI_10_AWSIZE AWVALID AXI_10_AWVALID BID AXI_10_BID BREADY AXI_10_BREADY BRESP AXI_10_BRESP BVALID AXI_10_BVALID RDATA AXI_10_RDATA RID AXI_10_RID RLAST AXI_10_RLAST RREADY AXI_10_RREADY RRESP AXI_10_RRESP RVALID AXI_10_RVALID WDATA AXI_10_WDATA WLAST AXI_10_WLAST WREADY AXI_10_WREADY WSTRB AXI_10_WSTRB WVALID AXI_10_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_10_RT true ARADDR AXI_10_ARADDR ARBURST AXI_10_ARBURST ARID AXI_10_ARID ARLEN AXI_10_ARLEN ARREADY AXI_10_ARREADY ARSIZE AXI_10_ARSIZE ARVALID AXI_10_ARVALID AWADDR AXI_10_AWADDR AWBURST AXI_10_AWBURST AWID AXI_10_AWID AWLEN AXI_10_AWLEN AWREADY AXI_10_AWREADY AWSIZE AXI_10_AWSIZE AWVALID AXI_10_AWVALID BID AXI_10_BID BREADY AXI_10_BREADY BRESP AXI_10_BRESP BVALID AXI_10_BVALID RDATA AXI_10_RDATA RID AXI_10_RID RLAST AXI_10_RLAST RREADY AXI_10_RREADY RRESP AXI_10_RRESP RVALID AXI_10_RVALID WDATA AXI_10_WDATA WLAST AXI_10_WLAST WREADY AXI_10_WREADY WSTRB AXI_10_WSTRB WVALID AXI_10_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_10_8HI true ARADDR AXI_10_ARADDR ARBURST AXI_10_ARBURST ARID AXI_10_ARID ARLEN AXI_10_ARLEN ARREADY AXI_10_ARREADY ARSIZE AXI_10_ARSIZE ARVALID AXI_10_ARVALID AWADDR AXI_10_AWADDR AWBURST AXI_10_AWBURST AWID AXI_10_AWID AWLEN AXI_10_AWLEN AWREADY AXI_10_AWREADY AWSIZE AXI_10_AWSIZE AWVALID AXI_10_AWVALID BID AXI_10_BID BREADY AXI_10_BREADY BRESP AXI_10_BRESP BVALID AXI_10_BVALID RDATA AXI_10_RDATA RID AXI_10_RID RLAST AXI_10_RLAST RREADY AXI_10_RREADY RRESP AXI_10_RRESP RVALID AXI_10_RVALID WDATA AXI_10_WDATA WLAST AXI_10_WLAST WREADY AXI_10_WREADY WSTRB AXI_10_WSTRB WVALID AXI_10_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_10_RT_8HI true ARADDR AXI_10_ARADDR ARBURST AXI_10_ARBURST ARID AXI_10_ARID ARLEN AXI_10_ARLEN ARREADY AXI_10_ARREADY ARSIZE AXI_10_ARSIZE ARVALID AXI_10_ARVALID AWADDR AXI_10_AWADDR AWBURST AXI_10_AWBURST AWID AXI_10_AWID AWLEN AXI_10_AWLEN AWREADY AXI_10_AWREADY AWSIZE AXI_10_AWSIZE AWVALID AXI_10_AWVALID BID AXI_10_BID BREADY AXI_10_BREADY BRESP AXI_10_BRESP BVALID AXI_10_BVALID RDATA AXI_10_RDATA RID AXI_10_RID RLAST AXI_10_RLAST RREADY AXI_10_RREADY RRESP AXI_10_RRESP RVALID AXI_10_RVALID WDATA AXI_10_WDATA WLAST AXI_10_WLAST WREADY AXI_10_WREADY WSTRB AXI_10_WSTRB WVALID AXI_10_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_11 true CLK AXI_11_ACLK ASSOCIATED_BUSIF SAXI_11 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_11_RT true CLK AXI_11_ACLK ASSOCIATED_BUSIF SAXI_11_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_11_8HI true CLK AXI_11_ACLK ASSOCIATED_BUSIF SAXI_11_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_11_RT_8HI true CLK AXI_11_ACLK ASSOCIATED_BUSIF SAXI_11_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_11_N true RST AXI_11_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_11 true ARADDR AXI_11_ARADDR ARBURST AXI_11_ARBURST ARID AXI_11_ARID ARLEN AXI_11_ARLEN ARREADY AXI_11_ARREADY ARSIZE AXI_11_ARSIZE ARVALID AXI_11_ARVALID AWADDR AXI_11_AWADDR AWBURST AXI_11_AWBURST AWID AXI_11_AWID AWLEN AXI_11_AWLEN AWREADY AXI_11_AWREADY AWSIZE AXI_11_AWSIZE AWVALID AXI_11_AWVALID BID AXI_11_BID BREADY AXI_11_BREADY BRESP AXI_11_BRESP BVALID AXI_11_BVALID RDATA AXI_11_RDATA RID AXI_11_RID RLAST AXI_11_RLAST RREADY AXI_11_RREADY RRESP AXI_11_RRESP RVALID AXI_11_RVALID WDATA AXI_11_WDATA WLAST AXI_11_WLAST WREADY AXI_11_WREADY WSTRB AXI_11_WSTRB WVALID AXI_11_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_11_RT true ARADDR AXI_11_ARADDR ARBURST AXI_11_ARBURST ARID AXI_11_ARID ARLEN AXI_11_ARLEN ARREADY AXI_11_ARREADY ARSIZE AXI_11_ARSIZE ARVALID AXI_11_ARVALID AWADDR AXI_11_AWADDR AWBURST AXI_11_AWBURST AWID AXI_11_AWID AWLEN AXI_11_AWLEN AWREADY AXI_11_AWREADY AWSIZE AXI_11_AWSIZE AWVALID AXI_11_AWVALID BID AXI_11_BID BREADY AXI_11_BREADY BRESP AXI_11_BRESP BVALID AXI_11_BVALID RDATA AXI_11_RDATA RID AXI_11_RID RLAST AXI_11_RLAST RREADY AXI_11_RREADY RRESP AXI_11_RRESP RVALID AXI_11_RVALID WDATA AXI_11_WDATA WLAST AXI_11_WLAST WREADY AXI_11_WREADY WSTRB AXI_11_WSTRB WVALID AXI_11_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_11_8HI true ARADDR AXI_11_ARADDR ARBURST AXI_11_ARBURST ARID AXI_11_ARID ARLEN AXI_11_ARLEN ARREADY AXI_11_ARREADY ARSIZE AXI_11_ARSIZE ARVALID AXI_11_ARVALID AWADDR AXI_11_AWADDR AWBURST AXI_11_AWBURST AWID AXI_11_AWID AWLEN AXI_11_AWLEN AWREADY AXI_11_AWREADY AWSIZE AXI_11_AWSIZE AWVALID AXI_11_AWVALID BID AXI_11_BID BREADY AXI_11_BREADY BRESP AXI_11_BRESP BVALID AXI_11_BVALID RDATA AXI_11_RDATA RID AXI_11_RID RLAST AXI_11_RLAST RREADY AXI_11_RREADY RRESP AXI_11_RRESP RVALID AXI_11_RVALID WDATA AXI_11_WDATA WLAST AXI_11_WLAST WREADY AXI_11_WREADY WSTRB AXI_11_WSTRB WVALID AXI_11_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_11_RT_8HI true ARADDR AXI_11_ARADDR ARBURST AXI_11_ARBURST ARID AXI_11_ARID ARLEN AXI_11_ARLEN ARREADY AXI_11_ARREADY ARSIZE AXI_11_ARSIZE ARVALID AXI_11_ARVALID AWADDR AXI_11_AWADDR AWBURST AXI_11_AWBURST AWID AXI_11_AWID AWLEN AXI_11_AWLEN AWREADY AXI_11_AWREADY AWSIZE AXI_11_AWSIZE AWVALID AXI_11_AWVALID BID AXI_11_BID BREADY AXI_11_BREADY BRESP AXI_11_BRESP BVALID AXI_11_BVALID RDATA AXI_11_RDATA RID AXI_11_RID RLAST AXI_11_RLAST RREADY AXI_11_RREADY RRESP AXI_11_RRESP RVALID AXI_11_RVALID WDATA AXI_11_WDATA WLAST AXI_11_WLAST WREADY AXI_11_WREADY WSTRB AXI_11_WSTRB WVALID AXI_11_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_12 true CLK AXI_12_ACLK ASSOCIATED_BUSIF SAXI_12 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_12_RT true CLK AXI_12_ACLK ASSOCIATED_BUSIF SAXI_12_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_12_8HI true CLK AXI_12_ACLK ASSOCIATED_BUSIF SAXI_12_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_12_RT_8HI true CLK AXI_12_ACLK ASSOCIATED_BUSIF SAXI_12_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_12_N true RST AXI_12_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_12 true ARADDR AXI_12_ARADDR ARBURST AXI_12_ARBURST ARID AXI_12_ARID ARLEN AXI_12_ARLEN ARREADY AXI_12_ARREADY ARSIZE AXI_12_ARSIZE ARVALID AXI_12_ARVALID AWADDR AXI_12_AWADDR AWBURST AXI_12_AWBURST AWID AXI_12_AWID AWLEN AXI_12_AWLEN AWREADY AXI_12_AWREADY AWSIZE AXI_12_AWSIZE AWVALID AXI_12_AWVALID BID AXI_12_BID BREADY AXI_12_BREADY BRESP AXI_12_BRESP BVALID AXI_12_BVALID RDATA AXI_12_RDATA RID AXI_12_RID RLAST AXI_12_RLAST RREADY AXI_12_RREADY RRESP AXI_12_RRESP RVALID AXI_12_RVALID WDATA AXI_12_WDATA WLAST AXI_12_WLAST WREADY AXI_12_WREADY WSTRB AXI_12_WSTRB WVALID AXI_12_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_12_RT true ARADDR AXI_12_ARADDR ARBURST AXI_12_ARBURST ARID AXI_12_ARID ARLEN AXI_12_ARLEN ARREADY AXI_12_ARREADY ARSIZE AXI_12_ARSIZE ARVALID AXI_12_ARVALID AWADDR AXI_12_AWADDR AWBURST AXI_12_AWBURST AWID AXI_12_AWID AWLEN AXI_12_AWLEN AWREADY AXI_12_AWREADY AWSIZE AXI_12_AWSIZE AWVALID AXI_12_AWVALID BID AXI_12_BID BREADY AXI_12_BREADY BRESP AXI_12_BRESP BVALID AXI_12_BVALID RDATA AXI_12_RDATA RID AXI_12_RID RLAST AXI_12_RLAST RREADY AXI_12_RREADY RRESP AXI_12_RRESP RVALID AXI_12_RVALID WDATA AXI_12_WDATA WLAST AXI_12_WLAST WREADY AXI_12_WREADY WSTRB AXI_12_WSTRB WVALID AXI_12_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_12_8HI true ARADDR AXI_12_ARADDR ARBURST AXI_12_ARBURST ARID AXI_12_ARID ARLEN AXI_12_ARLEN ARREADY AXI_12_ARREADY ARSIZE AXI_12_ARSIZE ARVALID AXI_12_ARVALID AWADDR AXI_12_AWADDR AWBURST AXI_12_AWBURST AWID AXI_12_AWID AWLEN AXI_12_AWLEN AWREADY AXI_12_AWREADY AWSIZE AXI_12_AWSIZE AWVALID AXI_12_AWVALID BID AXI_12_BID BREADY AXI_12_BREADY BRESP AXI_12_BRESP BVALID AXI_12_BVALID RDATA AXI_12_RDATA RID AXI_12_RID RLAST AXI_12_RLAST RREADY AXI_12_RREADY RRESP AXI_12_RRESP RVALID AXI_12_RVALID WDATA AXI_12_WDATA WLAST AXI_12_WLAST WREADY AXI_12_WREADY WSTRB AXI_12_WSTRB WVALID AXI_12_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_12_RT_8HI true ARADDR AXI_12_ARADDR ARBURST AXI_12_ARBURST ARID AXI_12_ARID ARLEN AXI_12_ARLEN ARREADY AXI_12_ARREADY ARSIZE AXI_12_ARSIZE ARVALID AXI_12_ARVALID AWADDR AXI_12_AWADDR AWBURST AXI_12_AWBURST AWID AXI_12_AWID AWLEN AXI_12_AWLEN AWREADY AXI_12_AWREADY AWSIZE AXI_12_AWSIZE AWVALID AXI_12_AWVALID BID AXI_12_BID BREADY AXI_12_BREADY BRESP AXI_12_BRESP BVALID AXI_12_BVALID RDATA AXI_12_RDATA RID AXI_12_RID RLAST AXI_12_RLAST RREADY AXI_12_RREADY RRESP AXI_12_RRESP RVALID AXI_12_RVALID WDATA AXI_12_WDATA WLAST AXI_12_WLAST WREADY AXI_12_WREADY WSTRB AXI_12_WSTRB WVALID AXI_12_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_13 true CLK AXI_13_ACLK ASSOCIATED_BUSIF SAXI_13 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_13_RT true CLK AXI_13_ACLK ASSOCIATED_BUSIF SAXI_13_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_13_8HI true CLK AXI_13_ACLK ASSOCIATED_BUSIF SAXI_13_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_13_RT_8HI true CLK AXI_13_ACLK ASSOCIATED_BUSIF SAXI_13_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_13_N true RST AXI_13_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_13 true ARADDR AXI_13_ARADDR ARBURST AXI_13_ARBURST ARID AXI_13_ARID ARLEN AXI_13_ARLEN ARREADY AXI_13_ARREADY ARSIZE AXI_13_ARSIZE ARVALID AXI_13_ARVALID AWADDR AXI_13_AWADDR AWBURST AXI_13_AWBURST AWID AXI_13_AWID AWLEN AXI_13_AWLEN AWREADY AXI_13_AWREADY AWSIZE AXI_13_AWSIZE AWVALID AXI_13_AWVALID BID AXI_13_BID BREADY AXI_13_BREADY BRESP AXI_13_BRESP BVALID AXI_13_BVALID RDATA AXI_13_RDATA RID AXI_13_RID RLAST AXI_13_RLAST RREADY AXI_13_RREADY RRESP AXI_13_RRESP RVALID AXI_13_RVALID WDATA AXI_13_WDATA WLAST AXI_13_WLAST WREADY AXI_13_WREADY WSTRB AXI_13_WSTRB WVALID AXI_13_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_13_RT true ARADDR AXI_13_ARADDR ARBURST AXI_13_ARBURST ARID AXI_13_ARID ARLEN AXI_13_ARLEN ARREADY AXI_13_ARREADY ARSIZE AXI_13_ARSIZE ARVALID AXI_13_ARVALID AWADDR AXI_13_AWADDR AWBURST AXI_13_AWBURST AWID AXI_13_AWID AWLEN AXI_13_AWLEN AWREADY AXI_13_AWREADY AWSIZE AXI_13_AWSIZE AWVALID AXI_13_AWVALID BID AXI_13_BID BREADY AXI_13_BREADY BRESP AXI_13_BRESP BVALID AXI_13_BVALID RDATA AXI_13_RDATA RID AXI_13_RID RLAST AXI_13_RLAST RREADY AXI_13_RREADY RRESP AXI_13_RRESP RVALID AXI_13_RVALID WDATA AXI_13_WDATA WLAST AXI_13_WLAST WREADY AXI_13_WREADY WSTRB AXI_13_WSTRB WVALID AXI_13_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_13_8HI true ARADDR AXI_13_ARADDR ARBURST AXI_13_ARBURST ARID AXI_13_ARID ARLEN AXI_13_ARLEN ARREADY AXI_13_ARREADY ARSIZE AXI_13_ARSIZE ARVALID AXI_13_ARVALID AWADDR AXI_13_AWADDR AWBURST AXI_13_AWBURST AWID AXI_13_AWID AWLEN AXI_13_AWLEN AWREADY AXI_13_AWREADY AWSIZE AXI_13_AWSIZE AWVALID AXI_13_AWVALID BID AXI_13_BID BREADY AXI_13_BREADY BRESP AXI_13_BRESP BVALID AXI_13_BVALID RDATA AXI_13_RDATA RID AXI_13_RID RLAST AXI_13_RLAST RREADY AXI_13_RREADY RRESP AXI_13_RRESP RVALID AXI_13_RVALID WDATA AXI_13_WDATA WLAST AXI_13_WLAST WREADY AXI_13_WREADY WSTRB AXI_13_WSTRB WVALID AXI_13_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_13_RT_8HI true ARADDR AXI_13_ARADDR ARBURST AXI_13_ARBURST ARID AXI_13_ARID ARLEN AXI_13_ARLEN ARREADY AXI_13_ARREADY ARSIZE AXI_13_ARSIZE ARVALID AXI_13_ARVALID AWADDR AXI_13_AWADDR AWBURST AXI_13_AWBURST AWID AXI_13_AWID AWLEN AXI_13_AWLEN AWREADY AXI_13_AWREADY AWSIZE AXI_13_AWSIZE AWVALID AXI_13_AWVALID BID AXI_13_BID BREADY AXI_13_BREADY BRESP AXI_13_BRESP BVALID AXI_13_BVALID RDATA AXI_13_RDATA RID AXI_13_RID RLAST AXI_13_RLAST RREADY AXI_13_RREADY RRESP AXI_13_RRESP RVALID AXI_13_RVALID WDATA AXI_13_WDATA WLAST AXI_13_WLAST WREADY AXI_13_WREADY WSTRB AXI_13_WSTRB WVALID AXI_13_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_14 true CLK AXI_14_ACLK ASSOCIATED_BUSIF SAXI_14 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_14_RT true CLK AXI_14_ACLK ASSOCIATED_BUSIF SAXI_14_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_14_8HI true CLK AXI_14_ACLK ASSOCIATED_BUSIF SAXI_14_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_14_RT_8HI true CLK AXI_14_ACLK ASSOCIATED_BUSIF SAXI_14_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_14_N true RST AXI_14_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_14 true ARADDR AXI_14_ARADDR ARBURST AXI_14_ARBURST ARID AXI_14_ARID ARLEN AXI_14_ARLEN ARREADY AXI_14_ARREADY ARSIZE AXI_14_ARSIZE ARVALID AXI_14_ARVALID AWADDR AXI_14_AWADDR AWBURST AXI_14_AWBURST AWID AXI_14_AWID AWLEN AXI_14_AWLEN AWREADY AXI_14_AWREADY AWSIZE AXI_14_AWSIZE AWVALID AXI_14_AWVALID BID AXI_14_BID BREADY AXI_14_BREADY BRESP AXI_14_BRESP BVALID AXI_14_BVALID RDATA AXI_14_RDATA RID AXI_14_RID RLAST AXI_14_RLAST RREADY AXI_14_RREADY RRESP AXI_14_RRESP RVALID AXI_14_RVALID WDATA AXI_14_WDATA WLAST AXI_14_WLAST WREADY AXI_14_WREADY WSTRB AXI_14_WSTRB WVALID AXI_14_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_14_RT true ARADDR AXI_14_ARADDR ARBURST AXI_14_ARBURST ARID AXI_14_ARID ARLEN AXI_14_ARLEN ARREADY AXI_14_ARREADY ARSIZE AXI_14_ARSIZE ARVALID AXI_14_ARVALID AWADDR AXI_14_AWADDR AWBURST AXI_14_AWBURST AWID AXI_14_AWID AWLEN AXI_14_AWLEN AWREADY AXI_14_AWREADY AWSIZE AXI_14_AWSIZE AWVALID AXI_14_AWVALID BID AXI_14_BID BREADY AXI_14_BREADY BRESP AXI_14_BRESP BVALID AXI_14_BVALID RDATA AXI_14_RDATA RID AXI_14_RID RLAST AXI_14_RLAST RREADY AXI_14_RREADY RRESP AXI_14_RRESP RVALID AXI_14_RVALID WDATA AXI_14_WDATA WLAST AXI_14_WLAST WREADY AXI_14_WREADY WSTRB AXI_14_WSTRB WVALID AXI_14_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_14_8HI true ARADDR AXI_14_ARADDR ARBURST AXI_14_ARBURST ARID AXI_14_ARID ARLEN AXI_14_ARLEN ARREADY AXI_14_ARREADY ARSIZE AXI_14_ARSIZE ARVALID AXI_14_ARVALID AWADDR AXI_14_AWADDR AWBURST AXI_14_AWBURST AWID AXI_14_AWID AWLEN AXI_14_AWLEN AWREADY AXI_14_AWREADY AWSIZE AXI_14_AWSIZE AWVALID AXI_14_AWVALID BID AXI_14_BID BREADY AXI_14_BREADY BRESP AXI_14_BRESP BVALID AXI_14_BVALID RDATA AXI_14_RDATA RID AXI_14_RID RLAST AXI_14_RLAST RREADY AXI_14_RREADY RRESP AXI_14_RRESP RVALID AXI_14_RVALID WDATA AXI_14_WDATA WLAST AXI_14_WLAST WREADY AXI_14_WREADY WSTRB AXI_14_WSTRB WVALID AXI_14_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_14_RT_8HI true ARADDR AXI_14_ARADDR ARBURST AXI_14_ARBURST ARID AXI_14_ARID ARLEN AXI_14_ARLEN ARREADY AXI_14_ARREADY ARSIZE AXI_14_ARSIZE ARVALID AXI_14_ARVALID AWADDR AXI_14_AWADDR AWBURST AXI_14_AWBURST AWID AXI_14_AWID AWLEN AXI_14_AWLEN AWREADY AXI_14_AWREADY AWSIZE AXI_14_AWSIZE AWVALID AXI_14_AWVALID BID AXI_14_BID BREADY AXI_14_BREADY BRESP AXI_14_BRESP BVALID AXI_14_BVALID RDATA AXI_14_RDATA RID AXI_14_RID RLAST AXI_14_RLAST RREADY AXI_14_RREADY RRESP AXI_14_RRESP RVALID AXI_14_RVALID WDATA AXI_14_WDATA WLAST AXI_14_WLAST WREADY AXI_14_WREADY WSTRB AXI_14_WSTRB WVALID AXI_14_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_15 true CLK AXI_15_ACLK ASSOCIATED_BUSIF SAXI_15 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_15_RT true CLK AXI_15_ACLK ASSOCIATED_BUSIF SAXI_15_RT FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_15_8HI true CLK AXI_15_ACLK ASSOCIATED_BUSIF SAXI_15_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_15_RT_8HI true CLK AXI_15_ACLK ASSOCIATED_BUSIF SAXI_15_RT_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_15_N true RST AXI_15_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_15 true ARADDR AXI_15_ARADDR ARBURST AXI_15_ARBURST ARID AXI_15_ARID ARLEN AXI_15_ARLEN ARREADY AXI_15_ARREADY ARSIZE AXI_15_ARSIZE ARVALID AXI_15_ARVALID AWADDR AXI_15_AWADDR AWBURST AXI_15_AWBURST AWID AXI_15_AWID AWLEN AXI_15_AWLEN AWREADY AXI_15_AWREADY AWSIZE AXI_15_AWSIZE AWVALID AXI_15_AWVALID BID AXI_15_BID BREADY AXI_15_BREADY BRESP AXI_15_BRESP BVALID AXI_15_BVALID RDATA AXI_15_RDATA RID AXI_15_RID RLAST AXI_15_RLAST RREADY AXI_15_RREADY RRESP AXI_15_RRESP RVALID AXI_15_RVALID WDATA AXI_15_WDATA WLAST AXI_15_WLAST WREADY AXI_15_WREADY WSTRB AXI_15_WSTRB WVALID AXI_15_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_15_RT true ARADDR AXI_15_ARADDR ARBURST AXI_15_ARBURST ARID AXI_15_ARID ARLEN AXI_15_ARLEN ARREADY AXI_15_ARREADY ARSIZE AXI_15_ARSIZE ARVALID AXI_15_ARVALID AWADDR AXI_15_AWADDR AWBURST AXI_15_AWBURST AWID AXI_15_AWID AWLEN AXI_15_AWLEN AWREADY AXI_15_AWREADY AWSIZE AXI_15_AWSIZE AWVALID AXI_15_AWVALID BID AXI_15_BID BREADY AXI_15_BREADY BRESP AXI_15_BRESP BVALID AXI_15_BVALID RDATA AXI_15_RDATA RID AXI_15_RID RLAST AXI_15_RLAST RREADY AXI_15_RREADY RRESP AXI_15_RRESP RVALID AXI_15_RVALID WDATA AXI_15_WDATA WLAST AXI_15_WLAST WREADY AXI_15_WREADY WSTRB AXI_15_WSTRB WVALID AXI_15_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_15_8HI true ARADDR AXI_15_ARADDR ARBURST AXI_15_ARBURST ARID AXI_15_ARID ARLEN AXI_15_ARLEN ARREADY AXI_15_ARREADY ARSIZE AXI_15_ARSIZE ARVALID AXI_15_ARVALID AWADDR AXI_15_AWADDR AWBURST AXI_15_AWBURST AWID AXI_15_AWID AWLEN AXI_15_AWLEN AWREADY AXI_15_AWREADY AWSIZE AXI_15_AWSIZE AWVALID AXI_15_AWVALID BID AXI_15_BID BREADY AXI_15_BREADY BRESP AXI_15_BRESP BVALID AXI_15_BVALID RDATA AXI_15_RDATA RID AXI_15_RID RLAST AXI_15_RLAST RREADY AXI_15_RREADY RRESP AXI_15_RRESP RVALID AXI_15_RVALID WDATA AXI_15_WDATA WLAST AXI_15_WLAST WREADY AXI_15_WREADY WSTRB AXI_15_WSTRB WVALID AXI_15_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_15_RT_8HI true ARADDR AXI_15_ARADDR ARBURST AXI_15_ARBURST ARID AXI_15_ARID ARLEN AXI_15_ARLEN ARREADY AXI_15_ARREADY ARSIZE AXI_15_ARSIZE ARVALID AXI_15_ARVALID AWADDR AXI_15_AWADDR AWBURST AXI_15_AWBURST AWID AXI_15_AWID AWLEN AXI_15_AWLEN AWREADY AXI_15_AWREADY AWSIZE AXI_15_AWSIZE AWVALID AXI_15_AWVALID BID AXI_15_BID BREADY AXI_15_BREADY BRESP AXI_15_BRESP BVALID AXI_15_BVALID RDATA AXI_15_RDATA RID AXI_15_RID RLAST AXI_15_RLAST RREADY AXI_15_RREADY RRESP AXI_15_RRESP RVALID AXI_15_RVALID WDATA AXI_15_WDATA WLAST AXI_15_WLAST WREADY AXI_15_WREADY WSTRB AXI_15_WSTRB WVALID AXI_15_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_16 true CLK AXI_16_ACLK ASSOCIATED_BUSIF SAXI_16 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_16_8HI true CLK AXI_16_ACLK ASSOCIATED_BUSIF SAXI_16_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_16_N true RST AXI_16_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_16 true ARADDR AXI_16_ARADDR ARBURST AXI_16_ARBURST ARID AXI_16_ARID ARLEN AXI_16_ARLEN ARREADY AXI_16_ARREADY ARSIZE AXI_16_ARSIZE ARVALID AXI_16_ARVALID AWADDR AXI_16_AWADDR AWBURST AXI_16_AWBURST AWID AXI_16_AWID AWLEN AXI_16_AWLEN AWREADY AXI_16_AWREADY AWSIZE AXI_16_AWSIZE AWVALID AXI_16_AWVALID BID AXI_16_BID BREADY AXI_16_BREADY BRESP AXI_16_BRESP BVALID AXI_16_BVALID RDATA AXI_16_RDATA RID AXI_16_RID RLAST AXI_16_RLAST RREADY AXI_16_RREADY RRESP AXI_16_RRESP RVALID AXI_16_RVALID WDATA AXI_16_WDATA WLAST AXI_16_WLAST WREADY AXI_16_WREADY WSTRB AXI_16_WSTRB WVALID AXI_16_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_16_8HI true ARADDR AXI_16_ARADDR ARBURST AXI_16_ARBURST ARID AXI_16_ARID ARLEN AXI_16_ARLEN ARREADY AXI_16_ARREADY ARSIZE AXI_16_ARSIZE ARVALID AXI_16_ARVALID AWADDR AXI_16_AWADDR AWBURST AXI_16_AWBURST AWID AXI_16_AWID AWLEN AXI_16_AWLEN AWREADY AXI_16_AWREADY AWSIZE AXI_16_AWSIZE AWVALID AXI_16_AWVALID BID AXI_16_BID BREADY AXI_16_BREADY BRESP AXI_16_BRESP BVALID AXI_16_BVALID RDATA AXI_16_RDATA RID AXI_16_RID RLAST AXI_16_RLAST RREADY AXI_16_RREADY RRESP AXI_16_RRESP RVALID AXI_16_RVALID WDATA AXI_16_WDATA WLAST AXI_16_WLAST WREADY AXI_16_WREADY WSTRB AXI_16_WSTRB WVALID AXI_16_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_17 true CLK AXI_17_ACLK ASSOCIATED_BUSIF SAXI_17 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_17_8HI true CLK AXI_17_ACLK ASSOCIATED_BUSIF SAXI_17_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_17_N true RST AXI_17_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_17 true ARADDR AXI_17_ARADDR ARBURST AXI_17_ARBURST ARID AXI_17_ARID ARLEN AXI_17_ARLEN ARREADY AXI_17_ARREADY ARSIZE AXI_17_ARSIZE ARVALID AXI_17_ARVALID AWADDR AXI_17_AWADDR AWBURST AXI_17_AWBURST AWID AXI_17_AWID AWLEN AXI_17_AWLEN AWREADY AXI_17_AWREADY AWSIZE AXI_17_AWSIZE AWVALID AXI_17_AWVALID BID AXI_17_BID BREADY AXI_17_BREADY BRESP AXI_17_BRESP BVALID AXI_17_BVALID RDATA AXI_17_RDATA RID AXI_17_RID RLAST AXI_17_RLAST RREADY AXI_17_RREADY RRESP AXI_17_RRESP RVALID AXI_17_RVALID WDATA AXI_17_WDATA WLAST AXI_17_WLAST WREADY AXI_17_WREADY WSTRB AXI_17_WSTRB WVALID AXI_17_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_17_8HI true ARADDR AXI_17_ARADDR ARBURST AXI_17_ARBURST ARID AXI_17_ARID ARLEN AXI_17_ARLEN ARREADY AXI_17_ARREADY ARSIZE AXI_17_ARSIZE ARVALID AXI_17_ARVALID AWADDR AXI_17_AWADDR AWBURST AXI_17_AWBURST AWID AXI_17_AWID AWLEN AXI_17_AWLEN AWREADY AXI_17_AWREADY AWSIZE AXI_17_AWSIZE AWVALID AXI_17_AWVALID BID AXI_17_BID BREADY AXI_17_BREADY BRESP AXI_17_BRESP BVALID AXI_17_BVALID RDATA AXI_17_RDATA RID AXI_17_RID RLAST AXI_17_RLAST RREADY AXI_17_RREADY RRESP AXI_17_RRESP RVALID AXI_17_RVALID WDATA AXI_17_WDATA WLAST AXI_17_WLAST WREADY AXI_17_WREADY WSTRB AXI_17_WSTRB WVALID AXI_17_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_18 true CLK AXI_18_ACLK ASSOCIATED_BUSIF SAXI_18 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_18_8HI true CLK AXI_18_ACLK ASSOCIATED_BUSIF SAXI_18_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_18_N true RST AXI_18_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_18 true ARADDR AXI_18_ARADDR ARBURST AXI_18_ARBURST ARID AXI_18_ARID ARLEN AXI_18_ARLEN ARREADY AXI_18_ARREADY ARSIZE AXI_18_ARSIZE ARVALID AXI_18_ARVALID AWADDR AXI_18_AWADDR AWBURST AXI_18_AWBURST AWID AXI_18_AWID AWLEN AXI_18_AWLEN AWREADY AXI_18_AWREADY AWSIZE AXI_18_AWSIZE AWVALID AXI_18_AWVALID BID AXI_18_BID BREADY AXI_18_BREADY BRESP AXI_18_BRESP BVALID AXI_18_BVALID RDATA AXI_18_RDATA RID AXI_18_RID RLAST AXI_18_RLAST RREADY AXI_18_RREADY RRESP AXI_18_RRESP RVALID AXI_18_RVALID WDATA AXI_18_WDATA WLAST AXI_18_WLAST WREADY AXI_18_WREADY WSTRB AXI_18_WSTRB WVALID AXI_18_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_18_8HI true ARADDR AXI_18_ARADDR ARBURST AXI_18_ARBURST ARID AXI_18_ARID ARLEN AXI_18_ARLEN ARREADY AXI_18_ARREADY ARSIZE AXI_18_ARSIZE ARVALID AXI_18_ARVALID AWADDR AXI_18_AWADDR AWBURST AXI_18_AWBURST AWID AXI_18_AWID AWLEN AXI_18_AWLEN AWREADY AXI_18_AWREADY AWSIZE AXI_18_AWSIZE AWVALID AXI_18_AWVALID BID AXI_18_BID BREADY AXI_18_BREADY BRESP AXI_18_BRESP BVALID AXI_18_BVALID RDATA AXI_18_RDATA RID AXI_18_RID RLAST AXI_18_RLAST RREADY AXI_18_RREADY RRESP AXI_18_RRESP RVALID AXI_18_RVALID WDATA AXI_18_WDATA WLAST AXI_18_WLAST WREADY AXI_18_WREADY WSTRB AXI_18_WSTRB WVALID AXI_18_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_19 true CLK AXI_19_ACLK ASSOCIATED_BUSIF SAXI_19 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_19_8HI true CLK AXI_19_ACLK ASSOCIATED_BUSIF SAXI_19_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_19_N true RST AXI_19_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_19 true ARADDR AXI_19_ARADDR ARBURST AXI_19_ARBURST ARID AXI_19_ARID ARLEN AXI_19_ARLEN ARREADY AXI_19_ARREADY ARSIZE AXI_19_ARSIZE ARVALID AXI_19_ARVALID AWADDR AXI_19_AWADDR AWBURST AXI_19_AWBURST AWID AXI_19_AWID AWLEN AXI_19_AWLEN AWREADY AXI_19_AWREADY AWSIZE AXI_19_AWSIZE AWVALID AXI_19_AWVALID BID AXI_19_BID BREADY AXI_19_BREADY BRESP AXI_19_BRESP BVALID AXI_19_BVALID RDATA AXI_19_RDATA RID AXI_19_RID RLAST AXI_19_RLAST RREADY AXI_19_RREADY RRESP AXI_19_RRESP RVALID AXI_19_RVALID WDATA AXI_19_WDATA WLAST AXI_19_WLAST WREADY AXI_19_WREADY WSTRB AXI_19_WSTRB WVALID AXI_19_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_19_8HI true ARADDR AXI_19_ARADDR ARBURST AXI_19_ARBURST ARID AXI_19_ARID ARLEN AXI_19_ARLEN ARREADY AXI_19_ARREADY ARSIZE AXI_19_ARSIZE ARVALID AXI_19_ARVALID AWADDR AXI_19_AWADDR AWBURST AXI_19_AWBURST AWID AXI_19_AWID AWLEN AXI_19_AWLEN AWREADY AXI_19_AWREADY AWSIZE AXI_19_AWSIZE AWVALID AXI_19_AWVALID BID AXI_19_BID BREADY AXI_19_BREADY BRESP AXI_19_BRESP BVALID AXI_19_BVALID RDATA AXI_19_RDATA RID AXI_19_RID RLAST AXI_19_RLAST RREADY AXI_19_RREADY RRESP AXI_19_RRESP RVALID AXI_19_RVALID WDATA AXI_19_WDATA WLAST AXI_19_WLAST WREADY AXI_19_WREADY WSTRB AXI_19_WSTRB WVALID AXI_19_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_20 true CLK AXI_20_ACLK ASSOCIATED_BUSIF SAXI_20 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_20_8HI true CLK AXI_20_ACLK ASSOCIATED_BUSIF SAXI_20_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_20_N true RST AXI_20_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_20 true ARADDR AXI_20_ARADDR ARBURST AXI_20_ARBURST ARID AXI_20_ARID ARLEN AXI_20_ARLEN ARREADY AXI_20_ARREADY ARSIZE AXI_20_ARSIZE ARVALID AXI_20_ARVALID AWADDR AXI_20_AWADDR AWBURST AXI_20_AWBURST AWID AXI_20_AWID AWLEN AXI_20_AWLEN AWREADY AXI_20_AWREADY AWSIZE AXI_20_AWSIZE AWVALID AXI_20_AWVALID BID AXI_20_BID BREADY AXI_20_BREADY BRESP AXI_20_BRESP BVALID AXI_20_BVALID RDATA AXI_20_RDATA RID AXI_20_RID RLAST AXI_20_RLAST RREADY AXI_20_RREADY RRESP AXI_20_RRESP RVALID AXI_20_RVALID WDATA AXI_20_WDATA WLAST AXI_20_WLAST WREADY AXI_20_WREADY WSTRB AXI_20_WSTRB WVALID AXI_20_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_20_8HI true ARADDR AXI_20_ARADDR ARBURST AXI_20_ARBURST ARID AXI_20_ARID ARLEN AXI_20_ARLEN ARREADY AXI_20_ARREADY ARSIZE AXI_20_ARSIZE ARVALID AXI_20_ARVALID AWADDR AXI_20_AWADDR AWBURST AXI_20_AWBURST AWID AXI_20_AWID AWLEN AXI_20_AWLEN AWREADY AXI_20_AWREADY AWSIZE AXI_20_AWSIZE AWVALID AXI_20_AWVALID BID AXI_20_BID BREADY AXI_20_BREADY BRESP AXI_20_BRESP BVALID AXI_20_BVALID RDATA AXI_20_RDATA RID AXI_20_RID RLAST AXI_20_RLAST RREADY AXI_20_RREADY RRESP AXI_20_RRESP RVALID AXI_20_RVALID WDATA AXI_20_WDATA WLAST AXI_20_WLAST WREADY AXI_20_WREADY WSTRB AXI_20_WSTRB WVALID AXI_20_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_21 true CLK AXI_21_ACLK ASSOCIATED_BUSIF SAXI_21 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_21_8HI true CLK AXI_21_ACLK ASSOCIATED_BUSIF SAXI_21_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_21_N true RST AXI_21_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_21 true ARADDR AXI_21_ARADDR ARBURST AXI_21_ARBURST ARID AXI_21_ARID ARLEN AXI_21_ARLEN ARREADY AXI_21_ARREADY ARSIZE AXI_21_ARSIZE ARVALID AXI_21_ARVALID AWADDR AXI_21_AWADDR AWBURST AXI_21_AWBURST AWID AXI_21_AWID AWLEN AXI_21_AWLEN AWREADY AXI_21_AWREADY AWSIZE AXI_21_AWSIZE AWVALID AXI_21_AWVALID BID AXI_21_BID BREADY AXI_21_BREADY BRESP AXI_21_BRESP BVALID AXI_21_BVALID RDATA AXI_21_RDATA RID AXI_21_RID RLAST AXI_21_RLAST RREADY AXI_21_RREADY RRESP AXI_21_RRESP RVALID AXI_21_RVALID WDATA AXI_21_WDATA WLAST AXI_21_WLAST WREADY AXI_21_WREADY WSTRB AXI_21_WSTRB WVALID AXI_21_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_21_8HI true ARADDR AXI_21_ARADDR ARBURST AXI_21_ARBURST ARID AXI_21_ARID ARLEN AXI_21_ARLEN ARREADY AXI_21_ARREADY ARSIZE AXI_21_ARSIZE ARVALID AXI_21_ARVALID AWADDR AXI_21_AWADDR AWBURST AXI_21_AWBURST AWID AXI_21_AWID AWLEN AXI_21_AWLEN AWREADY AXI_21_AWREADY AWSIZE AXI_21_AWSIZE AWVALID AXI_21_AWVALID BID AXI_21_BID BREADY AXI_21_BREADY BRESP AXI_21_BRESP BVALID AXI_21_BVALID RDATA AXI_21_RDATA RID AXI_21_RID RLAST AXI_21_RLAST RREADY AXI_21_RREADY RRESP AXI_21_RRESP RVALID AXI_21_RVALID WDATA AXI_21_WDATA WLAST AXI_21_WLAST WREADY AXI_21_WREADY WSTRB AXI_21_WSTRB WVALID AXI_21_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_22 true CLK AXI_22_ACLK ASSOCIATED_BUSIF SAXI_22 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_22_8HI true CLK AXI_22_ACLK ASSOCIATED_BUSIF SAXI_22_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_22_N true RST AXI_22_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_22 true ARADDR AXI_22_ARADDR ARBURST AXI_22_ARBURST ARID AXI_22_ARID ARLEN AXI_22_ARLEN ARREADY AXI_22_ARREADY ARSIZE AXI_22_ARSIZE ARVALID AXI_22_ARVALID AWADDR AXI_22_AWADDR AWBURST AXI_22_AWBURST AWID AXI_22_AWID AWLEN AXI_22_AWLEN AWREADY AXI_22_AWREADY AWSIZE AXI_22_AWSIZE AWVALID AXI_22_AWVALID BID AXI_22_BID BREADY AXI_22_BREADY BRESP AXI_22_BRESP BVALID AXI_22_BVALID RDATA AXI_22_RDATA RID AXI_22_RID RLAST AXI_22_RLAST RREADY AXI_22_RREADY RRESP AXI_22_RRESP RVALID AXI_22_RVALID WDATA AXI_22_WDATA WLAST AXI_22_WLAST WREADY AXI_22_WREADY WSTRB AXI_22_WSTRB WVALID AXI_22_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_22_8HI true ARADDR AXI_22_ARADDR ARBURST AXI_22_ARBURST ARID AXI_22_ARID ARLEN AXI_22_ARLEN ARREADY AXI_22_ARREADY ARSIZE AXI_22_ARSIZE ARVALID AXI_22_ARVALID AWADDR AXI_22_AWADDR AWBURST AXI_22_AWBURST AWID AXI_22_AWID AWLEN AXI_22_AWLEN AWREADY AXI_22_AWREADY AWSIZE AXI_22_AWSIZE AWVALID AXI_22_AWVALID BID AXI_22_BID BREADY AXI_22_BREADY BRESP AXI_22_BRESP BVALID AXI_22_BVALID RDATA AXI_22_RDATA RID AXI_22_RID RLAST AXI_22_RLAST RREADY AXI_22_RREADY RRESP AXI_22_RRESP RVALID AXI_22_RVALID WDATA AXI_22_WDATA WLAST AXI_22_WLAST WREADY AXI_22_WREADY WSTRB AXI_22_WSTRB WVALID AXI_22_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_23 true CLK AXI_23_ACLK ASSOCIATED_BUSIF SAXI_23 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_23_8HI true CLK AXI_23_ACLK ASSOCIATED_BUSIF SAXI_23_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_23_N true RST AXI_23_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_23 true ARADDR AXI_23_ARADDR ARBURST AXI_23_ARBURST ARID AXI_23_ARID ARLEN AXI_23_ARLEN ARREADY AXI_23_ARREADY ARSIZE AXI_23_ARSIZE ARVALID AXI_23_ARVALID AWADDR AXI_23_AWADDR AWBURST AXI_23_AWBURST AWID AXI_23_AWID AWLEN AXI_23_AWLEN AWREADY AXI_23_AWREADY AWSIZE AXI_23_AWSIZE AWVALID AXI_23_AWVALID BID AXI_23_BID BREADY AXI_23_BREADY BRESP AXI_23_BRESP BVALID AXI_23_BVALID RDATA AXI_23_RDATA RID AXI_23_RID RLAST AXI_23_RLAST RREADY AXI_23_RREADY RRESP AXI_23_RRESP RVALID AXI_23_RVALID WDATA AXI_23_WDATA WLAST AXI_23_WLAST WREADY AXI_23_WREADY WSTRB AXI_23_WSTRB WVALID AXI_23_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_23_8HI true ARADDR AXI_23_ARADDR ARBURST AXI_23_ARBURST ARID AXI_23_ARID ARLEN AXI_23_ARLEN ARREADY AXI_23_ARREADY ARSIZE AXI_23_ARSIZE ARVALID AXI_23_ARVALID AWADDR AXI_23_AWADDR AWBURST AXI_23_AWBURST AWID AXI_23_AWID AWLEN AXI_23_AWLEN AWREADY AXI_23_AWREADY AWSIZE AXI_23_AWSIZE AWVALID AXI_23_AWVALID BID AXI_23_BID BREADY AXI_23_BREADY BRESP AXI_23_BRESP BVALID AXI_23_BVALID RDATA AXI_23_RDATA RID AXI_23_RID RLAST AXI_23_RLAST RREADY AXI_23_RREADY RRESP AXI_23_RRESP RVALID AXI_23_RVALID WDATA AXI_23_WDATA WLAST AXI_23_WLAST WREADY AXI_23_WREADY WSTRB AXI_23_WSTRB WVALID AXI_23_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_24 true CLK AXI_24_ACLK ASSOCIATED_BUSIF SAXI_24 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_24_8HI true CLK AXI_24_ACLK ASSOCIATED_BUSIF SAXI_24_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_24_N true RST AXI_24_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_24 true ARADDR AXI_24_ARADDR ARBURST AXI_24_ARBURST ARID AXI_24_ARID ARLEN AXI_24_ARLEN ARREADY AXI_24_ARREADY ARSIZE AXI_24_ARSIZE ARVALID AXI_24_ARVALID AWADDR AXI_24_AWADDR AWBURST AXI_24_AWBURST AWID AXI_24_AWID AWLEN AXI_24_AWLEN AWREADY AXI_24_AWREADY AWSIZE AXI_24_AWSIZE AWVALID AXI_24_AWVALID BID AXI_24_BID BREADY AXI_24_BREADY BRESP AXI_24_BRESP BVALID AXI_24_BVALID RDATA AXI_24_RDATA RID AXI_24_RID RLAST AXI_24_RLAST RREADY AXI_24_RREADY RRESP AXI_24_RRESP RVALID AXI_24_RVALID WDATA AXI_24_WDATA WLAST AXI_24_WLAST WREADY AXI_24_WREADY WSTRB AXI_24_WSTRB WVALID AXI_24_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_24_8HI true ARADDR AXI_24_ARADDR ARBURST AXI_24_ARBURST ARID AXI_24_ARID ARLEN AXI_24_ARLEN ARREADY AXI_24_ARREADY ARSIZE AXI_24_ARSIZE ARVALID AXI_24_ARVALID AWADDR AXI_24_AWADDR AWBURST AXI_24_AWBURST AWID AXI_24_AWID AWLEN AXI_24_AWLEN AWREADY AXI_24_AWREADY AWSIZE AXI_24_AWSIZE AWVALID AXI_24_AWVALID BID AXI_24_BID BREADY AXI_24_BREADY BRESP AXI_24_BRESP BVALID AXI_24_BVALID RDATA AXI_24_RDATA RID AXI_24_RID RLAST AXI_24_RLAST RREADY AXI_24_RREADY RRESP AXI_24_RRESP RVALID AXI_24_RVALID WDATA AXI_24_WDATA WLAST AXI_24_WLAST WREADY AXI_24_WREADY WSTRB AXI_24_WSTRB WVALID AXI_24_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_25 true CLK AXI_25_ACLK ASSOCIATED_BUSIF SAXI_25 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_25_8HI true CLK AXI_25_ACLK ASSOCIATED_BUSIF SAXI_25_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_25_N true RST AXI_25_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_25 true ARADDR AXI_25_ARADDR ARBURST AXI_25_ARBURST ARID AXI_25_ARID ARLEN AXI_25_ARLEN ARREADY AXI_25_ARREADY ARSIZE AXI_25_ARSIZE ARVALID AXI_25_ARVALID AWADDR AXI_25_AWADDR AWBURST AXI_25_AWBURST AWID AXI_25_AWID AWLEN AXI_25_AWLEN AWREADY AXI_25_AWREADY AWSIZE AXI_25_AWSIZE AWVALID AXI_25_AWVALID BID AXI_25_BID BREADY AXI_25_BREADY BRESP AXI_25_BRESP BVALID AXI_25_BVALID RDATA AXI_25_RDATA RID AXI_25_RID RLAST AXI_25_RLAST RREADY AXI_25_RREADY RRESP AXI_25_RRESP RVALID AXI_25_RVALID WDATA AXI_25_WDATA WLAST AXI_25_WLAST WREADY AXI_25_WREADY WSTRB AXI_25_WSTRB WVALID AXI_25_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_25_8HI true ARADDR AXI_25_ARADDR ARBURST AXI_25_ARBURST ARID AXI_25_ARID ARLEN AXI_25_ARLEN ARREADY AXI_25_ARREADY ARSIZE AXI_25_ARSIZE ARVALID AXI_25_ARVALID AWADDR AXI_25_AWADDR AWBURST AXI_25_AWBURST AWID AXI_25_AWID AWLEN AXI_25_AWLEN AWREADY AXI_25_AWREADY AWSIZE AXI_25_AWSIZE AWVALID AXI_25_AWVALID BID AXI_25_BID BREADY AXI_25_BREADY BRESP AXI_25_BRESP BVALID AXI_25_BVALID RDATA AXI_25_RDATA RID AXI_25_RID RLAST AXI_25_RLAST RREADY AXI_25_RREADY RRESP AXI_25_RRESP RVALID AXI_25_RVALID WDATA AXI_25_WDATA WLAST AXI_25_WLAST WREADY AXI_25_WREADY WSTRB AXI_25_WSTRB WVALID AXI_25_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_26 true CLK AXI_26_ACLK ASSOCIATED_BUSIF SAXI_26 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_26_8HI true CLK AXI_26_ACLK ASSOCIATED_BUSIF SAXI_26_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_26_N true RST AXI_26_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_26 true ARADDR AXI_26_ARADDR ARBURST AXI_26_ARBURST ARID AXI_26_ARID ARLEN AXI_26_ARLEN ARREADY AXI_26_ARREADY ARSIZE AXI_26_ARSIZE ARVALID AXI_26_ARVALID AWADDR AXI_26_AWADDR AWBURST AXI_26_AWBURST AWID AXI_26_AWID AWLEN AXI_26_AWLEN AWREADY AXI_26_AWREADY AWSIZE AXI_26_AWSIZE AWVALID AXI_26_AWVALID BID AXI_26_BID BREADY AXI_26_BREADY BRESP AXI_26_BRESP BVALID AXI_26_BVALID RDATA AXI_26_RDATA RID AXI_26_RID RLAST AXI_26_RLAST RREADY AXI_26_RREADY RRESP AXI_26_RRESP RVALID AXI_26_RVALID WDATA AXI_26_WDATA WLAST AXI_26_WLAST WREADY AXI_26_WREADY WSTRB AXI_26_WSTRB WVALID AXI_26_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_26_8HI true ARADDR AXI_26_ARADDR ARBURST AXI_26_ARBURST ARID AXI_26_ARID ARLEN AXI_26_ARLEN ARREADY AXI_26_ARREADY ARSIZE AXI_26_ARSIZE ARVALID AXI_26_ARVALID AWADDR AXI_26_AWADDR AWBURST AXI_26_AWBURST AWID AXI_26_AWID AWLEN AXI_26_AWLEN AWREADY AXI_26_AWREADY AWSIZE AXI_26_AWSIZE AWVALID AXI_26_AWVALID BID AXI_26_BID BREADY AXI_26_BREADY BRESP AXI_26_BRESP BVALID AXI_26_BVALID RDATA AXI_26_RDATA RID AXI_26_RID RLAST AXI_26_RLAST RREADY AXI_26_RREADY RRESP AXI_26_RRESP RVALID AXI_26_RVALID WDATA AXI_26_WDATA WLAST AXI_26_WLAST WREADY AXI_26_WREADY WSTRB AXI_26_WSTRB WVALID AXI_26_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_27 true CLK AXI_27_ACLK ASSOCIATED_BUSIF SAXI_27 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_27_8HI true CLK AXI_27_ACLK ASSOCIATED_BUSIF SAXI_27_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_27_N true RST AXI_27_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_27 true ARADDR AXI_27_ARADDR ARBURST AXI_27_ARBURST ARID AXI_27_ARID ARLEN AXI_27_ARLEN ARREADY AXI_27_ARREADY ARSIZE AXI_27_ARSIZE ARVALID AXI_27_ARVALID AWADDR AXI_27_AWADDR AWBURST AXI_27_AWBURST AWID AXI_27_AWID AWLEN AXI_27_AWLEN AWREADY AXI_27_AWREADY AWSIZE AXI_27_AWSIZE AWVALID AXI_27_AWVALID BID AXI_27_BID BREADY AXI_27_BREADY BRESP AXI_27_BRESP BVALID AXI_27_BVALID RDATA AXI_27_RDATA RID AXI_27_RID RLAST AXI_27_RLAST RREADY AXI_27_RREADY RRESP AXI_27_RRESP RVALID AXI_27_RVALID WDATA AXI_27_WDATA WLAST AXI_27_WLAST WREADY AXI_27_WREADY WSTRB AXI_27_WSTRB WVALID AXI_27_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_27_8HI true ARADDR AXI_27_ARADDR ARBURST AXI_27_ARBURST ARID AXI_27_ARID ARLEN AXI_27_ARLEN ARREADY AXI_27_ARREADY ARSIZE AXI_27_ARSIZE ARVALID AXI_27_ARVALID AWADDR AXI_27_AWADDR AWBURST AXI_27_AWBURST AWID AXI_27_AWID AWLEN AXI_27_AWLEN AWREADY AXI_27_AWREADY AWSIZE AXI_27_AWSIZE AWVALID AXI_27_AWVALID BID AXI_27_BID BREADY AXI_27_BREADY BRESP AXI_27_BRESP BVALID AXI_27_BVALID RDATA AXI_27_RDATA RID AXI_27_RID RLAST AXI_27_RLAST RREADY AXI_27_RREADY RRESP AXI_27_RRESP RVALID AXI_27_RVALID WDATA AXI_27_WDATA WLAST AXI_27_WLAST WREADY AXI_27_WREADY WSTRB AXI_27_WSTRB WVALID AXI_27_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_28 true CLK AXI_28_ACLK ASSOCIATED_BUSIF SAXI_28 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_28_8HI true CLK AXI_28_ACLK ASSOCIATED_BUSIF SAXI_28_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_28_N true RST AXI_28_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_28 true ARADDR AXI_28_ARADDR ARBURST AXI_28_ARBURST ARID AXI_28_ARID ARLEN AXI_28_ARLEN ARREADY AXI_28_ARREADY ARSIZE AXI_28_ARSIZE ARVALID AXI_28_ARVALID AWADDR AXI_28_AWADDR AWBURST AXI_28_AWBURST AWID AXI_28_AWID AWLEN AXI_28_AWLEN AWREADY AXI_28_AWREADY AWSIZE AXI_28_AWSIZE AWVALID AXI_28_AWVALID BID AXI_28_BID BREADY AXI_28_BREADY BRESP AXI_28_BRESP BVALID AXI_28_BVALID RDATA AXI_28_RDATA RID AXI_28_RID RLAST AXI_28_RLAST RREADY AXI_28_RREADY RRESP AXI_28_RRESP RVALID AXI_28_RVALID WDATA AXI_28_WDATA WLAST AXI_28_WLAST WREADY AXI_28_WREADY WSTRB AXI_28_WSTRB WVALID AXI_28_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_28_8HI true ARADDR AXI_28_ARADDR ARBURST AXI_28_ARBURST ARID AXI_28_ARID ARLEN AXI_28_ARLEN ARREADY AXI_28_ARREADY ARSIZE AXI_28_ARSIZE ARVALID AXI_28_ARVALID AWADDR AXI_28_AWADDR AWBURST AXI_28_AWBURST AWID AXI_28_AWID AWLEN AXI_28_AWLEN AWREADY AXI_28_AWREADY AWSIZE AXI_28_AWSIZE AWVALID AXI_28_AWVALID BID AXI_28_BID BREADY AXI_28_BREADY BRESP AXI_28_BRESP BVALID AXI_28_BVALID RDATA AXI_28_RDATA RID AXI_28_RID RLAST AXI_28_RLAST RREADY AXI_28_RREADY RRESP AXI_28_RRESP RVALID AXI_28_RVALID WDATA AXI_28_WDATA WLAST AXI_28_WLAST WREADY AXI_28_WREADY WSTRB AXI_28_WSTRB WVALID AXI_28_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_29 true CLK AXI_29_ACLK ASSOCIATED_BUSIF SAXI_29 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_29_8HI true CLK AXI_29_ACLK ASSOCIATED_BUSIF SAXI_29_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_29_N true RST AXI_29_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_29 true ARADDR AXI_29_ARADDR ARBURST AXI_29_ARBURST ARID AXI_29_ARID ARLEN AXI_29_ARLEN ARREADY AXI_29_ARREADY ARSIZE AXI_29_ARSIZE ARVALID AXI_29_ARVALID AWADDR AXI_29_AWADDR AWBURST AXI_29_AWBURST AWID AXI_29_AWID AWLEN AXI_29_AWLEN AWREADY AXI_29_AWREADY AWSIZE AXI_29_AWSIZE AWVALID AXI_29_AWVALID BID AXI_29_BID BREADY AXI_29_BREADY BRESP AXI_29_BRESP BVALID AXI_29_BVALID RDATA AXI_29_RDATA RID AXI_29_RID RLAST AXI_29_RLAST RREADY AXI_29_RREADY RRESP AXI_29_RRESP RVALID AXI_29_RVALID WDATA AXI_29_WDATA WLAST AXI_29_WLAST WREADY AXI_29_WREADY WSTRB AXI_29_WSTRB WVALID AXI_29_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_29_8HI true ARADDR AXI_29_ARADDR ARBURST AXI_29_ARBURST ARID AXI_29_ARID ARLEN AXI_29_ARLEN ARREADY AXI_29_ARREADY ARSIZE AXI_29_ARSIZE ARVALID AXI_29_ARVALID AWADDR AXI_29_AWADDR AWBURST AXI_29_AWBURST AWID AXI_29_AWID AWLEN AXI_29_AWLEN AWREADY AXI_29_AWREADY AWSIZE AXI_29_AWSIZE AWVALID AXI_29_AWVALID BID AXI_29_BID BREADY AXI_29_BREADY BRESP AXI_29_BRESP BVALID AXI_29_BVALID RDATA AXI_29_RDATA RID AXI_29_RID RLAST AXI_29_RLAST RREADY AXI_29_RREADY RRESP AXI_29_RRESP RVALID AXI_29_RVALID WDATA AXI_29_WDATA WLAST AXI_29_WLAST WREADY AXI_29_WREADY WSTRB AXI_29_WSTRB WVALID AXI_29_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_30 true CLK AXI_30_ACLK ASSOCIATED_BUSIF SAXI_30 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_30_8HI true CLK AXI_30_ACLK ASSOCIATED_BUSIF SAXI_30_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_30_N true RST AXI_30_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_30 true ARADDR AXI_30_ARADDR ARBURST AXI_30_ARBURST ARID AXI_30_ARID ARLEN AXI_30_ARLEN ARREADY AXI_30_ARREADY ARSIZE AXI_30_ARSIZE ARVALID AXI_30_ARVALID AWADDR AXI_30_AWADDR AWBURST AXI_30_AWBURST AWID AXI_30_AWID AWLEN AXI_30_AWLEN AWREADY AXI_30_AWREADY AWSIZE AXI_30_AWSIZE AWVALID AXI_30_AWVALID BID AXI_30_BID BREADY AXI_30_BREADY BRESP AXI_30_BRESP BVALID AXI_30_BVALID RDATA AXI_30_RDATA RID AXI_30_RID RLAST AXI_30_RLAST RREADY AXI_30_RREADY RRESP AXI_30_RRESP RVALID AXI_30_RVALID WDATA AXI_30_WDATA WLAST AXI_30_WLAST WREADY AXI_30_WREADY WSTRB AXI_30_WSTRB WVALID AXI_30_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_30_8HI true ARADDR AXI_30_ARADDR ARBURST AXI_30_ARBURST ARID AXI_30_ARID ARLEN AXI_30_ARLEN ARREADY AXI_30_ARREADY ARSIZE AXI_30_ARSIZE ARVALID AXI_30_ARVALID AWADDR AXI_30_AWADDR AWBURST AXI_30_AWBURST AWID AXI_30_AWID AWLEN AXI_30_AWLEN AWREADY AXI_30_AWREADY AWSIZE AXI_30_AWSIZE AWVALID AXI_30_AWVALID BID AXI_30_BID BREADY AXI_30_BREADY BRESP AXI_30_BRESP BVALID AXI_30_BVALID RDATA AXI_30_RDATA RID AXI_30_RID RLAST AXI_30_RLAST RREADY AXI_30_RREADY RRESP AXI_30_RRESP RVALID AXI_30_RVALID WDATA AXI_30_WDATA WLAST AXI_30_WLAST WREADY AXI_30_WREADY WSTRB AXI_30_WSTRB WVALID AXI_30_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false ACLK_31 true CLK AXI_31_ACLK ASSOCIATED_BUSIF SAXI_31 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ACLK_31_8HI true CLK AXI_31_ACLK ASSOCIATED_BUSIF SAXI_31_8HI FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ARST_31_N true RST AXI_31_ARESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false SAXI_31 true ARADDR AXI_31_ARADDR ARBURST AXI_31_ARBURST ARID AXI_31_ARID ARLEN AXI_31_ARLEN ARREADY AXI_31_ARREADY ARSIZE AXI_31_ARSIZE ARVALID AXI_31_ARVALID AWADDR AXI_31_AWADDR AWBURST AXI_31_AWBURST AWID AXI_31_AWID AWLEN AXI_31_AWLEN AWREADY AXI_31_AWREADY AWSIZE AXI_31_AWSIZE AWVALID AXI_31_AWVALID BID AXI_31_BID BREADY AXI_31_BREADY BRESP AXI_31_BRESP BVALID AXI_31_BVALID RDATA AXI_31_RDATA RID AXI_31_RID RLAST AXI_31_RLAST RREADY AXI_31_RREADY RRESP AXI_31_RRESP RVALID AXI_31_RVALID WDATA AXI_31_WDATA WLAST AXI_31_WLAST WREADY AXI_31_WREADY WSTRB AXI_31_WSTRB WVALID AXI_31_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false SAXI_31_8HI true ARADDR AXI_31_ARADDR ARBURST AXI_31_ARBURST ARID AXI_31_ARID ARLEN AXI_31_ARLEN ARREADY AXI_31_ARREADY ARSIZE AXI_31_ARSIZE ARVALID AXI_31_ARVALID AWADDR AXI_31_AWADDR AWBURST AXI_31_AWBURST AWID AXI_31_AWID AWLEN AXI_31_AWLEN AWREADY AXI_31_AWREADY AWSIZE AXI_31_AWSIZE AWVALID AXI_31_AWVALID BID AXI_31_BID BREADY AXI_31_BREADY BRESP AXI_31_BRESP BVALID AXI_31_BVALID RDATA AXI_31_RDATA RID AXI_31_RID RLAST AXI_31_RLAST RREADY AXI_31_RREADY RRESP AXI_31_RRESP RVALID AXI_31_RVALID WDATA AXI_31_WDATA WLAST AXI_31_WLAST WREADY AXI_31_WREADY WSTRB AXI_31_WSTRB WVALID AXI_31_WVALID DATA_WIDTH 1 simulation.tlm PROTOCOL AXI4LITE simulation.tlm FREQ_HZ 100000000 simulation.tlm ID_WIDTH 0 simulation.tlm ADDR_WIDTH 1 simulation.tlm AWUSER_WIDTH 0 simulation.tlm ARUSER_WIDTH 0 simulation.tlm WUSER_WIDTH 0 simulation.tlm RUSER_WIDTH 0 simulation.tlm BUSER_WIDTH 0 simulation.tlm READ_WRITE_MODE READ_WRITE simulation.tlm HAS_BURST 0 simulation.tlm HAS_LOCK 0 simulation.tlm HAS_PROT 0 simulation.tlm HAS_CACHE 0 simulation.tlm HAS_QOS 0 simulation.tlm HAS_REGION 0 simulation.tlm HAS_WSTRB 0 simulation.tlm HAS_BRESP 0 simulation.tlm HAS_RRESP 0 simulation.tlm SUPPORTS_NARROW_BURST 0 simulation.tlm NUM_READ_OUTSTANDING 1 simulation.tlm NUM_WRITE_OUTSTANDING 1 simulation.tlm MAX_BURST_LENGTH 1 simulation.tlm PHASE 0.000 simulation.tlm CLK_DOMAIN simulation.tlm NUM_READ_THREADS 1 simulation.tlm NUM_WRITE_THREADS 1 simulation.tlm RUSER_BITS_PER_BYTE 0 simulation.tlm WUSER_BITS_PER_BYTE 0 simulation.tlm INSERT_VIP 0 simulation.rtl false PCLK_0 true CLK APB_0_PCLK ASSOCIATED_BUSIF SAPB_0 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl PRST_0_N true RST APB_0_PRESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl SAPB_0 true PADDR APB_0_PADDR PENABLE APB_0_PENABLE PRDATA APB_0_PRDATA PREADY APB_0_PREADY PSEL APB_0_PSEL PSLVERR APB_0_PSLVERR PWDATA APB_0_PWDATA PWRITE APB_0_PWRITE false PCLK_1 true CLK APB_1_PCLK ASSOCIATED_BUSIF SAPB_1 FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl true PRST_1_N true RST APB_1_PRESET_N POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl true SAPB_1 true PADDR APB_1_PADDR PENABLE APB_1_PENABLE PRDATA APB_1_PRDATA PREADY APB_1_PREADY PSEL APB_1_PSEL PSLVERR APB_1_PSLVERR PWDATA APB_1_PWDATA PWRITE APB_1_PWRITE false SAXI_00_TLM AXIMM_READ_SOCKET SAXI_00_rd_socket AXIMM_WRITE_SOCKET SAXI_00_wr_socket SAXI_01_TLM AXIMM_READ_SOCKET SAXI_01_rd_socket AXIMM_WRITE_SOCKET SAXI_01_wr_socket SAXI_02_TLM AXIMM_READ_SOCKET SAXI_02_rd_socket AXIMM_WRITE_SOCKET SAXI_02_wr_socket SAXI_03_TLM AXIMM_READ_SOCKET SAXI_03_rd_socket AXIMM_WRITE_SOCKET SAXI_03_wr_socket SAXI_04_TLM AXIMM_READ_SOCKET SAXI_04_rd_socket AXIMM_WRITE_SOCKET SAXI_04_wr_socket SAXI_05_TLM AXIMM_READ_SOCKET SAXI_05_rd_socket AXIMM_WRITE_SOCKET SAXI_05_wr_socket SAXI_06_TLM AXIMM_READ_SOCKET SAXI_06_rd_socket AXIMM_WRITE_SOCKET SAXI_06_wr_socket SAXI_07_TLM AXIMM_READ_SOCKET SAXI_07_rd_socket AXIMM_WRITE_SOCKET SAXI_07_wr_socket SAXI_08_TLM AXIMM_READ_SOCKET SAXI_08_rd_socket AXIMM_WRITE_SOCKET SAXI_08_wr_socket SAXI_09_TLM AXIMM_READ_SOCKET SAXI_09_rd_socket AXIMM_WRITE_SOCKET SAXI_09_wr_socket SAXI_10_TLM AXIMM_READ_SOCKET SAXI_10_rd_socket AXIMM_WRITE_SOCKET SAXI_10_wr_socket SAXI_11_TLM AXIMM_READ_SOCKET SAXI_11_rd_socket AXIMM_WRITE_SOCKET SAXI_11_wr_socket SAXI_12_TLM AXIMM_READ_SOCKET SAXI_12_rd_socket AXIMM_WRITE_SOCKET SAXI_12_wr_socket SAXI_13_TLM AXIMM_READ_SOCKET SAXI_13_rd_socket AXIMM_WRITE_SOCKET SAXI_13_wr_socket SAXI_14_TLM AXIMM_READ_SOCKET SAXI_14_rd_socket AXIMM_WRITE_SOCKET SAXI_14_wr_socket SAXI_15_TLM AXIMM_READ_SOCKET SAXI_15_rd_socket AXIMM_WRITE_SOCKET SAXI_15_wr_socket SAXI_16_TLM AXIMM_READ_SOCKET SAXI_16_rd_socket AXIMM_WRITE_SOCKET SAXI_16_wr_socket SAXI_17_TLM AXIMM_READ_SOCKET SAXI_17_rd_socket AXIMM_WRITE_SOCKET SAXI_17_wr_socket SAXI_18_TLM AXIMM_READ_SOCKET SAXI_18_rd_socket AXIMM_WRITE_SOCKET SAXI_18_wr_socket SAXI_19_TLM AXIMM_READ_SOCKET SAXI_19_rd_socket AXIMM_WRITE_SOCKET SAXI_19_wr_socket SAXI_20_TLM AXIMM_READ_SOCKET SAXI_20_rd_socket AXIMM_WRITE_SOCKET SAXI_20_wr_socket SAXI_21_TLM AXIMM_READ_SOCKET SAXI_21_rd_socket AXIMM_WRITE_SOCKET SAXI_21_wr_socket SAXI_22_TLM AXIMM_READ_SOCKET SAXI_22_rd_socket AXIMM_WRITE_SOCKET SAXI_22_wr_socket SAXI_23_TLM AXIMM_READ_SOCKET SAXI_23_rd_socket AXIMM_WRITE_SOCKET SAXI_23_wr_socket SAXI_24_TLM AXIMM_READ_SOCKET SAXI_24_rd_socket AXIMM_WRITE_SOCKET SAXI_24_wr_socket SAXI_25_TLM AXIMM_READ_SOCKET SAXI_25_rd_socket AXIMM_WRITE_SOCKET SAXI_25_wr_socket SAXI_26_TLM AXIMM_READ_SOCKET SAXI_26_rd_socket AXIMM_WRITE_SOCKET SAXI_26_wr_socket SAXI_27_TLM AXIMM_READ_SOCKET SAXI_27_rd_socket AXIMM_WRITE_SOCKET SAXI_27_wr_socket SAXI_28_TLM AXIMM_READ_SOCKET SAXI_28_rd_socket AXIMM_WRITE_SOCKET SAXI_28_wr_socket SAXI_29_TLM AXIMM_READ_SOCKET SAXI_29_rd_socket AXIMM_WRITE_SOCKET SAXI_29_wr_socket SAXI_30_TLM AXIMM_READ_SOCKET SAXI_30_rd_socket AXIMM_WRITE_SOCKET SAXI_30_wr_socket SAXI_31_TLM AXIMM_READ_SOCKET SAXI_31_rd_socket AXIMM_WRITE_SOCKET SAXI_31_wr_socket SAXI_00_8HI_TLM AXIMM_READ_SOCKET SAXI_00_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_00_8HI_wr_socket SAXI_01_8HI_TLM AXIMM_READ_SOCKET SAXI_01_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_01_8HI_wr_socket SAXI_02_8HI_TLM AXIMM_READ_SOCKET SAXI_02_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_02_8HI_wr_socket SAXI_03_8HI_TLM AXIMM_READ_SOCKET SAXI_03_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_03_8HI_wr_socket SAXI_04_8HI_TLM AXIMM_READ_SOCKET SAXI_04_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_04_8HI_wr_socket SAXI_05_8HI_TLM AXIMM_READ_SOCKET SAXI_05_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_05_8HI_wr_socket SAXI_06_8HI_TLM AXIMM_READ_SOCKET SAXI_06_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_06_8HI_wr_socket SAXI_07_8HI_TLM AXIMM_READ_SOCKET SAXI_07_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_07_8HI_wr_socket SAXI_08_8HI_TLM AXIMM_READ_SOCKET SAXI_08_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_08_8HI_wr_socket SAXI_09_8HI_TLM AXIMM_READ_SOCKET SAXI_09_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_09_8HI_wr_socket SAXI_10_8HI_TLM AXIMM_READ_SOCKET SAXI_10_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_10_8HI_wr_socket SAXI_11_8HI_TLM AXIMM_READ_SOCKET SAXI_11_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_11_8HI_wr_socket SAXI_12_8HI_TLM AXIMM_READ_SOCKET SAXI_12_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_12_8HI_wr_socket SAXI_13_8HI_TLM AXIMM_READ_SOCKET SAXI_13_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_13_8HI_wr_socket SAXI_14_8HI_TLM AXIMM_READ_SOCKET SAXI_14_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_14_8HI_wr_socket SAXI_15_8HI_TLM AXIMM_READ_SOCKET SAXI_15_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_15_8HI_wr_socket SAXI_16_8HI_TLM AXIMM_READ_SOCKET SAXI_16_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_16_8HI_wr_socket SAXI_17_8HI_TLM AXIMM_READ_SOCKET SAXI_17_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_17_8HI_wr_socket SAXI_18_8HI_TLM AXIMM_READ_SOCKET SAXI_18_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_18_8HI_wr_socket SAXI_19_8HI_TLM AXIMM_READ_SOCKET SAXI_19_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_19_8HI_wr_socket SAXI_20_8HI_TLM AXIMM_READ_SOCKET SAXI_20_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_20_8HI_wr_socket SAXI_21_8HI_TLM AXIMM_READ_SOCKET SAXI_21_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_21_8HI_wr_socket SAXI_22_8HI_TLM AXIMM_READ_SOCKET SAXI_22_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_22_8HI_wr_socket SAXI_23_8HI_TLM AXIMM_READ_SOCKET SAXI_23_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_23_8HI_wr_socket SAXI_24_8HI_TLM AXIMM_READ_SOCKET SAXI_24_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_24_8HI_wr_socket SAXI_25_8HI_TLM AXIMM_READ_SOCKET SAXI_25_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_25_8HI_wr_socket SAXI_26_8HI_TLM AXIMM_READ_SOCKET SAXI_26_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_26_8HI_wr_socket SAXI_27_8HI_TLM AXIMM_READ_SOCKET SAXI_27_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_27_8HI_wr_socket SAXI_28_8HI_TLM AXIMM_READ_SOCKET SAXI_28_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_28_8HI_wr_socket SAXI_29_8HI_TLM AXIMM_READ_SOCKET SAXI_29_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_29_8HI_wr_socket SAXI_30_8HI_TLM AXIMM_READ_SOCKET SAXI_30_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_30_8HI_wr_socket SAXI_31_8HI_TLM AXIMM_READ_SOCKET SAXI_31_8HI_rd_socket AXIMM_WRITE_SOCKET SAXI_31_8HI_wr_socket SAPB_0 Reg 0 4M 0 read-write false SAPB_1 Reg 0 4M 0 read-write false SAXI_00_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_01_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_02_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_03_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_04_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_05_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_06_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_07_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_08_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_09_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_10_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_11_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_12_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_13_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_14_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_15_RT_8HI HBM_MEM00 0x0200000000 512M 0 memory read-write false HBM_MEM01 0x0220000000 512M 0 memory read-write false HBM_MEM02 0x0240000000 512M 0 memory read-write false HBM_MEM03 0x0260000000 512M 0 memory read-write false HBM_MEM04 0x0280000000 512M 0 memory read-write false HBM_MEM05 0x02A0000000 512M 0 memory read-write false HBM_MEM06 0x02C0000000 512M 0 memory read-write false HBM_MEM07 0x02E0000000 512M 0 memory read-write false HBM_MEM08 0x0300000000 512M 0 memory read-write false HBM_MEM09 0x0320000000 512M 0 memory read-write false HBM_MEM10 0x0340000000 512M 0 memory read-write false HBM_MEM11 0x0360000000 512M 0 memory read-write false HBM_MEM12 0x0380000000 512M 0 memory read-write false HBM_MEM13 0x03A0000000 512M 0 memory read-write false HBM_MEM14 0x03C0000000 512M 0 memory read-write false HBM_MEM15 0x03E0000000 512M 0 memory read-write false SAXI_00_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_01_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_02_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_03_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_04_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_05_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_06_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_07_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_08_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_09_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_10_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_11_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_12_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_13_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_14_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_15_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_16_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_17_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_18_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_19_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_20_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_21_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_22_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_23_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_24_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_25_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_26_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_27_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_28_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_29_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_30_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_31_8HI HBM_MEM00 0x0000000000 512M 0 memory read-write false HBM_MEM01 0x0020000000 512M 0 memory read-write false HBM_MEM02 0x0040000000 512M 0 memory read-write false HBM_MEM03 0x0060000000 512M 0 memory read-write false HBM_MEM04 0x0080000000 512M 0 memory read-write false HBM_MEM05 0x00A0000000 512M 0 memory read-write false HBM_MEM06 0x00C0000000 512M 0 memory read-write false HBM_MEM07 0x00E0000000 512M 0 memory read-write false HBM_MEM08 0x0100000000 512M 0 memory read-write false HBM_MEM09 0x0120000000 512M 0 memory read-write false HBM_MEM10 0x0140000000 512M 0 memory read-write false HBM_MEM11 0x0160000000 512M 0 memory read-write false HBM_MEM12 0x0180000000 512M 0 memory read-write false HBM_MEM13 0x01A0000000 512M 0 memory read-write false HBM_MEM14 0x01C0000000 512M 0 memory read-write false HBM_MEM15 0x01E0000000 512M 0 memory read-write false HBM_MEM16 0x0200000000 512M 0 memory read-write false HBM_MEM17 0x0220000000 512M 0 memory read-write false HBM_MEM18 0x0240000000 512M 0 memory read-write false HBM_MEM19 0x0260000000 512M 0 memory read-write false HBM_MEM20 0x0280000000 512M 0 memory read-write false HBM_MEM21 0x02A0000000 512M 0 memory read-write false HBM_MEM22 0x02C0000000 512M 0 memory read-write false HBM_MEM23 0x02E0000000 512M 0 memory read-write false HBM_MEM24 0x0300000000 512M 0 memory read-write false HBM_MEM25 0x0320000000 512M 0 memory read-write false HBM_MEM26 0x0340000000 512M 0 memory read-write false HBM_MEM27 0x0360000000 512M 0 memory read-write false HBM_MEM28 0x0380000000 512M 0 memory read-write false HBM_MEM29 0x03A0000000 512M 0 memory read-write false HBM_MEM30 0x03C0000000 512M 0 memory read-write false HBM_MEM31 0x03E0000000 512M 0 memory read-write false SAXI_00_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_01_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_02_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_03_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_04_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_05_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_06_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_07_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_08_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_09_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_10_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_11_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_12_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_13_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_14_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_15_RT HBM_MEM00 0x100000000 256M 0 memory read-write false HBM_MEM01 0x110000000 256M 0 memory read-write false HBM_MEM02 0x120000000 256M 0 memory read-write false HBM_MEM03 0x130000000 256M 0 memory read-write false HBM_MEM04 0x140000000 256M 0 memory read-write false HBM_MEM05 0x150000000 256M 0 memory read-write false HBM_MEM06 0x160000000 256M 0 memory read-write false HBM_MEM07 0x170000000 256M 0 memory read-write false HBM_MEM08 0x180000000 256M 0 memory read-write false HBM_MEM09 0x190000000 256M 0 memory read-write false HBM_MEM10 0x1A0000000 256M 0 memory read-write false HBM_MEM11 0x1B0000000 256M 0 memory read-write false HBM_MEM12 0x1C0000000 256M 0 memory read-write false HBM_MEM13 0x1D0000000 256M 0 memory read-write false HBM_MEM14 0x1E0000000 256M 0 memory read-write false HBM_MEM15 0x1F0000000 256M 0 memory read-write false SAXI_00 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_01 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_02 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_03 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_04 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_05 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_06 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_07 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_08 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_09 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_10 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_11 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_12 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_13 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_14 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_15 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_16 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_17 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_18 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_19 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_20 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_21 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_22 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_23 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_24 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_25 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_26 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_27 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_28 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_29 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_30 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false SAXI_31 HBM_MEM00 0x000000000 256M 0 memory read-write false HBM_MEM01 0x010000000 256M 0 memory read-write false HBM_MEM02 0x020000000 256M 0 memory read-write false HBM_MEM03 0x030000000 256M 0 memory read-write false HBM_MEM04 0x040000000 256M 0 memory read-write false HBM_MEM05 0x050000000 256M 0 memory read-write false HBM_MEM06 0x060000000 256M 0 memory read-write false HBM_MEM07 0x070000000 256M 0 memory read-write false HBM_MEM08 0x080000000 256M 0 memory read-write false HBM_MEM09 0x090000000 256M 0 memory read-write false HBM_MEM10 0x0A0000000 256M 0 memory read-write false HBM_MEM11 0x0B0000000 256M 0 memory read-write false HBM_MEM12 0x0C0000000 256M 0 memory read-write false HBM_MEM13 0x0D0000000 256M 0 memory read-write false HBM_MEM14 0x0E0000000 256M 0 memory read-write false HBM_MEM15 0x0F0000000 256M 0 memory read-write false HBM_MEM16 0x100000000 256M 0 memory read-write false HBM_MEM17 0x110000000 256M 0 memory read-write false HBM_MEM18 0x120000000 256M 0 memory read-write false HBM_MEM19 0x130000000 256M 0 memory read-write false HBM_MEM20 0x140000000 256M 0 memory read-write false HBM_MEM21 0x150000000 256M 0 memory read-write false HBM_MEM22 0x160000000 256M 0 memory read-write false HBM_MEM23 0x170000000 256M 0 memory read-write false HBM_MEM24 0x180000000 256M 0 memory read-write false HBM_MEM25 0x190000000 256M 0 memory read-write false HBM_MEM26 0x1A0000000 256M 0 memory read-write false HBM_MEM27 0x1B0000000 256M 0 memory read-write false HBM_MEM28 0x1C0000000 256M 0 memory read-write false HBM_MEM29 0x1D0000000 256M 0 memory read-write false HBM_MEM30 0x1E0000000 256M 0 memory read-write false HBM_MEM31 0x1F0000000 256M 0 memory read-write false HBM_REF_CLK_0 in std_logic dummy_view HBM_REF_CLK_1 in std_logic dummy_view 0 true AXI_00_ACLK in std_logic dummy_view false AXI_00_ARESET_N in std_logic dummy_view false AXI_00_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_00_ARBURST in 1 0 std_logic_vector dummy_view false AXI_00_ARID in 5 0 std_logic_vector dummy_view false AXI_00_ARLEN in 3 0 std_logic_vector dummy_view false AXI_00_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_00_ARVALID in std_logic dummy_view false AXI_00_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_00_AWBURST in 1 0 std_logic_vector dummy_view false AXI_00_AWID in 5 0 std_logic_vector dummy_view false AXI_00_AWLEN in 3 0 std_logic_vector dummy_view false AXI_00_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_00_AWVALID in std_logic dummy_view false AXI_00_RREADY in std_logic dummy_view false AXI_00_BREADY in std_logic dummy_view false AXI_00_WDATA in 255 0 std_logic_vector dummy_view false AXI_00_WLAST in std_logic dummy_view false AXI_00_WSTRB in 31 0 std_logic_vector dummy_view false AXI_00_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_00_WVALID in std_logic dummy_view false AXI_01_ACLK in std_logic dummy_view false AXI_01_ARESET_N in std_logic dummy_view false AXI_01_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_01_ARBURST in 1 0 std_logic_vector dummy_view false AXI_01_ARID in 5 0 std_logic_vector dummy_view false AXI_01_ARLEN in 3 0 std_logic_vector dummy_view false AXI_01_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_01_ARVALID in std_logic dummy_view false AXI_01_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_01_AWBURST in 1 0 std_logic_vector dummy_view false AXI_01_AWID in 5 0 std_logic_vector dummy_view false AXI_01_AWLEN in 3 0 std_logic_vector dummy_view false AXI_01_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_01_AWVALID in std_logic dummy_view false AXI_01_RREADY in std_logic dummy_view false AXI_01_BREADY in std_logic dummy_view false AXI_01_WDATA in 255 0 std_logic_vector dummy_view false AXI_01_WLAST in std_logic dummy_view false AXI_01_WSTRB in 31 0 std_logic_vector dummy_view false AXI_01_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_01_WVALID in std_logic dummy_view false AXI_02_ACLK in std_logic dummy_view false AXI_02_ARESET_N in std_logic dummy_view false AXI_02_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_02_ARBURST in 1 0 std_logic_vector dummy_view false AXI_02_ARID in 5 0 std_logic_vector dummy_view false AXI_02_ARLEN in 3 0 std_logic_vector dummy_view false AXI_02_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_02_ARVALID in std_logic dummy_view false AXI_02_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_02_AWBURST in 1 0 std_logic_vector dummy_view false AXI_02_AWID in 5 0 std_logic_vector dummy_view false AXI_02_AWLEN in 3 0 std_logic_vector dummy_view false AXI_02_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_02_AWVALID in std_logic dummy_view false AXI_02_RREADY in std_logic dummy_view false AXI_02_BREADY in std_logic dummy_view false AXI_02_WDATA in 255 0 std_logic_vector dummy_view false AXI_02_WLAST in std_logic dummy_view false AXI_02_WSTRB in 31 0 std_logic_vector dummy_view false AXI_02_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_02_WVALID in std_logic dummy_view false AXI_03_ACLK in std_logic dummy_view false AXI_03_ARESET_N in std_logic dummy_view false AXI_03_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_03_ARBURST in 1 0 std_logic_vector dummy_view false AXI_03_ARID in 5 0 std_logic_vector dummy_view false AXI_03_ARLEN in 3 0 std_logic_vector dummy_view false AXI_03_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_03_ARVALID in std_logic dummy_view false AXI_03_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_03_AWBURST in 1 0 std_logic_vector dummy_view false AXI_03_AWID in 5 0 std_logic_vector dummy_view false AXI_03_AWLEN in 3 0 std_logic_vector dummy_view false AXI_03_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_03_AWVALID in std_logic dummy_view false AXI_03_RREADY in std_logic dummy_view false AXI_03_BREADY in std_logic dummy_view false AXI_03_WDATA in 255 0 std_logic_vector dummy_view false AXI_03_WLAST in std_logic dummy_view false AXI_03_WSTRB in 31 0 std_logic_vector dummy_view false AXI_03_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_03_WVALID in std_logic dummy_view false AXI_04_ACLK in std_logic dummy_view false AXI_04_ARESET_N in std_logic dummy_view false AXI_04_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_04_ARBURST in 1 0 std_logic_vector dummy_view false AXI_04_ARID in 5 0 std_logic_vector dummy_view false AXI_04_ARLEN in 3 0 std_logic_vector dummy_view false AXI_04_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_04_ARVALID in std_logic dummy_view false AXI_04_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_04_AWBURST in 1 0 std_logic_vector dummy_view false AXI_04_AWID in 5 0 std_logic_vector dummy_view false AXI_04_AWLEN in 3 0 std_logic_vector dummy_view false AXI_04_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_04_AWVALID in std_logic dummy_view false AXI_04_RREADY in std_logic dummy_view false AXI_04_BREADY in std_logic dummy_view false AXI_04_WDATA in 255 0 std_logic_vector dummy_view false AXI_04_WLAST in std_logic dummy_view false AXI_04_WSTRB in 31 0 std_logic_vector dummy_view false AXI_04_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_04_WVALID in std_logic dummy_view false AXI_05_ACLK in std_logic dummy_view false AXI_05_ARESET_N in std_logic dummy_view false AXI_05_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_05_ARBURST in 1 0 std_logic_vector dummy_view false AXI_05_ARID in 5 0 std_logic_vector dummy_view false AXI_05_ARLEN in 3 0 std_logic_vector dummy_view false AXI_05_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_05_ARVALID in std_logic dummy_view false AXI_05_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_05_AWBURST in 1 0 std_logic_vector dummy_view false AXI_05_AWID in 5 0 std_logic_vector dummy_view false AXI_05_AWLEN in 3 0 std_logic_vector dummy_view false AXI_05_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_05_AWVALID in std_logic dummy_view false AXI_05_RREADY in std_logic dummy_view false AXI_05_BREADY in std_logic dummy_view false AXI_05_WDATA in 255 0 std_logic_vector dummy_view false AXI_05_WLAST in std_logic dummy_view false AXI_05_WSTRB in 31 0 std_logic_vector dummy_view false AXI_05_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_05_WVALID in std_logic dummy_view false AXI_06_ACLK in std_logic dummy_view false AXI_06_ARESET_N in std_logic dummy_view false AXI_06_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_06_ARBURST in 1 0 std_logic_vector dummy_view false AXI_06_ARID in 5 0 std_logic_vector dummy_view false AXI_06_ARLEN in 3 0 std_logic_vector dummy_view false AXI_06_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_06_ARVALID in std_logic dummy_view false AXI_06_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_06_AWBURST in 1 0 std_logic_vector dummy_view false AXI_06_AWID in 5 0 std_logic_vector dummy_view false AXI_06_AWLEN in 3 0 std_logic_vector dummy_view false AXI_06_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_06_AWVALID in std_logic dummy_view false AXI_06_RREADY in std_logic dummy_view false AXI_06_BREADY in std_logic dummy_view false AXI_06_WDATA in 255 0 std_logic_vector dummy_view false AXI_06_WLAST in std_logic dummy_view false AXI_06_WSTRB in 31 0 std_logic_vector dummy_view false AXI_06_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_06_WVALID in std_logic dummy_view false AXI_07_ACLK in std_logic dummy_view false AXI_07_ARESET_N in std_logic dummy_view false AXI_07_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_07_ARBURST in 1 0 std_logic_vector dummy_view false AXI_07_ARID in 5 0 std_logic_vector dummy_view false AXI_07_ARLEN in 3 0 std_logic_vector dummy_view false AXI_07_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_07_ARVALID in std_logic dummy_view false AXI_07_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_07_AWBURST in 1 0 std_logic_vector dummy_view false AXI_07_AWID in 5 0 std_logic_vector dummy_view false AXI_07_AWLEN in 3 0 std_logic_vector dummy_view false AXI_07_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_07_AWVALID in std_logic dummy_view false AXI_07_RREADY in std_logic dummy_view false AXI_07_BREADY in std_logic dummy_view false AXI_07_WDATA in 255 0 std_logic_vector dummy_view false AXI_07_WLAST in std_logic dummy_view false AXI_07_WSTRB in 31 0 std_logic_vector dummy_view false AXI_07_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_07_WVALID in std_logic dummy_view false AXI_08_ACLK in std_logic dummy_view false AXI_08_ARESET_N in std_logic dummy_view false AXI_08_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_08_ARBURST in 1 0 std_logic_vector dummy_view false AXI_08_ARID in 5 0 std_logic_vector dummy_view false AXI_08_ARLEN in 3 0 std_logic_vector dummy_view false AXI_08_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_08_ARVALID in std_logic dummy_view false AXI_08_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_08_AWBURST in 1 0 std_logic_vector dummy_view false AXI_08_AWID in 5 0 std_logic_vector dummy_view false AXI_08_AWLEN in 3 0 std_logic_vector dummy_view false AXI_08_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_08_AWVALID in std_logic dummy_view false AXI_08_RREADY in std_logic dummy_view false AXI_08_BREADY in std_logic dummy_view false AXI_08_WDATA in 255 0 std_logic_vector dummy_view false AXI_08_WLAST in std_logic dummy_view false AXI_08_WSTRB in 31 0 std_logic_vector dummy_view false AXI_08_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_08_WVALID in std_logic dummy_view false AXI_09_ACLK in std_logic dummy_view false AXI_09_ARESET_N in std_logic dummy_view false AXI_09_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_09_ARBURST in 1 0 std_logic_vector dummy_view false AXI_09_ARID in 5 0 std_logic_vector dummy_view false AXI_09_ARLEN in 3 0 std_logic_vector dummy_view false AXI_09_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_09_ARVALID in std_logic dummy_view false AXI_09_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_09_AWBURST in 1 0 std_logic_vector dummy_view false AXI_09_AWID in 5 0 std_logic_vector dummy_view false AXI_09_AWLEN in 3 0 std_logic_vector dummy_view false AXI_09_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_09_AWVALID in std_logic dummy_view false AXI_09_RREADY in std_logic dummy_view false AXI_09_BREADY in std_logic dummy_view false AXI_09_WDATA in 255 0 std_logic_vector dummy_view false AXI_09_WLAST in std_logic dummy_view false AXI_09_WSTRB in 31 0 std_logic_vector dummy_view false AXI_09_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_09_WVALID in std_logic dummy_view false AXI_10_ACLK in std_logic dummy_view false AXI_10_ARESET_N in std_logic dummy_view false AXI_10_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_10_ARBURST in 1 0 std_logic_vector dummy_view false AXI_10_ARID in 5 0 std_logic_vector dummy_view false AXI_10_ARLEN in 3 0 std_logic_vector dummy_view false AXI_10_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_10_ARVALID in std_logic dummy_view false AXI_10_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_10_AWBURST in 1 0 std_logic_vector dummy_view false AXI_10_AWID in 5 0 std_logic_vector dummy_view false AXI_10_AWLEN in 3 0 std_logic_vector dummy_view false AXI_10_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_10_AWVALID in std_logic dummy_view false AXI_10_RREADY in std_logic dummy_view false AXI_10_BREADY in std_logic dummy_view false AXI_10_WDATA in 255 0 std_logic_vector dummy_view false AXI_10_WLAST in std_logic dummy_view false AXI_10_WSTRB in 31 0 std_logic_vector dummy_view false AXI_10_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_10_WVALID in std_logic dummy_view false AXI_11_ACLK in std_logic dummy_view false AXI_11_ARESET_N in std_logic dummy_view false AXI_11_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_11_ARBURST in 1 0 std_logic_vector dummy_view false AXI_11_ARID in 5 0 std_logic_vector dummy_view false AXI_11_ARLEN in 3 0 std_logic_vector dummy_view false AXI_11_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_11_ARVALID in std_logic dummy_view false AXI_11_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_11_AWBURST in 1 0 std_logic_vector dummy_view false AXI_11_AWID in 5 0 std_logic_vector dummy_view false AXI_11_AWLEN in 3 0 std_logic_vector dummy_view false AXI_11_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_11_AWVALID in std_logic dummy_view false AXI_11_RREADY in std_logic dummy_view false AXI_11_BREADY in std_logic dummy_view false AXI_11_WDATA in 255 0 std_logic_vector dummy_view false AXI_11_WLAST in std_logic dummy_view false AXI_11_WSTRB in 31 0 std_logic_vector dummy_view false AXI_11_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_11_WVALID in std_logic dummy_view false AXI_12_ACLK in std_logic dummy_view false AXI_12_ARESET_N in std_logic dummy_view false AXI_12_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_12_ARBURST in 1 0 std_logic_vector dummy_view false AXI_12_ARID in 5 0 std_logic_vector dummy_view false AXI_12_ARLEN in 3 0 std_logic_vector dummy_view false AXI_12_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_12_ARVALID in std_logic dummy_view false AXI_12_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_12_AWBURST in 1 0 std_logic_vector dummy_view false AXI_12_AWID in 5 0 std_logic_vector dummy_view false AXI_12_AWLEN in 3 0 std_logic_vector dummy_view false AXI_12_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_12_AWVALID in std_logic dummy_view false AXI_12_RREADY in std_logic dummy_view false AXI_12_BREADY in std_logic dummy_view false AXI_12_WDATA in 255 0 std_logic_vector dummy_view false AXI_12_WLAST in std_logic dummy_view false AXI_12_WSTRB in 31 0 std_logic_vector dummy_view false AXI_12_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_12_WVALID in std_logic dummy_view false AXI_13_ACLK in std_logic dummy_view false AXI_13_ARESET_N in std_logic dummy_view false AXI_13_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_13_ARBURST in 1 0 std_logic_vector dummy_view false AXI_13_ARID in 5 0 std_logic_vector dummy_view false AXI_13_ARLEN in 3 0 std_logic_vector dummy_view false AXI_13_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_13_ARVALID in std_logic dummy_view false AXI_13_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_13_AWBURST in 1 0 std_logic_vector dummy_view false AXI_13_AWID in 5 0 std_logic_vector dummy_view false AXI_13_AWLEN in 3 0 std_logic_vector dummy_view false AXI_13_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_13_AWVALID in std_logic dummy_view false AXI_13_RREADY in std_logic dummy_view false AXI_13_BREADY in std_logic dummy_view false AXI_13_WDATA in 255 0 std_logic_vector dummy_view false AXI_13_WLAST in std_logic dummy_view false AXI_13_WSTRB in 31 0 std_logic_vector dummy_view false AXI_13_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_13_WVALID in std_logic dummy_view false AXI_14_ACLK in std_logic dummy_view false AXI_14_ARESET_N in std_logic dummy_view false AXI_14_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_14_ARBURST in 1 0 std_logic_vector dummy_view false AXI_14_ARID in 5 0 std_logic_vector dummy_view false AXI_14_ARLEN in 3 0 std_logic_vector dummy_view false AXI_14_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_14_ARVALID in std_logic dummy_view false AXI_14_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_14_AWBURST in 1 0 std_logic_vector dummy_view false AXI_14_AWID in 5 0 std_logic_vector dummy_view false AXI_14_AWLEN in 3 0 std_logic_vector dummy_view false AXI_14_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_14_AWVALID in std_logic dummy_view false AXI_14_RREADY in std_logic dummy_view false AXI_14_BREADY in std_logic dummy_view false AXI_14_WDATA in 255 0 std_logic_vector dummy_view false AXI_14_WLAST in std_logic dummy_view false AXI_14_WSTRB in 31 0 std_logic_vector dummy_view false AXI_14_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_14_WVALID in std_logic dummy_view false AXI_15_ACLK in std_logic dummy_view false AXI_15_ARESET_N in std_logic dummy_view false AXI_15_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_15_ARBURST in 1 0 std_logic_vector dummy_view false AXI_15_ARID in 5 0 std_logic_vector dummy_view false AXI_15_ARLEN in 3 0 std_logic_vector dummy_view false AXI_15_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_15_ARVALID in std_logic dummy_view false AXI_15_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_15_AWBURST in 1 0 std_logic_vector dummy_view false AXI_15_AWID in 5 0 std_logic_vector dummy_view false AXI_15_AWLEN in 3 0 std_logic_vector dummy_view false AXI_15_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_15_AWVALID in std_logic dummy_view false AXI_15_RREADY in std_logic dummy_view false AXI_15_BREADY in std_logic dummy_view false AXI_15_WDATA in 255 0 std_logic_vector dummy_view false AXI_15_WLAST in std_logic dummy_view false AXI_15_WSTRB in 31 0 std_logic_vector dummy_view false AXI_15_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_15_WVALID in std_logic dummy_view false AXI_16_ACLK in std_logic dummy_view false AXI_16_ARESET_N in std_logic dummy_view false AXI_16_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_16_ARBURST in 1 0 std_logic_vector dummy_view false AXI_16_ARID in 5 0 std_logic_vector dummy_view false AXI_16_ARLEN in 3 0 std_logic_vector dummy_view false AXI_16_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_16_ARVALID in std_logic dummy_view false AXI_16_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_16_AWBURST in 1 0 std_logic_vector dummy_view false AXI_16_AWID in 5 0 std_logic_vector dummy_view false AXI_16_AWLEN in 3 0 std_logic_vector dummy_view false AXI_16_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_16_AWVALID in std_logic dummy_view false AXI_16_RREADY in std_logic dummy_view false AXI_16_BREADY in std_logic dummy_view false AXI_16_WDATA in 255 0 std_logic_vector dummy_view false AXI_16_WLAST in std_logic dummy_view false AXI_16_WSTRB in 31 0 std_logic_vector dummy_view false AXI_16_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_16_WVALID in std_logic dummy_view false AXI_17_ACLK in std_logic dummy_view false AXI_17_ARESET_N in std_logic dummy_view false AXI_17_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_17_ARBURST in 1 0 std_logic_vector dummy_view false AXI_17_ARID in 5 0 std_logic_vector dummy_view false AXI_17_ARLEN in 3 0 std_logic_vector dummy_view false AXI_17_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_17_ARVALID in std_logic dummy_view false AXI_17_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_17_AWBURST in 1 0 std_logic_vector dummy_view false AXI_17_AWID in 5 0 std_logic_vector dummy_view false AXI_17_AWLEN in 3 0 std_logic_vector dummy_view false AXI_17_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_17_AWVALID in std_logic dummy_view false AXI_17_RREADY in std_logic dummy_view false AXI_17_BREADY in std_logic dummy_view false AXI_17_WDATA in 255 0 std_logic_vector dummy_view false AXI_17_WLAST in std_logic dummy_view false AXI_17_WSTRB in 31 0 std_logic_vector dummy_view false AXI_17_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_17_WVALID in std_logic dummy_view false AXI_18_ACLK in std_logic dummy_view false AXI_18_ARESET_N in std_logic dummy_view false AXI_18_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_18_ARBURST in 1 0 std_logic_vector dummy_view false AXI_18_ARID in 5 0 std_logic_vector dummy_view false AXI_18_ARLEN in 3 0 std_logic_vector dummy_view false AXI_18_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_18_ARVALID in std_logic dummy_view false AXI_18_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_18_AWBURST in 1 0 std_logic_vector dummy_view false AXI_18_AWID in 5 0 std_logic_vector dummy_view false AXI_18_AWLEN in 3 0 std_logic_vector dummy_view false AXI_18_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_18_AWVALID in std_logic dummy_view false AXI_18_RREADY in std_logic dummy_view false AXI_18_BREADY in std_logic dummy_view false AXI_18_WDATA in 255 0 std_logic_vector dummy_view false AXI_18_WLAST in std_logic dummy_view false AXI_18_WSTRB in 31 0 std_logic_vector dummy_view false AXI_18_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_18_WVALID in std_logic dummy_view false AXI_19_ACLK in std_logic dummy_view false AXI_19_ARESET_N in std_logic dummy_view false AXI_19_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_19_ARBURST in 1 0 std_logic_vector dummy_view false AXI_19_ARID in 5 0 std_logic_vector dummy_view false AXI_19_ARLEN in 3 0 std_logic_vector dummy_view false AXI_19_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_19_ARVALID in std_logic dummy_view false AXI_19_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_19_AWBURST in 1 0 std_logic_vector dummy_view false AXI_19_AWID in 5 0 std_logic_vector dummy_view false AXI_19_AWLEN in 3 0 std_logic_vector dummy_view false AXI_19_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_19_AWVALID in std_logic dummy_view false AXI_19_RREADY in std_logic dummy_view false AXI_19_BREADY in std_logic dummy_view false AXI_19_WDATA in 255 0 std_logic_vector dummy_view false AXI_19_WLAST in std_logic dummy_view false AXI_19_WSTRB in 31 0 std_logic_vector dummy_view false AXI_19_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_19_WVALID in std_logic dummy_view false AXI_20_ACLK in std_logic dummy_view false AXI_20_ARESET_N in std_logic dummy_view false AXI_20_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_20_ARBURST in 1 0 std_logic_vector dummy_view false AXI_20_ARID in 5 0 std_logic_vector dummy_view false AXI_20_ARLEN in 3 0 std_logic_vector dummy_view false AXI_20_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_20_ARVALID in std_logic dummy_view false AXI_20_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_20_AWBURST in 1 0 std_logic_vector dummy_view false AXI_20_AWID in 5 0 std_logic_vector dummy_view false AXI_20_AWLEN in 3 0 std_logic_vector dummy_view false AXI_20_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_20_AWVALID in std_logic dummy_view false AXI_20_RREADY in std_logic dummy_view false AXI_20_BREADY in std_logic dummy_view false AXI_20_WDATA in 255 0 std_logic_vector dummy_view false AXI_20_WLAST in std_logic dummy_view false AXI_20_WSTRB in 31 0 std_logic_vector dummy_view false AXI_20_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_20_WVALID in std_logic dummy_view false AXI_21_ACLK in std_logic dummy_view false AXI_21_ARESET_N in std_logic dummy_view false AXI_21_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_21_ARBURST in 1 0 std_logic_vector dummy_view false AXI_21_ARID in 5 0 std_logic_vector dummy_view false AXI_21_ARLEN in 3 0 std_logic_vector dummy_view false AXI_21_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_21_ARVALID in std_logic dummy_view false AXI_21_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_21_AWBURST in 1 0 std_logic_vector dummy_view false AXI_21_AWID in 5 0 std_logic_vector dummy_view false AXI_21_AWLEN in 3 0 std_logic_vector dummy_view false AXI_21_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_21_AWVALID in std_logic dummy_view false AXI_21_RREADY in std_logic dummy_view false AXI_21_BREADY in std_logic dummy_view false AXI_21_WDATA in 255 0 std_logic_vector dummy_view false AXI_21_WLAST in std_logic dummy_view false AXI_21_WSTRB in 31 0 std_logic_vector dummy_view false AXI_21_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_21_WVALID in std_logic dummy_view false AXI_22_ACLK in std_logic dummy_view false AXI_22_ARESET_N in std_logic dummy_view false AXI_22_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_22_ARBURST in 1 0 std_logic_vector dummy_view false AXI_22_ARID in 5 0 std_logic_vector dummy_view false AXI_22_ARLEN in 3 0 std_logic_vector dummy_view false AXI_22_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_22_ARVALID in std_logic dummy_view false AXI_22_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_22_AWBURST in 1 0 std_logic_vector dummy_view false AXI_22_AWID in 5 0 std_logic_vector dummy_view false AXI_22_AWLEN in 3 0 std_logic_vector dummy_view false AXI_22_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_22_AWVALID in std_logic dummy_view false AXI_22_RREADY in std_logic dummy_view false AXI_22_BREADY in std_logic dummy_view false AXI_22_WDATA in 255 0 std_logic_vector dummy_view false AXI_22_WLAST in std_logic dummy_view false AXI_22_WSTRB in 31 0 std_logic_vector dummy_view false AXI_22_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_22_WVALID in std_logic dummy_view false AXI_23_ACLK in std_logic dummy_view false AXI_23_ARESET_N in std_logic dummy_view false AXI_23_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_23_ARBURST in 1 0 std_logic_vector dummy_view false AXI_23_ARID in 5 0 std_logic_vector dummy_view false AXI_23_ARLEN in 3 0 std_logic_vector dummy_view false AXI_23_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_23_ARVALID in std_logic dummy_view false AXI_23_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_23_AWBURST in 1 0 std_logic_vector dummy_view false AXI_23_AWID in 5 0 std_logic_vector dummy_view false AXI_23_AWLEN in 3 0 std_logic_vector dummy_view false AXI_23_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_23_AWVALID in std_logic dummy_view false AXI_23_RREADY in std_logic dummy_view false AXI_23_BREADY in std_logic dummy_view false AXI_23_WDATA in 255 0 std_logic_vector dummy_view false AXI_23_WLAST in std_logic dummy_view false AXI_23_WSTRB in 31 0 std_logic_vector dummy_view false AXI_23_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_23_WVALID in std_logic dummy_view false AXI_24_ACLK in std_logic dummy_view false AXI_24_ARESET_N in std_logic dummy_view false AXI_24_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_24_ARBURST in 1 0 std_logic_vector dummy_view false AXI_24_ARID in 5 0 std_logic_vector dummy_view false AXI_24_ARLEN in 3 0 std_logic_vector dummy_view false AXI_24_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_24_ARVALID in std_logic dummy_view false AXI_24_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_24_AWBURST in 1 0 std_logic_vector dummy_view false AXI_24_AWID in 5 0 std_logic_vector dummy_view false AXI_24_AWLEN in 3 0 std_logic_vector dummy_view false AXI_24_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_24_AWVALID in std_logic dummy_view false AXI_24_RREADY in std_logic dummy_view false AXI_24_BREADY in std_logic dummy_view false AXI_24_WDATA in 255 0 std_logic_vector dummy_view false AXI_24_WLAST in std_logic dummy_view false AXI_24_WSTRB in 31 0 std_logic_vector dummy_view false AXI_24_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_24_WVALID in std_logic dummy_view false AXI_25_ACLK in std_logic dummy_view false AXI_25_ARESET_N in std_logic dummy_view false AXI_25_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_25_ARBURST in 1 0 std_logic_vector dummy_view false AXI_25_ARID in 5 0 std_logic_vector dummy_view false AXI_25_ARLEN in 3 0 std_logic_vector dummy_view false AXI_25_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_25_ARVALID in std_logic dummy_view false AXI_25_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_25_AWBURST in 1 0 std_logic_vector dummy_view false AXI_25_AWID in 5 0 std_logic_vector dummy_view false AXI_25_AWLEN in 3 0 std_logic_vector dummy_view false AXI_25_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_25_AWVALID in std_logic dummy_view false AXI_25_RREADY in std_logic dummy_view false AXI_25_BREADY in std_logic dummy_view false AXI_25_WDATA in 255 0 std_logic_vector dummy_view false AXI_25_WLAST in std_logic dummy_view false AXI_25_WSTRB in 31 0 std_logic_vector dummy_view false AXI_25_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_25_WVALID in std_logic dummy_view false AXI_26_ACLK in std_logic dummy_view false AXI_26_ARESET_N in std_logic dummy_view false AXI_26_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_26_ARBURST in 1 0 std_logic_vector dummy_view false AXI_26_ARID in 5 0 std_logic_vector dummy_view false AXI_26_ARLEN in 3 0 std_logic_vector dummy_view false AXI_26_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_26_ARVALID in std_logic dummy_view false AXI_26_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_26_AWBURST in 1 0 std_logic_vector dummy_view false AXI_26_AWID in 5 0 std_logic_vector dummy_view false AXI_26_AWLEN in 3 0 std_logic_vector dummy_view false AXI_26_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_26_AWVALID in std_logic dummy_view false AXI_26_RREADY in std_logic dummy_view false AXI_26_BREADY in std_logic dummy_view false AXI_26_WDATA in 255 0 std_logic_vector dummy_view false AXI_26_WLAST in std_logic dummy_view false AXI_26_WSTRB in 31 0 std_logic_vector dummy_view false AXI_26_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_26_WVALID in std_logic dummy_view false AXI_27_ACLK in std_logic dummy_view false AXI_27_ARESET_N in std_logic dummy_view false AXI_27_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_27_ARBURST in 1 0 std_logic_vector dummy_view false AXI_27_ARID in 5 0 std_logic_vector dummy_view false AXI_27_ARLEN in 3 0 std_logic_vector dummy_view false AXI_27_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_27_ARVALID in std_logic dummy_view false AXI_27_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_27_AWBURST in 1 0 std_logic_vector dummy_view false AXI_27_AWID in 5 0 std_logic_vector dummy_view false AXI_27_AWLEN in 3 0 std_logic_vector dummy_view false AXI_27_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_27_AWVALID in std_logic dummy_view false AXI_27_RREADY in std_logic dummy_view false AXI_27_BREADY in std_logic dummy_view false AXI_27_WDATA in 255 0 std_logic_vector dummy_view false AXI_27_WLAST in std_logic dummy_view false AXI_27_WSTRB in 31 0 std_logic_vector dummy_view false AXI_27_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_27_WVALID in std_logic dummy_view false AXI_28_ACLK in std_logic dummy_view false AXI_28_ARESET_N in std_logic dummy_view false AXI_28_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_28_ARBURST in 1 0 std_logic_vector dummy_view false AXI_28_ARID in 5 0 std_logic_vector dummy_view false AXI_28_ARLEN in 3 0 std_logic_vector dummy_view false AXI_28_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_28_ARVALID in std_logic dummy_view false AXI_28_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_28_AWBURST in 1 0 std_logic_vector dummy_view false AXI_28_AWID in 5 0 std_logic_vector dummy_view false AXI_28_AWLEN in 3 0 std_logic_vector dummy_view false AXI_28_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_28_AWVALID in std_logic dummy_view false AXI_28_RREADY in std_logic dummy_view false AXI_28_BREADY in std_logic dummy_view false AXI_28_WDATA in 255 0 std_logic_vector dummy_view false AXI_28_WLAST in std_logic dummy_view false AXI_28_WSTRB in 31 0 std_logic_vector dummy_view false AXI_28_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_28_WVALID in std_logic dummy_view false AXI_29_ACLK in std_logic dummy_view false AXI_29_ARESET_N in std_logic dummy_view false AXI_29_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_29_ARBURST in 1 0 std_logic_vector dummy_view false AXI_29_ARID in 5 0 std_logic_vector dummy_view false AXI_29_ARLEN in 3 0 std_logic_vector dummy_view false AXI_29_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_29_ARVALID in std_logic dummy_view false AXI_29_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_29_AWBURST in 1 0 std_logic_vector dummy_view false AXI_29_AWID in 5 0 std_logic_vector dummy_view false AXI_29_AWLEN in 3 0 std_logic_vector dummy_view false AXI_29_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_29_AWVALID in std_logic dummy_view false AXI_29_RREADY in std_logic dummy_view false AXI_29_BREADY in std_logic dummy_view false AXI_29_WDATA in 255 0 std_logic_vector dummy_view false AXI_29_WLAST in std_logic dummy_view false AXI_29_WSTRB in 31 0 std_logic_vector dummy_view false AXI_29_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_29_WVALID in std_logic dummy_view false AXI_30_ACLK in std_logic dummy_view false AXI_30_ARESET_N in std_logic dummy_view false AXI_30_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_30_ARBURST in 1 0 std_logic_vector dummy_view false AXI_30_ARID in 5 0 std_logic_vector dummy_view false AXI_30_ARLEN in 3 0 std_logic_vector dummy_view false AXI_30_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_30_ARVALID in std_logic dummy_view false AXI_30_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_30_AWBURST in 1 0 std_logic_vector dummy_view false AXI_30_AWID in 5 0 std_logic_vector dummy_view false AXI_30_AWLEN in 3 0 std_logic_vector dummy_view false AXI_30_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_30_AWVALID in std_logic dummy_view false AXI_30_RREADY in std_logic dummy_view false AXI_30_BREADY in std_logic dummy_view false AXI_30_WDATA in 255 0 std_logic_vector dummy_view false AXI_30_WLAST in std_logic dummy_view false AXI_30_WSTRB in 31 0 std_logic_vector dummy_view false AXI_30_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_30_WVALID in std_logic dummy_view false AXI_31_ACLK in std_logic dummy_view false AXI_31_ARESET_N in std_logic dummy_view false AXI_31_ARADDR in 36 0 std_logic_vector dummy_view 0 false AXI_31_ARBURST in 1 0 std_logic_vector dummy_view false AXI_31_ARID in 5 0 std_logic_vector dummy_view false AXI_31_ARLEN in 3 0 std_logic_vector dummy_view false AXI_31_ARSIZE in 2 0 std_logic_vector dummy_view false AXI_31_ARVALID in std_logic dummy_view false AXI_31_AWADDR in 36 0 std_logic_vector dummy_view 0 false AXI_31_AWBURST in 1 0 std_logic_vector dummy_view false AXI_31_AWID in 5 0 std_logic_vector dummy_view false AXI_31_AWLEN in 3 0 std_logic_vector dummy_view false AXI_31_AWSIZE in 2 0 std_logic_vector dummy_view false AXI_31_AWVALID in std_logic dummy_view false AXI_31_RREADY in std_logic dummy_view false AXI_31_BREADY in std_logic dummy_view false AXI_31_WDATA in 255 0 std_logic_vector dummy_view false AXI_31_WLAST in std_logic dummy_view false AXI_31_WSTRB in 31 0 std_logic_vector dummy_view false AXI_31_WDATA_PARITY in 31 0 std_logic_vector dummy_view 0 false AXI_31_WVALID in std_logic dummy_view false dfi_0_clk in std_logic dummy_view 0 true dfi_0_rst_n in std_logic dummy_view 0 true dfi_0_init_start in std_logic dummy_view 0 true dfi_0_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_0_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_0_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_0_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_0_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_0_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_0_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_0_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_0_aw_ck_dis in std_logic dummy_view 0 true dfi_0_lp_pwr_e_req in std_logic dummy_view 0 true dfi_0_lp_sr_e_req in std_logic dummy_view 0 true dfi_0_lp_pwr_x_req in std_logic dummy_view 0 true dfi_0_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_0_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_0_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_0_ctrlupd_ack in std_logic dummy_view 0 true dfi_0_phyupd_req in std_logic dummy_view 0 true dfi_0_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_0_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_1_clk in std_logic dummy_view 0 true dfi_1_rst_n in std_logic dummy_view 0 true dfi_1_init_start in std_logic dummy_view 0 true dfi_1_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_1_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_1_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_1_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_1_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_1_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_1_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_1_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_1_aw_ck_dis in std_logic dummy_view 0 true dfi_1_lp_pwr_e_req in std_logic dummy_view 0 true dfi_1_lp_sr_e_req in std_logic dummy_view 0 true dfi_1_lp_pwr_x_req in std_logic dummy_view 0 true dfi_1_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_1_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_1_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_1_ctrlupd_ack in std_logic dummy_view 0 true dfi_1_phyupd_req in std_logic dummy_view 0 true dfi_1_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_1_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_2_clk in std_logic dummy_view 0 true dfi_2_rst_n in std_logic dummy_view 0 true dfi_2_init_start in std_logic dummy_view 0 true dfi_2_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_2_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_2_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_2_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_2_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_2_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_2_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_2_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_2_aw_ck_dis in std_logic dummy_view 0 true dfi_2_lp_pwr_e_req in std_logic dummy_view 0 true dfi_2_lp_sr_e_req in std_logic dummy_view 0 true dfi_2_lp_pwr_x_req in std_logic dummy_view 0 true dfi_2_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_2_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_2_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_2_ctrlupd_ack in std_logic dummy_view 0 true dfi_2_phyupd_req in std_logic dummy_view 0 true dfi_2_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_2_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_3_clk in std_logic dummy_view 0 true dfi_3_rst_n in std_logic dummy_view 0 true dfi_3_init_start in std_logic dummy_view 0 true dfi_3_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_3_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_3_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_3_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_3_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_3_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_3_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_3_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_3_aw_ck_dis in std_logic dummy_view 0 true dfi_3_lp_pwr_e_req in std_logic dummy_view 0 true dfi_3_lp_sr_e_req in std_logic dummy_view 0 true dfi_3_lp_pwr_x_req in std_logic dummy_view 0 true dfi_3_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_3_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_3_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_3_ctrlupd_ack in std_logic dummy_view 0 true dfi_3_phyupd_req in std_logic dummy_view 0 true dfi_3_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_3_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_4_clk in std_logic dummy_view 0 true dfi_4_rst_n in std_logic dummy_view 0 true dfi_4_init_start in std_logic dummy_view 0 true dfi_4_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_4_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_4_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_4_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_4_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_4_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_4_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_4_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_4_aw_ck_dis in std_logic dummy_view 0 true dfi_4_lp_pwr_e_req in std_logic dummy_view 0 true dfi_4_lp_sr_e_req in std_logic dummy_view 0 true dfi_4_lp_pwr_x_req in std_logic dummy_view 0 true dfi_4_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_4_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_4_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_4_ctrlupd_ack in std_logic dummy_view 0 true dfi_4_phyupd_req in std_logic dummy_view 0 true dfi_4_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_4_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_5_clk in std_logic dummy_view 0 true dfi_5_rst_n in std_logic dummy_view 0 true dfi_5_init_start in std_logic dummy_view 0 true dfi_5_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_5_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_5_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_5_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_5_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_5_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_5_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_5_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_5_aw_ck_dis in std_logic dummy_view 0 true dfi_5_lp_pwr_e_req in std_logic dummy_view 0 true dfi_5_lp_sr_e_req in std_logic dummy_view 0 true dfi_5_lp_pwr_x_req in std_logic dummy_view 0 true dfi_5_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_5_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_5_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_5_ctrlupd_ack in std_logic dummy_view 0 true dfi_5_phyupd_req in std_logic dummy_view 0 true dfi_5_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_5_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_6_clk in std_logic dummy_view 0 true dfi_6_rst_n in std_logic dummy_view 0 true dfi_6_init_start in std_logic dummy_view 0 true dfi_6_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_6_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_6_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_6_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_6_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_6_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_6_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_6_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_6_aw_ck_dis in std_logic dummy_view 0 true dfi_6_lp_pwr_e_req in std_logic dummy_view 0 true dfi_6_lp_sr_e_req in std_logic dummy_view 0 true dfi_6_lp_pwr_x_req in std_logic dummy_view 0 true dfi_6_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_6_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_6_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_6_ctrlupd_ack in std_logic dummy_view 0 true dfi_6_phyupd_req in std_logic dummy_view 0 true dfi_6_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_6_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_7_clk in std_logic dummy_view 0 true dfi_7_rst_n in std_logic dummy_view 0 true dfi_7_init_start in std_logic dummy_view 0 true dfi_7_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_7_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_7_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_7_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_7_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_7_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_7_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_7_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_7_aw_ck_dis in std_logic dummy_view 0 true dfi_7_lp_pwr_e_req in std_logic dummy_view 0 true dfi_7_lp_sr_e_req in std_logic dummy_view 0 true dfi_7_lp_pwr_x_req in std_logic dummy_view 0 true dfi_7_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_7_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_7_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_7_ctrlupd_ack in std_logic dummy_view 0 true dfi_7_phyupd_req in std_logic dummy_view 0 true dfi_7_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_7_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_8_clk in std_logic dummy_view 0 true dfi_8_rst_n in std_logic dummy_view 0 true dfi_8_init_start in std_logic dummy_view 0 true dfi_8_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_8_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_8_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_8_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_8_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_8_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_8_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_8_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_8_aw_ck_dis in std_logic dummy_view 0 true dfi_8_lp_pwr_e_req in std_logic dummy_view 0 true dfi_8_lp_sr_e_req in std_logic dummy_view 0 true dfi_8_lp_pwr_x_req in std_logic dummy_view 0 true dfi_8_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_8_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_8_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_8_ctrlupd_ack in std_logic dummy_view 0 true dfi_8_phyupd_req in std_logic dummy_view 0 true dfi_8_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_8_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_9_clk in std_logic dummy_view 0 true dfi_9_rst_n in std_logic dummy_view 0 true dfi_9_init_start in std_logic dummy_view 0 true dfi_9_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_9_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_9_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_9_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_9_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_9_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_9_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_9_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_9_aw_ck_dis in std_logic dummy_view 0 true dfi_9_lp_pwr_e_req in std_logic dummy_view 0 true dfi_9_lp_sr_e_req in std_logic dummy_view 0 true dfi_9_lp_pwr_x_req in std_logic dummy_view 0 true dfi_9_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_9_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_9_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_9_ctrlupd_ack in std_logic dummy_view 0 true dfi_9_phyupd_req in std_logic dummy_view 0 true dfi_9_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_9_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_10_clk in std_logic dummy_view 0 true dfi_10_rst_n in std_logic dummy_view 0 true dfi_10_init_start in std_logic dummy_view 0 true dfi_10_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_10_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_10_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_10_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_10_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_10_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_10_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_10_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_10_aw_ck_dis in std_logic dummy_view 0 true dfi_10_lp_pwr_e_req in std_logic dummy_view 0 true dfi_10_lp_sr_e_req in std_logic dummy_view 0 true dfi_10_lp_pwr_x_req in std_logic dummy_view 0 true dfi_10_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_10_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_10_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_10_ctrlupd_ack in std_logic dummy_view 0 true dfi_10_phyupd_req in std_logic dummy_view 0 true dfi_10_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_10_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_11_clk in std_logic dummy_view 0 true dfi_11_rst_n in std_logic dummy_view 0 true dfi_11_init_start in std_logic dummy_view 0 true dfi_11_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_11_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_11_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_11_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_11_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_11_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_11_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_11_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_11_aw_ck_dis in std_logic dummy_view 0 true dfi_11_lp_pwr_e_req in std_logic dummy_view 0 true dfi_11_lp_sr_e_req in std_logic dummy_view 0 true dfi_11_lp_pwr_x_req in std_logic dummy_view 0 true dfi_11_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_11_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_11_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_11_ctrlupd_ack in std_logic dummy_view 0 true dfi_11_phyupd_req in std_logic dummy_view 0 true dfi_11_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_11_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_12_clk in std_logic dummy_view 0 true dfi_12_rst_n in std_logic dummy_view 0 true dfi_12_init_start in std_logic dummy_view 0 true dfi_12_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_12_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_12_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_12_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_12_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_12_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_12_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_12_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_12_aw_ck_dis in std_logic dummy_view 0 true dfi_12_lp_pwr_e_req in std_logic dummy_view 0 true dfi_12_lp_sr_e_req in std_logic dummy_view 0 true dfi_12_lp_pwr_x_req in std_logic dummy_view 0 true dfi_12_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_12_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_12_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_12_ctrlupd_ack in std_logic dummy_view 0 true dfi_12_phyupd_req in std_logic dummy_view 0 true dfi_12_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_12_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_13_clk in std_logic dummy_view 0 true dfi_13_rst_n in std_logic dummy_view 0 true dfi_13_init_start in std_logic dummy_view 0 true dfi_13_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_13_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_13_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_13_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_13_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_13_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_13_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_13_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_13_aw_ck_dis in std_logic dummy_view 0 true dfi_13_lp_pwr_e_req in std_logic dummy_view 0 true dfi_13_lp_sr_e_req in std_logic dummy_view 0 true dfi_13_lp_pwr_x_req in std_logic dummy_view 0 true dfi_13_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_13_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_13_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_13_ctrlupd_ack in std_logic dummy_view 0 true dfi_13_phyupd_req in std_logic dummy_view 0 true dfi_13_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_13_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_14_clk in std_logic dummy_view 0 true dfi_14_rst_n in std_logic dummy_view 0 true dfi_14_init_start in std_logic dummy_view 0 true dfi_14_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_14_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_14_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_14_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_14_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_14_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_14_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_14_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_14_aw_ck_dis in std_logic dummy_view 0 true dfi_14_lp_pwr_e_req in std_logic dummy_view 0 true dfi_14_lp_sr_e_req in std_logic dummy_view 0 true dfi_14_lp_pwr_x_req in std_logic dummy_view 0 true dfi_14_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_14_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_14_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_14_ctrlupd_ack in std_logic dummy_view 0 true dfi_14_phyupd_req in std_logic dummy_view 0 true dfi_14_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_14_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_15_clk in std_logic dummy_view 0 true dfi_15_rst_n in std_logic dummy_view 0 true dfi_15_init_start in std_logic dummy_view 0 true dfi_15_aw_ck_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_15_aw_cke_p0 in 1 0 std_logic_vector dummy_view 0 true dfi_15_aw_row_p0 in 11 0 std_logic_vector dummy_view 0 true dfi_15_aw_col_p0 in 15 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_p0 in 255 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_mask_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_dbi_p0 in 31 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_par_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_dq_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_par_en_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_15_aw_ck_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_15_aw_cke_p1 in 1 0 std_logic_vector dummy_view 0 true dfi_15_aw_row_p1 in 11 0 std_logic_vector dummy_view 0 true dfi_15_aw_col_p1 in 15 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_p1 in 255 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_mask_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_dbi_p1 in 31 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_par_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_dq_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_par_en_p1 in 7 0 std_logic_vector dummy_view 0 true dfi_15_aw_ck_dis in std_logic dummy_view 0 true dfi_15_lp_pwr_e_req in std_logic dummy_view 0 true dfi_15_lp_sr_e_req in std_logic dummy_view 0 true dfi_15_lp_pwr_x_req in std_logic dummy_view 0 true dfi_15_aw_tx_indx_ld in std_logic dummy_view 0 true dfi_15_dw_tx_indx_ld in std_logic dummy_view 0 true dfi_15_dw_rx_indx_ld in std_logic dummy_view 0 true dfi_15_ctrlupd_ack in std_logic dummy_view 0 true dfi_15_phyupd_req in std_logic dummy_view 0 true dfi_15_dw_wrdata_dqs_p0 in 7 0 std_logic_vector dummy_view 0 true dfi_15_dw_wrdata_dqs_p1 in 7 0 std_logic_vector dummy_view 0 true APB_0_PWDATA in 31 0 std_logic_vector dummy_view false APB_0_PADDR in 21 0 std_logic_vector dummy_view false APB_0_PCLK in std_logic dummy_view APB_0_PENABLE in std_logic dummy_view false APB_0_PRESET_N in std_logic dummy_view APB_0_PSEL in std_logic dummy_view false APB_0_PWRITE in std_logic dummy_view false APB_1_PWDATA in 31 0 std_logic_vector dummy_view false APB_1_PADDR in 21 0 std_logic_vector dummy_view false APB_1_PCLK in std_logic dummy_view APB_1_PENABLE in std_logic dummy_view false APB_1_PRESET_N in std_logic dummy_view APB_1_PSEL in std_logic dummy_view false APB_1_PWRITE in std_logic dummy_view false AXI_00_ARREADY out std_logic dummy_view false AXI_00_AWREADY out std_logic dummy_view false AXI_00_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_00_RDATA out 255 0 std_logic_vector dummy_view false AXI_00_RID out 5 0 std_logic_vector dummy_view false AXI_00_RLAST out std_logic dummy_view false AXI_00_RRESP out 1 0 std_logic_vector dummy_view false AXI_00_RVALID out std_logic dummy_view false AXI_00_WREADY out std_logic dummy_view false AXI_00_BID out 5 0 std_logic_vector dummy_view false AXI_00_BRESP out 1 0 std_logic_vector dummy_view false AXI_00_BVALID out std_logic dummy_view false AXI_01_ARREADY out std_logic dummy_view false AXI_01_AWREADY out std_logic dummy_view false AXI_01_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_01_RDATA out 255 0 std_logic_vector dummy_view false AXI_01_RID out 5 0 std_logic_vector dummy_view false AXI_01_RLAST out std_logic dummy_view false AXI_01_RRESP out 1 0 std_logic_vector dummy_view false AXI_01_RVALID out std_logic dummy_view false AXI_01_WREADY out std_logic dummy_view false AXI_01_BID out 5 0 std_logic_vector dummy_view false AXI_01_BRESP out 1 0 std_logic_vector dummy_view false AXI_01_BVALID out std_logic dummy_view false AXI_02_ARREADY out std_logic dummy_view false AXI_02_AWREADY out std_logic dummy_view false AXI_02_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_02_RDATA out 255 0 std_logic_vector dummy_view false AXI_02_RID out 5 0 std_logic_vector dummy_view false AXI_02_RLAST out std_logic dummy_view false AXI_02_RRESP out 1 0 std_logic_vector dummy_view false AXI_02_RVALID out std_logic dummy_view false AXI_02_WREADY out std_logic dummy_view false AXI_02_BID out 5 0 std_logic_vector dummy_view false AXI_02_BRESP out 1 0 std_logic_vector dummy_view false AXI_02_BVALID out std_logic dummy_view false AXI_03_ARREADY out std_logic dummy_view false AXI_03_AWREADY out std_logic dummy_view false AXI_03_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_03_RDATA out 255 0 std_logic_vector dummy_view false AXI_03_RID out 5 0 std_logic_vector dummy_view false AXI_03_RLAST out std_logic dummy_view false AXI_03_RRESP out 1 0 std_logic_vector dummy_view false AXI_03_RVALID out std_logic dummy_view false AXI_03_WREADY out std_logic dummy_view false AXI_03_BID out 5 0 std_logic_vector dummy_view false AXI_03_BRESP out 1 0 std_logic_vector dummy_view false AXI_03_BVALID out std_logic dummy_view false AXI_04_ARREADY out std_logic dummy_view false AXI_04_AWREADY out std_logic dummy_view false AXI_04_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_04_RDATA out 255 0 std_logic_vector dummy_view false AXI_04_RID out 5 0 std_logic_vector dummy_view false AXI_04_RLAST out std_logic dummy_view false AXI_04_RRESP out 1 0 std_logic_vector dummy_view false AXI_04_RVALID out std_logic dummy_view false AXI_04_WREADY out std_logic dummy_view false AXI_04_BID out 5 0 std_logic_vector dummy_view false AXI_04_BRESP out 1 0 std_logic_vector dummy_view false AXI_04_BVALID out std_logic dummy_view false AXI_05_ARREADY out std_logic dummy_view false AXI_05_AWREADY out std_logic dummy_view false AXI_05_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_05_RDATA out 255 0 std_logic_vector dummy_view false AXI_05_RID out 5 0 std_logic_vector dummy_view false AXI_05_RLAST out std_logic dummy_view false AXI_05_RRESP out 1 0 std_logic_vector dummy_view false AXI_05_RVALID out std_logic dummy_view false AXI_05_WREADY out std_logic dummy_view false AXI_05_BID out 5 0 std_logic_vector dummy_view false AXI_05_BRESP out 1 0 std_logic_vector dummy_view false AXI_05_BVALID out std_logic dummy_view false AXI_06_ARREADY out std_logic dummy_view false AXI_06_AWREADY out std_logic dummy_view false AXI_06_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_06_RDATA out 255 0 std_logic_vector dummy_view false AXI_06_RID out 5 0 std_logic_vector dummy_view false AXI_06_RLAST out std_logic dummy_view false AXI_06_RRESP out 1 0 std_logic_vector dummy_view false AXI_06_RVALID out std_logic dummy_view false AXI_06_WREADY out std_logic dummy_view false AXI_06_BID out 5 0 std_logic_vector dummy_view false AXI_06_BRESP out 1 0 std_logic_vector dummy_view false AXI_06_BVALID out std_logic dummy_view false AXI_07_ARREADY out std_logic dummy_view false AXI_07_AWREADY out std_logic dummy_view false AXI_07_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_07_RDATA out 255 0 std_logic_vector dummy_view false AXI_07_RID out 5 0 std_logic_vector dummy_view false AXI_07_RLAST out std_logic dummy_view false AXI_07_RRESP out 1 0 std_logic_vector dummy_view false AXI_07_RVALID out std_logic dummy_view false AXI_07_WREADY out std_logic dummy_view false AXI_07_BID out 5 0 std_logic_vector dummy_view false AXI_07_BRESP out 1 0 std_logic_vector dummy_view false AXI_07_BVALID out std_logic dummy_view false AXI_08_ARREADY out std_logic dummy_view false AXI_08_AWREADY out std_logic dummy_view false AXI_08_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_08_RDATA out 255 0 std_logic_vector dummy_view false AXI_08_RID out 5 0 std_logic_vector dummy_view false AXI_08_RLAST out std_logic dummy_view false AXI_08_RRESP out 1 0 std_logic_vector dummy_view false AXI_08_RVALID out std_logic dummy_view false AXI_08_WREADY out std_logic dummy_view false AXI_08_BID out 5 0 std_logic_vector dummy_view false AXI_08_BRESP out 1 0 std_logic_vector dummy_view false AXI_08_BVALID out std_logic dummy_view false AXI_09_ARREADY out std_logic dummy_view false AXI_09_AWREADY out std_logic dummy_view false AXI_09_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_09_RDATA out 255 0 std_logic_vector dummy_view false AXI_09_RID out 5 0 std_logic_vector dummy_view false AXI_09_RLAST out std_logic dummy_view false AXI_09_RRESP out 1 0 std_logic_vector dummy_view false AXI_09_RVALID out std_logic dummy_view false AXI_09_WREADY out std_logic dummy_view false AXI_09_BID out 5 0 std_logic_vector dummy_view false AXI_09_BRESP out 1 0 std_logic_vector dummy_view false AXI_09_BVALID out std_logic dummy_view false AXI_10_ARREADY out std_logic dummy_view false AXI_10_AWREADY out std_logic dummy_view false AXI_10_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_10_RDATA out 255 0 std_logic_vector dummy_view false AXI_10_RID out 5 0 std_logic_vector dummy_view false AXI_10_RLAST out std_logic dummy_view false AXI_10_RRESP out 1 0 std_logic_vector dummy_view false AXI_10_RVALID out std_logic dummy_view false AXI_10_WREADY out std_logic dummy_view false AXI_10_BID out 5 0 std_logic_vector dummy_view false AXI_10_BRESP out 1 0 std_logic_vector dummy_view false AXI_10_BVALID out std_logic dummy_view false AXI_11_ARREADY out std_logic dummy_view false AXI_11_AWREADY out std_logic dummy_view false AXI_11_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_11_RDATA out 255 0 std_logic_vector dummy_view false AXI_11_RID out 5 0 std_logic_vector dummy_view false AXI_11_RLAST out std_logic dummy_view false AXI_11_RRESP out 1 0 std_logic_vector dummy_view false AXI_11_RVALID out std_logic dummy_view false AXI_11_WREADY out std_logic dummy_view false AXI_11_BID out 5 0 std_logic_vector dummy_view false AXI_11_BRESP out 1 0 std_logic_vector dummy_view false AXI_11_BVALID out std_logic dummy_view false AXI_12_ARREADY out std_logic dummy_view false AXI_12_AWREADY out std_logic dummy_view false AXI_12_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_12_RDATA out 255 0 std_logic_vector dummy_view false AXI_12_RID out 5 0 std_logic_vector dummy_view false AXI_12_RLAST out std_logic dummy_view false AXI_12_RRESP out 1 0 std_logic_vector dummy_view false AXI_12_RVALID out std_logic dummy_view false AXI_12_WREADY out std_logic dummy_view false AXI_12_BID out 5 0 std_logic_vector dummy_view false AXI_12_BRESP out 1 0 std_logic_vector dummy_view false AXI_12_BVALID out std_logic dummy_view false AXI_13_ARREADY out std_logic dummy_view false AXI_13_AWREADY out std_logic dummy_view false AXI_13_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_13_RDATA out 255 0 std_logic_vector dummy_view false AXI_13_RID out 5 0 std_logic_vector dummy_view false AXI_13_RLAST out std_logic dummy_view false AXI_13_RRESP out 1 0 std_logic_vector dummy_view false AXI_13_RVALID out std_logic dummy_view false AXI_13_WREADY out std_logic dummy_view false AXI_13_BID out 5 0 std_logic_vector dummy_view false AXI_13_BRESP out 1 0 std_logic_vector dummy_view false AXI_13_BVALID out std_logic dummy_view false AXI_14_ARREADY out std_logic dummy_view false AXI_14_AWREADY out std_logic dummy_view false AXI_14_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_14_RDATA out 255 0 std_logic_vector dummy_view false AXI_14_RID out 5 0 std_logic_vector dummy_view false AXI_14_RLAST out std_logic dummy_view false AXI_14_RRESP out 1 0 std_logic_vector dummy_view false AXI_14_RVALID out std_logic dummy_view false AXI_14_WREADY out std_logic dummy_view false AXI_14_BID out 5 0 std_logic_vector dummy_view false AXI_14_BRESP out 1 0 std_logic_vector dummy_view false AXI_14_BVALID out std_logic dummy_view false AXI_15_ARREADY out std_logic dummy_view false AXI_15_AWREADY out std_logic dummy_view false AXI_15_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_15_RDATA out 255 0 std_logic_vector dummy_view false AXI_15_RID out 5 0 std_logic_vector dummy_view false AXI_15_RLAST out std_logic dummy_view false AXI_15_RRESP out 1 0 std_logic_vector dummy_view false AXI_15_RVALID out std_logic dummy_view false AXI_15_WREADY out std_logic dummy_view false AXI_15_BID out 5 0 std_logic_vector dummy_view false AXI_15_BRESP out 1 0 std_logic_vector dummy_view false AXI_15_BVALID out std_logic dummy_view false AXI_16_ARREADY out std_logic dummy_view false AXI_16_AWREADY out std_logic dummy_view false AXI_16_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_16_RDATA out 255 0 std_logic_vector dummy_view false AXI_16_RID out 5 0 std_logic_vector dummy_view false AXI_16_RLAST out std_logic dummy_view false AXI_16_RRESP out 1 0 std_logic_vector dummy_view false AXI_16_RVALID out std_logic dummy_view false AXI_16_WREADY out std_logic dummy_view false AXI_16_BID out 5 0 std_logic_vector dummy_view false AXI_16_BRESP out 1 0 std_logic_vector dummy_view false AXI_16_BVALID out std_logic dummy_view false AXI_17_ARREADY out std_logic dummy_view false AXI_17_AWREADY out std_logic dummy_view false AXI_17_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_17_RDATA out 255 0 std_logic_vector dummy_view false AXI_17_RID out 5 0 std_logic_vector dummy_view false AXI_17_RLAST out std_logic dummy_view false AXI_17_RRESP out 1 0 std_logic_vector dummy_view false AXI_17_RVALID out std_logic dummy_view false AXI_17_WREADY out std_logic dummy_view false AXI_17_BID out 5 0 std_logic_vector dummy_view false AXI_17_BRESP out 1 0 std_logic_vector dummy_view false AXI_17_BVALID out std_logic dummy_view false AXI_18_ARREADY out std_logic dummy_view false AXI_18_AWREADY out std_logic dummy_view false AXI_18_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_18_RDATA out 255 0 std_logic_vector dummy_view false AXI_18_RID out 5 0 std_logic_vector dummy_view false AXI_18_RLAST out std_logic dummy_view false AXI_18_RRESP out 1 0 std_logic_vector dummy_view false AXI_18_RVALID out std_logic dummy_view false AXI_18_WREADY out std_logic dummy_view false AXI_18_BID out 5 0 std_logic_vector dummy_view false AXI_18_BRESP out 1 0 std_logic_vector dummy_view false AXI_18_BVALID out std_logic dummy_view false AXI_19_ARREADY out std_logic dummy_view false AXI_19_AWREADY out std_logic dummy_view false AXI_19_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_19_RDATA out 255 0 std_logic_vector dummy_view false AXI_19_RID out 5 0 std_logic_vector dummy_view false AXI_19_RLAST out std_logic dummy_view false AXI_19_RRESP out 1 0 std_logic_vector dummy_view false AXI_19_RVALID out std_logic dummy_view false AXI_19_WREADY out std_logic dummy_view false AXI_19_BID out 5 0 std_logic_vector dummy_view false AXI_19_BRESP out 1 0 std_logic_vector dummy_view false AXI_19_BVALID out std_logic dummy_view false AXI_20_ARREADY out std_logic dummy_view false AXI_20_AWREADY out std_logic dummy_view false AXI_20_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_20_RDATA out 255 0 std_logic_vector dummy_view false AXI_20_RID out 5 0 std_logic_vector dummy_view false AXI_20_RLAST out std_logic dummy_view false AXI_20_RRESP out 1 0 std_logic_vector dummy_view false AXI_20_RVALID out std_logic dummy_view false AXI_20_WREADY out std_logic dummy_view false AXI_20_BID out 5 0 std_logic_vector dummy_view false AXI_20_BRESP out 1 0 std_logic_vector dummy_view false AXI_20_BVALID out std_logic dummy_view false AXI_21_ARREADY out std_logic dummy_view false AXI_21_AWREADY out std_logic dummy_view false AXI_21_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_21_RDATA out 255 0 std_logic_vector dummy_view false AXI_21_RID out 5 0 std_logic_vector dummy_view false AXI_21_RLAST out std_logic dummy_view false AXI_21_RRESP out 1 0 std_logic_vector dummy_view false AXI_21_RVALID out std_logic dummy_view false AXI_21_WREADY out std_logic dummy_view false AXI_21_BID out 5 0 std_logic_vector dummy_view false AXI_21_BRESP out 1 0 std_logic_vector dummy_view false AXI_21_BVALID out std_logic dummy_view false AXI_22_ARREADY out std_logic dummy_view false AXI_22_AWREADY out std_logic dummy_view false AXI_22_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_22_RDATA out 255 0 std_logic_vector dummy_view false AXI_22_RID out 5 0 std_logic_vector dummy_view false AXI_22_RLAST out std_logic dummy_view false AXI_22_RRESP out 1 0 std_logic_vector dummy_view false AXI_22_RVALID out std_logic dummy_view false AXI_22_WREADY out std_logic dummy_view false AXI_22_BID out 5 0 std_logic_vector dummy_view false AXI_22_BRESP out 1 0 std_logic_vector dummy_view false AXI_22_BVALID out std_logic dummy_view false AXI_23_ARREADY out std_logic dummy_view false AXI_23_AWREADY out std_logic dummy_view false AXI_23_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_23_RDATA out 255 0 std_logic_vector dummy_view false AXI_23_RID out 5 0 std_logic_vector dummy_view false AXI_23_RLAST out std_logic dummy_view false AXI_23_RRESP out 1 0 std_logic_vector dummy_view false AXI_23_RVALID out std_logic dummy_view false AXI_23_WREADY out std_logic dummy_view false AXI_23_BID out 5 0 std_logic_vector dummy_view false AXI_23_BRESP out 1 0 std_logic_vector dummy_view false AXI_23_BVALID out std_logic dummy_view false AXI_24_ARREADY out std_logic dummy_view false AXI_24_AWREADY out std_logic dummy_view false AXI_24_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_24_RDATA out 255 0 std_logic_vector dummy_view false AXI_24_RID out 5 0 std_logic_vector dummy_view false AXI_24_RLAST out std_logic dummy_view false AXI_24_RRESP out 1 0 std_logic_vector dummy_view false AXI_24_RVALID out std_logic dummy_view false AXI_24_WREADY out std_logic dummy_view false AXI_24_BID out 5 0 std_logic_vector dummy_view false AXI_24_BRESP out 1 0 std_logic_vector dummy_view false AXI_24_BVALID out std_logic dummy_view false AXI_25_ARREADY out std_logic dummy_view false AXI_25_AWREADY out std_logic dummy_view false AXI_25_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_25_RDATA out 255 0 std_logic_vector dummy_view false AXI_25_RID out 5 0 std_logic_vector dummy_view false AXI_25_RLAST out std_logic dummy_view false AXI_25_RRESP out 1 0 std_logic_vector dummy_view false AXI_25_RVALID out std_logic dummy_view false AXI_25_WREADY out std_logic dummy_view false AXI_25_BID out 5 0 std_logic_vector dummy_view false AXI_25_BRESP out 1 0 std_logic_vector dummy_view false AXI_25_BVALID out std_logic dummy_view false AXI_26_ARREADY out std_logic dummy_view false AXI_26_AWREADY out std_logic dummy_view false AXI_26_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_26_RDATA out 255 0 std_logic_vector dummy_view false AXI_26_RID out 5 0 std_logic_vector dummy_view false AXI_26_RLAST out std_logic dummy_view false AXI_26_RRESP out 1 0 std_logic_vector dummy_view false AXI_26_RVALID out std_logic dummy_view false AXI_26_WREADY out std_logic dummy_view false AXI_26_BID out 5 0 std_logic_vector dummy_view false AXI_26_BRESP out 1 0 std_logic_vector dummy_view false AXI_26_BVALID out std_logic dummy_view false AXI_27_ARREADY out std_logic dummy_view false AXI_27_AWREADY out std_logic dummy_view false AXI_27_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_27_RDATA out 255 0 std_logic_vector dummy_view false AXI_27_RID out 5 0 std_logic_vector dummy_view false AXI_27_RLAST out std_logic dummy_view false AXI_27_RRESP out 1 0 std_logic_vector dummy_view false AXI_27_RVALID out std_logic dummy_view false AXI_27_WREADY out std_logic dummy_view false AXI_27_BID out 5 0 std_logic_vector dummy_view false AXI_27_BRESP out 1 0 std_logic_vector dummy_view false AXI_27_BVALID out std_logic dummy_view false AXI_28_ARREADY out std_logic dummy_view false AXI_28_AWREADY out std_logic dummy_view false AXI_28_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_28_RDATA out 255 0 std_logic_vector dummy_view false AXI_28_RID out 5 0 std_logic_vector dummy_view false AXI_28_RLAST out std_logic dummy_view false AXI_28_RRESP out 1 0 std_logic_vector dummy_view false AXI_28_RVALID out std_logic dummy_view false AXI_28_WREADY out std_logic dummy_view false AXI_28_BID out 5 0 std_logic_vector dummy_view false AXI_28_BRESP out 1 0 std_logic_vector dummy_view false AXI_28_BVALID out std_logic dummy_view false AXI_29_ARREADY out std_logic dummy_view false AXI_29_AWREADY out std_logic dummy_view false AXI_29_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_29_RDATA out 255 0 std_logic_vector dummy_view false AXI_29_RID out 5 0 std_logic_vector dummy_view false AXI_29_RLAST out std_logic dummy_view false AXI_29_RRESP out 1 0 std_logic_vector dummy_view false AXI_29_RVALID out std_logic dummy_view false AXI_29_WREADY out std_logic dummy_view false AXI_29_BID out 5 0 std_logic_vector dummy_view false AXI_29_BRESP out 1 0 std_logic_vector dummy_view false AXI_29_BVALID out std_logic dummy_view false AXI_30_ARREADY out std_logic dummy_view false AXI_30_AWREADY out std_logic dummy_view false AXI_30_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_30_RDATA out 255 0 std_logic_vector dummy_view false AXI_30_RID out 5 0 std_logic_vector dummy_view false AXI_30_RLAST out std_logic dummy_view false AXI_30_RRESP out 1 0 std_logic_vector dummy_view false AXI_30_RVALID out std_logic dummy_view false AXI_30_WREADY out std_logic dummy_view false AXI_30_BID out 5 0 std_logic_vector dummy_view false AXI_30_BRESP out 1 0 std_logic_vector dummy_view false AXI_30_BVALID out std_logic dummy_view false AXI_31_ARREADY out std_logic dummy_view false AXI_31_AWREADY out std_logic dummy_view false AXI_31_RDATA_PARITY out 31 0 std_logic_vector dummy_view false AXI_31_RDATA out 255 0 std_logic_vector dummy_view false AXI_31_RID out 5 0 std_logic_vector dummy_view false AXI_31_RLAST out std_logic dummy_view false AXI_31_RRESP out 1 0 std_logic_vector dummy_view false AXI_31_RVALID out std_logic dummy_view false AXI_31_WREADY out std_logic dummy_view false AXI_31_BID out 5 0 std_logic_vector dummy_view false AXI_31_BRESP out 1 0 std_logic_vector dummy_view false AXI_31_BVALID out std_logic dummy_view false dfi_0_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_0_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_0_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_0_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_0_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_0_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_0_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_0_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_0_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_0_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_0_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_0_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_0_ctrlupd_req out std_logic dummy_view 0 true dfi_0_phyupd_ack out std_logic dummy_view 0 true dfi_0_clk_init out std_logic dummy_view 0 true dfi_0_init_complete out std_logic dummy_view 0 true dfi_0_out_rst_n out std_logic dummy_view 0 true dfi_1_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_1_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_1_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_1_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_1_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_1_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_1_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_1_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_1_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_1_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_1_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_1_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_1_ctrlupd_req out std_logic dummy_view 0 true dfi_1_phyupd_ack out std_logic dummy_view 0 true dfi_1_clk_init out std_logic dummy_view 0 true dfi_1_init_complete out std_logic dummy_view 0 true dfi_1_out_rst_n out std_logic dummy_view 0 true dfi_2_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_2_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_2_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_2_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_2_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_2_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_2_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_2_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_2_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_2_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_2_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_2_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_2_ctrlupd_req out std_logic dummy_view 0 true dfi_2_phyupd_ack out std_logic dummy_view 0 true dfi_2_clk_init out std_logic dummy_view 0 true dfi_2_init_complete out std_logic dummy_view 0 true dfi_2_out_rst_n out std_logic dummy_view 0 true dfi_3_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_3_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_3_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_3_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_3_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_3_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_3_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_3_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_3_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_3_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_3_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_3_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_3_ctrlupd_req out std_logic dummy_view 0 true dfi_3_phyupd_ack out std_logic dummy_view 0 true dfi_3_clk_init out std_logic dummy_view 0 true dfi_3_init_complete out std_logic dummy_view 0 true dfi_3_out_rst_n out std_logic dummy_view 0 true dfi_4_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_4_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_4_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_4_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_4_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_4_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_4_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_4_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_4_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_4_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_4_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_4_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_4_ctrlupd_req out std_logic dummy_view 0 true dfi_4_phyupd_ack out std_logic dummy_view 0 true dfi_4_clk_init out std_logic dummy_view 0 true dfi_4_init_complete out std_logic dummy_view 0 true dfi_4_out_rst_n out std_logic dummy_view 0 true dfi_5_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_5_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_5_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_5_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_5_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_5_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_5_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_5_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_5_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_5_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_5_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_5_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_5_ctrlupd_req out std_logic dummy_view 0 true dfi_5_phyupd_ack out std_logic dummy_view 0 true dfi_5_clk_init out std_logic dummy_view 0 true dfi_5_init_complete out std_logic dummy_view 0 true dfi_5_out_rst_n out std_logic dummy_view 0 true dfi_6_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_6_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_6_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_6_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_6_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_6_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_6_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_6_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_6_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_6_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_6_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_6_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_6_ctrlupd_req out std_logic dummy_view 0 true dfi_6_phyupd_ack out std_logic dummy_view 0 true dfi_6_clk_init out std_logic dummy_view 0 true dfi_6_init_complete out std_logic dummy_view 0 true dfi_6_out_rst_n out std_logic dummy_view 0 true dfi_7_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_7_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_7_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_7_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_7_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_7_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_7_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_7_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_7_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_7_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_7_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_7_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_7_ctrlupd_req out std_logic dummy_view 0 true dfi_7_phyupd_ack out std_logic dummy_view 0 true dfi_7_clk_init out std_logic dummy_view 0 true dfi_7_init_complete out std_logic dummy_view 0 true dfi_7_out_rst_n out std_logic dummy_view 0 true dfi_8_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_8_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_8_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_8_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_8_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_8_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_8_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_8_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_8_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_8_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_8_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_8_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_8_ctrlupd_req out std_logic dummy_view 0 true dfi_8_phyupd_ack out std_logic dummy_view 0 true dfi_8_clk_init out std_logic dummy_view 0 true dfi_8_init_complete out std_logic dummy_view 0 true dfi_8_out_rst_n out std_logic dummy_view 0 true dfi_9_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_9_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_9_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_9_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_9_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_9_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_9_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_9_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_9_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_9_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_9_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_9_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_9_ctrlupd_req out std_logic dummy_view 0 true dfi_9_phyupd_ack out std_logic dummy_view 0 true dfi_9_clk_init out std_logic dummy_view 0 true dfi_9_init_complete out std_logic dummy_view 0 true dfi_9_out_rst_n out std_logic dummy_view 0 true dfi_10_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_10_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_10_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_10_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_10_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_10_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_10_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_10_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_10_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_10_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_10_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_10_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_10_ctrlupd_req out std_logic dummy_view 0 true dfi_10_phyupd_ack out std_logic dummy_view 0 true dfi_10_clk_init out std_logic dummy_view 0 true dfi_10_init_complete out std_logic dummy_view 0 true dfi_10_out_rst_n out std_logic dummy_view 0 true dfi_11_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_11_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_11_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_11_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_11_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_11_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_11_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_11_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_11_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_11_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_11_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_11_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_11_ctrlupd_req out std_logic dummy_view 0 true dfi_11_phyupd_ack out std_logic dummy_view 0 true dfi_11_clk_init out std_logic dummy_view 0 true dfi_11_init_complete out std_logic dummy_view 0 true dfi_11_out_rst_n out std_logic dummy_view 0 true dfi_12_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_12_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_12_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_12_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_12_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_12_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_12_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_12_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_12_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_12_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_12_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_12_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_12_ctrlupd_req out std_logic dummy_view 0 true dfi_12_phyupd_ack out std_logic dummy_view 0 true dfi_12_clk_init out std_logic dummy_view 0 true dfi_12_init_complete out std_logic dummy_view 0 true dfi_12_out_rst_n out std_logic dummy_view 0 true dfi_13_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_13_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_13_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_13_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_13_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_13_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_13_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_13_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_13_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_13_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_13_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_13_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_13_ctrlupd_req out std_logic dummy_view 0 true dfi_13_phyupd_ack out std_logic dummy_view 0 true dfi_13_clk_init out std_logic dummy_view 0 true dfi_13_init_complete out std_logic dummy_view 0 true dfi_13_out_rst_n out std_logic dummy_view 0 true dfi_14_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_14_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_14_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_14_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_14_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_14_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_14_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_14_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_14_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_14_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_14_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_14_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_14_ctrlupd_req out std_logic dummy_view 0 true dfi_14_phyupd_ack out std_logic dummy_view 0 true dfi_14_clk_init out std_logic dummy_view 0 true dfi_14_init_complete out std_logic dummy_view 0 true dfi_14_out_rst_n out std_logic dummy_view 0 true dfi_15_dw_rddata_p0 out 255 0 std_logic_vector dummy_view 0 true dfi_15_dw_rddata_dm_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_15_dw_rddata_dbi_p0 out 31 0 std_logic_vector dummy_view 0 true dfi_15_dw_rddata_par_p0 out 7 0 std_logic_vector dummy_view 0 true dfi_15_dw_rddata_p1 out 255 0 std_logic_vector dummy_view 0 true dfi_15_dw_rddata_dm_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_15_dw_rddata_dbi_p1 out 31 0 std_logic_vector dummy_view 0 true dfi_15_dw_rddata_par_p1 out 7 0 std_logic_vector dummy_view 0 true dfi_15_dbi_byte_disable out 15 0 std_logic_vector dummy_view 0 true dfi_15_dw_rddata_valid out 3 0 std_logic_vector dummy_view 0 true dfi_15_dw_derr_n out 7 0 std_logic_vector dummy_view 0 true dfi_15_aw_aerr_n out 1 0 std_logic_vector dummy_view 0 true dfi_15_ctrlupd_req out std_logic dummy_view 0 true dfi_15_phyupd_ack out std_logic dummy_view 0 true dfi_15_clk_init out std_logic dummy_view 0 true dfi_15_init_complete out std_logic dummy_view 0 true dfi_15_out_rst_n out std_logic dummy_view 0 true APB_0_PRDATA out 31 0 std_logic_vector dummy_view false APB_0_PREADY out std_logic dummy_view false APB_0_PSLVERR out std_logic dummy_view false APB_1_PRDATA out 31 0 std_logic_vector dummy_view false APB_1_PREADY out std_logic dummy_view false APB_1_PSLVERR out std_logic dummy_view false apb_complete_0 out std_logic dummy_view apb_complete_1 out std_logic dummy_view true sl_iport0 in 36 0 std_logic_vector dummy_view 0 false sl_oport0 out 16 0 std_logic_vector dummy_view 0 false sl_iport1 in 36 0 std_logic_vector dummy_view 0 false sl_oport1 out 16 0 std_logic_vector dummy_view 0 false DRAM_0_STAT_CATTRIP out std_logic dummy_view DRAM_0_STAT_TEMP out 6 0 std_logic_vector dummy_view DRAM_1_STAT_CATTRIP out std_logic dummy_view 0 true DRAM_1_STAT_TEMP out 6 0 std_logic_vector dummy_view 0 true SAXI_00_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_00_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_01_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_01_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_02_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_02_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_03_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_03_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_04_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_04_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_05_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_05_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_06_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_06_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_07_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_07_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_08_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_08_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_09_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_09_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_10_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_10_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_11_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_11_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_12_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_12_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_13_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_13_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_14_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_14_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_15_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_15_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_16_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_16_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_17_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_17_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_18_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_18_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_19_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_19_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_20_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_20_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_21_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_21_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_22_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_22_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_23_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_23_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_24_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_24_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_25_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_25_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_26_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_26_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_27_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_27_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_28_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_28_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_29_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_29_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_30_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_30_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_31_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_31_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_00_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_00_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_01_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_01_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_02_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_02_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_03_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_03_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_04_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_04_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_05_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_05_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_06_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_06_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_07_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_07_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_08_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_08_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_09_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_09_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_10_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_10_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_11_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_11_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_12_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_12_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_13_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_13_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_14_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_14_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_15_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_15_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_16_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_16_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_17_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_17_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_18_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_18_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_19_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_19_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_20_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_20_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_21_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_21_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_22_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_22_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_23_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_23_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_24_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_24_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_25_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_25_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_26_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_26_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_27_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_27_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_28_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_28_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_29_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_29_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_30_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_30_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 SAXI_31_8HI_wr_socket AXIMM Write Socket AXIMM socket for write xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name wr_socket width 256 1 SAXI_31_8HI_rd_socket AXIMM Read Socket AXIMM socket for read xtlm::xtlm_aximm_target_socket xtlm.h provides tlm name rd_socket width 256 1 HBM_STACK 2 SWITCH_ENABLE_00 FALSE SWITCH_ENABLE_01 FALSE INIT_BYPASS FALSE INIT_SEQ_TIMEOUT 10000000 AXI_RST_ASSERT_WIDTH 16 AXI_RST_DEASSERT_WIDTH 2 TEMP_WAIT_PERIOD_0 100000 TEMP_WAIT_PERIOD_1 100000 SWITCH_EN_0 0 SWITCH_EN_1 0 AXI_CLK_FREQ 300.000 AXI_CLK1_FREQ 300.000 HBM_REF_CLK_FREQ_0 100 HBM_REF_CLK_FREQ_1 100 HBM_CLK_FREQ_0 600 HBM_CLK_FREQ_1 600 HBM_STACK_NUM 0 CLK_SEL_00 FALSE CLK_SEL_01 FALSE CLK_SEL_02 FALSE CLK_SEL_03 FALSE CLK_SEL_04 FALSE CLK_SEL_05 FALSE CLK_SEL_06 FALSE CLK_SEL_07 TRUE CLK_SEL_08 FALSE CLK_SEL_09 FALSE CLK_SEL_10 FALSE CLK_SEL_11 FALSE CLK_SEL_12 FALSE CLK_SEL_13 FALSE CLK_SEL_14 FALSE CLK_SEL_15 FALSE CLK_SEL_16 FALSE CLK_SEL_17 FALSE CLK_SEL_18 FALSE CLK_SEL_19 FALSE CLK_SEL_20 FALSE CLK_SEL_21 FALSE CLK_SEL_22 FALSE CLK_SEL_23 TRUE CLK_SEL_24 FALSE CLK_SEL_25 FALSE CLK_SEL_26 FALSE CLK_SEL_27 FALSE CLK_SEL_28 FALSE CLK_SEL_29 FALSE CLK_SEL_30 FALSE CLK_SEL_31 FALSE DATARATE_STACK_0 1200 DATARATE_STACK_1 1200 READ_PERCENT_00 40 READ_PERCENT_01 40 READ_PERCENT_02 40 READ_PERCENT_03 40 READ_PERCENT_04 40 READ_PERCENT_05 40 READ_PERCENT_06 40 READ_PERCENT_07 40 READ_PERCENT_08 40 READ_PERCENT_09 40 READ_PERCENT_10 40 READ_PERCENT_11 40 READ_PERCENT_12 40 READ_PERCENT_13 40 READ_PERCENT_14 40 READ_PERCENT_15 40 READ_PERCENT_16 40 READ_PERCENT_17 40 READ_PERCENT_18 40 READ_PERCENT_19 40 READ_PERCENT_20 40 READ_PERCENT_21 40 READ_PERCENT_22 40 READ_PERCENT_23 40 READ_PERCENT_24 40 READ_PERCENT_25 40 READ_PERCENT_26 40 READ_PERCENT_27 40 READ_PERCENT_28 40 READ_PERCENT_29 40 READ_PERCENT_30 40 READ_PERCENT_31 40 WRITE_PERCENT_00 40 WRITE_PERCENT_01 40 WRITE_PERCENT_02 40 WRITE_PERCENT_03 40 WRITE_PERCENT_04 40 WRITE_PERCENT_05 40 WRITE_PERCENT_06 40 WRITE_PERCENT_07 40 WRITE_PERCENT_08 40 WRITE_PERCENT_09 40 WRITE_PERCENT_10 40 WRITE_PERCENT_11 40 WRITE_PERCENT_12 40 WRITE_PERCENT_13 40 WRITE_PERCENT_14 40 WRITE_PERCENT_15 40 WRITE_PERCENT_16 40 WRITE_PERCENT_17 40 WRITE_PERCENT_18 40 WRITE_PERCENT_19 40 WRITE_PERCENT_20 40 WRITE_PERCENT_21 40 WRITE_PERCENT_22 40 WRITE_PERCENT_23 40 WRITE_PERCENT_24 40 WRITE_PERCENT_25 40 WRITE_PERCENT_26 40 WRITE_PERCENT_27 40 WRITE_PERCENT_28 40 WRITE_PERCENT_29 40 WRITE_PERCENT_30 40 WRITE_PERCENT_31 40 PAGEHIT_PERCENT_00 75 PAGEHIT_PERCENT_01 75 MC_ENABLE_00 FALSE MC_ENABLE_01 FALSE MC_ENABLE_02 FALSE MC_ENABLE_03 FALSE MC_ENABLE_04 FALSE MC_ENABLE_05 FALSE MC_ENABLE_06 FALSE MC_ENABLE_07 FALSE MC_ENABLE_08 FALSE MC_ENABLE_09 FALSE MC_ENABLE_10 FALSE MC_ENABLE_11 FALSE MC_ENABLE_12 FALSE MC_ENABLE_13 FALSE MC_ENABLE_14 FALSE MC_ENABLE_15 FALSE MC_ENABLE_APB_00 FALSE MC_ENABLE_APB_01 FALSE PHY_ENABLE_00 TRUE PHY_ENABLE_01 TRUE PHY_ENABLE_02 TRUE PHY_ENABLE_03 TRUE PHY_ENABLE_04 TRUE PHY_ENABLE_05 TRUE PHY_ENABLE_06 TRUE PHY_ENABLE_07 TRUE PHY_ENABLE_08 TRUE PHY_ENABLE_09 TRUE PHY_ENABLE_10 TRUE PHY_ENABLE_11 TRUE PHY_ENABLE_12 TRUE PHY_ENABLE_13 TRUE PHY_ENABLE_14 TRUE PHY_ENABLE_15 TRUE PHY_ENABLE_16 TRUE PHY_ENABLE_17 TRUE PHY_ENABLE_18 TRUE PHY_ENABLE_19 TRUE PHY_ENABLE_20 TRUE PHY_ENABLE_21 TRUE PHY_ENABLE_22 TRUE PHY_ENABLE_23 TRUE PHY_ENABLE_24 TRUE PHY_ENABLE_25 TRUE PHY_ENABLE_26 TRUE PHY_ENABLE_27 TRUE PHY_ENABLE_28 TRUE PHY_ENABLE_29 TRUE PHY_ENABLE_30 TRUE PHY_ENABLE_31 TRUE PHY_ENABLE_APB_00 TRUE PHY_ENABLE_APB_01 TRUE USER_MC0_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC1_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC2_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC3_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC4_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC5_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC6_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC7_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC8_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC9_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC10_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC11_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC12_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC13_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC14_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm USER_MC15_ADDR_BIT NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 simulation.tlm SAXI_00 true simulation.tlm SAXI_01 true simulation.tlm SAXI_02 true simulation.tlm SAXI_03 true simulation.tlm SAXI_04 true simulation.tlm SAXI_05 true simulation.tlm SAXI_06 true simulation.tlm SAXI_07 true simulation.tlm SAXI_08 true simulation.tlm SAXI_09 true simulation.tlm SAXI_10 true simulation.tlm SAXI_11 true simulation.tlm SAXI_12 true simulation.tlm SAXI_13 true simulation.tlm SAXI_14 true simulation.tlm SAXI_15 true simulation.tlm SAXI_16 true simulation.tlm SAXI_17 true simulation.tlm SAXI_18 true simulation.tlm SAXI_19 true simulation.tlm SAXI_20 true simulation.tlm SAXI_21 true simulation.tlm SAXI_22 true simulation.tlm SAXI_23 true simulation.tlm SAXI_24 true simulation.tlm SAXI_25 true simulation.tlm SAXI_26 true simulation.tlm SAXI_27 true simulation.tlm SAXI_28 true simulation.tlm SAXI_29 true simulation.tlm SAXI_30 true simulation.tlm SAXI_31 true simulation.tlm STACK_8HI false simulation.tlm choice_list_09f2b396 NON_SYNTHESIZABLE SYNTHESIZABLE choice_list_0ccad734 450 choice_list_0da07c0e ROW_BANK_COLUMN ROW_COLUMN_BANK BANK_ROW_COLUMN 14R-2BA-1BG-5C-1BG 2BA-14R-1BG-5C-1BG choice_list_153d9765 4GB 8GB choice_list_15f907ff 100 104 109 114 120 126 133 141 150 160 171 185 200 218 240 267 300 choice_list_30725cf7 LEFT RIGHT choice_list_3aa546d8 MULTIPLE choice_list_56638a14 UC1899 UC1299 choice_list_606e5fda AXI_16_ACLK AXI_17_ACLK AXI_18_ACLK AXI_19_ACLK AXI_20_ACLK AXI_21_ACLK AXI_22_ACLK AXI_23_ACLK AXI_24_ACLK AXI_25_ACLK AXI_26_ACLK AXI_27_ACLK AXI_28_ACLK AXI_29_ACLK AXI_30_ACLK AXI_31_ACLK choice_list_6330c9d2 10 choice_list_7167c927 Controller_and_Physical_Layer Physical_Layer_Only choice_list_7873c525 div4 choice_list_7a7dde49 true false choice_list_811163c2 User_Defined Linear Random choice_list_8aad6ae4 1 2 choice_list_99269739 32 33 36 choice_list_b9d8ad80 yes no choice_list_c2b73541 TRUE FALSEE FALSE choice_list_c3f33c2a 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 300 choice_list_e42ba42f false true choice_list_e7c484ae TRUE FALSE choice_list_f099505f div4 div8 choice_list_ff2e97f4 AXI_00_ACLK AXI_01_ACLK AXI_02_ACLK AXI_03_ACLK AXI_04_ACLK AXI_05_ACLK AXI_06_ACLK AXI_07_ACLK AXI_08_ACLK AXI_09_ACLK AXI_10_ACLK AXI_11_ACLK AXI_12_ACLK AXI_13_ACLK AXI_14_ACLK AXI_15_ACLK HBM Memory Interface IP USER_CTRL_PHY_MODE Physical_Layer_Only USER_EN_PHY_ONLY TRUE USER_INIT_TIMEOUT_VAL 10000000 USER_AXI_ADDR_SIZE 36 USER_EN_VNC FALSE USER_EN_LOW_FREQ FALSE USER_DEBUG_EN FALSE USER_DIS_REF_CLK_BUFG FALSE USER_XSDB_EN FALSE USER_XSDB_INTF_EN FALSE USER_INIT_BYPASS FALSE USER_SINGLE_STACK_SELECTION LEFT false USER_HBM_DENSITY 8GB USER_HBM_STACK 2 USER_MEMORY_DISPLAY 8192 false USER_AUTO_POPULATE yes USER_SWITCH_ENABLE_00 FALSE false USER_SWITCH_ENABLE_01 FALSE false USER_HBM_REF_CLK_0 100 USER_HBM_REF_CLK_PS_0 5000.00 USER_HBM_REF_CLK_XDC_0 10.00 USER_HBM_REF_CLK_PS_1 5000.00 USER_HBM_REF_CLK_XDC_1 10.00 USER_HBM_CLKOUTDIV_0 2 USER_HBM_FBDIV_0 24 USER_HBM_CP_0 6 USER_HBM_RES_0 1 USER_HBM_LFHF_0 3 USER_HBM_LOCK_REF_DLY_0 27 USER_HBM_LOCK_FB_DLY_0 27 USER_HBM_LOCK_CNT_0 1000 USER_HBM_HEX_CP_RES_0 0x00001600 USER_HBM_HEX_CP_0 0x00000000 USER_HBM_HEX_LOCK_FB_REF_DLY_0 0x00001b1b USER_HBM_HEX_LOCK_CNT_0 0x00000000 USER_HBM_HEX_FBDIV_CLKOUTDIV_0 0x00000602 USER_HBM_CP_1 6 USER_HBM_RES_1 1 USER_HBM_LFHF_1 3 USER_HBM_LOCK_REF_DLY_1 27 USER_HBM_LOCK_FB_DLY_1 27 USER_HBM_LOCK_CNT_1 1000 USER_HBM_REF_CLK_1 100 USER_HBM_CLKOUTDIV_1 2 USER_HBM_FBDIV_1 24 USER_HBM_HEX_CP_RES_1 0x00001600 USER_HBM_HEX_CP_1 0x00000000 USER_HBM_HEX_LOCK_FB_REF_DLY_1 0x00001b1b USER_HBM_HEX_LOCK_CNT_1 0x00000000 USER_HBM_HEX_FBDIV_CLKOUTDIV_1 0x00000602 USER_HBM_TCK_0 600 USER_HBM_TCK_0_PERIOD 1.6666666666666667 USER_HYNIX_MEM false USER_tRC_0 0x1D USER_tRAS_0 0x14 USER_tRCDRD_0 0x09 USER_tRCDWR_0 0x06 USER_tRRDL_0 0x03 USER_tRRDS_0 0x03 USER_tFAW_0 0x00A USER_tRTP_0 0x05 USER_tRTP_1 0x05 USER_tRTP_2 0x05 USER_tRTP_3 0x05 USER_tRTP_4 0x05 USER_tRTP_5 0x05 USER_tRTP_6 0x05 USER_tRTP_7 0x05 USER_tRTP_8 0x05 USER_tRTP_9 0x05 USER_tRTP_10 0x05 USER_tRTP_11 0x05 USER_tRTP_12 0x05 USER_tRTP_13 0x05 USER_tRTP_14 0x05 USER_tRTP_15 0x05 USER_tRP_0 0x09 USER_tWR_0 0x0A USER_tWR_1 0x0A USER_tWR_2 0x0F USER_tWR_3 0x0F USER_tWR_4 0x0F USER_tWR_5 0x0F USER_tWR_6 0x0F USER_tWR_7 0x0F USER_tWR_8 0x0F USER_tWR_9 0x0F USER_tWR_10 0x0F USER_tWR_11 0x0F USER_tWR_12 0x0F USER_tWR_13 0x0F USER_tWR_14 0x0F USER_tWR_15 0x0F USER_tWTRL_0 0x6 USER_tWTRS_0 0x3 USER_tXP_0 0x05 USER_tRFC_0 0x09C USER_tRFCSB_0 0x60 USER_tRREFD_0 0x5 USER_WL_0 0x07 USER_RL_0 0x16 USER_RL_1 0x16 USER_RL_2 0x16 USER_RL_3 0x16 USER_RL_4 0x16 USER_RL_5 0x16 USER_RL_6 0x16 USER_RL_7 0x16 USER_RL_8 0x16 USER_RL_9 0x16 USER_RL_10 0x16 USER_RL_11 0x16 USER_RL_12 0x16 USER_RL_13 0x16 USER_RL_14 0x16 USER_RL_15 0x16 USER_tRC_1 0x1D USER_tRAS_1 0x14 USER_tRCDRD_1 0x09 USER_tRCDWR_1 0x06 USER_tRRDL_1 0x03 USER_tRRDS_1 0x03 USER_tFAW_1 0x00A USER_tRP_1 0x09 USER_tWTRL_1 0x6 USER_tWTRS_1 0x3 USER_tXP_1 0x05 USER_tRFC_1 0x09C USER_tRFCSB_1 0x60 USER_tRREFD_1 0x5 USER_WL_1 0x07 USER_APB_PCLK_0 100 USER_APB_PCLK_PERIOD_0 10.0 USER_TEMP_POLL_PERIOD_0 1.0 USER_TEMP_POLL_CNT_0 100000 USER_APB_PCLK_1 100 USER_APB_PCLK_PERIOD_1 10.0 USER_TEMP_POLL_PERIOD_1 1.0 USER_TEMP_POLL_CNT_1 100000 USER_MC0_POP_EN false USER_MC1_POP_EN false USER_MC2_POP_EN false USER_MC3_POP_EN false USER_MC4_POP_EN false USER_MC5_POP_EN false USER_MC6_POP_EN false USER_MC7_POP_EN false USER_MC8_POP_EN false USER_MC9_POP_EN false USER_MC10_POP_EN false USER_MC11_POP_EN false USER_MC12_POP_EN false USER_MC13_POP_EN false USER_MC14_POP_EN false USER_MC15_POP_EN false USER_MC0_TRAFFIC_OPTION User_Defined USER_MC1_TRAFFIC_OPTION User_Defined USER_MC2_TRAFFIC_OPTION User_Defined USER_MC3_TRAFFIC_OPTION User_Defined USER_MC4_TRAFFIC_OPTION User_Defined USER_MC5_TRAFFIC_OPTION User_Defined USER_MC6_TRAFFIC_OPTION User_Defined USER_MC7_TRAFFIC_OPTION User_Defined USER_MC8_TRAFFIC_OPTION User_Defined USER_MC9_TRAFFIC_OPTION User_Defined USER_MC10_TRAFFIC_OPTION User_Defined USER_MC11_TRAFFIC_OPTION User_Defined USER_MC12_TRAFFIC_OPTION User_Defined USER_MC13_TRAFFIC_OPTION User_Defined USER_MC14_TRAFFIC_OPTION User_Defined USER_MC15_TRAFFIC_OPTION User_Defined USER_HBM_TCK_1 600 USER_HBM_TCK_1_PERIOD 1.6666666666666667 USER_LINE_RATE_0 div4 USER_LINE_RATE_1 div4 USER_LINE_RATE_2 div4 USER_LINE_RATE_3 div4 USER_LINE_RATE_4 div4 USER_LINE_RATE_5 div4 USER_LINE_RATE_6 div4 USER_LINE_RATE_7 div4 USER_LINE_RATE_8 div4 USER_LINE_RATE_9 div4 USER_LINE_RATE_10 div4 USER_LINE_RATE_11 div4 USER_LINE_RATE_12 div4 USER_LINE_RATE_13 div4 USER_LINE_RATE_14 div4 USER_LINE_RATE_15 div4 USER_HBM_REF_OUT_CLK_0 1200 USER_HBM_REF_OUT_CLK_1 1200 USER_ENABLE_VT_TRACKING_0 false USER_ENABLE_VT_TRACKING_1 false USER_ENABLE_VT_TRACKING_2 false USER_ENABLE_VT_TRACKING_3 false USER_ENABLE_VT_TRACKING_4 false USER_ENABLE_VT_TRACKING_5 false USER_ENABLE_VT_TRACKING_6 false USER_ENABLE_VT_TRACKING_7 false USER_ENABLE_VT_TRACKING_8 false USER_ENABLE_VT_TRACKING_9 false USER_ENABLE_VT_TRACKING_10 false USER_ENABLE_VT_TRACKING_11 false USER_ENABLE_VT_TRACKING_12 false USER_ENABLE_VT_TRACKING_13 false USER_ENABLE_VT_TRACKING_14 false USER_ENABLE_VT_TRACKING_15 false USER_ENABLE_DQS_TRAINING_0 false USER_ENABLE_DQS_TRAINING_1 false USER_ENABLE_DQS_TRAINING_2 false USER_ENABLE_DQS_TRAINING_3 false USER_ENABLE_DQS_TRAINING_4 false USER_ENABLE_DQS_TRAINING_5 false USER_ENABLE_DQS_TRAINING_6 false USER_ENABLE_DQS_TRAINING_7 false USER_ENABLE_DQS_TRAINING_8 false USER_ENABLE_DQS_TRAINING_9 false USER_ENABLE_DQS_TRAINING_10 false USER_ENABLE_DQS_TRAINING_11 false USER_ENABLE_DQS_TRAINING_12 false USER_ENABLE_DQS_TRAINING_13 false USER_ENABLE_DQS_TRAINING_14 false USER_ENABLE_DQS_TRAINING_15 false USER_MC0_WRITE_DBI_EN true USER_MC1_WRITE_DBI_EN true USER_MC2_WRITE_DBI_EN true USER_MC3_WRITE_DBI_EN true USER_MC4_WRITE_DBI_EN true USER_MC5_WRITE_DBI_EN true USER_MC6_WRITE_DBI_EN true USER_MC7_WRITE_DBI_EN true USER_MC8_WRITE_DBI_EN true USER_MC9_WRITE_DBI_EN true USER_MC10_WRITE_DBI_EN true USER_MC11_WRITE_DBI_EN true USER_MC12_WRITE_DBI_EN true USER_MC13_WRITE_DBI_EN true USER_MC14_WRITE_DBI_EN true USER_MC15_WRITE_DBI_EN true USER_MC0_READ_DBI_EN true USER_MC1_READ_DBI_EN true USER_MC2_READ_DBI_EN true USER_MC3_READ_DBI_EN true USER_MC4_READ_DBI_EN true USER_MC5_READ_DBI_EN true USER_MC6_READ_DBI_EN true USER_MC7_READ_DBI_EN true USER_MC8_READ_DBI_EN true USER_MC9_READ_DBI_EN true USER_MC10_READ_DBI_EN true USER_MC11_READ_DBI_EN true USER_MC12_READ_DBI_EN true USER_MC13_READ_DBI_EN true USER_MC14_READ_DBI_EN true USER_MC15_READ_DBI_EN true USER_CLK_SEL_LIST0 AXI_07_ACLK false USER_CLK_SEL_LIST1 AXI_23_ACLK false USER_CLK_SEL_00 FALSE USER_CLK_SEL_01 FALSE USER_CLK_SEL_02 FALSE USER_CLK_SEL_03 FALSE USER_CLK_SEL_04 FALSE USER_CLK_SEL_05 FALSE USER_CLK_SEL_06 FALSE USER_CLK_SEL_07 FALSE USER_CLK_SEL_08 FALSE USER_CLK_SEL_09 FALSE USER_CLK_SEL_10 FALSE USER_CLK_SEL_11 FALSE USER_CLK_SEL_12 FALSE USER_CLK_SEL_13 FALSE USER_CLK_SEL_14 FALSE USER_CLK_SEL_15 FALSE USER_CLK_SEL_16 FALSE USER_CLK_SEL_17 FALSE USER_CLK_SEL_18 FALSE USER_CLK_SEL_19 FALSE USER_CLK_SEL_20 FALSE USER_CLK_SEL_21 FALSE USER_CLK_SEL_22 FALSE USER_CLK_SEL_23 FALSE USER_CLK_SEL_24 FALSE USER_CLK_SEL_25 FALSE USER_CLK_SEL_26 FALSE USER_CLK_SEL_27 FALSE USER_CLK_SEL_28 FALSE USER_CLK_SEL_29 FALSE USER_CLK_SEL_30 FALSE USER_CLK_SEL_31 FALSE USER_MC_ENABLE_00 FALSE false USER_MC_ENABLE_01 FALSE false USER_MC_ENABLE_02 FALSE false USER_MC_ENABLE_03 FALSE false USER_MC_ENABLE_04 FALSE false USER_MC_ENABLE_05 FALSE false USER_MC_ENABLE_06 FALSE false USER_MC_ENABLE_07 FALSE false USER_MC_ENABLE_08 FALSE false USER_MC_ENABLE_09 FALSE false USER_MC_ENABLE_10 FALSE false USER_MC_ENABLE_11 FALSE false USER_MC_ENABLE_12 FALSE false USER_MC_ENABLE_13 FALSE false USER_MC_ENABLE_14 FALSE false USER_MC_ENABLE_15 FALSE false USER_MC_ENABLE_APB_00 FALSE USER_MC_ENABLE_APB_01 FALSE USER_MC0_MANUAL_ADDR_MAP_SEL false USER_MC0_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC1_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC2_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC3_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC4_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC5_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC6_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC7_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC8_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC9_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC10_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC11_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC12_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC13_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC14_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC15_PRE_DEF_ADDR_MAP_SEL ROW_BANK_COLUMN false USER_MC0_WRITE_READ_REGROUPING false USER_MC1_WRITE_READ_REGROUPING false USER_MC2_WRITE_READ_REGROUPING false USER_MC3_WRITE_READ_REGROUPING false USER_MC4_WRITE_READ_REGROUPING false USER_MC5_WRITE_READ_REGROUPING false USER_MC6_WRITE_READ_REGROUPING false USER_MC7_WRITE_READ_REGROUPING false USER_MC8_WRITE_READ_REGROUPING false USER_MC9_WRITE_READ_REGROUPING false USER_MC10_WRITE_READ_REGROUPING false USER_MC11_WRITE_READ_REGROUPING false USER_MC12_WRITE_READ_REGROUPING false USER_MC13_WRITE_READ_REGROUPING false USER_MC14_WRITE_READ_REGROUPING false USER_MC15_WRITE_READ_REGROUPING false USER_MC0_LOOKAHEAD_SBRF false false USER_MC1_LOOKAHEAD_SBRF false false USER_MC2_LOOKAHEAD_SBRF false false USER_MC3_LOOKAHEAD_SBRF false false USER_MC4_LOOKAHEAD_SBRF false false USER_MC5_LOOKAHEAD_SBRF false false USER_MC6_LOOKAHEAD_SBRF false false USER_MC7_LOOKAHEAD_SBRF false false USER_MC8_LOOKAHEAD_SBRF false false USER_MC9_LOOKAHEAD_SBRF false false USER_MC10_LOOKAHEAD_SBRF false false USER_MC11_LOOKAHEAD_SBRF false false USER_MC12_LOOKAHEAD_SBRF false false USER_MC13_LOOKAHEAD_SBRF false false USER_MC14_LOOKAHEAD_SBRF false false USER_MC15_LOOKAHEAD_SBRF false false USER_MC0_CLOSE_PAGE_REORDER false USER_MC1_CLOSE_PAGE_REORDER false USER_MC2_CLOSE_PAGE_REORDER false USER_MC3_CLOSE_PAGE_REORDER false USER_MC4_CLOSE_PAGE_REORDER false USER_MC5_CLOSE_PAGE_REORDER false USER_MC6_CLOSE_PAGE_REORDER false USER_MC7_CLOSE_PAGE_REORDER false USER_MC8_CLOSE_PAGE_REORDER false USER_MC9_CLOSE_PAGE_REORDER false USER_MC10_CLOSE_PAGE_REORDER false USER_MC11_CLOSE_PAGE_REORDER false USER_MC12_CLOSE_PAGE_REORDER false USER_MC13_CLOSE_PAGE_REORDER false USER_MC14_CLOSE_PAGE_REORDER false USER_MC15_CLOSE_PAGE_REORDER false USER_MC0_REF_TEMP_COMP false USER_MC1_REF_TEMP_COMP false USER_MC2_REF_TEMP_COMP false USER_MC3_REF_TEMP_COMP false USER_MC4_REF_TEMP_COMP false USER_MC5_REF_TEMP_COMP false USER_MC6_REF_TEMP_COMP false USER_MC7_REF_TEMP_COMP false USER_MC8_REF_TEMP_COMP false USER_MC9_REF_TEMP_COMP false USER_MC10_REF_TEMP_COMP false USER_MC11_REF_TEMP_COMP false USER_MC12_REF_TEMP_COMP false USER_MC13_REF_TEMP_COMP false USER_MC14_REF_TEMP_COMP false USER_MC15_REF_TEMP_COMP false USER_MC0_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC1_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC2_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC3_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC4_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC5_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC6_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC7_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC8_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC9_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC10_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC11_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC12_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC13_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC14_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC15_IDLE_ENTR_SELF_REFRESH_MODE 0x00000000 USER_MC0_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC1_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC2_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC3_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC4_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC5_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC6_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC7_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC8_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC9_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC10_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC11_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC12_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC13_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC14_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC15_IDLE_ENTR_PWR_DOWN_MODE 0x00000000 USER_MC0_TEMP_CTRL_SELF_REF_INTVL false USER_MC1_TEMP_CTRL_SELF_REF_INTVL false USER_MC2_TEMP_CTRL_SELF_REF_INTVL false USER_MC3_TEMP_CTRL_SELF_REF_INTVL false USER_MC4_TEMP_CTRL_SELF_REF_INTVL false USER_MC5_TEMP_CTRL_SELF_REF_INTVL false USER_MC6_TEMP_CTRL_SELF_REF_INTVL false USER_MC7_TEMP_CTRL_SELF_REF_INTVL false USER_MC8_TEMP_CTRL_SELF_REF_INTVL false USER_MC9_TEMP_CTRL_SELF_REF_INTVL false USER_MC10_TEMP_CTRL_SELF_REF_INTVL false USER_MC11_TEMP_CTRL_SELF_REF_INTVL false USER_MC12_TEMP_CTRL_SELF_REF_INTVL false USER_MC13_TEMP_CTRL_SELF_REF_INTVL false USER_MC14_TEMP_CTRL_SELF_REF_INTVL false USER_MC15_TEMP_CTRL_SELF_REF_INTVL false USER_MC0_ECC_BYPASS false USER_MC1_ECC_BYPASS false USER_MC2_ECC_BYPASS false USER_MC3_ECC_BYPASS false USER_MC4_ECC_BYPASS false USER_MC5_ECC_BYPASS false USER_MC6_ECC_BYPASS false USER_MC7_ECC_BYPASS false USER_MC8_ECC_BYPASS false USER_MC9_ECC_BYPASS false USER_MC10_ECC_BYPASS false USER_MC11_ECC_BYPASS false USER_MC12_ECC_BYPASS false USER_MC13_ECC_BYPASS false USER_MC14_ECC_BYPASS false USER_MC15_ECC_BYPASS false USER_MC0_ENABLE_ECC_CORRECTION false USER_MC1_ENABLE_ECC_CORRECTION false USER_MC2_ENABLE_ECC_CORRECTION false USER_MC3_ENABLE_ECC_CORRECTION false USER_MC4_ENABLE_ECC_CORRECTION false USER_MC5_ENABLE_ECC_CORRECTION false USER_MC6_ENABLE_ECC_CORRECTION false USER_MC7_ENABLE_ECC_CORRECTION false USER_MC8_ENABLE_ECC_CORRECTION false USER_MC9_ENABLE_ECC_CORRECTION false USER_MC10_ENABLE_ECC_CORRECTION false USER_MC11_ENABLE_ECC_CORRECTION false USER_MC12_ENABLE_ECC_CORRECTION false USER_MC13_ENABLE_ECC_CORRECTION false USER_MC14_ENABLE_ECC_CORRECTION false USER_MC15_ENABLE_ECC_CORRECTION false USER_MC0_ECC_SCRUB_BITS 0 false USER_MC1_ECC_SCRUB_BITS 0 false USER_MC2_ECC_SCRUB_BITS 0 false USER_MC3_ECC_SCRUB_BITS 0 false USER_MC4_ECC_SCRUB_BITS 0 false USER_MC5_ECC_SCRUB_BITS 0 false USER_MC6_ECC_SCRUB_BITS 0 false USER_MC7_ECC_SCRUB_BITS 0 false USER_MC8_ECC_SCRUB_BITS 0 false USER_MC9_ECC_SCRUB_BITS 0 false USER_MC10_ECC_SCRUB_BITS 0 false USER_MC11_ECC_SCRUB_BITS 0 false USER_MC12_ECC_SCRUB_BITS 0 false USER_MC13_ECC_SCRUB_BITS 0 false USER_MC14_ECC_SCRUB_BITS 0 false USER_MC15_ECC_SCRUB_BITS 0 false USER_MC0_ENABLE_ECC_SCRUBBING false false USER_MC1_ENABLE_ECC_SCRUBBING false false USER_MC2_ENABLE_ECC_SCRUBBING false false USER_MC3_ENABLE_ECC_SCRUBBING false false USER_MC4_ENABLE_ECC_SCRUBBING false false USER_MC5_ENABLE_ECC_SCRUBBING false false USER_MC6_ENABLE_ECC_SCRUBBING false false USER_MC7_ENABLE_ECC_SCRUBBING false false USER_MC8_ENABLE_ECC_SCRUBBING false false USER_MC9_ENABLE_ECC_SCRUBBING false false USER_MC10_ENABLE_ECC_SCRUBBING false false USER_MC11_ENABLE_ECC_SCRUBBING false false USER_MC12_ENABLE_ECC_SCRUBBING false false USER_MC13_ENABLE_ECC_SCRUBBING false false USER_MC14_ENABLE_ECC_SCRUBBING false false USER_MC15_ENABLE_ECC_SCRUBBING false false USER_MC0_ECC_SCRUB_PERIOD 0x0002 false USER_MC1_ECC_SCRUB_PERIOD 0x0002 false USER_MC2_ECC_SCRUB_PERIOD 0x0002 false USER_MC3_ECC_SCRUB_PERIOD 0x0002 false USER_MC4_ECC_SCRUB_PERIOD 0x0002 false USER_MC5_ECC_SCRUB_PERIOD 0x0002 false USER_MC6_ECC_SCRUB_PERIOD 0x0002 false USER_MC7_ECC_SCRUB_PERIOD 0x0002 false USER_MC8_ECC_SCRUB_PERIOD 0x0002 false USER_MC9_ECC_SCRUB_PERIOD 0x0002 false USER_MC10_ECC_SCRUB_PERIOD 0x0002 false USER_MC11_ECC_SCRUB_PERIOD 0x0002 false USER_MC12_ECC_SCRUB_PERIOD 0x0002 false USER_MC13_ECC_SCRUB_PERIOD 0x0002 false USER_MC14_ECC_SCRUB_PERIOD 0x0002 false USER_MC15_ECC_SCRUB_PERIOD 0x0002 false USER_MC0_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC1_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC2_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC3_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC4_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC5_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC6_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC7_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC8_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC9_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC10_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC11_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC12_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC13_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC14_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC15_INITILIZE_MEM_USING_ECC_SCRUB false false USER_MC0_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC1_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC2_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC3_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC4_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC5_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC6_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC7_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC8_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC9_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC10_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC11_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC12_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC13_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC14_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC15_INITILIZE_MEM_USING_RMW_ECC_SCRUB false false USER_MC0_MANUAL_REFRESH_SEL false USER_MC0_MANUAL_ADV_OPTIONS false USER_MC0_COL_ADDR_LOW 0x4 USER_MC0_COL_ADDR_HIGH 0xa USER_MC0_LADDR_BA0_BA4_MAP 0x00282248 USER_MC0_LADDR_BA5_MAP 0x00 USER_MC0_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC0_LADDR_RA5_RA9_MAP 0x55134914 USER_MC0_LADDR_RA10_RA14_MAP 0x00061759 USER_MC0_LADDR_RA15_RA17_MAP 0x00000 USER_MC0_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC0_LADDR_CA5_CA9_MAP 0x00000001 USER_MC0_LADDR_CA10_CA15_MAP 0x00000000 USER_MC0_BG_INTERLEAVE_EN true USER_MC0_EN_TEMP_CTRL_REF_MODE false USER_MC0_EN_TEMP_COMP_SF_PERIOD false USER_MC0_REF_CMD_PERIOD 0x0924 USER_MC0_EN_SBREF false USER_MC0_BURST_RW_REFRESH_HOLDOFF false USER_MC0_SBREF_ISSUE_PER 0x01e false USER_STACK_8HI false USER_MC0_LOOKAHEAD_PCH true USER_MC0_LOOKAHEAD_ACT true USER_MC0_REORDER_EN true USER_MC0_REORDER_RW_ONLY false USER_MC0_REORDER_QUEUE_EN true USER_MC0_MAINTAIN_COHERENCY true USER_MC0_Q_AGE_LIMIT 0x7f USER_MC0_EN_DATA_MASK true USER_MC0_INIT_PERR_RETRY_EN false USER_MC0_USER_PARITY_EN false USER_MC0_DQ_PARITY_EN false USER_MC0_RD_DQ_PARITY_EN false USER_MC0_WR_DQ_PARITY_EN false USER_MC0_CA_PARITY_EN false USER_MC0_HBM_CB_EN false USER_MC0_DM_EN true false USER_MC0_RMW_EN false false USER_MC1_MANUAL_ADDR_MAP_SEL false false USER_MC1_MANUAL_REFRESH_SEL false USER_MC1_MANUAL_ADV_OPTIONS false USER_MC1_COL_ADDR_LOW 0x4 USER_MC1_COL_ADDR_HIGH 0x4 USER_MC1_LADDR_BA0_BA4_MAP 0x00282248 USER_MC1_LADDR_BA5_MAP 0x05 USER_MC1_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC1_LADDR_RA5_RA9_MAP 0x55134914 USER_MC1_LADDR_RA10_RA14_MAP 0x00061759 USER_MC1_LADDR_RA15_RA17_MAP 0x00000 USER_MC1_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC1_LADDR_CA5_CA9_MAP 0x00000001 USER_MC1_LADDR_CA10_CA15_MAP 0x00000000 USER_MC1_BG_INTERLEAVE_EN true USER_MC1_EN_TEMP_CTRL_REF_MODE false USER_MC1_EN_TEMP_COMP_SF_PERIOD false USER_MC1_REF_CMD_PERIOD 0x0924 USER_MC1_EN_SBREF false USER_MC1_BURST_RW_REFRESH_HOLDOFF false USER_MC1_SBREF_ISSUE_PER 0x01e false USER_MC1_LOOKAHEAD_PCH true USER_MC1_LOOKAHEAD_ACT true USER_MC1_REORDER_EN true USER_MC1_REORDER_RW_ONLY false USER_MC1_REORDER_QUEUE_EN true USER_MC1_MAINTAIN_COHERENCY true USER_MC1_Q_AGE_LIMIT 0x7f USER_MC1_EN_DATA_MASK true USER_MC1_INIT_PERR_RETRY_EN false USER_MC1_USER_PARITY_EN false USER_MC1_DQ_PARITY_EN false USER_MC1_RD_DQ_PARITY_EN false USER_MC1_WR_DQ_PARITY_EN false USER_MC1_CA_PARITY_EN false USER_MC1_HBM_CB_EN false USER_MC1_DM_EN true false USER_MC1_RMW_EN false false USER_MC2_MANUAL_ADDR_MAP_SEL false false USER_MC2_MANUAL_REFRESH_SEL false USER_MC2_MANUAL_ADV_OPTIONS false USER_MC2_COL_ADDR_LOW 0x4 USER_MC2_COL_ADDR_HIGH 0x4 USER_MC2_LADDR_BA0_BA4_MAP 0x00282248 USER_MC2_LADDR_BA5_MAP 0x05 USER_MC2_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC2_LADDR_RA5_RA9_MAP 0x55134914 USER_MC2_LADDR_RA10_RA14_MAP 0x00061759 USER_MC2_LADDR_RA15_RA17_MAP 0x00000 USER_MC2_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC2_LADDR_CA5_CA9_MAP 0x00000001 USER_MC2_LADDR_CA10_CA15_MAP 0x00000000 USER_MC2_BG_INTERLEAVE_EN true USER_MC2_EN_TEMP_CTRL_REF_MODE false USER_MC2_EN_TEMP_COMP_SF_PERIOD false USER_MC2_REF_CMD_PERIOD 0x0924 USER_MC2_EN_SBREF false USER_MC2_BURST_RW_REFRESH_HOLDOFF false USER_MC2_SBREF_ISSUE_PER 0x01e false USER_MC2_LOOKAHEAD_PCH true USER_MC2_LOOKAHEAD_ACT true USER_MC2_REORDER_EN true USER_MC2_REORDER_RW_ONLY false USER_MC2_REORDER_QUEUE_EN true USER_MC2_MAINTAIN_COHERENCY true USER_MC2_Q_AGE_LIMIT 0x7f USER_MC2_EN_DATA_MASK true USER_MC2_INIT_PERR_RETRY_EN false USER_MC2_USER_PARITY_EN false USER_MC2_DQ_PARITY_EN false USER_MC2_RD_DQ_PARITY_EN false USER_MC2_WR_DQ_PARITY_EN false USER_MC2_CA_PARITY_EN false USER_MC2_HBM_CB_EN false USER_MC2_DM_EN true false USER_MC2_RMW_EN false false USER_MC3_MANUAL_ADDR_MAP_SEL false false USER_MC3_MANUAL_REFRESH_SEL false USER_MC3_MANUAL_ADV_OPTIONS false USER_MC3_COL_ADDR_LOW 0x4 USER_MC3_COL_ADDR_HIGH 0x4 USER_MC3_LADDR_BA0_BA4_MAP 0x00282248 USER_MC3_LADDR_BA5_MAP 0x05 USER_MC3_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC3_LADDR_RA5_RA9_MAP 0x55134914 USER_MC3_LADDR_RA10_RA14_MAP 0x00061759 USER_MC3_LADDR_RA15_RA17_MAP 0x00000 USER_MC3_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC3_LADDR_CA5_CA9_MAP 0x00000001 USER_MC3_LADDR_CA10_CA15_MAP 0x00000000 USER_MC3_BG_INTERLEAVE_EN true USER_MC3_EN_TEMP_CTRL_REF_MODE false USER_MC3_EN_TEMP_COMP_SF_PERIOD false USER_MC3_REF_CMD_PERIOD 0x0924 USER_MC3_EN_SBREF false USER_MC3_BURST_RW_REFRESH_HOLDOFF false USER_MC3_SBREF_ISSUE_PER 0x01e false USER_MC3_LOOKAHEAD_PCH true USER_MC3_LOOKAHEAD_ACT true USER_MC3_REORDER_EN true USER_MC3_REORDER_RW_ONLY false USER_MC3_REORDER_QUEUE_EN true USER_MC3_MAINTAIN_COHERENCY true USER_MC3_Q_AGE_LIMIT 0x7f USER_MC3_EN_DATA_MASK true USER_MC3_INIT_PERR_RETRY_EN false USER_MC3_USER_PARITY_EN false USER_MC3_DQ_PARITY_EN false USER_MC3_RD_DQ_PARITY_EN false USER_MC3_WR_DQ_PARITY_EN false USER_MC3_CA_PARITY_EN false USER_MC3_HBM_CB_EN false USER_MC3_DM_EN true false USER_MC3_RMW_EN false false USER_MC4_MANUAL_ADDR_MAP_SEL false false USER_MC4_MANUAL_REFRESH_SEL false USER_MC4_MANUAL_ADV_OPTIONS false USER_MC4_COL_ADDR_LOW 0x4 USER_MC4_COL_ADDR_HIGH 0x4 USER_MC4_LADDR_BA0_BA4_MAP 0x00282248 USER_MC4_LADDR_BA5_MAP 0x05 USER_MC4_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC4_LADDR_RA5_RA9_MAP 0x55134914 USER_MC4_LADDR_RA10_RA14_MAP 0x00061759 USER_MC4_LADDR_RA15_RA17_MAP 0x00000 USER_MC4_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC4_LADDR_CA5_CA9_MAP 0x00000001 USER_MC4_LADDR_CA10_CA15_MAP 0x00000000 USER_MC4_BG_INTERLEAVE_EN true USER_MC4_EN_TEMP_CTRL_REF_MODE false USER_MC4_EN_TEMP_COMP_SF_PERIOD false USER_MC4_REF_CMD_PERIOD 0x0924 USER_MC4_EN_SBREF false USER_MC4_BURST_RW_REFRESH_HOLDOFF false USER_MC4_SBREF_ISSUE_PER 0x01e false USER_MC4_LOOKAHEAD_PCH true USER_MC4_LOOKAHEAD_ACT true USER_MC4_REORDER_EN true USER_MC4_REORDER_RW_ONLY false USER_MC4_REORDER_QUEUE_EN true USER_MC4_MAINTAIN_COHERENCY true USER_MC4_Q_AGE_LIMIT 0x7f USER_MC4_EN_DATA_MASK true USER_MC4_INIT_PERR_RETRY_EN false USER_MC4_USER_PARITY_EN false USER_MC4_DQ_PARITY_EN false USER_MC4_RD_DQ_PARITY_EN false USER_MC4_WR_DQ_PARITY_EN false USER_MC4_CA_PARITY_EN false USER_MC4_HBM_CB_EN false USER_MC4_DM_EN true false USER_MC4_RMW_EN false false USER_MC5_MANUAL_ADDR_MAP_SEL false false USER_MC5_MANUAL_REFRESH_SEL false USER_MC5_MANUAL_ADV_OPTIONS false USER_MC5_COL_ADDR_LOW 0x4 USER_MC5_COL_ADDR_HIGH 0x4 USER_MC5_LADDR_BA0_BA4_MAP 0x00282248 USER_MC5_LADDR_BA5_MAP 0x05 USER_MC5_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC5_LADDR_RA5_RA9_MAP 0x55134914 USER_MC5_LADDR_RA10_RA14_MAP 0x00061759 USER_MC5_LADDR_RA15_RA17_MAP 0x00000 USER_MC5_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC5_LADDR_CA5_CA9_MAP 0x00000001 USER_MC5_LADDR_CA10_CA15_MAP 0x00000000 USER_MC5_BG_INTERLEAVE_EN true USER_MC5_EN_TEMP_CTRL_REF_MODE false USER_MC5_EN_TEMP_COMP_SF_PERIOD false USER_MC5_REF_CMD_PERIOD 0x0924 USER_MC5_EN_SBREF false USER_MC5_BURST_RW_REFRESH_HOLDOFF false USER_MC5_SBREF_ISSUE_PER 0x01e false USER_MC5_LOOKAHEAD_PCH true USER_MC5_LOOKAHEAD_ACT true USER_MC5_REORDER_EN true USER_MC5_REORDER_RW_ONLY false USER_MC5_REORDER_QUEUE_EN true USER_MC5_MAINTAIN_COHERENCY true USER_MC5_Q_AGE_LIMIT 0x7f USER_MC5_EN_DATA_MASK true USER_MC5_INIT_PERR_RETRY_EN false USER_MC5_USER_PARITY_EN false USER_MC5_DQ_PARITY_EN false USER_MC5_RD_DQ_PARITY_EN false USER_MC5_WR_DQ_PARITY_EN false USER_MC5_CA_PARITY_EN false USER_MC5_HBM_CB_EN false USER_MC5_DM_EN true false USER_MC5_RMW_EN false false USER_MC6_MANUAL_ADDR_MAP_SEL false false USER_MC6_MANUAL_REFRESH_SEL false USER_MC6_MANUAL_ADV_OPTIONS false USER_MC6_COL_ADDR_LOW 0x4 USER_MC6_COL_ADDR_HIGH 0x4 USER_MC6_LADDR_BA0_BA4_MAP 0x00282248 USER_MC6_LADDR_BA5_MAP 0x05 USER_MC6_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC6_LADDR_RA5_RA9_MAP 0x55134914 USER_MC6_LADDR_RA10_RA14_MAP 0x00061759 USER_MC6_LADDR_RA15_RA17_MAP 0x00000 USER_MC6_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC6_LADDR_CA5_CA9_MAP 0x00000001 USER_MC6_LADDR_CA10_CA15_MAP 0x00000000 USER_MC6_BG_INTERLEAVE_EN true USER_MC6_EN_TEMP_CTRL_REF_MODE false USER_MC6_EN_TEMP_COMP_SF_PERIOD false USER_MC6_REF_CMD_PERIOD 0x0924 USER_MC6_EN_SBREF false USER_MC6_BURST_RW_REFRESH_HOLDOFF false USER_MC6_SBREF_ISSUE_PER 0x01e false USER_MC6_LOOKAHEAD_PCH true USER_MC6_LOOKAHEAD_ACT true USER_MC6_REORDER_EN true USER_MC6_REORDER_RW_ONLY false USER_MC6_REORDER_QUEUE_EN true USER_MC6_MAINTAIN_COHERENCY true USER_MC6_Q_AGE_LIMIT 0x7f USER_MC6_EN_DATA_MASK true USER_MC6_INIT_PERR_RETRY_EN false USER_MC6_USER_PARITY_EN false USER_MC6_DQ_PARITY_EN false USER_MC6_RD_DQ_PARITY_EN false USER_MC6_WR_DQ_PARITY_EN false USER_MC6_CA_PARITY_EN false USER_MC6_HBM_CB_EN false USER_MC6_DM_EN true false USER_MC6_RMW_EN false false USER_MC7_MANUAL_ADDR_MAP_SEL false false USER_MC7_MANUAL_REFRESH_SEL false USER_MC7_MANUAL_ADV_OPTIONS false USER_MC7_COL_ADDR_LOW 0x4 USER_MC7_COL_ADDR_HIGH 0x4 USER_MC7_LADDR_BA0_BA4_MAP 0x00282248 USER_MC7_LADDR_BA5_MAP 0x05 USER_MC7_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC7_LADDR_RA5_RA9_MAP 0x55134914 USER_MC7_LADDR_RA10_RA14_MAP 0x00061759 USER_MC7_LADDR_RA15_RA17_MAP 0x00000 USER_MC7_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC7_LADDR_CA5_CA9_MAP 0x00000001 USER_MC7_LADDR_CA10_CA15_MAP 0x00000000 USER_MC7_BG_INTERLEAVE_EN true USER_MC7_EN_TEMP_CTRL_REF_MODE false USER_MC7_EN_TEMP_COMP_SF_PERIOD false USER_MC7_REF_CMD_PERIOD 0x0924 USER_MC7_EN_SBREF false USER_MC7_BURST_RW_REFRESH_HOLDOFF false USER_MC7_SBREF_ISSUE_PER 0x01e false USER_MC7_LOOKAHEAD_PCH true USER_MC7_LOOKAHEAD_ACT true USER_MC7_REORDER_EN true USER_MC7_REORDER_RW_ONLY false USER_MC7_REORDER_QUEUE_EN true USER_MC7_MAINTAIN_COHERENCY true USER_MC7_Q_AGE_LIMIT 0x7f USER_MC7_EN_DATA_MASK true USER_MC7_INIT_PERR_RETRY_EN false USER_MC7_USER_PARITY_EN false USER_MC7_DQ_PARITY_EN false USER_MC7_RD_DQ_PARITY_EN false USER_MC7_WR_DQ_PARITY_EN false USER_MC7_CA_PARITY_EN false USER_MC7_HBM_CB_EN false USER_MC7_DM_EN true false USER_MC7_RMW_EN false false USER_MC8_MANUAL_ADDR_MAP_SEL false false USER_MC8_MANUAL_REFRESH_SEL false USER_MC8_MANUAL_ADV_OPTIONS false USER_MC8_COL_ADDR_LOW 0x4 USER_MC8_COL_ADDR_HIGH 0x4 USER_MC8_LADDR_BA0_BA4_MAP 0x00282248 USER_MC8_LADDR_BA5_MAP 0x05 USER_MC8_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC8_LADDR_RA5_RA9_MAP 0x55134914 USER_MC8_LADDR_RA10_RA14_MAP 0x00061759 USER_MC8_LADDR_RA15_RA17_MAP 0x00000 USER_MC8_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC8_LADDR_CA5_CA9_MAP 0x00000001 USER_MC8_LADDR_CA10_CA15_MAP 0x00000000 USER_MC8_BG_INTERLEAVE_EN true USER_MC8_EN_TEMP_CTRL_REF_MODE false USER_MC8_EN_TEMP_COMP_SF_PERIOD false USER_MC8_REF_CMD_PERIOD 0x0924 USER_MC8_EN_SBREF false USER_MC8_BURST_RW_REFRESH_HOLDOFF false USER_MC8_SBREF_ISSUE_PER 0x01e false USER_MC8_LOOKAHEAD_PCH true USER_MC8_LOOKAHEAD_ACT true USER_MC8_REORDER_EN true USER_MC8_REORDER_RW_ONLY false USER_MC8_REORDER_QUEUE_EN true USER_MC8_MAINTAIN_COHERENCY true USER_MC8_Q_AGE_LIMIT 0x7f USER_MC8_EN_DATA_MASK true USER_MC8_INIT_PERR_RETRY_EN false USER_MC8_USER_PARITY_EN false USER_MC8_DQ_PARITY_EN false USER_MC8_RD_DQ_PARITY_EN false USER_MC8_WR_DQ_PARITY_EN false USER_MC8_CA_PARITY_EN false USER_MC8_HBM_CB_EN false USER_MC8_DM_EN true false USER_MC8_RMW_EN false false USER_MC9_MANUAL_ADDR_MAP_SEL false false USER_MC9_MANUAL_REFRESH_SEL false USER_MC9_MANUAL_ADV_OPTIONS false USER_MC9_COL_ADDR_LOW 0x4 USER_MC9_COL_ADDR_HIGH 0x4 USER_MC9_LADDR_BA0_BA4_MAP 0x00282248 USER_MC9_LADDR_BA5_MAP 0x05 USER_MC9_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC9_LADDR_RA5_RA9_MAP 0x55134914 USER_MC9_LADDR_RA10_RA14_MAP 0x00061759 USER_MC9_LADDR_RA15_RA17_MAP 0x00000 USER_MC9_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC9_LADDR_CA5_CA9_MAP 0x00000001 USER_MC9_LADDR_CA10_CA15_MAP 0x00000000 USER_MC9_BG_INTERLEAVE_EN true USER_MC9_EN_TEMP_CTRL_REF_MODE false USER_MC9_EN_TEMP_COMP_SF_PERIOD false USER_MC9_REF_CMD_PERIOD 0x0924 USER_MC9_EN_SBREF false USER_MC9_BURST_RW_REFRESH_HOLDOFF false USER_MC9_SBREF_ISSUE_PER 0x01e false USER_MC9_LOOKAHEAD_PCH true USER_MC9_LOOKAHEAD_ACT true USER_MC9_REORDER_EN true USER_MC9_REORDER_RW_ONLY false USER_MC9_REORDER_QUEUE_EN true USER_MC9_MAINTAIN_COHERENCY true USER_MC9_Q_AGE_LIMIT 0x7f USER_MC9_EN_DATA_MASK true USER_MC9_INIT_PERR_RETRY_EN false USER_MC9_USER_PARITY_EN false USER_MC9_DQ_PARITY_EN false USER_MC9_RD_DQ_PARITY_EN false USER_MC9_WR_DQ_PARITY_EN false USER_MC9_CA_PARITY_EN false USER_MC9_HBM_CB_EN false USER_MC9_DM_EN true false USER_MC9_RMW_EN false false USER_MC10_MANUAL_ADDR_MAP_SEL false false USER_MC10_MANUAL_REFRESH_SEL false USER_MC10_MANUAL_ADV_OPTIONS false USER_MC10_COL_ADDR_LOW 0x4 USER_MC10_COL_ADDR_HIGH 0x4 USER_MC10_LADDR_BA0_BA4_MAP 0x00282248 USER_MC10_LADDR_BA5_MAP 0x05 USER_MC10_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC10_LADDR_RA5_RA9_MAP 0x55134914 USER_MC10_LADDR_RA10_RA14_MAP 0x00061759 USER_MC10_LADDR_RA15_RA17_MAP 0x00000 USER_MC10_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC10_LADDR_CA5_CA9_MAP 0x00000001 USER_MC10_LADDR_CA10_CA15_MAP 0x00000000 USER_MC10_BG_INTERLEAVE_EN true USER_MC10_EN_TEMP_CTRL_REF_MODE false USER_MC10_EN_TEMP_COMP_SF_PERIOD false USER_MC10_REF_CMD_PERIOD 0x0924 USER_MC10_EN_SBREF false USER_MC10_BURST_RW_REFRESH_HOLDOFF false USER_MC10_SBREF_ISSUE_PER 0x01e false USER_MC10_LOOKAHEAD_PCH true USER_MC10_LOOKAHEAD_ACT true USER_MC10_REORDER_EN true USER_MC10_REORDER_RW_ONLY false USER_MC10_REORDER_QUEUE_EN true USER_MC10_MAINTAIN_COHERENCY true USER_MC10_Q_AGE_LIMIT 0x7f USER_MC10_EN_DATA_MASK true USER_MC10_INIT_PERR_RETRY_EN false USER_MC10_USER_PARITY_EN false USER_MC10_DQ_PARITY_EN false USER_MC10_RD_DQ_PARITY_EN false USER_MC10_WR_DQ_PARITY_EN false USER_MC10_CA_PARITY_EN false USER_MC10_HBM_CB_EN false USER_MC10_DM_EN true false USER_MC10_RMW_EN false false USER_MC11_MANUAL_ADDR_MAP_SEL false false USER_MC11_MANUAL_REFRESH_SEL false USER_MC11_MANUAL_ADV_OPTIONS false USER_MC11_COL_ADDR_LOW 0x4 USER_MC11_COL_ADDR_HIGH 0x4 USER_MC11_LADDR_BA0_BA4_MAP 0x00282248 USER_MC11_LADDR_BA5_MAP 0x05 USER_MC11_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC11_LADDR_RA5_RA9_MAP 0x55134914 USER_MC11_LADDR_RA10_RA14_MAP 0x00061759 USER_MC11_LADDR_RA15_RA17_MAP 0x00000 USER_MC11_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC11_LADDR_CA5_CA9_MAP 0x00000001 USER_MC11_LADDR_CA10_CA15_MAP 0x00000000 USER_MC11_BG_INTERLEAVE_EN true USER_MC11_EN_TEMP_CTRL_REF_MODE false USER_MC11_EN_TEMP_COMP_SF_PERIOD false USER_MC11_REF_CMD_PERIOD 0x0924 USER_MC11_EN_SBREF false USER_MC11_BURST_RW_REFRESH_HOLDOFF false USER_MC11_SBREF_ISSUE_PER 0x01e false USER_MC11_LOOKAHEAD_PCH true USER_MC11_LOOKAHEAD_ACT true USER_MC11_REORDER_EN true USER_MC11_REORDER_RW_ONLY false USER_MC11_REORDER_QUEUE_EN true USER_MC11_MAINTAIN_COHERENCY true USER_MC11_Q_AGE_LIMIT 0x7f USER_MC11_EN_DATA_MASK true USER_MC11_INIT_PERR_RETRY_EN false USER_MC11_USER_PARITY_EN false USER_MC11_DQ_PARITY_EN false USER_MC11_RD_DQ_PARITY_EN false USER_MC11_WR_DQ_PARITY_EN false USER_MC11_CA_PARITY_EN false USER_MC11_HBM_CB_EN false USER_MC11_DM_EN true false USER_MC11_RMW_EN false false USER_MC12_MANUAL_ADDR_MAP_SEL false false USER_MC12_MANUAL_REFRESH_SEL false USER_MC12_MANUAL_ADV_OPTIONS false USER_MC12_COL_ADDR_LOW 0x4 USER_MC12_COL_ADDR_HIGH 0x4 USER_MC12_LADDR_BA0_BA4_MAP 0x00282248 USER_MC12_LADDR_BA5_MAP 0x05 USER_MC12_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC12_LADDR_RA5_RA9_MAP 0x55134914 USER_MC12_LADDR_RA10_RA14_MAP 0x00061759 USER_MC12_LADDR_RA15_RA17_MAP 0x00000 USER_MC12_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC12_LADDR_CA5_CA9_MAP 0x00000001 USER_MC12_LADDR_CA10_CA15_MAP 0x00000000 USER_MC12_BG_INTERLEAVE_EN true USER_MC12_EN_TEMP_CTRL_REF_MODE false USER_MC12_EN_TEMP_COMP_SF_PERIOD false USER_MC12_REF_CMD_PERIOD 0x0924 USER_MC12_EN_SBREF false USER_MC12_BURST_RW_REFRESH_HOLDOFF false USER_MC12_SBREF_ISSUE_PER 0x01e false USER_MC12_LOOKAHEAD_PCH true USER_MC12_LOOKAHEAD_ACT true USER_MC12_REORDER_EN true USER_MC12_REORDER_RW_ONLY false USER_MC12_REORDER_QUEUE_EN true USER_MC12_MAINTAIN_COHERENCY true USER_MC12_Q_AGE_LIMIT 0x7f USER_MC12_EN_DATA_MASK true USER_MC12_INIT_PERR_RETRY_EN false USER_MC12_USER_PARITY_EN false USER_MC12_DQ_PARITY_EN false USER_MC12_RD_DQ_PARITY_EN false USER_MC12_WR_DQ_PARITY_EN false USER_MC12_CA_PARITY_EN false USER_MC12_HBM_CB_EN false USER_MC12_DM_EN true false USER_MC12_RMW_EN false false USER_MC13_MANUAL_ADDR_MAP_SEL false false USER_MC13_MANUAL_REFRESH_SEL false USER_MC13_MANUAL_ADV_OPTIONS false USER_MC13_COL_ADDR_LOW 0x4 USER_MC13_COL_ADDR_HIGH 0x4 USER_MC13_LADDR_BA0_BA4_MAP 0x00282248 USER_MC13_LADDR_BA5_MAP 0x05 USER_MC13_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC13_LADDR_RA5_RA9_MAP 0x55134914 USER_MC13_LADDR_RA10_RA14_MAP 0x00061759 USER_MC13_LADDR_RA15_RA17_MAP 0x00000 USER_MC13_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC13_LADDR_CA5_CA9_MAP 0x00000001 USER_MC13_LADDR_CA10_CA15_MAP 0x00000000 USER_MC13_BG_INTERLEAVE_EN true USER_MC13_EN_TEMP_CTRL_REF_MODE false USER_MC13_EN_TEMP_COMP_SF_PERIOD false USER_MC13_REF_CMD_PERIOD 0x0924 USER_MC13_EN_SBREF false USER_MC13_BURST_RW_REFRESH_HOLDOFF false USER_MC13_SBREF_ISSUE_PER 0x01e false USER_MC13_LOOKAHEAD_PCH true USER_MC13_LOOKAHEAD_ACT true USER_MC13_REORDER_EN true USER_MC13_REORDER_RW_ONLY false USER_MC13_REORDER_QUEUE_EN true USER_MC13_MAINTAIN_COHERENCY true USER_MC13_Q_AGE_LIMIT 0x7f USER_MC13_EN_DATA_MASK true USER_MC13_INIT_PERR_RETRY_EN false USER_MC13_USER_PARITY_EN false USER_MC13_DQ_PARITY_EN false USER_MC13_RD_DQ_PARITY_EN false USER_MC13_WR_DQ_PARITY_EN false USER_MC13_CA_PARITY_EN false USER_MC13_HBM_CB_EN false USER_MC13_DM_EN true false USER_MC13_RMW_EN false false USER_MC14_MANUAL_ADDR_MAP_SEL false false USER_MC14_MANUAL_REFRESH_SEL false USER_MC14_MANUAL_ADV_OPTIONS false USER_MC14_COL_ADDR_LOW 0x4 USER_MC14_COL_ADDR_HIGH 0x4 USER_MC14_LADDR_BA0_BA4_MAP 0x00282248 USER_MC14_LADDR_BA5_MAP 0x05 USER_MC14_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC14_LADDR_RA5_RA9_MAP 0x55134914 USER_MC14_LADDR_RA10_RA14_MAP 0x00061759 USER_MC14_LADDR_RA15_RA17_MAP 0x00000 USER_MC14_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC14_LADDR_CA5_CA9_MAP 0x00000001 USER_MC14_LADDR_CA10_CA15_MAP 0x00000000 USER_MC14_BG_INTERLEAVE_EN true USER_MC14_EN_TEMP_CTRL_REF_MODE false USER_MC14_EN_TEMP_COMP_SF_PERIOD false USER_MC14_REF_CMD_PERIOD 0x0924 USER_MC14_EN_SBREF false USER_MC14_BURST_RW_REFRESH_HOLDOFF false USER_MC14_SBREF_ISSUE_PER 0x01e false USER_MC14_LOOKAHEAD_PCH true USER_MC14_LOOKAHEAD_ACT true USER_MC14_REORDER_EN true USER_MC14_REORDER_RW_ONLY false USER_MC14_REORDER_QUEUE_EN true USER_MC14_MAINTAIN_COHERENCY true USER_MC14_Q_AGE_LIMIT 0x7f USER_MC14_EN_DATA_MASK true USER_MC14_INIT_PERR_RETRY_EN false USER_MC14_USER_PARITY_EN false USER_MC14_DQ_PARITY_EN false USER_MC14_RD_DQ_PARITY_EN false USER_MC14_WR_DQ_PARITY_EN false USER_MC14_CA_PARITY_EN false USER_MC14_HBM_CB_EN false USER_MC14_DM_EN true false USER_MC14_RMW_EN false false USER_MC15_MANUAL_ADDR_MAP_SEL false false USER_MC15_MANUAL_REFRESH_SEL false USER_MC15_MANUAL_ADV_OPTIONS false USER_MC15_COL_ADDR_LOW 0x4 USER_MC15_COL_ADDR_HIGH 0x4 USER_MC15_LADDR_BA0_BA4_MAP 0x00282248 USER_MC15_LADDR_BA5_MAP 0x05 USER_MC15_LADDR_RA0_RA4_MAP 0x0f38d30b USER_MC15_LADDR_RA5_RA9_MAP 0x55134914 USER_MC15_LADDR_RA10_RA14_MAP 0x00061759 USER_MC15_LADDR_RA15_RA17_MAP 0x00000 USER_MC15_LADDR_CA0_CA4_MAP 0xc61440c0 USER_MC15_LADDR_CA5_CA9_MAP 0x00000001 USER_MC15_LADDR_CA10_CA15_MAP 0x00000000 USER_MC15_BG_INTERLEAVE_EN true USER_MC15_EN_TEMP_CTRL_REF_MODE false USER_MC15_EN_TEMP_COMP_SF_PERIOD false USER_MC15_REF_CMD_PERIOD 0x0924 USER_MC15_EN_SBREF false USER_MC15_BURST_RW_REFRESH_HOLDOFF false USER_MC15_SBREF_ISSUE_PER 0x01e false USER_MC15_LOOKAHEAD_PCH true USER_MC15_LOOKAHEAD_ACT true USER_MC15_REORDER_EN true USER_MC15_REORDER_RW_ONLY false USER_MC15_REORDER_QUEUE_EN true USER_MC15_MAINTAIN_COHERENCY true USER_MC15_Q_AGE_LIMIT 0x7f USER_MC15_EN_DATA_MASK true USER_MC15_INIT_PERR_RETRY_EN false USER_MC15_USER_PARITY_EN false USER_MC15_DQ_PARITY_EN false USER_MC15_RD_DQ_PARITY_EN false USER_MC15_WR_DQ_PARITY_EN false USER_MC15_CA_PARITY_EN false USER_MC15_HBM_CB_EN false USER_MC15_DM_EN true false USER_MC15_RMW_EN false false USER_MC0_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC0_CA0_CA5_MAP 0x1c61440c0 USER_MC1_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC1_CA0_CA5_MAP 0x1c61440c0 USER_MC2_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC2_CA0_CA5_MAP 0x1c61440c0 USER_MC3_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC3_CA0_CA5_MAP 0x1c61440c0 USER_MC4_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC4_CA0_CA5_MAP 0x1c61440c0 USER_MC5_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC5_CA0_CA5_MAP 0x1c61440c0 USER_MC6_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC6_CA0_CA5_MAP 0x1c61440c0 USER_MC7_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC7_CA0_CA5_MAP 0x1c61440c0 USER_MC8_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC8_CA0_CA5_MAP 0x1c61440c0 USER_MC9_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC9_CA0_CA5_MAP 0x1c61440c0 USER_MC10_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC10_CA0_CA5_MAP 0x1c61440c0 USER_MC11_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC11_CA0_CA5_MAP 0x1c61440c0 USER_MC12_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC12_CA0_CA5_MAP 0x1c61440c0 USER_MC13_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC13_CA0_CA5_MAP 0x1c61440c0 USER_MC14_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC14_CA0_CA5_MAP 0x1c61440c0 USER_MC15_RA0_RA13_MAPPING 0x61759551349140f38d30b USER_MC15_CA0_CA5_MAP 0x1c61440c0 USER_MC0_ADDR_BIT MC0 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC1_ADDR_BIT MC1 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC2_ADDR_BIT MC2 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC3_ADDR_BIT MC2 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC4_ADDR_BIT MC4 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC5_ADDR_BIT MC5 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC6_ADDR_BIT MC6 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC7_ADDR_BIT MC7 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC8_ADDR_BIT MC8 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC9_ADDR_BIT MC9 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC10_ADDR_BIT MC10 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC11_ADDR_BIT MC11 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC12_ADDR_BIT MC12 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC13_ADDR_BIT MC13 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC14_ADDR_BIT MC14 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_MC15_ADDR_BIT MC15 Address Map NA,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,BG1,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BG0 false USER_READ_PERCENT_00 40 USER_READ_PERCENT_01 40 USER_READ_PERCENT_02 40 USER_READ_PERCENT_03 40 USER_READ_PERCENT_04 40 USER_READ_PERCENT_05 40 USER_READ_PERCENT_06 40 USER_READ_PERCENT_07 40 USER_READ_PERCENT_08 40 USER_READ_PERCENT_09 40 USER_READ_PERCENT_10 40 USER_READ_PERCENT_11 40 USER_READ_PERCENT_12 40 USER_READ_PERCENT_13 40 USER_READ_PERCENT_14 40 USER_READ_PERCENT_15 40 USER_READ_PERCENT_16 40 USER_READ_PERCENT_17 40 USER_READ_PERCENT_18 40 USER_READ_PERCENT_19 40 USER_READ_PERCENT_20 40 USER_READ_PERCENT_21 40 USER_READ_PERCENT_22 40 USER_READ_PERCENT_23 40 USER_READ_PERCENT_24 40 USER_READ_PERCENT_25 40 USER_READ_PERCENT_26 40 USER_READ_PERCENT_27 40 USER_READ_PERCENT_28 40 USER_READ_PERCENT_29 40 USER_READ_PERCENT_30 40 USER_READ_PERCENT_31 40 USER_WRITE_PERCENT_00 40 USER_WRITE_PERCENT_01 40 USER_WRITE_PERCENT_02 40 USER_WRITE_PERCENT_03 40 USER_WRITE_PERCENT_04 40 USER_WRITE_PERCENT_05 40 USER_WRITE_PERCENT_06 40 USER_WRITE_PERCENT_07 40 USER_WRITE_PERCENT_08 40 USER_WRITE_PERCENT_09 40 USER_WRITE_PERCENT_10 40 USER_WRITE_PERCENT_11 40 USER_WRITE_PERCENT_12 40 USER_WRITE_PERCENT_13 40 USER_WRITE_PERCENT_14 40 USER_WRITE_PERCENT_15 40 USER_WRITE_PERCENT_16 40 USER_WRITE_PERCENT_17 40 USER_WRITE_PERCENT_18 40 USER_WRITE_PERCENT_19 40 USER_WRITE_PERCENT_20 40 USER_WRITE_PERCENT_21 40 USER_WRITE_PERCENT_22 40 USER_WRITE_PERCENT_23 40 USER_WRITE_PERCENT_24 40 USER_WRITE_PERCENT_25 40 USER_WRITE_PERCENT_26 40 USER_WRITE_PERCENT_27 40 USER_WRITE_PERCENT_28 40 USER_WRITE_PERCENT_29 40 USER_WRITE_PERCENT_30 40 USER_WRITE_PERCENT_31 40 USER_PAGEHIT_PERCENT_00 75 USER_PAGEHIT_PERCENT_01 75 USER_SAXI_00 true false USER_SAXI_01 true false USER_SAXI_02 true false USER_SAXI_03 true false USER_SAXI_04 true false USER_SAXI_05 true false USER_SAXI_06 true false USER_SAXI_07 true false USER_SAXI_08 true false USER_SAXI_09 true false USER_SAXI_10 true false USER_SAXI_11 true false USER_SAXI_12 true false USER_SAXI_13 true false USER_SAXI_14 true false USER_SAXI_15 true false USER_SAXI_16 true false USER_SAXI_17 true false USER_SAXI_18 true false USER_SAXI_19 true false USER_SAXI_20 true false USER_SAXI_21 true false USER_SAXI_22 true false USER_SAXI_23 true false USER_SAXI_24 true false USER_SAXI_25 true false USER_SAXI_26 true false USER_SAXI_27 true false USER_SAXI_28 true false USER_SAXI_29 true false USER_SAXI_30 true false USER_SAXI_31 true false USER_APB_EN false USER_DFI_CLK0_FREQ 300.000 USER_DFI_CLK1_FREQ 300.000 USER_AXI_CLK_FREQ 300.000 false USER_AXI_INPUT_CLK_FREQ 100 USER_AXI_INPUT_CLK_NS 10.000 USER_AXI_INPUT_CLK_PS 10000 USER_AXI_INPUT_CLK_XDC 10.000 HBM_MMCM_FBOUT_MULT0 9 false HBM_MMCM_CLKOUTDIV0 3 false HBM_MMCM_DIVCLK_DIV0 1 false USER_AXI_CLK1_FREQ 300.000 false USER_AXI_INPUT_CLK1_FREQ 100 USER_AXI_INPUT_CLK1_NS 10.000 USER_AXI_INPUT_CLK1_PS 10000 USER_AXI_INPUT_CLK1_XDC 10.000 HBM_MMCM1_FBOUT_MULT0 9 false HBM_MMCM1_CLKOUTDIV0 3 false HBM_MMCM1_DIVCLK_DIV0 1 false USER_PHY_ENABLE_00 TRUE USER_PHY_ENABLE_01 TRUE USER_PHY_ENABLE_02 TRUE USER_PHY_ENABLE_03 TRUE USER_PHY_ENABLE_04 TRUE USER_PHY_ENABLE_05 TRUE USER_PHY_ENABLE_06 TRUE USER_PHY_ENABLE_07 TRUE USER_PHY_ENABLE_08 TRUE USER_PHY_ENABLE_09 TRUE USER_PHY_ENABLE_10 TRUE USER_PHY_ENABLE_11 TRUE USER_PHY_ENABLE_12 TRUE USER_PHY_ENABLE_13 TRUE USER_PHY_ENABLE_14 TRUE USER_PHY_ENABLE_15 TRUE USER_CHAR_BOARD UC1899 USER_EXAMPLE_TG SYNTHESIZABLE false USER_CLOCKS_SELECTION MULTIPLE false USER_CLK_MMCM_INPUT_FREQ 100 USER_CLK_MMCM_OUT1 10 USER_CLK_MMCM_OUT2 10 USER_CLK_MMCM_OUT3 10 USER_CLK_MMCM_OUT4 10 USER_CLK_MMCM_OUT5 10 USER_CLK_MMCM_OUT6 10 false USER_1CLK_MMCM_CLKFBOUT_MULT 9 USER_1CLK_MMCM_CLKOUTDIV1 2 USER_1CLK_MMCM_CLKOUTDIV2 2 USER_1CLK_MMCM_CLKOUTDIV3 2 USER_1CLK_MMCM_CLKOUTDIV4 2 USER_1CLK_MMCM_CLKOUTDIV5 2 USER_1CLK_MMCM_CLKOUTDIV6 2 USER_1CLK_MMCM_DIVCLK_DIV 1 USER_HBM_PLL_OP_FOR_TCK_0 450 USER_HBM_PLL_OP_FOR_TCK_1 450 USER_HBM_OP_TCK_0 10 USER_HBM_OP_TCK_1 10 Component_Name hbm_0 HBM IP XPM_MEMORY xtlm protobuf 9 2020.2