xilinx.com xci unknown 1.0 pr_read_mem 4096 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 OTHER NONE 8192 32 1 OTHER NONE 8192 32 1 100000000 0 0 0.000 0 5 5 1 4 0 1 9 0 0 1 NONE 0 0 0 ./ 0 0 0 0 0 0 0 0 Estimated Power for IP : 5.931282 mW virtexuplusHBM 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pr_read_mem.mem pr_read_mem.mif 0 1 0 0 1 32 32 1 1 64 64 0 0 CE CE ALL 0 0 0 0 0 0 0 1 1 32 32 WRITE_FIRST WRITE_FIRST 64 64 virtexuplusHBM 4 Memory_Slave AXI4_Full false Minimum_Area false 9 NONE ../../../../coe/read.coe ALL pr_read_mem false false false false false false false false false Use_ENA_Pin Always_Enabled Single_Bit_Error_Injection false Native true no_mem_loaded Single_Port_RAM WRITE_FIRST WRITE_FIRST 0 0 BRAM 0 100 100 50 0 0 0 8kx2 false false 1 1 64 64 false false false false 0 false false CE CE SYNC false false false false false false false 32 64 64 No_ECC false false false Stand_Alone virtexuplusHBM xilinx.com:au50:part0:1.3 xcu50 fsvh2104 VERILOG MIXED -2 E TRUE TRUE IP_Flow 4 TRUE . . 2020.2 OUT_OF_CONTEXT