xilinx.com xci unknown 1.0 wrdata_fifo 100000000 0 0 0.000 100000000 0 0 0.000 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 300000000 0 0 0.000 100000000 0 0 0.000 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 150000000 0 0 0.000 0 0 0 0 0 0 0 8 1 1 1 1 4 0 32 1 1 1 64 1 8 1 1 1 1 0 0 9 BlankString 1024 1 32 64 1 64 2 0 512 0 1 0 0 0 0 0 0 0 0 virtexuplusHBM 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 6 1 1 1 1 1 1 0 0 4 BlankString 1 0 0 0 2 1 512x72 1kx18 512x36 512x72 512x36 512x72 512x36 2 1022 1022 1022 1022 1022 1022 3 0 0 0 0 0 0 0 510 1023 1023 1023 1023 1023 1023 509 0 0 0 0 0 0 0 0 0 10 1024 300 10 0 0 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 9 512 1024 16 1024 16 1024 16 150 9 10 4 10 4 10 4 1 32 0 0 false false false 0 0 Slave_Interface_Clock_Enable Common_Clock wrdata_fifo 64 false 9 false false 0 2 1022 1022 1022 1022 1022 1022 3 false false false false false false false false false Hard_ECC false false false false false false true false false true Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Independent_Clocks_Builtin_FIFO 0 510 1023 1023 1023 1023 1023 1023 509 false false false 0 Native false false false false false false false false false false false false false false 1024 512 1024 16 1024 16 1024 16 false 512 1024 Embedded_Reg false false Active_High Active_High AXI4 Standard_FIFO No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold READ_WRITE 0 300 false 10 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered true Synchronous_Reset false 1 0 0 1 1 4 false false Active_High Active_High true true false false false Active_High 0 false Active_High 150 false 9 true FIFO false false false false FIFO FIFO 2 2 false FIFO FIFO FIFO virtexuplusHBM xilinx.com:au50:part0:1.3 xcu50 fsvh2104 VERILOG MIXED -2 E TRUE TRUE IP_Flow 5 TRUE . . 2020.2 OUT_OF_CONTEXT