xilinx.com customized_ip xdma_pcie4c_ip 1.0 m_axis_cq m_axis_cq The Completer Request interface is used to transmit Completion TLP's to the Client Application TDATA m_axis_cq_tdata TKEEP m_axis_cq_tkeep TLAST m_axis_cq_tlast TREADY m_axis_cq_tready TUSER m_axis_cq_tuser TVALID m_axis_cq_tvalid TDATA_NUM_BYTES 32 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 88 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl s_axis_cc s_axis_cc The Completer Completion Interface is used to transmit Completion TLP's TDATA s_axis_cc_tdata TKEEP s_axis_cc_tkeep TLAST s_axis_cc_tlast TREADY s_axis_cc_tready TUSER s_axis_cc_tuser TVALID s_axis_cc_tvalid TDATA_NUM_BYTES 32 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 33 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl s_axis_rq s_axis_rq The Requestor Request interface received requests TLP's from the Client Application TDATA s_axis_rq_tdata TKEEP s_axis_rq_tkeep TLAST s_axis_rq_tlast TREADY s_axis_rq_tready TUSER s_axis_rq_tuser TVALID s_axis_rq_tvalid TDATA_NUM_BYTES 32 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 62 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl m_axis_rc m_axis_rc The Requestor Completer interface transmits completions to the client application TDATA m_axis_rc_tdata TKEEP m_axis_rc_tkeep TLAST m_axis_rc_tlast TREADY m_axis_rc_tready TUSER m_axis_rc_tuser TVALID m_axis_rc_tvalid TDATA_NUM_BYTES 32 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 75 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl cxs_tx ACTIVE_ACK cxs0_active_ack_tx ACTIVE_REQ cxs0_active_req_tx CNTL cxs0_cntl_tx CNTL_CHK cxs0_cntl_chk_tx CRDGNT cxs0_crdgnt_tx CRDGNT_CHK cxs0_crdgnt_chk_tx CRDRTN cxs0_crdrtn_tx CRDRTN_CHK cxs0_crdrtn_chk_tx DATA cxs0_data_tx DATA_CHK cxs0_data_chk_tx DEACT_HINT cxs0_deact_hint_tx VALID cxs0_valid_tx VALID_CHK cxs0_valid_chk_tx DATA_FLIT_WIDTH 256 MAX_PKT_PER_FLIT 2 DATACHECK NONE none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none false cxs_rx ACTIVE_ACK cxs0_active_ack_rx ACTIVE_REQ cxs0_active_req_rx CNTL cxs0_cntl_rx CNTL_CHK cxs0_cntl_chk_rx CRDGNT cxs0_crdgnt_rx CRDGNT_CHK cxs0_crdgnt_chk_rx CRDRTN cxs0_crdrtn_rx CRDRTN_CHK cxs0_crdrtn_chk_rx DATA cxs0_data_rx DATA_CHK cxs0_data_chk_rx DEACT_HINT cxs0_deact_hint_rx VALID cxs0_valid_rx VALID_CHK cxs0_valid_chk_rx DATA_FLIT_WIDTH 256 MAX_PKT_PER_FLIT 2 DATACHECK NONE none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none false CLK.s_aclk CLK.s_aclk CLK s_aclk ASSOCIATED_BUSIF S_AXI_DVSEC FREQ_HZ 250000000 ASSOCIATED_RESET s_aresetn FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none INSERT_VIP 0 simulation.rtl false RST.s_aresetn RST.s_aresetn RST s_aresetn POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false S_AXI_DVSEC ARADDR s_axi_araddr ARBURST s_axi_arburst ARCACHE s_axi_arcache ARID s_axi_arid ARLEN s_axi_arlen ARLOCK s_axi_arlock ARPROT s_axi_arprot ARQOS s_axi_arqos ARREADY s_axi_arready ARSIZE s_axi_arsize ARUSER s_axi_aruser ARVALID s_axi_arvalid AWADDR s_axi_awaddr AWBURST s_axi_awburst AWCACHE s_axi_awcache AWID s_axi_awid AWLEN s_axi_awlen AWLOCK s_axi_awlock AWPROT s_axi_awprot AWQOS s_axi_awqos AWREADY s_axi_awready AWSIZE s_axi_awsize AWUSER s_axi_awuser AWVALID s_axi_awvalid BID s_axi_bid BREADY s_axi_bready BRESP s_axi_bresp BVALID s_axi_bvalid RDATA s_axi_rdata RID s_axi_rid RLAST s_axi_rlast RREADY s_axi_rready RRESP s_axi_rresp RVALID s_axi_rvalid WDATA s_axi_wdata WLAST s_axi_wlast WREADY s_axi_wready WSTRB s_axi_wstrb WVALID s_axi_wvalid DATA_WIDTH 1 none PROTOCOL AXI4LITE none FREQ_HZ 100000000 none ID_WIDTH 0 none ADDR_WIDTH 1 none AWUSER_WIDTH 0 none ARUSER_WIDTH 0 none WUSER_WIDTH 0 none RUSER_WIDTH 0 none BUSER_WIDTH 0 none READ_WRITE_MODE READ_WRITE none HAS_BURST 0 none HAS_LOCK 0 none HAS_PROT 0 none HAS_CACHE 0 none HAS_QOS 0 none HAS_REGION 0 none HAS_WSTRB 0 none HAS_BRESP 0 none HAS_RRESP 0 none SUPPORTS_NARROW_BURST 0 none NUM_READ_OUTSTANDING 1 none NUM_WRITE_OUTSTANDING 1 none MAX_BURST_LENGTH 1 none PHASE 0.000 none CLK_DOMAIN none NUM_READ_THREADS 1 none NUM_WRITE_THREADS 1 none RUSER_BITS_PER_BYTE 0 none WUSER_BITS_PER_BYTE 0 none INSERT_VIP 0 simulation.rtl false RST.sys_rst RST.sys_rst sys_rst interface RST sys_reset BOARD.ASSOCIATED_PARAM SYS_RST_N_BOARD_INTERFACE required TYPE PCIE_PERST POLARITY ACTIVE_LOW none INSERT_VIP 0 simulation.rtl pcie4_mgt pcie_7x_mgt PCIExpress Serial Link Interface rxn pci_exp_rxn rxp pci_exp_rxp txn pci_exp_txn txp pci_exp_txp BOARD.ASSOCIATED_PARAM PCIE_BOARD_INTERFACE required true pcie4_cfg_fc pcie_cfg_fc Configuration Flow Control INTERFACE CPLD cfg_fc_cpld CPLH cfg_fc_cplh NPD cfg_fc_npd NPH cfg_fc_nph PD cfg_fc_pd PH cfg_fc_ph SEL cfg_fc_sel true pcie4_cfg_mgmt pcie4_cfg_mgmt PCIE Configuration Management Interface ADDR cfg_mgmt_addr BYTE_EN cfg_mgmt_byte_enable DEBUG_ACCESS cfg_mgmt_debug_access FUNCTION_NUMBER cfg_mgmt_function_number READ_DATA cfg_mgmt_read_data READ_EN cfg_mgmt_read READ_WRITE_DONE cfg_mgmt_read_write_done WRITE_DATA cfg_mgmt_write_data WRITE_EN cfg_mgmt_write true pcie4_cfg_mgmt_if pcie4_cfg_mgmt PCIE Configuration Management Interface ADDR cfg_mgmt_addr BYTE_EN cfg_mgmt_byte_enable DEBUG_ACCESS cfg_mgmt_debug_access FUNCTION_NUMBER cfg_mgmt_function_number READ_DATA cfg_mgmt_read_data READ_EN cfg_mgmt_read READ_WRITE_DONE cfg_mgmt_read_write_done WRITE_DATA cfg_mgmt_write_data WRITE_EN cfg_mgmt_write false pcie4_cfg_pm pcie4_cfg_pm PCIE4 Power Management Interface pm_aspm_l1entry_reject cfg_pm_aspm_l1_entry_reject pm_aspm_tx_l0s_entry_disable cfg_pm_aspm_tx_l0s_entry_disable true pcie4_cfg_msi pcie4_cfg_msi PCIE MSI interrupt attr cfg_interrupt_msi_attr data cfg_interrupt_msi_data enable cfg_interrupt_msi_enable fail cfg_interrupt_msi_fail function_number cfg_interrupt_msi_function_number int_vector cfg_interrupt_msi_int mask_update cfg_interrupt_msi_mask_update mmenable cfg_interrupt_msi_mmenable pending_status cfg_interrupt_msi_pending_status pending_status_data_enable cfg_interrupt_msi_pending_status_data_enable pending_status_function_num cfg_interrupt_msi_pending_status_function_num select cfg_interrupt_msi_select sent cfg_interrupt_msi_sent tph_present cfg_interrupt_msi_tph_present tph_st_tag cfg_interrupt_msi_tph_st_tag tph_type cfg_interrupt_msi_tph_type true pcie4_cfg_msix_internal pcie4_cfg_msix_internal PCIE MSIx Int Interrupt attr cfg_interrupt_msi_attr enable cfg_interrupt_msix_enable fail cfg_interrupt_msi_fail function_number cfg_interrupt_msi_function_number int_vector cfg_interrupt_msix_int mask cfg_interrupt_msix_mask mint_vector cfg_interrupt_msi_int sent cfg_interrupt_msi_sent tph_present cfg_interrupt_msi_tph_present tph_st_tag cfg_interrupt_msi_tph_st_tag tph_type cfg_interrupt_msi_tph_type vec_pending cfg_interrupt_msix_vec_pending vec_pending_status cfg_interrupt_msix_vec_pending_status vf_enable cfg_interrupt_msix_vf_enable vf_mask cfg_interrupt_msix_vf_mask false pcie4_cfg_msix_internal_if pcie4_cfg_msix_internal PCIE MSIx Int Interrupt attr cfg_interrupt_msi_attr enable cfg_interrupt_msix_enable fail cfg_interrupt_msi_fail function_number cfg_interrupt_msi_function_number int_vector cfg_interrupt_msix_int mask cfg_interrupt_msix_mask mint_vector cfg_interrupt_msi_int sent cfg_interrupt_msi_sent tph_present cfg_interrupt_msi_tph_present tph_st_tag cfg_interrupt_msi_tph_st_tag tph_type cfg_interrupt_msi_tph_type vec_pending cfg_interrupt_msix_vec_pending vec_pending_status cfg_interrupt_msix_vec_pending_status vf_enable cfg_interrupt_msix_vf_enable vf_mask cfg_interrupt_msix_vf_mask false pcie4_cfg_external_msix pcie4_cfg_external_msix_without_msi PCIE MSI-X Interrupt address cfg_interrupt_msix_address data cfg_interrupt_msix_data enable cfg_interrupt_msix_enable fail cfg_interrupt_msi_fail function_number cfg_interrupt_msi_function_number int_vector cfg_interrupt_msix_int mask cfg_interrupt_msix_mask sent cfg_interrupt_msi_sent vec_pending cfg_interrupt_msix_vec_pending vec_pending_status cfg_interrupt_msix_vec_pending_status vf_enable cfg_interrupt_msix_vf_enable vf_mask cfg_interrupt_msix_vf_mask false pcie4_cfg_external_msix_without_msi_if pcie4_cfg_external_msix_without_msi PCIE MSI-X Interrupt address cfg_interrupt_msix_address data cfg_interrupt_msix_data enable cfg_interrupt_msix_enable fail cfg_interrupt_msi_fail function_number cfg_interrupt_msi_function_number int_vector cfg_interrupt_msix_int mask cfg_interrupt_msix_mask sent cfg_interrupt_msi_sent vec_pending cfg_interrupt_msix_vec_pending vec_pending_status cfg_interrupt_msix_vec_pending_status vf_enable cfg_interrupt_msix_vf_enable vf_mask cfg_interrupt_msix_vf_mask false pcie4_cfg_msix_external pcie4_cfg_external_msix_with_msi PCIE MSI-X Interrupt address cfg_interrupt_msix_address data cfg_interrupt_msix_data enable cfg_interrupt_msix_enable int_vector cfg_interrupt_msix_int mask cfg_interrupt_msix_mask vec_pending cfg_interrupt_msix_vec_pending vec_pending_status cfg_interrupt_msix_vec_pending_status vf_enable cfg_interrupt_msix_vf_enable vf_mask cfg_interrupt_msix_vf_mask false pcie4_cfg_external_msix_with_msi_if pcie4_cfg_external_msix_with_msi PCIE MSI-X Interrupt address cfg_interrupt_msix_address data cfg_interrupt_msix_data enable cfg_interrupt_msix_enable int_vector cfg_interrupt_msix_int mask cfg_interrupt_msix_mask vec_pending cfg_interrupt_msix_vec_pending vec_pending_status cfg_interrupt_msix_vec_pending_status vf_enable cfg_interrupt_msix_vf_enable vf_mask cfg_interrupt_msix_vf_mask false pcie4_cfg_interrupt pcie4_cfg_interrupt PCIE Legacy Interrupt INTx_VECTOR cfg_interrupt_int PENDING cfg_interrupt_pending SENT cfg_interrupt_sent pcie4_cfg_ext pcie4_cfg_ext Configuration Extend Interface function_number cfg_ext_function_number read_data cfg_ext_read_data read_data_valid cfg_ext_read_data_valid read_received cfg_ext_read_received register_number cfg_ext_register_number write_byte_enable cfg_ext_write_byte_enable write_data cfg_ext_write_data write_received cfg_ext_write_received false pcie4_rbar pcie4_rbar Resizable bar Interface bar_size rbar_bar_size function_number rbar_function_number write_enable_bar0 rbar_write_enable_bar0 write_enable_bar1 rbar_write_enable_bar1 write_enable_bar2 rbar_write_enable_bar2 write_enable_bar3 rbar_write_enable_bar3 write_enable_bar4 rbar_write_enable_bar4 write_enable_bar5 rbar_write_enable_bar5 false pcie4_cfg_mesg_tx pcie4_cfg_mesg_tx Configuration Transmit Message Interface TRANSMIT cfg_msg_transmit TRANSMIT_DATA cfg_msg_transmit_data TRANSMIT_DONE cfg_msg_transmit_done TRANSMIT_TYPE cfg_msg_transmit_type true pcie4_cfg_mesg_rcvd pcie4_cfg_mesg_rcvd Configuration Received Message Interface recd cfg_msg_received recd_data cfg_msg_received_data recd_type cfg_msg_received_type true pcie4_cfg_control pcie4_cfg_control It allows a broad range of information exchange between user application and the core bus_number cfg_bus_number config_space_enable cfg_config_space_enable ds_bus_number cfg_ds_bus_number ds_device_number cfg_ds_device_number ds_port_number cfg_ds_port_number dsn cfg_dsn err_cor_in cfg_err_cor_in err_uncor_in cfg_err_uncor_in flr_done cfg_flr_done flr_in_process cfg_flr_in_process hot_reset_in cfg_hot_reset_in hot_reset_out cfg_hot_reset_out link_training_enable cfg_link_training_enable power_state_change_ack cfg_power_state_change_ack power_state_change_interrupt cfg_power_state_change_interrupt req_pm_transition_l23_ready cfg_req_pm_transition_l23_ready vf_flr_done cfg_vf_flr_done vf_flr_func_num cfg_vf_flr_func_num vf_flr_in_process cfg_vf_flr_in_process true pcie4_cfg_control_if pcie4_cfg_control It allows a broad range of information exchange between user application and the core bus_number cfg_bus_number config_space_enable cfg_config_space_enable ds_bus_number cfg_ds_bus_number ds_device_number cfg_ds_device_number ds_function_number cfg_ds_function_number ds_port_number cfg_ds_port_number dsn cfg_dsn err_cor_in cfg_err_cor_in err_uncor_in cfg_err_uncor_in flr_done cfg_flr_done flr_in_process cfg_flr_in_process hot_reset_in cfg_hot_reset_in hot_reset_out cfg_hot_reset_out link_training_enable cfg_link_training_enable pm_aspm_l1entry_reject cfg_pm_aspm_l1_entry_reject pm_aspm_tx_l0s_entry_disable cfg_pm_aspm_tx_l0s_entry_disable power_state_change_ack cfg_power_state_change_ack power_state_change_interrupt cfg_power_state_change_interrupt rbar_function_number rbar_function_number rbar_size rbar_bar_size req_pm_transition_l23_ready cfg_req_pm_transition_l23_ready vf_flr_done cfg_vf_flr_done vf_flr_func_num cfg_vf_flr_func_num vf_flr_in_process cfg_vf_flr_in_process write_enable_rbar0 rbar_write_enable_bar0 write_enable_rbar1 rbar_write_enable_bar1 write_enable_rbar2 rbar_write_enable_bar2 write_enable_rbar3 rbar_write_enable_bar3 write_enable_rbar4 rbar_write_enable_bar4 write_enable_rbar5 rbar_write_enable_bar5 false pcie4_pcie_id pcie4_pcie_id PCIE 4 PCIE ID interface subsys_vend_id cfg_subsys_vend_id vend_id cfg_vend_id false pcie4_pcie_id_pf0 pcie4_pcie_id_pf0 PCIE 4 PCIE ID interface dev_id_pf0 cfg_dev_id_pf0 rev_id_pf0 cfg_rev_id_pf0 subsys_id_pf0 cfg_subsys_id_pf0 false pcie4_pcie_id_pf1 pcie4_pcie_id_pf1 PCIE 4 PCIE ID interface dev_id_pf1 cfg_dev_id_pf1 rev_id_pf1 cfg_rev_id_pf1 subsys_id_pf1 cfg_subsys_id_pf1 false pcie4_pcie_id_pf2 pcie4_pcie_id_pf2 PCIE 4 PCIE ID interface dev_id_pf2 cfg_dev_id_pf2 rev_id_pf2 cfg_rev_id_pf2 subsys_id_pf2 cfg_subsys_id_pf2 false pcie4_pcie_id_pf3 pcie4_pcie_id_pf3 PCIE 4 PCIE ID interface dev_id_pf3 cfg_dev_id_pf3 rev_id_pf3 cfg_rev_id_pf3 subsys_id_pf3 cfg_subsys_id_pf3 false pcie4_cfg_status pcie4_cfg_status Configuration Status Interface cq_np_req pcie_cq_np_req cq_np_req_count pcie_cq_np_req_count current_speed cfg_current_speed err_cor_out cfg_err_cor_out err_fatal_out cfg_err_fatal_out err_nonfatal_out cfg_err_nonfatal_out function_power_state cfg_function_power_state function_status cfg_function_status link_power_state cfg_link_power_state local_error_out cfg_local_error_out local_error_valid cfg_local_error_valid ltssm_state cfg_ltssm_state max_payload cfg_max_payload max_read_req cfg_max_read_req negotiated_width cfg_negotiated_width obff_enable cfg_obff_enable phy_link_down cfg_phy_link_down phy_link_status cfg_phy_link_status pl_status_change cfg_pl_status_change rcb_status cfg_rcb_status rq_seq_num0 pcie_rq_seq_num0 rq_seq_num1 pcie_rq_seq_num1 rq_seq_num_vld0 pcie_rq_seq_num_vld0 rq_seq_num_vld1 pcie_rq_seq_num_vld1 rq_tag0 pcie_rq_tag0 rq_tag1 pcie_rq_tag1 rq_tag_av pcie_rq_tag_av rq_tag_vld0 pcie_rq_tag_vld0 rq_tag_vld1 pcie_rq_tag_vld1 rx_pm_state cfg_rx_pm_state tph_requester_enable cfg_tph_requester_enable tph_st_mode cfg_tph_st_mode tx_pm_state cfg_tx_pm_state vf_power_state cfg_vf_power_state vf_status cfg_vf_status vf_tph_requester_enable cfg_vf_tph_requester_enable vf_tph_st_mode cfg_vf_tph_st_mode true pcie4_cfg_status_if pcie4_cfg_status Configuration Status Interface cq_np_req pcie_cq_np_req cq_np_req_count pcie_cq_np_req_count current_speed cfg_current_speed err_cor_out cfg_err_cor_out err_fatal_out cfg_err_fatal_out err_nonfatal_out cfg_err_nonfatal_out function_power_state cfg_function_power_state function_status cfg_function_status link_power_state cfg_link_power_state local_error_out cfg_local_error_out local_error_valid cfg_local_error_valid ltssm_state cfg_ltssm_state max_payload cfg_max_payload max_read_req cfg_max_read_req negotiated_width cfg_negotiated_width obff_enable cfg_obff_enable phy_link_down cfg_phy_link_down phy_link_status cfg_phy_link_status pl_status_change cfg_pl_status_change rcb_status cfg_rcb_status rq_seq_num0 pcie_rq_seq_num0 rq_seq_num1 pcie_rq_seq_num1 rq_seq_num_vld0 pcie_rq_seq_num_vld0 rq_seq_num_vld1 pcie_rq_seq_num_vld1 rq_tag0 pcie_rq_tag0 rq_tag1 pcie_rq_tag1 rq_tag_av pcie_rq_tag_av rq_tag_vld0 pcie_rq_tag_vld0 rq_tag_vld1 pcie_rq_tag_vld1 rx_pm_state cfg_rx_pm_state tph_requester_enable cfg_tph_requester_enable tph_st_mode cfg_tph_st_mode tx_pm_state cfg_tx_pm_state vf_power_state cfg_vf_power_state vf_status cfg_vf_status vf_tph_requester_enable cfg_vf_tph_requester_enable vf_tph_st_mode cfg_vf_tph_st_mode false pcie4_transmit_fc pcie4_transmit_fc Transmit Flow Control Interfce npd_av pcie_tfc_npd_av nph_av pcie_tfc_nph_av true pcie4_drp pcie4_drp PCIE DRP Interface DADDR drp_addr DEN drp_en DI drp_di DO drp_do DRDY drp_rdy DWE drp_we false pcie4_drp_if pcie4_drp PCIE DRP Interface DADDR drp_addr DEN drp_en DI drp_di DO drp_do DRDY drp_rdy DWE drp_we false CLK.sys_clk CLK.sys_clk sys_clk interface CLK sys_clk FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl CLK.sys_clk_gt CLK.sys_clk_gt sys_clk_gt interface CLK sys_clk_gt FREQ_HZ 100000000 none FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl CLK.user_clk CLK.user_clk user_clk interface CLK user_clk ASSOCIATED_BUSIF m_axis_cq:s_axis_cc:s_axis_rq:m_axis_rc:cxs_rx:cxs_tx FREQ_HZ 125000000 ASSOCIATED_RESET user_reset FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none INSERT_VIP 0 simulation.rtl CLK.mcap_clk CLK.mcap_clk mcap_clk interface CLK mcap_clk FREQ_HZ 125000000 FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false CLK.core_clk CLK.core_clk core_clk interface CLK core_clk FREQ_HZ 500000000 FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false CLK.gt_drp_clk CLK.gt_drp_clk gt_drp_clk interface CLK gt_drp_clk FREQ_HZ 125000000 FREQ_TOLERANCE_HZ 0 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false RST.user_reset RST.user_reset user_reset interface RST user_reset POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl pcie4_pl pcie4_pl Physical Layer Interface eq_in_progress pl_eq_in_progress eq_mismatch pl_eq_mismatch eq_phase pl_eq_phase gen2_upstream_prefer_deemph pl_gen2_upstream_prefer_deemph redo_eq pl_redo_eq redo_eq_pending pl_redo_eq_pending redo_eq_speed pl_redo_eq_speed false configure configure req_data conf_req_data req_ready conf_req_ready req_reg_num conf_req_reg_num req_type conf_req_type req_valid conf_req_valid resp_rdata conf_resp_rdata resp_valid conf_resp_valid false cap cap GNT cap_gnt REL cap_rel REQ cap_req false pcie4_ext_pipe_rp pcie4_ext_pipe_rp PCIE4 External PIPE Interface COMMANDS_IN common_commands_in COMMANDS_OUT common_commands_out RX_0 pipe_rx_0_sigs RX_1 pipe_rx_1_sigs RX_2 pipe_rx_2_sigs RX_3 pipe_rx_3_sigs RX_4 pipe_rx_4_sigs RX_5 pipe_rx_5_sigs RX_6 pipe_rx_6_sigs RX_7 pipe_rx_7_sigs RX_8 pipe_rx_8_sigs RX_9 pipe_rx_9_sigs RX_10 pipe_rx_10_sigs RX_11 pipe_rx_11_sigs RX_12 pipe_rx_12_sigs RX_13 pipe_rx_13_sigs RX_14 pipe_rx_14_sigs RX_15 pipe_rx_15_sigs TX_0 pipe_tx_0_sigs TX_1 pipe_tx_1_sigs TX_2 pipe_tx_2_sigs TX_3 pipe_tx_3_sigs TX_4 pipe_tx_4_sigs TX_5 pipe_tx_5_sigs TX_6 pipe_tx_6_sigs TX_7 pipe_tx_7_sigs TX_8 pipe_tx_8_sigs TX_9 pipe_tx_9_sigs TX_10 pipe_tx_10_sigs TX_11 pipe_tx_11_sigs TX_12 pipe_tx_12_sigs TX_13 pipe_tx_13_sigs TX_14 pipe_tx_14_sigs TX_15 pipe_tx_15_sigs false pcie4_ext_pipe_ep pcie4_ext_pipe_ep PCIE4 External PIPE Interface COMMANDS_IN common_commands_out COMMANDS_OUT common_commands_in RX_0 pipe_tx_0_sigs RX_1 pipe_tx_1_sigs RX_2 pipe_tx_2_sigs RX_3 pipe_tx_3_sigs RX_4 pipe_tx_4_sigs RX_5 pipe_tx_5_sigs RX_6 pipe_tx_6_sigs RX_7 pipe_tx_7_sigs RX_8 pipe_tx_8_sigs RX_9 pipe_tx_9_sigs RX_10 pipe_tx_10_sigs RX_11 pipe_tx_11_sigs RX_12 pipe_tx_12_sigs RX_13 pipe_tx_13_sigs RX_14 pipe_tx_14_sigs RX_15 pipe_tx_15_sigs TX_0 pipe_rx_0_sigs TX_1 pipe_rx_1_sigs TX_2 pipe_rx_2_sigs TX_3 pipe_rx_3_sigs TX_4 pipe_rx_4_sigs TX_5 pipe_rx_5_sigs TX_6 pipe_rx_6_sigs TX_7 pipe_rx_7_sigs TX_8 pipe_rx_8_sigs TX_9 pipe_rx_9_sigs TX_10 pipe_rx_10_sigs TX_11 pipe_rx_11_sigs TX_12 pipe_rx_12_sigs TX_13 pipe_rx_13_sigs TX_14 pipe_rx_14_sigs TX_15 pipe_rx_15_sigs false pcie4_ext_pipe_ep_legacy pcie4_ext_pipe_ep_legacy PCIE4 External PIPE Interface COMMANDS_IN common_commands_out COMMANDS_OUT common_commands_in RX_0 pipe_tx_0_sigs RX_1 pipe_tx_1_sigs RX_2 pipe_tx_2_sigs RX_3 pipe_tx_3_sigs RX_4 pipe_tx_4_sigs RX_5 pipe_tx_5_sigs RX_6 pipe_tx_6_sigs RX_7 pipe_tx_7_sigs RX_8 pipe_tx_8_sigs RX_9 pipe_tx_9_sigs RX_10 pipe_tx_10_sigs RX_11 pipe_tx_11_sigs RX_12 pipe_tx_12_sigs RX_13 pipe_tx_13_sigs RX_14 pipe_tx_14_sigs RX_15 pipe_tx_15_sigs TX_0 pipe_rx_0_sigs TX_1 pipe_rx_1_sigs TX_2 pipe_rx_2_sigs TX_3 pipe_rx_3_sigs TX_4 pipe_rx_4_sigs TX_5 pipe_rx_5_sigs TX_6 pipe_rx_6_sigs TX_7 pipe_rx_7_sigs TX_8 pipe_rx_8_sigs TX_9 pipe_rx_9_sigs TX_10 pipe_rx_10_sigs TX_11 pipe_rx_11_sigs TX_12 pipe_rx_12_sigs TX_13 pipe_rx_13_sigs TX_14 pipe_rx_14_sigs TX_15 pipe_rx_15_sigs false pcie4c_usp_ext_gtcom pcie4c_usp_ext_gtcommon PCIE4 Ultrascale+ External GT COMMON Interface exts_qpll0lock_out ext_qpll0lock_out exts_qpll0outclk_out ext_qpll0outclk_out exts_qpll0outrefclk_out ext_qpll0outrefclk_out exts_qpll0pd ext_qpll0pd exts_qpll0reset ext_qpll0reset exts_qpll1lock_out ext_qpll1lock_out exts_qpll1outclk_out ext_qpll1outclk_out exts_qpll1outrefclk_out ext_qpll1outrefclk_out exts_qpll1pd ext_qpll1pd exts_qpll1reset ext_qpll1reset exts_qpllxrate ext_qpllxrate exts_qpllxrcalenb ext_qpllxrcalenb exts_qpllxrefclk ext_qpllxrefclk false pcie4c_usp_int_gtcom pcie4c_usp_int_gtcommon PCIE4 Ultrascale+ Internal GT COMMON Interface ints_qpll0lock_out int_qpll0lock_out ints_qpll0outclk_out int_qpll0outclk_out ints_qpll0outrefclk_out int_qpll0outrefclk_out ints_qpll1lock_out int_qpll1lock_out ints_qpll1outclk_out int_qpll1outclk_out ints_qpll1outrefclk_out int_qpll1outrefclk_out false pcie_ext_ch_gt pcie_ext_ch_gt channel DRP signals DADDR ext_ch_gt_drpaddr DEN ext_ch_gt_drpen DI ext_ch_gt_drpdi DO ext_ch_gt_drpdo DRDY ext_ch_gt_drprdy DWE ext_ch_gt_drpwe false transceiver_debug transceiver_debug Transceiver Debug Interface bufgtdiv gt_bufgtdiv cpll_lock gt_cplllock dmonfiforeset gt_dmonfiforeset dmonitorclk gt_dmonitorclk dmonitorout gt_dmonitorout eyescandataerror gt_eyescandataerror gen34_eios_det gt_gen34_eios_det gtpowergood gt_gtpowergood loopback gt_loopback pcieuserratedone gt_pcieuserratedone pcieuserratestart gt_pcieuserratestart phystatus gt_phystatus prst_n phy_prst_n qpll0_lock gt_qpll0lock qpll1_lock gt_qpll1lock rate_idle gt_pcierateidle rrst_n phy_rrst_n rst_fsm phy_rst_fsm rst_idle phy_rst_idle rxbufreset gt_rxbufreset rxbufstatus gt_rxbufstatus rxcdrlock gt_rxcdrlock rxcdrreset gt_rxcdrreset rxcommadet gt_rxcommadet rxdfelpmreset gt_rxdfelpmreset rxdlysresetdone gt_rxdlysresetdone rxeq_fsm phy_rxeq_fsm rxoutclk gt_rxoutclk rxoutclkfabric gt_rxoutclkfabric rxoutclkpcs gt_rxoutclkpcs rxpcsreset gt_rxpcsreset rxphaligndone gt_rxphaligndone rxpmareset gt_rxpmareset rxpmaresetdone gt_rxpmaresetdone rxprbscntreset gt_rxprbscntreset rxprbserr gt_rxprbserr rxprbslocked gt_rxprbslocked rxprbssel gt_rxprbssel rxrecclkout gt_rxrecclkout rxresetdone gt_rxresetdone rxstatus gt_rxstatus rxsyncdone gt_rxsyncdone rxvalid gt_rxvalid txdlysresetdone gt_txdlysresetdone txelecidle gt_txelecidle txeq_ctrl phy_txeq_ctrl txeq_fsm phy_txeq_fsm txeq_preset phy_txeq_preset txinhibit gt_txinhibit txoutclk gt_txoutclk txoutclkfabric gt_txoutclkfabric txoutclkpcs gt_txoutclkpcs txpcsreset gt_txpcsreset txphaligndone gt_txphaligndone txphinitdone gt_txphinitdone txpmareset gt_txpmareset txpmaresetdone gt_txpmaresetdone txprbsforceerr gt_txprbsforceerr txprbssel gt_txprbssel txprogdivresetdone gt_txprogdivresetdone txresetdone gt_txresetdone txsyncdone gt_txsyncdone false pcie4_gt_if pcie4_gt_if GT Interface bufgtce_out bufgtce_out bufgtcemask_out bufgtcemask_out bufgtdiv_out bufgtdiv_out bufgtreset_out bufgtreset_out bufgtrstmask_out bufgtrstmask_out cpllfreqlock_in cpllfreqlock_in cplllock_out cplllock_out cpllpd_in cpllpd_in cpllreset_in cpllreset_in dmonfiforeset_in dmonfiforeset_in dmonitorclk_in dmonitorclk_in dmonitorout_out dmonitorout_out drpaddr_in drpaddr_in drpclk_in drpclk_in drpdi_in drpdi_in drpdo_out drpdo_out drpen_in drpen_in drprdy_out drprdy_out drprst_in drprst_in drpwe_in drpwe_in ext_phy_clk_bufg_gt_ce ext_phy_clk_bufg_gt_ce ext_phy_clk_bufg_gt_reset ext_phy_clk_bufg_gt_reset ext_phy_clk_bufgtcemask ext_phy_clk_bufgtcemask ext_phy_clk_bufgtdiv ext_phy_clk_bufgtdiv ext_phy_clk_gt_bufgtrstmask ext_phy_clk_gt_bufgtrstmask ext_phy_clk_int_clock ext_phy_clk_int_clock ext_phy_clk_pclk ext_phy_clk_pclk ext_phy_clk_pclk2_gt ext_phy_clk_pclk2_gt ext_phy_clk_phy_coreclk ext_phy_clk_phy_coreclk ext_phy_clk_phy_mcapclk ext_phy_clk_phy_mcapclk ext_phy_clk_phy_pclk2 ext_phy_clk_phy_pclk2 ext_phy_clk_phy_userclk ext_phy_clk_phy_userclk ext_phy_clk_rst_idle ext_phy_clk_rst_idle ext_phy_clk_txoutclk ext_phy_clk_txoutclk eyescanreset_in eyescanreset_in gtpowergood_out gtpowergood_out gtrefclk0_in gtrefclk0_in gtrefclk00_in gtrefclk00_in gtrefclk01_in gtrefclk01_in gtrxreset_in gtrxreset_in gttxreset_in gttxreset_in gtwiz_reset_rx_done_in gtwiz_reset_rx_done_in gtwiz_reset_tx_done_in gtwiz_reset_tx_done_in gtwiz_userclk_rx_active_in gtwiz_userclk_rx_active_in gtwiz_userclk_tx_active_in gtwiz_userclk_tx_active_in loopback_in loopback_in pcieeqrxeqadaptdone_in pcieeqrxeqadaptdone_in pcierategen3_out pcierategen3_out pcierateidle_out pcierateidle_out pcierateqpll0_in pcierateqpll0_in pcierateqpll1_in pcierateqpll1_in pcierateqpllpd_out pcierateqpllpd_out pcierateqpllreset_out pcierateqpllreset_out pcierstidle_in pcierstidle_in pciersttxsyncstart_in pciersttxsyncstart_in pciesynctxsyncdone_out pciesynctxsyncdone_out pcieusergen3rdy_out pcieusergen3rdy_out pcieuserphystatusrst_out pcieuserphystatusrst_out pcieuserratedone_in pcieuserratedone_in pcieuserratestart_out pcieuserratestart_out phystatus_out phystatus_out qpll0freqlock_in qpll0freqlock_in qpll0lock_out qpll0lock_out qpll0outclk_out qpll0outclk_out qpll0outrefclk_out qpll0outrefclk_out qpll0pd_in qpll0pd_in qpll0reset_in qpll0reset_in qpll1freqlock_in qpll1freqlock_in qpll1lock_out qpll1lock_out qpll1outclk_out qpll1outclk_out qpll1outrefclk_out qpll1outrefclk_out qpll1pd_in qpll1pd_in qpll1reset_in qpll1reset_in rcalenb_in rcalenb_in resetovrd_in resetovrd_in rx8b10ben_in rx8b10ben_in rxbufreset_in rxbufreset_in rxbufstatus_out rxbufstatus_out rxbyteisaligned_out rxbyteisaligned_out rxbyterealign_out rxbyterealign_out rxcdrfreqreset_in rxcdrfreqreset_in rxcdrhold_in rxcdrhold_in rxcdrlock_out rxcdrlock_out rxcdrreset_in rxcdrreset_in rxclkcorcnt_out rxclkcorcnt_out rxcommadet_out rxcommadet_out rxcommadeten_in rxcommadeten_in rxctrl0_out rxctrl0_out rxctrl1_out rxctrl1_out rxctrl2_out rxctrl2_out rxctrl3_out rxctrl3_out rxdata_out rxdata_out rxdfeagchold_in rxdfeagchold_in rxdfecfokhold_in rxdfecfokhold_in rxdfekhhold_in rxdfekhhold_in rxdfelfhold_in rxdfelfhold_in rxdfelpmreset_in rxdfelpmreset_in rxdfetap2hold_in rxdfetap2hold_in rxdfetap3hold_in rxdfetap3hold_in rxdfetap4hold_in rxdfetap4hold_in rxdfetap5hold_in rxdfetap5hold_in rxdfetap6hold_in rxdfetap6hold_in rxdfetap7hold_in rxdfetap7hold_in rxdfetap8hold_in rxdfetap8hold_in rxdfetap9hold_in rxdfetap9hold_in rxdfetap10hold_in rxdfetap10hold_in rxdfetap11hold_in rxdfetap11hold_in rxdfetap12hold_in rxdfetap12hold_in rxdfetap13hold_in rxdfetap13hold_in rxdfetap14hold_in rxdfetap14hold_in rxdfetap15hold_in rxdfetap15hold_in rxdfeuthold_in rxdfeuthold_in rxdfevphold_in rxdfevphold_in rxdlysresetdone_out rxdlysresetdone_out rxelecidle_out rxelecidle_out rxlpmen_in rxlpmen_in rxlpmgchold_in rxlpmgchold_in rxlpmhfhold_in rxlpmhfhold_in rxlpmlfhold_in rxlpmlfhold_in rxlpmoshold_in rxlpmoshold_in rxmcommaalignen_in rxmcommaalignen_in rxoshold_in rxoshold_in rxoutclk_out rxoutclk_out rxoutclkfabric_out rxoutclkfabric_out rxoutclkpcs_out rxoutclkpcs_out rxpcommaalignen_in rxpcommaalignen_in rxpcsreset_in rxpcsreset_in rxpd_in rxpd_in rxphaligndone_out rxphaligndone_out rxpmareset_in rxpmareset_in rxpmaresetdone_out rxpmaresetdone_out rxpolarity_in rxpolarity_in rxprbscntreset_in rxprbscntreset_in rxprbserr_out rxprbserr_out rxprbslocked_out rxprbslocked_out rxprbssel_in rxprbssel_in rxprogdivreset_in rxprogdivreset_in rxrate_in rxrate_in rxratedone_out rxratedone_out rxratemode_in rxratemode_in rxrecclkout_out rxrecclkout_out rxresetdone_out rxresetdone_out rxslide_in rxslide_in rxstatus_out rxstatus_out rxsyncdone_out rxsyncdone_out rxtermination_in rxtermination_in rxuserrdy_in rxuserrdy_in rxusrclk2_in rxusrclk2_in rxusrclk_in rxusrclk_in rxvalid_out rxvalid_out tx8b10ben_in tx8b10ben_in txctrl0_in txctrl0_in txctrl1_in txctrl1_in txctrl2_in txctrl2_in txdata_in txdata_in txdeemph_in txdeemph_in txdetectrx_in txdetectrx_in txdiffctrl_in txdiffctrl_in txdlybypass_in txdlybypass_in txdlyen_in txdlyen_in txdlyhold_in txdlyhold_in txdlyovrden_in txdlyovrden_in txdlysreset_in txdlysreset_in txdlysresetdone_out txdlysresetdone_out txdlyupdown_in txdlyupdown_in txelecidle_in txelecidle_in txmaincursor_in txmaincursor_in txmargin_in txmargin_in txoutclk_out txoutclk_out txoutclkfabric_out txoutclkfabric_out txoutclkpcs_out txoutclkpcs_out txoutclksel_in txoutclksel_in txpcsreset_in txpcsreset_in txpd_in txpd_in txpdelecidlemode_in txpdelecidlemode_in txphalign_in txphalign_in txphaligndone_out txphaligndone_out txphalignen_in txphalignen_in txphdlypd_in txphdlypd_in txphdlyreset_in txphdlyreset_in txphdlytstclk_in txphdlytstclk_in txphinit_in txphinit_in txphinitdone_out txphinitdone_out txphovrden_in txphovrden_in txpisopd_in txpisopd_in txpmareset_in txpmareset_in txpmaresetdone_out txpmaresetdone_out txpostcursor_in txpostcursor_in txprbsforceerr_in txprbsforceerr_in txprbssel_in txprbssel_in txprecursor_in txprecursor_in txprgdivresetdone_out txprgdivresetdone_out txprogdivreset_in txprogdivreset_in txrate_in txrate_in txresetdone_out txresetdone_out txswing_in txswing_in txsyncallin_in txsyncallin_in txsyncdone_out txsyncdone_out txsyncin_in txsyncin_in txsyncmode_in txsyncmode_in txsyncout_out txsyncout_out txuserrdy_in txuserrdy_in txusrclk2_in txusrclk2_in txusrclk_in txusrclk_in false xilinx_elaboratesubcores Elaborate Sub-Cores :vivado.xilinx.com:elaborate.subcores xilinx_elaboratesubcores_view_fileset outputProductCRC 9:c92835d0 pci_exp_txn out 7 0 std_logic_vector xilinx_elaboratesubcores true pci_exp_txp out 7 0 std_logic_vector xilinx_elaboratesubcores true pci_exp_rxn in 7 0 std_logic_vector xilinx_elaboratesubcores 0 true pci_exp_rxp in 7 0 std_logic_vector xilinx_elaboratesubcores 0 true user_clk out std_logic xilinx_elaboratesubcores user_reset out std_logic xilinx_elaboratesubcores user_lnk_up out std_logic xilinx_elaboratesubcores s_axis_rq_tdata in 255 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_rq_tkeep in 7 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_rq_tlast in std_logic xilinx_elaboratesubcores 0 s_axis_rq_tready out 3 0 std_logic_vector xilinx_elaboratesubcores s_axis_rq_tuser in 61 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_rq_tvalid in std_logic xilinx_elaboratesubcores 0 m_axis_rc_tdata out 255 0 std_logic_vector xilinx_elaboratesubcores m_axis_rc_tkeep out 7 0 std_logic_vector xilinx_elaboratesubcores m_axis_rc_tlast out std_logic xilinx_elaboratesubcores m_axis_rc_tready in std_logic xilinx_elaboratesubcores 0 m_axis_rc_tuser out 74 0 std_logic_vector xilinx_elaboratesubcores m_axis_rc_tvalid out std_logic xilinx_elaboratesubcores m_axis_cq_tdata out 255 0 std_logic_vector xilinx_elaboratesubcores m_axis_cq_tkeep out 7 0 std_logic_vector xilinx_elaboratesubcores m_axis_cq_tlast out std_logic xilinx_elaboratesubcores m_axis_cq_tready in std_logic xilinx_elaboratesubcores 0 m_axis_cq_tuser out 87 0 std_logic_vector xilinx_elaboratesubcores m_axis_cq_tvalid out std_logic xilinx_elaboratesubcores s_axis_cc_tdata in 255 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_cc_tkeep in 7 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_cc_tlast in std_logic xilinx_elaboratesubcores 0 s_axis_cc_tready out 3 0 std_logic_vector xilinx_elaboratesubcores s_axis_cc_tuser in 32 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_cc_tvalid in std_logic xilinx_elaboratesubcores 0 cxs0_active_req_tx in std_logic xilinx_elaboratesubcores 0 false cxs0_active_ack_tx out std_logic xilinx_elaboratesubcores false cxs0_deact_hint_tx out std_logic xilinx_elaboratesubcores false cxs0_valid_tx in std_logic xilinx_elaboratesubcores 0 false cxs0_crdgnt_tx out std_logic xilinx_elaboratesubcores false cxs0_crdrtn_tx in std_logic xilinx_elaboratesubcores 0 false cxs0_cntl_tx in 13 0 std_logic_vector xilinx_elaboratesubcores 0 false cxs0_data_tx in 255 0 std_logic_vector xilinx_elaboratesubcores 0 false cxs0_valid_chk_tx in std_logic xilinx_elaboratesubcores 0 false cxs0_crdgnt_chk_tx out std_logic xilinx_elaboratesubcores false cxs0_crdrtn_chk_tx in std_logic xilinx_elaboratesubcores 0 false cxs0_cntl_chk_tx in std_logic xilinx_elaboratesubcores 0 false cxs0_data_chk_tx in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false cxs0_active_req_rx out std_logic xilinx_elaboratesubcores false cxs0_active_ack_rx in std_logic xilinx_elaboratesubcores 0 false cxs0_deact_hint_rx in std_logic xilinx_elaboratesubcores 0 false cxs0_valid_rx out std_logic xilinx_elaboratesubcores false cxs0_crdgnt_rx in std_logic xilinx_elaboratesubcores 0 false cxs0_crdrtn_rx out std_logic xilinx_elaboratesubcores false cxs0_cntl_rx out 13 0 std_logic_vector xilinx_elaboratesubcores false cxs0_data_rx out 255 0 std_logic_vector xilinx_elaboratesubcores false cxs0_valid_chk_rx out std_logic xilinx_elaboratesubcores false cxs0_crdgnt_chk_rx in std_logic xilinx_elaboratesubcores 0 false cxs0_crdrtn_chk_rx out std_logic xilinx_elaboratesubcores false cxs0_cntl_chk_rx out std_logic xilinx_elaboratesubcores false cxs0_data_chk_rx out 31 0 std_logic xilinx_elaboratesubcores false ccix_rx_credit_av out 7 0 std_logic_vector xilinx_elaboratesubcores false cfg_vc1_enable out std_logic xilinx_elaboratesubcores false cfg_vc1_negotiation_pending out std_logic xilinx_elaboratesubcores false cfg_fc_vc_sel in std_logic xilinx_elaboratesubcores 0 false ccix_optimized_tlp_tx_and_rx_enable out std_logic xilinx_elaboratesubcores false ccix_optimized_tlp_tx_and_rx_enable_rp in std_logic xilinx_elaboratesubcores 0 false s_aclk in std_logic xilinx_elaboratesubcores 0 false s_aresetn in std_logic xilinx_elaboratesubcores 0 false s_axi_araddr in 13 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_arburst in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_arcache in 3 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_arid in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_arlen in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_arlock in std_logic xilinx_elaboratesubcores 0 false s_axi_arprot in 2 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_arqos in 3 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_arready out std_logic xilinx_elaboratesubcores false s_axi_arsize in 2 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_aruser in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_arvalid in std_logic xilinx_elaboratesubcores 0 false s_axi_awaddr in 13 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_awburst in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_awcache in 3 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_awid in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_awlen in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_awlock in std_logic xilinx_elaboratesubcores 0 false s_axi_awprot in 2 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_awqos in 3 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_awready out std_logic xilinx_elaboratesubcores false s_axi_awsize in 2 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_awuser in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_awvalid in std_logic xilinx_elaboratesubcores 0 false s_axi_bid out 15 0 std_logic_vector xilinx_elaboratesubcores false s_axi_bready in std_logic xilinx_elaboratesubcores 0 false s_axi_bresp out 1 0 std_logic_vector xilinx_elaboratesubcores false s_axi_bvalid out std_logic xilinx_elaboratesubcores false s_axi_rdata out 31 0 std_logic_vector xilinx_elaboratesubcores false s_axi_rid out 15 0 std_logic_vector xilinx_elaboratesubcores false s_axi_rlast out std_logic xilinx_elaboratesubcores false s_axi_rready in std_logic xilinx_elaboratesubcores 0 false s_axi_rresp out 1 0 std_logic_vector xilinx_elaboratesubcores false s_axi_rvalid out std_logic xilinx_elaboratesubcores false s_axi_wdata in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_wlast in std_logic xilinx_elaboratesubcores 0 false s_axi_wready out std_logic xilinx_elaboratesubcores false s_axi_wstrb in 3 0 std_logic_vector xilinx_elaboratesubcores 0 false s_axi_wvalid in std_logic xilinx_elaboratesubcores 0 false pcie_rq_seq_num0 out 5 0 std_logic_vector xilinx_elaboratesubcores true rd_interrupt out std_logic xilinx_elaboratesubcores false wr_interrupt out std_logic xilinx_elaboratesubcores false pcie_rq_seq_num_vld0 out std_logic xilinx_elaboratesubcores true pcie_rq_seq_num1 out 5 0 std_logic_vector xilinx_elaboratesubcores true pcie_rq_seq_num_vld1 out std_logic xilinx_elaboratesubcores true pcie_rq_tag0 out 7 0 std_logic_vector xilinx_elaboratesubcores true pcie_rq_tag1 out 7 0 std_logic_vector xilinx_elaboratesubcores true pcie_rq_tag_av out 3 0 std_logic_vector xilinx_elaboratesubcores true pcie_rq_tag_vld0 out std_logic xilinx_elaboratesubcores true pcie_rq_tag_vld1 out std_logic xilinx_elaboratesubcores true pcie_tfc_nph_av out 3 0 std_logic_vector xilinx_elaboratesubcores true pcie_tfc_npd_av out 3 0 std_logic_vector xilinx_elaboratesubcores true pcie_cq_np_req in 1 0 std_logic_vector xilinx_elaboratesubcores 1 true pcie_cq_np_req_count out 5 0 std_logic_vector xilinx_elaboratesubcores true cfg_phy_link_down out std_logic xilinx_elaboratesubcores true cfg_phy_link_status out 1 0 std_logic_vector xilinx_elaboratesubcores true cfg_negotiated_width out 2 0 std_logic_vector xilinx_elaboratesubcores true cfg_current_speed out 1 0 std_logic_vector xilinx_elaboratesubcores true cfg_max_payload out 1 0 std_logic_vector xilinx_elaboratesubcores true cfg_max_read_req out 2 0 std_logic_vector xilinx_elaboratesubcores true cfg_function_status out 15 0 std_logic_vector xilinx_elaboratesubcores true cfg_function_power_state out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_vf_status out 503 0 std_logic_vector xilinx_elaboratesubcores true cfg_vf_power_state out 755 0 std_logic_vector xilinx_elaboratesubcores true cfg_link_power_state out 1 0 std_logic_vector xilinx_elaboratesubcores true cfg_mgmt_addr in 9 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_mgmt_function_number in 7 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_mgmt_write in std_logic xilinx_elaboratesubcores 0 true cfg_mgmt_write_data in 31 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_mgmt_byte_enable in 3 0 std_logic_vector xilinx_elaboratesubcores 0 cfg_mgmt_read in std_logic xilinx_elaboratesubcores 0 true cfg_mgmt_read_data out 31 0 std_logic_vector xilinx_elaboratesubcores true cfg_mgmt_read_write_done out std_logic xilinx_elaboratesubcores true cfg_mgmt_debug_access in std_logic xilinx_elaboratesubcores 0 true cfg_err_cor_out out std_logic xilinx_elaboratesubcores true cfg_err_nonfatal_out out std_logic xilinx_elaboratesubcores true cfg_err_fatal_out out std_logic xilinx_elaboratesubcores true cfg_local_error_valid out std_logic xilinx_elaboratesubcores true cfg_local_error_out out 4 0 std_logic_vector xilinx_elaboratesubcores true cfg_ltssm_state out 5 0 std_logic_vector xilinx_elaboratesubcores true cfg_rx_pm_state out 1 0 std_logic_vector xilinx_elaboratesubcores true cfg_tx_pm_state out 1 0 std_logic_vector xilinx_elaboratesubcores true cfg_rcb_status out 3 0 std_logic_vector xilinx_elaboratesubcores true cfg_obff_enable out 1 0 std_logic_vector xilinx_elaboratesubcores true cfg_pl_status_change out std_logic xilinx_elaboratesubcores true cfg_tph_requester_enable out 3 0 std_logic_vector xilinx_elaboratesubcores true cfg_tph_st_mode out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_vf_tph_requester_enable out 251 0 std_logic_vector xilinx_elaboratesubcores true cfg_vf_tph_st_mode out 755 0 std_logic_vector xilinx_elaboratesubcores true cfg_msg_received out std_logic xilinx_elaboratesubcores true cfg_msg_received_data out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_msg_received_type out 4 0 std_logic_vector xilinx_elaboratesubcores true cfg_msg_transmit in std_logic xilinx_elaboratesubcores 0 true cfg_msg_transmit_type in 2 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_msg_transmit_data in 31 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_msg_transmit_done out std_logic xilinx_elaboratesubcores true cfg_fc_ph out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_pd out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_nph out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_npd out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_cplh out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_cpld out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_sel in 2 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_dsn in 63 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_bus_number out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_power_state_change_ack in std_logic xilinx_elaboratesubcores 0 true cfg_power_state_change_interrupt out std_logic xilinx_elaboratesubcores true cfg_err_cor_in in std_logic xilinx_elaboratesubcores 0 true cfg_err_uncor_in in std_logic xilinx_elaboratesubcores 0 true cfg_flr_in_process out 3 0 std_logic_vector xilinx_elaboratesubcores true cfg_flr_done in 3 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_vf_flr_in_process out 251 0 std_logic_vector xilinx_elaboratesubcores true cfg_vf_flr_func_num in 7 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_vf_flr_done in 0 0 std_logic xilinx_elaboratesubcores 0 true cfg_link_training_enable in std_logic xilinx_elaboratesubcores 1 true cfg_ext_read_received out std_logic xilinx_elaboratesubcores false cfg_ext_write_received out std_logic xilinx_elaboratesubcores false cfg_ext_register_number out 9 0 std_logic_vector xilinx_elaboratesubcores false cfg_ext_function_number out 7 0 std_logic_vector xilinx_elaboratesubcores false cfg_ext_write_data out 31 0 std_logic_vector xilinx_elaboratesubcores false cfg_ext_write_byte_enable out 3 0 std_logic_vector xilinx_elaboratesubcores false cfg_ext_read_data in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false cfg_ext_read_data_valid in std_logic xilinx_elaboratesubcores 0 false rbar_bar_size out 6 0 std_logic_vector xilinx_elaboratesubcores false rbar_function_number out 8 0 std_logic_vector xilinx_elaboratesubcores false rbar_write_enable_bar0 out std_logic xilinx_elaboratesubcores false rbar_write_enable_bar1 out std_logic xilinx_elaboratesubcores false rbar_write_enable_bar2 out std_logic xilinx_elaboratesubcores false rbar_write_enable_bar3 out std_logic xilinx_elaboratesubcores false rbar_write_enable_bar4 out std_logic xilinx_elaboratesubcores false rbar_write_enable_bar5 out std_logic xilinx_elaboratesubcores false cfg_interrupt_int in 3 0 std_logic_vector xilinx_elaboratesubcores 0 cfg_interrupt_pending in 3 0 std_logic_vector xilinx_elaboratesubcores 0 cfg_interrupt_sent out std_logic xilinx_elaboratesubcores cfg_interrupt_msi_enable out 3 0 std_logic_vector xilinx_elaboratesubcores true cfg_interrupt_msi_mmenable out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_interrupt_msi_mask_update out std_logic xilinx_elaboratesubcores true cfg_interrupt_msi_data out 31 0 std_logic_vector xilinx_elaboratesubcores true cfg_interrupt_msi_select in 1 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_int in 31 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_pending_status in 31 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_pending_status_data_enable in std_logic xilinx_elaboratesubcores 0 true cfg_interrupt_msi_pending_status_function_num in 1 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_sent out std_logic xilinx_elaboratesubcores true cfg_interrupt_msi_fail out std_logic xilinx_elaboratesubcores true cfg_interrupt_msi_attr in 2 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_tph_present in std_logic xilinx_elaboratesubcores 0 true cfg_interrupt_msi_tph_type in 1 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_tph_st_tag in 7 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_function_number in 7 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msix_enable out 3 0 std_logic_vector xilinx_elaboratesubcores false cfg_interrupt_msix_mask out 3 0 std_logic_vector xilinx_elaboratesubcores false cfg_interrupt_msix_vf_enable out 251 0 std_logic_vector xilinx_elaboratesubcores false cfg_interrupt_msix_vf_mask out 251 0 std_logic_vector xilinx_elaboratesubcores false cfg_pm_aspm_l1_entry_reject in std_logic xilinx_elaboratesubcores 0 true cfg_pm_aspm_tx_l0s_entry_disable in std_logic xilinx_elaboratesubcores 0 true cfg_interrupt_msix_data in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false cfg_interrupt_msix_address in 63 0 std_logic_vector xilinx_elaboratesubcores 0 false cfg_interrupt_msix_int in std_logic xilinx_elaboratesubcores 0 false cfg_interrupt_msix_vec_pending in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false cfg_interrupt_msix_vec_pending_status out 0 0 std_logic xilinx_elaboratesubcores false cfg_hot_reset_out out std_logic xilinx_elaboratesubcores true cfg_config_space_enable in std_logic xilinx_elaboratesubcores 1 true cfg_req_pm_transition_l23_ready in std_logic xilinx_elaboratesubcores 0 true cfg_hot_reset_in in std_logic xilinx_elaboratesubcores 0 true cfg_ds_port_number in 7 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_ds_bus_number in 7 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_ds_device_number in 4 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_ds_function_number in 2 0 std_logic_vector xilinx_elaboratesubcores 0 false cfg_subsys_vend_id in 15 0 std_logic_vector xilinx_elaboratesubcores 0x10EE false cfg_dev_id_pf0 in 15 0 std_logic_vector xilinx_elaboratesubcores 0x9038 false cfg_dev_id_pf1 in 15 0 std_logic_vector xilinx_elaboratesubcores 0x9011 false cfg_dev_id_pf2 in 15 0 std_logic_vector xilinx_elaboratesubcores 0x9438 false cfg_dev_id_pf3 in 15 0 std_logic_vector xilinx_elaboratesubcores 0x9638 false cfg_vend_id in 15 0 std_logic_vector xilinx_elaboratesubcores 0x10EE false cfg_rev_id_pf0 in 7 0 std_logic_vector xilinx_elaboratesubcores 0x00 false cfg_rev_id_pf1 in 7 0 std_logic_vector xilinx_elaboratesubcores 0x00 false cfg_rev_id_pf2 in 7 0 std_logic_vector xilinx_elaboratesubcores 0x00 false cfg_rev_id_pf3 in 7 0 std_logic_vector xilinx_elaboratesubcores 0x00 false cfg_subsys_id_pf0 in 15 0 std_logic_vector xilinx_elaboratesubcores 0x0007 false cfg_subsys_id_pf1 in 15 0 std_logic_vector xilinx_elaboratesubcores 0x0007 false cfg_subsys_id_pf2 in 15 0 std_logic_vector xilinx_elaboratesubcores 0x0007 false cfg_subsys_id_pf3 in 15 0 std_logic_vector xilinx_elaboratesubcores 0x0007 false sys_clk in std_logic xilinx_elaboratesubcores 0 sys_clk_ce_out out std_logic xilinx_elaboratesubcores false sys_clk_gt in std_logic xilinx_elaboratesubcores 0 sys_reset in std_logic xilinx_elaboratesubcores 0 conf_req_type in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false conf_req_reg_num in 3 0 std_logic_vector xilinx_elaboratesubcores 0 false conf_req_data in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false conf_req_valid in std_logic xilinx_elaboratesubcores 0 false conf_req_ready out std_logic xilinx_elaboratesubcores false conf_resp_rdata out 31 0 std_logic_vector xilinx_elaboratesubcores false conf_resp_valid out std_logic xilinx_elaboratesubcores false pl_gen2_upstream_prefer_deemph in std_logic xilinx_elaboratesubcores 0 false pl_eq_in_progress out std_logic xilinx_elaboratesubcores false pl_redo_eq in std_logic xilinx_elaboratesubcores 0 false pl_redo_eq_speed in std_logic xilinx_elaboratesubcores 0 false pl_eq_mismatch out std_logic xilinx_elaboratesubcores false pl_redo_eq_pending out std_logic xilinx_elaboratesubcores false pl_eq_phase out 1 0 std_logic_vector xilinx_elaboratesubcores false ext_qpllxrefclk out 1 0 std_logic_vector xilinx_elaboratesubcores false ext_qpllxrcalenb out std_logic xilinx_elaboratesubcores false ext_qpllxrate out 5 0 std_logic_vector xilinx_elaboratesubcores false ext_qpll0pd out 1 0 std_logic_vector xilinx_elaboratesubcores false ext_qpll0reset out 1 0 std_logic_vector xilinx_elaboratesubcores false ext_qpll0lock_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_qpll0outclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_qpll0outrefclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false int_qpll0lock_out out 1 0 std_logic_vector xilinx_elaboratesubcores false int_qpll0outrefclk_out out 1 0 std_logic_vector xilinx_elaboratesubcores false int_qpll0outclk_out out 1 0 std_logic_vector xilinx_elaboratesubcores false ext_qpll1pd out 1 0 std_logic_vector xilinx_elaboratesubcores false ext_qpll1reset out 1 0 std_logic_vector xilinx_elaboratesubcores false ext_qpll1lock_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_qpll1outclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_qpll1outrefclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false int_qpll1lock_out out 1 0 std_logic_vector xilinx_elaboratesubcores false int_qpll1outrefclk_out out 1 0 std_logic_vector xilinx_elaboratesubcores false int_qpll1outclk_out out 1 0 std_logic_vector xilinx_elaboratesubcores false common_commands_in in 25 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_0_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_1_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_2_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_3_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_4_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_5_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_6_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_7_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_8_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_9_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_10_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_11_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_12_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_13_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_14_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_15_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false common_commands_out out 25 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_0_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_1_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_2_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_3_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_4_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_5_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_6_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_7_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_8_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_9_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_10_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_11_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_12_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_13_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_14_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_15_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false gt_pcieuserratedone in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_loopback in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_txprbsforceerr in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_txinhibit in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_txprbssel in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_rxprbssel in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_rxprbscntreset in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_txelecidle out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxpmaresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txphaligndone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txphinitdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txdlysresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxphaligndone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxdlysresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxsyncdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_eyescandataerror out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxprbserr out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_dmonfiforeset in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_dmonitorclk in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_dmonitorout out 127 0 std_logic_vector xilinx_elaboratesubcores false gt_rxcommadet out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_phystatus out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxvalid out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxcdrlock out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_pcierateidle out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_pcieuserratestart out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_gtpowergood out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_cplllock out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxoutclk out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxrecclkout out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_qpll1lock out 1 0 std_logic_vector xilinx_elaboratesubcores false gt_qpll0lock out 1 0 std_logic_vector xilinx_elaboratesubcores false gt_rxstatus out 23 0 std_logic_vector xilinx_elaboratesubcores false gt_rxbufstatus out 23 0 std_logic_vector xilinx_elaboratesubcores false gt_bufgtdiv out 8 0 std_logic_vector xilinx_elaboratesubcores false phy_txeq_ctrl out 15 0 std_logic_vector xilinx_elaboratesubcores false phy_txeq_preset out 31 0 std_logic_vector xilinx_elaboratesubcores false phy_rst_fsm out 3 0 std_logic_vector xilinx_elaboratesubcores false phy_txeq_fsm out 23 0 std_logic_vector xilinx_elaboratesubcores false phy_rxeq_fsm out 23 0 std_logic_vector xilinx_elaboratesubcores false phy_rst_idle out std_logic xilinx_elaboratesubcores false phy_rrst_n out std_logic xilinx_elaboratesubcores false phy_prst_n out std_logic xilinx_elaboratesubcores false ext_ch_gt_drpclk out std_logic xilinx_elaboratesubcores false gt_gen34_eios_det out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txoutclk out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txoutclkfabric out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxoutclkfabric out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txoutclkpcs out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxoutclkpcs out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txpmareset in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_rxpmareset in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_txpcsreset in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_rxpcsreset in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_rxbufreset in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_rxcdrreset in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_rxdfelpmreset in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_txprogdivresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txpmaresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txsyncdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxprbslocked out 7 0 std_logic_vector xilinx_elaboratesubcores false ext_ch_gt_drpaddr in 79 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_ch_gt_drpen in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_ch_gt_drpdi in 127 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_ch_gt_drpwe in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_ch_gt_drpdo out 127 0 std_logic_vector xilinx_elaboratesubcores false ext_ch_gt_drprdy out 7 0 std_logic_vector xilinx_elaboratesubcores false drp_rdy out std_logic xilinx_elaboratesubcores false drp_do out 15 0 std_logic_vector xilinx_elaboratesubcores false drp_clk in std_logic xilinx_elaboratesubcores 1 false drp_en in std_logic xilinx_elaboratesubcores 0 false drp_we in std_logic xilinx_elaboratesubcores 0 false drp_addr in 9 0 std_logic_vector xilinx_elaboratesubcores 0 false drp_di in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false gtrefclk01_in out 1 0 std_logic_vector xilinx_elaboratesubcores false gtrefclk00_in out 1 0 std_logic_vector xilinx_elaboratesubcores false pcierateqpll0_in out 5 0 std_logic_vector xilinx_elaboratesubcores false pcierateqpll1_in out 5 0 std_logic_vector xilinx_elaboratesubcores false qpll0pd_in out 1 0 std_logic_vector xilinx_elaboratesubcores false qpll0reset_in out 1 0 std_logic_vector xilinx_elaboratesubcores false qpll1pd_in out 1 0 std_logic_vector xilinx_elaboratesubcores false qpll1reset_in out 1 0 std_logic_vector xilinx_elaboratesubcores false rcalenb_in out 1 0 std_logic_vector xilinx_elaboratesubcores false qpll0lock_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false qpll0outclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false qpll0outrefclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false qpll1lock_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false qpll1outclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false qpll1outrefclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false qpll0freqlock_in out 7 0 std_logic_vector xilinx_elaboratesubcores false qpll1freqlock_in out 7 0 std_logic_vector xilinx_elaboratesubcores false pcierateqpllpd_out in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false pcierateqpllreset_out in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false gtwiz_reset_rx_done_in out 0 0 std_logic xilinx_elaboratesubcores false gtwiz_reset_tx_done_in out 0 0 std_logic xilinx_elaboratesubcores false gtwiz_userclk_rx_active_in out 0 0 std_logic xilinx_elaboratesubcores false gtwiz_userclk_tx_active_in out 0 0 std_logic xilinx_elaboratesubcores false loopback_in out 23 0 std_logic_vector xilinx_elaboratesubcores false rxpd_in out 15 0 std_logic_vector xilinx_elaboratesubcores false rxprbssel_in out 31 0 std_logic_vector xilinx_elaboratesubcores false rxrate_in out 23 0 std_logic_vector xilinx_elaboratesubcores false txctrl0_in out 127 0 std_logic_vector xilinx_elaboratesubcores false txctrl1_in out 127 0 std_logic_vector xilinx_elaboratesubcores false txctrl2_in out 63 0 std_logic_vector xilinx_elaboratesubcores false txdata_in out 1023 0 std_logic_vector xilinx_elaboratesubcores false txdeemph_in out 15 0 std_logic_vector xilinx_elaboratesubcores false txdiffctrl_in out 39 0 std_logic_vector xilinx_elaboratesubcores false txprbssel_in out 31 0 std_logic_vector xilinx_elaboratesubcores false txprecursor_in out 39 0 std_logic_vector xilinx_elaboratesubcores false txrate_in out 23 0 std_logic_vector xilinx_elaboratesubcores false txmaincursor_in out 55 0 std_logic_vector xilinx_elaboratesubcores false txmargin_in out 23 0 std_logic_vector xilinx_elaboratesubcores false txoutclksel_in out 23 0 std_logic_vector xilinx_elaboratesubcores false txpd_in out 15 0 std_logic_vector xilinx_elaboratesubcores false txpostcursor_in out 39 0 std_logic_vector xilinx_elaboratesubcores false cpllfreqlock_in out 7 0 std_logic_vector xilinx_elaboratesubcores false cpllpd_in out 7 0 std_logic_vector xilinx_elaboratesubcores false cpllreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false dmonfiforeset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false dmonitorclk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false eyescanreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false gtrefclk0_in out 7 0 std_logic_vector xilinx_elaboratesubcores false gtrxreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txpisopd_in out 7 0 std_logic_vector xilinx_elaboratesubcores false gttxreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false pcieeqrxeqadaptdone_in out 7 0 std_logic_vector xilinx_elaboratesubcores false pcierstidle_in out 7 0 std_logic_vector xilinx_elaboratesubcores false pciersttxsyncstart_in out 7 0 std_logic_vector xilinx_elaboratesubcores false pcieuserratedone_in out 7 0 std_logic_vector xilinx_elaboratesubcores false resetovrd_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rx8b10ben_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxbufreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxcdrfreqreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxcdrhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxcdrreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxcommadeten_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfeagchold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfecfokhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfekhhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfelfhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfelpmreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap10hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap11hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap12hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap13hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap14hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap15hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap2hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap3hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap4hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap5hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap6hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap7hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap8hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap9hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfeuthold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfevphold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxlpmen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxlpmgchold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxlpmhfhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxlpmlfhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxlpmoshold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxmcommaalignen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxoshold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxpcommaalignen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxpcsreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxpmareset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxpolarity_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxprbscntreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxprogdivreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxslide_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxtermination_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxuserrdy_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxusrclk2_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxusrclk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false tx8b10ben_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdetectrx_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlybypass_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlyen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlyhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlyovrden_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlysreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlyupdown_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txelecidle_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txpcsreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphalign_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphalignen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphdlypd_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphdlyreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphdlytstclk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphinit_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphovrden_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxratemode_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txpmareset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txprbsforceerr_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txprogdivreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txpdelecidlemode_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txswing_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txsyncallin_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txsyncin_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txsyncmode_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txuserrdy_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txusrclk2_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txusrclk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxclkcorcnt_out in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false bufgtcemask_out in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false bufgtrstmask_out in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false rxbufstatus_out in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false rxstatus_out in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false rxctrl2_out in 63 0 std_logic_vector xilinx_elaboratesubcores 0 false rxctrl3_out in 63 0 std_logic_vector xilinx_elaboratesubcores 0 false bufgtdiv_out in 71 0 std_logic_vector xilinx_elaboratesubcores 0 false dmonitorout_out in 127 0 std_logic_vector xilinx_elaboratesubcores 0 false rxctrl0_out in 127 0 std_logic_vector xilinx_elaboratesubcores 0 false rxctrl1_out in 127 0 std_logic_vector xilinx_elaboratesubcores 0 false rxdata_out in 1023 0 std_logic_vector xilinx_elaboratesubcores 0 false bufgtreset_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false bufgtce_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false cplllock_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gtpowergood_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pcierategen3_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pcierateidle_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pciesynctxsyncdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pcieusergen3rdy_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pcieuserphystatusrst_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pcieuserratestart_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false phystatus_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxbyteisaligned_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxbyterealign_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxcdrlock_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxcommadet_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxphaligndone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxpmaresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxdlysresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxelecidle_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxoutclk_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxoutclkfabric_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxoutclkpcs_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxprbserr_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxprbslocked_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxratedone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxrecclkout_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxsyncdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txdlysresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxvalid_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txoutclk_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txoutclkfabric_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txoutclkpcs_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txphaligndone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txphinitdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txpmaresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txprgdivresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txsyncdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txsyncout_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_phy_clk_bufg_gt_ce out std_logic xilinx_elaboratesubcores false ext_phy_clk_bufg_gt_reset out std_logic xilinx_elaboratesubcores false ext_phy_clk_rst_idle out std_logic xilinx_elaboratesubcores false ext_phy_clk_txoutclk out std_logic xilinx_elaboratesubcores false ext_phy_clk_bufgtcemask out std_logic xilinx_elaboratesubcores false ext_phy_clk_gt_bufgtrstmask out std_logic xilinx_elaboratesubcores false ext_phy_clk_bufgtdiv out 8 0 std_logic_vector xilinx_elaboratesubcores false ext_phy_clk_pclk2_gt in std_logic xilinx_elaboratesubcores 0 false ext_phy_clk_int_clock in std_logic xilinx_elaboratesubcores 0 false ext_phy_clk_pclk in std_logic xilinx_elaboratesubcores 0 false ext_phy_clk_phy_pclk2 in std_logic xilinx_elaboratesubcores 0 false ext_phy_clk_phy_coreclk in std_logic xilinx_elaboratesubcores 0 false ext_phy_clk_phy_userclk in std_logic xilinx_elaboratesubcores 0 false ext_phy_clk_phy_mcapclk in std_logic xilinx_elaboratesubcores 0 false drpaddr_in out 79 0 std_logic_vector xilinx_elaboratesubcores false drpen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false drpdi_in out 127 0 std_logic_vector xilinx_elaboratesubcores false drpwe_in out 7 0 std_logic_vector xilinx_elaboratesubcores false drprst_in out 7 0 std_logic_vector xilinx_elaboratesubcores false drpdo_out in 127 0 std_logic_vector xilinx_elaboratesubcores 0 false drprdy_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false drpclk_in out std_logic xilinx_elaboratesubcores false cap_req out std_logic xilinx_elaboratesubcores false cap_gnt in std_logic xilinx_elaboratesubcores 1 false cap_rel in std_logic xilinx_elaboratesubcores 0 false mcap_design_switch out std_logic xilinx_elaboratesubcores false free_run_clock in std_logic xilinx_elaboratesubcores 0 false gt_drp_clk out std_logic xilinx_elaboratesubcores false mcap_clk out std_logic xilinx_elaboratesubcores false core_clk out std_logic xilinx_elaboratesubcores false phy_rdy_out out std_logic xilinx_elaboratesubcores ats_pri_en out std_logic xilinx_elaboratesubcores false pipe_debug_ctl_in_tx0 in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_debug_ctl_in_tx1 in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_debug_ctl_in_rx0 in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_debug_ctl_in_rx1 in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_debug_ltssm_rec_spd_1 in std_logic xilinx_elaboratesubcores 0 false pipe_debug_ltssm_pol_act in std_logic xilinx_elaboratesubcores 0 false pipe_debug_ctl_vec4 in 3 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_debug_mux_ctl in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_debug_debug_out_128_0 out 127 0 std_logic_vector xilinx_elaboratesubcores false pipe_debug_debug_out_ext_16_0 out 15 0 std_logic_vector xilinx_elaboratesubcores false pipe_debug_debug_out_128_1 out 127 0 std_logic_vector xilinx_elaboratesubcores false pipe_debug_debug_out_ext_16_1 out 15 0 std_logic_vector xilinx_elaboratesubcores false pipe_debug_debug_out_128_2 out 127 0 std_logic_vector xilinx_elaboratesubcores false pipe_debug_debug_out_ext_16_2 out 15 0 std_logic_vector xilinx_elaboratesubcores false pipe_debug_debug_out_128_3 out 127 0 std_logic_vector xilinx_elaboratesubcores false pipe_debug_debug_out_ext_16_3 out 15 0 std_logic_vector xilinx_elaboratesubcores false pipe_debug_inject_tx_status out 7 0 std_logic_vector xilinx_elaboratesubcores false pipe_debug_inject_rx_status out 7 0 std_logic_vector xilinx_elaboratesubcores false PL_LINK_CAP_MAX_LINK_SPEED Pl Link Cap Max Link Speed 4 PL_LINK_CAP_MAX_LINK_WIDTH Pl Link Cap Max Link Width 8 CRM_USER_CLK_FREQ User Clk Freq 2 CRM_CORE_CLK_FREQ_500 Core Clk Freq TRUE PLL_TYPE PLL Type 2 PF0_LINK_CAP_ASPM_SUPPORT ASPM Support 0 AXI4_DATA_WIDTH C Data Width 256 PHY_REFCLK_FREQ Ref Clk Freq 0 AXI4_TKEEP_WIDTH Keep Width 8 AXI4_RQ_TUSER_WIDTH RQ User Width 62 AXI4_CQ_TUSER_WIDTH CQ User Width 88 AXI4_RC_TUSER_WIDTH RC User Width 75 AXI4_CC_TUSER_WIDTH CC User Width 33 AXIS_CCIX_RX_TDATA_WIDTH CCIX Rx Data Width 256 AXIS_CCIX_RX_TUSER_WIDTH CCIX Rx User Width 47 AXIS_CCIX_TX_TDATA_WIDTH CCIX Tx Data Width 256 AXIS_CCIX_TX_TUSER_WIDTH CCIX Tx User Width 47 ARI_CAP_ENABLE Ari Cap Enable FALSE PF0_ARI_CAP_NEXT_FUNC Pf0 ARI Cap Next Func 0x00 PF1_ARI_CAP_NEXT_FUNC Pf1 ARI Cap Next Func 0x00 PF2_ARI_CAP_NEXT_FUNC Pf2 ARI Cap Next Func 0x00 PF3_ARI_CAP_NEXT_FUNC Pf3 ARI Cap Next Func 0x00 AXISTEN_IF_CC_ALIGNMENT_MODE Axisten If Cc Alignment Mode 0x1 AXISTEN_IF_CQ_ALIGNMENT_MODE Axisten If Cq Alignment Mode 0x1 AXISTEN_IF_RC_ALIGNMENT_MODE Axisten If Rc Alignment Mode 0x0 AXISTEN_IF_RQ_ALIGNMENT_MODE Axisten If Rq Alignment Mode 0x0 AXISTEN_IF_EXT_512_CQ_STRADDLE Axisten If CQ Straddle FALSE AXISTEN_IF_EXT_512_CC_STRADDLE Axisten If CC Straddle FALSE AXISTEN_IF_EXT_512_RQ_STRADDLE Axisten If RQ Straddle FALSE AXISTEN_IF_EXT_512_RC_STRADDLE Axisten If RC Straddle FALSE AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE Axisten If 512 4TLP/2TLP Rc Straddle FALSE AXISTEN_IF_RC_STRADDLE Axisten If Rc Straddle TRUE PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE Pf0 Aer Cap Ecrc Gen and Check Capable FALSE PF0_AER_CAP_NEXTPTR Pf0 Aer Cap Nextptr 0x1C0 PF0_PCIE_CAP_NEXTPTR pcie Nextptr 0x000 PF1_PCIE_CAP_NEXTPTR pcie Nextptr 0x000 PF2_PCIE_CAP_NEXTPTR pcie Nextptr 0x000 PF3_PCIE_CAP_NEXTPTR pcie Nextptr 0x000 VF0_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR vf0 ext space Nextptr 0x000 VF1_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR vf1/ ext space Nextptr 0x000 VF2_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR vf2 ext space Nextptr 0x000 VF3_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR vf3 ext space Nextptr 0x000 PF0_ARI_CAP_NEXTPTR Pf0 Ari Cap Nextptr 0x1C0 PF0_BAR0_APERTURE_SIZE Pf0 Bar0 Aperture Size 0x009 PF0_BAR0_CONTROL Pf0 Bar0 Control 0x4 PF0_BAR1_APERTURE_SIZE Pf0 Bar1 Aperture Size 0x000 PF0_BAR1_CONTROL Pf0 Bar1 Control 0x0 PF0_BAR2_APERTURE_SIZE Pf0 Bar2 Aperture Size 0x000 PF0_BAR2_CONTROL Pf0 Bar2 Control 0x0 PF0_BAR3_APERTURE_SIZE Pf0 Bar3 Aperture Size 0x000 PF0_BAR3_CONTROL Pf0 Bar3 Control 0x0 PF0_BAR4_APERTURE_SIZE Pf0 Bar4 Aperture Size 0x000 PF0_BAR4_CONTROL Pf0 Bar4 Control 0x0 PF0_BAR5_APERTURE_SIZE Pf0 Bar5 Aperture Size 0x000 PF0_BAR5_CONTROL Pf0 Bar5 Control 0x0 PF0_CAPABILITY_POINTER Pf0 Capability Pointer 0x40 PF0_CLASS_CODE Pf0 Class Code 0x070001 PF0_VENDOR_ID Pf0 Vendor Id 0x10EE PF0_DEVICE_ID Pf0 Device Id 0x9038 PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 128b Cas Atomic Completer Support FALSE PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 32b Atomic Completer Support FALSE PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 64b Atomic Completer Support FALSE PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT Pf0 Dev Cap2 Tph Completer Support FALSE PF0_DEV_CAP_EXT_TAG_SUPPORTED Pf0 Dev Cap Ext Tag Supported TRUE PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE Pf0 Dev Cap Function Level Reset Capable FALSE PF0_DEV_CAP_MAX_PAYLOAD_SIZE Pf0 Dev Cap Max Payload Size 0x3 DSN_CAP_ENABLE Dsn Cap Enable FALSE PF0_VC_CAP_ENABLE Vc Cap Enable TRUE PF0_DSN_CAP_NEXTPTR Pf0 Dsn Cap Nextptr 0x1C0 PF0_EXPANSION_ROM_APERTURE_SIZE Pf0 Expansion Rom Aperture Size 0x000 PF0_EXPANSION_ROM_ENABLE Pf0 Expansion Rom Enable FALSE PF0_INTERRUPT_PIN Pf0 Interrupt Pin 0x1 PF0_LINK_STATUS_SLOT_CLOCK_CONFIG Pf0 Link Status Slot Clock Config TRUE PF0_MSIX_CAP_NEXTPTR Pf0 Msix Cap Nextptr 0x70 PF0_MSIX_CAP_PBA_BIR Pf0 Msix Cap Pba Bir 0 PF0_MSIX_CAP_PBA_OFFSET Pf0 Msix Cap Pba Offset 0x00000000 PF0_MSIX_CAP_TABLE_BIR Pf0 Msix Cap Table Bir 0 PF0_MSIX_CAP_TABLE_OFFSET Pf0 Msix Cap Table Offset 0x00000000 PF0_MSIX_CAP_TABLE_SIZE Pf0 Msix Cap Table Size 0x000 PF0_MSI_CAP_MULTIMSGCAP Pf0 Msi Cap Multimsgcap 0 PF0_MSI_CAP_NEXTPTR Pf0 Msi Cap Nextptr 0x70 PF0_PM_CAP_NEXTPTR Pf0 Pm Cap Nextptr 0x48 PF0_PM_CAP_PMESUPPORT_D0 Pf0 Pm Cap Pmesupport D0 FALSE PF0_PM_CAP_PMESUPPORT_D1 Pf0 Pm Cap Pmesupport D1 FALSE PF0_PM_CAP_PMESUPPORT_D3HOT Pf0 Pm Cap Pmesupport D3hot FALSE PF0_PM_CAP_SUPP_D1_STATE Pf0 Pm Cap Supp D1 State FALSE PF0_REVISION_ID Pf0 Revision Id 0x00 PF0_SRIOV_BAR0_APERTURE_SIZE Pf0 Sriov Bar0 Aperture Size 0x00 PF0_SRIOV_BAR0_CONTROL Pf0 Sriov Bar0 Control 0x0 PF0_SRIOV_BAR1_APERTURE_SIZE Pf0 Sriov Bar1 Aperture Size 0x00 PF0_SRIOV_BAR1_CONTROL Pf0 Sriov Bar1 Control 0x0 PF0_SRIOV_BAR2_APERTURE_SIZE Pf0 Sriov Bar2 Aperture Size 0x00 PF0_SRIOV_BAR2_CONTROL Pf0 Sriov Bar2 Control 0x0 PF0_SRIOV_BAR3_APERTURE_SIZE Pf0 Sriov Bar3 Aperture Size 0x00 PF0_SRIOV_BAR3_CONTROL Pf0 Sriov Bar3 Control 0x0 PF0_SRIOV_BAR4_APERTURE_SIZE Pf0 Sriov Bar4 Aperture Size 0x00 PF0_SRIOV_BAR4_CONTROL Pf0 Sriov Bar4 Control 0x0 PF0_SRIOV_BAR5_APERTURE_SIZE Pf0 Sriov Bar5 Aperture Size 0x00 PF0_SRIOV_BAR5_CONTROL Pf0 Sriov Bar5 Control 0x0 PF0_SRIOV_CAP_INITIAL_VF Pf0 Sriov Cap Initial Vf 0x0000 PF0_SRIOV_CAP_NEXTPTR Pf0 Sriov Cap Nextptr 0x1F0 PF0_SRIOV_CAP_TOTAL_VF Pf0 Sriov Cap Total Vf 0x0000 PF0_SRIOV_CAP_VER Pf0 Sriov Cap Ver 0x1 PF0_SRIOV_FIRST_VF_OFFSET Pf0 Sriov First Vf Offset 0x0000 PF0_SRIOV_FUNC_DEP_LINK Pf0 Sriov Func Dep Link 0x0000 PF0_SRIOV_SUPPORTED_PAGE_SIZE Pf0 Sriov Supported Page Size 0x00000553 PF0_SRIOV_VF_DEVICE_ID Pf0 Sriov Vf Device Id 0x0000 PF0_SUBSYSTEM_VENDOR_ID Pf0 Subsystem Vendor Id 0x10EE PF0_SUBSYSTEM_ID Pf0 Subsystem Id 0x0007 PF0_TPHR_CAP_ENABLE Pf0 Tphr Cap Enable FALSE PF0_TPHR_CAP_NEXTPTR Pf0 Tphr Cap Nextptr 0x000 PF0_TPHR_CAP_ST_MODE_SEL Pf0 Tphr Cap St Mode Sel 0x0 PF0_TPHR_CAP_ST_TABLE_LOC Pf0 Tphr Cap St Table Loc 0x0 PF0_TPHR_CAP_ST_TABLE_SIZE Pf0 Tphr Cap St Table Size 0x000 PF0_TPHR_CAP_VER Pf0 Tphr Cap Ver 0x1 PF1_TPHR_CAP_ST_MODE_SEL Pf1 Tphr Cap St Mode Sel 0x0 PF2_TPHR_CAP_ST_MODE_SEL Pf2 Tphr Cap St Mode Sel 0x0 PF3_TPHR_CAP_ST_MODE_SEL Pf3 Tphr Cap St Mode Sel 0x0 PF0_TPHR_CAP_DEV_SPECIFIC_MODE Pf0 Tphr Cap Dev Specific Mode TRUE PF0_TPHR_CAP_INT_VEC_MODE Pf0 Tphr Cap Int Vec Mode FALSE PF0_SECONDARY_PCIE_CAP_NEXTPTR Secondary Pcie Extended Capability Nextptr 0x1F0 MCAP_CAP_NEXTPTR MCAP Cap Nextptr 0x000 PF0_VC_CAP_NEXTPTR Pf0 Vc Cap Nextptr 0x000 SPARE_WORD1 Secondary Pcie Extended Capability Nextptr 0x00000000 PF1_AER_CAP_NEXTPTR Pf1 Aer Cap Nextptr 0x000 PF1_ARI_CAP_NEXTPTR Pf1 Ari Cap Nextptr 0x000 PF1_BAR0_APERTURE_SIZE Pf1 Bar0 Aperture Size 0x009 PF1_BAR0_CONTROL Pf1 Bar0 Control 0x4 PF1_BAR1_APERTURE_SIZE Pf1 Bar1 Aperture Size 0x000 PF1_BAR1_CONTROL Pf1 Bar1 Control 0x0 PF1_BAR2_APERTURE_SIZE Pf1 Bar2 Aperture Size 0x000 PF1_BAR2_CONTROL Pf1 Bar2 Control 0x0 PF1_BAR3_APERTURE_SIZE Pf1 Bar3 Aperture Size 0x000 PF1_BAR3_CONTROL Pf1 Bar3 Control 0x0 PF1_BAR4_APERTURE_SIZE Pf1 Bar4 Aperture Size 0x000 PF1_BAR4_CONTROL Pf1 Bar4 Control 0x0 PF1_BAR5_APERTURE_SIZE Pf1 Bar5 Aperture Size 0x000 PF1_BAR5_CONTROL Pf1 Bar5 Control 0x0 PF1_CAPABILITY_POINTER Pf1 Capability Pointer 0x40 PF1_CLASS_CODE Pf1 Class Code 0x058000 PF1_DEVICE_ID Pf1 Device Id 0x9011 PF1_DEV_CAP_MAX_PAYLOAD_SIZE Pf1 Dev Cap Max Payload Size 0x3 PF1_DSN_CAP_NEXTPTR Pf1 Dsn Cap Nextptr 0x000 PF1_EXPANSION_ROM_APERTURE_SIZE Pf1 Expansion Rom Aperture Size 0x000 PF1_EXPANSION_ROM_ENABLE Pf1 Expansion Rom Enable FALSE PF1_INTERRUPT_PIN Pf1 Interrupt Pin 0x0 PF1_MSIX_CAP_NEXTPTR Pf1 Msix Cap Nextptr 0x70 PF1_MSIX_CAP_PBA_BIR Pf1 Msix Cap Pba Bir 0 PF1_MSIX_CAP_PBA_OFFSET Pf1 Msix Cap Pba Offset 0x00000000 PF1_MSIX_CAP_TABLE_BIR Pf1 Msix Cap Table Bir 0 PF1_MSIX_CAP_TABLE_OFFSET Pf1 Msix Cap Table Offset 0x00000000 PF1_MSIX_CAP_TABLE_SIZE Pf1 Msix Cap Table Size 0x000 PF1_MSI_CAP_MULTIMSGCAP Pf1 Msi Cap Multimsgcap 0 PF1_MSI_CAP_NEXTPTR Pf1 Msi Cap Nextptr 0x70 PF1_PM_CAP_NEXTPTR Pf1 Pm Cap Nextptr 0x70 PF1_REVISION_ID Pf1 Revision Id 0x00 PF1_SRIOV_BAR0_APERTURE_SIZE Pf1 Sriov Bar0 Aperture Size 0x00 PF1_SRIOV_BAR0_CONTROL Pf1 Sriov Bar0 Control 0x0 PF1_SRIOV_BAR1_APERTURE_SIZE Pf1 Sriov Bar1 Aperture Size 0x00 PF1_SRIOV_BAR1_CONTROL Pf1 Sriov Bar1 Control 0x0 PF1_SRIOV_BAR2_APERTURE_SIZE Pf1 Sriov Bar2 Aperture Size 0x00 PF1_SRIOV_BAR2_CONTROL Pf1 Sriov Bar2 Control 0x0 PF1_SRIOV_BAR3_APERTURE_SIZE Pf1 Sriov Bar3 Aperture Size 0x00 PF1_SRIOV_BAR3_CONTROL Pf1 Sriov Bar3 Control 0x0 PF1_SRIOV_BAR4_APERTURE_SIZE Pf1 Sriov Bar4 Aperture Size 0x00 PF1_SRIOV_BAR4_CONTROL Pf1 Sriov Bar4 Control 0x0 PF1_SRIOV_BAR5_APERTURE_SIZE Pf1 Sriov Bar5 Aperture Size 0x00 PF1_SRIOV_BAR5_CONTROL Pf1 Sriov Bar5 Control 0x0 PF1_SRIOV_CAP_INITIAL_VF Pf1 Sriov Cap Initial Vf 0x0000 PF1_SRIOV_CAP_NEXTPTR Pf1 Sriov Cap Nextptr 0x000 PF1_SRIOV_CAP_TOTAL_VF Pf1 Sriov Cap Total Vf 0x0000 PF1_SRIOV_CAP_VER Pf1 Sriov Cap Ver 0x1 PF1_SRIOV_FIRST_VF_OFFSET Pf1 Sriov First Vf Offset 0x0000 PF1_SRIOV_FUNC_DEP_LINK Pf1 Sriov Func Dep Link 0x0001 PF1_SRIOV_SUPPORTED_PAGE_SIZE Pf1 Sriov Supported Page Size 0x00000553 PF1_SRIOV_VF_DEVICE_ID Pf1 Sriov Vf Device Id 0x0000 PF1_SUBSYSTEM_ID Pf1 Subsystem Id 0x0007 PF1_TPHR_CAP_NEXTPTR Pf1 Tphr Cap Nextptr 0x000 PF2_AER_CAP_NEXTPTR Pf2 Aer Cap Nextptr 0x000 PF2_ARI_CAP_NEXTPTR Pf2 Ari Cap Nextptr 0x000 PF2_BAR0_APERTURE_SIZE Pf2 Bar0 Aperture Size 0x009 PF2_BAR0_CONTROL Pf2 Bar0 Control 0x4 PF2_BAR1_APERTURE_SIZE Pf2 Bar1 Aperture Size 0x000 PF2_BAR1_CONTROL Pf2 Bar1 Control 0x0 PF2_BAR2_APERTURE_SIZE Pf2 Bar2 Aperture Size 0x000 PF2_BAR2_CONTROL Pf2 Bar2 Control 0x0 PF2_BAR3_APERTURE_SIZE Pf2 Bar3 Aperture Size 0x000 PF2_BAR3_CONTROL Pf2 Bar3 Control 0x0 PF2_BAR4_APERTURE_SIZE Pf2 Bar4 Aperture Size 0x000 PF2_BAR4_CONTROL Pf2 Bar4 Control 0x0 PF2_BAR5_APERTURE_SIZE Pf2 Bar5 Aperture Size 0x000 PF2_BAR5_CONTROL Pf2 Bar5 Control 0x0 PF2_CAPABILITY_POINTER Pf2 Capability Pointer 0x40 PF2_CLASS_CODE Pf2 Class Code 0x058000 PF2_DEVICE_ID Pf2 Device Id 0x9438 PF2_DEV_CAP_MAX_PAYLOAD_SIZE Pf2 Dev Cap Max Payload Size 0x3 PF2_DSN_CAP_NEXTPTR Pf2 Dsn Cap Nextptr 0x000 PF2_EXPANSION_ROM_APERTURE_SIZE Pf2 Expansion Rom Aperture Size 0x000 PF2_EXPANSION_ROM_ENABLE Pf2 Expansion Rom Enable FALSE PF2_INTERRUPT_PIN Pf2 Interrupt Pin 0x0 PF2_MSIX_CAP_NEXTPTR Pf2 Msix Cap Nextptr 0x70 PF2_MSIX_CAP_PBA_BIR Pf2 Msix Cap Pba Bir 0 PF2_MSIX_CAP_PBA_OFFSET Pf2 Msix Cap Pba Offset 0x00000000 PF2_MSIX_CAP_TABLE_BIR Pf2 Msix Cap Table Bir 0 PF2_MSIX_CAP_TABLE_OFFSET Pf2 Msix Cap Table Offset 0x00000000 PF2_MSIX_CAP_TABLE_SIZE Pf2 Msix Cap Table Size 0x000 PF2_MSI_CAP_MULTIMSGCAP Pf2 Msi Cap Multimsgcap 0 PF2_MSI_CAP_NEXTPTR Pf2 Msi Cap Nextptr 0x70 PF2_PM_CAP_NEXTPTR Pf2 Pm Cap Nextptr 0x70 PF2_REVISION_ID Pf2 Revision Id 0x00 PF2_SRIOV_BAR0_APERTURE_SIZE Pf2 Sriov Bar0 Aperture Size 0x00 PF2_SRIOV_BAR0_CONTROL Pf2 Sriov Bar0 Control 0x0 PF2_SRIOV_BAR1_APERTURE_SIZE Pf2 Sriov Bar1 Aperture Size 0x00 PF2_SRIOV_BAR1_CONTROL Pf2 Sriov Bar1 Control 0x0 PF2_SRIOV_BAR2_APERTURE_SIZE Pf2 Sriov Bar2 Aperture Size 0x00 PF2_SRIOV_BAR2_CONTROL Pf2 Sriov Bar2 Control 0x0 PF2_SRIOV_BAR3_APERTURE_SIZE Pf2 Sriov Bar3 Aperture Size 0x00 PF2_SRIOV_BAR3_CONTROL Pf2 Sriov Bar3 Control 0x0 PF2_SRIOV_BAR4_APERTURE_SIZE Pf2 Sriov Bar4 Aperture Size 0x00 PF2_SRIOV_BAR4_CONTROL Pf2 Sriov Bar4 Control 0x0 PF2_SRIOV_BAR5_APERTURE_SIZE Pf2 Sriov Bar5 Aperture Size 0x00 PF2_SRIOV_BAR5_CONTROL Pf2 Sriov Bar5 Control 0x0 PF2_SRIOV_CAP_INITIAL_VF Pf2 Sriov Cap Initial Vf 0x0000 PF2_SRIOV_CAP_NEXTPTR Pf2 Sriov Cap Nextptr 0x000 PF2_SRIOV_CAP_TOTAL_VF Pf2 Sriov Cap Total Vf 0x0000 PF2_SRIOV_CAP_VER Pf2 Sriov Cap Ver 0x1 PF2_SRIOV_FIRST_VF_OFFSET Pf2 Sriov First Vf Offset 0x0000 PF2_SRIOV_FUNC_DEP_LINK Pf2 Sriov Func Dep Link 0x0002 PF2_SRIOV_SUPPORTED_PAGE_SIZE Pf2 Sriov Supported Page Size 0x00000553 PF2_SRIOV_VF_DEVICE_ID Pf2 Sriov Vf Device Id 0x0000 PF2_SUBSYSTEM_ID Pf2 Subsystem Id 0x0007 PF2_TPHR_CAP_NEXTPTR Pf2 Tphr Cap Nextptr 0x000 PF3_AER_CAP_NEXTPTR Pf3 Aer Cap Nextptr 0x000 PF3_ARI_CAP_NEXTPTR Pf3 Ari Cap Nextptr 0x000 PF3_BAR0_APERTURE_SIZE Pf3 Bar0 Aperture Size 0x009 PF3_BAR0_CONTROL Pf3 Bar0 Control 0x4 PF3_BAR1_APERTURE_SIZE Pf3 Bar1 Aperture Size 0x000 PF3_BAR1_CONTROL Pf3 Bar1 Control 0x0 PF3_BAR2_APERTURE_SIZE Pf3 Bar2 Aperture Size 0x000 PF3_BAR2_CONTROL Pf3 Bar2 Control 0x0 PF3_BAR3_APERTURE_SIZE Pf3 Bar3 Aperture Size 0x000 PF3_BAR3_CONTROL Pf3 Bar3 Control 0x0 PF3_BAR4_APERTURE_SIZE Pf3 Bar4 Aperture Size 0x000 PF3_BAR4_CONTROL Pf3 Bar4 Control 0x0 PF3_BAR5_APERTURE_SIZE Pf3 Bar5 Aperture Size 0x000 PF3_BAR5_CONTROL Pf3 Bar5 Control 0x0 PF3_CAPABILITY_POINTER Pf3 Capability Pointer 0x40 PF3_CLASS_CODE Pf3 Class Code 0x058000 PF3_DEVICE_ID Pf3 Device Id 0x9638 PF3_DEV_CAP_MAX_PAYLOAD_SIZE Pf3 Dev Cap Max Payload Size 0x3 PF3_DSN_CAP_NEXTPTR Pf3 Dsn Cap Nextptr 0x000 PF3_EXPANSION_ROM_APERTURE_SIZE Pf3 Expansion Rom Aperture Size 0x000 PF3_EXPANSION_ROM_ENABLE Pf3 Expansion Rom Enable FALSE PF3_INTERRUPT_PIN Pf3 Interrupt Pin 0x0 PF3_MSIX_CAP_NEXTPTR Pf3 Msix Cap Nextptr 0x70 PF3_MSIX_CAP_PBA_BIR Pf3 Msix Cap Pba Bir 0 PF3_MSIX_CAP_PBA_OFFSET Pf3 Msix Cap Pba Offset 0x00000000 PF3_MSIX_CAP_TABLE_BIR Pf3 Msix Cap Table Bir 0 PF3_MSIX_CAP_TABLE_OFFSET Pf3 Msix Cap Table Offset 0x00000000 PF3_MSIX_CAP_TABLE_SIZE Pf3 Msix Cap Table Size 0x000 PF3_MSI_CAP_MULTIMSGCAP Pf3 Msi Cap Multimsgcap 0 PF3_MSI_CAP_NEXTPTR Pf3 Msi Cap Nextptr 0x70 PF3_PM_CAP_NEXTPTR Pf3 Pm Cap Nextptr 0x70 PF3_REVISION_ID Pf3 Revision Id 0x00 PF3_SRIOV_BAR0_APERTURE_SIZE Pf3 Sriov Bar0 Aperture Size 0x00 PF3_SRIOV_BAR0_CONTROL Pf3 Sriov Bar0 Control 0x0 PF3_SRIOV_BAR1_APERTURE_SIZE Pf3 Sriov Bar1 Aperture Size 0x00 PF3_SRIOV_BAR1_CONTROL Pf3 Sriov Bar1 Control 0x0 PF3_SRIOV_BAR2_APERTURE_SIZE Pf3 Sriov Bar2 Aperture Size 0x00 PF3_SRIOV_BAR2_CONTROL Pf3 Sriov Bar2 Control 0x0 PF3_SRIOV_BAR3_APERTURE_SIZE Pf3 Sriov Bar3 Aperture Size 0x00 PF3_SRIOV_BAR3_CONTROL Pf3 Sriov Bar3 Control 0x0 PF3_SRIOV_BAR4_APERTURE_SIZE Pf3 Sriov Bar4 Aperture Size 0x00 PF3_SRIOV_BAR4_CONTROL Pf3 Sriov Bar4 Control 0x0 PF3_SRIOV_BAR5_APERTURE_SIZE Pf3 Sriov Bar5 Aperture Size 0x00 PF3_SRIOV_BAR5_CONTROL Pf3 Sriov Bar5 Control 0x0 PF3_SRIOV_CAP_INITIAL_VF Pf3 Sriov Cap Initial Vf 0x0000 PF3_SRIOV_CAP_NEXTPTR Pf3 Sriov Cap Nextptr 0x000 PF3_SRIOV_CAP_TOTAL_VF Pf3 Sriov Cap Total Vf 0x0000 PF3_SRIOV_CAP_VER Pf3 Sriov Cap Ver 0x1 PF3_SRIOV_FIRST_VF_OFFSET Pf3 Sriov First Vf Offset 0x0000 PF3_SRIOV_FUNC_DEP_LINK Pf3 Sriov Func Dep Link 0x0003 PF3_SRIOV_SUPPORTED_PAGE_SIZE Pf3 Sriov Supported Page Size 0x00000553 PF3_SRIOV_VF_DEVICE_ID Pf3 Sriov Vf Device Id 0x0000 PF3_SUBSYSTEM_ID Pf3 Subsystem Id 0x0007 PF3_TPHR_CAP_NEXTPTR Pf3 Tphr Cap Nextptr 0x000 PL_UPSTREAM_FACING Pl Upstream Facing TRUE PL_DISABLE_LANE_REVERSAL Pl Disable Lane Reversal TRUE PF0_MSI_CAP_PERVECMASKCAP en pf0 msi per vec masking FALSE PF1_MSI_CAP_PERVECMASKCAP en pf1 msi per vec masking FALSE PF2_MSI_CAP_PERVECMASKCAP en pf2 msi per vec masking FALSE PF3_MSI_CAP_PERVECMASKCAP en pf3 msi per vec masking FALSE SRIOV_CAP_ENABLE Sriov Cap Enable 0x1 TL_CREDITS_CD Tl Credits Cd 0x000 TL_CREDITS_CH Tl Credits Ch 0x00 TL_CREDITS_NPD Tl Credits Npd 0x004 TL_CREDITS_NPH Tl Credits Nph 0x20 TL_CREDITS_PD Tl Credits Pd 0x3E0 TL_CREDITS_PH Tl Credits Ph 0x20 EXTENDED_CFG_EXTEND_INTERFACE_ENABLE Tl Extended Cfg Extend Interface Enable FALSE EXT_XVC_VSEC_ENABLE Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design FALSE LEGACY_CFG_EXTEND_INTERFACE_ENABLE FALSE ACS_EXT_CAP_ENABLE FALSE ACS_CAP_NEXTPTR 0x000 PDVSEC_NEXTPTR 0x000 TL_LEGACY_MODE_ENABLE Tl Legacy Mode Enable FALSE TL_PF_ENABLE_REG 0 VF0_CAPABILITY_POINTER Vf0 Capability Pointer 0x70 TL_COMPLETION_RAM_SIZE Completion Space 0x2 gen_x0y0_xdc Generate X0Y0 XDC 0 gen_x0y1_xdc Generate X0Y1 XDC 0 gen_x0y2_xdc Generate X0Y2 XDC 0 gen_x0y3_xdc Generate X0Y3 XDC 0 gen_x0y4_xdc Generate X0Y4 XDC 0 gen_x0y5_xdc Generate X0Y5 XDC 0 gen_x0y6_xdc Generate X0Y6 XDC 0 gen_x0y7_xdc Generate X0Y7 XDC 0 gen_x1y0_xdc Generate X1Y0 XDC 0 gen_x1y1_xdc Generate X1Y1 XDC 0 gen_x1y2_xdc Generate X1Y2 XDC 0 gen_x1y3_xdc Generate X1Y3 XDC 0 gen_x1y4_xdc Generate X1Y4 XDC 0 gen_x1y5_xdc Generate X1Y5 XDC 0 xlnx_ref_board Xlnx Ref Board AU50 pcie_blk_locn Pcie Blk Locn 6 PIPE_SIM FALSE AXISTEN_IF_ENABLE_CLIENT_TAG TRUE PCIE_FAST_CONFIG PCIE FAST CONFIG NONE EXT_STARTUP_PRIMITIVE EXT STARTUP PRIMITIVE FALSE PL_INTERFACE PL INTERFACE FALSE PCIE_CONFIGURATION PCIE CONFIGURATION FALSE CFG_STATUS_IF TRUE TX_FC_IF TRUE CFG_EXT_IF FALSE CFG_FC_IF TRUE PER_FUNC_STATUS_IF TRUE CFG_MGMT_IF TRUE RCV_MSG_IF TRUE CFG_TX_MSG_IF TRUE CFG_CTL_IF TRUE CFG_PM_IF TRUE PCIE_ID_IF FALSE MSI_EN TRUE MSIX_EN FALSE PCIE4_DRP FALSE DIS_GT_WIZARD FALSE BMD_PIO_MODE FALSE SRIOV_EXD_MODE FALSE DBG_CHECKER FALSE ENABLE_IBERT FALSE GEN4_EIEOS_0S7 TRUE ENABLE_JTAG_DBG FALSE ENABLE_LTSSM_DBG FALSE TWO_PORT_SWITCH FALSE TWO_PORT_CONFIG X8G3 TRANSCEIVER_CTRL_STATUS_PORTS FALSE SHARED_LOGIC 1 GTWIZ_IN_CORE 1 GTCOM_IN_CORE 2 AXISTEN_IF_RX_PARITY_EN FALSE AXISTEN_IF_TX_PARITY_EN FALSE AXISTEN_IF_MSIX_RX_PARITY_EN FALSE LL_TX_TLP_PARITY_CHK FALSE LL_RX_TLP_PARITY_GEN FALSE TL2CFG_IF_PARITY_CHK FALSE AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE FALSE DEDICATE_PERST FALSE SYS_RESET_POLARITY 0 MCAP_ENABLEMENT NONE MCAP_FPGA_BITSTREAM_VERSION MCAP Bitstream Version Register Value 0x00000000 EXT_CH_GT_DRP FALSE EN_GT_SELECTION FALSE SELECT_QUAD GTY_Quad_227 silicon_revision Silicon Revision Beta DEV_PORT_TYPE 0 VFG0_MSIX_CAP_PBA_BIR Pf0 Msix Cap Pba Bir 0 VFG0_MSIX_CAP_PBA_OFFSET Pf0 Msix Cap Pba Offset 0x00000000 VFG0_MSIX_CAP_TABLE_BIR Pf0 Msix Cap Table Bir 0 VFG0_MSIX_CAP_TABLE_OFFSET Pf0 Msix Cap Table Offset 0x00000000 VFG0_MSIX_CAP_TABLE_SIZE Pf0 Msix Cap Table Size 0x000 VFG1_MSIX_CAP_PBA_BIR Pf0 Msix Cap Pba Bir 0 VFG1_MSIX_CAP_PBA_OFFSET Pf0 Msix Cap Pba Offset 0x00000000 VFG1_MSIX_CAP_TABLE_BIR Pf0 Msix Cap Table Bir 0 VFG1_MSIX_CAP_TABLE_OFFSET Pf0 Msix Cap Table Offset 0x00000000 VFG1_MSIX_CAP_TABLE_SIZE Pf0 Msix Cap Table Size 0x000 VFG2_MSIX_CAP_PBA_BIR Pf0 Msix Cap Pba Bir 0 VFG2_MSIX_CAP_PBA_OFFSET Pf0 Msix Cap Pba Offset 0x00000000 VFG2_MSIX_CAP_TABLE_BIR Pf0 Msix Cap Table Bir 0 VFG2_MSIX_CAP_TABLE_OFFSET Pf0 Msix Cap Table Offset 0x00000000 VFG2_MSIX_CAP_TABLE_SIZE Pf0 Msix Cap Table Size 0x000 VFG3_MSIX_CAP_PBA_BIR Pf0 Msix Cap Pba Bir 0 VFG3_MSIX_CAP_PBA_OFFSET Pf0 Msix Cap Pba Offset 0x00000000 VFG3_MSIX_CAP_TABLE_BIR Pf0 Msix Cap Table Bir 0 VFG3_MSIX_CAP_TABLE_OFFSET Pf0 Msix Cap Table Offset 0x00000000 VFG3_MSIX_CAP_TABLE_SIZE Pf0 Msix Cap Table Size 0x000 EN_PARITY FALSE INS_LOSS_PROFILE ADD-IN_CARD MSI_X_OPTIONS None COMPLETER_MODEL FALSE DBG_DESCRAMBLE_EN FALSE PIPE_DEBUG_EN FALSE MSI_INT MSI Ints 32 VU9P_BOARD FALSE PHY_LP_TXPRESET 4 IS_BOARD_PROJECT Is Board Flow Enabled 1 GT_DRP_CLK_SRC GT DRP Clk Source 0 FREE_RUN_FREQ Free Run Freq 1 PM_ENABLE_L23_ENTRY FALSE AWS_MODE_VALUE aws mode value 0 AXISTEN_IF_CCIX_RX_CREDIT_LIMIT Ccix Rx Credit Limit 0x08 AXISTEN_IF_CCIX_TX_CREDIT_LIMIT Ccix Tx Credit Limit 0x08 AXISTEN_IF_CCIX_TX_REGISTERED_TREADY Ccix Tx Tready Registered FALSE CCIX_DIRECT_ATTACH_MODE Ccix Direct Attach Mode FALSE CCIX_ENABLE Ccix Enable FALSE THREE_PORT_SWITCH FALSE CCIX_DVSEC Ccix Dvsec Enable FALSE CCIX_VENDOR_ID Pf0 Vendor Id 0x1E2C PF0_ATS_CAP_INV_QUEUE_DEPTH Pf0 Ats Cap Inv Queue Depth 0x00 PF0_ATS_CAP_NEXTPTR Pf0 Ats Cap Next Ptr 0x000 PF0_ATS_CAP_ON Pf0 Ats Cap On FALSE PF0_PRI_CAP_NEXTPTR Pf0 Pri Cap Next Ptr 0x000 PF0_PRI_CAP_ON Pf0 Pri Cap On FALSE PF0_PRI_OST_PR_CAPACITY Pf0 Pri Ost Pr Capacity 0x00000000 PF0_VC_ARB_CAPABILITY Pf0 Vc Arb Capability 0x0 PF0_VC_ARB_TBL_OFFSET Pf0 Vc Arb Tbl Offset 0x31 PF0_VC_EXTENDED_COUNT Pf0 Vc Extended Count FALSE PF0_VC_LOW_PRIORITY_EXTENDED_COUNT Pf0 Vc Low Priority Extended Count FALSE PF1_ATS_CAP_INV_QUEUE_DEPTH Pf1 Ats Cap Inv Queue Depth 0x00 PF1_ATS_CAP_NEXTPTR Pf1 Ats Cap Next Ptr 0x000 PF1_ATS_CAP_ON Pf1 Ats Cap On FALSE PF1_PRI_CAP_NEXTPTR Pf1 Pri Cap Next Ptr 0x000 PF1_PRI_CAP_ON Pf1 Pri Cap ON FALSE PF1_PRI_OST_PR_CAPACITY Pf1 Pri Ost Pr Capacity 0x00000000 PF2_ATS_CAP_INV_QUEUE_DEPTH Pf2 Ats Cap Inv Queue Depth 0x00 PF2_ATS_CAP_NEXTPTR Pf2 Ats Cap Next Ptr 0x000 PF2_ATS_CAP_ON Pf2 Ats Cap On FALSE PF2_PRI_CAP_NEXTPTR Pf2 Pri Cap Next Ptr 0x000 PF2_PRI_CAP_ON Pf2 Pri Cap On FALSE PF2_PRI_OST_PR_CAPACITY Pf2 Pri Ost Pr Capacity 0x00000000 PF3_ATS_CAP_INV_QUEUE_DEPTH Pf3 Ats Cap Inv Queue Depth 0x00 PF3_ATS_CAP_NEXTPTR Pf3 Ats Cap Next Ptr 0x000 PF3_ATS_CAP_ON Pf3 Ats Cap On FALSE PF3_PRI_CAP_NEXTPTR Pf3 Pri Cap Next Ptr 0x000 PF3_PRI_CAP_ON Pf3 Pri Cap On FALSE PF3_PRI_OST_PR_CAPACITY Pf3 Pri Ost Pr Capacity 0x00000000 PL_CTRL_SKP_GEN_ENABLE Pl Ctrl Skp Gen Enable FALSE PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE Pl Ctrl Skp Parity And Crc Check Disable TRUE PL_USER_SPARE2 Pl User Spare2 0x0000 TL_CREDITS_CD_VC1 Tl Credits Cd Vc1 0x000 TL_CREDITS_CH_VC1 Tl Credits Ch Vc1 0x00 TL_CREDITS_NPD_VC1 Tl Credits Npd Vc1 0x000 TL_CREDITS_NPH_VC1 Tl Credits Nph Vc1 0x01 TL_CREDITS_PD_VC1 Tl Credits Pd Vc1 0x1C0 TL_CREDITS_PH_VC1 Tl Credits Ph Vc1 0x40 TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1 Tl Fc update Min Interval Time Vc1 0x02 TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1 Tl Fc Update Min Internal Tlp Count Vc1 0x04 TL_FEATURE_ENABLE_FC_SCALING Tl Feature Enable Fc Scaling FALSE VFG0_ATS_CAP_INV_QUEUE_DEPTH Vfg0 Ats Cap Inv Queue Depth 0x00 VFG0_ATS_CAP_NEXTPTR Vfg0 Ats Cap Next Ptr 0x000 VFG0_ATS_CAP_ON Vfg0 Ats Cap On FALSE VFG1_ATS_CAP_INV_QUEUE_DEPTH Vfg1 Ats Cap Inv Queue Depth 0x00 VFG1_ATS_CAP_NEXTPTR Vfg1 Ats Cap Next Ptr 0x000 VFG1_ATS_CAP_ON Vfg1 Ats Cap On FALSE VFG2_ATS_CAP_INV_QUEUE_DEPTH Vfg2 Ats Cap Inv Queue Depth 0x00 VFG2_ATS_CAP_NEXTPTR Vfg2 Ats Cap Next Ptr 0x000 VFG2_ATS_CAP_ON Vfg2 Ats Cap On FALSE VFG3_ATS_CAP_INV_QUEUE_DEPTH Vfg3 Ats Cap Inv Queue Depth 0x00 VFG3_ATS_CAP_NEXTPTR Vfg3 Ats Cap Next Ptr 0x000 VFG3_ATS_CAP_ON Vfg3 Ats Cap On FALSE EXT_SYS_CLK_BUFG FALSE AXISTEN_IF_ENABLE_MSG_ROUTE 0x20000 GT_TYPE GTY TX_RX_MASTER_CHANNEL X1Y15 X1_CH_EN X1Y15 X2_CH_EN X1Y15 X1Y14 X4_CH_EN X1Y15 X1Y14 X1Y13 X1Y12 X8_CH_EN X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 XS_CH_EN X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 X1Y7 X1Y6 X1Y5 X1Y4 X1Y3 X1Y2 X1Y1 X1Y0 ENABLE_MORE FALSE DISABLE_BRAM_PIPELINE FALSE DISABLE_EQ_SYNCHRONIZER FALSE ENABLE_AUTO_RXEQ FALSE ENABLE_MULTIPF_AER multi pf aer fix FALSE RBAR_ENABLE FALSE PF0_RBAR_CAP_BAR0_UPPER PF0 Resizable BAR0 Capability upper 16 bits 0x0000 PF0_RBAR_CAP_BAR0_LOWER PF0 Resizable BAR0 Capability lower 32 bits 0x0000fff0 PF0_RBAR_CAP_BAR1_UPPER PF0 Resizable BAR1 Capability upper 16 bits 0x0000 PF0_RBAR_CAP_BAR1_LOWER PF0 Resizable BAR1 Capability lower 32 bits 0x00000000 PF0_RBAR_CAP_BAR2_UPPER PF0 Resizable BAR2 Capability upper 16 bits 0x0000 PF0_RBAR_CAP_BAR2_LOWER PF0 Resizable BAR2 Capability lower 32 bits 0x00000000 PF0_RBAR_CAP_BAR3_UPPER PF0 Resizable BAR3 Capability upper 16 bits 0x0000 PF0_RBAR_CAP_BAR3_LOWER PF0 Resizable BAR3 Capability lower 32 bits 0x00000000 PF0_RBAR_CAP_BAR4_UPPER PF0 Resizable BAR4 Capability upper 16 bits 0x0000 PF0_RBAR_CAP_BAR4_LOWER PF0 Resizable BAR4 Capability lower 32 bits 0x00000000 PF0_RBAR_CAP_BAR5_UPPER PF0 Resizable BAR5 Capability upper 16 bits 0x0000 PF0_RBAR_CAP_BAR5_LOWER PF0 Resizable BAR5 Capability lower 32 bits 0x00000000 PF1_RBAR_CAP_BAR0_UPPER PF1 Resizable BAR0 Capability upper 16 bits 0x0000 PF1_RBAR_CAP_BAR0_LOWER PF1 Resizable BAR0 Capability lower 32 bits 0x0000fff0 PF1_RBAR_CAP_BAR1_UPPER PF1 Resizable BAR1 Capability upper 16 bits 0x0000 PF1_RBAR_CAP_BAR1_LOWER PF1 Resizable BAR1 Capability lower 32 bits 0x00000000 PF1_RBAR_CAP_BAR2_UPPER PF1 Resizable BAR2 Capability upper 16 bits 0x0000 PF1_RBAR_CAP_BAR2_LOWER PF1 Resizable BAR2 Capability lower 32 bits 0x00000000 PF1_RBAR_CAP_BAR3_UPPER PF1 Resizable BAR3 Capability upper 16 bits 0x0000 PF1_RBAR_CAP_BAR3_LOWER PF1 Resizable BAR3 Capability lower 32 bits 0x00000000 PF1_RBAR_CAP_BAR4_UPPER PF1 Resizable BAR4 Capability upper 16 bits 0x0000 PF1_RBAR_CAP_BAR4_LOWER PF1 Resizable BAR4 Capability lower 32 bits 0x00000000 PF1_RBAR_CAP_BAR5_UPPER PF1 Resizable BAR5 Capability upper 16 bits 0x0000 PF1_RBAR_CAP_BAR5_LOWER PF1 Resizable BAR5 Capability lower 32 bits 0x00000000 PF2_RBAR_CAP_BAR0_UPPER PF2 Resizable BAR0 Capability upper 16 bits 0x0000 PF2_RBAR_CAP_BAR0_LOWER PF2 Resizable BAR0 Capability lower 32 bits 0x0000fff0 PF2_RBAR_CAP_BAR1_UPPER PF2 Resizable BAR1 Capability upper 16 bits 0x0000 PF2_RBAR_CAP_BAR1_LOWER PF2 Resizable BAR1 Capability lower 32 bits 0x00000000 PF2_RBAR_CAP_BAR2_UPPER PF2 Resizable BAR2 Capability upper 16 bits 0x0000 PF2_RBAR_CAP_BAR2_LOWER PF2 Resizable BAR2 Capability lower 32 bits 0x00000000 PF2_RBAR_CAP_BAR3_UPPER PF2 Resizable BAR3 Capability upper 16 bits 0x0000 PF2_RBAR_CAP_BAR3_LOWER PF2 Resizable BAR3 Capability lower 32 bits 0x00000000 PF2_RBAR_CAP_BAR4_UPPER PF2 Resizable BAR4 Capability upper 16 bits 0x0000 PF2_RBAR_CAP_BAR4_LOWER PF2 Resizable BAR4 Capability lower 32 bits 0x00000000 PF2_RBAR_CAP_BAR5_UPPER PF2 Resizable BAR5 Capability upper 16 bits 0x0000 PF2_RBAR_CAP_BAR5_LOWER PF2 Resizable BAR5 Capability lower 32 bits 0x00000000 PF3_RBAR_CAP_BAR0_UPPER PF3 Resizable BAR0 Capability upper 16 bits 0x0000 PF3_RBAR_CAP_BAR0_LOWER PF3 Resizable BAR0 Capability lower 32 bits 0x0000fff0 PF3_RBAR_CAP_BAR1_UPPER PF3 Resizable BAR1 Capability upper 16 bits 0x0000 PF3_RBAR_CAP_BAR1_LOWER PF3 Resizable BAR1 Capability lower 32 bits 0x00000000 PF3_RBAR_CAP_BAR2_UPPER PF3 Resizable BAR2 Capability upper 16 bits 0x0000 PF3_RBAR_CAP_BAR2_LOWER PF3 Resizable BAR2 Capability lower 32 bits 0x00000000 PF3_RBAR_CAP_BAR3_UPPER PF3 Resizable BAR3 Capability upper 16 bits 0x0000 PF3_RBAR_CAP_BAR3_LOWER PF3 Resizable BAR3 Capability lower 32 bits 0x00000000 PF3_RBAR_CAP_BAR4_UPPER PF3 Resizable BAR4 Capability upper 16 bits 0x0000 PF3_RBAR_CAP_BAR4_LOWER PF3 Resizable BAR4 Capability lower 32 bits 0x00000000 PF3_RBAR_CAP_BAR5_UPPER PF3 Resizable BAR5 Capability upper 16 bits 0x0000 PF3_RBAR_CAP_BAR5_LOWER PF3 Resizable BAR5 Capability lower 32 bits 0x00000000 RBAR_CAP_NEXTPTR 0x000 PF0_RBAR_NUM_BAR 0x1 PF1_RBAR_NUM_BAR 0x1 PF2_RBAR_NUM_BAR 0x1 PF3_RBAR_NUM_BAR 0x1 PF0_RBAR_BAR_INDEX_0 0x0 PF0_RBAR_BAR_INDEX_1 0x7 PF0_RBAR_BAR_INDEX_2 0x7 PF0_RBAR_BAR_INDEX_3 0x7 PF0_RBAR_BAR_INDEX_4 0x7 PF0_RBAR_BAR_INDEX_5 0x7 PF1_RBAR_BAR_INDEX_0 0x0 PF1_RBAR_BAR_INDEX_1 0x7 PF1_RBAR_BAR_INDEX_2 0x7 PF1_RBAR_BAR_INDEX_3 0x7 PF1_RBAR_BAR_INDEX_4 0x7 PF1_RBAR_BAR_INDEX_5 0x7 PF2_RBAR_BAR_INDEX_0 0x0 PF2_RBAR_BAR_INDEX_1 0x7 PF2_RBAR_BAR_INDEX_2 0x7 PF2_RBAR_BAR_INDEX_3 0x7 PF2_RBAR_BAR_INDEX_4 0x7 PF2_RBAR_BAR_INDEX_5 0x7 PF3_RBAR_BAR_INDEX_0 0x0 PF3_RBAR_BAR_INDEX_1 0x7 PF3_RBAR_BAR_INDEX_2 0x7 PF3_RBAR_BAR_INDEX_3 0x7 PF3_RBAR_BAR_INDEX_4 0x7 PF3_RBAR_BAR_INDEX_5 0x7 USE_STANDARD_INTERFACES Use standard interfaces FALSE DMA_2RP FALSE SRIOV_ACTIVE_VFS 252 QDMA_TPH_MSIX_BRAMS_DIS FALSE MASTER_GT_QUAD_INX 3 MASTER_GT_CONTAINER 27 ENABLE_MSIX_32VEC FALSE BROADCOM_SBR_WA FALSE choice_list_002f5e3f PCI_Express_Endpoint_device Legacy_PCI_Express_Endpoint_device Root_Port_of_PCI_Express_Root_Complex choice_list_0cee66fe 1 4 64 choice_list_0f93492c Chip-to-Chip Add-in_Card Backplane choice_list_165ed04b 64 choice_list_1e9fb93b X1 X2 X4 X8 X16 choice_list_24b724fb Basic Advanced choice_list_34d65ff4 128 choice_list_35d06715 2 choice_list_38306dd1 SOFT HARD choice_list_3ca2cbc7 BAR_0 choice_list_3d9ff82c 500 250 choice_list_52d29139 Bytes Kilobytes Megabytes Gigabytes choice_list_5590a31b X1Y15 choice_list_589df8e9 RAM Other_memory_controller Flash choice_list_5e2921cd Kilobytes choice_list_5e45706a 1_vector 2_vectors 4_vectors 8_vectors 16_vectors 32_vectors choice_list_61bc5fcf 0 4 7 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 220 224 228 232 236 240 244 248 252 choice_list_635d42ef X1Y15 X1Y14 choice_list_6b979ebc 250 choice_list_6e3ded9c 0 1 2 3 choice_list_6e6f488f X1Y15 X1Y14 X1Y13 X1Y12 choice_list_6eff49bd ACTIVE_LOW ACTIVE_HIGH choice_list_75aee2a8 X8G3 X16G3 choice_list_7a7dde49 true false choice_list_7d45a81a 128_bytes 256_bytes 512_bytes 1024_bytes choice_list_7e60966b 2.5_GT/s 5.0_GT/s 8.0_GT/s 16.0_GT/s choice_list_8061eec5 None Tandem_PROM Tandem_PCIe Tandem_PCIe_with_Field_Updates DFX_over_PCIe choice_list_81a1639d DWORD_Aligned Address_Aligned choice_list_847d868a 1 2 3 4 5 6 choice_list_88156f2e QPLL1 QPLL0 choice_list_8b5e4915 4 5 choice_list_909966b7 X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 choice_list_914704bd 100_MHz 125_MHz choice_list_97bc19ec 256_bit choice_list_98ff8152 GTY choice_list_9aec9108 Internal External choice_list_a30da595 Custom pcie_perstn choice_list_a44ca313 Custom pci_express_x1 pci_express_x16 pci_express_x2 pci_express_x4 pci_express_x8 choice_list_aa031417 1 2 3 4 choice_list_abc20383 GTY_Quad_227 GTY_Quad_226 GTY_Quad_225 GTY_Quad_224 choice_list_b41755a5 X1Y0 X0Y1 X0Y0 X1Y1 choice_list_bdd7203f True False choice_list_bea500ca None MSI-X_External MSI-X_Internal MSI-X_AXI4-Stream choice_list_c15e8c67 1 2 4 8 16 32 64 128 256 512 choice_list_c3d223d9 Memory choice_list_c8a15465 X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 X1Y7 X1Y6 X1Y5 X1Y4 X1Y3 X1Y2 X1Y1 X1Y0 choice_list_ca005b72 No_ASPM L1_Supported choice_list_d123c74c Bytes Kilobytes Megabytes choice_list_d53faa96 100_MHz 125_MHz 250_MHz choice_list_d85ad257 0 choice_list_d992adf6 Generic_XT_compatible_serial_controller 16450_compatible_serial_controller Parallel_port IEEE_1284_controller Multiport_serial_controller 16650_compatible_serial_controller IEEE_1284_target_device Hayes_compatible_modem_with_16550_compatible_interface ECP_1.X_compliant_parallel_port 16850_compatible_serial_controller Hayes_compatible_modem_with_16750_compatible_interface Smart_Card Bi_directional_parallel_port Other_communications_device GPIB(IEEE_488.1/2)_controller 16550_compatible_serial_controller Hayes_compatible_modem_with_16450_compatible_interface 16750_compatible_serial_controller Hayes_compatible_modem_with_16650_compatible_interface Generic_modem 16950_compatible_serial_controller choice_list_dff1a45d Wireless_controller Satellite_communication_controllers Data_acquisition_and_signal_processing_controllers Processing_accelerators Intelligent_I/O_controllers Docking_stations Device_was_built_before_Class_Code_definitions_were_finalized Memory_controller Simple_communication_controllers Serial_bus_controllers Encryption/Decryption_controllers Display_controller Multimedia_device Input_devices Mass_storage_controller Processors Device_does_not_fit_in_any_defined_classes Bridge_device Network_controller Base_system_peripherals choice_list_e7c484ae TRUE FALSE choice_list_e9cf6440 Disabled 32bit_Enabled 64bit_Enabled choice_list_eaa1f22e AU50 choice_list_ec64e624 N/A choice_list_ed82972e sample_smoke_test0 sample_smoke_test1 pio_writeReadBack_test0 choice_list_f1174048 NONE INTA INTB INTC INTD choice_list_f149a468 Extreme Good choice_list_fc3456a9 Disabled Enabled choice_pairs_3c87fcdb 1 0 choice_pairs_53749dec 1 0 choice_pairs_6f00a734 0 1 2 xilinx_elaboratesubcores_view_fileset ip_0/xdma_pcie4c_ip_gt.xci xci ip_0/xdma_pcie4c_ip_gt.xml xml The Xilinx UltraScale+ PCI Express Integrated Block (1-lane, 2-lane, 4-lane, 8-lane and 16-lane) in conjunction with flexible Ultra series architectural features such as integrated GTs (Gigabit Transceivers) and BRAM (Block RAMs) are used to implement a PCI Express Base Specification v3.1 compliant PCI Express Endpoint. device_port_type Device Port Type PCI_Express_Endpoint_device xlnx_ref_board Xlnx Ref Board AU50 true testname test sample_smoke_test0 PL_LINK_CAP_MAX_LINK_SPEED Pl Link Cap Max Link Speed 8.0_GT/s PL_LINK_CAP_MAX_LINK_WIDTH Pl Link Cap Max Link Width The Xilinx Ultrascale Series Gen3 Integrated Block for PCI Expressification v3.0 compliant PCI Express Endpoint. X8 REF_CLK_FREQ Ref Clk Freq 100_MHz AXISTEN_IF_EXT_512_CQ_STRADDLE Axisten If Rc Straddle false false AXISTEN_IF_EXT_512_CC_STRADDLE Axisten If Rc Straddle false AXISTEN_IF_EXT_512_RQ_STRADDLE Axisten If Rc Straddle false false AXISTEN_IF_EXT_512_RC_STRADDLE Axisten If Rc Straddle true AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE Axisten If 512 4TLP/2TLP Rc Straddle false false AXISTEN_IF_RC_STRADDLE Axisten If Rc Straddle true axisten_if_enable_client_tag Enable Client Tag true PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE Pf0 Aer Cap Ecrc Gen and Check Capable false type1_membase_memlimit_enable Type1 Config MemBase and MemLimit Enabled type1_prefetchable_membase_memlimit Type1 Config Prefetchable MemBase and MemLimit 64bit_Enabled PF0_CLASS_CODE Pf0 Class Code 070001 false PF0_DEVICE_ID Pf0 Device Id 9038 PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 128b Cas Atomic Completer Support false PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 32b Atomic Completer Support false PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 64b Atomic Completer Support false PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT Pf0 Dev Cap2 Tph Completer Support false PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE Pf0 Dev Cap Function Level Reset Capable false PF0_INTERRUPT_PIN Pf0 Interrupt Pin INTA PF0_LINK_STATUS_SLOT_CLOCK_CONFIG Pf0 Link Status Slot Clock Config true PF0_MSIX_CAP_PBA_BIR Pf0 Msix Cap Pba Bir BAR_0 false PF0_MSIX_CAP_PBA_OFFSET Pf0 Msix Cap Pba Offset 00000000 false PF0_MSIX_CAP_TABLE_BIR Pf0 Msix Cap Table Bir BAR_0 false PF0_MSIX_CAP_TABLE_OFFSET Pf0 Msix Cap Table Offset 00000000 false PF0_MSIX_CAP_TABLE_SIZE Pf0 Msix Cap Table Size 000 false PF0_MSI_CAP_MULTIMSGCAP Pf0 Msi Cap Multimsgcap 1_vector PF0_PM_CAP_PMESUPPORT_D1 Pf0 Pm Cap Pmesupport D1 false PF0_PM_CAP_PMESUPPORT_D3HOT Pf0 Pm Cap Pmesupport D3hot false PF0_PM_CAP_SUPP_D1_STATE Pf0 Pm Cap Supp D1 State false PF0_REVISION_ID Pf0 Revision Id 00 PF0_SRIOV_CAP_INITIAL_VF Pf0 Sriov Cap Initial Vf 0 SRIOV_FIRST_VF_OFFSET Pf0 Sriov First Vf Offset 4 PF0_SRIOV_FIRST_VF_OFFSET Pf0 Sriov First Vf Offset 0 false PF0_SRIOV_FUNC_DEP_LINK Pf0 Sriov Func Dep Link 0000 PF0_SRIOV_SUPPORTED_PAGE_SIZE Pf0 Sriov Supported Page Size 00000553 false PF0_SRIOV_VF_DEVICE_ID Pf0 Sriov Vf Device Id 0000 PF0_SUBSYSTEM_ID Pf0 Subsystem Id 0007 PF1_CLASS_CODE Pf1 Class Code 058000 PF1_DEVICE_ID Pf1 Device Id 9011 PF1_INTERRUPT_PIN Pf1 Interrupt Pin NONE PF1_MSIX_CAP_PBA_BIR Pf1 Msix Cap Pba Bir BAR_0 false PF1_MSIX_CAP_TABLE_BIR Pf1 Msix Cap Table Bir BAR_0 false PF1_MSIX_CAP_TABLE_SIZE Pf1 Msix Cap Table Size 000 false PF1_MSIX_CAP_TABLE_OFFSET Pf1 Msix Cap Table Offset 00000000 false PF1_MSIX_CAP_PBA_OFFSET Pf1 Msix Cap Pba Offset 00000000 false PF1_MSI_CAP_MULTIMSGCAP Pf1 Msi Cap Multimsgcap 1_vector PF1_REVISION_ID Pf1 Revision Id 00 PF1_SRIOV_CAP_INITIAL_VF Pf1 Sriov Cap Initial Vf 0 PF1_SRIOV_CAP_VER Pf1 Sriov Cap Ver 1 PF1_SRIOV_FIRST_VF_OFFSET Pf1 Sriov First Vf Offset 0 false PF1_SRIOV_FUNC_DEP_LINK Pf1 Sriov Func Dep Link 0001 PF1_SRIOV_SUPPORTED_PAGE_SIZE Pf1 Sriov Supported Page Size 00000553 false PF1_SRIOV_VF_DEVICE_ID Pf1 Sriov Vf Device Id 0000 PF1_SUBSYSTEM_ID Pf1 Subsystem Id 0007 PF2_CLASS_CODE Pf2 Class Code 058000 PF2_DEVICE_ID Pf2 Device Id 9438 PF2_INTERRUPT_PIN Pf2 Interrupt Pin NONE PF2_MSIX_CAP_PBA_BIR Pf2 Msix Cap Pba Bir BAR_0 false PF2_MSIX_CAP_TABLE_BIR Pf2 Msix Cap Table Bir BAR_0 false PF2_MSIX_CAP_TABLE_SIZE Pf2 Msix Cap Table Size 000 false PF2_MSIX_CAP_TABLE_OFFSET Pf2 Msix Cap Table Offset 00000000 false PF2_MSIX_CAP_PBA_OFFSET Pf2 Msix Cap Pba Offset 00000000 false PF2_MSI_CAP_MULTIMSGCAP Pf2 Msi Cap Multimsgcap 1_vector PF2_REVISION_ID Pf2 Revision Id 00 PF2_SRIOV_CAP_INITIAL_VF Pf2 Sriov Cap Initial Vf 0 PF2_SRIOV_CAP_VER Pf2 Sriov Cap Ver 1 PF2_SRIOV_FIRST_VF_OFFSET Pf2 Sriov First Vf Offset 0 false PF2_SRIOV_FUNC_DEP_LINK Pf2 Sriov Func Dep Link 0002 PF2_SRIOV_SUPPORTED_PAGE_SIZE Pf2 Sriov Supported Page Size 00000553 false PF2_SRIOV_VF_DEVICE_ID Pf2 Sriov Vf Device Id 0000 PF2_SUBSYSTEM_ID Pf2 Subsystem Id 0007 PF3_CLASS_CODE Pf3 Class Code 058000 PF3_DEVICE_ID Pf3 Device Id 9638 PF3_INTERRUPT_PIN Pf3 Interrupt Pin NONE PF3_MSIX_CAP_PBA_BIR Pf3 Msix Cap Pba Bir BAR_0 false PF3_MSIX_CAP_TABLE_BIR Pf3 Msix Cap Table Bir BAR_0 false PF3_MSIX_CAP_TABLE_SIZE Pf3 Msix Cap Table Size 000 false PF3_MSIX_CAP_TABLE_OFFSET Pf3 Msix Cap Table Offset 00000000 false PF3_MSIX_CAP_PBA_OFFSET Pf3 Msix Cap Pba Offset 00000000 false PF3_MSI_CAP_MULTIMSGCAP Pf3 Msi Cap Multimsgcap 1_vector PF3_REVISION_ID Pf3 Revision Id 00 PF3_SRIOV_CAP_INITIAL_VF Pf3 Sriov Cap Initial Vf 0 PF3_SRIOV_CAP_VER Pf3 Sriov Cap Ver 1 PF3_SRIOV_FIRST_VF_OFFSET Pf3 Sriov First Vf Offset 0 false PF3_SRIOV_FUNC_DEP_LINK Pf3 Sriov Func Dep Link 0003 PF3_SRIOV_SUPPORTED_PAGE_SIZE Pf3 Sriov Supported Page Size 00000553 false PF3_SRIOV_VF_DEVICE_ID Pf3 Sriov Vf Device Id 0000 PF3_SUBSYSTEM_ID Pf3 Subsystem Id 0007 TL_PF_ENABLE_REG 1 SRIOV_CAP_ENABLE Sriov Cap Enable false Component_Name xdma_pcie4c_ip PF0_Use_Class_Code_Lookup_Assistant false PF1_Use_Class_Code_Lookup_Assistant false PF2_Use_Class_Code_Lookup_Assistant false PF3_Use_Class_Code_Lookup_Assistant false PF0_PM_CAP_PMESUPPORT_D0 Pf0 Pm Cap Pmesupport D0 false PF0_SUBSYSTEM_VENDOR_ID Pf0 Subsystem Vendor Id 10EE PF1_SUBSYSTEM_VENDOR_ID Pf1 Subsystem Vendor Id 10EE PF2_SUBSYSTEM_VENDOR_ID Pf2 Subsystem Vendor Id 10EE PF3_SUBSYSTEM_VENDOR_ID Pf3 Subsystem Vendor Id 10EE pf1_sriov_bar5_scale Pf1 Sriov Bar5 Scale Kilobytes false pf2_sriov_bar5_scale Pf2 Sriov Bar5 Scale Kilobytes false pf3_sriov_bar5_scale Pf3 Sriov Bar5 Scale Kilobytes false pf0_class_code_sub Pf0 Class Code Sub 00 pf1_sriov_bar4_type Pf1 Sriov Bar4 Type N/A false pf2_sriov_bar4_type Pf2 Sriov Bar4 Type N/A false pf3_sriov_bar4_type Pf3 Sriov Bar4 Type N/A false pf0_vc_cap_enabled Pf0 Vc Cap Enabled true pf1_sriov_bar5_type Pf1 Sriov Bar5 Type N/A false pf2_sriov_bar5_type Pf2 Sriov Bar5 Type N/A false pf3_sriov_bar5_type Pf3 Sriov Bar5 Type N/A false pf1_sriov_bar0_enabled Pf1 Sriov Bar0 Enabled true false pf2_sriov_bar0_enabled Pf2 Sriov Bar0 Enabled true false pf3_sriov_bar0_enabled Pf3 Sriov Bar0 Enabled true false pf0_sriov_bar5_enabled Pf0 Sriov Bar5 Enabled false pf2_sriov_bar5_enabled Pf2 Sriov Bar5 Enabled false false pf3_sriov_bar5_enabled Pf3 Sriov Bar5 Enabled false false pcie_blk_locn Pcie Blk Locn X1Y0 pf0_sriov_bar1_64bit Pf0 Sriov Bar1 64bit false false pf1_class_code_base Pf1 Class Code Base 05 pf2_class_code_base Pf2 Class Code Base 05 pf3_class_code_base Pf3 Class Code Base 05 pf1_sriov_bar3_prefetchable Pf1 Sriov Bar3 Prefetchable false false pf2_sriov_bar3_prefetchable Pf2 Sriov Bar3 Prefetchable false false pf3_sriov_bar3_prefetchable Pf3 Sriov Bar3 Prefetchable false false pf1_sriov_bar0_64bit Pf1 Sriov Bar0 64bit false false pf2_sriov_bar0_64bit Pf2 Sriov Bar0 64bit false false pf3_sriov_bar0_64bit Pf3 Sriov Bar0 64bit false false pf1_bar3_type Pf1 Bar3 Type N/A false pf2_bar3_type Pf2 Bar3 Type N/A false pf3_bar3_type Pf3 Bar3 Type N/A false pf2_bar2_enabled Pf2 Bar2 Enabled false false pf3_bar2_enabled Pf3 Bar2 Enabled false false pf1_bar2_enabled Pf1 Bar2 Enabled false false pf1_bar2_type Pf1 Bar2 Type N/A false pf1_bar2_64bit Pf1 Bar2 64bit false false pf1_bar2_prefetchable Pf1 Bar2 Prefetchable false false pf1_bar2_scale Pf1 Bar2 Scale Kilobytes false pf1_bar2_size Pf1 Bar2 Size 128 false pf0_class_code_interface Pf0 Class Code Interface 01 pf0_sriov_bar1_scale Pf0 Sriov Bar1 Scale Kilobytes false pf1_bar4_type Pf1 Bar4 Type N/A false pf2_bar2_type Pf2 Bar2 Type N/A false pf2_bar2_64bit Pf2 Bar2 64bit false false pf2_bar2_prefetchable Pf2 Bar2 Prefetchable false false pf2_bar2_scale Pf2 Bar2 Scale Kilobytes false pf2_bar2_size Pf2 Bar2 Size 128 false pf2_bar4_type Pf2 Bar4 Type N/A false pf3_bar2_type Pf3 Bar2 Type N/A false pf3_bar2_64bit Pf3 Bar2 64bit false false pf3_bar2_prefetchable Pf3 Bar2 Prefetchable false false pf3_bar2_scale Pf3 Bar2 Scale Kilobytes false pf3_bar2_size Pf3 Bar2 Size 128 false pf3_bar4_type Pf3 Bar4 Type N/A false pf0_base_class_menu Pf0 Base Class Menu Simple_communication_controllers pf0_sub_class_interface_menu Pf0 Sub Class Interface Menu 16450_compatible_serial_controller pf1_sriov_bar0_scale Pf1 Sriov Bar0 Scale Kilobytes false pf1_expansion_rom_enabled Pf1 Expansion Rom Enabled false false pf0_sriov_bar0_enabled Pf0 Sriov Bar0 Enabled true pf1_sriov_bar0_prefetchable Pf1 Sriov Bar0 Prefetchable false false pf1_bar5_type Pf1 Bar5 Type N/A false pf0_sriov_bar5_prefetchable Pf0 Sriov Bar5 Prefetchable false pf1_sriov_bar1_enabled Pf1 Sriov Bar1 Enabled false false pf1_class_code_interface Pf1 Class Code Interface 00 pf0_sriov_bar2_64bit Pf0 Sriov Bar2 64bit false false pf1_msix_enabled Pf1 Msix Enabled false pf1_bar5_prefetchable Pf1 Bar5 Prefetchable false pf1_sriov_bar1_64bit Pf1 Sriov Bar1 64bit false false pf1_bar3_64bit Pf1 Bar3 64bit false false pf0_sriov_bar2_prefetchable Pf0 Sriov Bar2 Prefetchable false false pf1_bar3_enabled Pf1 Bar3 Enabled false false pf0_sriov_bar2_scale Pf0 Sriov Bar2 Scale Kilobytes false pf1_sriov_bar1_scale Pf1 Sriov Bar1 Scale Kilobytes false pf1_bar3_scale Pf1 Bar3 Scale Kilobytes false pf0_sriov_bar1_enabled Pf0 Sriov Bar1 Enabled false AXISTEN_IF_RQ_ALIGNMENT_MODE DWORD_Aligned AXISTEN_IF_CQ_ALIGNMENT_MODE Address_Aligned alignment_mode_256b Alignment Mode DWORD_Aligned pf1_sriov_bar4_prefetchable Pf1 Sriov Bar4 Prefetchable false false pf1_sriov_bar2_enabled Pf1 Sriov Bar2 Enabled false false pf0_sriov_bar3_64bit Pf0 Sriov Bar3 64bit false false pf0_sriov_bar0_size Pf0 Sriov Bar0 Size 2 pf1_sriov_bar2_64bit Pf1 Sriov Bar2 64bit false false pf1_bar4_64bit Pf1 Bar4 64bit false false pf0_sriov_bar1_size Pf0 Sriov Bar1 Size 2 false pf0_bar0_enabled Pf0 Bar0 Enabled true pf0_bar0_type Pf0 Bar0 Type Memory pf0_bar0_64bit Pf0 Bar0 64bit false pf0_bar0_prefetchable Pf0 Bar0 Prefetchable false false pf0_bar0_scale Pf0 Bar0 Scale Kilobytes pf0_bar0_size Pf0 Bar0 Size 64 pf0_bar1_enabled Pf0 Bar1 Enabled false pf0_bar1_type Pf0 Bar1 Type N/A false pf0_bar1_64bit Pf0 Bar1 64bit false false pf0_bar1_prefetchable Pf0 Bar1 Prefetchable false false pf0_bar1_scale Pf0 Bar1 Scale Kilobytes false pf0_bar1_size Pf0 Bar1 Size 128 false pf0_bar2_enabled Pf0 Bar2 Enabled false pf0_bar2_type Pf0 Bar2 Type N/A false pf0_bar2_64bit Pf0 Bar2 64bit false false pf0_bar2_prefetchable Pf0 Bar2 Prefetchable false false pf0_bar2_scale Pf0 Bar2 Scale Kilobytes false pf0_bar2_size Pf0 Bar2 Size 128 false pf0_bar3_enabled Pf0 Bar3 Enabled false pf0_bar3_type Pf0 Bar3 Type N/A false pf0_bar3_64bit Pf0 Bar3 64bit false false pf0_bar3_prefetchable Pf0 Bar3 Prefetchable false false pf0_bar3_scale Pf0 Bar3 Scale Kilobytes false pf0_bar3_size Pf0 Bar3 Size 128 false pf0_bar4_enabled Pf0 Bar4 Enabled false pf0_bar4_type Pf0 Bar4 Type N/A false pf0_bar4_64bit Pf0 Bar4 64bit false false pf0_bar4_prefetchable Pf0 Bar4 Prefetchable false false pf0_bar4_scale Pf0 Bar4 Scale Kilobytes false pf0_bar4_size Pf0 Bar4 Size 128 false pf0_bar5_enabled Pf0 Bar5 Enabled false pf0_bar5_type Pf0 Bar5 Type N/A false pf0_bar5_prefetchable Pf0 Bar5 Prefetchable false pf0_bar5_scale Pf0 Bar5 Scale Kilobytes false pf0_bar5_size Pf0 Bar5 Size 128 false pf0_sriov_bar3_scale Pf0 Sriov Bar3 Scale Kilobytes false pf1_bar4_enabled Pf1 Bar4 Enabled false false pf1_sriov_bar1_prefetchable Pf1 Sriov Bar1 Prefetchable false false pf0_sriov_bar2_size Pf0 Sriov Bar2 Size 2 false pf1_sriov_bar2_scale Pf1 Sriov Bar2 Scale Kilobytes false pf1_bar4_scale Pf1 Bar4 Scale Kilobytes false pf0_sriov_bar3_size Pf0 Sriov Bar3 Size 2 false pf0_sriov_bar2_enabled Pf0 Sriov Bar2 Enabled false pf0_dev_cap_max_payload Pf0 Dev Cap Max Payload 1024_bytes gen_x0y0 Gen X0y0 true gen_x0y1 Gen X0y1 false gen_x0y2 Gen X0y2 false gen_x0y3 Gen X0y3 false gen_x0y4 Gen X0y4 false gen_x0y5 Gen X0y5 false gen_x0y6 Gen X0y6 false gen_x0y7 Gen X0y7 false gen_x1y0 Gen X1y0 false gen_x1y1 Gen X1y1 false gen_x1y2 Gen X1y2 false gen_x1y3 Gen X1y3 false gen_x1y4 Gen X1y4 false gen_x1y5 Gen X1y5 false pf0_sriov_bar4_size Pf0 Sriov Bar4 Size 2 false pf1_expansion_rom_scale Pf1 Expansion Rom Scale Kilobytes false pf1_expansion_rom_size Pf1 Expansion Rom Size 2 false pf1_sriov_bar3_enabled Pf1 Sriov Bar3 Enabled false false pf0_sriov_bar4_64bit Pf0 Sriov Bar4 64bit false false pf0_sriov_bar5_size Pf0 Sriov Bar5 Size 2 false pf0_sriov_bar3_prefetchable Pf0 Sriov Bar3 Prefetchable false false pf1_sriov_bar3_64bit Pf1 Sriov Bar3 64bit false false pf0_expansion_rom_enabled Pf0 Expansion Rom Enabled false pf0_sriov_bar4_scale Pf0 Sriov Bar4 Scale Kilobytes false pf1_base_class_menu Pf1 Base Class Menu Memory_controller pf1_sub_class_interface_menu Pf1 Sub Class Interface Menu Other_memory_controller pf0_sriov_bar0_type Pf0 Sriov Bar0 Type Memory pf1_bar5_enabled Pf1 Bar5 Enabled false false pf1_bar3_prefetchable Pf1 Bar3 Prefetchable false false pf1_sriov_bar0_size Pf1 Sriov Bar0 Size 2 false pf1_sriov_bar3_scale Pf1 Sriov Bar3 Scale Kilobytes false pf1_bar5_scale Pf1 Bar5 Scale Kilobytes false pf1_class_code_sub Pf1 Class Code Sub 80 extended_tag_field Extended Tag Field true pf0_sriov_bar1_type Pf0 Sriov Bar1 Type N/A false pf0_sriov_bar0_prefetchable Pf0 Sriov Bar0 Prefetchable false false pf0_expansion_rom_scale Pf0 Expansion Rom Scale Kilobytes false pf0_expansion_rom_size Pf0 Expansion Rom Size 2 false pf1_sriov_bar1_size Pf1 Sriov Bar1 Size 2 false pf0_sriov_bar3_enabled Pf0 Sriov Bar3 Enabled false pf1_sriov_bar5_prefetchable Pf1 Sriov Bar5 Prefetchable false pf0_sriov_bar2_type Pf0 Sriov Bar2 Type N/A false vendor_id Vendor Id 10EE pf1_vendor_id Vendor Id 10EE pf2_vendor_id Vendor Id 10EE pf3_vendor_id Vendor Id 10EE pf0_tphr_enable Pf0 Tphr Enable false pf1_sriov_bar2_size Pf1 Sriov Bar2 Size 2 false pf0_sriov_bar3_type Pf0 Sriov Bar3 Type N/A false pf1_sriov_bar3_size Pf1 Sriov Bar3 Size 2 false pf1_bar0_enabled Pf1 Bar0 Enabled true false pf1_bar0_type Pf1 Bar0 Type Memory false pf1_bar0_64bit Pf1 Bar0 64bit false false pf1_bar0_prefetchable Pf1 Bar0 Prefetchable false false pf1_bar0_scale Pf1 Bar0 Scale Kilobytes false pf1_bar0_size Pf1 Bar0 Size 64 false pf1_bar1_enabled Pf1 Bar1 Enabled false false pf1_bar1_type Pf1 Bar1 Type N/A false pf1_bar1_64bit Pf1 Bar1 64bit false false pf1_bar1_prefetchable Pf1 Bar1 Prefetchable false false pf1_bar1_scale Pf1 Bar1 Scale Kilobytes false pf1_bar1_size Pf1 Bar1 Size 128 false pf1_sriov_bar4_enabled Pf1 Sriov Bar4 Enabled false false pf0_sriov_bar4_type Pf0 Sriov Bar4 Type N/A false pf1_sriov_bar4_64bit Pf1 Sriov Bar4 64bit false false pf1_sriov_bar2_prefetchable Pf1 Sriov Bar2 Prefetchable false false pf0_sriov_cap_ver Pf0 Sriov Cap Ver 1 pf1_sriov_bar4_size Pf1 Sriov Bar4 Size 2 false pf1_msi_enabled Pf1 Msi Enabled false false pf0_sriov_bar5_scale Pf0 Sriov Bar5 Scale Kilobytes false pf0_sriov_bar5_type Pf0 Sriov Bar5 Type N/A false ext_pcie_cfg_space_enabled Ext Pcie Cfg Space Enabled false legacy_ext_pcie_cfg_space_enabled Legacy Ext Pcie Cfg Space Enabled false ext_xvc_vsec_enable Enable to add the PCIe XVC-VSEC to the Examlpe Design false false acs_ext_cap_enable ACS Ext Capability false pf1_sriov_bar4_scale Pf1 Sriov Bar4 Scale Kilobytes false pf1_sriov_bar5_size Pf1 Sriov Bar5 Size 2 false pf0_ari_enabled Pf0 Ari Enabled false perf_level Perf Level Extreme pf0_class_code_base Pf0 Class Code Base 07 axisten_if_width Axisten If Width 256_bit pf0_sriov_bar4_enabled Pf0 Sriov Bar4 Enabled false pf1_sriov_bar0_type Pf1 Sriov Bar0 Type Memory false pf1_bar3_size Pf1 Bar3 Size 128 false pf0_sriov_bar4_prefetchable Pf0 Sriov Bar4 Prefetchable false false pf0_aer_enabled Pf0 Aer Enabled true pf0_dsn_enabled Pf0 Dsn Enabled false pf1_sriov_bar1_type Pf1 Sriov Bar1 Type N/A false pf0_sriov_bar0_64bit Pf0 Sriov Bar0 64bit false pf1_bar4_size Pf1 Bar4 Size 128 false pf0_msi_enabled Pf0 Msi Enabled true pf1_sriov_bar5_enabled Pf1 Sriov Bar5 Enabled false false pf1_sriov_bar2_type Pf1 Sriov Bar2 Type N/A false pf0_msix_enabled Pf0 Msix Enabled false pf1_bar5_size Pf1 Bar5 Size 128 false pf1_bar4_prefetchable Pf1 Bar4 Prefetchable false false pf0_sriov_bar0_scale Pf0 Sriov Bar0 Scale Kilobytes pf0_sriov_bar1_prefetchable Pf0 Sriov Bar1 Prefetchable false false pf1_sriov_bar3_type Pf1 Sriov Bar3 Type N/A false pf2_sriov_bar0_scale Pf2 Sriov Bar0 Scale Kilobytes false pf2_expansion_rom_enabled Pf2 Expansion Rom Enabled false false pf2_sriov_bar0_prefetchable Pf2 Sriov Bar0 Prefetchable false false pf2_bar5_type Pf2 Bar5 Type N/A false pf2_sriov_bar1_enabled Pf2 Sriov Bar1 Enabled false false pf2_class_code_interface Pf2 Class Code Interface 00 pf2_msix_enabled Pf2 Msix Enabled false pf2_bar5_prefetchable Pf2 Bar5 Prefetchable false pf2_sriov_bar1_64bit Pf2 Sriov Bar1 64bit false false pf2_bar3_64bit Pf2 Bar3 64bit false false pf2_bar3_enabled Pf2 Bar3 Enabled false false pf2_sriov_bar1_scale Pf2 Sriov Bar1 Scale Kilobytes false pf2_bar3_scale Pf2 Bar3 Scale Kilobytes false pf2_sriov_bar4_prefetchable Pf2 Sriov Bar4 Prefetchable false false pf2_sriov_bar2_enabled Pf2 Sriov Bar2 Enabled false false pf2_sriov_bar2_64bit Pf2 Sriov Bar2 64bit false false pf2_bar4_64bit Pf2 Bar4 64bit false false pf2_bar4_enabled Pf2 Bar4 Enabled false false pf2_sriov_bar1_prefetchable Pf2 Sriov Bar1 Prefetchable false false pf2_sriov_bar2_scale Pf2 Sriov Bar2 Scale Kilobytes false pf2_bar4_scale Pf2 Bar4 Scale Kilobytes false pf2_expansion_rom_scale Pf2 Expansion Rom Scale Kilobytes false pf2_expansion_rom_size Pf2 Expansion Rom Size 2 false pf2_sriov_bar3_enabled Pf2 Sriov Bar3 Enabled false false pf2_sriov_bar3_64bit Pf2 Sriov Bar3 64bit false false pf2_base_class_menu Pf2 Base Class Menu Memory_controller pf2_sub_class_interface_menu Pf2 Sub Class Interface Menu Other_memory_controller pf2_bar5_enabled Pf2 Bar5 Enabled false false pf2_bar3_prefetchable Pf2 Bar3 Prefetchable false false pf2_sriov_bar0_size Pf2 Sriov Bar0 Size 2 false pf2_sriov_bar3_scale Pf2 Sriov Bar3 Scale Kilobytes false pf2_bar5_scale Pf2 Bar5 Scale Kilobytes false pf2_class_code_sub Pf2 Class Code Sub 80 pf2_sriov_bar1_size Pf2 Sriov Bar1 Size 2 false pf2_sriov_bar5_prefetchable Pf2 Sriov Bar5 Prefetchable false pf2_sriov_bar2_size Pf2 Sriov Bar2 Size 2 false pf2_sriov_bar3_size Pf2 Sriov Bar3 Size 2 false pf2_bar0_enabled Pf2 Bar0 Enabled true false pf2_bar0_type Pf2 Bar0 Type Memory false pf2_bar0_64bit Pf2 Bar0 64bit false false pf2_bar0_prefetchable Pf2 Bar0 Prefetchable false false pf2_bar0_scale Pf2 Bar0 Scale Kilobytes false pf2_bar0_size Pf2 Bar0 Size 64 false pf2_bar1_enabled Pf2 Bar1 Enabled false false pf2_bar1_type Pf2 Bar1 Type N/A false pf2_bar1_64bit Pf2 Bar1 64bit false false pf2_bar1_prefetchable Pf2 Bar1 Prefetchable false false pf2_bar1_scale Pf2 Bar1 Scale Kilobytes false pf2_bar1_size Pf2 Bar1 Size 128 false pf2_sriov_bar4_enabled Pf2 Sriov Bar4 Enabled false false pf2_sriov_bar4_64bit Pf2 Sriov Bar4 64bit false false pf2_sriov_bar2_prefetchable Pf2 Sriov Bar2 Prefetchable false false pf2_sriov_bar4_size Pf2 Sriov Bar4 Size 2 false pf2_msi_enabled Pf2 Msi Enabled false false pf2_sriov_bar4_scale Pf2 Sriov Bar4 Scale Kilobytes false pf2_sriov_bar5_size Pf2 Sriov Bar5 Size 2 false pf2_sriov_bar0_type Pf2 Sriov Bar0 Type Memory false pf2_bar3_size Pf2 Bar3 Size 128 false pf2_sriov_bar1_type Pf2 Sriov Bar1 Type N/A false pf2_bar4_size Pf2 Bar4 Size 128 false pf2_sriov_bar2_type Pf2 Sriov Bar2 Type N/A false pf2_bar5_size Pf2 Bar5 Size 128 false pf2_bar4_prefetchable Pf2 Bar4 Prefetchable false false pf2_sriov_bar3_type Pf2 Sriov Bar3 Type N/A false pf3_sriov_bar0_scale Pf3 Sriov Bar0 Scale Kilobytes false pf3_expansion_rom_enabled Pf3 Expansion Rom Enabled false false pf3_sriov_bar0_prefetchable Pf3 Sriov Bar0 Prefetchable false false pf3_bar5_type Pf3 Bar5 Type N/A false pf3_sriov_bar1_enabled Pf3 Sriov Bar1 Enabled false false pf3_class_code_interface Pf3 Class Code Interface 00 pf3_msix_enabled Pf3 Msix Enabled false pf3_bar5_prefetchable Pf3 Bar5 Prefetchable false pf3_sriov_bar1_64bit Pf3 Sriov Bar1 64bit false false pf3_bar3_64bit Pf3 Bar3 64bit false false pf3_bar3_enabled Pf3 Bar3 Enabled false false pf3_sriov_bar1_scale Pf3 Sriov Bar1 Scale Kilobytes false pf3_bar3_scale Pf3 Bar3 Scale Kilobytes false pf3_sriov_bar4_prefetchable Pf3 Sriov Bar4 Prefetchable false false pf3_sriov_bar2_enabled Pf3 Sriov Bar2 Enabled false false pf3_sriov_bar2_64bit Pf3 Sriov Bar2 64bit false false pf3_bar4_64bit Pf3 Bar4 64bit false false pf3_bar4_enabled Pf3 Bar4 Enabled false false pf3_sriov_bar1_prefetchable Pf3 Sriov Bar1 Prefetchable false false pf3_sriov_bar2_scale Pf3 Sriov Bar2 Scale Kilobytes false pf3_bar4_scale Pf3 Bar4 Scale Kilobytes false pf3_expansion_rom_scale Pf3 Expansion Rom Scale Kilobytes false pf3_expansion_rom_size Pf3 Expansion Rom Size 2 false pf3_sriov_bar3_enabled Pf3 Sriov Bar3 Enabled false false pf3_sriov_bar3_64bit Pf3 Sriov Bar3 64bit false false pf3_base_class_menu Pf3 Base Class Menu Memory_controller pf3_sub_class_interface_menu Pf3 Sub Class Interface Menu Other_memory_controller pf3_bar5_enabled Pf3 Bar5 Enabled false false pf3_bar3_prefetchable Pf3 Bar3 Prefetchable false false pf3_sriov_bar0_size Pf3 Sriov Bar0 Size 2 false pf3_sriov_bar3_scale Pf3 Sriov Bar3 Scale Kilobytes false pf3_bar5_scale Pf3 Bar5 Scale Kilobytes false pf3_class_code_sub Pf3 Class Code Sub 80 pf3_sriov_bar1_size Pf3 Sriov Bar1 Size 2 false pf3_sriov_bar5_prefetchable Pf3 Sriov Bar5 Prefetchable false pf3_sriov_bar2_size Pf3 Sriov Bar2 Size 2 false pf3_sriov_bar3_size Pf3 Sriov Bar3 Size 2 false pf3_bar0_enabled Pf3 Bar0 Enabled true false pf3_bar0_type Pf3 Bar0 Type Memory false pf3_bar0_64bit Pf3 Bar0 64bit false false pf3_bar0_prefetchable Pf3 Bar0 Prefetchable false false pf3_bar0_scale Pf3 Bar0 Scale Kilobytes false pf3_bar0_size Pf3 Bar0 Size 64 false pf3_bar1_enabled Pf3 Bar1 Enabled false false pf3_bar1_type Pf3 Bar1 Type N/A false pf3_bar1_64bit Pf3 Bar1 64bit false false pf3_bar1_prefetchable Pf3 Bar1 Prefetchable false false pf3_bar1_scale Pf3 Bar1 Scale Kilobytes false pf3_bar1_size Pf3 Bar1 Size 128 false pf3_sriov_bar4_enabled Pf3 Sriov Bar4 Enabled false false pf3_sriov_bar4_64bit Pf3 Sriov Bar4 64bit false false pf3_sriov_bar2_prefetchable Pf3 Sriov Bar2 Prefetchable false false pf3_sriov_bar4_size Pf3 Sriov Bar4 Size 2 false pf3_msi_enabled Pf3 Msi Enabled false false pf3_sriov_bar4_scale Pf3 Sriov Bar4 Scale Kilobytes false pf3_sriov_bar5_size Pf3 Sriov Bar5 Size 2 false pf3_sriov_bar0_type Pf3 Sriov Bar0 Type Memory false pf3_bar3_size Pf3 Bar3 Size 128 false pf3_sriov_bar1_type Pf3 Sriov Bar1 Type N/A false pf3_bar4_size Pf3 Bar4 Size 128 false pf3_sriov_bar2_type Pf3 Sriov Bar2 Type N/A false pf3_bar5_size Pf3 Bar5 Size 128 false pf3_bar4_prefetchable Pf3 Bar4 Prefetchable false false pf3_sriov_bar3_type Pf3 Sriov Bar3 Type N/A false mode_selection Mode Advanced pipe_sim false en_ext_clk false en_msi_per_vec_masking false coreclk_freq CORE CLOCK FREQ 500 true plltype PLL TYPE QPLL1 axisten_freq AXISTEN IF FREQ 250 aspm_support ASPM Support No_ASPM SRIOV_CAP_ENABLE_EXT SRIOV Cap Enable false cfg_fc_if true cfg_ext_if false cfg_status_if true per_func_status_if true cfg_mgmt_if true rcv_msg_if true true cfg_tx_msg_if true cfg_ctl_if true tx_fc_if true en_pcie_drp false en_parity false en_pl_ifc false en_pcie_conf false dis_gt_wizard false bmd_pio_mode false sriov_exd_mode false dbg_checker false false enable_ibert false two_port_switch false two_port_config X8G3 RX_PPM_OFFSET Specify the PPM offset between received data and transmitted data 0 RX_SSC_PPM Specify the spread spectrum clocking modulation in PPM 0 INS_LOSS_NYQ Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB 15 ins_loss_profile Add-in_Card true enable_gen4 true en_transceiver_status_ports false true Shared_Logic 1 gtwiz_in_core 1 gtcom_in_core 2 dedicate_perst false sys_reset_polarity ACTIVE_LOW mcap_enablement MCAP Enable None mcap_fpga_bitstream_version MCAP Bitstream Version Register Value 00000000 false enable_code 0000 en_ext_ch_gt_drp false ext_startup_primitive false en_gt_selection false select_quad GTY_Quad_227 false copy_pf0 true copy_sriov_pf0 true cfg_pm_if true pcie_id_if FALSE PL_DISABLE_LANE_REVERSAL true MSI_X_OPTIONS None completer_model false en_dbg_descramble false enable_jtag_dbg false true enable_ltssm_dbg false true tl_credits_cd 15 tl_credits_ch 15 set_finite_credit false gen4_eieos_0s7 true vu9p_board false PHY_LP_TXPRESET 4 SYS_RST_N_BOARD_INTERFACE Custom PCIE_BOARD_INTERFACE Custom gt_drp_clk_src GT DRP Clk Source Internal free_run_freq Free Run Freq 100_MHz en_l23_entry false aws_mode_value aws mode value 0 enable_ccix FALSE enable_dvsec FALSE X1_CH_EN X1Y15 X2_CH_EN X1Y15 X1Y14 X4_CH_EN X1Y15 X1Y14 X1Y13 X1Y12 X8_CH_EN X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 XS_CH_EN X1Y15 X1Y14 X1Y13 X1Y12 X1Y11 X1Y10 X1Y9 X1Y8 X1Y7 X1Y6 X1Y5 X1Y4 X1Y3 X1Y2 X1Y1 X1Y0 GT_TYPE GTY TX_RX_MASTER_CHANNEL X1Y15 ext_sys_clk_bufg false axisten_if_enable_msg_route 20000 true enable_more_clk false disable_bram_pipeline false disable_eq_synchronizer false axisten_if_enable_msg_route_override true enable_auto_rxeq False pf0_ats_enabled Pf0 Ats Enabled false three_port_switch Three Port Switch Enable false pf0_pri_enabled Pf0 Pri Enabled false gen_pipe_debug false enable_mark_debug false enable_multipf_aer false master_cal_only false rbar_enable false pf0_rbar_num Number of Resizable BARs for PF0 1 pf1_rbar_num Number of Resizable BARs for PF1 1 pf2_rbar_num Number of Resizable BARs for PF2 1 pf3_rbar_num Number of Resizable BARs for PF3 1 pf0_bar0_index PF0 BAR0 index 0 pf0_bar1_index PF0 BAR1 index 7 pf0_bar2_index PF0 BAR2 index 7 pf0_bar3_index PF0 BAR3 index 7 pf0_bar4_index PF0 BAR4 index 7 pf0_bar5_index PF0 BAR5 index 7 pf1_bar0_index PF0 BAR0 index 0 pf1_bar1_index PF1 BAR1 index 7 pf1_bar2_index PF1 BAR2 index 7 pf1_bar3_index PF1 BAR3 index 7 pf1_bar4_index PF1 BAR4 index 7 pf1_bar5_index PF1 BAR5 index 7 pf2_bar0_index PF2 BAR0 index 0 pf2_bar1_index PF2 BAR1 index 7 pf2_bar2_index PF2 BAR2 index 7 pf2_bar3_index PF2 BAR3 index 7 pf2_bar4_index PF2 BAR4 index 7 pf2_bar5_index PF2 BAR5 index 7 pf3_bar0_index PF3 BAR0 index 0 pf3_bar1_index PF3 BAR1 index 7 pf3_bar2_index PF3 BAR2 index 7 pf3_bar3_index PF3 BAR3 index 7 pf3_bar4_index PF3 BAR4 index 7 pf3_bar5_index PF3 BAR5 index 7 pf0_rbar_cap_bar0 PF0 RBAR CAP BAR0 0x00000000fff0 pf0_rbar_cap_bar1 PF0 RBAR CAP BAR1 0x000000000000 pf0_rbar_cap_bar2 PF0 RBAR CAP BAR2 0x000000000000 pf0_rbar_cap_bar3 PF0 RBAR CAP BAR3 0x000000000000 pf0_rbar_cap_bar4 PF0 RBAR CAP BAR4 0x000000000000 pf0_rbar_cap_bar5 PF0 RBAR CAP BAR5 0x000000000000 pf1_rbar_cap_bar0 PF1 RBAR CAP BAR0 0x00000000fff0 pf1_rbar_cap_bar1 PF1 RBAR CAP BAR1 0x000000000000 pf1_rbar_cap_bar2 PF1 RBAR CAP BAR2 0x000000000000 pf1_rbar_cap_bar3 PF1 RBAR CAP BAR3 0x000000000000 pf1_rbar_cap_bar4 PF1 RBAR CAP BAR4 0x000000000000 pf1_rbar_cap_bar5 PF1 RBAR CAP BAR5 0x000000000000 pf2_rbar_cap_bar0 PF2 RBAR CAP BAR0 0x00000000fff0 pf2_rbar_cap_bar1 PF2 RBAR CAP BAR1 0x000000000000 pf2_rbar_cap_bar2 PF2 RBAR CAP BAR2 0x000000000000 pf2_rbar_cap_bar3 PF2 RBAR CAP BAR3 0x000000000000 pf2_rbar_cap_bar4 PF2 RBAR CAP BAR4 0x000000000000 pf2_rbar_cap_bar5 PF2 RBAR CAP BAR5 0x000000000000 pf3_rbar_cap_bar0 PF3 RBAR CAP BAR0 0x00000000fff0 pf3_rbar_cap_bar1 PF3 RBAR CAP BAR1 0x000000000000 pf3_rbar_cap_bar2 PF3 RBAR CAP BAR2 0x000000000000 pf3_rbar_cap_bar3 PF3 RBAR CAP BAR3 0x000000000000 pf3_rbar_cap_bar4 PF3 RBAR CAP BAR4 0x000000000000 pf3_rbar_cap_bar5 PF3 RBAR CAP BAR5 0x000000000000 enable_multi_pcie false msix_type MSI-X Type HARD VFG0_MSIX_CAP_PBA_OFFSET vfg0 Msix Cap Pba Offset 00000000 VFG1_MSIX_CAP_PBA_OFFSET vfg1 Msix Cap Pba Offset 00000000 VFG2_MSIX_CAP_PBA_OFFSET vfg2 Msix Cap Pba Offset 00000000 VFG3_MSIX_CAP_PBA_OFFSET vfg3 Msix Cap Pba Offset 00000000 VFG0_MSIX_CAP_TABLE_OFFSET vfg0 Msix Cap table Offset 00000000 VFG1_MSIX_CAP_TABLE_OFFSET vfg1 Msix Cap table Offset 00000000 VFG2_MSIX_CAP_TABLE_OFFSET vfg2 Msix Cap table Offset 00000000 VFG3_MSIX_CAP_TABLE_OFFSET vfg3 Msix Cap table Offset 00000000 VFG0_MSIX_CAP_TABLE_SIZE vfg0 Msix Cap Table Size 0 VFG1_MSIX_CAP_TABLE_SIZE vfg1 Msix Cap Table Size 0 VFG2_MSIX_CAP_TABLE_SIZE vfg2 Msix Cap Table Size 0 VFG3_MSIX_CAP_TABLE_SIZE vfg3 Msix Cap Table Size 0 disable_gt_loc Disable GT loc constraint delivery false use_standard_interfaces use standard interfaces for IPI design false dma_2rp Truncate ports for 2RP DMA design false disable_user_clock_root true qdma_tph_msix_brams_dis false double_quad false enable_epyc_chipset_fix false MASTER_GT GTHE4_CHANNEL_X49Y99 enable_msix_32vec false broadcom_sbr_wa false user_interface_signals false link_training_signals false transmit_fc_interface false config_fc_interface false config_status_interface false config_mgmt_interface false rx_mesg_interface false config_tx_mesg_interface false config_interface false false config_ctrl_interface false config_pwr_mgmt_interface false interrupt_interface false descrambler_pipe_debug_signals false false descrambler_user_interface_signals false exdes_simulation_tab false tl_tx_mux_strict_priority false UltraScale+ Integrated Block (PCIE4C) for PCI Express XPM_CDC XPM_FIFO XPM_MEMORY 10 2020.2