xilinx.com BlockDiagram bd_9f2c 1.00.a isTop true IO TRACE CLK.CLK Clk Clock CLK Clk FREQ_HZ 100000000 PHASE 0.000 ASSOCIATED_ASYNC_RESET Reset RST.RESET Reset Reset RST Reset POLARITY ACTIVE_HIGH BlockDiagram :vivado.xilinx.com: Clk in Reset in xilinx.com BlockDiagram bd_9f2c_imp 1.00.a microblaze_I bd_9f2c_microblaze_I_0 17 mb_microblaze_0 0 1 1 0 1 1 1 0 3 0 0 rst_0 bd_9f2c_rst_0_0 ilmb bd_9f2c_ilmb_0 2 dlmb bd_9f2c_dlmb_0 3 dlmb_cntlr bd_9f2c_dlmb_cntlr_0 0x0000000000000000 0x000000000000FFFF 0x00000000C0010000 ilmb_cntlr bd_9f2c_ilmb_cntlr_0 0x0000000000000000 0x000000000000FFFF 0x0000000080010000 lmb_bram_I bd_9f2c_lmb_bram_I_0 True_Dual_Port_RAM second_dlmb_cntlr bd_9f2c_second_dlmb_cntlr_0 0x0000000000010000 0x0000000000017FFF 0x00000000C0010000 second_ilmb_cntlr bd_9f2c_second_ilmb_cntlr_0 0x0000000000010000 0x0000000000017FFF 0x0000000080010000 second_lmb_bram_I bd_9f2c_second_lmb_bram_I_0 True_Dual_Port_RAM iomodule_0 bd_9f2c_iomodule_0_0 iomodule 0x0000000080000000 0x000000008000FFFF 0x00000000C0000000 1 0x00000000C0000000 0x00000000FFFFFFFF 0x00000000C0000000 1 1 17 ilmb dlmb ilmb_sl_0 dlmb_sl_0 dlmb_sl_1 ilmb_port dlmb_port ilmb_sl_1 dlmb_sl_2 ilmb_port_2 dlmb_port_2 Clk2 Reset MB_Reset LMB_Rst2 IO_Rst xilinx.com Addressing/microblaze_I microblaze 10.0 DLMB ILMB Data 4G 32 SEG_dlmb_cntlr_Mem /dlmb_cntlr/SLMB/Mem 0x00000000 64K SEG_iomodule_0_IO /iomodule_0/SLMB/IO 0xC0000000 1G SEG_iomodule_0_Reg /iomodule_0/SLMB/Reg 0x80000000 64K SEG_second_dlmb_cntlr_Mem /second_dlmb_cntlr/SLMB/Mem 0x00010000 32K Instruction 4G 32 SEG_ilmb_cntlr_Mem /ilmb_cntlr/SLMB/Mem 0x00000000 64K SEG_second_ilmb_cntlr_Mem /second_ilmb_cntlr/SLMB/Mem 0x00010000 32K