xilinx.com customized_ip xdma_pcie3_ip 1.0 m_axis_cq m_axis_cq The Completer Request interface is used to transmit Completion TLP's to the Client Application TDATA m_axis_cq_tdata TKEEP m_axis_cq_tkeep TLAST m_axis_cq_tlast TREADY m_axis_cq_tready TUSER m_axis_cq_tuser TVALID m_axis_cq_tvalid TDATA_NUM_BYTES 32 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 85 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none s_axis_cc s_axis_cc The Completer Completion Interface is used to transmit Completion TLP's TDATA s_axis_cc_tdata TKEEP s_axis_cc_tkeep TLAST s_axis_cc_tlast TREADY s_axis_cc_tready TUSER s_axis_cc_tuser TVALID s_axis_cc_tvalid TDATA_NUM_BYTES 32 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 33 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none s_axis_rq s_axis_rq The Requestor Request interface received requests TLP's from the Client Application TDATA s_axis_rq_tdata TKEEP s_axis_rq_tkeep TLAST s_axis_rq_tlast TREADY s_axis_rq_tready TUSER s_axis_rq_tuser TVALID s_axis_rq_tvalid TDATA_NUM_BYTES 32 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 60 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none m_axis_rc m_axis_rc The Requestor Completer interface transmits completions to the client application TDATA m_axis_rc_tdata TKEEP m_axis_rc_tkeep TLAST m_axis_rc_tlast TREADY m_axis_rc_tready TUSER m_axis_rc_tuser TVALID m_axis_rc_tvalid TDATA_NUM_BYTES 32 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 75 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none pcie_7x_mgt pcie_7x_mgt PCIExpress Serial Link Interface rxn pci_exp_rxn rxp pci_exp_rxp txn pci_exp_txn txp pci_exp_txp pcie_cfg_fc pcie_cfg_fc Configuration Flow Control INTERFACE CPLD cfg_fc_cpld CPLH cfg_fc_cplh NPD cfg_fc_npd NPH cfg_fc_nph PD cfg_fc_pd PH cfg_fc_ph SEL cfg_fc_sel true pcie_cfg_mgmt pcie_cfg_mgmt PCIE Configuration Management Interface ADDR cfg_mgmt_addr BYTE_EN cfg_mgmt_byte_enable READ_DATA cfg_mgmt_read_data READ_EN cfg_mgmt_read READ_WRITE_DONE cfg_mgmt_read_write_done TYPE1_CFG_REG_ACCESS cfg_mgmt_type1_cfg_reg_access WRITE_DATA cfg_mgmt_write_data WRITE_EN cfg_mgmt_write true pcie3_cfg_msi pcie3_us_cfg_msi PCIE MSI interrupt attr cfg_interrupt_msi_attr data cfg_interrupt_msi_data enable cfg_interrupt_msi_enable fail cfg_interrupt_msi_fail function_number cfg_interrupt_msi_function_number int_vector cfg_interrupt_msi_int mask_update cfg_interrupt_msi_mask_update mmenable cfg_interrupt_msi_mmenable pending_status cfg_interrupt_msi_pending_status pending_status_data_enable cfg_interrupt_msi_pending_status_data_enable pending_status_function_num cfg_interrupt_msi_pending_status_function_num select cfg_interrupt_msi_select sent cfg_interrupt_msi_sent tph_present cfg_interrupt_msi_tph_present tph_st_tag cfg_interrupt_msi_tph_st_tag tph_type cfg_interrupt_msi_tph_type vf_enable cfg_interrupt_msi_vf_enable true pcie3_cfg_msix pcie3_us_cfg_msix PCIE MSIx Interrupt address cfg_interrupt_msix_address data cfg_interrupt_msix_data enable cfg_interrupt_msix_enable fail cfg_interrupt_msix_fail int_vector cfg_interrupt_msix_int mask cfg_interrupt_msix_mask sent cfg_interrupt_msix_sent vf_enable cfg_interrupt_msix_vf_enable vf_mask cfg_interrupt_msix_vf_mask false pcie3_cfg_interrupt pcie3_cfg_interrupt PCIE Legacy Interrupt INTx_VECTOR cfg_interrupt_int PENDING cfg_interrupt_pending SENT cfg_interrupt_sent pcie3_cfg_ext pcie3_us_cfg_ext Configuration Extend Interface function_number cfg_ext_function_number read_data cfg_ext_read_data read_data_valid cfg_ext_read_data_valid read_received cfg_ext_read_received register_number cfg_ext_register_number write_byte_enable cfg_ext_write_byte_enable write_data cfg_ext_write_data write_received cfg_ext_write_received false pcie3_cfg_mesg_tx pcie3_us_cfg_mesg_tx Configuration Transmit Message Interface TRANSMIT cfg_msg_transmit TRANSMIT_DATA cfg_msg_transmit_data TRANSMIT_DONE cfg_msg_transmit_done TRANSMIT_TYPE cfg_msg_transmit_type true pcie3_cfg_mesg_rcvd pcie3_us_cfg_mesg_rcvd Configuration Received Message Interface recd cfg_msg_received recd_data cfg_msg_received_data recd_type cfg_msg_received_type true pcie3_cfg_control pcie3_us_cfg_control It allows a broad range of information exchange between user application and the core config_space_enable cfg_config_space_enable ds_bus_number cfg_ds_bus_number ds_device_number cfg_ds_device_number ds_function_number cfg_ds_function_number ds_port_number cfg_ds_port_number dsn cfg_dsn err_cor_in cfg_err_cor_in err_uncor_in cfg_err_uncor_in flr_done cfg_flr_done flr_in_process cfg_flr_in_process hot_reset_in cfg_hot_reset_in hot_reset_out cfg_hot_reset_out link_training_enable cfg_link_training_enable local_error cfg_local_error per_function_number cfg_per_function_number per_function_output_request cfg_per_function_output_request per_function_update_done cfg_per_function_update_done power_state_change_ack cfg_power_state_change_ack power_state_change_interrupt cfg_power_state_change_interrupt req_pm_transition_l23_ready cfg_req_pm_transition_l23_ready subsys_vend_id cfg_subsys_vend_id vf_flr_done cfg_vf_flr_done vf_flr_in_process cfg_vf_flr_in_process true pcie3_per_func_status pcie3_us_per_func_status Per Function Status Interface STATUS_CONTROL cfg_per_func_status_control STATUS_DATA cfg_per_func_status_data true pcie3_user_tph pcie3_us_user_tph PCIE TPH Interface function_num user_tph_function_num stt_address user_tph_stt_address stt_read_data user_tph_stt_read_data stt_read_data_valid user_tph_stt_read_data_valid stt_read_enable user_tph_stt_read_enable false pcie3_cfg_status pcie3_us_cfg_status Configuration Status Interface cq_np_req pcie_cq_np_req cq_np_req_count pcie_cq_np_req_count current_speed cfg_current_speed dpa_substate_change cfg_dpa_substate_change err_cor_out cfg_err_cor_out err_fatal_out cfg_err_fatal_out err_nonfatal_out cfg_err_nonfatal_out function_power_state cfg_function_power_state function_status cfg_function_status link_power_state cfg_link_power_state ltr_enable cfg_ltr_enable ltssm_state cfg_ltssm_state max_payload cfg_max_payload max_read_req cfg_max_read_req negotiated_width cfg_negotiated_width obff_enable cfg_obff_enable phy_link_down cfg_phy_link_down phy_link_status cfg_phy_link_status pl_status_change cfg_pl_status_change rcb_status cfg_rcb_status rq_seq_num pcie_rq_seq_num rq_seq_num_vld pcie_rq_seq_num_vld rq_tag pcie_rq_tag rq_tag_av pcie_rq_tag_av rq_tag_vld pcie_rq_tag_vld tfc_npd_av pcie_tfc_npd_av tfc_nph_av pcie_tfc_nph_av tph_requester_enable cfg_tph_requester_enable tph_st_mode cfg_tph_st_mode vf_power_state cfg_vf_power_state vf_status cfg_vf_status vf_tph_requester_enable cfg_vf_tph_requester_enable vf_tph_st_mode cfg_vf_tph_st_mode true pcie3_transmit_fc pcie3_us_transmit_fc Transmit Flow Control Interfce npd_av pcie_tfc_npd_av nph_av pcie_tfc_nph_av true pcie3_us_drp pcie3_us_drp PCIE DRP Interface DADDR drp_addr DEN drp_en DI drp_di DO drp_do DRDY drp_rdy DWE drp_we false CLK.sys_clk CLK.sys_clk sys_clk interface CLK sys_clk FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none CLK.sys_clk_gt CLK.sys_clk_gt sys_clk_gt interface CLK sys_clk_gt FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none RST.sys_rst RST.sys_rst sys_rst interface RST sys_reset POLARITY ACTIVE_LOW none CLK.user_clk CLK.user_clk user_clk interface CLK user_clk ASSOCIATED_BUSIF m_axis_cq:s_axis_cc:s_axis_rq:m_axis_rc FREQ_HZ 125000000 ASSOCIATED_RESET user_reset PHASE 0.000 none CLK_DOMAIN none RST.user_reset RST.user_reset user_reset interface RST user_reset POLARITY ACTIVE_HIGH pcie3_pl pcie3_pl Physical Layer Interface eq_in_progress pl_eq_in_progress eq_phase pl_eq_phase eq_reset_eieos_count pl_eq_reset_eieos_count gen2_upstream_prefer_deemph pl_gen2_upstream_prefer_deemph false configure configure req_data conf_req_data req_ready conf_req_ready req_reg_num conf_req_reg_num req_type conf_req_type req_valid conf_req_valid resp_rdata conf_resp_rdata resp_valid conf_resp_valid false cap cap GNT cap_gnt REL cap_rel REQ cap_req false startup startup STARTUP Interface cfgclk startup_cfgclk cfgmclk startup_cfgmclk di startup_di do startup_do dts startup_dts eos startup_eos fcsbo startup_fcsbo fcsbts startup_fcsbts gsr startup_gsr gts startup_gts keyclearb startup_keyclearb pack startup_pack preq startup_preq userdoneo startup_usrdoneo usrcclko startup_usrcclko usrclkts startup_usrcclkts usrdonets startup_usrdonets false pcie3_ext_pipe_rp pcie3_ext_pipe_rp PCIE3 External PIPE Interface COMMANDS_IN common_commands_in COMMANDS_OUT common_commands_out RX_0 pipe_rx_0_sigs RX_1 pipe_rx_1_sigs RX_2 pipe_rx_2_sigs RX_3 pipe_rx_3_sigs RX_4 pipe_rx_4_sigs RX_5 pipe_rx_5_sigs RX_6 pipe_rx_6_sigs RX_7 pipe_rx_7_sigs TX_0 pipe_tx_0_sigs TX_1 pipe_tx_1_sigs TX_2 pipe_tx_2_sigs TX_3 pipe_tx_3_sigs TX_4 pipe_tx_4_sigs TX_5 pipe_tx_5_sigs TX_6 pipe_tx_6_sigs TX_7 pipe_tx_7_sigs false pcie3_ext_pipe_ep pcie3_ext_pipe_ep PCIE3 External PIPE Interface COMMANDS_IN common_commands_out COMMANDS_OUT common_commands_in RX_0 pipe_tx_0_sigs RX_1 pipe_tx_1_sigs RX_2 pipe_tx_2_sigs RX_3 pipe_tx_3_sigs RX_4 pipe_tx_4_sigs RX_5 pipe_tx_5_sigs RX_6 pipe_tx_6_sigs RX_7 pipe_tx_7_sigs TX_0 pipe_rx_0_sigs TX_1 pipe_rx_1_sigs TX_2 pipe_rx_2_sigs TX_3 pipe_rx_3_sigs TX_4 pipe_rx_4_sigs TX_5 pipe_rx_5_sigs TX_6 pipe_rx_6_sigs TX_7 pipe_rx_7_sigs false pcie3_ext_pipe_ep_legacy pcie3_ext_pipe_ep_legacy PCIE3 External PIPE Interface COMMANDS_IN common_commands_out COMMANDS_OUT common_commands_in RX_0 pipe_tx_0_sigs RX_1 pipe_tx_1_sigs RX_2 pipe_tx_2_sigs RX_3 pipe_tx_3_sigs RX_4 pipe_tx_4_sigs RX_5 pipe_tx_5_sigs RX_6 pipe_tx_6_sigs RX_7 pipe_tx_7_sigs TX_0 pipe_rx_0_sigs TX_1 pipe_rx_1_sigs TX_2 pipe_rx_2_sigs TX_3 pipe_rx_3_sigs TX_4 pipe_rx_4_sigs TX_5 pipe_rx_5_sigs TX_6 pipe_rx_6_sigs TX_7 pipe_rx_7_sigs false pcie3_us_ext_shared_logic pcie3_us_ext_shared_logic PCIE3 Ultrascale External Shared Logic Interface exts_qpll1lock_out ext_qpll1lock_out exts_qpll1outclk_out ext_qpll1outclk_out exts_qpll1outrefclk_out ext_qpll1outrefclk_out exts_qpll1pd ext_qpll1pd exts_qpll1rate ext_qpll1rate exts_qpll1refclk ext_qpll1refclk exts_qpll1reset ext_qpll1reset false pcie3_us_int_shared_logic pcie3_us_int_shared_logic PCIE3 Ultrascale Internal Shared Logic Interface ints_qpll1lock_out int_qpll1lock_out ints_qpll1outclk_out int_qpll1outclk_out ints_qpll1outrefclk_out int_qpll1outrefclk_out true pcie_ext_ch_gt pcie_ext_ch_gt channel DRP signals DADDR ext_ch_gt_drpaddr DEN ext_ch_gt_drpen DI ext_ch_gt_drpdi DO ext_ch_gt_drpdo DRDY ext_ch_gt_drprdy DWE ext_ch_gt_drpwe false pcie3_us_gt_if pcie3_us_gt_if GT Interface bufgtce_out bufgtce_out bufgtcemask_out bufgtcemask_out bufgtdiv_out bufgtdiv_out bufgtreset_out bufgtreset_out bufgtrstmask_out bufgtrstmask_out cplllock_out cplllock_out cpllpd_in cpllpd_in cpllreset_in cpllreset_in dmonfiforeset_in dmonfiforeset_in dmonitorclk_in dmonitorclk_in dmonitorout_out dmonitorout_out drpaddr_in drpaddr_in drpclk_in drpclk_in drpdi_in drpdi_in drpdo_out drpdo_out drpen_in drpen_in drprdy_out drprdy_out drpwe_in drpwe_in eyescandataerror_out eyescandataerror_out eyescanreset_in eyescanreset_in gthrxn_in gthrxn_in gthrxp_in gthrxp_in gthtxn_out gthtxn_out gthtxp_out gthtxp_out gtpowergood_out gtpowergood_out gtrefclk0_in gtrefclk0_in gtrefclk01_in gtrefclk01_in gtrxreset_in gtrxreset_in gttxreset_in gttxreset_in gtwiz_reset_rx_done_in gtwiz_reset_rx_done_in gtwiz_reset_tx_done_in gtwiz_reset_tx_done_in gtwiz_userclk_rx_active_in gtwiz_userclk_rx_active_in gtwiz_userclk_tx_active_in gtwiz_userclk_tx_active_in gtwiz_userclk_tx_reset_in gtwiz_userclk_tx_reset_in loopback_in loopback_in pcieeqrxeqadaptdone_in pcieeqrxeqadaptdone_in pcierategen3_out pcierategen3_out pcierateidle_out pcierateidle_out pcierateqpllpd_out pcierateqpllpd_out pcierateqpllreset_out pcierateqpllreset_out pcierstidle_in pcierstidle_in pciersttxsyncstart_in pciersttxsyncstart_in pciesynctxsyncdone_out pciesynctxsyncdone_out pcieusergen3rdy_out pcieusergen3rdy_out pcieuserphystatusrst_out pcieuserphystatusrst_out pcieuserratedone_in pcieuserratedone_in pcieuserratestart_out pcieuserratestart_out pcsrsvdin_in pcsrsvdin_in pcsrsvdout_out pcsrsvdout_out phystatus_out phystatus_out qpll0clk_in qpll0clk_in qpll0refclk_in qpll0refclk_in qpll1clk_in qpll1clk_in qpll1lock_out qpll1lock_out qpll1outclk_out qpll1outclk_out qpll1outrefclk_out qpll1outrefclk_out qpll1pd_in qpll1pd_in qpll1refclk_in qpll1refclk_in qpll1reset_in qpll1reset_in qpllrsvd2_in qpllrsvd2_in qpllrsvd3_in qpllrsvd3_in rx8b10ben_in rx8b10ben_in rxbufreset_in rxbufreset_in rxbufstatus_out rxbufstatus_out rxbyteisaligned_out rxbyteisaligned_out rxbyterealign_out rxbyterealign_out rxcdrhold_in rxcdrhold_in rxcdrlock_out rxcdrlock_out rxclkcorcnt_out rxclkcorcnt_out rxcommadet_out rxcommadet_out rxcommadeten_in rxcommadeten_in rxctrl0_out rxctrl0_out rxctrl1_out rxctrl1_out rxctrl2_out rxctrl2_out rxctrl3_out rxctrl3_out rxdata_out rxdata_out rxdfeagchold_in rxdfeagchold_in rxdfecfokhold_in rxdfecfokhold_in rxdfekhhold_in rxdfekhhold_in rxdfelfhold_in rxdfelfhold_in rxdfetap2hold_in rxdfetap2hold_in rxdfetap3hold_in rxdfetap3hold_in rxdfetap4hold_in rxdfetap4hold_in rxdfetap5hold_in rxdfetap5hold_in rxdfetap6hold_in rxdfetap6hold_in rxdfetap7hold_in rxdfetap7hold_in rxdfetap8hold_in rxdfetap8hold_in rxdfetap9hold_in rxdfetap9hold_in rxdfetap10hold_in rxdfetap10hold_in rxdfetap11hold_in rxdfetap11hold_in rxdfetap12hold_in rxdfetap12hold_in rxdfetap13hold_in rxdfetap13hold_in rxdfetap14hold_in rxdfetap14hold_in rxdfetap15hold_in rxdfetap15hold_in rxdfeuthold_in rxdfeuthold_in rxdfevphold_in rxdfevphold_in rxdlysresetdone_out rxdlysresetdone_out rxelecidle_out rxelecidle_out rxlpmen_in rxlpmen_in rxlpmgchold_in rxlpmgchold_in rxlpmhfhold_in rxlpmhfhold_in rxlpmlfhold_in rxlpmlfhold_in rxlpmoshold_in rxlpmoshold_in rxmcommaalignen_in rxmcommaalignen_in rxoshold_in rxoshold_in rxoutclk_out rxoutclk_out rxpcommaalignen_in rxpcommaalignen_in rxpd_in rxpd_in rxphaligndone_out rxphaligndone_out rxpmaresetdone_out rxpmaresetdone_out rxpolarity_in rxpolarity_in rxprbscntreset_in rxprbscntreset_in rxprbserr_out rxprbserr_out rxprbslocked_out rxprbslocked_out rxprbssel_in rxprbssel_in rxprgdivresetdone_out rxprgdivresetdone_out rxprogdivreset_in rxprogdivreset_in rxrate_in rxrate_in rxratedone_out rxratedone_out rxratemode_in rxratemode_in rxresetdone_out rxresetdone_out rxslide_in rxslide_in rxstatus_out rxstatus_out rxsyncdone_out rxsyncdone_out rxuserrdy_in rxuserrdy_in rxusrclk2_in rxusrclk2_in rxusrclk_in rxusrclk_in rxvalid_out rxvalid_out tx8b10ben_in tx8b10ben_in txctrl0_in txctrl0_in txctrl1_in txctrl1_in txctrl2_in txctrl2_in txdata_in txdata_in txdeemph_in txdeemph_in txdetectrx_in txdetectrx_in txdiffctrl_in txdiffctrl_in txdlybypass_in txdlybypass_in txdlyen_in txdlyen_in txdlyhold_in txdlyhold_in txdlyovrden_in txdlyovrden_in txdlysreset_in txdlysreset_in txdlysresetdone_out txdlysresetdone_out txdlyupdown_in txdlyupdown_in txelecidle_in txelecidle_in txinhibit_in txinhibit_in txmaincursor_in txmaincursor_in txmargin_in txmargin_in txoutclk_out txoutclk_out txoutclksel_in txoutclksel_in txpd_in txpd_in txphalign_in txphalign_in txphaligndone_out txphaligndone_out txphalignen_in txphalignen_in txphdlypd_in txphdlypd_in txphdlyreset_in txphdlyreset_in txphdlytstclk_in txphdlytstclk_in txphinit_in txphinit_in txphinitdone_out txphinitdone_out txphovrden_in txphovrden_in txpmaresetdone_out txpmaresetdone_out txpostcursor_in txpostcursor_in txprbsforceerr_in txprbsforceerr_in txprbssel_in txprbssel_in txprecursor_in txprecursor_in txprgdivresetdone_out txprgdivresetdone_out txprogdivreset_in txprogdivreset_in txrate_in txrate_in txresetdone_out txresetdone_out txswing_in txswing_in txsyncallin_in txsyncallin_in txsyncdone_out txsyncdone_out txsyncin_in txsyncin_in txsyncmode_in txsyncmode_in txsyncout_out txsyncout_out txuserrdy_in txuserrdy_in txusrclk2_in txusrclk2_in txusrclk_in txusrclk_in false transceiver_debug transceiver_debug Transceiver Debug Interface bufgtdiv gt_bufgtdiv cpll_lock gt_cplllock dmonfiforeset gt_dmonfiforeset dmonitorclk gt_dmonitorclk dmonitorout gt_dmonitorout eyescandataerror gt_eyescandataerror gtpowergood gt_gtpowergood loopback gt_loopback pcieuserratedone gt_pcieuserratedone pcieuserratestart gt_pcieuserratestart phystatus gt_phystatus prst_n phy_prst_n qpll_lock gt_qpll1lock rate_idle gt_pcierateidle rrst_n phy_rrst_n rst_fsm phy_rst_fsm rst_idle phy_rst_idle rxbufstatus gt_rxbufstatus rxcdrlock gt_rxcdrlock rxcommadet gt_rxcommadet rxdlysresetdone gt_rxdlysresetdone rxeq_fsm phy_rxeq_fsm rxoutclk gt_rxoutclk rxphaligndone gt_rxphaligndone rxpmaresetdone gt_rxpmaresetdone rxprbscntreset gt_rxprbscntreset rxprbserr gt_rxprbserr rxprbssel gt_rxprbssel rxrecclkout gt_rxrecclkout rxresetdone gt_rxresetdone rxstatus gt_rxstatus rxsyncdone gt_rxsyncdone rxvalid gt_rxvalid txdlysresetdone gt_txdlysresetdone txelecidle gt_txelecidle txeq_ctrl phy_txeq_ctrl txeq_fsm phy_txeq_fsm txeq_preset phy_txeq_preset txinhibit gt_txinhibit txphaligndone gt_txphaligndone txphinitdone gt_txphinitdone txprbsforceerr gt_txprbsforceerr txprbssel gt_txprbssel txresetdone gt_txresetdone false xilinx_elaboratesubcores Elaborate Sub-Cores :vivado.xilinx.com:elaborate.subcores xilinx_elaboratesubcores_view_fileset outputProductCRC 8:b37969dc pci_exp_txn out 7 0 std_logic_vector xilinx_elaboratesubcores pci_exp_txp out 7 0 std_logic_vector xilinx_elaboratesubcores pci_exp_rxn in 7 0 std_logic_vector xilinx_elaboratesubcores 0 pci_exp_rxp in 7 0 std_logic_vector xilinx_elaboratesubcores 0 user_clk out std_logic xilinx_elaboratesubcores user_reset out std_logic xilinx_elaboratesubcores user_lnk_up out std_logic xilinx_elaboratesubcores s_axis_rq_tdata in 255 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_rq_tkeep in 7 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_rq_tlast in std_logic xilinx_elaboratesubcores 0 s_axis_rq_tready out 3 0 std_logic_vector xilinx_elaboratesubcores s_axis_rq_tuser in 59 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_rq_tvalid in std_logic xilinx_elaboratesubcores 0 m_axis_rc_tdata out 255 0 std_logic_vector xilinx_elaboratesubcores m_axis_rc_tkeep out 7 0 std_logic_vector xilinx_elaboratesubcores m_axis_rc_tlast out std_logic xilinx_elaboratesubcores m_axis_rc_tready in std_logic xilinx_elaboratesubcores 0 m_axis_rc_tuser out 74 0 std_logic_vector xilinx_elaboratesubcores m_axis_rc_tvalid out std_logic xilinx_elaboratesubcores m_axis_cq_tdata out 255 0 std_logic_vector xilinx_elaboratesubcores m_axis_cq_tkeep out 7 0 std_logic_vector xilinx_elaboratesubcores m_axis_cq_tlast out std_logic xilinx_elaboratesubcores m_axis_cq_tready in std_logic xilinx_elaboratesubcores 0 m_axis_cq_tuser out 84 0 std_logic_vector xilinx_elaboratesubcores m_axis_cq_tvalid out std_logic xilinx_elaboratesubcores s_axis_cc_tdata in 255 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_cc_tkeep in 7 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_cc_tlast in std_logic xilinx_elaboratesubcores 0 s_axis_cc_tready out 3 0 std_logic_vector xilinx_elaboratesubcores s_axis_cc_tuser in 32 0 std_logic_vector xilinx_elaboratesubcores 0 s_axis_cc_tvalid in std_logic xilinx_elaboratesubcores 0 pcie_rq_seq_num out 3 0 std_logic_vector xilinx_elaboratesubcores true pcie_rq_seq_num_vld out std_logic xilinx_elaboratesubcores true pcie_rq_tag out 5 0 std_logic_vector xilinx_elaboratesubcores true pcie_rq_tag_av out 1 0 std_logic_vector xilinx_elaboratesubcores true pcie_rq_tag_vld out std_logic xilinx_elaboratesubcores true pcie_tfc_nph_av out 1 0 std_logic_vector xilinx_elaboratesubcores true pcie_tfc_npd_av out 1 0 std_logic_vector xilinx_elaboratesubcores true pcie_cq_np_req in std_logic xilinx_elaboratesubcores 1 true pcie_cq_np_req_count out 5 0 std_logic_vector xilinx_elaboratesubcores true cfg_phy_link_down out std_logic xilinx_elaboratesubcores true cfg_phy_link_status out 1 0 std_logic_vector xilinx_elaboratesubcores true cfg_negotiated_width out 3 0 std_logic_vector xilinx_elaboratesubcores true cfg_current_speed out 2 0 std_logic_vector xilinx_elaboratesubcores true cfg_max_payload out 2 0 std_logic_vector xilinx_elaboratesubcores true cfg_max_read_req out 2 0 std_logic_vector xilinx_elaboratesubcores true cfg_function_status out 15 0 std_logic_vector xilinx_elaboratesubcores true cfg_function_power_state out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_vf_status out 15 0 std_logic_vector xilinx_elaboratesubcores true cfg_vf_power_state out 23 0 std_logic_vector xilinx_elaboratesubcores true cfg_link_power_state out 1 0 std_logic_vector xilinx_elaboratesubcores true cfg_mgmt_addr in 18 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_mgmt_write in std_logic xilinx_elaboratesubcores 0 true cfg_mgmt_write_data in 31 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_mgmt_byte_enable in 3 0 std_logic_vector xilinx_elaboratesubcores 0 cfg_mgmt_read in std_logic xilinx_elaboratesubcores 0 true cfg_mgmt_read_data out 31 0 std_logic_vector xilinx_elaboratesubcores true cfg_mgmt_read_write_done out std_logic xilinx_elaboratesubcores true cfg_mgmt_type1_cfg_reg_access in std_logic xilinx_elaboratesubcores 0 true cfg_err_cor_out out std_logic xilinx_elaboratesubcores true cfg_err_nonfatal_out out std_logic xilinx_elaboratesubcores true cfg_err_fatal_out out std_logic xilinx_elaboratesubcores true cfg_local_error out std_logic xilinx_elaboratesubcores true cfg_ltr_enable out std_logic xilinx_elaboratesubcores true cfg_ltssm_state out 5 0 std_logic_vector xilinx_elaboratesubcores true cfg_rcb_status out 3 0 std_logic_vector xilinx_elaboratesubcores true cfg_dpa_substate_change out 3 0 std_logic_vector xilinx_elaboratesubcores true cfg_obff_enable out 1 0 std_logic_vector xilinx_elaboratesubcores true cfg_pl_status_change out std_logic xilinx_elaboratesubcores true cfg_tph_requester_enable out 3 0 std_logic_vector xilinx_elaboratesubcores true cfg_tph_st_mode out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_vf_tph_requester_enable out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_vf_tph_st_mode out 23 0 std_logic_vector xilinx_elaboratesubcores true cfg_msg_received out std_logic xilinx_elaboratesubcores true cfg_msg_received_data out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_msg_received_type out 4 0 std_logic_vector xilinx_elaboratesubcores true cfg_msg_transmit in std_logic xilinx_elaboratesubcores 0 true cfg_msg_transmit_type in 2 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_msg_transmit_data in 31 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_msg_transmit_done out std_logic xilinx_elaboratesubcores true cfg_fc_ph out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_pd out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_nph out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_npd out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_cplh out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_cpld out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_fc_sel in 2 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_per_func_status_control in 2 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_per_func_status_data out 15 0 std_logic_vector xilinx_elaboratesubcores true cfg_per_function_number in 3 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_per_function_output_request in std_logic xilinx_elaboratesubcores 0 true cfg_per_function_update_done out std_logic xilinx_elaboratesubcores true cfg_dsn in 63 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_power_state_change_ack in std_logic xilinx_elaboratesubcores 0 true cfg_power_state_change_interrupt out std_logic xilinx_elaboratesubcores true cfg_err_cor_in in std_logic xilinx_elaboratesubcores 0 true cfg_err_uncor_in in std_logic xilinx_elaboratesubcores 0 true cfg_flr_in_process out 3 0 std_logic_vector xilinx_elaboratesubcores true cfg_flr_done in 3 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_vf_flr_in_process out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_vf_flr_done in 7 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_link_training_enable in std_logic xilinx_elaboratesubcores 1 true cfg_ext_read_received out std_logic xilinx_elaboratesubcores false cfg_ext_write_received out std_logic xilinx_elaboratesubcores false cfg_ext_register_number out 9 0 std_logic_vector xilinx_elaboratesubcores false cfg_ext_function_number out 7 0 std_logic_vector xilinx_elaboratesubcores false cfg_ext_write_data out 31 0 std_logic_vector xilinx_elaboratesubcores false cfg_ext_write_byte_enable out 3 0 std_logic_vector xilinx_elaboratesubcores false cfg_ext_read_data in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false cfg_ext_read_data_valid in std_logic xilinx_elaboratesubcores 0 false cfg_interrupt_int in 3 0 std_logic_vector xilinx_elaboratesubcores 0 cfg_interrupt_pending in 3 0 std_logic_vector xilinx_elaboratesubcores 0 cfg_interrupt_sent out std_logic xilinx_elaboratesubcores cfg_interrupt_msi_enable out 3 0 std_logic_vector xilinx_elaboratesubcores true cfg_interrupt_msi_vf_enable out 7 0 std_logic_vector xilinx_elaboratesubcores true cfg_interrupt_msi_mmenable out 11 0 std_logic_vector xilinx_elaboratesubcores true cfg_interrupt_msi_mask_update out std_logic xilinx_elaboratesubcores true cfg_interrupt_msi_data out 31 0 std_logic_vector xilinx_elaboratesubcores true cfg_interrupt_msi_select in 3 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_int in 31 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_pending_status in 31 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_pending_status_data_enable in std_logic xilinx_elaboratesubcores 0 true cfg_interrupt_msi_pending_status_function_num in 3 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_sent out std_logic xilinx_elaboratesubcores true cfg_interrupt_msi_fail out std_logic xilinx_elaboratesubcores true cfg_interrupt_msi_attr in 2 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_tph_present in std_logic xilinx_elaboratesubcores 0 true cfg_interrupt_msi_tph_type in 1 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_tph_st_tag in 8 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msi_function_number in 3 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_interrupt_msix_enable out 3 0 std_logic_vector xilinx_elaboratesubcores false cfg_interrupt_msix_mask out 3 0 std_logic_vector xilinx_elaboratesubcores false cfg_interrupt_msix_vf_enable out 7 0 std_logic_vector xilinx_elaboratesubcores false cfg_interrupt_msix_vf_mask out 7 0 std_logic_vector xilinx_elaboratesubcores false cfg_interrupt_msix_data in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false cfg_interrupt_msix_address in 63 0 std_logic_vector xilinx_elaboratesubcores 0 false cfg_interrupt_msix_int in std_logic xilinx_elaboratesubcores 0 false cfg_interrupt_msix_sent out std_logic xilinx_elaboratesubcores false cfg_interrupt_msix_fail out std_logic xilinx_elaboratesubcores false cfg_hot_reset_out out std_logic xilinx_elaboratesubcores true cfg_config_space_enable in std_logic xilinx_elaboratesubcores 1 true cfg_req_pm_transition_l23_ready in std_logic xilinx_elaboratesubcores 0 true cfg_hot_reset_in in std_logic xilinx_elaboratesubcores 0 true cfg_ds_port_number in 7 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_ds_bus_number in 7 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_ds_device_number in 4 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_ds_function_number in 2 0 std_logic_vector xilinx_elaboratesubcores 0 true cfg_subsys_vend_id in 15 0 std_logic_vector xilinx_elaboratesubcores 0x10EE true drp_rdy out std_logic xilinx_elaboratesubcores false drp_do out 15 0 std_logic_vector xilinx_elaboratesubcores false drp_clk in std_logic xilinx_elaboratesubcores 1 false drp_en in std_logic xilinx_elaboratesubcores 0 false drp_we in std_logic xilinx_elaboratesubcores 0 false drp_addr in 9 0 std_logic_vector xilinx_elaboratesubcores 0 false drp_di in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false user_tph_stt_address in 4 0 std_logic_vector xilinx_elaboratesubcores 0 false user_tph_function_num in 3 0 std_logic_vector xilinx_elaboratesubcores 0 false user_tph_stt_read_data out 31 0 std_logic_vector xilinx_elaboratesubcores false user_tph_stt_read_data_valid out std_logic xilinx_elaboratesubcores false user_tph_stt_read_enable in std_logic xilinx_elaboratesubcores 0 false sys_clk in std_logic xilinx_elaboratesubcores 0 sys_clk_gt in std_logic xilinx_elaboratesubcores 0 sys_reset in std_logic xilinx_elaboratesubcores 0 conf_req_type in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false conf_req_reg_num in 3 0 std_logic_vector xilinx_elaboratesubcores 0 false conf_req_data in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false conf_req_valid in std_logic xilinx_elaboratesubcores 0 false conf_req_ready out std_logic xilinx_elaboratesubcores false conf_resp_rdata out 31 0 std_logic_vector xilinx_elaboratesubcores false conf_resp_valid out std_logic xilinx_elaboratesubcores false mcap_design_switch out std_logic xilinx_elaboratesubcores false mcap_eos_in in std_logic xilinx_elaboratesubcores 0 false startup_cfgclk out std_logic xilinx_elaboratesubcores false startup_cfgmclk out std_logic xilinx_elaboratesubcores false startup_di out 3 0 std_logic_vector xilinx_elaboratesubcores false startup_eos out std_logic xilinx_elaboratesubcores false startup_preq out std_logic xilinx_elaboratesubcores false startup_do in 3 0 std_logic_vector xilinx_elaboratesubcores 0 false startup_dts in 3 0 std_logic_vector xilinx_elaboratesubcores 0 false startup_fcsbo in std_logic xilinx_elaboratesubcores 0 false startup_fcsbts in std_logic xilinx_elaboratesubcores 0 false startup_gsr in std_logic xilinx_elaboratesubcores 0 false startup_gts in std_logic xilinx_elaboratesubcores 0 false startup_keyclearb in std_logic xilinx_elaboratesubcores 1 false startup_pack in std_logic xilinx_elaboratesubcores 0 false startup_usrcclko in std_logic xilinx_elaboratesubcores 0 false startup_usrcclkts in std_logic xilinx_elaboratesubcores 1 false startup_usrdoneo in std_logic xilinx_elaboratesubcores 0 false startup_usrdonets in std_logic xilinx_elaboratesubcores 1 false cap_req out std_logic xilinx_elaboratesubcores false cap_gnt in std_logic xilinx_elaboratesubcores 1 false cap_rel in std_logic xilinx_elaboratesubcores 0 false pl_eq_reset_eieos_count in std_logic xilinx_elaboratesubcores 0 false pl_gen2_upstream_prefer_deemph in std_logic xilinx_elaboratesubcores 0 false pl_eq_in_progress out std_logic xilinx_elaboratesubcores false pl_eq_phase out 1 0 std_logic_vector xilinx_elaboratesubcores false pcie_perstn1_in in std_logic xilinx_elaboratesubcores 0 true pcie_perstn0_out out std_logic xilinx_elaboratesubcores true pcie_perstn1_out out std_logic xilinx_elaboratesubcores true ext_qpll1refclk out 1 0 std_logic_vector xilinx_elaboratesubcores false ext_qpll1rate out 5 0 std_logic_vector xilinx_elaboratesubcores false ext_qpll1pd out 1 0 std_logic_vector xilinx_elaboratesubcores false ext_qpll1reset out 1 0 std_logic_vector xilinx_elaboratesubcores false ext_qpll1lock_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_qpll1outclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_qpll1outrefclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false int_qpll1lock_out out 1 0 std_logic_vector xilinx_elaboratesubcores true int_qpll1outrefclk_out out 1 0 std_logic_vector xilinx_elaboratesubcores true int_qpll1outclk_out out 1 0 std_logic_vector xilinx_elaboratesubcores true common_commands_in in 25 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_0_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_1_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_2_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_3_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_4_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_5_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_6_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false pipe_rx_7_sigs in 83 0 std_logic_vector xilinx_elaboratesubcores 0 false common_commands_out out 25 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_0_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_1_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_2_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_3_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_4_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_5_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_6_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false pipe_tx_7_sigs out 83 0 std_logic_vector xilinx_elaboratesubcores false gt_pcieuserratedone in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_loopback in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_txprbsforceerr in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_txinhibit in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_txprbssel in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_rxprbssel in 31 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_rxprbscntreset in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_txelecidle out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxpmaresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txphaligndone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txphinitdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_txdlysresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxphaligndone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxdlysresetdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxsyncdone out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_eyescandataerror out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxprbserr out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_dmonfiforeset in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_dmonitorclk in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gt_dmonitorout out 135 0 std_logic_vector xilinx_elaboratesubcores false gt_rxcommadet out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_phystatus out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxvalid out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxcdrlock out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_pcierateidle out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_pcieuserratestart out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_gtpowergood out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_cplllock out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxoutclk out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_rxrecclkout out 7 0 std_logic_vector xilinx_elaboratesubcores false gt_qpll1lock out 1 0 std_logic_vector xilinx_elaboratesubcores false gt_rxstatus out 23 0 std_logic_vector xilinx_elaboratesubcores false gt_rxbufstatus out 23 0 std_logic_vector xilinx_elaboratesubcores false gt_bufgtdiv out 8 0 std_logic_vector xilinx_elaboratesubcores false phy_txeq_ctrl out 15 0 std_logic_vector xilinx_elaboratesubcores false phy_txeq_preset out 31 0 std_logic_vector xilinx_elaboratesubcores false phy_rst_fsm out 3 0 std_logic_vector xilinx_elaboratesubcores false phy_txeq_fsm out 23 0 std_logic_vector xilinx_elaboratesubcores false phy_rxeq_fsm out 23 0 std_logic_vector xilinx_elaboratesubcores false phy_rst_idle out std_logic xilinx_elaboratesubcores false phy_rrst_n out std_logic xilinx_elaboratesubcores false phy_prst_n out std_logic xilinx_elaboratesubcores false ext_ch_gt_drpclk out std_logic xilinx_elaboratesubcores false ext_ch_gt_drpaddr in 71 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_ch_gt_drpen in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_ch_gt_drpdi in 127 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_ch_gt_drpwe in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false ext_ch_gt_drpdo out 127 0 std_logic_vector xilinx_elaboratesubcores false ext_ch_gt_drprdy out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdlysresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxelecidle_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxoutclk_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxphaligndone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxpmaresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxprbserr_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxprbslocked_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxprgdivresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxratedone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxsyncdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxvalid_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txdlysresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txoutclk_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txphaligndone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txphinitdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txpmaresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txprgdivresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txresetdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txsyncout_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false txsyncdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false cplllock_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false eyescandataerror_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gtpowergood_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pcierategen3_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pcierateidle_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pciesynctxsyncdone_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pcieusergen3rdy_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pcieuserphystatusrst_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pcieuserratestart_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false phystatus_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxbyteisaligned_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxbyterealign_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxcdrlock_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false rxcommadet_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gthtxn_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false gthtxp_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false drprdy_out in 7 0 std_logic_vector xilinx_elaboratesubcores 0 false pcierateqpllpd_out in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false pcierateqpllreset_out in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false rxclkcorcnt_out in 15 0 std_logic_vector xilinx_elaboratesubcores 0 false bufgtce_out in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false bufgtcemask_out in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false bufgtreset_out in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false bufgtrstmask_out in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false rxbufstatus_out in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false rxstatus_out in 23 0 std_logic_vector xilinx_elaboratesubcores 0 false rxctrl2_out in 63 0 std_logic_vector xilinx_elaboratesubcores 0 false rxctrl3_out in 63 0 std_logic_vector xilinx_elaboratesubcores 0 false bufgtdiv_out in 71 0 std_logic_vector xilinx_elaboratesubcores 0 false pcsrsvdout_out in 95 0 std_logic_vector xilinx_elaboratesubcores 0 false drpdo_out in 127 0 std_logic_vector xilinx_elaboratesubcores 0 false rxctrl0_out in 127 0 std_logic_vector xilinx_elaboratesubcores 0 false rxctrl1_out in 127 0 std_logic_vector xilinx_elaboratesubcores 0 false dmonitorout_out in 135 0 std_logic_vector xilinx_elaboratesubcores 0 false rxdata_out in 1023 0 std_logic_vector xilinx_elaboratesubcores 0 false gtwiz_reset_rx_done_in out 0 0 std_logic xilinx_elaboratesubcores false gtwiz_reset_tx_done_in out 0 0 std_logic xilinx_elaboratesubcores false gtwiz_userclk_rx_active_in out 0 0 std_logic xilinx_elaboratesubcores false gtwiz_userclk_tx_active_in out 0 0 std_logic xilinx_elaboratesubcores false gtwiz_userclk_tx_reset_in out 0 0 std_logic xilinx_elaboratesubcores false cpllpd_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfeagchold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfecfokhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfelfhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfekhhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap2hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap3hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap4hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap5hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap6hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap7hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap8hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap9hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap10hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap11hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap12hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap13hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap14hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfetap15hold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfeuthold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxdfevphold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxoshold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxlpmgchold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxlpmhfhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxlpmlfhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxlpmoshold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false cpllreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false dmonfiforeset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false dmonitorclk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false drpclk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false drpen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false drpwe_in out 7 0 std_logic_vector xilinx_elaboratesubcores false eyescanreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false gthrxn_in out 7 0 std_logic_vector xilinx_elaboratesubcores false gthrxp_in out 7 0 std_logic_vector xilinx_elaboratesubcores false gtrefclk0_in out 7 0 std_logic_vector xilinx_elaboratesubcores false gtrxreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false gttxreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false pcieeqrxeqadaptdone_in out 7 0 std_logic_vector xilinx_elaboratesubcores false pcierstidle_in out 7 0 std_logic_vector xilinx_elaboratesubcores false pciersttxsyncstart_in out 7 0 std_logic_vector xilinx_elaboratesubcores false pcieuserratedone_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rx8b10ben_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxbufreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxcdrhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxcommadeten_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxlpmen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxmcommaalignen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxpcommaalignen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxpolarity_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxprbscntreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxprogdivreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxratemode_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxslide_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxuserrdy_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxusrclk2_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxusrclk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false tx8b10ben_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdeemph_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdetectrx_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlybypass_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlyen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlyhold_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlyovrden_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlysreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txdlyupdown_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txelecidle_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txinhibit_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphalign_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphalignen_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphdlypd_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphdlyreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphdlytstclk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphinit_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txphovrden_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txprbsforceerr_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txprogdivreset_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txswing_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txsyncallin_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txsyncin_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txsyncmode_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txuserrdy_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txusrclk2_in out 7 0 std_logic_vector xilinx_elaboratesubcores false txusrclk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false rxpd_in out 15 0 std_logic_vector xilinx_elaboratesubcores false txpd_in out 15 0 std_logic_vector xilinx_elaboratesubcores false loopback_in out 23 0 std_logic_vector xilinx_elaboratesubcores false rxrate_in out 23 0 std_logic_vector xilinx_elaboratesubcores false txrate_in out 23 0 std_logic_vector xilinx_elaboratesubcores false txmargin_in out 23 0 std_logic_vector xilinx_elaboratesubcores false txoutclksel_in out 23 0 std_logic_vector xilinx_elaboratesubcores false rxprbssel_in out 31 0 std_logic_vector xilinx_elaboratesubcores false txdiffctrl_in out 31 0 std_logic_vector xilinx_elaboratesubcores false txprbssel_in out 31 0 std_logic_vector xilinx_elaboratesubcores false txprecursor_in out 39 0 std_logic_vector xilinx_elaboratesubcores false txpostcursor_in out 39 0 std_logic_vector xilinx_elaboratesubcores false txmaincursor_in out 55 0 std_logic_vector xilinx_elaboratesubcores false txctrl2_in out 63 0 std_logic_vector xilinx_elaboratesubcores false drpaddr_in out 71 0 std_logic_vector xilinx_elaboratesubcores false drpdi_in out 127 0 std_logic_vector xilinx_elaboratesubcores false pcsrsvdin_in out 127 0 std_logic_vector xilinx_elaboratesubcores false txctrl0_in out 127 0 std_logic_vector xilinx_elaboratesubcores false txctrl1_in out 127 0 std_logic_vector xilinx_elaboratesubcores false txdata_in out 1023 0 std_logic_vector xilinx_elaboratesubcores false qpll0clk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false qpll0refclk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false qpll1clk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false qpll1refclk_in out 7 0 std_logic_vector xilinx_elaboratesubcores false gtrefclk01_in out 1 0 std_logic_vector xilinx_elaboratesubcores false qpll1pd_in out 1 0 std_logic_vector xilinx_elaboratesubcores false qpll1reset_in out 1 0 std_logic_vector xilinx_elaboratesubcores false qpll1lock_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false qpll1outclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false qpll1outrefclk_out in 1 0 std_logic_vector xilinx_elaboratesubcores 0 false qpllrsvd2_in out 9 0 std_logic_vector xilinx_elaboratesubcores false qpllrsvd3_in out 9 0 std_logic_vector xilinx_elaboratesubcores false free_run_clock in std_logic xilinx_elaboratesubcores 0 false phy_rdy_out out std_logic xilinx_elaboratesubcores PL_LINK_CAP_MAX_LINK_SPEED Pl Link Cap Max Link Speed 4 PL_LINK_CAP_MAX_LINK_WIDTH Pl Link Cap Max Link Width 8 USER_CLK_FREQ User Clk Freq 3 CORE_CLK_FREQ Core Clk Freq 2 PLL_TYPE PLL Type 2 PF0_LINK_CAP_ASPM_SUPPORT ASPM Support 0 C_DATA_WIDTH C Data Width 256 REF_CLK_FREQ Ref Clk Freq 0 PCIE_LINK_SPEED Pcie Link Speed 3 KEEP_WIDTH Keep Width 8 ARI_CAP_ENABLE Ari Cap Enable FALSE PF0_ARI_CAP_NEXT_FUNC Pf0 ARI Cap Next Func 0x00 AXISTEN_IF_CC_ALIGNMENT_MODE Axisten If Cc Alignment Mode TRUE AXISTEN_IF_CQ_ALIGNMENT_MODE Axisten If Cq Alignment Mode TRUE AXISTEN_IF_RC_ALIGNMENT_MODE Axisten If Rc Alignment Mode FALSE AXISTEN_IF_RC_STRADDLE Axisten If Rc Straddle TRUE AXISTEN_IF_RQ_ALIGNMENT_MODE Axisten If Rq Alignment Mode FALSE AXISTEN_IF_ENABLE_MSG_ROUTE 0x20000 AXISTEN_IF_ENABLE_RX_MSG_INTFC FALSE PF0_AER_CAP_ECRC_CHECK_CAPABLE Pf0 Aer Cap Ecrc Check Capable FALSE PF0_AER_CAP_ECRC_GEN_CAPABLE Pf0 Aer Cap Ecrc Gen Capable FALSE PF0_AER_CAP_NEXTPTR Pf0 Aer Cap Nextptr 0x300 PF0_ARI_CAP_NEXTPTR Pf0 Ari Cap Nextptr 0x000 VF0_ARI_CAP_NEXTPTR Vf0 Ari Cap Nextptr 0x000 VF1_ARI_CAP_NEXTPTR Vf1 Ari Cap Nextptr 0x000 VF2_ARI_CAP_NEXTPTR Vf2 Ari Cap Nextptr 0x000 VF3_ARI_CAP_NEXTPTR Vf3 Ari Cap Nextptr 0x000 VF4_ARI_CAP_NEXTPTR Vf4 Ari Cap Nextptr 0x000 VF5_ARI_CAP_NEXTPTR Vf5 Ari Cap Nextptr 0x000 PF0_BAR0_APERTURE_SIZE Pf0 Bar0 Aperture Size 0x09 PF0_BAR0_CONTROL Pf0 Bar0 Control 0x4 PF0_BAR1_APERTURE_SIZE Pf0 Bar1 Aperture Size 0x00 PF0_BAR1_CONTROL Pf0 Bar1 Control 0x0 PF0_BAR2_APERTURE_SIZE Pf0 Bar2 Aperture Size 0x00 PF0_BAR2_CONTROL Pf0 Bar2 Control 0x0 PF0_BAR3_APERTURE_SIZE Pf0 Bar3 Aperture Size 0x00 PF0_BAR3_CONTROL Pf0 Bar3 Control 0x0 PF0_BAR4_APERTURE_SIZE Pf0 Bar4 Aperture Size 0x00 PF0_BAR4_CONTROL Pf0 Bar4 Control 0x0 PF0_BAR5_APERTURE_SIZE Pf0 Bar5 Aperture Size 0x00 PF0_BAR5_CONTROL Pf0 Bar5 Control 0x0 PF0_CAPABILITY_POINTER Pf0 Capability Pointer 0x80 PF0_CLASS_CODE Pf0 Class Code 0x070001 PF0_VENDOR_ID Pf0 Vendor Id 0x10EE PF0_DEVICE_ID Pf0 Device Id 0x8038 PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 128b Cas Atomic Completer Support FALSE PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 32b Atomic Completer Support FALSE PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 64b Atomic Completer Support FALSE PF0_DEV_CAP2_LTR_SUPPORT Pf0 Dev Cap2 Ltr Support FALSE PF0_DEV_CAP2_OBFF_SUPPORT Pf0 Dev Cap2 Obff Support 0x0 PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT Pf0 Dev Cap2 Tph Completer Support FALSE PF0_DEV_CAP_EXT_TAG_SUPPORTED Pf0 Dev Cap Ext Tag Supported TRUE PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE Pf0 Dev Cap Function Level Reset Capable FALSE PF0_DEV_CAP_MAX_PAYLOAD_SIZE Pf0 Dev Cap Max Payload Size 0x2 PF0_DPA_CAP_NEXTPTR Pf0 Dpa Cap Nextptr 0x300 PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 Pf0 DPA Cap Sub State Power Allocation0 0x00 PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 Pf0 DPA Cap Sub State Power Allocation1 0x00 PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 Pf0 DPA Cap Sub State Power Allocation2 0x00 PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 Pf0 DPA Cap Sub State Power Allocation3 0x00 PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 Pf0 DPA Cap Sub State Power Allocation4 0x00 PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 Pf0 DPA Cap Sub State Power Allocation5 0x00 PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 Pf0 DPA Cap Sub State Power Allocation6 0x00 PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 Pf0 DPA Cap Sub State Power Allocation7 0x00 PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 Pf1 DPA Cap Sub State Power Allocation0 0x00 PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 Pf1 DPA Cap Sub State Power Allocation1 0x00 PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 Pf1 DPA Cap Sub State Power Allocation2 0x00 PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 Pf1 DPA Cap Sub State Power Allocation3 0x00 PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 Pf1 DPA Cap Sub State Power Allocation4 0x00 PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 Pf1 DPA Cap Sub State Power Allocation5 0x00 PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 Pf1 DPA Cap Sub State Power Allocation6 0x00 PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 Pf1 DPA Cap Sub State Power Allocation7 0x00 PF0_DSN_CAP_NEXTPTR Pf0 Dsn Cap Nextptr 0x300 PF0_EXPANSION_ROM_APERTURE_SIZE Pf0 Expansion Rom Aperture Size 0x00 PF0_EXPANSION_ROM_ENABLE Pf0 Expansion Rom Enable FALSE PF0_INTERRUPT_PIN Pf0 Interrupt Pin 0x1 PF0_LINK_STATUS_SLOT_CLOCK_CONFIG Pf0 Link Status Slot Clock Config TRUE PF0_LTR_CAP_NEXTPTR Pf0 Ltr Cap Nextptr 0x300 PF0_MSIX_CAP_NEXTPTR Pf0 Msix Cap Nextptr 0x00 PF0_MSIX_CAP_PBA_BIR Pf0 Msix Cap Pba Bir 0 PF0_MSIX_CAP_PBA_OFFSET Pf0 Msix Cap Pba Offset 0x00000000 PF0_MSIX_CAP_TABLE_BIR Pf0 Msix Cap Table Bir 0 PF0_MSIX_CAP_TABLE_OFFSET Pf0 Msix Cap Table Offset 0x00000000 PF0_MSIX_CAP_TABLE_SIZE Pf0 Msix Cap Table Size 0x000 PF0_MSI_CAP_MULTIMSGCAP Pf0 Msi Cap Multimsgcap 0 PF0_MSI_CAP_NEXTPTR Pf0 Msi Cap Nextptr 0xC0 PF0_PB_CAP_NEXTPTR Pf0 Pb Cap Nextptr 0x274 PF0_PM_CAP_NEXTPTR Pf0 Pm Cap Nextptr 0x90 PF0_PM_CAP_PMESUPPORT_D0 Pf0 Pm Cap Pmesupport D0 FALSE PF0_PM_CAP_PMESUPPORT_D1 Pf0 Pm Cap Pmesupport D1 FALSE PF0_PM_CAP_PMESUPPORT_D3HOT Pf0 Pm Cap Pmesupport D3hot FALSE PF0_PM_CAP_SUPP_D1_STATE Pf0 Pm Cap Supp D1 State FALSE PF0_RBAR_CAP_ENABLE Pf0 Rbar Cap Enable FALSE PF0_RBAR_CAP_NEXTPTR Pf0 Rbar Cap Nextptr 0x300 PF0_RBAR_CAP_SIZE0 Pf0 Rbar Cap Size0 0x00000 PF0_RBAR_CAP_SIZE1 Pf0 Rbar Cap Size1 0x00000 PF0_RBAR_CAP_SIZE2 Pf0 Rbar Cap Size2 0x00000 PF1_RBAR_CAP_SIZE0 Pf1 Rbar Cap Size0 0x00000 PF1_RBAR_CAP_SIZE1 Pf1 Rbar Cap Size1 0x00000 PF1_RBAR_CAP_SIZE2 Pf1 Rbar Cap Size2 0x00000 PF0_REVISION_ID Pf0 Revision Id 0x00 PF0_SRIOV_BAR0_APERTURE_SIZE Pf0 Sriov Bar0 Aperture Size 0x00 PF0_SRIOV_BAR0_CONTROL Pf0 Sriov Bar0 Control 0x0 PF0_SRIOV_BAR1_APERTURE_SIZE Pf0 Sriov Bar1 Aperture Size 0x00 PF0_SRIOV_BAR1_CONTROL Pf0 Sriov Bar1 Control 0x0 PF0_SRIOV_BAR2_APERTURE_SIZE Pf0 Sriov Bar2 Aperture Size 0x00 PF0_SRIOV_BAR2_CONTROL Pf0 Sriov Bar2 Control 0x0 PF0_SRIOV_BAR3_APERTURE_SIZE Pf0 Sriov Bar3 Aperture Size 0x00 PF0_SRIOV_BAR3_CONTROL Pf0 Sriov Bar3 Control 0x0 PF0_SRIOV_BAR4_APERTURE_SIZE Pf0 Sriov Bar4 Aperture Size 0x00 PF0_SRIOV_BAR4_CONTROL Pf0 Sriov Bar4 Control 0x0 PF0_SRIOV_BAR5_APERTURE_SIZE Pf0 Sriov Bar5 Aperture Size 0x00 PF0_SRIOV_BAR5_CONTROL Pf0 Sriov Bar5 Control 0x0 PF0_SRIOV_CAP_INITIAL_VF Pf0 Sriov Cap Initial Vf 0x0000 PF0_SRIOV_CAP_NEXTPTR Pf0 Sriov Cap Nextptr 0x300 PF0_SRIOV_CAP_TOTAL_VF Pf0 Sriov Cap Total Vf 0x0000 PF0_SRIOV_CAP_VER Pf0 Sriov Cap Ver 0x0 PF0_SRIOV_FIRST_VF_OFFSET Pf0 Sriov First Vf Offset 0x0000 PF0_SRIOV_FUNC_DEP_LINK Pf0 Sriov Func Dep Link 0x0000 PF0_SRIOV_SUPPORTED_PAGE_SIZE Pf0 Sriov Supported Page Size 0x00000553 PF0_SRIOV_VF_DEVICE_ID Pf0 Sriov Vf Device Id 0x0000 PF0_SUBSYSTEM_VENDOR_ID Pf0 Subsystem Vendor Id 0x10EE PF0_SUBSYSTEM_ID Pf0 Subsystem Id 0x0007 PF0_TPHR_CAP_ENABLE Pf0 Tphr Cap Enable FALSE PF0_TPHR_CAP_NEXTPTR Pf0 Tphr Cap Nextptr 0x300 VF0_TPHR_CAP_NEXTPTR Vf0 Tphr Cap Nextptr 0x000 VF1_TPHR_CAP_NEXTPTR Vf1 Tphr Cap Nextptr 0x000 VF2_TPHR_CAP_NEXTPTR Vf2 Tphr Cap Nextptr 0x000 VF3_TPHR_CAP_NEXTPTR Vf3 Tphr Cap Nextptr 0x000 VF4_TPHR_CAP_NEXTPTR Vf4 Tphr Cap Nextptr 0x000 VF5_TPHR_CAP_NEXTPTR Vf5 Tphr Cap Nextptr 0x000 PF0_TPHR_CAP_ST_MODE_SEL Pf0 Tphr Cap St Mode Sel 0x0 PF0_TPHR_CAP_ST_TABLE_LOC Pf0 Tphr Cap St Table Loc 0x0 PF0_TPHR_CAP_ST_TABLE_SIZE Pf0 Tphr Cap St Table Size 0x000 PF0_TPHR_CAP_VER Pf0 Tphr Cap Ver 0x1 PF1_TPHR_CAP_ST_MODE_SEL Pf1 Tphr Cap St Mode Sel 0x0 PF1_TPHR_CAP_ST_TABLE_LOC Pf1 Tphr Cap St Table Loc 0x0 PF1_TPHR_CAP_ST_TABLE_SIZE Pf1 Tphr Cap St Table Size 0x000 PF1_TPHR_CAP_VER Pf1 Tphr Cap Ver 0x1 VF0_TPHR_CAP_ST_MODE_SEL Vf0 Tphr Cap St Mode Sel 0x0 VF0_TPHR_CAP_ST_TABLE_LOC Vf0 Tphr Cap St Table Loc 0x0 VF0_TPHR_CAP_ST_TABLE_SIZE Vf0 Tphr Cap St Table Size 0x000 VF0_TPHR_CAP_VER Vf0 Tphr Cap Ver 0x1 VF1_TPHR_CAP_ST_MODE_SEL Vf1 Tphr Cap St Mode Sel 0x0 VF1_TPHR_CAP_ST_TABLE_LOC Vf1 Tphr Cap St Table Loc 0x0 VF1_TPHR_CAP_ST_TABLE_SIZE Vf1 Tphr Cap St Table Size 0x000 VF1_TPHR_CAP_VER Vf1 Tphr Cap Ver 0x1 VF2_TPHR_CAP_ST_MODE_SEL Vf2 Tphr Cap St Mode Sel 0x0 VF2_TPHR_CAP_ST_TABLE_LOC Vf2 Tphr Cap St Table Loc 0x0 VF2_TPHR_CAP_ST_TABLE_SIZE Vf2 Tphr Cap St Table Size 0x000 VF2_TPHR_CAP_VER Vf2 Tphr Cap Ver 0x1 VF3_TPHR_CAP_ST_MODE_SEL Vf3 Tphr Cap St Mode Sel 0x0 VF3_TPHR_CAP_ST_TABLE_LOC Vf3 Tphr Cap St Table Loc 0x0 VF3_TPHR_CAP_ST_TABLE_SIZE Vf3 Tphr Cap St Table Size 0x000 VF3_TPHR_CAP_VER Vf3 Tphr Cap Ver 0x1 VF4_TPHR_CAP_ST_MODE_SEL Vf4 Tphr Cap St Mode Sel 0x0 VF4_TPHR_CAP_ST_TABLE_LOC Vf4 Tphr Cap St Table Loc 0x0 VF4_TPHR_CAP_ST_TABLE_SIZE Vf4 Tphr Cap St Table Size 0x000 VF4_TPHR_CAP_VER Vf4 Tphr Cap Ver 0x1 VF5_TPHR_CAP_ST_MODE_SEL Vf5 Tphr Cap St Mode Sel 0x0 VF5_TPHR_CAP_ST_TABLE_LOC Vf5 Tphr Cap St Table Loc 0x0 VF5_TPHR_CAP_ST_TABLE_SIZE Vf5 Tphr Cap St Table Size 0x000 VF5_TPHR_CAP_VER Vf5 Tphr Cap Ver 0x1 PF0_TPHR_CAP_DEV_SPECIFIC_MODE Pf0 Tphr Cap Dev Specific Mode TRUE PF0_TPHR_CAP_INT_VEC_MODE Pf0 Tphr Cap Int Vec Mode FALSE PF1_TPHR_CAP_DEV_SPECIFIC_MODE Pf1 Tphr Cap Dev Specific Mode TRUE PF1_TPHR_CAP_INT_VEC_MODE Pf1 Tphr Cap Int Vec Mode FALSE VF0_TPHR_CAP_DEV_SPECIFIC_MODE Vf0 Tphr Cap Dev Specific Mode TRUE VF0_TPHR_CAP_INT_VEC_MODE Vf0 Tphr Cap Int Vec Mode FALSE VF1_TPHR_CAP_DEV_SPECIFIC_MODE Vf1 Tphr Cap Dev Specific Mode TRUE VF1_TPHR_CAP_INT_VEC_MODE Vf1 Tphr Cap Int Vec Mode FALSE VF2_TPHR_CAP_DEV_SPECIFIC_MODE Vf2 Tphr Cap Dev Specific Mode TRUE VF2_TPHR_CAP_INT_VEC_MODE Vf2 Tphr Cap Int Vec Mode FALSE VF3_TPHR_CAP_DEV_SPECIFIC_MODE Vf3 Tphr Cap Dev Specific Mode TRUE VF3_TPHR_CAP_INT_VEC_MODE Vf3 Tphr Cap Int Vec Mode FALSE VF4_TPHR_CAP_DEV_SPECIFIC_MODE Vf4 Tphr Cap Dev Specific Mode TRUE VF4_TPHR_CAP_INT_VEC_MODE Vf4 Tphr Cap Int Vec Mode FALSE VF5_TPHR_CAP_DEV_SPECIFIC_MODE Vf5 Tphr Cap Dev Specific Mode TRUE VF5_TPHR_CAP_INT_VEC_MODE Vf5 Tphr Cap Int Vec Mode FALSE PF0_SECONDARY_PCIE_CAP_NEXTPTR Secondary Pcie Extended Capability Nextptr 0x000 MCAP_CAP_NEXTPTR MCAP Cap Nextptr 0x000 PF0_VC_CAP_NEXTPTR Pf0 Vc Cap Nextptr 0x000 SPARE_WORD1 Secondary Pcie Extended Capability Nextptr 0x00000000 PF1_AER_CAP_ECRC_CHECK_CAPABLE Pf1 Aer Cap Ecrc Check Capable FALSE PF1_AER_CAP_ECRC_GEN_CAPABLE Pf1 Aer Cap Ecrc Gen Capable FALSE PF1_AER_CAP_NEXTPTR Pf1 Aer Cap Nextptr 0x000 PF1_ARI_CAP_NEXTPTR Pf1 Ari Cap Nextptr 0x000 PF1_BAR0_APERTURE_SIZE Pf1 Bar0 Aperture Size 0x00 PF1_BAR0_CONTROL Pf1 Bar0 Control 0x0 PF1_BAR1_APERTURE_SIZE Pf1 Bar1 Aperture Size 0x00 PF1_BAR1_CONTROL Pf1 Bar1 Control 0x0 PF1_BAR2_APERTURE_SIZE Pf1 Bar2 Aperture Size 0x00 PF1_BAR2_CONTROL Pf1 Bar2 Control 0x0 PF1_BAR3_APERTURE_SIZE Pf1 Bar3 Aperture Size 0x00 PF1_BAR3_CONTROL Pf1 Bar3 Control 0x0 PF1_BAR4_APERTURE_SIZE Pf1 Bar4 Aperture Size 0x00 PF1_BAR4_CONTROL Pf1 Bar4 Control 0x0 PF1_BAR5_APERTURE_SIZE Pf1 Bar5 Aperture Size 0x00 PF1_BAR5_CONTROL Pf1 Bar5 Control 0x0 PF1_CAPABILITY_POINTER Pf1 Capability Pointer 0x80 PF1_CLASS_CODE Pf1 Class Code 0x058000 PF1_DEVICE_ID Pf1 Device Id 0x8011 PF1_DEV_CAP_MAX_PAYLOAD_SIZE Pf1 Dev Cap Max Payload Size 0x2 PF1_DPA_CAP_NEXTPTR Pf1 Dpa Cap Nextptr 0x000 PF1_DSN_CAP_NEXTPTR Pf1 Dsn Cap Nextptr 0x000 PF1_EXPANSION_ROM_APERTURE_SIZE Pf1 Expansion Rom Aperture Size 0x00 PF1_EXPANSION_ROM_ENABLE Pf1 Expansion Rom Enable FALSE PF1_INTERRUPT_PIN Pf1 Interrupt Pin 0x0 PF1_MSIX_CAP_NEXTPTR Pf1 Msix Cap Nextptr 0x00 PF1_MSIX_CAP_PBA_BIR Pf1 Msix Cap Pba Bir 0 PF1_MSIX_CAP_PBA_OFFSET Pf1 Msix Cap Pba Offset 0x00000000 PF1_MSIX_CAP_TABLE_BIR Pf1 Msix Cap Table Bir 0 PF1_MSIX_CAP_TABLE_OFFSET Pf1 Msix Cap Table Offset 0x00000000 PF1_MSIX_CAP_TABLE_SIZE Pf1 Msix Cap Table Size 0x000 PF1_MSI_CAP_MULTIMSGCAP Pf1 Msi Cap Multimsgcap 0 PF1_MSI_CAP_NEXTPTR Pf1 Msi Cap Nextptr 0x00 PF1_PB_CAP_NEXTPTR Pf1 Pb Cap Nextptr 0x000 PF1_PM_CAP_NEXTPTR Pf1 Pm Cap Nextptr 0x00 PF1_RBAR_CAP_ENABLE Pf1 Rbar Cap Enable FALSE PF1_RBAR_CAP_NEXTPTR Pf1 Rbar Cap Nextptr 0x000 PF1_REVISION_ID Pf1 Revision Id 0x00 PF1_SRIOV_BAR0_APERTURE_SIZE Pf1 Sriov Bar0 Aperture Size 0x00 PF1_SRIOV_BAR0_CONTROL Pf1 Sriov Bar0 Control 0x0 PF1_SRIOV_BAR1_APERTURE_SIZE Pf1 Sriov Bar1 Aperture Size 0x00 PF1_SRIOV_BAR1_CONTROL Pf1 Sriov Bar1 Control 0x0 PF1_SRIOV_BAR2_APERTURE_SIZE Pf1 Sriov Bar2 Aperture Size 0x00 PF1_SRIOV_BAR2_CONTROL Pf1 Sriov Bar2 Control 0x0 PF1_SRIOV_BAR3_APERTURE_SIZE Pf1 Sriov Bar3 Aperture Size 0x00 PF1_SRIOV_BAR3_CONTROL Pf1 Sriov Bar3 Control 0x0 PF1_SRIOV_BAR4_APERTURE_SIZE Pf1 Sriov Bar4 Aperture Size 0x00 PF1_SRIOV_BAR4_CONTROL Pf1 Sriov Bar4 Control 0x0 PF1_SRIOV_BAR5_APERTURE_SIZE Pf1 Sriov Bar5 Aperture Size 0x00 PF1_SRIOV_BAR5_CONTROL Pf1 Sriov Bar5 Control 0x0 PF1_SRIOV_CAP_INITIAL_VF Pf1 Sriov Cap Initial Vf 0x0000 PF1_SRIOV_CAP_NEXTPTR Pf1 Sriov Cap Nextptr 0x000 PF1_SRIOV_CAP_TOTAL_VF Pf1 Sriov Cap Total Vf 0x0000 PF1_SRIOV_CAP_VER Pf1 Sriov Cap Ver 0x0 PF1_SRIOV_FIRST_VF_OFFSET Pf1 Sriov First Vf Offset 0x0000 PF1_SRIOV_FUNC_DEP_LINK Pf1 Sriov Func Dep Link 0x0001 PF1_SRIOV_SUPPORTED_PAGE_SIZE Pf1 Sriov Supported Page Size 0x00000553 PF1_SRIOV_VF_DEVICE_ID Pf1 Sriov Vf Device Id 0x0000 PF1_SUBSYSTEM_ID Pf1 Subsystem Id 0x0007 PF1_TPHR_CAP_ENABLE Pf1 Tphr Cap Enable FALSE PF1_TPHR_CAP_NEXTPTR Pf1 Tphr Cap Nextptr 0x000 PL_UPSTREAM_FACING Pl Upstream Facing TRUE en_msi_per_vec_masking en msi per vec masking FALSE SRIOV_CAP_ENABLE Sriov Cap Enable FALSE TL_CREDITS_CD Tl Credits Cd 0x000 TL_CREDITS_CH Tl Credits Ch 0x00 TL_CREDITS_NPD Tl Credits Npd 0x028 TL_CREDITS_NPH Tl Credits Nph 0x20 TL_CREDITS_PD Tl Credits Pd 0x198 TL_CREDITS_PH Tl Credits Ph 0x20 TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE Tl Extended Cfg Extend Interface Enable FALSE ACS_EXT_CAP_ENABLE FALSE ACS_CAP_NEXTPTR 0x000 TL_LEGACY_MODE_ENABLE Tl Legacy Mode Enable FALSE TL_PF_ENABLE_REG Tl Pf Enable Reg 0x0 VF0_CAPABILITY_POINTER Vf0 Capability Pointer 0x80 VF0_MSIX_CAP_PBA_BIR Vf0 Msix Cap Pba Bir 0 VF0_MSIX_CAP_PBA_OFFSET Vf0 Msix Cap Pba Offset 0x00000000 VF0_MSIX_CAP_TABLE_BIR Vf0 Msix Cap Table Bir 0 VF0_MSIX_CAP_TABLE_OFFSET Vf0 Msix Cap Table Offset 0x00000000 VF0_MSIX_CAP_TABLE_SIZE Vf0 Msix Cap Table Size 0x000 VF0_MSI_CAP_MULTIMSGCAP Vf0 Msi Cap Multimsgcap 0 VF0_PM_CAP_NEXTPTR Vf0 Pm Cap Nextptr 0x00 VF1_MSIX_CAP_PBA_BIR Vf1 Msix Cap Pba Bir 0 VF1_MSIX_CAP_PBA_OFFSET Vf1 Msix Cap Pba Offset 0x00000000 VF1_MSIX_CAP_TABLE_BIR Vf1 Msix Cap Table Bir 0 VF1_MSIX_CAP_TABLE_OFFSET Vf1 Msix Cap Table Offset 0x00000000 VF1_MSIX_CAP_TABLE_SIZE Vf1 Msix Cap Table Size 0x000 VF1_MSI_CAP_MULTIMSGCAP Vf1 Msi Cap Multimsgcap 0 VF1_PM_CAP_NEXTPTR Vf1 Pm Cap Nextptr 0x00 VF2_MSIX_CAP_PBA_BIR Vf2 Msix Cap Pba Bir 0 VF2_MSIX_CAP_PBA_OFFSET Vf2 Msix Cap Pba Offset 0x00000000 VF2_MSIX_CAP_TABLE_BIR Vf2 Msix Cap Table Bir 0 VF2_MSIX_CAP_TABLE_OFFSET Vf2 Msix Cap Table Offset 0x00000000 VF2_MSIX_CAP_TABLE_SIZE Vf2 Msix Cap Table Size 0x000 VF2_MSI_CAP_MULTIMSGCAP Vf2 Msi Cap Multimsgcap 0 VF2_PM_CAP_NEXTPTR Vf2 Pm Cap Nextptr 0x00 VF3_MSIX_CAP_PBA_BIR Vf3 Msix Cap Pba Bir 0 VF3_MSIX_CAP_PBA_OFFSET Vf3 Msix Cap Pba Offset 0x00000000 VF3_MSIX_CAP_TABLE_BIR Vf3 Msix Cap Table Bir 0 VF3_MSIX_CAP_TABLE_OFFSET Vf3 Msix Cap Table Offset 0x00000000 VF3_MSIX_CAP_TABLE_SIZE Vf3 Msix Cap Table Size 0x000 VF3_MSI_CAP_MULTIMSGCAP Vf3 Msi Cap Multimsgcap 0 VF3_PM_CAP_NEXTPTR Vf3 Pm Cap Nextptr 0x00 VF4_MSIX_CAP_PBA_BIR Vf4 Msix Cap Pba Bir 0 VF4_MSIX_CAP_PBA_OFFSET Vf4 Msix Cap Pba Offset 0x00000000 VF4_MSIX_CAP_TABLE_BIR Vf4 Msix Cap Table Bir 0 VF4_MSIX_CAP_TABLE_OFFSET Vf4 Msix Cap Table Offset 0x00000000 VF4_MSIX_CAP_TABLE_SIZE Vf4 Msix Cap Table Size 0x000 VF4_MSI_CAP_MULTIMSGCAP Vf4 Msi Cap Multimsgcap 0 VF4_PM_CAP_NEXTPTR Vf4 Pm Cap Nextptr 0x00 VF5_MSIX_CAP_PBA_BIR Vf5 Msix Cap Pba Bir 0 VF5_MSIX_CAP_PBA_OFFSET Vf5 Msix Cap Pba Offset 0x00000000 VF5_MSIX_CAP_TABLE_BIR Vf5 Msix Cap Table Bir 0 VF5_MSIX_CAP_TABLE_OFFSET Vf5 Msix Cap Table Offset 0x00000000 VF5_MSIX_CAP_TABLE_SIZE Vf5 Msix Cap Table Size 0x000 VF5_MSI_CAP_MULTIMSGCAP Vf5 Msi Cap Multimsgcap 0 VF5_PM_CAP_NEXTPTR Vf5 Pm Cap Nextptr 0x00 COMPLETION_SPACE Completion Space 16KB gen_x0y0_xdc Generate X0Y0 XDC 1 gen_x0y1_xdc Generate X0Y1 XDC 0 gen_x0y2_xdc Generate X0Y2 XDC 0 gen_x0y3_xdc Generate X0Y3 XDC 0 gen_x0y4_xdc Generate X0Y4 XDC 0 gen_x0y5_xdc Generate X0Y5 XDC 0 xlnx_ref_board Xlnx Ref Board 0 pcie_blk_locn Pcie Blk Locn 0 PIPE_SIM FALSE AXISTEN_IF_ENABLE_CLIENT_TAG TRUE PCIE_USE_MODE PCIE USE MODE 2.0 PCIE_FAST_CONFIG PCIE FAST CONFIG NONE EXT_STARTUP_PRIMITIVE EXT STARTUP PRIMITIVE FALSE PL_INTERFACE PL INTERFACE FALSE PCIE_CONFIGURATION PCIE CONFIGURATION FALSE CFG_STATUS_IF TRUE TX_FC_IF TRUE CFG_EXT_IF FALSE CFG_FC_IF TRUE PER_FUNC_STATUS_IF TRUE CFG_MGMT_IF TRUE RCV_MSG_IF TRUE CFG_TX_MSG_IF TRUE CFG_CTL_IF TRUE MSI_EN TRUE MSIX_EN FALSE PCIE3_DRP FALSE DIS_GT_WIZARD FALSE TRANSCEIVER_CTRL_STATUS_PORTS FALSE SHARED_LOGIC 1 DEDICATE_PERST TRUE SYS_RESET_POLARITY 0 MCAP_ENABLEMENT NONE PHY_LP_TXPRESET Phy Lp Txpreset 4 EXT_CH_GT_DRP FALSE EN_GT_SELECTION FALSE SELECT_QUAD GTH_Quad_225 silicon_revision Silicon Revision Production DEV_PORT_TYPE 0 RX_DETECT Receiver Detect 0 ENABLE_IBERT FALSE DBG_DESCRAMBLE_EN FALSE ENABLE_JTAG_DBG FALSE AXISTEN_IF_CC_PARITY_CHK FALSE AXISTEN_IF_RQ_PARITY_CHK FALSE ENABLE_AUTO_RXEQ FALSE GTWIZ_IN_CORE 1 INS_LOSS_PROFILE Add-in_Card PM_ENABLE_L23_ENTRY FALSE BMD_PIO_MODE FALSE MULT_PF_DES TRUE ENABLE_GT_V1_5 FALSE EXT_XVC_VSEC_ENABLE Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design FALSE choice_list_24b724fb Basic Advanced choice_list_3c2e0592 QPLL1 choice_list_52d29139 Bytes Kilobytes Megabytes Gigabytes choice_list_55451da8 X1 X2 X4 X8 choice_list_6b979ebc 250 choice_list_6f5507b7 None choice_list_7a7dde49 true false choice_list_86c5d341 500 choice_list_8b5e4915 4 5 choice_list_bdd7203f True False choice_list_be0f0e98 X0Y0 X0Y1 X0Y2 X0Y3 choice_list_c15e8c67 1 2 4 8 16 32 64 128 256 512 choice_list_c3d223d9 Memory choice_list_c63ab5b1 0 1 2 3 4 5 6 choice_list_d123c74c Bytes Kilobytes Megabytes choice_list_d85ad257 0 choice_list_dd772e63 Extreme choice_list_ec64e624 N/A choice_list_f1174048 NONE INTA INTB INTC INTD choice_pairs_0b493de9 No_ASPM L1_Supported choice_pairs_0d200523 00_Not_Supported 01_MSI_only choice_pairs_11ed4471 1_vector 2_vectors 4_vectors 8_vectors 16_vectors 32_vectors choice_pairs_12c31cff Chip-to-Chip Add-in_Card Backplane choice_pairs_3c87fcdb 1 0 choice_pairs_3f2631bf 128_bytes 256_bytes 512_bytes 1024_bytes choice_pairs_3fe73c5d BAR_0 0 BAR_1 1 BAR_2 2 BAR_3 3 BAR_4 4 BAR_5 choice_pairs_49d248fb BAR_0 choice_pairs_4b246358 Wireless_controller Satellite_communication_controllers Data_acquisition_and_signal_processing_controllers Intelligent_I/O_controllers Docking_stations Device_was_built_before_Class_Code_definitions_were_finalized Memory_controller Simple_communication_controllers Serial_bus_controllers Encryption/Decryption_controllers Display_controller Multimedia_device Input_devices Mass_storage_controller Processors Device_does_not_fit_in_any_defined_classes Bridge_device Network_controller Base_system_peripherals choice_pairs_503b93ee None DWORD_Aligned Address_Aligned choice_pairs_53749dec 1 0 choice_pairs_649e04ee GTH_Quad_225 GTH_Quad_224 choice_pairs_7156aca5 Default Falling_Edge choice_pairs_7ddd9aec ACTIVE_LOW ACTIVE_HIGH choice_pairs_8b05c234 DWORD_Aligned Address_Aligned choice_pairs_96d05a8d 100_MHz 125_MHz 250_MHz choice_pairs_c1620769 256_bit choice_pairs_c98117c0 RAM Other_memory_controller Flash choice_pairs_d3142f18 None Tandem Tandem_with_Field_Updates PR_over_PCIe choice_pairs_dc66c043 PCI_Express_Endpoint_device Legacy_PCI_Express_Endpoint_device Root_Port_of_PCI_Express_Root_Complex choice_pairs_dd20f238 None Tandem_PROM Tandem_Pcie choice_pairs_e13c2c7f Generic_XT_compatible_serial_controller 16450_compatible_serial_controller Parallel_port IEEE_1284_controller Multiport_serial_controller 16650_compatible_serial_controller IEEE_1284_target_device Hayes_compatible_modem_with_16550_compatible_interface ECP_1.X_compliant_parallel_port 16850_compatible_serial_controller Hayes_compatible_modem_with_16750_compatible_interface Smart_Card Bi_directional_parallel_port Other_communications_device GPIB(IEEE_488.1/2)_controller 16550_compatible_serial_controller Hayes_compatible_modem_with_16450_compatible_interface 16750_compatible_serial_controller Hayes_compatible_modem_with_16650_compatible_interface Generic_modem 16950_compatible_serial_controller choice_pairs_f8a795d6 2.5_GT/s 5.0_GT/s 8.0_GT/s xilinx_elaboratesubcores_view_fileset ip_0/xdma_pcie3_ip_gt.xci xci ip_0/xdma_pcie3_ip_gt.xml xml The Xilinx UltraScale Gen3 Integrated Block for PCI Express (1-lane, 2-lane, 4-lane, and 8-lane) in conjunction with flexible UltraScale architectural features such as integrated GTs (Gigabit Transceivers) and BRAM (Block RAMs) are used to implement a PCI Express Base Specification v3.1 compliant PCI Express devices. device_port_type Device Port Type PCI_Express_Endpoint_device xlnx_ref_board Xlnx Ref Board None true PL_LINK_CAP_MAX_LINK_SPEED Pl Link Cap Max Link Speed 8.0_GT/s PL_LINK_CAP_MAX_LINK_WIDTH Pl Link Cap Max Link Width The Xilinx Ultrascale Series Gen3 Integrated Block for PCI Expressification v3.0 compliant PCI Express Endpoint. X8 REF_CLK_FREQ Ref Clk Freq 100_MHz AXISTEN_IF_RC_STRADDLE Axisten If Rc Straddle true axisten_if_enable_client_tag Enable Client Tag true PF0_AER_CAP_ECRC_CHECK_CAPABLE Pf0 Aer Cap Ecrc Check Capable false PF0_AER_CAP_ECRC_GEN_CAPABLE Pf0 Aer Cap Ecrc Gen Capable false PF0_DEVICE_ID Pf0 Device Id 8038 PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 128b Cas Atomic Completer Support false PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 32b Atomic Completer Support false PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT Pf0 Dev Cap2 64b Atomic Completer Support false PF0_DEV_CAP2_OBFF_SUPPORT Pf0 Dev Cap2 Obff Support 00_Not_Supported PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT Pf0 Dev Cap2 Tph Completer Support false PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE Pf0 Dev Cap Function Level Reset Capable false PF0_INTERRUPT_PIN Pf0 Interrupt Pin INTA PF0_LINK_STATUS_SLOT_CLOCK_CONFIG Pf0 Link Status Slot Clock Config true PF0_MSIX_CAP_PBA_BIR Pf0 Msix Cap Pba Bir BAR_0 PF0_MSIX_CAP_PBA_OFFSET Pf0 Msix Cap Pba Offset 00000000 PF0_MSIX_CAP_TABLE_BIR Pf0 Msix Cap Table Bir BAR_0 PF0_MSIX_CAP_TABLE_OFFSET Pf0 Msix Cap Table Offset 00000000 PF0_MSIX_CAP_TABLE_SIZE Pf0 Msix Cap Table Size 000 PF0_MSI_CAP_MULTIMSGCAP Pf0 Msi Cap Multimsgcap 1_vector PF0_PM_CAP_PMESUPPORT_D1 Pf0 Pm Cap Pmesupport D1 false PF0_PM_CAP_PMESUPPORT_D3HOT Pf0 Pm Cap Pmesupport D3hot false PF0_PM_CAP_SUPP_D1_STATE Pf0 Pm Cap Supp D1 State false PF0_REVISION_ID Pf0 Revision Id 00 PF0_SRIOV_CAP_INITIAL_VF Pf0 Sriov Cap Initial Vf 0 PF0_SRIOV_FIRST_VF_OFFSET Pf0 Sriov First Vf Offset N/A PF0_SRIOV_FUNC_DEP_LINK Pf0 Sriov Func Dep Link 0000 PF0_SRIOV_SUPPORTED_PAGE_SIZE Pf0 Sriov Supported Page Size 00000553 PF0_SRIOV_VF_DEVICE_ID Pf0 Sriov Vf Device Id 0000 PF0_SUBSYSTEM_ID Pf0 Subsystem Id 0007 PF1_AER_CAP_ECRC_CHECK_CAPABLE Pf1 Aer Cap Ecrc Check Capable false PF1_AER_CAP_ECRC_GEN_CAPABLE Pf1 Aer Cap Ecrc Gen Capable false PF1_DEVICE_ID Pf1 Device Id 8011 PF1_INTERRUPT_PIN Pf1 Interrupt Pin NONE PF1_MSIX_CAP_PBA_BIR Pf1 Msix Cap Pba Bir BAR_0 PF1_MSIX_CAP_TABLE_BIR Pf1 Msix Cap Table Bir BAR_0 PF1_MSIX_CAP_TABLE_SIZE Pf1 Msix Cap Table Size 000 PF1_MSIX_CAP_TABLE_OFFSET Pf1 Msix Cap Table Offset 00000000 PF1_MSIX_CAP_PBA_OFFSET Pf1 Msix Cap Pba Offset 00000000 PF1_MSI_CAP_MULTIMSGCAP Pf1 Msi Cap Multimsgcap 1_vector PF1_REVISION_ID Pf1 Revision Id 00 PF1_SRIOV_CAP_INITIAL_VF Pf1 Sriov Cap Initial Vf 0 PF1_SRIOV_CAP_VER Pf1 Sriov Cap Ver 0 PF1_SRIOV_FIRST_VF_OFFSET Pf1 Sriov First Vf Offset N/A PF1_SRIOV_FUNC_DEP_LINK Pf1 Sriov Func Dep Link 0001 PF1_SRIOV_SUPPORTED_PAGE_SIZE Pf1 Sriov Supported Page Size 00000553 PF1_SRIOV_VF_DEVICE_ID Pf1 Sriov Vf Device Id 0000 PF1_SUBSYSTEM_ID Pf1 Subsystem Id 0007 tl_pf0_enable_reg Tl Pf0 Enable Reg true TL_PF_ENABLE_REG Tl Pf Enable Reg false SRIOV_CAP_ENABLE Sriov Cap Enable false VF0_MSIX_CAP_PBA_BIR Vf0 Msix Cap Pba Bir BAR_0 VF0_MSIX_CAP_PBA_OFFSET Vf0 Msix Cap Pba Offset 00000000 VF0_MSIX_CAP_TABLE_BIR Vf0 Msix Cap Table Bir BAR_0 VF0_MSIX_CAP_TABLE_OFFSET Vf0 Msix Cap Table Offset 00000000 VF0_MSIX_CAP_TABLE_SIZE Vf0 Msix Cap Table Size 000 VF0_MSI_CAP_MULTIMSGCAP Vf0 Msi Cap Multimsgcap 1_vector VF1_MSIX_CAP_PBA_BIR Vf1 Msix Cap Pba Bir BAR_0 VF1_MSIX_CAP_PBA_OFFSET Vf1 Msix Cap Pba Offset 00000000 VF1_MSIX_CAP_TABLE_BIR Vf1 Msix Cap Table Bir BAR_0 VF1_MSIX_CAP_TABLE_OFFSET Vf1 Msix Cap Table Offset 00000000 VF1_MSIX_CAP_TABLE_SIZE Vf1 Msix Cap Table Size 000 VF1_MSI_CAP_MULTIMSGCAP Vf1 Msi Cap Multimsgcap 1_vector VF2_MSIX_CAP_PBA_BIR Vf2 Msix Cap Pba Bir BAR_0 VF2_MSIX_CAP_PBA_OFFSET Vf2 Msix Cap Pba Offset 00000000 VF2_MSIX_CAP_TABLE_BIR Vf2 Msix Cap Table Bir BAR_0 VF2_MSIX_CAP_TABLE_OFFSET Vf2 Msix Cap Table Offset 00000000 VF2_MSIX_CAP_TABLE_SIZE Vf2 Msix Cap Table Size 000 VF2_MSI_CAP_MULTIMSGCAP Vf2 Msi Cap Multimsgcap 1_vector VF3_MSIX_CAP_PBA_BIR Vf3 Msix Cap Pba Bir BAR_0 VF3_MSIX_CAP_PBA_OFFSET Vf3 Msix Cap Pba Offset 00000000 VF3_MSIX_CAP_TABLE_BIR Vf3 Msix Cap Table Bir BAR_0 VF3_MSIX_CAP_TABLE_OFFSET Vf3 Msix Cap Table Offset 00000000 VF3_MSIX_CAP_TABLE_SIZE Vf3 Msix Cap Table Size 000 VF3_MSI_CAP_MULTIMSGCAP Vf3 Msi Cap Multimsgcap 1_vector VF4_MSIX_CAP_PBA_BIR Vf4 Msix Cap Pba Bir BAR_0 VF4_MSIX_CAP_PBA_OFFSET Vf4 Msix Cap Pba Offset 00000000 VF4_MSIX_CAP_TABLE_BIR Vf4 Msix Cap Table Bir BAR_0 VF4_MSIX_CAP_TABLE_OFFSET Vf4 Msix Cap Table Offset 00000000 VF4_MSIX_CAP_TABLE_SIZE Vf4 Msix Cap Table Size 000 VF4_MSI_CAP_MULTIMSGCAP Vf4 Msi Cap Multimsgcap 1_vector VF5_MSIX_CAP_PBA_BIR Vf5 Msix Cap Pba Bir BAR_0 VF5_MSIX_CAP_PBA_OFFSET Vf5 Msix Cap Pba Offset 00000000 VF5_MSIX_CAP_TABLE_BIR Vf5 Msix Cap Table Bir BAR_0 VF5_MSIX_CAP_TABLE_OFFSET Vf5 Msix Cap Table Offset 00000000 VF5_MSIX_CAP_TABLE_SIZE Vf5 Msix Cap Table Size 000 VF5_MSI_CAP_MULTIMSGCAP Vf5 Msi Cap Multimsgcap 1_vector Component_Name xdma_pcie3_ip PF0_Use_Class_Code_Lookup_Assistant false PF1_Use_Class_Code_Lookup_Assistant false PF0_PM_CAP_PMESUPPORT_D0 Pf0 Pm Cap Pmesupport D0 false PF0_SUBSYSTEM_VENDOR_ID Pf0 Subsystem Vendor Id 10EE pf1_sriov_bar5_scale Pf1 Sriov Bar5 Scale Kilobytes pf1_sriov_bar4_type Pf1 Sriov Bar4 Type N/A pf0_vc_cap_enabled Pf0 Vc Cap Enabled false pf1_sriov_bar5_type Pf1 Sriov Bar5 Type N/A pf1_sriov_bar0_enabled Pf1 Sriov Bar0 Enabled true pf0_sriov_bar5_enabled Pf0 Sriov Bar5 Enabled false pcie_blk_locn Pcie Blk Locn X0Y0 pf0_sriov_bar1_64bit Pf0 Sriov Bar1 64bit false pf1_sriov_bar3_prefetchable Pf1 Sriov Bar3 Prefetchable false pf0_pb_enabled Pf0 Pb Enabled false pf1_sriov_bar0_64bit Pf1 Sriov Bar0 64bit false pf1_bar3_type Pf1 Bar3 Type N/A pf1_bar2_enabled Pf1 Bar2 Enabled false pf1_bar2_type Pf1 Bar2 Type N/A pf1_bar2_64bit Pf1 Bar2 64bit false pf1_bar2_prefetchable Pf1 Bar2 Prefetchable false pf1_bar2_scale Pf1 Bar2 Scale Kilobytes pf1_bar2_size Pf1 Bar2 Size 2 pf0_sriov_bar1_scale Pf0 Sriov Bar1 Scale Kilobytes pf1_bar4_type Pf1 Bar4 Type N/A pf0_base_class_menu Pf0 Base Class Menu Simple_communication_controllers pf0_class_code_base Pf0 Class Code Base 07 pf0_sub_class_interface_menu Pf0 Sub Class Interface Menu 16450_compatible_serial_controller pf0_class_code_sub Pf0 Class Code Sub 00 pf0_class_code_interface Pf0 Class Code Interface 01 PF0_CLASS_CODE Pf0 Class Code 070001 pf1_base_class_menu Pf1 Base Class Menu Memory_controller pf1_class_code_base Pf1 Class Code Base 05 pf1_sub_class_interface_menu Pf1 Sub Class Interface Menu Other_memory_controller pf1_class_code_sub Pf1 Class Code Sub 80 pf1_class_code_interface Pf1 Class Code Interface 00 PF1_CLASS_CODE Pf1 Class Code 058000 pf1_sriov_bar0_scale Pf1 Sriov Bar0 Scale Kilobytes pf1_expansion_rom_enabled Pf1 Expansion Rom Enabled false pf0_sriov_bar0_enabled Pf0 Sriov Bar0 Enabled true pf1_sriov_bar0_prefetchable Pf1 Sriov Bar0 Prefetchable false pf1_bar5_type Pf1 Bar5 Type N/A pf0_sriov_bar5_prefetchable Pf0 Sriov Bar5 Prefetchable false pf1_sriov_bar1_enabled Pf1 Sriov Bar1 Enabled false pf0_sriov_bar2_64bit Pf0 Sriov Bar2 64bit false pf1_msix_enabled Pf1 Msix Enabled false pf1_bar5_prefetchable Pf1 Bar5 Prefetchable false pf0_rbar_enabled Pf0 Rbar Enabled false pf1_pb_enabled Pf1 Pb Enabled false pf1_sriov_bar1_64bit Pf1 Sriov Bar1 64bit false pf1_bar3_64bit Pf1 Bar3 64bit false pf0_sriov_bar2_prefetchable Pf0 Sriov Bar2 Prefetchable false pf1_bar3_enabled Pf1 Bar3 Enabled false pf0_sriov_bar2_scale Pf0 Sriov Bar2 Scale Kilobytes pf1_sriov_bar1_scale Pf1 Sriov Bar1 Scale Kilobytes pf1_bar3_scale Pf1 Bar3 Scale Kilobytes pf0_sriov_bar1_enabled Pf0 Sriov Bar1 Enabled false alignment_mode Alignment Mode DWORD_Aligned pf1_sriov_bar4_prefetchable Pf1 Sriov Bar4 Prefetchable false pf1_sriov_bar2_enabled Pf1 Sriov Bar2 Enabled false pf0_sriov_bar3_64bit Pf0 Sriov Bar3 64bit false pf0_sriov_bar0_size Pf0 Sriov Bar0 Size 2 pf1_sriov_bar2_64bit Pf1 Sriov Bar2 64bit false pf1_bar4_64bit Pf1 Bar4 64bit false pf0_sriov_bar1_size Pf0 Sriov Bar1 Size 2 pf0_bar0_enabled Pf0 Bar0 Enabled true pf0_bar0_type Pf0 Bar0 Type Memory pf0_bar0_64bit Pf0 Bar0 64bit false pf0_bar0_prefetchable Pf0 Bar0 Prefetchable false pf0_bar0_scale Pf0 Bar0 Scale Kilobytes pf0_bar0_size Pf0 Bar0 Size 64 pf0_bar1_enabled Pf0 Bar1 Enabled false pf0_bar1_type Pf0 Bar1 Type N/A pf0_bar1_64bit Pf0 Bar1 64bit false pf0_bar1_prefetchable Pf0 Bar1 Prefetchable false pf0_bar1_scale Pf0 Bar1 Scale Kilobytes pf0_bar1_size Pf0 Bar1 Size 2 pf0_bar2_enabled Pf0 Bar2 Enabled false pf0_bar2_type Pf0 Bar2 Type N/A pf0_bar2_64bit Pf0 Bar2 64bit false pf0_bar2_prefetchable Pf0 Bar2 Prefetchable false pf0_bar2_scale Pf0 Bar2 Scale Kilobytes pf0_bar2_size Pf0 Bar2 Size 2 pf0_bar3_enabled Pf0 Bar3 Enabled false pf0_bar3_type Pf0 Bar3 Type N/A pf0_bar3_64bit Pf0 Bar3 64bit false pf0_bar3_prefetchable Pf0 Bar3 Prefetchable false pf0_bar3_scale Pf0 Bar3 Scale Kilobytes pf0_bar3_size Pf0 Bar3 Size 2 pf0_bar4_enabled Pf0 Bar4 Enabled false pf0_bar4_type Pf0 Bar4 Type N/A pf0_bar4_64bit Pf0 Bar4 64bit false pf0_bar4_prefetchable Pf0 Bar4 Prefetchable false pf0_bar4_scale Pf0 Bar4 Scale Kilobytes pf0_bar4_size Pf0 Bar4 Size 2 pf0_bar5_enabled Pf0 Bar5 Enabled false pf0_bar5_type Pf0 Bar5 Type N/A pf0_bar5_prefetchable Pf0 Bar5 Prefetchable false pf0_bar5_scale Pf0 Bar5 Scale Kilobytes pf0_bar5_size Pf0 Bar5 Size 2 pf0_sriov_bar3_scale Pf0 Sriov Bar3 Scale Kilobytes pf1_bar4_enabled Pf1 Bar4 Enabled false pf1_sriov_bar1_prefetchable Pf1 Sriov Bar1 Prefetchable false pf0_sriov_bar2_size Pf0 Sriov Bar2 Size 2 pf1_sriov_bar2_scale Pf1 Sriov Bar2 Scale Kilobytes pf1_bar4_scale Pf1 Bar4 Scale Kilobytes pf0_sriov_bar3_size Pf0 Sriov Bar3 Size 2 pf0_sriov_bar2_enabled Pf0 Sriov Bar2 Enabled false pf0_dev_cap_max_payload Pf0 Dev Cap Max Payload 512_bytes gen_x0y0 Gen X0y0 true gen_x0y1 Gen X0y1 false gen_x0y2 Gen X0y2 false gen_x0y3 Gen X0y3 false gen_x0y4 Gen X0y4 false gen_x0y5 Gen X0y5 false pf0_sriov_bar4_size Pf0 Sriov Bar4 Size 2 pf1_expansion_rom_scale Pf1 Expansion Rom Scale Kilobytes pf1_expansion_rom_size Pf1 Expansion Rom Size 2 pf1_rbar_enabled Pf1 Rbar Enabled false pf1_tphr_enable Pf1 Tphr Enable false pf1_sriov_bar3_enabled Pf1 Sriov Bar3 Enabled false pf0_sriov_bar4_64bit Pf0 Sriov Bar4 64bit false pf0_sriov_bar5_size Pf0 Sriov Bar5 Size 2 pf0_sriov_bar3_prefetchable Pf0 Sriov Bar3 Prefetchable false pf1_sriov_bar3_64bit Pf1 Sriov Bar3 64bit false pf0_expansion_rom_enabled Pf0 Expansion Rom Enabled false pf0_sriov_bar4_scale Pf0 Sriov Bar4 Scale Kilobytes pf0_sriov_bar0_type Pf0 Sriov Bar0 Type Memory pf1_bar5_enabled Pf1 Bar5 Enabled false pf1_bar3_prefetchable Pf1 Bar3 Prefetchable false pf1_sriov_bar0_size Pf1 Sriov Bar0 Size 2 pf1_sriov_bar3_scale Pf1 Sriov Bar3 Scale Kilobytes pf1_bar5_scale Pf1 Bar5 Scale Kilobytes extended_tag_field Extended Tag Field true pf0_sriov_bar1_type Pf0 Sriov Bar1 Type N/A pf0_sriov_bar0_prefetchable Pf0 Sriov Bar0 Prefetchable false pf0_expansion_rom_scale Pf0 Expansion Rom Scale Kilobytes pf0_expansion_rom_size Pf0 Expansion Rom Size 2 pf1_sriov_bar1_size Pf1 Sriov Bar1 Size 2 pf1_ari_enabled Pf1 Ari Enabled false pf0_sriov_bar3_enabled Pf0 Sriov Bar3 Enabled false pf1_sriov_bar5_prefetchable Pf1 Sriov Bar5 Prefetchable false pf0_sriov_bar2_type Pf0 Sriov Bar2 Type N/A vendor_id Vendor Id 10EE pf0_tphr_enable Pf0 Tphr Enable false pf1_sriov_bar2_size Pf1 Sriov Bar2 Size 2 pf0_sriov_bar3_type Pf0 Sriov Bar3 Type N/A pf1_sriov_bar3_size Pf1 Sriov Bar3 Size 2 pf1_bar0_enabled Pf1 Bar0 Enabled false pf1_bar0_type Pf1 Bar0 Type N/A pf1_bar0_64bit Pf1 Bar0 64bit false pf1_bar0_prefetchable Pf1 Bar0 Prefetchable false pf1_bar0_scale Pf1 Bar0 Scale Kilobytes pf1_bar0_size Pf1 Bar0 Size 2 pf1_bar1_enabled Pf1 Bar1 Enabled false pf1_bar1_type Pf1 Bar1 Type N/A pf1_bar1_64bit Pf1 Bar1 64bit false pf1_bar1_prefetchable Pf1 Bar1 Prefetchable false pf1_bar1_scale Pf1 Bar1 Scale Kilobytes pf1_bar1_size Pf1 Bar1 Size 2 pf1_sriov_bar4_enabled Pf1 Sriov Bar4 Enabled false pf1_aer_enabled Pf1 Aer Enabled true pf1_dsn_enabled Pf1 Dsn Enabled false pf0_sriov_bar4_type Pf0 Sriov Bar4 Type N/A pf1_sriov_bar4_64bit Pf1 Sriov Bar4 64bit false pf1_sriov_bar2_prefetchable Pf1 Sriov Bar2 Prefetchable false pf0_sriov_cap_ver Pf0 Sriov Cap Ver 0 pf1_sriov_bar4_size Pf1 Sriov Bar4 Size 2 pf1_msi_enabled Pf1 Msi Enabled true pf0_sriov_bar5_scale Pf0 Sriov Bar5 Scale Kilobytes pf1_dpa_enabled Pf1 Dpa Enabled false pf0_sriov_bar5_type Pf0 Sriov Bar5 Type N/A ext_pcie_cfg_space_enabled Ext Pcie Cfg Space Enabled false pf1_sriov_bar4_scale Pf1 Sriov Bar4 Scale Kilobytes pf1_sriov_bar5_size Pf1 Sriov Bar5 Size 2 pf0_ari_enabled Pf0 Ari Enabled false perf_level Perf Level Extreme axisten_if_width Axisten If Width 256_bit pf0_sriov_bar4_enabled Pf0 Sriov Bar4 Enabled false pf1_sriov_bar0_type Pf1 Sriov Bar0 Type Memory pf1_bar3_size Pf1 Bar3 Size 2 pf0_sriov_bar4_prefetchable Pf0 Sriov Bar4 Prefetchable false pf0_aer_enabled Pf0 Aer Enabled true pf0_dsn_enabled Pf0 Dsn Enabled false pf1_sriov_bar1_type Pf1 Sriov Bar1 Type N/A pf0_sriov_bar0_64bit Pf0 Sriov Bar0 64bit false pf1_bar4_size Pf1 Bar4 Size 2 pf0_msi_enabled Pf0 Msi Enabled true pf1_sriov_bar5_enabled Pf1 Sriov Bar5 Enabled false pf0_dpa_enabled Pf0 Dpa Enabled false pf1_sriov_bar2_type Pf1 Sriov Bar2 Type N/A pf0_msix_enabled Pf0 Msix Enabled false pf1_bar5_size Pf1 Bar5 Size 2 pf1_bar4_prefetchable Pf1 Bar4 Prefetchable false pf0_sriov_bar0_scale Pf0 Sriov Bar0 Scale Kilobytes pf1_dev_cap_max_payload Pf1 Dev Cap Max Payload 512_bytes pf0_sriov_bar1_prefetchable Pf0 Sriov Bar1 Prefetchable false pf1_sriov_bar3_type Pf1 Sriov Bar3 Type N/A pf0_ltr_enabled Pf0 Ltr Enabled false mode_selection Mode Advanced pipe_sim false en_ext_clk false en_msi_per_vec_masking false tandem_mode Tandem Mode None coreclk_freq CORE CLOCK FREQ 500 plltype PLL TYPE QPLL1 axisten_freq AXISTEN IF FREQ 250 aspm_support ASPM Support No_ASPM SRIOV_CAP_ENABLE_EXT SRIOV Cap Enable false axisten_if_enable_msg_route 20000 axisten_if_enable_rx_msg_intfc false cfg_fc_if true cfg_ext_if false acs_ext_cap_enable ACS Ext Capability false cfg_status_if true per_func_status_if true cfg_mgmt_if true rcv_msg_if true cfg_tx_msg_if true cfg_ctl_if true tx_fc_if true en_pcie_drp false en_pl_ifc false en_pcie_conf false dis_gt_wizard false RX_PPM_OFFSET Specify the PPM offset between received data and transmitted data 0 RX_SSC_PPM Specify the spread spectrum clocking modulation in PPM 0 INS_LOSS_NYQ Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB 15 en_transceiver_status_ports false Shared_Logic 1 dedicate_perst true sys_reset_polarity ACTIVE_LOW mcap_enablement MCAP Enable None PHY_LP_TXPRESET Phy Lp Txpreset 4 RX_DETECT Receiver Detect Default en_ext_ch_gt_drp false ext_startup_primitive false en_gt_selection false select_quad GTH_Quad_225 performance false cc_cq_alignment CC CQ Alignment Mode Address_Aligned rc_rq_alignment CC CQ Alignment Mode DWORD_Aligned ins_loss_profile Add-in_Card enable_ibert false en_dbg_descramble false enable_jtag_dbg false en_parity false enable_auto_rxeq False special_gui false gtwiz_in_core 1 en_l23_entry false bmd_pio_mode false mult_pf_des true enable_gt_v1_5 false ext_xvc_vsec_enable Enable to add the PCIe XVC-VSEC to the Examlpe Design false false axisten_if_enable_msg_route_override true UltraScale FPGA Gen3 Integrated Block for PCI Express XPM_CDC 3 2018.2