pll_clk[2:0] pll_clk[2:0] rf label clk clk rst rst rf_wide_wen rf_wide_wen rf_wide_offset[3:0] rf_wide_offset[3:0] rf_wide_data[511:0] rf_wide_data[511:0] rf_rdata[255:0] rf_rdata[255:0] rf_wdata[255:0] rf_wdata[255:0] rf_wen[7:0] rf_wen[7:0] rf_raddr[31:0] rf_raddr[31:0] rf_waddr[31:0] rf_waddr[31:0] casr[9:0] casr[9:0] basr[3:0] basr[3:0] rasr[16:0] rasr[16:0] srf_value[31:0] srf_value[31:0] srf_wen[2:0] srf_wen[2:0] casr_r[31:0] casr_r[31:0] basr_r[31:0] basr_r[31:0] rasr_r[31:0] rasr_r[31:0] reg_file[15:0][31:0] reg_file[15:0][31:0] wdata[7:0][31:0] wdata[7:0][31:0] wen[7:0] wen[7:0] waddr[7:0][3:0] waddr[7:0][3:0] raddr[7:0][3:0] raddr[7:0][3:0] j[31:0] j[31:0] wide_reg[511:0] wide_reg[511:0] clk clk rst rst fs label softmc_end softmc_end read_size[11:0] read_size[11:0] read_seq_incoming read_seq_incoming buffer_space[11:0] buffer_space[11:0] UNSIGNEDDECRADIX br_resolve br_resolve br_target[10:0] br_target[10:0] addr_out[10:0] addr_out[10:0] valid_out valid_out data_in[63:0] data_in[63:0] HEXRADIX valid_in valid_in addr_in[10:0] addr_in[10:0] ready_out ready_out instr[63:0] instr[63:0] instr_pc[10:0] instr_pc[10:0] instr_valid instr_valid inst_is_br inst_is_br is_end is_end is_ddr_start is_ddr_start need_flush need_flush state_r[2:0] state_r[2:0] state_ns[2:0] state_ns[2:0] pc_r[10:0] pc_r[10:0] pc_ns[10:0] pc_ns[10:0] instr_pc_r[10:0] instr_pc_r[10:0] instr_pc_ns[10:0] instr_pc_ns[10:0] instr_r[63:0] instr_r[63:0] instr_ns[63:0] instr_ns[63:0] instr_valid_r instr_valid_r instr_valid_ns instr_valid_ns WAIT_RESOLVE_S[31:0] WAIT_RESOLVE_S[31:0] FETCH_NEXT_LINE_S[31:0] FETCH_NEXT_LINE_S[31:0] WAIT_BUFFER_SPACE_S[31:0] WAIT_BUFFER_SPACE_S[31:0] fend label clk clk rst rst softmc_fin softmc_fin user_rst user_rst init_calib_complete init_calib_complete rbe_switch_mode rbe_switch_mode frontend_ready frontend_ready addr_in[10:0] addr_in[10:0] valid_in valid_in data_out[63:0] data_out[63:0] valid_out valid_out addr_out[10:0] addr_out[10:0] ready_in ready_in h2c_tdata_0[255:0] h2c_tdata_0[255:0] h2c_tlast_0 h2c_tlast_0 h2c_tvalid_0 h2c_tvalid_0 h2c_tready_0 h2c_tready_0 h2c_tkeep_0[31:0] h2c_tkeep_0[31:0] per_rd_init per_rd_init per_zq_init per_zq_init delay_fin[31:0] delay_fin[31:0] imem_wr_en imem_wr_en imem_rd_en imem_rd_en imem_addr[10:0] imem_addr[10:0] imem_wr_data[63:0] imem_wr_data[63:0] imem_rd_data[63:0] imem_rd_data[63:0] maint_inst[63:0] maint_inst[63:0] maint_valid maint_valid maint_addr[10:0] maint_addr[10:0] maint_req maint_req maint_ack maint_ack maint_process maint_process program_process program_process state_r[1:0] state_r[1:0] state_ns[1:0] state_ns[1:0] rst_ctr_ns[4:0] rst_ctr_ns[4:0] rst_ctr_r[4:0] rst_ctr_r[4:0] xfer_ctr_r[10:0] xfer_ctr_r[10:0] xfer_ctr_ns[10:0] xfer_ctr_ns[10:0] valid_out_sr[0:0] valid_out_sr[0:0] addr_out_sr[10:0] addr_out_sr[10:0] SIM_MEM[31:0] SIM_MEM[31:0] IDLE_S[1:0] IDLE_S[1:0] INIT_MEM_S[1:0] INIT_MEM_S[1:0] EXECUTE_S[1:0] EXECUTE_S[1:0] maint label clk clk clk clk rst rst init_calib_complete init_calib_complete softmc_fin softmc_fin aref_en aref_en aref_en_valid aref_en_valid maint_ack maint_ack maint_req maint_req per_rd_init per_rd_init per_zq_init per_zq_init per_ref_init per_ref_init maint_process maint_process program_process program_process in_addr[10:0] in_addr[10:0] in_valid in_valid out_data[63:0] out_data[63:0] out_valid out_valid out_addr[10:0] out_addr[10:0] zq_ack zq_ack per_rd_ack per_rd_ack ref_ack ref_ack zq_request zq_request zq_process zq_process per_rd_request per_rd_request per_rd_process per_rd_process pr_ref_request pr_ref_request pr_ref_process pr_ref_process pr_read_out[63:0] pr_read_out[63:0] pr_zq_out[63:0] pr_zq_out[63:0] pr_ref_out[63:0] pr_ref_out[63:0] maint_prescaler_tick_r_lcl maint_prescaler_tick_r_lcl maint_prescaler_r[6:0] maint_prescaler_r[6:0] maint_prescaler_ns[6:0] maint_prescaler_ns[6:0] maint_prescaler_tick_ns maint_prescaler_tick_ns periodic_rd_timer_r[1:0] periodic_rd_timer_r[1:0] periodic_rd_timer[1:0] periodic_rd_timer[1:0] periodic_rd_timer_one periodic_rd_timer_one periodic_rd_request periodic_rd_request \zq_cntrl.zq_tick \zq_cntrl.zq_tick \zq_cntrl.zq_timer.zq_timer_r [17:0] \zq_cntrl.zq_timer.zq_timer_r [17:0] \zq_cntrl.zq_timer.zq_timer_ns [17:0] \zq_cntrl.zq_timer.zq_timer_ns [17:0] \zq_cntrl.zq_request_logic.zq_clear \zq_cntrl.zq_request_logic.zq_clear \zq_cntrl.zq_request_logic.zq_request_r \zq_cntrl.zq_request_logic.zq_request_r \zq_cntrl.zq_request_logic.zq_request_ns \zq_cntrl.zq_request_logic.zq_request_ns autoref_timer_r[3:0] autoref_timer_r[3:0] autoref_timer[3:0] autoref_timer[3:0] aref_switch_ns aref_switch_ns aref_switch_r aref_switch_r ds label clk clk rst rst instr[63:0] instr[63:0] instr_pc[10:0] instr_pc[10:0] instr_valid instr_valid ddr_valid ddr_valid exe_valid exe_valid ddr_uop[99:0] ddr_uop[99:0] exe_uop[60:0] exe_uop[60:0] exe_pc[10:0] exe_pc[10:0] ddr_valid_r ddr_valid_r ddr_valid_ns ddr_valid_ns exe_valid_r exe_valid_r exe_valid_ns exe_valid_ns exe_pc_r[10:0] exe_pc_r[10:0] ddr_uop_r[3:0][24:0] ddr_uop_r[3:0][24:0] ddr_uop_ns[3:0][24:0] ddr_uop_ns[3:0][24:0] exe_uop_r[60:0] exe_uop_r[60:0] exe_uop_ns[60:0] exe_uop_ns[60:0] ddr_insts[3:0][15:0] ddr_insts[3:0][15:0] imd[26:0] imd[26:0] i[31:0] i[31:0] div[31:0] div[31:0] es label ep label clk clk rst rst exe_valid exe_valid exe_uop[60:0] exe_uop[60:0] exe_pc[10:0] exe_pc[10:0] br_resolve br_resolve br_target[10:0] br_target[10:0] wide_wen wide_wen rf_wdata[31:0] rf_wdata[31:0] rf_wen rf_wen rf_raddr[7:0] rf_raddr[7:0] rf_waddr[3:0] rf_waddr[3:0] rf_rdata[63:0] rf_rdata[63:0] mem_wen mem_wen mem_ren mem_ren mem_addr[9:0] mem_addr[9:0] UNSIGNEDDECRADIX mem_wdata[31:0] mem_wdata[31:0] mem_rdata[31:0] mem_rdata[31:0] s2_valid s2_valid s2_uop[60:0] s2_uop[60:0] s2_pc[10:0] s2_pc[10:0] s2_rs1[3:0] s2_rs1[3:0] s2_rs2[3:0] s2_rs2[3:0] s2_rt[3:0] s2_rt[3:0] s2_wen s2_wen s2_mem_ren s2_mem_ren s2_mem_wen s2_mem_wen s3_wen s3_wen s3_rt[3:0] s3_rt[3:0] s2_wide_wen s2_wide_wen s2_imd_r[31:0] s2_imd_r[31:0] s2_imd_ns[31:0] s2_imd_ns[31:0] s3_br_resolve s3_br_resolve s3_br_target[10:0] s3_br_target[10:0] s2_wdata[31:0] s2_wdata[31:0] s2_rs1_data[31:0] s2_rs1_data[31:0] s2_rs2_data[31:0] s2_rs2_data[31:0] s2_mem_wdata[31:0] s2_mem_wdata[31:0] fetch_pc[10:0] fetch_pc[10:0] clk clk rst rst ddr_valid ddr_valid exe_valid exe_valid ddr_uop[99:0] ddr_uop[99:0] exe_uop[60:0] exe_uop[60:0] exe_pc[10:0] exe_pc[10:0] br_resolve br_resolve br_target[10:0] br_target[10:0] ddr_write[3:0] ddr_write[3:0] ddr_read[3:0] ddr_read[3:0] ddr_pre[3:0] ddr_pre[3:0] ddr_act[3:0] ddr_act[3:0] ddr_ref[3:0] ddr_ref[3:0] ddr_zq[3:0] ddr_zq[3:0] ddr_nop[3:0] ddr_nop[3:0] ddr_ap[3:0] ddr_ap[3:0] ddr_pall[3:0] ddr_pall[3:0] ddr_half_bl[3:0] ddr_half_bl[3:0] ddr_bg[7:0] ddr_bg[7:0] ddr_bank[7:0] ddr_bank[7:0] ddr_col[39:0] ddr_col[39:0] ddr_row[67:0] ddr_row[67:0] ddr_wdata[511:0] ddr_wdata[511:0] rf_wide_wen rf_wide_wen rf_wide_offset[3:0] rf_wide_offset[3:0] rf_rdata[255:0] rf_rdata[255:0] rf_wdata[255:0] rf_wdata[255:0] rf_wen[7:0] rf_wen[7:0] rf_raddr[31:0] rf_raddr[31:0] rf_waddr[31:0] rf_waddr[31:0] casr[9:0] casr[9:0] basr[3:0] basr[3:0] rasr[16:0] rasr[16:0] wide_reg[511:0] wide_reg[511:0] srf_value[31:0] srf_value[31:0] srf_wen[2:0] srf_wen[2:0] s2_exe s2_exe rf_wen_ddr[7:0] rf_wen_ddr[7:0] rf_waddr_ddr[31:0] rf_waddr_ddr[31:0] rf_wdata_ddr[255:0] rf_wdata_ddr[255:0] rf_raddr_ddr[31:0] rf_raddr_ddr[31:0] rf_wdata_exe[31:0] rf_wdata_exe[31:0] rf_raddr_exe[7:0] rf_raddr_exe[7:0] rf_waddr_exe[3:0] rf_waddr_exe[3:0] rf_wen_exe rf_wen_exe rf_wide_wen_exe rf_wide_wen_exe mem_wen mem_wen mem_ren mem_ren mem_addr[9:0] mem_addr[9:0] mem_wdata[31:0] mem_wdata[31:0] mem_rdata[31:0] mem_rdata[31:0] exe_target_srf exe_target_srf rbe label rbf label clk clk srst srst din[511:0] din[511:0] wr_en wr_en rd_en rd_en dout[255:0] dout[255:0] full full empty empty valid valid prog_full prog_full wr_rst_busy wr_rst_busy rd_rst_busy rd_rst_busy clk clk rst rst flush flush read_seq_incoming read_seq_incoming incoming_reads[11:0] incoming_reads[11:0] buffer_space[11:0] buffer_space[11:0] switch_mode switch_mode rd_data[511:0] rd_data[511:0] rd_valid rd_valid per_rd_init per_rd_init per_zq_init per_zq_init ddr_wdata[511:0] ddr_wdata[511:0] c2h_tdata_0[255:0] c2h_tdata_0[255:0] c2h_tlast_0 c2h_tlast_0 c2h_tvalid_0 c2h_tvalid_0 c2h_tready_0 c2h_tready_0 c2h_tkeep_0[31:0] c2h_tkeep_0[31:0] buffer_space_r[11:0] buffer_space_r[11:0] UNSIGNEDDECRADIX mode_r mode_r mode_ns mode_ns rd_valid_r rd_valid_r xctr_r[9:0] xctr_r[9:0] UNSIGNEDDECRADIX ignore_read_r ignore_read_r ignore_read_ns ignore_read_ns ignore_flush_r ignore_flush_r ignore_flush_ns ignore_flush_ns read_diff[511:0] read_diff[511:0] diff_valid diff_valid pc_out[127:0][2:0] pc_out[127:0][2:0] pc_out_l2[63:0][3:0] pc_out_l2[63:0][3:0] pc_out_l3[31:0][4:0] pc_out_l3[31:0][4:0] pc_out_l4[15:0][5:0] pc_out_l4[15:0][5:0] pc_out_l5[7:0][6:0] pc_out_l5[7:0][6:0] pc_out_l6[3:0][7:0] pc_out_l6[3:0][7:0] pc_out_l7[1:0][8:0] pc_out_l7[1:0][8:0] pop_count_value[15:0] pop_count_value[15:0] pop_count_valid pop_count_valid l1[31:0] l1[31:0] l2[31:0] l2[31:0] l3[31:0] l3[31:0] l4[31:0] l4[31:0] l5[31:0] l5[31:0] l6[31:0] l6[31:0] dsr_out[511:0] dsr_out[511:0] dsr_valid dsr_valid tlast tlast rbf_empty rbf_empty rbf_rd_valid rbf_rd_valid rbf_full rbf_full fifo_almost_full fifo_almost_full fifo_valid fifo_valid proc_flush_ns proc_flush_ns proc_flush_r proc_flush_r buffer_space_ns[11:0] buffer_space_ns[11:0] UNSIGNEDDECRADIX READ_MODE[31:0] READ_MODE[31:0] DIFF_MODE[31:0] DIFF_MODE[31:0] ddr_adapter label rst rst init_calib_complete init_calib_complete ddr_write[3:0] ddr_write[3:0] ddr_read[3:0] ddr_read[3:0] ddr_pre[3:0] ddr_pre[3:0] ddr_act[3:0] ddr_act[3:0] ddr_ref[3:0] ddr_ref[3:0] ddr_zq[3:0] ddr_zq[3:0] ddr_mrs[3:0] ddr_mrs[3:0] ddr_nop[3:0] ddr_nop[3:0] ddr_ap[3:0] ddr_ap[3:0] ddr_half_bl[3:0] ddr_half_bl[3:0] ddr_pall[3:0] ddr_pall[3:0] ddr_bg[7:0] ddr_bg[7:0] ddr_bank[7:0] ddr_bank[7:0] ddr_col[39:0] ddr_col[39:0] ddr_row[67:0] ddr_row[67:0] ddr_wdata[511:0] ddr_wdata[511:0] ddr_maint_read ddr_maint_read dBufAdr[4:0] dBufAdr[4:0] wrData[511:0] wrData[511:0] wrDataMask[63:0] wrDataMask[63:0] clk clk wrDataEn wrDataEn mc_ACT_n[7:0] mc_ACT_n[7:0] mc_ADR[135:0] mc_ADR[135:0] mc_BA[15:0] mc_BA[15:0] mc_BG[15:0] mc_BG[15:0] mc_CS_n[7:0] mc_CS_n[7:0] mcRdCAS mcRdCAS mcWrCAS mcWrCAS winRank[1:0] winRank[1:0] winBuf[4:0] winBuf[4:0] rdDataEn rdDataEn rdDataEnd rdDataEnd mcCasSlot[1:0] mcCasSlot[1:0] mcCasSlot2 mcCasSlot2 gt_data_ready gt_data_ready iss_dummy_read iss_dummy_read ddr_wdata_r[511:0] ddr_wdata_r[511:0] wrDataBuf[1023:0] wrDataBuf[1023:0] wrDataBuf_ns[1023:0] wrDataBuf_ns[1023:0] slot1_full slot1_full slot1_full_ns slot1_full_ns slot2_full slot2_full slot2_full_ns slot2_full_ns iss_dummy_read_r iss_dummy_read_r iss_dummy_read_ns iss_dummy_read_ns read_will_be_dummy_r read_will_be_dummy_r read_will_be_dummy_ns read_will_be_dummy_ns init_calib_complete_r init_calib_complete_r wrDataEn_r wrDataEn_r ACT_n_ns[7:0] ACT_n_ns[7:0] ACT_n_r[7:0] ACT_n_r[7:0] ADR_ns[135:0] ADR_ns[135:0] ADR_r[135:0] ADR_r[135:0] BA_ns[15:0] BA_ns[15:0] BA_r[15:0] BA_r[15:0] BG_ns[15:0] BG_ns[15:0] BG_r[15:0] BG_r[15:0] CS_n_ns[7:0] CS_n_ns[7:0] CS_n_r[7:0] CS_n_r[7:0] ODT_ns[7:0] ODT_ns[7:0] ODT_r[7:0] ODT_r[7:0] RdCAS_ns RdCAS_ns RdCAS_r RdCAS_r WrCAS_ns WrCAS_ns WrCAS_r WrCAS_r mcCasSlot_r[1:0] mcCasSlot_r[1:0] mcCasSlot_ns[1:0] mcCasSlot_ns[1:0] gt_data_ready_r gt_data_ready_r gt_data_ready_ns gt_data_ready_ns mc_cmd_i[31:0] mc_cmd_i[31:0] adr_bit_i[31:0] adr_bit_i[31:0] bank_bit_i[31:0] bank_bit_i[31:0] bg_bit_i[31:0] bg_bit_i[31:0] phy label c0_init_calib_complete c0_init_calib_complete c0_ddr4_act_n c0_ddr4_act_n c0_ddr4_adr[16:0] c0_ddr4_adr[16:0] BINARYRADIX c0_ddr4_ba[1:0] c0_ddr4_ba[1:0] c0_ddr4_bg[1:0] c0_ddr4_bg[1:0] pll_clk0[10:0] pll_clk0[10:0] pll_clk1[10:0] pll_clk1[10:0] gclk_in[5:0] gclk_in[5:0] c0_ddr4_ck_c[0:0] c0_ddr4_ck_c[0:0] c0_ddr4_ck_t[0:0] c0_ddr4_ck_t[0:0] c0_ddr4_cke[0:0] c0_ddr4_cke[0:0] c0_ddr4_cs_n[0:0] c0_ddr4_cs_n[0:0] c0_ddr4_dm_dbi_n[7:0] c0_ddr4_dm_dbi_n[7:0] c0_ddr4_dq[63:0] c0_ddr4_dq[63:0] c0_ddr4_dqs_c[7:0] c0_ddr4_dqs_c[7:0] c0_ddr4_dqs_t[7:0] c0_ddr4_dqs_t[7:0] c0_ddr4_odt[0:0] c0_ddr4_odt[0:0] c0_ddr4_reset_n c0_ddr4_reset_n c0_ddr4_ui_clk c0_ddr4_ui_clk c0_ddr4_ui_clk_sync_rst c0_ddr4_ui_clk_sync_rst c0_init_calib_complete c0_init_calib_complete c0_sys_clk_n c0_sys_clk_n c0_sys_clk_p c0_sys_clk_p dBufAdr[4:0] dBufAdr[4:0] dbg_bus[511:0] dbg_bus[511:0] dbg_clk dbg_clk gt_data_ready gt_data_ready mcCasSlot[1:0] mcCasSlot[1:0] mcCasSlot2[0:0] mcCasSlot2[0:0] mcRdCAS[0:0] mcRdCAS[0:0] mcWrCAS[0:0] mcWrCAS[0:0] mc_ACT_n[7:0] mc_ACT_n[7:0] mc_ADR[135:0] mc_ADR[135:0] mc_BA[15:0] mc_BA[15:0] mc_BG[15:0] mc_BG[15:0] mc_CKE[7:0] mc_CKE[7:0] mc_CS_n[7:0] mc_CS_n[7:0] mc_ODT[7:0] mc_ODT[7:0] per_rd_done[0:0] per_rd_done[0:0] rdData[511:0] rdData[511:0] rdDataAddr[4:0] rdDataAddr[4:0] rdDataEn[0:0] rdDataEn[0:0] rdDataEnd[0:0] rdDataEnd[0:0] rmw_rd_done[0:0] rmw_rd_done[0:0] sys_rst sys_rst tCWL[5:0] tCWL[5:0] winBuf[4:0] winBuf[4:0] winInjTxn[0:0] winInjTxn[0:0] winRank[1:0] winRank[1:0] winRmw[0:0] winRmw[0:0] wrData[511:0] wrData[511:0] wrDataAddr[4:0] wrDataAddr[4:0] wrDataEn[0:0] wrDataEn[0:0] wrDataMask[63:0] wrDataMask[63:0] dllt label clk_sel clk_sel Dram0 label CK[1:0] CK[1:0] ACT_n ACT_n RAS_n_A16 RAS_n_A16 CAS_n_A15 CAS_n_A15 WE_n_A14 WE_n_A14 ALERT_n ALERT_n PARITY PARITY RESET_n RESET_n TEN TEN CS_n CS_n CKE CKE ODT ODT C[2:0] C[2:0] BG[1:0] BG[1:0] BA[1:0] BA[1:0] ADDR[13:0] ADDR[13:0] BINARYRADIX ADDR_17 ADDR_17 DM_n[0:0] DM_n[0:0] DQ[7:0] DQ[7:0] DQS_t[0:0] DQS_t[0:0] DQS_c[0:0] DQS_c[0:0] ZQ ZQ PWR PWR VREF_CA VREF_CA VREF_DQ VREF_DQ CONFIGURED_DQ_BITS[31:0] CONFIGURED_DQ_BITS[31:0] CONFIGURED_DQS_BITS[31:0] CONFIGURED_DQS_BITS[31:0] CONFIGURED_DM_BITS[31:0] CONFIGURED_DM_BITS[31:0] Dram7 label CK[1:0] CK[1:0] ACT_n ACT_n RAS_n_A16 RAS_n_A16 CAS_n_A15 CAS_n_A15 WE_n_A14 WE_n_A14 ALERT_n ALERT_n PARITY PARITY RESET_n RESET_n TEN TEN CS_n CS_n CKE CKE ODT ODT C[2:0] C[2:0] BG[1:0] BG[1:0] BA[1:0] BA[1:0] ADDR[13:0] ADDR[13:0] BINARYRADIX ADDR_17 ADDR_17 DM_n[0:0] DM_n[0:0] DQ[7:0] DQ[7:0] DQS_t[0:0] DQS_t[0:0] DQS_c[0:0] DQS_c[0:0] ZQ ZQ PWR PWR VREF_CA VREF_CA VREF_DQ VREF_DQ CONFIGURED_DQ_BITS[31:0] CONFIGURED_DQ_BITS[31:0] CONFIGURED_DQS_BITS[31:0] CONFIGURED_DQS_BITS[31:0] CONFIGURED_DM_BITS[31:0] CONFIGURED_DM_BITS[31:0] cmdName[31:0] cmdName[31:0] ASCIIRADIX c0_ddr4_ck_c[0:0] c0_ddr4_ck_c[0:0] dmem label clka clka ena ena wea[0:0] wea[0:0] addra[9:0] addra[9:0] dina[31:0] dina[31:0] douta[31:0] douta[31:0]