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// IP VLNV: xilinx.com:ip:xdma:4.1
// IP Revision: 4

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
xdma your_instance_name (
  .sys_clk(sys_clk),                                    // input wire sys_clk
  .sys_clk_gt(sys_clk_gt),                              // input wire sys_clk_gt
  .sys_rst_n(sys_rst_n),                                // input wire sys_rst_n
  .user_lnk_up(user_lnk_up),                            // output wire user_lnk_up
  .pci_exp_txp(pci_exp_txp),                            // output wire [7 : 0] pci_exp_txp
  .pci_exp_txn(pci_exp_txn),                            // output wire [7 : 0] pci_exp_txn
  .pci_exp_rxp(pci_exp_rxp),                            // input wire [7 : 0] pci_exp_rxp
  .pci_exp_rxn(pci_exp_rxn),                            // input wire [7 : 0] pci_exp_rxn
  .axi_aclk(axi_aclk),                                  // output wire axi_aclk
  .axi_aresetn(axi_aresetn),                            // output wire axi_aresetn
  .usr_irq_req(usr_irq_req),                            // input wire [0 : 0] usr_irq_req
  .usr_irq_ack(usr_irq_ack),                            // output wire [0 : 0] usr_irq_ack
  .msi_enable(msi_enable),                              // output wire msi_enable
  .msi_vector_width(msi_vector_width),                  // output wire [2 : 0] msi_vector_width
  .cfg_mgmt_addr(cfg_mgmt_addr),                        // input wire [18 : 0] cfg_mgmt_addr
  .cfg_mgmt_write(cfg_mgmt_write),                      // input wire cfg_mgmt_write
  .cfg_mgmt_write_data(cfg_mgmt_write_data),            // input wire [31 : 0] cfg_mgmt_write_data
  .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),          // input wire [3 : 0] cfg_mgmt_byte_enable
  .cfg_mgmt_read(cfg_mgmt_read),                        // input wire cfg_mgmt_read
  .cfg_mgmt_read_data(cfg_mgmt_read_data),              // output wire [31 : 0] cfg_mgmt_read_data
  .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),  // output wire cfg_mgmt_read_write_done
  .s_axis_c2h_tdata_0(s_axis_c2h_tdata_0),              // input wire [255 : 0] s_axis_c2h_tdata_0
  .s_axis_c2h_tlast_0(s_axis_c2h_tlast_0),              // input wire s_axis_c2h_tlast_0
  .s_axis_c2h_tvalid_0(s_axis_c2h_tvalid_0),            // input wire s_axis_c2h_tvalid_0
  .s_axis_c2h_tready_0(s_axis_c2h_tready_0),            // output wire s_axis_c2h_tready_0
  .s_axis_c2h_tkeep_0(s_axis_c2h_tkeep_0),              // input wire [31 : 0] s_axis_c2h_tkeep_0
  .m_axis_h2c_tdata_0(m_axis_h2c_tdata_0),              // output wire [255 : 0] m_axis_h2c_tdata_0
  .m_axis_h2c_tlast_0(m_axis_h2c_tlast_0),              // output wire m_axis_h2c_tlast_0
  .m_axis_h2c_tvalid_0(m_axis_h2c_tvalid_0),            // output wire m_axis_h2c_tvalid_0
  .m_axis_h2c_tready_0(m_axis_h2c_tready_0),            // input wire m_axis_h2c_tready_0
  .m_axis_h2c_tkeep_0(m_axis_h2c_tkeep_0)              // output wire [31 : 0] m_axis_h2c_tkeep_0
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file xdma.v when simulating
// the core, xdma. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.