xilinx.com customized_ip axis_clock_converter 1.0 S_AXIS S_AXIS TVALID s_axis_tvalid TREADY s_axis_tready TDATA s_axis_tdata TSTRB s_axis_tstrb TKEEP s_axis_tkeep TLAST s_axis_tlast TID s_axis_tid TDEST s_axis_tdest TUSER s_axis_tuser TDATA_NUM_BYTES 32 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl M_AXIS M_AXIS TVALID m_axis_tvalid TREADY m_axis_tready TDATA m_axis_tdata TSTRB m_axis_tstrb TKEEP m_axis_tkeep TLAST m_axis_tlast TID m_axis_tid TDEST m_axis_tdest TUSER m_axis_tuser TDATA_NUM_BYTES 32 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl S_RSTIF S_RSTIF RST s_axis_aresetn POLARITY ACTIVE_LOW none INSERT_VIP 0 simulation.rtl M_RSTIF M_RSTIF RST m_axis_aresetn POLARITY ACTIVE_LOW none INSERT_VIP 0 simulation.rtl S_CLKIF S_CLKIF CLK s_axis_aclk FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl M_CLKIF M_CLKIF CLK m_axis_aclk FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl S_CLKENIF S_CLKENIF CE s_axis_aclken POLARITY ACTIVE_LOW none false M_CLKENIF M_CLKENIF CE m_axis_aclken POLARITY ACTIVE_LOW none false s_axis_aresetn in wire dummy_view 0x0 m_axis_aresetn in wire dummy_view 0x0 s_axis_aclken in wire dummy_view 0x1 false m_axis_aclken in wire dummy_view 0x1 false s_axis_aclk in wire dummy_view 0x0 s_axis_tvalid in wire dummy_view 0x0 s_axis_tready out wire dummy_view s_axis_tdata in 255 0 wire dummy_view 0x0000000000000000000000000000000000000000000000000000000000000000 true s_axis_tstrb in 31 0 wire dummy_view 0xFFFFFFFF false s_axis_tkeep in 31 0 wire dummy_view 0xFFFFFFFF true s_axis_tlast in wire dummy_view 0x1 true s_axis_tid in 0 0 wire dummy_view 0x0 false s_axis_tdest in 0 0 wire dummy_view 0x0 false s_axis_tuser in 0 0 wire dummy_view 0x0 false m_axis_aclk in wire dummy_view 0x0 m_axis_tvalid out wire dummy_view m_axis_tready in wire dummy_view 0x1 m_axis_tdata out 255 0 wire dummy_view true m_axis_tstrb out 31 0 wire dummy_view false m_axis_tkeep out 31 0 wire dummy_view true m_axis_tlast out wire dummy_view true m_axis_tid out 0 0 wire dummy_view false m_axis_tdest out 0 0 wire dummy_view false m_axis_tuser out 0 0 wire dummy_view false C_FAMILY virtexuplusHBM C_AXIS_TDATA_WIDTH 256 C_AXIS_TID_WIDTH 1 C_AXIS_TDEST_WIDTH 1 C_AXIS_TUSER_WIDTH 1 C_AXIS_SIGNAL_SET 0b00000000000000000000000000011011 C_IS_ACLK_ASYNC 1 C_SYNCHRONIZER_STAGE 2 C_S_AXIS_ACLK_RATIO 1 C_M_AXIS_ACLK_RATIO 2 C_ACLKEN_CONV_MODE 0 choice_list_27ecedf0 16:1 15:1 14:1 13:1 12:1 11:1 10:1 9:1 8:1 7:1 6:1 5:1 4:1 3:1 2:1 1:1 1:2 1:3 1:4 1:5 1:6 1:7 1:8 1:9 1:10 1:11 1:12 1:13 1:14 1:15 1:16 choice_pairs_37189c7b 0 1 choice_pairs_7e3eb5e2 0 1 2 3 The AXI4-Stream Clock Converter IP provides the infrastructure to change the clocking rate between a AXI4-Stream master and slave. TDATA_NUM_BYTES TDATA Width (bytes) 32 true TID_WIDTH TID Width (bits) 0 true TDEST_WIDTH TDEST Width (bits) 0 true TUSER_WIDTH TUSER Width (bits) 0 true IS_ACLK_ASYNC Asynchronous Clocks 1 true HAS_TSTRB Enable TSTRB 0 true HAS_TKEEP Enable TKEEP 1 true HAS_TLAST Enable TLAST 1 true SYNCHRONIZATION_STAGES Synchronization Stages across Cross Clock Domain Logic 2 true ACLK_RATIO SI to MI Clock Ratio 1:2 false ACLKEN_CONV_MODE ACLKEN Conversion Mode 0 true Component_Name axis_clock_converter AXI4-Stream Clock Converter XPM_CDC XPM_FIFO 21 2019.2