xilinx.com customized_ip phy_ddr4 1.0 C0_SYS_CLK true CLK_N c0_sys_clk_n CLK_P c0_sys_clk_p BOARD.ASSOCIATED_PARAM C0_CLOCK_BOARD_INTERFACE CAN_DEBUG false none FREQ_HZ 100000000 none true C0_SYS_CLK_I true CLK c0_sys_clk_i FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false C0_DDR4 true ACT_N c0_ddr4_act_n ADR c0_ddr4_adr BA c0_ddr4_ba BG c0_ddr4_bg C_ID c0_ddr4_c CK_C c0_ddr4_ck_c CK_T c0_ddr4_ck_t CKE c0_ddr4_cke CS_N c0_ddr4_cs_n DM_N c0_ddr4_dm_dbi_n DQ c0_ddr4_dq DQS_C c0_ddr4_dqs_c DQS_T c0_ddr4_dqs_t ODT c0_ddr4_odt PAR c0_ddr4_parity RESET_N c0_ddr4_reset_n BOARD.ASSOCIATED_PARAM C0_DDR4_BOARD_INTERFACE CAN_DEBUG false none TIMEPERIOD_PS 1250 none MEMORY_TYPE COMPONENTS none MEMORY_PART none DATA_WIDTH 8 none CS_ENABLED true none DATA_MASK_ENABLED true none SLOT Single none CUSTOM_PARTS none MEM_ADDR_MAP ROW_COLUMN_BANK none BURST_LENGTH 8 none AXI_ARBITRATION_SCHEME TDM none CAS_LATENCY 11 none CAS_WRITE_LATENCY 11 none false C0_DDR4_S_AXI_CTRL true ARADDR c0_ddr4_s_axi_ctrl_araddr ARREADY c0_ddr4_s_axi_ctrl_arready ARVALID c0_ddr4_s_axi_ctrl_arvalid AWADDR c0_ddr4_s_axi_ctrl_awaddr AWREADY c0_ddr4_s_axi_ctrl_awready AWVALID c0_ddr4_s_axi_ctrl_awvalid BREADY c0_ddr4_s_axi_ctrl_bready BRESP c0_ddr4_s_axi_ctrl_bresp BVALID c0_ddr4_s_axi_ctrl_bvalid RDATA c0_ddr4_s_axi_ctrl_rdata RREADY c0_ddr4_s_axi_ctrl_rready RRESP c0_ddr4_s_axi_ctrl_rresp RVALID c0_ddr4_s_axi_ctrl_rvalid WDATA c0_ddr4_s_axi_ctrl_wdata WREADY c0_ddr4_s_axi_ctrl_wready WVALID c0_ddr4_s_axi_ctrl_wvalid FREQ_HZ 1.665e+08 DATA_WIDTH 1 none PROTOCOL AXI4LITE none ID_WIDTH 0 none ADDR_WIDTH 1 none AWUSER_WIDTH 0 none ARUSER_WIDTH 0 none WUSER_WIDTH 0 none RUSER_WIDTH 0 none BUSER_WIDTH 0 none READ_WRITE_MODE READ_WRITE none HAS_BURST 0 none HAS_LOCK 0 none HAS_PROT 0 none HAS_CACHE 0 none HAS_QOS 0 none HAS_REGION 0 none HAS_WSTRB 0 none HAS_BRESP 0 none HAS_RRESP 0 none SUPPORTS_NARROW_BURST 0 none NUM_READ_OUTSTANDING 1 none NUM_WRITE_OUTSTANDING 1 none MAX_BURST_LENGTH 1 none PHASE 0.000 none CLK_DOMAIN none NUM_READ_THREADS 1 none NUM_WRITE_THREADS 1 none RUSER_BITS_PER_BYTE 0 none WUSER_BITS_PER_BYTE 0 none INSERT_VIP 0 simulation.rtl false C0_DDR4_S_AXI true ARADDR c0_ddr4_s_axi_araddr ARBURST c0_ddr4_s_axi_arburst ARCACHE c0_ddr4_s_axi_arcache ARID c0_ddr4_s_axi_arid ARLEN c0_ddr4_s_axi_arlen ARLOCK c0_ddr4_s_axi_arlock ARPROT c0_ddr4_s_axi_arprot ARQOS c0_ddr4_s_axi_arqos ARREADY c0_ddr4_s_axi_arready ARSIZE c0_ddr4_s_axi_arsize ARVALID c0_ddr4_s_axi_arvalid AWADDR c0_ddr4_s_axi_awaddr AWBURST c0_ddr4_s_axi_awburst AWCACHE c0_ddr4_s_axi_awcache AWID c0_ddr4_s_axi_awid AWLEN c0_ddr4_s_axi_awlen AWLOCK c0_ddr4_s_axi_awlock AWPROT c0_ddr4_s_axi_awprot AWQOS c0_ddr4_s_axi_awqos AWREADY c0_ddr4_s_axi_awready AWSIZE c0_ddr4_s_axi_awsize AWVALID c0_ddr4_s_axi_awvalid BID c0_ddr4_s_axi_bid BREADY c0_ddr4_s_axi_bready BRESP c0_ddr4_s_axi_bresp BVALID c0_ddr4_s_axi_bvalid RDATA c0_ddr4_s_axi_rdata RID c0_ddr4_s_axi_rid RLAST c0_ddr4_s_axi_rlast RREADY c0_ddr4_s_axi_rready RRESP c0_ddr4_s_axi_rresp RVALID c0_ddr4_s_axi_rvalid WDATA c0_ddr4_s_axi_wdata WLAST c0_ddr4_s_axi_wlast WREADY c0_ddr4_s_axi_wready WSTRB c0_ddr4_s_axi_wstrb WVALID c0_ddr4_s_axi_wvalid FREQ_HZ 1.665e+08 DATA_WIDTH 1 none PROTOCOL AXI4LITE none ID_WIDTH 0 none ADDR_WIDTH 1 none AWUSER_WIDTH 0 none ARUSER_WIDTH 0 none WUSER_WIDTH 0 none RUSER_WIDTH 0 none BUSER_WIDTH 0 none READ_WRITE_MODE READ_WRITE none HAS_BURST 0 none HAS_LOCK 0 none HAS_PROT 0 none HAS_CACHE 0 none HAS_QOS 0 none HAS_REGION 0 none HAS_WSTRB 0 none HAS_BRESP 0 none HAS_RRESP 0 none SUPPORTS_NARROW_BURST 0 none NUM_READ_OUTSTANDING 1 none NUM_WRITE_OUTSTANDING 1 none MAX_BURST_LENGTH 1 none PHASE 0.000 none CLK_DOMAIN none NUM_READ_THREADS 1 none NUM_WRITE_THREADS 1 none RUSER_BITS_PER_BYTE 0 none WUSER_BITS_PER_BYTE 0 none INSERT_VIP 0 simulation.rtl false C0_DDR4_ARESETN true RST c0_ddr4_aresetn POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false C0_DDR4_RESET true RST c0_ddr4_ui_clk_sync_rst POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl true C0_DDR4_CLOCK true CLK c0_ddr4_ui_clk FREQ_HZ 1.665e+08 PHASE 0.00 ASSOCIATED_BUSIF C0_DDR4_S_AXI:C0_DDR4_S_AXI_CTRL ASSOCIATED_RESET c0_ddr4_aresetn:c0_ddr4_ui_clk_sync_rst CLK_DOMAIN none INSERT_VIP 0 simulation.rtl true ADDN_UI_CLKOUT1 true CLK addn_ui_clkout1 FREQ_HZ 0 PHASE 0 ASSOCIATED_ASYNC_RESET c0_aresetn CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ADDN_UI_CLKOUT2 true CLK addn_ui_clkout2 FREQ_HZ 0 PHASE 0 ASSOCIATED_ASYNC_RESET c0_aresetn CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ADDN_UI_CLKOUT3 true CLK addn_ui_clkout3 FREQ_HZ 0 PHASE 0 ASSOCIATED_ASYNC_RESET c0_aresetn CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ADDN_UI_CLKOUT4 true CLK addn_ui_clkout4 FREQ_HZ 0 PHASE 0 ASSOCIATED_ASYNC_RESET c0_aresetn CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false SYSTEM_RESET true RST sys_rst POLARITY ACTIVE_HIGH BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE INSERT_VIP 0 simulation.rtl C0_DDR4_MEMORY_MAP C0_DDR4_ADDRESS_BLOCK 0 34359738368 32 memory read-write false C0_DDR4_MEMORY_MAP_CTRL C0_REG 0 4096 32 register read-write false xilinx_elaborateports Elaborate Ports :vivado.xilinx.com:elaborate.ports outputProductCRC 9:ec1001e4 xilinx_elaboratesubcores Elaborate Sub-Cores :vivado.xilinx.com:elaborate.subcores xilinx_elaboratesubcores_view_fileset outputProductCRC 9:937f737e c0_init_calib_complete out wire xilinx_elaborateports true dbg_clk out wire xilinx_elaborateports true c0_sys_clk_p in wire xilinx_elaborateports 0 true c0_sys_clk_n in wire xilinx_elaborateports 0 true c0_sys_clk_i in wire xilinx_elaborateports 0 false dbg_rd_data_cmp out 63 0 std_logic xilinx_elaborateports 0 false dbg_expected_data out 63 0 std_logic xilinx_elaborateports 0 false dbg_cal_seq out 2 0 std_logic xilinx_elaborateports 0 false dbg_cal_seq_cnt out 31 0 std_logic xilinx_elaborateports 0 false dbg_cal_seq_rd_cnt out 7 0 std_logic xilinx_elaborateports 0 false dbg_rd_valid out wire xilinx_elaborateports false dbg_cmp_byte out 5 0 std_logic xilinx_elaborateports 0 false dbg_rd_data out 63 0 std_logic xilinx_elaborateports 0 false dbg_cplx_config out 15 0 std_logic xilinx_elaborateports 0 false dbg_cplx_status out 1 0 std_logic xilinx_elaborateports 0 false dbg_io_address out 27 0 std_logic xilinx_elaborateports 0 false dbg_pllGate out wire xilinx_elaborateports false dbg_phy2clb_fixdly_rdy_low out 19 0 std_logic xilinx_elaborateports 0 false dbg_phy2clb_fixdly_rdy_upp out 19 0 std_logic xilinx_elaborateports 0 false dbg_phy2clb_phy_rdy_low out 19 0 std_logic xilinx_elaborateports 0 false dbg_phy2clb_phy_rdy_upp out 19 0 std_logic xilinx_elaborateports 0 false cal_r0_status out 127 0 std_logic xilinx_elaborateports 0 false cal_post_status out 8 0 std_logic xilinx_elaborateports 0 false dbg_bus out 511 0 std_logic xilinx_elaborateports 0 true c0_ddr4_ecc_err_addr out 51 0 std_logic xilinx_elaborateports 0 false c0_ddr4_ecc_single out 7 0 std_logic xilinx_elaborateports 0 false c0_ddr4_ecc_multiple out 7 0 std_logic xilinx_elaborateports 0 false c0_ddr4_adr out 16 0 std_logic xilinx_elaborateports false c0_ddr4_ba out 1 0 std_logic xilinx_elaborateports false c0_ddr4_cke out 1 0 std_logic xilinx_elaborateports false c0_ddr4_cs_n out 1 0 std_logic xilinx_elaborateports false c0_ddr4_dm_dbi_n inout 8 0 std_logic xilinx_elaborateports false c0_ddr4_dq inout 71 0 std_logic xilinx_elaborateports false c0_ddr4_dqs_c inout 17 0 std_logic xilinx_elaborateports false c0_ddr4_dqs_t inout 17 0 std_logic xilinx_elaborateports false c0_ddr4_odt out 1 0 std_logic xilinx_elaborateports false c0_ddr4_parity out std_logic xilinx_elaborateports true c0_ddr4_bg out 1 0 std_logic xilinx_elaborateports false c0_ddr4_c out 0 0 std_logic xilinx_elaborateports false c0_ddr4_reset_n out std_logic xilinx_elaborateports false c0_ddr4_act_n out std_logic xilinx_elaborateports false c0_ddr4_ck_c out 0 0 std_logic xilinx_elaborateports false c0_ddr4_ck_t out 0 0 std_logic xilinx_elaborateports false c0_ddr4_ui_clk out std_logic xilinx_elaborateports true c0_ddr4_ui_clk_sync_rst out std_logic xilinx_elaborateports true c0_ddr4_app_en in std_logic xilinx_elaborateports 0 false c0_ddr4_app_hi_pri in std_logic xilinx_elaborateports 0 false c0_ddr4_app_wdf_end in std_logic xilinx_elaborateports 0 false c0_ddr4_app_wdf_wren in std_logic xilinx_elaborateports 0 false c0_ddr4_app_correct_en_i in std_logic xilinx_elaborateports 0 false c0_ddr4_app_rd_data_end out std_logic xilinx_elaborateports false c0_ddr4_app_rd_data_valid out std_logic xilinx_elaborateports false c0_ddr4_app_rdy out std_logic xilinx_elaborateports false c0_ddr4_app_wdf_rdy out std_logic xilinx_elaborateports false c0_ddr4_app_ref_req in std_logic xilinx_elaborateports 0 false c0_ddr4_app_ref_ack out std_logic xilinx_elaborateports false c0_ddr4_app_zq_req in std_logic xilinx_elaborateports 0 false c0_ddr4_app_zq_ack out std_logic xilinx_elaborateports false c0_ddr4_app_autoprecharge in std_logic xilinx_elaborateports 0 false c0_ddr4_app_addr in 31 0 std_logic xilinx_elaborateports 0 false c0_ddr4_app_cmd in 2 0 std_logic xilinx_elaborateports 0 false c0_ddr4_app_wdf_data in 575 0 std_logic xilinx_elaborateports 0 false c0_ddr4_app_wdf_mask in 71 0 std_logic xilinx_elaborateports 0 false c0_ddr4_app_rd_data out 575 0 std_logic xilinx_elaborateports false c0_ddr4_app_sref_req in std_logic xilinx_elaborateports 0 false c0_ddr4_app_sref_ack out std_logic xilinx_elaborateports 0 false c0_ddr4_app_save_req in std_logic xilinx_elaborateports 0 false c0_ddr4_app_save_ack out std_logic xilinx_elaborateports 0 false c0_ddr4_app_restore_en in std_logic xilinx_elaborateports 0 false c0_ddr4_app_restore_complete in std_logic xilinx_elaborateports 0 false c0_ddr4_app_mem_init_skip in std_logic xilinx_elaborateports 0 false c0_ddr4_app_xsdb_select in std_logic xilinx_elaborateports 0 false c0_ddr4_app_xsdb_rd_en in std_logic xilinx_elaborateports 0 false c0_ddr4_app_xsdb_wr_en in std_logic xilinx_elaborateports 0 false c0_ddr4_app_xsdb_addr in 15 0 std_logic xilinx_elaborateports 0 false c0_ddr4_app_xsdb_wr_data in 8 0 std_logic xilinx_elaborateports 0 false c0_ddr4_app_xsdb_rd_data out 8 0 std_logic xilinx_elaborateports 0 false c0_ddr4_app_xsdb_rdy out std_logic xilinx_elaborateports 0 false c0_ddr4_restore_crc_error out std_logic xilinx_elaborateports 0 false c0_ddr4_app_dbg_out out 31 0 std_logic xilinx_elaborateports 0 false c0_ddr4_aresetn in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_awvalid in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_awready out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_awaddr in 31 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_wvalid in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_wready out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_wdata in 31 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_bvalid out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_bready in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_bresp out 1 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_arvalid in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_arready out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_araddr in 31 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_rvalid out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_rready in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_rdata out 31 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_ctrl_rresp out 1 0 std_logic xilinx_elaborateports 0 false c0_ddr4_interrupt out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_awid in 3 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_awaddr in 31 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_awlen in 7 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_awsize in 2 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_awburst in 1 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_awlock in 0 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_awcache in 3 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_awprot in 2 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_awqos in 3 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_awvalid in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_awready out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_wdata in 63 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_wstrb in 7 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_wlast in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_wvalid in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_wready out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_bready in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_bid out 3 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_bresp out 1 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_bvalid out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_arid in 3 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_araddr in 31 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_arlen in 7 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_arsize in 2 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_arburst in 1 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_arlock in 0 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_arcache in 3 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_arprot in 2 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_arqos in 3 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_arvalid in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_arready out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_rready in std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_rlast out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_rvalid out std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_rresp out 1 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_rid out 3 0 std_logic xilinx_elaborateports 0 false c0_ddr4_s_axi_rdata out 63 0 std_logic xilinx_elaborateports 0 false traffic_error in 575 0 std_logic xilinx_elaborateports 0 false traffic_wr_done in std_logic xilinx_elaborateports 0 false traffic_status_err_bit_valid in std_logic xilinx_elaborateports 0 false traffic_status_err_type_valid in std_logic xilinx_elaborateports 0 false traffic_status_err_type in std_logic xilinx_elaborateports 0 false traffic_status_done in std_logic xilinx_elaborateports 0 false traffic_status_watch_dog_hang in std_logic xilinx_elaborateports 0 false win_start in 3 0 std_logic xilinx_elaborateports 0 false traffic_clr_error out wire xilinx_elaborateports false traffic_start out wire xilinx_elaborateports false traffic_rst out wire xilinx_elaborateports false traffic_err_chk_en out wire xilinx_elaborateports false traffic_instr_addr_mode out 3 0 std_logic xilinx_elaborateports 0 false traffic_instr_data_mode out 3 0 std_logic xilinx_elaborateports 0 false traffic_instr_rw_mode out 3 0 std_logic xilinx_elaborateports 0 false traffic_instr_rw_submode out 1 0 std_logic xilinx_elaborateports 0 false traffic_instr_num_of_iter out 31 0 std_logic xilinx_elaborateports 0 false traffic_instr_nxt_instr out 5 0 std_logic xilinx_elaborateports 0 false win_status out 31 0 std_logic xilinx_elaborateports 0 false addn_ui_clkout1 out std_logic xilinx_elaborateports false addn_ui_clkout2 out std_logic xilinx_elaborateports false addn_ui_clkout3 out std_logic xilinx_elaborateports false addn_ui_clkout4 out std_logic xilinx_elaborateports false c0_ddr4_mcs_lmb_ce out std_logic xilinx_elaborateports false c0_ddr4_mcs_lmb_ue out std_logic xilinx_elaborateports false sys_rst in wire xilinx_elaborateports rdDataEn out 0 0 std_logic_vector xilinx_elaborateports rdDataEnd out 0 0 std_logic_vector xilinx_elaborateports per_rd_done out 0 0 std_logic_vector xilinx_elaborateports rmw_rd_done out 0 0 std_logic_vector xilinx_elaborateports wrDataEn out 0 0 std_logic_vector xilinx_elaborateports mc_ACT_n in 7 0 std_logic_vector xilinx_elaborateports mcCasSlot in 1 0 std_logic_vector xilinx_elaborateports mcCasSlot2 in 0 0 std_logic_vector xilinx_elaborateports mcRdCAS in 0 0 std_logic_vector xilinx_elaborateports mcWrCAS in 0 0 std_logic_vector xilinx_elaborateports winInjTxn in 0 0 std_logic_vector xilinx_elaborateports winRmw in 0 0 std_logic_vector xilinx_elaborateports gt_data_ready in std_logic xilinx_elaborateports winRank in 1 0 std_logic_vector xilinx_elaborateports tCWL out 5 0 std_logic_vector xilinx_elaborateports wrData in 575 0 std_logic_vector xilinx_elaborateports rdData out 575 0 std_logic_vector xilinx_elaborateports mc_ADR in 135 0 std_logic_vector xilinx_elaborateports mc_BA in 15 0 std_logic_vector xilinx_elaborateports mc_CKE in 15 0 std_logic_vector xilinx_elaborateports mc_CS_n in 15 0 std_logic_vector xilinx_elaborateports mc_ODT in 15 0 std_logic_vector xilinx_elaborateports dBufAdr in 4 0 std_logic_vector xilinx_elaborateports rdDataAddr out 4 0 std_logic_vector xilinx_elaborateports wrDataAddr out 4 0 std_logic_vector xilinx_elaborateports winBuf in 4 0 std_logic_vector xilinx_elaborateports ddr4_act_n out std_logic xilinx_elaborateports ddr4_adr out 16 0 std_logic_vector xilinx_elaborateports ddr4_ba out 1 0 std_logic_vector xilinx_elaborateports ddr4_bg out 1 0 std_logic_vector xilinx_elaborateports ddr4_par out std_logic xilinx_elaborateports ddr4_cke out 1 0 std_logic_vector xilinx_elaborateports ddr4_odt out 1 0 std_logic_vector xilinx_elaborateports ddr4_cs_n out 1 0 std_logic_vector xilinx_elaborateports ddr4_ck_t out std_logic xilinx_elaborateports ddr4_ck_c out std_logic xilinx_elaborateports ddr4_reset_n out std_logic xilinx_elaborateports ddr4_parity out std_logic xilinx_elaborateports ddr4_dq inout 71 0 std_logic_vector xilinx_elaborateports ddr4_dqs_c inout 17 0 std_logic_vector xilinx_elaborateports ddr4_dqs_t inout 17 0 std_logic_vector xilinx_elaborateports mc_BG in 15 0 std_logic_vector xilinx_elaborateports C0.ControllerType ControllerType DDR4_SDRAM C0.APP_ADDR_WIDTH App Address Width 32 C0.MEM_TYPE MEM TYPE DDR4 C0.BUFG_LOC_1 BUFG LOC1 X0Y46 C0.BUFG_LOC_2 BUFG LOC1 X0Y7 C0.BUFG_DIV_LOC_1 BUFG DIV LOC1 X0Y7 C0.BUFG_DIV_LOC_2 BUFG DIV LOC2 X0Y6 C0.PBLOCK_SLICE_LOC PBLOCK SLICE LOC 0 C0.PBLOCK_RAMB36_LOC PBLOCK RAMB36 LOC 0 C0.PBLOCK_RAMB18_LOC PBLOCK RAMB18 LOC 0 C0.PBLOCK_SLICE_LOC_SC PBLOCK SLICE LOC SC 0 C0.PBLOCK_RAMB36_LOC_SC PBLOCK RAMB36 LOC SC 0 C0.PBLOCK_RAMB18_LOC_SC PBLOCK RAMB18 LOC SC 0 C0.MMCM_IDX_BANK MMCM IDX BANK 1 C0.CENTER_BANK_CLOCK_REGION CENTER BANK CLOCK REGION 0 C0.CENTER_BANK_MMCME3_ADV_SITE CENTER BANK MMCME3 ADV SITE 0 C0.SYSCLK_CENTER_INFO SYSCLK CENTER INFO FALSE PING_PONG_PHY Ping Pong Phy 1 C0.DDR4_CS_ADDR CS Width Check 32 C0.DDR4_VrefVoltage Vref Voltage 0.84 C0.DDR4_AL Additive Latency 0 C0.DDR4_DQ_WIDTH DQ WIDTH 72 C0.DDR4_nCK_PER_CLK nCK PER CLK 4 C0.DDR4_DM_WIDTH DM WIDTH 9 C0.DDR4_DQS_WIDTH DQS WIDTH 18 C0.DDR4_nCS_PER_RANK nCS PER RANK 2 C0.DDR4_MEM_DEVICE_WIDTH MEM DEVICE WIDTH 72 C0.DDR4_USE_DM_PORT USE DM PORT 0 C0.DDR4_USE_CS_PORT USE CS PORT 1 C0.DDR4_ROW_WIDTH ROW WIDTH 17 C0.DDR4_ADDR_WIDTH ADDR WIDTH 17 C0.DDR4_BANK_WIDTH BANK WIDTH 2 C0.DDR4_BANK_GROUP_WIDTH BANK GROUP WIDTH 2 LR_WIDTH LR WIDTH 1 C0.DDR4_CK_WIDTH CK WIDTH 1 C0.DDR4_CKE_WIDTH CKE WIDTH 2 C0.DDR4_CS_WIDTH CS WIDTH 2 C0.DDR4_ODT_WIDTH ODT WIDTH 2 C0.DDR4_MEMORY_TYPE MEMORY TYPE RDIMMs C0.DDR4_MEMORY_PART MEMORY PART MTA36ASF4G72PZ-2G3 C0.DDR4_DATA_MASK DATA MASK 18 C0.DDR4_COLUMN_WIDTH COLUMN WIDTH 10 C0.DDR4_SPEED_GRADE SPEED GRADE 083 C0.DDR4_MEM_DENSITY MEM DENSITY 32GB C0.DDR4_MEM_DENSITY_MB MEM DENSITY MB 8192 C0.DDR4_MEM_DENSITY_GB MEM DENSITY GB 8 C0.DDR4_COMP_DENSITY COMP DENSITY 8Gb C0.DDR4_MEM_COMP_WIDTH MEM COMP WIDTH 4 C0.DDR4_DATABITS_PER_STROBE DATABITS PER STROBE 4 C0.DDR4_MODEL_SPEED_GRADE MODEL SPEED GRADE DDR4_833_Timing C0.DDR4_RANK_WIDTH RANK WIDTH 2 C0.DDR4_IO_VOLTAGE IO VOLTAGE 1.2V C0.DDR4_MIN_PERIOD MIN PERIOD 833 C0.DDR4_MAX_PERIOD MAX PERIOD 1600 C0.DDR4_MR0 Mode register_0 value 0 C0.DDR4_MR2 Mode register_2 value 0 C0.DDR4_nAL Additive Latency in number of clock 0 C0.DDR4_BURST_MODE Burst Mode 0 C0.DDR4_BURST_TYPE Burst Type 0 C0.DDR4_CL Cas Latency 0 C0.DDR4_CWL Cas Write Latency 0 C0.DDR4_OUTPUT_DRV Output drive Strength 0 C0.DDR4_RTT_NOM RTT Nominal 0 C0.DDR4_RTT_WR RTT WR 0 C0.DDR4_MEM Memory Name 0 C0.DDR4_DBAW DBAW 0 C0.DDR4_tCK tCK 1500 C0.DDR4_Configuration Configuration 0 C0.DDR4_tCKE tCKE 0 C0.DDR4_tFAW tFAW 9 C0.DDR4_tFAW_dlr tFAW_dlr 16 C0.DDR4_tMRD tMRD 2 C0.DDR4_tRAS tRAS 22 C0.DDR4_tRCD tRCD 10 C0.DDR4_tREFI tREFI 5200 C0.DDR4_tRFC tRFC 234 C0.DDR4_tRFC_dlr tRFC_dlr 80 C0.DDR4_tRP tRP 10 C0.DDR4_tWR tWR 10 C0.DDR4_tRRD tRRD C0.DDR4_tRTP tRTP 5 C0.DDR4_tRRD_S tRRD_S 3 C0.DDR4_tRRD_L tRRD_L 4 C0.DDR4_tRRD_dlr tRRD_dlr 4 C0.DDR4_tWTR tWTR C0.DDR4_tWTR_S tWTR_S 2 C0.DDR4_tWTR_L tWTR_L 5 C0.DDR4_tXPR tXPR 60 C0.DDR4_tZQI tZQI 0 C0.DDR4_tZQCS tZQCS 128 C0.DDR4_tZQINIT tZQINIT 256 C0.DDR4_tCCD_3ds tCCD_3ds 5 C0.DDR4_CLKOUTPHY_MODE CLKOUTPHY_MODE VCO C0.DDR4_CLKOUT0_DIVIDE CLKOUT0_DIVIDE 9 C0.DDR4_CLKOUT1_DIVIDE CLKOUT1_DIVIDE 0 C0.DDR4_CLKFBOUT_MULT CLKFBOUT_MULT 15 C0.DDR4_DIVCLK_DIVIDE DIVCLK DIVIDE 1 CAL_INPUT_CLK_PERIOD Calculated Input Clock Period 10000 C0.DDR4_CLKIN_PERIOD CLKIN_PERIOD 10000 C0.DDR4_HR_MIN_FREQ High Range Supported frequency 0 C0.DDR4_DCI_CASCADE_CUTOFF DCI Cascade Cutoff 938 C0.DDR4_IS_FASTER_SPEED_RAM Is Faster Speed RAM No C0.DDR4_AXI_ID_WIDTH AXI ID Width 4 C0.DDR4_AXI_ADDR_WIDTH AXI Address Width 32 C0.DDR4_AXI_DATA_WIDTH AXI Data Width 64 C0.DDR4_MEM_SIZE Memory Size 34359738368 C0.DDR4_UI_CLOCK DDR4 UI CLOCK 166500000 C0.DDR4_CA_MIRROR CA MIRROR 1 C0.DDR4_IS_CUSTOM IS CUSTOM false C0.DDR4_AUTO_AP_COL_A3 AUTO AP COL A3 false C0.DDR4_MCS_ECC MCS ECC 0 C0.DDR4_Slot Slot Type 1 C0.APP_DATA_WIDTH APP Data Width 576 C0.APP_MASK_WIDTH APP Mask Width 72 C0.DDR4_StackHeight 1 CUSTOM_PART_ATTRIBUTES custom_part_attributes NONE M_ADDN_UI_CLKOUT1_FREQ_HZ CLKOUT1 FREQ HZ 0.0 M_ADDN_UI_CLKOUT2_FREQ_HZ CLKOUT2 FREQ HZ 0.0 M_ADDN_UI_CLKOUT3_FREQ_HZ CLKOUT3 FREQ HZ 0.0 M_ADDN_UI_CLKOUT4_FREQ_HZ CLKOUT4 FREQ HZ 0.0 M_ADDN_UI_CLKOUT1_PHASE CLKOUT1 PHASE 0 M_ADDN_UI_CLKOUT2_PHASE CLKOUT2 PHASE 0 M_ADDN_UI_CLKOUT3_PHASE CLKOUT3 PHASE 0 M_ADDN_UI_CLKOUT4_PHASE CLKOUT4 PHASE 0 CLKOUT0_DIVIDE CLKOUT0 DIVIDE 0 CLKOUT1_DIVIDE CLKOUT1 DIVIDE 0 CLKOUT2_DIVIDE CLKOUT2 DIVIDE 0 CLKOUT3_DIVIDE CLKOUT3 DIVIDE 0 CLKOUT4_DIVIDE CLKOUT4 DIVIDE 0 CLKOUT6_DIVIDE CLKOUT6 DIVIDE 0 Debug_Signal Disable Simulation_Mode Simulation Mode BFM choice_list_09ec3310 Single Dual choice_list_157065e4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 choice_list_266493f0 DDR4_SDRAM choice_list_28391b73 1.2V choice_list_2b96b8de Differential No_Buffer choice_list_301b19dd ON OFF choice_list_30636008 4:1 choice_list_34c5244e Components UDIMMs SODIMMs RDIMMs LRDIMMs choice_list_4665eb01 0 1 2 3 4 5 6 7 choice_list_4e3dbc0a SIMPLE_TG ADVANCED_TG choice_list_6330c9d2 10 choice_list_67b045e5 BFM Unisim choice_list_687ca1a5 None 500 375 300 250 214 188 167 150 136 125 115 107 100 94 88 83 79 75 71 68 65 63 60 58 56 54 52 50 48 47 45 44 43 42 41 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 choice_list_7240037c MTA18ASF1G72PDZ-2G1 MTA9ASF51272PZ-2G1 MTA18ASF2G72PDZ-2G3 MTA9ASF1G72PZ-2G3 M393A1G43DB1-CRC MTA9ASF51272PZ-2G3 MTA18ADF1G72PZ-2G1 MTA18ASF1G72PZ-2G1 MTA36ASF2G72PZ-2G1 MTA18ASF2G72PZ-2G9 MTA18ASF2G72PZ-2G3 MTA36ASF4G72PZ-2G3 M393A2G40DB1-CRC M393A8K40B21-CTC M393AAK40B41-CTC M393A2K40BB1-CRC choice_list_8b4f223f Strict Normal choice_list_98f5c8fa RZQ/6 choice_list_a187d5e4 512 1024 choice_list_ac75ef1e Custom choice_list_ad101c66 RZQ/7 RZQ/6 choice_list_ae57517c 9 choice_list_c89503c8 ROW_BANK_COLUMN BANK_ROW_COLUMN ROW_COLUMN_BANK ROW_COLUMN_BANK_INTLV choice_list_c8951bc1 NONE choice_list_d6556846 32 64 128 256 512 choice_list_d8920bdd 8 choice_list_df7e3f8b Sequential Interleaved choice_list_e7093afb 25 26 27 28 29 30 31 32 33 34 35 36 choice_list_ed30197c TDM ROUND_ROBIN RD_PRI_REG RD_PRI_REG_STARVE_LIMIT WRITE_PRIORITY_REG WRITE_PRIORITY choice_list_ef319ec8 Differential Single_Ended No_Buffer choice_list_f3cd92fb Disable Enable choice_list_fe2d3253 72 choice_list_ff0950bb 0 CL-1 CL-2 choice_pairs_01257c99 Complete_Memory_Controller Phy_Only_Single Phy_Only_PingPong choice_pairs_05415bea 14000 13999 13200 13199 12000 11999 10801 10800 10500 10499 10000 9601 9600 9599 9000 8999 8572 8571 8400 8399 8000 7715 7714 7501 7500 7499 7201 7200 7000 6999 6858 6857 6500 6499 6000 5999 5573 5572 5571 5401 5400 5335 5334 5333 5000 4876 4875 4801 4800 4715 4714 4667 4666 4573 4572 4571 4500 4499 4446 4445 4444 4401 4400 4286 4285 4223 4222 4126 4125 4124 4000 3858 3857 3779 3778 3777 3715 3714 3601 3600 3563 3562 3557 3556 3555 3500 3499 3429 3428 3335 3334 3333 3250 3249 3188 3187 3112 3111 3000 2999 2889 2888 2801 2800 2787 2786 2785 2751 2750 2701 2700 2668 2667 2666 2641 2640 2639 2625 2624 2572 2571 2500 2445 2444 2438 2437 2401 2400 2399 2334 2333 2287 2286 2250 2249 2223 2222 2201 2200 2161 2160 2143 2142 2112 2111 2100 2099 2063 2062 2000 1960 1959 1921 1920 1919 1890 1889 1888 1886 1885 1858 1857 1801 1800 1799 1782 1781 1779 1778 1777 1750 1749 1715 1714 1680 1679 1668 1667 1666 1625 1624 1600 1594 1593 1592 1591 1556 1555 1544 1543 xilinx_elaboratesubcores_view_fileset ip_0/phy_ddr4_microblaze_mcs.xci xci ip_0/phy_ddr4_microblaze_mcs.xml xml ip_1/phy_ddr4_phy.xci xci ip_1/phy_ddr4_phy.xml xml phy_ddr4 instance_path inst/u_ddr_cal_riu/mcs0/inst/microblaze_I bootloop_file sw/calibration_0/Debug/calibration_ddr.elf endian little processor_type MICROBLAZE-LE is_visible false DDR4 Interface Generator for Ultrascale Architecture C0.ControllerType DDR4_SDRAM false IOPowerReduction OFF Enable_SysPorts Auto assign static ports true Phy_Only Phy_Only_Single RESET_BOARD_INTERFACE Custom true C0_CLOCK_BOARD_INTERFACE Custom true IS_FROM_PHY 1 RECONFIG_XSDB_SAVE_RESTORE false AL_SEL 0 Example_TG SIMPLE_TG false C0.DDR4_Clamshell false false C0.MIGRATION false TIMING_OP1 false TIMING_OP2 false TIMING_3DS false SET_DW_TO_40 false DIFF_TERM_SYSCLK false C0_DDR4_BOARD_INTERFACE Custom true C0.DDR4_TimePeriod 1500 C0.DDR4_InputClockPeriod 10000 C0.DDR4_Specify_MandD false C0.DDR4_CLKFBOUT_MULT 15 false C0.DDR4_DIVCLK_DIVIDE 1 false C0.DDR4_CLKOUT0_DIVIDE 9 false C0.DDR4_PhyClockRatio 4:1 C0.DDR4_MemoryType RDIMMs C0.DDR4_MemoryPart MTA36ASF4G72PZ-2G3 C0.DDR4_Slot Single C0.DDR4_MemoryVoltage 1.2V C0.DDR4_DataWidth 72 C0.DDR4_DataMask NONE false C0.DDR4_Ecc false false C0.DDR4_MCS_ECC false C0.DDR4_AxiSelection false false C0.DDR4_AUTO_AP_COL_A3 false C0.DDR4_Ordering Normal C0.DDR4_BurstLength 8 false C0.DDR4_BurstType Sequential C0.DDR4_OutputDriverImpedenceControl RZQ/7 C0.DDR4_OnDieTermination RZQ/6 C0.DDR4_CasLatency 10 C0.DDR4_CasWriteLatency 9 C0.DDR4_ChipSelect true false C0.DDR4_isCKEShared false C0.DDR4_AxiDataWidth 64 C0.DDR4_AxiArbitrationScheme RD_PRI_REG C0.DDR4_AxiNarrowBurst false C0.DDR4_AxiAddressWidth 32 C0.DDR4_AxiIDWidth 4 C0.DDR4_Capacity 512 C0.DDR4_Mem_Add_Map ROW_COLUMN_BANK C0.DDR4_MemoryName MainMemory C0.DDR4_AutoPrecharge false false C0.DDR4_UserRefresh_ZQCS false false C0.DDR4_CustomParts no_file_loaded file_csv false C0.DDR4_isCustom false C0.DDR4_SELF_REFRESH false false C0.DDR4_SAVE_RESTORE false C0.DDR4_RESTORE_CRC false false ADDN_UI_CLKOUT1_FREQ_HZ None ADDN_UI_CLKOUT2_FREQ_HZ None ADDN_UI_CLKOUT3_FREQ_HZ None ADDN_UI_CLKOUT4_FREQ_HZ None CLKOUT6 false Component_Name phy_ddr4 No_Controller 1 System_Clock Differential Reference_Clock Differential Debug_Signal Disable IO_Power_Reduction IO_Power_Reduction false DCI_Cascade DCI Cascade false Default_Bank_Selections Default Bank Selections false Simulation_Mode BFM PARTIAL_RECONFIG_FLOW_MIG false false MCS_DBG_EN false C0.DDR4_CK_SKEW_0 0 C0.DDR4_CK_SKEW_1 0 C0.DDR4_CK_SKEW_2 0 C0.DDR4_CK_SKEW_3 0 C0.DDR4_ADDR_SKEW_0 0 C0.DDR4_ADDR_SKEW_1 0 C0.DDR4_ADDR_SKEW_2 0 C0.DDR4_ADDR_SKEW_3 0 C0.DDR4_ADDR_SKEW_4 0 C0.DDR4_ADDR_SKEW_5 0 C0.DDR4_ADDR_SKEW_6 0 C0.DDR4_ADDR_SKEW_7 0 C0.DDR4_ADDR_SKEW_8 0 C0.DDR4_ADDR_SKEW_9 0 C0.DDR4_ADDR_SKEW_10 0 C0.DDR4_ADDR_SKEW_11 0 C0.DDR4_ADDR_SKEW_12 0 C0.DDR4_ADDR_SKEW_13 0 C0.DDR4_ADDR_SKEW_14 0 C0.DDR4_ADDR_SKEW_15 0 C0.DDR4_ADDR_SKEW_16 0 C0.DDR4_ADDR_SKEW_17 0 C0.DDR4_BA_SKEW_0 0 C0.DDR4_BA_SKEW_1 0 C0.DDR4_BG_SKEW_0 0 C0.DDR4_BG_SKEW_1 0 C0.DDR4_CS_SKEW_0 0 C0.DDR4_CS_SKEW_1 0 C0.DDR4_CS_SKEW_2 0 C0.DDR4_CS_SKEW_3 0 C0.DDR4_CKE_SKEW_0 0 C0.DDR4_CKE_SKEW_1 0 C0.DDR4_CKE_SKEW_2 0 C0.DDR4_CKE_SKEW_3 0 C0.DDR4_ACT_SKEW 0 C0.DDR4_PAR_SKEW 0 C0.DDR4_ODT_SKEW_0 0 C0.DDR4_ODT_SKEW_1 0 C0.DDR4_ODT_SKEW_2 0 C0.DDR4_ODT_SKEW_3 0 C0.DDR4_LR_SKEW_0 0 C0.DDR4_LR_SKEW_1 0 C0.DDR4_TREFI 0 C0.DDR4_TRFC 0 C0.DDR4_TRFC_DLR 0 C0.DDR4_TXPR 0 C0.DDR4_nCK_TREFI 0 C0.DDR4_nCK_TRFC 0 C0.DDR4_nCK_TRFC_DLR 0 C0.DDR4_nCK_TXPR 5 C0.ADDR_WIDTH ADDR WIDTH 17 C0.BANK_GROUP_WIDTH BANK GROUP WIDTH 2 C0.LR_WIDTH LR WIDTH 1 C0.CK_WIDTH CK WIDTH 1 C0.CKE_WIDTH CKE WIDTH 2 C0.CS_WIDTH CS WIDTH 2 C0.ODT_WIDTH ODT WIDTH 2 C0.StackHeight 1 PING_PONG_PHY Ping Pong Phy 1 C0.DDR4_Enable_LVAUX false DDR4 SDRAM (MIG) 8 2019.2