| Age | Commit message (Collapse) | Author | Lines | 
|---|
|  |  | 
|  | Added capacitors for subschematics. | 
|  | Added test points everywhere neccessary.
Added missing pull resistors to guarantee a defined state everywhere. | 
|  | Added connectors for UART access. | 
|  | Added pull resistors to every pin of uC.
Restructured main schematic.
Added ISP interface. | 
|  | Added capacitor in parallel to reset switch to reduce sensitivity and
oscillations. | 
|  | Added pull resistors to all ports.
Added capacitors for all components to prevent high switching currents.
Reordered status LEDs and transistors. | 
|  | Separated logic IO from power with transistors. | 
|  | Added JTAG interface. | 
|  |  | 
|  |  | 
|  | Moved buttons and status interface to Port D to prepare Port C as JTAG
interface. | 
|  |  | 
|  |  | 
|  | Minor layout fix. | 
|  | Implemented hierarchy.
Added button interface.
Added status interface. | 
|  | Added Power wirings and connectors.
Added 7-segment display output components and wiring to schematic.
Added shift registers for button inputs. | 
|  |  |